1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * SPDX-License-Identifier: BSD-4-Clause AND BSD-3-Clause 50 * 51 * Copyright (c) 1997, 1998, 1999, 2000 52 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 53 * 54 * Redistribution and use in source and binary forms, with or without 55 * modification, are permitted provided that the following conditions 56 * are met: 57 * 1. Redistributions of source code must retain the above copyright 58 * notice, this list of conditions and the following disclaimer. 59 * 2. Redistributions in binary form must reproduce the above copyright 60 * notice, this list of conditions and the following disclaimer in the 61 * documentation and/or other materials provided with the distribution. 62 * 3. All advertising materials mentioning features or use of this software 63 * must display the following acknowledgement: 64 * This product includes software developed by Bill Paul. 65 * 4. Neither the name of the author nor the names of any co-contributors 66 * may be used to endorse or promote products derived from this software 67 * without specific prior written permission. 68 * 69 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 70 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 71 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 72 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 73 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 74 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 75 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 76 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 77 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 78 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 79 * THE POSSIBILITY OF SUCH DAMAGE. 80 */ 81 /*- 82 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 83 * 84 * Permission to use, copy, modify, and distribute this software for any 85 * purpose with or without fee is hereby granted, provided that the above 86 * copyright notice and this permission notice appear in all copies. 87 * 88 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 89 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 90 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 91 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 92 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 93 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 94 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 95 */ 96 97 /* 98 * Device driver for the Marvell Yukon II Ethernet controller. 99 * Due to lack of documentation, this driver is based on the code from 100 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 101 */ 102 103 #include <sys/cdefs.h> 104 __FBSDID("$FreeBSD$"); 105 106 #include <sys/param.h> 107 #include <sys/systm.h> 108 #include <sys/bus.h> 109 #include <sys/endian.h> 110 #include <sys/mbuf.h> 111 #include <sys/malloc.h> 112 #include <sys/kernel.h> 113 #include <sys/module.h> 114 #include <sys/socket.h> 115 #include <sys/sockio.h> 116 #include <sys/queue.h> 117 #include <sys/sysctl.h> 118 119 #include <net/bpf.h> 120 #include <net/ethernet.h> 121 #include <net/if.h> 122 #include <net/if_var.h> 123 #include <net/if_arp.h> 124 #include <net/if_dl.h> 125 #include <net/if_media.h> 126 #include <net/if_types.h> 127 #include <net/if_vlan_var.h> 128 129 #include <netinet/in.h> 130 #include <netinet/in_systm.h> 131 #include <netinet/ip.h> 132 #include <netinet/tcp.h> 133 #include <netinet/udp.h> 134 135 #include <machine/bus.h> 136 #include <machine/in_cksum.h> 137 #include <machine/resource.h> 138 #include <sys/rman.h> 139 140 #include <dev/mii/mii.h> 141 #include <dev/mii/miivar.h> 142 143 #include <dev/pci/pcireg.h> 144 #include <dev/pci/pcivar.h> 145 146 #include <dev/msk/if_mskreg.h> 147 148 MODULE_DEPEND(msk, pci, 1, 1, 1); 149 MODULE_DEPEND(msk, ether, 1, 1, 1); 150 MODULE_DEPEND(msk, miibus, 1, 1, 1); 151 152 /* "device miibus" required. See GENERIC if you get errors here. */ 153 #include "miibus_if.h" 154 155 /* Tunables. */ 156 static int msi_disable = 0; 157 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 158 static int legacy_intr = 0; 159 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 160 static int jumbo_disable = 0; 161 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable); 162 163 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 164 165 /* 166 * Devices supported by this driver. 167 */ 168 static const struct msk_product { 169 uint16_t msk_vendorid; 170 uint16_t msk_deviceid; 171 const char *msk_name; 172 } msk_products[] = { 173 { VENDORID_SK, DEVICEID_SK_YUKON2, 174 "SK-9Sxx Gigabit Ethernet" }, 175 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 176 "SK-9Exx Gigabit Ethernet"}, 177 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 178 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 179 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 180 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 181 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 182 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 183 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 184 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 185 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 186 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 187 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 188 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 189 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 190 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 191 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 192 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 193 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 194 "Marvell Yukon 88E8035 Fast Ethernet" }, 195 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 196 "Marvell Yukon 88E8036 Fast Ethernet" }, 197 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 198 "Marvell Yukon 88E8038 Fast Ethernet" }, 199 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 200 "Marvell Yukon 88E8039 Fast Ethernet" }, 201 { VENDORID_MARVELL, DEVICEID_MRVL_8040, 202 "Marvell Yukon 88E8040 Fast Ethernet" }, 203 { VENDORID_MARVELL, DEVICEID_MRVL_8040T, 204 "Marvell Yukon 88E8040T Fast Ethernet" }, 205 { VENDORID_MARVELL, DEVICEID_MRVL_8042, 206 "Marvell Yukon 88E8042 Fast Ethernet" }, 207 { VENDORID_MARVELL, DEVICEID_MRVL_8048, 208 "Marvell Yukon 88E8048 Fast Ethernet" }, 209 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 210 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 211 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 212 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 213 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 214 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 215 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 216 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 217 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 218 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 219 { VENDORID_MARVELL, DEVICEID_MRVL_4365, 220 "Marvell Yukon 88E8070 Gigabit Ethernet" }, 221 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 222 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 223 { VENDORID_MARVELL, DEVICEID_MRVL_436B, 224 "Marvell Yukon 88E8071 Gigabit Ethernet" }, 225 { VENDORID_MARVELL, DEVICEID_MRVL_436C, 226 "Marvell Yukon 88E8072 Gigabit Ethernet" }, 227 { VENDORID_MARVELL, DEVICEID_MRVL_436D, 228 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 229 { VENDORID_MARVELL, DEVICEID_MRVL_4370, 230 "Marvell Yukon 88E8075 Gigabit Ethernet" }, 231 { VENDORID_MARVELL, DEVICEID_MRVL_4380, 232 "Marvell Yukon 88E8057 Gigabit Ethernet" }, 233 { VENDORID_MARVELL, DEVICEID_MRVL_4381, 234 "Marvell Yukon 88E8059 Gigabit Ethernet" }, 235 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 236 "D-Link 550SX Gigabit Ethernet" }, 237 { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX, 238 "D-Link 560SX Gigabit Ethernet" }, 239 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 240 "D-Link 560T Gigabit Ethernet" } 241 }; 242 243 static const char *model_name[] = { 244 "Yukon XL", 245 "Yukon EC Ultra", 246 "Yukon EX", 247 "Yukon EC", 248 "Yukon FE", 249 "Yukon FE+", 250 "Yukon Supreme", 251 "Yukon Ultra 2", 252 "Yukon Unknown", 253 "Yukon Optima", 254 }; 255 256 static int mskc_probe(device_t); 257 static int mskc_attach(device_t); 258 static int mskc_detach(device_t); 259 static int mskc_shutdown(device_t); 260 static int mskc_setup_rambuffer(struct msk_softc *); 261 static int mskc_suspend(device_t); 262 static int mskc_resume(device_t); 263 static bus_dma_tag_t mskc_get_dma_tag(device_t, device_t); 264 static void mskc_reset(struct msk_softc *); 265 266 static int msk_probe(device_t); 267 static int msk_attach(device_t); 268 static int msk_detach(device_t); 269 270 static void msk_tick(void *); 271 static void msk_intr(void *); 272 static void msk_intr_phy(struct msk_if_softc *); 273 static void msk_intr_gmac(struct msk_if_softc *); 274 static __inline void msk_rxput(struct msk_if_softc *); 275 static int msk_handle_events(struct msk_softc *); 276 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 277 static void msk_intr_hwerr(struct msk_softc *); 278 #ifndef __NO_STRICT_ALIGNMENT 279 static __inline void msk_fixup_rx(struct mbuf *); 280 #endif 281 static __inline void msk_rxcsum(struct msk_if_softc *, uint32_t, struct mbuf *); 282 static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 283 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 284 static void msk_txeof(struct msk_if_softc *, int); 285 static int msk_encap(struct msk_if_softc *, struct mbuf **); 286 static void msk_start(struct ifnet *); 287 static void msk_start_locked(struct ifnet *); 288 static int msk_ioctl(struct ifnet *, u_long, caddr_t); 289 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 290 static void msk_set_rambuffer(struct msk_if_softc *); 291 static void msk_set_tx_stfwd(struct msk_if_softc *); 292 static void msk_init(void *); 293 static void msk_init_locked(struct msk_if_softc *); 294 static void msk_stop(struct msk_if_softc *); 295 static void msk_watchdog(struct msk_if_softc *); 296 static int msk_mediachange(struct ifnet *); 297 static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 298 static void msk_phy_power(struct msk_softc *, int); 299 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 300 static int msk_status_dma_alloc(struct msk_softc *); 301 static void msk_status_dma_free(struct msk_softc *); 302 static int msk_txrx_dma_alloc(struct msk_if_softc *); 303 static int msk_rx_dma_jalloc(struct msk_if_softc *); 304 static void msk_txrx_dma_free(struct msk_if_softc *); 305 static void msk_rx_dma_jfree(struct msk_if_softc *); 306 static int msk_rx_fill(struct msk_if_softc *, int); 307 static int msk_init_rx_ring(struct msk_if_softc *); 308 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 309 static void msk_init_tx_ring(struct msk_if_softc *); 310 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 311 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 312 static int msk_newbuf(struct msk_if_softc *, int); 313 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 314 315 static int msk_phy_readreg(struct msk_if_softc *, int, int); 316 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 317 static int msk_miibus_readreg(device_t, int, int); 318 static int msk_miibus_writereg(device_t, int, int, int); 319 static void msk_miibus_statchg(device_t); 320 321 static void msk_rxfilter(struct msk_if_softc *); 322 static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 323 324 static void msk_stats_clear(struct msk_if_softc *); 325 static void msk_stats_update(struct msk_if_softc *); 326 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS); 327 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS); 328 static void msk_sysctl_node(struct msk_if_softc *); 329 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 330 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 331 332 static device_method_t mskc_methods[] = { 333 /* Device interface */ 334 DEVMETHOD(device_probe, mskc_probe), 335 DEVMETHOD(device_attach, mskc_attach), 336 DEVMETHOD(device_detach, mskc_detach), 337 DEVMETHOD(device_suspend, mskc_suspend), 338 DEVMETHOD(device_resume, mskc_resume), 339 DEVMETHOD(device_shutdown, mskc_shutdown), 340 341 DEVMETHOD(bus_get_dma_tag, mskc_get_dma_tag), 342 343 DEVMETHOD_END 344 }; 345 346 static driver_t mskc_driver = { 347 "mskc", 348 mskc_methods, 349 sizeof(struct msk_softc) 350 }; 351 352 static devclass_t mskc_devclass; 353 354 static device_method_t msk_methods[] = { 355 /* Device interface */ 356 DEVMETHOD(device_probe, msk_probe), 357 DEVMETHOD(device_attach, msk_attach), 358 DEVMETHOD(device_detach, msk_detach), 359 DEVMETHOD(device_shutdown, bus_generic_shutdown), 360 361 /* MII interface */ 362 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 363 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 364 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 365 366 DEVMETHOD_END 367 }; 368 369 static driver_t msk_driver = { 370 "msk", 371 msk_methods, 372 sizeof(struct msk_if_softc) 373 }; 374 375 static devclass_t msk_devclass; 376 377 DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, NULL, NULL); 378 DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, NULL, NULL); 379 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, NULL, NULL); 380 381 static struct resource_spec msk_res_spec_io[] = { 382 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 383 { -1, 0, 0 } 384 }; 385 386 static struct resource_spec msk_res_spec_mem[] = { 387 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 388 { -1, 0, 0 } 389 }; 390 391 static struct resource_spec msk_irq_spec_legacy[] = { 392 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 393 { -1, 0, 0 } 394 }; 395 396 static struct resource_spec msk_irq_spec_msi[] = { 397 { SYS_RES_IRQ, 1, RF_ACTIVE }, 398 { -1, 0, 0 } 399 }; 400 401 static int 402 msk_miibus_readreg(device_t dev, int phy, int reg) 403 { 404 struct msk_if_softc *sc_if; 405 406 sc_if = device_get_softc(dev); 407 408 return (msk_phy_readreg(sc_if, phy, reg)); 409 } 410 411 static int 412 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 413 { 414 struct msk_softc *sc; 415 int i, val; 416 417 sc = sc_if->msk_softc; 418 419 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 420 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 421 422 for (i = 0; i < MSK_TIMEOUT; i++) { 423 DELAY(1); 424 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 425 if ((val & GM_SMI_CT_RD_VAL) != 0) { 426 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 427 break; 428 } 429 } 430 431 if (i == MSK_TIMEOUT) { 432 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 433 val = 0; 434 } 435 436 return (val); 437 } 438 439 static int 440 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 441 { 442 struct msk_if_softc *sc_if; 443 444 sc_if = device_get_softc(dev); 445 446 return (msk_phy_writereg(sc_if, phy, reg, val)); 447 } 448 449 static int 450 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 451 { 452 struct msk_softc *sc; 453 int i; 454 455 sc = sc_if->msk_softc; 456 457 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 458 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 459 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 460 for (i = 0; i < MSK_TIMEOUT; i++) { 461 DELAY(1); 462 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 463 GM_SMI_CT_BUSY) == 0) 464 break; 465 } 466 if (i == MSK_TIMEOUT) 467 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 468 469 return (0); 470 } 471 472 static void 473 msk_miibus_statchg(device_t dev) 474 { 475 struct msk_softc *sc; 476 struct msk_if_softc *sc_if; 477 struct mii_data *mii; 478 struct ifnet *ifp; 479 uint32_t gmac; 480 481 sc_if = device_get_softc(dev); 482 sc = sc_if->msk_softc; 483 484 MSK_IF_LOCK_ASSERT(sc_if); 485 486 mii = device_get_softc(sc_if->msk_miibus); 487 ifp = sc_if->msk_ifp; 488 if (mii == NULL || ifp == NULL || 489 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 490 return; 491 492 sc_if->msk_flags &= ~MSK_FLAG_LINK; 493 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 494 (IFM_AVALID | IFM_ACTIVE)) { 495 switch (IFM_SUBTYPE(mii->mii_media_active)) { 496 case IFM_10_T: 497 case IFM_100_TX: 498 sc_if->msk_flags |= MSK_FLAG_LINK; 499 break; 500 case IFM_1000_T: 501 case IFM_1000_SX: 502 case IFM_1000_LX: 503 case IFM_1000_CX: 504 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) 505 sc_if->msk_flags |= MSK_FLAG_LINK; 506 break; 507 default: 508 break; 509 } 510 } 511 512 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) { 513 /* Enable Tx FIFO Underrun. */ 514 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 515 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 516 /* 517 * Because mii(4) notify msk(4) that it detected link status 518 * change, there is no need to enable automatic 519 * speed/flow-control/duplex updates. 520 */ 521 gmac = GM_GPCR_AU_ALL_DIS; 522 switch (IFM_SUBTYPE(mii->mii_media_active)) { 523 case IFM_1000_SX: 524 case IFM_1000_T: 525 gmac |= GM_GPCR_SPEED_1000; 526 break; 527 case IFM_100_TX: 528 gmac |= GM_GPCR_SPEED_100; 529 break; 530 case IFM_10_T: 531 break; 532 } 533 534 if ((IFM_OPTIONS(mii->mii_media_active) & 535 IFM_ETH_RXPAUSE) == 0) 536 gmac |= GM_GPCR_FC_RX_DIS; 537 if ((IFM_OPTIONS(mii->mii_media_active) & 538 IFM_ETH_TXPAUSE) == 0) 539 gmac |= GM_GPCR_FC_TX_DIS; 540 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 541 gmac |= GM_GPCR_DUP_FULL; 542 else 543 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS; 544 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 545 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 546 /* Read again to ensure writing. */ 547 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 548 gmac = GMC_PAUSE_OFF; 549 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 550 if ((IFM_OPTIONS(mii->mii_media_active) & 551 IFM_ETH_RXPAUSE) != 0) 552 gmac = GMC_PAUSE_ON; 553 } 554 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 555 556 /* Enable PHY interrupt for FIFO underrun/overflow. */ 557 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 558 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 559 } else { 560 /* 561 * Link state changed to down. 562 * Disable PHY interrupts. 563 */ 564 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 565 /* Disable Rx/Tx MAC. */ 566 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 567 if ((gmac & (GM_GPCR_RX_ENA | GM_GPCR_TX_ENA)) != 0) { 568 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 569 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 570 /* Read again to ensure writing. */ 571 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 572 } 573 } 574 } 575 576 static u_int 577 msk_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 578 { 579 uint32_t *mchash = arg; 580 uint32_t crc; 581 582 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 583 /* Just want the 6 least significant bits. */ 584 crc &= 0x3f; 585 /* Set the corresponding bit in the hash table. */ 586 mchash[crc >> 5] |= 1 << (crc & 0x1f); 587 588 return (1); 589 } 590 591 static void 592 msk_rxfilter(struct msk_if_softc *sc_if) 593 { 594 struct msk_softc *sc; 595 struct ifnet *ifp; 596 uint32_t mchash[2]; 597 uint16_t mode; 598 599 sc = sc_if->msk_softc; 600 601 MSK_IF_LOCK_ASSERT(sc_if); 602 603 ifp = sc_if->msk_ifp; 604 605 bzero(mchash, sizeof(mchash)); 606 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 607 if ((ifp->if_flags & IFF_PROMISC) != 0) 608 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 609 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 610 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 611 mchash[0] = 0xffff; 612 mchash[1] = 0xffff; 613 } else { 614 mode |= GM_RXCR_UCF_ENA; 615 if_foreach_llmaddr(ifp, msk_hash_maddr, mchash); 616 if (mchash[0] != 0 || mchash[1] != 0) 617 mode |= GM_RXCR_MCF_ENA; 618 } 619 620 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 621 mchash[0] & 0xffff); 622 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 623 (mchash[0] >> 16) & 0xffff); 624 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 625 mchash[1] & 0xffff); 626 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 627 (mchash[1] >> 16) & 0xffff); 628 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 629 } 630 631 static void 632 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 633 { 634 struct msk_softc *sc; 635 636 sc = sc_if->msk_softc; 637 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 638 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 639 RX_VLAN_STRIP_ON); 640 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 641 TX_VLAN_TAG_ON); 642 } else { 643 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 644 RX_VLAN_STRIP_OFF); 645 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 646 TX_VLAN_TAG_OFF); 647 } 648 } 649 650 static int 651 msk_rx_fill(struct msk_if_softc *sc_if, int jumbo) 652 { 653 uint16_t idx; 654 int i; 655 656 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 657 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 658 /* Wait until controller executes OP_TCPSTART command. */ 659 for (i = 100; i > 0; i--) { 660 DELAY(100); 661 idx = CSR_READ_2(sc_if->msk_softc, 662 Y2_PREF_Q_ADDR(sc_if->msk_rxq, 663 PREF_UNIT_GET_IDX_REG)); 664 if (idx != 0) 665 break; 666 } 667 if (i == 0) { 668 device_printf(sc_if->msk_if_dev, 669 "prefetch unit stuck?\n"); 670 return (ETIMEDOUT); 671 } 672 /* 673 * Fill consumed LE with free buffer. This can be done 674 * in Rx handler but we don't want to add special code 675 * in fast handler. 676 */ 677 if (jumbo > 0) { 678 if (msk_jumbo_newbuf(sc_if, 0) != 0) 679 return (ENOBUFS); 680 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 681 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 682 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 683 } else { 684 if (msk_newbuf(sc_if, 0) != 0) 685 return (ENOBUFS); 686 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 687 sc_if->msk_cdata.msk_rx_ring_map, 688 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 689 } 690 sc_if->msk_cdata.msk_rx_prod = 0; 691 CSR_WRITE_2(sc_if->msk_softc, 692 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 693 sc_if->msk_cdata.msk_rx_prod); 694 } 695 return (0); 696 } 697 698 static int 699 msk_init_rx_ring(struct msk_if_softc *sc_if) 700 { 701 struct msk_ring_data *rd; 702 struct msk_rxdesc *rxd; 703 int i, nbuf, prod; 704 705 MSK_IF_LOCK_ASSERT(sc_if); 706 707 sc_if->msk_cdata.msk_rx_cons = 0; 708 sc_if->msk_cdata.msk_rx_prod = 0; 709 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 710 711 rd = &sc_if->msk_rdata; 712 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 713 for (i = prod = 0; i < MSK_RX_RING_CNT; i++) { 714 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 715 rxd->rx_m = NULL; 716 rxd->rx_le = &rd->msk_rx_ring[prod]; 717 MSK_INC(prod, MSK_RX_RING_CNT); 718 } 719 nbuf = MSK_RX_BUF_CNT; 720 prod = 0; 721 /* Have controller know how to compute Rx checksum. */ 722 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 723 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 724 #ifdef MSK_64BIT_DMA 725 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 726 rxd->rx_m = NULL; 727 rxd->rx_le = &rd->msk_rx_ring[prod]; 728 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 729 ETHER_HDR_LEN); 730 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 731 MSK_INC(prod, MSK_RX_RING_CNT); 732 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 733 #endif 734 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 735 rxd->rx_m = NULL; 736 rxd->rx_le = &rd->msk_rx_ring[prod]; 737 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 738 ETHER_HDR_LEN); 739 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 740 MSK_INC(prod, MSK_RX_RING_CNT); 741 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 742 nbuf--; 743 } 744 for (i = 0; i < nbuf; i++) { 745 if (msk_newbuf(sc_if, prod) != 0) 746 return (ENOBUFS); 747 MSK_RX_INC(prod, MSK_RX_RING_CNT); 748 } 749 750 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 751 sc_if->msk_cdata.msk_rx_ring_map, 752 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 753 754 /* Update prefetch unit. */ 755 sc_if->msk_cdata.msk_rx_prod = prod; 756 CSR_WRITE_2(sc_if->msk_softc, 757 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 758 (sc_if->msk_cdata.msk_rx_prod + MSK_RX_RING_CNT - 1) % 759 MSK_RX_RING_CNT); 760 if (msk_rx_fill(sc_if, 0) != 0) 761 return (ENOBUFS); 762 return (0); 763 } 764 765 static int 766 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 767 { 768 struct msk_ring_data *rd; 769 struct msk_rxdesc *rxd; 770 int i, nbuf, prod; 771 772 MSK_IF_LOCK_ASSERT(sc_if); 773 774 sc_if->msk_cdata.msk_rx_cons = 0; 775 sc_if->msk_cdata.msk_rx_prod = 0; 776 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 777 778 rd = &sc_if->msk_rdata; 779 bzero(rd->msk_jumbo_rx_ring, 780 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 781 for (i = prod = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 782 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 783 rxd->rx_m = NULL; 784 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 785 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 786 } 787 nbuf = MSK_RX_BUF_CNT; 788 prod = 0; 789 /* Have controller know how to compute Rx checksum. */ 790 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 791 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 792 #ifdef MSK_64BIT_DMA 793 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 794 rxd->rx_m = NULL; 795 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 796 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 797 ETHER_HDR_LEN); 798 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 799 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 800 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 801 #endif 802 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 803 rxd->rx_m = NULL; 804 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 805 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 806 ETHER_HDR_LEN); 807 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 808 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 809 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 810 nbuf--; 811 } 812 for (i = 0; i < nbuf; i++) { 813 if (msk_jumbo_newbuf(sc_if, prod) != 0) 814 return (ENOBUFS); 815 MSK_RX_INC(prod, MSK_JUMBO_RX_RING_CNT); 816 } 817 818 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 819 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 820 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 821 822 /* Update prefetch unit. */ 823 sc_if->msk_cdata.msk_rx_prod = prod; 824 CSR_WRITE_2(sc_if->msk_softc, 825 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 826 (sc_if->msk_cdata.msk_rx_prod + MSK_JUMBO_RX_RING_CNT - 1) % 827 MSK_JUMBO_RX_RING_CNT); 828 if (msk_rx_fill(sc_if, 1) != 0) 829 return (ENOBUFS); 830 return (0); 831 } 832 833 static void 834 msk_init_tx_ring(struct msk_if_softc *sc_if) 835 { 836 struct msk_ring_data *rd; 837 struct msk_txdesc *txd; 838 int i; 839 840 sc_if->msk_cdata.msk_tso_mtu = 0; 841 sc_if->msk_cdata.msk_last_csum = 0; 842 sc_if->msk_cdata.msk_tx_prod = 0; 843 sc_if->msk_cdata.msk_tx_cons = 0; 844 sc_if->msk_cdata.msk_tx_cnt = 0; 845 sc_if->msk_cdata.msk_tx_high_addr = 0; 846 847 rd = &sc_if->msk_rdata; 848 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 849 for (i = 0; i < MSK_TX_RING_CNT; i++) { 850 txd = &sc_if->msk_cdata.msk_txdesc[i]; 851 txd->tx_m = NULL; 852 txd->tx_le = &rd->msk_tx_ring[i]; 853 } 854 855 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 856 sc_if->msk_cdata.msk_tx_ring_map, 857 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 858 } 859 860 static __inline void 861 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 862 { 863 struct msk_rx_desc *rx_le; 864 struct msk_rxdesc *rxd; 865 struct mbuf *m; 866 867 #ifdef MSK_64BIT_DMA 868 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 869 rx_le = rxd->rx_le; 870 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 871 MSK_INC(idx, MSK_RX_RING_CNT); 872 #endif 873 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 874 m = rxd->rx_m; 875 rx_le = rxd->rx_le; 876 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 877 } 878 879 static __inline void 880 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 881 { 882 struct msk_rx_desc *rx_le; 883 struct msk_rxdesc *rxd; 884 struct mbuf *m; 885 886 #ifdef MSK_64BIT_DMA 887 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 888 rx_le = rxd->rx_le; 889 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 890 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT); 891 #endif 892 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 893 m = rxd->rx_m; 894 rx_le = rxd->rx_le; 895 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 896 } 897 898 static int 899 msk_newbuf(struct msk_if_softc *sc_if, int idx) 900 { 901 struct msk_rx_desc *rx_le; 902 struct msk_rxdesc *rxd; 903 struct mbuf *m; 904 bus_dma_segment_t segs[1]; 905 bus_dmamap_t map; 906 int nsegs; 907 908 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 909 if (m == NULL) 910 return (ENOBUFS); 911 912 m->m_len = m->m_pkthdr.len = MCLBYTES; 913 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 914 m_adj(m, ETHER_ALIGN); 915 #ifndef __NO_STRICT_ALIGNMENT 916 else 917 m_adj(m, MSK_RX_BUF_ALIGN); 918 #endif 919 920 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 921 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 922 BUS_DMA_NOWAIT) != 0) { 923 m_freem(m); 924 return (ENOBUFS); 925 } 926 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 927 928 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 929 #ifdef MSK_64BIT_DMA 930 rx_le = rxd->rx_le; 931 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr)); 932 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 933 MSK_INC(idx, MSK_RX_RING_CNT); 934 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 935 #endif 936 if (rxd->rx_m != NULL) { 937 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 938 BUS_DMASYNC_POSTREAD); 939 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 940 rxd->rx_m = NULL; 941 } 942 map = rxd->rx_dmamap; 943 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 944 sc_if->msk_cdata.msk_rx_sparemap = map; 945 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 946 BUS_DMASYNC_PREREAD); 947 rxd->rx_m = m; 948 rx_le = rxd->rx_le; 949 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 950 rx_le->msk_control = 951 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 952 953 return (0); 954 } 955 956 static int 957 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 958 { 959 struct msk_rx_desc *rx_le; 960 struct msk_rxdesc *rxd; 961 struct mbuf *m; 962 bus_dma_segment_t segs[1]; 963 bus_dmamap_t map; 964 int nsegs; 965 966 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 967 if (m == NULL) 968 return (ENOBUFS); 969 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 970 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 971 m_adj(m, ETHER_ALIGN); 972 #ifndef __NO_STRICT_ALIGNMENT 973 else 974 m_adj(m, MSK_RX_BUF_ALIGN); 975 #endif 976 977 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 978 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 979 BUS_DMA_NOWAIT) != 0) { 980 m_freem(m); 981 return (ENOBUFS); 982 } 983 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 984 985 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 986 #ifdef MSK_64BIT_DMA 987 rx_le = rxd->rx_le; 988 rx_le->msk_addr = htole32(MSK_ADDR_HI(segs[0].ds_addr)); 989 rx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 990 MSK_INC(idx, MSK_JUMBO_RX_RING_CNT); 991 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 992 #endif 993 if (rxd->rx_m != NULL) { 994 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 995 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 996 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 997 rxd->rx_dmamap); 998 rxd->rx_m = NULL; 999 } 1000 map = rxd->rx_dmamap; 1001 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 1002 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 1003 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 1004 BUS_DMASYNC_PREREAD); 1005 rxd->rx_m = m; 1006 rx_le = rxd->rx_le; 1007 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 1008 rx_le->msk_control = 1009 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 1010 1011 return (0); 1012 } 1013 1014 /* 1015 * Set media options. 1016 */ 1017 static int 1018 msk_mediachange(struct ifnet *ifp) 1019 { 1020 struct msk_if_softc *sc_if; 1021 struct mii_data *mii; 1022 int error; 1023 1024 sc_if = ifp->if_softc; 1025 1026 MSK_IF_LOCK(sc_if); 1027 mii = device_get_softc(sc_if->msk_miibus); 1028 error = mii_mediachg(mii); 1029 MSK_IF_UNLOCK(sc_if); 1030 1031 return (error); 1032 } 1033 1034 /* 1035 * Report current media status. 1036 */ 1037 static void 1038 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 1039 { 1040 struct msk_if_softc *sc_if; 1041 struct mii_data *mii; 1042 1043 sc_if = ifp->if_softc; 1044 MSK_IF_LOCK(sc_if); 1045 if ((ifp->if_flags & IFF_UP) == 0) { 1046 MSK_IF_UNLOCK(sc_if); 1047 return; 1048 } 1049 mii = device_get_softc(sc_if->msk_miibus); 1050 1051 mii_pollstat(mii); 1052 ifmr->ifm_active = mii->mii_media_active; 1053 ifmr->ifm_status = mii->mii_media_status; 1054 MSK_IF_UNLOCK(sc_if); 1055 } 1056 1057 static int 1058 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1059 { 1060 struct msk_if_softc *sc_if; 1061 struct ifreq *ifr; 1062 struct mii_data *mii; 1063 int error, mask, reinit; 1064 1065 sc_if = ifp->if_softc; 1066 ifr = (struct ifreq *)data; 1067 error = 0; 1068 1069 switch(command) { 1070 case SIOCSIFMTU: 1071 MSK_IF_LOCK(sc_if); 1072 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) 1073 error = EINVAL; 1074 else if (ifp->if_mtu != ifr->ifr_mtu) { 1075 if (ifr->ifr_mtu > ETHERMTU) { 1076 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 1077 error = EINVAL; 1078 MSK_IF_UNLOCK(sc_if); 1079 break; 1080 } 1081 if ((sc_if->msk_flags & 1082 MSK_FLAG_JUMBO_NOCSUM) != 0) { 1083 ifp->if_hwassist &= 1084 ~(MSK_CSUM_FEATURES | CSUM_TSO); 1085 ifp->if_capenable &= 1086 ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1087 VLAN_CAPABILITIES(ifp); 1088 } 1089 } 1090 ifp->if_mtu = ifr->ifr_mtu; 1091 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1092 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1093 msk_init_locked(sc_if); 1094 } 1095 } 1096 MSK_IF_UNLOCK(sc_if); 1097 break; 1098 case SIOCSIFFLAGS: 1099 MSK_IF_LOCK(sc_if); 1100 if ((ifp->if_flags & IFF_UP) != 0) { 1101 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 1102 ((ifp->if_flags ^ sc_if->msk_if_flags) & 1103 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1104 msk_rxfilter(sc_if); 1105 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0) 1106 msk_init_locked(sc_if); 1107 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1108 msk_stop(sc_if); 1109 sc_if->msk_if_flags = ifp->if_flags; 1110 MSK_IF_UNLOCK(sc_if); 1111 break; 1112 case SIOCADDMULTI: 1113 case SIOCDELMULTI: 1114 MSK_IF_LOCK(sc_if); 1115 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1116 msk_rxfilter(sc_if); 1117 MSK_IF_UNLOCK(sc_if); 1118 break; 1119 case SIOCGIFMEDIA: 1120 case SIOCSIFMEDIA: 1121 mii = device_get_softc(sc_if->msk_miibus); 1122 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1123 break; 1124 case SIOCSIFCAP: 1125 reinit = 0; 1126 MSK_IF_LOCK(sc_if); 1127 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1128 if ((mask & IFCAP_TXCSUM) != 0 && 1129 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1130 ifp->if_capenable ^= IFCAP_TXCSUM; 1131 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1132 ifp->if_hwassist |= MSK_CSUM_FEATURES; 1133 else 1134 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 1135 } 1136 if ((mask & IFCAP_RXCSUM) != 0 && 1137 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) { 1138 ifp->if_capenable ^= IFCAP_RXCSUM; 1139 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) 1140 reinit = 1; 1141 } 1142 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1143 (IFCAP_VLAN_HWCSUM & ifp->if_capabilities) != 0) 1144 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1145 if ((mask & IFCAP_TSO4) != 0 && 1146 (IFCAP_TSO4 & ifp->if_capabilities) != 0) { 1147 ifp->if_capenable ^= IFCAP_TSO4; 1148 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 1149 ifp->if_hwassist |= CSUM_TSO; 1150 else 1151 ifp->if_hwassist &= ~CSUM_TSO; 1152 } 1153 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1154 (IFCAP_VLAN_HWTSO & ifp->if_capabilities) != 0) 1155 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1156 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1157 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 1158 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1159 if ((IFCAP_VLAN_HWTAGGING & ifp->if_capenable) == 0) 1160 ifp->if_capenable &= 1161 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 1162 msk_setvlan(sc_if, ifp); 1163 } 1164 if (ifp->if_mtu > ETHERMTU && 1165 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 1166 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 1167 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1168 } 1169 VLAN_CAPABILITIES(ifp); 1170 if (reinit > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1171 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1172 msk_init_locked(sc_if); 1173 } 1174 MSK_IF_UNLOCK(sc_if); 1175 break; 1176 default: 1177 error = ether_ioctl(ifp, command, data); 1178 break; 1179 } 1180 1181 return (error); 1182 } 1183 1184 static int 1185 mskc_probe(device_t dev) 1186 { 1187 const struct msk_product *mp; 1188 uint16_t vendor, devid; 1189 int i; 1190 1191 vendor = pci_get_vendor(dev); 1192 devid = pci_get_device(dev); 1193 mp = msk_products; 1194 for (i = 0; i < nitems(msk_products); i++, mp++) { 1195 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1196 device_set_desc(dev, mp->msk_name); 1197 return (BUS_PROBE_DEFAULT); 1198 } 1199 } 1200 1201 return (ENXIO); 1202 } 1203 1204 static int 1205 mskc_setup_rambuffer(struct msk_softc *sc) 1206 { 1207 int next; 1208 int i; 1209 1210 /* Get adapter SRAM size. */ 1211 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; 1212 if (bootverbose) 1213 device_printf(sc->msk_dev, 1214 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1215 if (sc->msk_ramsize == 0) 1216 return (0); 1217 1218 sc->msk_pflags |= MSK_FLAG_RAMBUF; 1219 /* 1220 * Give receiver 2/3 of memory and round down to the multiple 1221 * of 1024. Tx/Rx RAM buffer size of Yukon II should be multiple 1222 * of 1024. 1223 */ 1224 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1225 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1226 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1227 sc->msk_rxqstart[i] = next; 1228 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1229 next = sc->msk_rxqend[i] + 1; 1230 sc->msk_txqstart[i] = next; 1231 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1232 next = sc->msk_txqend[i] + 1; 1233 if (bootverbose) { 1234 device_printf(sc->msk_dev, 1235 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1236 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1237 sc->msk_rxqend[i]); 1238 device_printf(sc->msk_dev, 1239 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1240 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1241 sc->msk_txqend[i]); 1242 } 1243 } 1244 1245 return (0); 1246 } 1247 1248 static void 1249 msk_phy_power(struct msk_softc *sc, int mode) 1250 { 1251 uint32_t our, val; 1252 int i; 1253 1254 switch (mode) { 1255 case MSK_PHY_POWERUP: 1256 /* Switch power to VCC (WA for VAUX problem). */ 1257 CSR_WRITE_1(sc, B0_POWER_CTRL, 1258 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1259 /* Disable Core Clock Division, set Clock Select to 0. */ 1260 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1261 1262 val = 0; 1263 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1264 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1265 /* Enable bits are inverted. */ 1266 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1267 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1268 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1269 } 1270 /* 1271 * Enable PCI & Core Clock, enable clock gating for both Links. 1272 */ 1273 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1274 1275 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1276 our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1277 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 1278 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1279 /* Deassert Low Power for 1st PHY. */ 1280 our |= PCI_Y2_PHY1_COMA; 1281 if (sc->msk_num_port > 1) 1282 our |= PCI_Y2_PHY2_COMA; 1283 } 1284 } 1285 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U || 1286 sc->msk_hw_id == CHIP_ID_YUKON_EX || 1287 sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) { 1288 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4); 1289 val &= (PCI_FORCE_ASPM_REQUEST | 1290 PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY | 1291 PCI_ASPM_CLKRUN_REQUEST); 1292 /* Set all bits to 0 except bits 15..12. */ 1293 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val); 1294 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5); 1295 val &= PCI_CTL_TIM_VMAIN_AV_MSK; 1296 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val); 1297 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0); 1298 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); 1299 /* 1300 * Disable status race, workaround for 1301 * Yukon EC Ultra & Yukon EX. 1302 */ 1303 val = CSR_READ_4(sc, B2_GP_IO); 1304 val |= GLB_GPIO_STAT_RACE_DIS; 1305 CSR_WRITE_4(sc, B2_GP_IO, val); 1306 CSR_READ_4(sc, B2_GP_IO); 1307 } 1308 /* Release PHY from PowerDown/COMA mode. */ 1309 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our); 1310 1311 for (i = 0; i < sc->msk_num_port; i++) { 1312 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1313 GMLC_RST_SET); 1314 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1315 GMLC_RST_CLR); 1316 } 1317 break; 1318 case MSK_PHY_POWERDOWN: 1319 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1320 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1321 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1322 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1323 val &= ~PCI_Y2_PHY1_COMA; 1324 if (sc->msk_num_port > 1) 1325 val &= ~PCI_Y2_PHY2_COMA; 1326 } 1327 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1328 1329 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1330 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1331 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1332 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1333 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1334 /* Enable bits are inverted. */ 1335 val = 0; 1336 } 1337 /* 1338 * Disable PCI & Core Clock, disable clock gating for 1339 * both Links. 1340 */ 1341 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1342 CSR_WRITE_1(sc, B0_POWER_CTRL, 1343 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1344 break; 1345 default: 1346 break; 1347 } 1348 } 1349 1350 static void 1351 mskc_reset(struct msk_softc *sc) 1352 { 1353 bus_addr_t addr; 1354 uint16_t status; 1355 uint32_t val; 1356 int i, initram; 1357 1358 /* Disable ASF. */ 1359 if (sc->msk_hw_id >= CHIP_ID_YUKON_XL && 1360 sc->msk_hw_id <= CHIP_ID_YUKON_SUPR) { 1361 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 1362 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 1363 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1364 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); 1365 /* Clear AHB bridge & microcontroller reset. */ 1366 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | 1367 Y2_ASF_HCU_CCSR_CPU_RST_MODE); 1368 /* Clear ASF microcontroller state. */ 1369 status &= ~Y2_ASF_HCU_CCSR_UC_STATE_MSK; 1370 status &= ~Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK; 1371 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); 1372 CSR_WRITE_4(sc, B28_Y2_CPU_WDOG, 0); 1373 } else 1374 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1375 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1376 /* 1377 * Since we disabled ASF, S/W reset is required for 1378 * Power Management. 1379 */ 1380 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1381 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1382 } 1383 1384 /* Clear all error bits in the PCI status register. */ 1385 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1386 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1387 1388 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1389 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1390 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 1391 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1392 1393 switch (sc->msk_bustype) { 1394 case MSK_PEX_BUS: 1395 /* Clear all PEX errors. */ 1396 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1397 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1398 if ((val & PEX_RX_OV) != 0) { 1399 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1400 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1401 } 1402 break; 1403 case MSK_PCI_BUS: 1404 case MSK_PCIX_BUS: 1405 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1406 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1407 if (val == 0) 1408 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1409 if (sc->msk_bustype == MSK_PCIX_BUS) { 1410 /* Set Cache Line Size opt. */ 1411 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1412 val |= PCI_CLS_OPT; 1413 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1414 } 1415 break; 1416 } 1417 /* Set PHY power state. */ 1418 msk_phy_power(sc, MSK_PHY_POWERUP); 1419 1420 /* Reset GPHY/GMAC Control */ 1421 for (i = 0; i < sc->msk_num_port; i++) { 1422 /* GPHY Control reset. */ 1423 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1424 CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1425 /* GMAC Control reset. */ 1426 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1427 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1428 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1429 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 1430 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) 1431 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), 1432 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 1433 GMC_BYP_RETR_ON); 1434 } 1435 1436 if (sc->msk_hw_id == CHIP_ID_YUKON_SUPR && 1437 sc->msk_hw_rev > CHIP_REV_YU_SU_B0) 1438 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, PCI_CLK_MACSEC_DIS); 1439 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) { 1440 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */ 1441 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080); 1442 } 1443 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1444 1445 /* LED On. */ 1446 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1447 1448 /* Clear TWSI IRQ. */ 1449 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1450 1451 /* Turn off hardware timer. */ 1452 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1453 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1454 1455 /* Turn off descriptor polling. */ 1456 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1457 1458 /* Turn off time stamps. */ 1459 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1460 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1461 1462 initram = 0; 1463 if (sc->msk_hw_id == CHIP_ID_YUKON_XL || 1464 sc->msk_hw_id == CHIP_ID_YUKON_EC || 1465 sc->msk_hw_id == CHIP_ID_YUKON_FE) 1466 initram++; 1467 1468 /* Configure timeout values. */ 1469 for (i = 0; initram > 0 && i < sc->msk_num_port; i++) { 1470 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1471 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1472 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1473 MSK_RI_TO_53); 1474 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1475 MSK_RI_TO_53); 1476 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1477 MSK_RI_TO_53); 1478 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1479 MSK_RI_TO_53); 1480 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1481 MSK_RI_TO_53); 1482 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1483 MSK_RI_TO_53); 1484 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1485 MSK_RI_TO_53); 1486 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1487 MSK_RI_TO_53); 1488 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1489 MSK_RI_TO_53); 1490 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1491 MSK_RI_TO_53); 1492 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1493 MSK_RI_TO_53); 1494 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1495 MSK_RI_TO_53); 1496 } 1497 1498 /* Disable all interrupts. */ 1499 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1500 CSR_READ_4(sc, B0_HWE_IMSK); 1501 CSR_WRITE_4(sc, B0_IMSK, 0); 1502 CSR_READ_4(sc, B0_IMSK); 1503 1504 /* 1505 * On dual port PCI-X card, there is an problem where status 1506 * can be received out of order due to split transactions. 1507 */ 1508 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) { 1509 uint16_t pcix_cmd; 1510 1511 pcix_cmd = pci_read_config(sc->msk_dev, 1512 sc->msk_pcixcap + PCIXR_COMMAND, 2); 1513 /* Clear Max Outstanding Split Transactions. */ 1514 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS; 1515 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1516 pci_write_config(sc->msk_dev, 1517 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2); 1518 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1519 } 1520 if (sc->msk_expcap != 0) { 1521 /* Change Max. Read Request Size to 2048 bytes. */ 1522 if (pci_get_max_read_req(sc->msk_dev) == 512) 1523 pci_set_max_read_req(sc->msk_dev, 2048); 1524 } 1525 1526 /* Clear status list. */ 1527 bzero(sc->msk_stat_ring, 1528 sizeof(struct msk_stat_desc) * sc->msk_stat_count); 1529 sc->msk_stat_cons = 0; 1530 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1531 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1532 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1533 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1534 /* Set the status list base address. */ 1535 addr = sc->msk_stat_ring_paddr; 1536 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1537 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1538 /* Set the status list last index. */ 1539 CSR_WRITE_2(sc, STAT_LAST_IDX, sc->msk_stat_count - 1); 1540 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1541 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1542 /* WA for dev. #4.3 */ 1543 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1544 /* WA for dev. #4.18 */ 1545 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1546 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1547 } else { 1548 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1549 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1550 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1551 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1552 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1553 else 1554 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1555 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1556 } 1557 /* 1558 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1559 */ 1560 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1561 1562 /* Enable status unit. */ 1563 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1564 1565 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1566 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1567 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1568 } 1569 1570 static int 1571 msk_probe(device_t dev) 1572 { 1573 struct msk_softc *sc; 1574 char desc[100]; 1575 1576 sc = device_get_softc(device_get_parent(dev)); 1577 /* 1578 * Not much to do here. We always know there will be 1579 * at least one GMAC present, and if there are two, 1580 * mskc_attach() will create a second device instance 1581 * for us. 1582 */ 1583 snprintf(desc, sizeof(desc), 1584 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1585 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1586 sc->msk_hw_rev); 1587 device_set_desc_copy(dev, desc); 1588 1589 return (BUS_PROBE_DEFAULT); 1590 } 1591 1592 static int 1593 msk_attach(device_t dev) 1594 { 1595 struct msk_softc *sc; 1596 struct msk_if_softc *sc_if; 1597 struct ifnet *ifp; 1598 struct msk_mii_data *mmd; 1599 int i, port, error; 1600 uint8_t eaddr[6]; 1601 1602 if (dev == NULL) 1603 return (EINVAL); 1604 1605 error = 0; 1606 sc_if = device_get_softc(dev); 1607 sc = device_get_softc(device_get_parent(dev)); 1608 mmd = device_get_ivars(dev); 1609 port = mmd->port; 1610 1611 sc_if->msk_if_dev = dev; 1612 sc_if->msk_port = port; 1613 sc_if->msk_softc = sc; 1614 sc_if->msk_flags = sc->msk_pflags; 1615 sc->msk_if[port] = sc_if; 1616 /* Setup Tx/Rx queue register offsets. */ 1617 if (port == MSK_PORT_A) { 1618 sc_if->msk_txq = Q_XA1; 1619 sc_if->msk_txsq = Q_XS1; 1620 sc_if->msk_rxq = Q_R1; 1621 } else { 1622 sc_if->msk_txq = Q_XA2; 1623 sc_if->msk_txsq = Q_XS2; 1624 sc_if->msk_rxq = Q_R2; 1625 } 1626 1627 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1628 msk_sysctl_node(sc_if); 1629 1630 if ((error = msk_txrx_dma_alloc(sc_if)) != 0) 1631 goto fail; 1632 msk_rx_dma_jalloc(sc_if); 1633 1634 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1635 if (ifp == NULL) { 1636 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1637 error = ENOSPC; 1638 goto fail; 1639 } 1640 ifp->if_softc = sc_if; 1641 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1642 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1643 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1644 /* 1645 * Enable Rx checksum offloading if controller supports 1646 * new descriptor formant and controller is not Yukon XL. 1647 */ 1648 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 1649 sc->msk_hw_id != CHIP_ID_YUKON_XL) 1650 ifp->if_capabilities |= IFCAP_RXCSUM; 1651 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1652 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1653 ifp->if_capabilities |= IFCAP_RXCSUM; 1654 ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO; 1655 ifp->if_capenable = ifp->if_capabilities; 1656 ifp->if_ioctl = msk_ioctl; 1657 ifp->if_start = msk_start; 1658 ifp->if_init = msk_init; 1659 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1660 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1; 1661 IFQ_SET_READY(&ifp->if_snd); 1662 /* 1663 * Get station address for this interface. Note that 1664 * dual port cards actually come with three station 1665 * addresses: one for each port, plus an extra. The 1666 * extra one is used by the SysKonnect driver software 1667 * as a 'virtual' station address for when both ports 1668 * are operating in failover mode. Currently we don't 1669 * use this extra address. 1670 */ 1671 MSK_IF_LOCK(sc_if); 1672 for (i = 0; i < ETHER_ADDR_LEN; i++) 1673 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1674 1675 /* 1676 * Call MI attach routine. Can't hold locks when calling into ether_*. 1677 */ 1678 MSK_IF_UNLOCK(sc_if); 1679 ether_ifattach(ifp, eaddr); 1680 MSK_IF_LOCK(sc_if); 1681 1682 /* VLAN capability setup */ 1683 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1684 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) { 1685 /* 1686 * Due to Tx checksum offload hardware bugs, msk(4) manually 1687 * computes checksum for short frames. For VLAN tagged frames 1688 * this workaround does not work so disable checksum offload 1689 * for VLAN interface. 1690 */ 1691 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO; 1692 /* 1693 * Enable Rx checksum offloading for VLAN tagged frames 1694 * if controller support new descriptor format. 1695 */ 1696 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1697 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1698 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1699 } 1700 ifp->if_capenable = ifp->if_capabilities; 1701 /* 1702 * Disable RX checksum offloading on controllers that don't use 1703 * new descriptor format but give chance to enable it. 1704 */ 1705 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) 1706 ifp->if_capenable &= ~IFCAP_RXCSUM; 1707 1708 /* 1709 * Tell the upper layer(s) we support long frames. 1710 * Must appear after the call to ether_ifattach() because 1711 * ether_ifattach() sets ifi_hdrlen to the default value. 1712 */ 1713 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1714 1715 /* 1716 * Do miibus setup. 1717 */ 1718 MSK_IF_UNLOCK(sc_if); 1719 error = mii_attach(dev, &sc_if->msk_miibus, ifp, msk_mediachange, 1720 msk_mediastatus, BMSR_DEFCAPMASK, PHY_ADDR_MARV, MII_OFFSET_ANY, 1721 mmd->mii_flags); 1722 if (error != 0) { 1723 device_printf(sc_if->msk_if_dev, "attaching PHYs failed\n"); 1724 ether_ifdetach(ifp); 1725 error = ENXIO; 1726 goto fail; 1727 } 1728 1729 fail: 1730 if (error != 0) { 1731 /* Access should be ok even though lock has been dropped */ 1732 sc->msk_if[port] = NULL; 1733 msk_detach(dev); 1734 } 1735 1736 return (error); 1737 } 1738 1739 /* 1740 * Attach the interface. Allocate softc structures, do ifmedia 1741 * setup and ethernet/BPF attach. 1742 */ 1743 static int 1744 mskc_attach(device_t dev) 1745 { 1746 struct msk_softc *sc; 1747 struct msk_mii_data *mmd; 1748 int error, msic, msir, reg; 1749 1750 sc = device_get_softc(dev); 1751 sc->msk_dev = dev; 1752 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1753 MTX_DEF); 1754 1755 /* 1756 * Map control/status registers. 1757 */ 1758 pci_enable_busmaster(dev); 1759 1760 /* Allocate I/O resource */ 1761 #ifdef MSK_USEIOSPACE 1762 sc->msk_res_spec = msk_res_spec_io; 1763 #else 1764 sc->msk_res_spec = msk_res_spec_mem; 1765 #endif 1766 sc->msk_irq_spec = msk_irq_spec_legacy; 1767 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1768 if (error) { 1769 if (sc->msk_res_spec == msk_res_spec_mem) 1770 sc->msk_res_spec = msk_res_spec_io; 1771 else 1772 sc->msk_res_spec = msk_res_spec_mem; 1773 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1774 if (error) { 1775 device_printf(dev, "couldn't allocate %s resources\n", 1776 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1777 "I/O"); 1778 mtx_destroy(&sc->msk_mtx); 1779 return (ENXIO); 1780 } 1781 } 1782 1783 /* Enable all clocks before accessing any registers. */ 1784 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 1785 1786 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1787 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1788 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1789 /* Bail out if chip is not recognized. */ 1790 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1791 sc->msk_hw_id > CHIP_ID_YUKON_OPT || 1792 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) { 1793 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1794 sc->msk_hw_id, sc->msk_hw_rev); 1795 mtx_destroy(&sc->msk_mtx); 1796 return (ENXIO); 1797 } 1798 1799 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1800 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1801 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 1802 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1803 "max number of Rx events to process"); 1804 1805 sc->msk_process_limit = MSK_PROC_DEFAULT; 1806 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1807 "process_limit", &sc->msk_process_limit); 1808 if (error == 0) { 1809 if (sc->msk_process_limit < MSK_PROC_MIN || 1810 sc->msk_process_limit > MSK_PROC_MAX) { 1811 device_printf(dev, "process_limit value out of range; " 1812 "using default: %d\n", MSK_PROC_DEFAULT); 1813 sc->msk_process_limit = MSK_PROC_DEFAULT; 1814 } 1815 } 1816 1817 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT; 1818 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 1819 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 1820 "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0, 1821 "Maximum number of time to delay interrupts"); 1822 resource_int_value(device_get_name(dev), device_get_unit(dev), 1823 "int_holdoff", &sc->msk_int_holdoff); 1824 1825 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1826 /* Check number of MACs. */ 1827 sc->msk_num_port = 1; 1828 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1829 CFG_DUAL_MAC_MSK) { 1830 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1831 sc->msk_num_port++; 1832 } 1833 1834 /* Check bus type. */ 1835 if (pci_find_cap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) { 1836 sc->msk_bustype = MSK_PEX_BUS; 1837 sc->msk_expcap = reg; 1838 } else if (pci_find_cap(sc->msk_dev, PCIY_PCIX, ®) == 0) { 1839 sc->msk_bustype = MSK_PCIX_BUS; 1840 sc->msk_pcixcap = reg; 1841 } else 1842 sc->msk_bustype = MSK_PCI_BUS; 1843 1844 switch (sc->msk_hw_id) { 1845 case CHIP_ID_YUKON_EC: 1846 sc->msk_clock = 125; /* 125 MHz */ 1847 sc->msk_pflags |= MSK_FLAG_JUMBO; 1848 break; 1849 case CHIP_ID_YUKON_EC_U: 1850 sc->msk_clock = 125; /* 125 MHz */ 1851 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM; 1852 break; 1853 case CHIP_ID_YUKON_EX: 1854 sc->msk_clock = 125; /* 125 MHz */ 1855 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1856 MSK_FLAG_AUTOTX_CSUM; 1857 /* 1858 * Yukon Extreme seems to have silicon bug for 1859 * automatic Tx checksum calculation capability. 1860 */ 1861 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 1862 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM; 1863 /* 1864 * Yukon Extreme A0 could not use store-and-forward 1865 * for jumbo frames, so disable Tx checksum 1866 * offloading for jumbo frames. 1867 */ 1868 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 1869 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM; 1870 break; 1871 case CHIP_ID_YUKON_FE: 1872 sc->msk_clock = 100; /* 100 MHz */ 1873 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1874 break; 1875 case CHIP_ID_YUKON_FE_P: 1876 sc->msk_clock = 50; /* 50 MHz */ 1877 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 | 1878 MSK_FLAG_AUTOTX_CSUM; 1879 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 1880 /* 1881 * XXX 1882 * FE+ A0 has status LE writeback bug so msk(4) 1883 * does not rely on status word of received frame 1884 * in msk_rxeof() which in turn disables all 1885 * hardware assistance bits reported by the status 1886 * word as well as validity of the received frame. 1887 * Just pass received frames to upper stack with 1888 * minimal test and let upper stack handle them. 1889 */ 1890 sc->msk_pflags |= MSK_FLAG_NOHWVLAN | 1891 MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM; 1892 } 1893 break; 1894 case CHIP_ID_YUKON_XL: 1895 sc->msk_clock = 156; /* 156 MHz */ 1896 sc->msk_pflags |= MSK_FLAG_JUMBO; 1897 break; 1898 case CHIP_ID_YUKON_SUPR: 1899 sc->msk_clock = 125; /* 125 MHz */ 1900 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1901 MSK_FLAG_AUTOTX_CSUM; 1902 break; 1903 case CHIP_ID_YUKON_UL_2: 1904 sc->msk_clock = 125; /* 125 MHz */ 1905 sc->msk_pflags |= MSK_FLAG_JUMBO; 1906 break; 1907 case CHIP_ID_YUKON_OPT: 1908 sc->msk_clock = 125; /* 125 MHz */ 1909 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2; 1910 break; 1911 default: 1912 sc->msk_clock = 156; /* 156 MHz */ 1913 break; 1914 } 1915 1916 /* Allocate IRQ resources. */ 1917 msic = pci_msi_count(dev); 1918 if (bootverbose) 1919 device_printf(dev, "MSI count : %d\n", msic); 1920 if (legacy_intr != 0) 1921 msi_disable = 1; 1922 if (msi_disable == 0 && msic > 0) { 1923 msir = 1; 1924 if (pci_alloc_msi(dev, &msir) == 0) { 1925 if (msir == 1) { 1926 sc->msk_pflags |= MSK_FLAG_MSI; 1927 sc->msk_irq_spec = msk_irq_spec_msi; 1928 } else 1929 pci_release_msi(dev); 1930 } 1931 } 1932 1933 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1934 if (error) { 1935 device_printf(dev, "couldn't allocate IRQ resources\n"); 1936 goto fail; 1937 } 1938 1939 if ((error = msk_status_dma_alloc(sc)) != 0) 1940 goto fail; 1941 1942 /* Set base interrupt mask. */ 1943 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1944 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1945 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1946 1947 /* Reset the adapter. */ 1948 mskc_reset(sc); 1949 1950 if ((error = mskc_setup_rambuffer(sc)) != 0) 1951 goto fail; 1952 1953 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1954 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1955 device_printf(dev, "failed to add child for PORT_A\n"); 1956 error = ENXIO; 1957 goto fail; 1958 } 1959 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1960 mmd->port = MSK_PORT_A; 1961 mmd->pmd = sc->msk_pmd; 1962 mmd->mii_flags |= MIIF_DOPAUSE; 1963 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1964 mmd->mii_flags |= MIIF_HAVEFIBER; 1965 if (sc->msk_pmd == 'P') 1966 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1967 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd); 1968 1969 if (sc->msk_num_port > 1) { 1970 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1971 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1972 device_printf(dev, "failed to add child for PORT_B\n"); 1973 error = ENXIO; 1974 goto fail; 1975 } 1976 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | 1977 M_ZERO); 1978 mmd->port = MSK_PORT_B; 1979 mmd->pmd = sc->msk_pmd; 1980 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1981 mmd->mii_flags |= MIIF_HAVEFIBER; 1982 if (sc->msk_pmd == 'P') 1983 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1984 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd); 1985 } 1986 1987 error = bus_generic_attach(dev); 1988 if (error) { 1989 device_printf(dev, "failed to attach port(s)\n"); 1990 goto fail; 1991 } 1992 1993 /* Hook interrupt last to avoid having to lock softc. */ 1994 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1995 INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand); 1996 if (error != 0) { 1997 device_printf(dev, "couldn't set up interrupt handler\n"); 1998 goto fail; 1999 } 2000 fail: 2001 if (error != 0) 2002 mskc_detach(dev); 2003 2004 return (error); 2005 } 2006 2007 /* 2008 * Shutdown hardware and free up resources. This can be called any 2009 * time after the mutex has been initialized. It is called in both 2010 * the error case in attach and the normal detach case so it needs 2011 * to be careful about only freeing resources that have actually been 2012 * allocated. 2013 */ 2014 static int 2015 msk_detach(device_t dev) 2016 { 2017 struct msk_softc *sc; 2018 struct msk_if_softc *sc_if; 2019 struct ifnet *ifp; 2020 2021 sc_if = device_get_softc(dev); 2022 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 2023 ("msk mutex not initialized in msk_detach")); 2024 MSK_IF_LOCK(sc_if); 2025 2026 ifp = sc_if->msk_ifp; 2027 if (device_is_attached(dev)) { 2028 /* XXX */ 2029 sc_if->msk_flags |= MSK_FLAG_DETACH; 2030 msk_stop(sc_if); 2031 /* Can't hold locks while calling detach. */ 2032 MSK_IF_UNLOCK(sc_if); 2033 callout_drain(&sc_if->msk_tick_ch); 2034 if (ifp) 2035 ether_ifdetach(ifp); 2036 MSK_IF_LOCK(sc_if); 2037 } 2038 2039 /* 2040 * We're generally called from mskc_detach() which is using 2041 * device_delete_child() to get to here. It's already trashed 2042 * miibus for us, so don't do it here or we'll panic. 2043 * 2044 * if (sc_if->msk_miibus != NULL) { 2045 * device_delete_child(dev, sc_if->msk_miibus); 2046 * sc_if->msk_miibus = NULL; 2047 * } 2048 */ 2049 2050 msk_rx_dma_jfree(sc_if); 2051 msk_txrx_dma_free(sc_if); 2052 bus_generic_detach(dev); 2053 2054 sc = sc_if->msk_softc; 2055 sc->msk_if[sc_if->msk_port] = NULL; 2056 MSK_IF_UNLOCK(sc_if); 2057 if (ifp) 2058 if_free(ifp); 2059 2060 return (0); 2061 } 2062 2063 static int 2064 mskc_detach(device_t dev) 2065 { 2066 struct msk_softc *sc; 2067 2068 sc = device_get_softc(dev); 2069 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 2070 2071 if (device_is_alive(dev)) { 2072 if (sc->msk_devs[MSK_PORT_A] != NULL) { 2073 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 2074 M_DEVBUF); 2075 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 2076 } 2077 if (sc->msk_devs[MSK_PORT_B] != NULL) { 2078 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 2079 M_DEVBUF); 2080 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 2081 } 2082 bus_generic_detach(dev); 2083 } 2084 2085 /* Disable all interrupts. */ 2086 CSR_WRITE_4(sc, B0_IMSK, 0); 2087 CSR_READ_4(sc, B0_IMSK); 2088 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2089 CSR_READ_4(sc, B0_HWE_IMSK); 2090 2091 /* LED Off. */ 2092 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 2093 2094 /* Put hardware reset. */ 2095 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2096 2097 msk_status_dma_free(sc); 2098 2099 if (sc->msk_intrhand) { 2100 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand); 2101 sc->msk_intrhand = NULL; 2102 } 2103 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 2104 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0) 2105 pci_release_msi(dev); 2106 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 2107 mtx_destroy(&sc->msk_mtx); 2108 2109 return (0); 2110 } 2111 2112 static bus_dma_tag_t 2113 mskc_get_dma_tag(device_t bus, device_t child __unused) 2114 { 2115 2116 return (bus_get_dma_tag(bus)); 2117 } 2118 2119 struct msk_dmamap_arg { 2120 bus_addr_t msk_busaddr; 2121 }; 2122 2123 static void 2124 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2125 { 2126 struct msk_dmamap_arg *ctx; 2127 2128 if (error != 0) 2129 return; 2130 ctx = arg; 2131 ctx->msk_busaddr = segs[0].ds_addr; 2132 } 2133 2134 /* Create status DMA region. */ 2135 static int 2136 msk_status_dma_alloc(struct msk_softc *sc) 2137 { 2138 struct msk_dmamap_arg ctx; 2139 bus_size_t stat_sz; 2140 int count, error; 2141 2142 /* 2143 * It seems controller requires number of status LE entries 2144 * is power of 2 and the maximum number of status LE entries 2145 * is 4096. For dual-port controllers, the number of status 2146 * LE entries should be large enough to hold both port's 2147 * status updates. 2148 */ 2149 count = 3 * MSK_RX_RING_CNT + MSK_TX_RING_CNT; 2150 count = imin(4096, roundup2(count, 1024)); 2151 sc->msk_stat_count = count; 2152 stat_sz = count * sizeof(struct msk_stat_desc); 2153 error = bus_dma_tag_create( 2154 bus_get_dma_tag(sc->msk_dev), /* parent */ 2155 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 2156 BUS_SPACE_MAXADDR, /* lowaddr */ 2157 BUS_SPACE_MAXADDR, /* highaddr */ 2158 NULL, NULL, /* filter, filterarg */ 2159 stat_sz, /* maxsize */ 2160 1, /* nsegments */ 2161 stat_sz, /* maxsegsize */ 2162 0, /* flags */ 2163 NULL, NULL, /* lockfunc, lockarg */ 2164 &sc->msk_stat_tag); 2165 if (error != 0) { 2166 device_printf(sc->msk_dev, 2167 "failed to create status DMA tag\n"); 2168 return (error); 2169 } 2170 2171 /* Allocate DMA'able memory and load the DMA map for status ring. */ 2172 error = bus_dmamem_alloc(sc->msk_stat_tag, 2173 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 2174 BUS_DMA_ZERO, &sc->msk_stat_map); 2175 if (error != 0) { 2176 device_printf(sc->msk_dev, 2177 "failed to allocate DMA'able memory for status ring\n"); 2178 return (error); 2179 } 2180 2181 ctx.msk_busaddr = 0; 2182 error = bus_dmamap_load(sc->msk_stat_tag, sc->msk_stat_map, 2183 sc->msk_stat_ring, stat_sz, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2184 if (error != 0) { 2185 device_printf(sc->msk_dev, 2186 "failed to load DMA'able memory for status ring\n"); 2187 return (error); 2188 } 2189 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 2190 2191 return (0); 2192 } 2193 2194 static void 2195 msk_status_dma_free(struct msk_softc *sc) 2196 { 2197 2198 /* Destroy status block. */ 2199 if (sc->msk_stat_tag) { 2200 if (sc->msk_stat_ring_paddr) { 2201 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 2202 sc->msk_stat_ring_paddr = 0; 2203 } 2204 if (sc->msk_stat_ring) { 2205 bus_dmamem_free(sc->msk_stat_tag, 2206 sc->msk_stat_ring, sc->msk_stat_map); 2207 sc->msk_stat_ring = NULL; 2208 } 2209 bus_dma_tag_destroy(sc->msk_stat_tag); 2210 sc->msk_stat_tag = NULL; 2211 } 2212 } 2213 2214 static int 2215 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 2216 { 2217 struct msk_dmamap_arg ctx; 2218 struct msk_txdesc *txd; 2219 struct msk_rxdesc *rxd; 2220 bus_size_t rxalign; 2221 int error, i; 2222 2223 /* Create parent DMA tag. */ 2224 error = bus_dma_tag_create( 2225 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2226 1, 0, /* alignment, boundary */ 2227 BUS_SPACE_MAXADDR, /* lowaddr */ 2228 BUS_SPACE_MAXADDR, /* highaddr */ 2229 NULL, NULL, /* filter, filterarg */ 2230 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2231 0, /* nsegments */ 2232 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2233 0, /* flags */ 2234 NULL, NULL, /* lockfunc, lockarg */ 2235 &sc_if->msk_cdata.msk_parent_tag); 2236 if (error != 0) { 2237 device_printf(sc_if->msk_if_dev, 2238 "failed to create parent DMA tag\n"); 2239 goto fail; 2240 } 2241 /* Create tag for Tx ring. */ 2242 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2243 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2244 BUS_SPACE_MAXADDR, /* lowaddr */ 2245 BUS_SPACE_MAXADDR, /* highaddr */ 2246 NULL, NULL, /* filter, filterarg */ 2247 MSK_TX_RING_SZ, /* maxsize */ 2248 1, /* nsegments */ 2249 MSK_TX_RING_SZ, /* maxsegsize */ 2250 0, /* flags */ 2251 NULL, NULL, /* lockfunc, lockarg */ 2252 &sc_if->msk_cdata.msk_tx_ring_tag); 2253 if (error != 0) { 2254 device_printf(sc_if->msk_if_dev, 2255 "failed to create Tx ring DMA tag\n"); 2256 goto fail; 2257 } 2258 2259 /* Create tag for Rx ring. */ 2260 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2261 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2262 BUS_SPACE_MAXADDR, /* lowaddr */ 2263 BUS_SPACE_MAXADDR, /* highaddr */ 2264 NULL, NULL, /* filter, filterarg */ 2265 MSK_RX_RING_SZ, /* maxsize */ 2266 1, /* nsegments */ 2267 MSK_RX_RING_SZ, /* maxsegsize */ 2268 0, /* flags */ 2269 NULL, NULL, /* lockfunc, lockarg */ 2270 &sc_if->msk_cdata.msk_rx_ring_tag); 2271 if (error != 0) { 2272 device_printf(sc_if->msk_if_dev, 2273 "failed to create Rx ring DMA tag\n"); 2274 goto fail; 2275 } 2276 2277 /* Create tag for Tx buffers. */ 2278 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2279 1, 0, /* alignment, boundary */ 2280 BUS_SPACE_MAXADDR, /* lowaddr */ 2281 BUS_SPACE_MAXADDR, /* highaddr */ 2282 NULL, NULL, /* filter, filterarg */ 2283 MSK_TSO_MAXSIZE, /* maxsize */ 2284 MSK_MAXTXSEGS, /* nsegments */ 2285 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2286 0, /* flags */ 2287 NULL, NULL, /* lockfunc, lockarg */ 2288 &sc_if->msk_cdata.msk_tx_tag); 2289 if (error != 0) { 2290 device_printf(sc_if->msk_if_dev, 2291 "failed to create Tx DMA tag\n"); 2292 goto fail; 2293 } 2294 2295 rxalign = 1; 2296 /* 2297 * Workaround hardware hang which seems to happen when Rx buffer 2298 * is not aligned on multiple of FIFO word(8 bytes). 2299 */ 2300 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2301 rxalign = MSK_RX_BUF_ALIGN; 2302 /* Create tag for Rx buffers. */ 2303 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2304 rxalign, 0, /* alignment, boundary */ 2305 BUS_SPACE_MAXADDR, /* lowaddr */ 2306 BUS_SPACE_MAXADDR, /* highaddr */ 2307 NULL, NULL, /* filter, filterarg */ 2308 MCLBYTES, /* maxsize */ 2309 1, /* nsegments */ 2310 MCLBYTES, /* maxsegsize */ 2311 0, /* flags */ 2312 NULL, NULL, /* lockfunc, lockarg */ 2313 &sc_if->msk_cdata.msk_rx_tag); 2314 if (error != 0) { 2315 device_printf(sc_if->msk_if_dev, 2316 "failed to create Rx DMA tag\n"); 2317 goto fail; 2318 } 2319 2320 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2321 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2322 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2323 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2324 if (error != 0) { 2325 device_printf(sc_if->msk_if_dev, 2326 "failed to allocate DMA'able memory for Tx ring\n"); 2327 goto fail; 2328 } 2329 2330 ctx.msk_busaddr = 0; 2331 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2332 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2333 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2334 if (error != 0) { 2335 device_printf(sc_if->msk_if_dev, 2336 "failed to load DMA'able memory for Tx ring\n"); 2337 goto fail; 2338 } 2339 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2340 2341 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2342 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2343 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2344 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2345 if (error != 0) { 2346 device_printf(sc_if->msk_if_dev, 2347 "failed to allocate DMA'able memory for Rx ring\n"); 2348 goto fail; 2349 } 2350 2351 ctx.msk_busaddr = 0; 2352 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2353 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2354 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2355 if (error != 0) { 2356 device_printf(sc_if->msk_if_dev, 2357 "failed to load DMA'able memory for Rx ring\n"); 2358 goto fail; 2359 } 2360 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2361 2362 /* Create DMA maps for Tx buffers. */ 2363 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2364 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2365 txd->tx_m = NULL; 2366 txd->tx_dmamap = NULL; 2367 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2368 &txd->tx_dmamap); 2369 if (error != 0) { 2370 device_printf(sc_if->msk_if_dev, 2371 "failed to create Tx dmamap\n"); 2372 goto fail; 2373 } 2374 } 2375 /* Create DMA maps for Rx buffers. */ 2376 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2377 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2378 device_printf(sc_if->msk_if_dev, 2379 "failed to create spare Rx dmamap\n"); 2380 goto fail; 2381 } 2382 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2383 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2384 rxd->rx_m = NULL; 2385 rxd->rx_dmamap = NULL; 2386 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2387 &rxd->rx_dmamap); 2388 if (error != 0) { 2389 device_printf(sc_if->msk_if_dev, 2390 "failed to create Rx dmamap\n"); 2391 goto fail; 2392 } 2393 } 2394 2395 fail: 2396 return (error); 2397 } 2398 2399 static int 2400 msk_rx_dma_jalloc(struct msk_if_softc *sc_if) 2401 { 2402 struct msk_dmamap_arg ctx; 2403 struct msk_rxdesc *jrxd; 2404 bus_size_t rxalign; 2405 int error, i; 2406 2407 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 2408 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2409 device_printf(sc_if->msk_if_dev, 2410 "disabling jumbo frame support\n"); 2411 return (0); 2412 } 2413 /* Create tag for jumbo Rx ring. */ 2414 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2415 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2416 BUS_SPACE_MAXADDR, /* lowaddr */ 2417 BUS_SPACE_MAXADDR, /* highaddr */ 2418 NULL, NULL, /* filter, filterarg */ 2419 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2420 1, /* nsegments */ 2421 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2422 0, /* flags */ 2423 NULL, NULL, /* lockfunc, lockarg */ 2424 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2425 if (error != 0) { 2426 device_printf(sc_if->msk_if_dev, 2427 "failed to create jumbo Rx ring DMA tag\n"); 2428 goto jumbo_fail; 2429 } 2430 2431 rxalign = 1; 2432 /* 2433 * Workaround hardware hang which seems to happen when Rx buffer 2434 * is not aligned on multiple of FIFO word(8 bytes). 2435 */ 2436 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2437 rxalign = MSK_RX_BUF_ALIGN; 2438 /* Create tag for jumbo Rx buffers. */ 2439 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2440 rxalign, 0, /* alignment, boundary */ 2441 BUS_SPACE_MAXADDR, /* lowaddr */ 2442 BUS_SPACE_MAXADDR, /* highaddr */ 2443 NULL, NULL, /* filter, filterarg */ 2444 MJUM9BYTES, /* maxsize */ 2445 1, /* nsegments */ 2446 MJUM9BYTES, /* maxsegsize */ 2447 0, /* flags */ 2448 NULL, NULL, /* lockfunc, lockarg */ 2449 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2450 if (error != 0) { 2451 device_printf(sc_if->msk_if_dev, 2452 "failed to create jumbo Rx DMA tag\n"); 2453 goto jumbo_fail; 2454 } 2455 2456 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2457 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2458 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2459 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2460 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2461 if (error != 0) { 2462 device_printf(sc_if->msk_if_dev, 2463 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2464 goto jumbo_fail; 2465 } 2466 2467 ctx.msk_busaddr = 0; 2468 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2469 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2470 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2471 msk_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 2472 if (error != 0) { 2473 device_printf(sc_if->msk_if_dev, 2474 "failed to load DMA'able memory for jumbo Rx ring\n"); 2475 goto jumbo_fail; 2476 } 2477 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2478 2479 /* Create DMA maps for jumbo Rx buffers. */ 2480 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2481 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2482 device_printf(sc_if->msk_if_dev, 2483 "failed to create spare jumbo Rx dmamap\n"); 2484 goto jumbo_fail; 2485 } 2486 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2487 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2488 jrxd->rx_m = NULL; 2489 jrxd->rx_dmamap = NULL; 2490 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2491 &jrxd->rx_dmamap); 2492 if (error != 0) { 2493 device_printf(sc_if->msk_if_dev, 2494 "failed to create jumbo Rx dmamap\n"); 2495 goto jumbo_fail; 2496 } 2497 } 2498 2499 return (0); 2500 2501 jumbo_fail: 2502 msk_rx_dma_jfree(sc_if); 2503 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support " 2504 "due to resource shortage\n"); 2505 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2506 return (error); 2507 } 2508 2509 static void 2510 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2511 { 2512 struct msk_txdesc *txd; 2513 struct msk_rxdesc *rxd; 2514 int i; 2515 2516 /* Tx ring. */ 2517 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2518 if (sc_if->msk_rdata.msk_tx_ring_paddr) 2519 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2520 sc_if->msk_cdata.msk_tx_ring_map); 2521 if (sc_if->msk_rdata.msk_tx_ring) 2522 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2523 sc_if->msk_rdata.msk_tx_ring, 2524 sc_if->msk_cdata.msk_tx_ring_map); 2525 sc_if->msk_rdata.msk_tx_ring = NULL; 2526 sc_if->msk_rdata.msk_tx_ring_paddr = 0; 2527 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2528 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2529 } 2530 /* Rx ring. */ 2531 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2532 if (sc_if->msk_rdata.msk_rx_ring_paddr) 2533 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2534 sc_if->msk_cdata.msk_rx_ring_map); 2535 if (sc_if->msk_rdata.msk_rx_ring) 2536 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2537 sc_if->msk_rdata.msk_rx_ring, 2538 sc_if->msk_cdata.msk_rx_ring_map); 2539 sc_if->msk_rdata.msk_rx_ring = NULL; 2540 sc_if->msk_rdata.msk_rx_ring_paddr = 0; 2541 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2542 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2543 } 2544 /* Tx buffers. */ 2545 if (sc_if->msk_cdata.msk_tx_tag) { 2546 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2547 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2548 if (txd->tx_dmamap) { 2549 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2550 txd->tx_dmamap); 2551 txd->tx_dmamap = NULL; 2552 } 2553 } 2554 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2555 sc_if->msk_cdata.msk_tx_tag = NULL; 2556 } 2557 /* Rx buffers. */ 2558 if (sc_if->msk_cdata.msk_rx_tag) { 2559 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2560 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2561 if (rxd->rx_dmamap) { 2562 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2563 rxd->rx_dmamap); 2564 rxd->rx_dmamap = NULL; 2565 } 2566 } 2567 if (sc_if->msk_cdata.msk_rx_sparemap) { 2568 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2569 sc_if->msk_cdata.msk_rx_sparemap); 2570 sc_if->msk_cdata.msk_rx_sparemap = 0; 2571 } 2572 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2573 sc_if->msk_cdata.msk_rx_tag = NULL; 2574 } 2575 if (sc_if->msk_cdata.msk_parent_tag) { 2576 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2577 sc_if->msk_cdata.msk_parent_tag = NULL; 2578 } 2579 } 2580 2581 static void 2582 msk_rx_dma_jfree(struct msk_if_softc *sc_if) 2583 { 2584 struct msk_rxdesc *jrxd; 2585 int i; 2586 2587 /* Jumbo Rx ring. */ 2588 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2589 if (sc_if->msk_rdata.msk_jumbo_rx_ring_paddr) 2590 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2591 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2592 if (sc_if->msk_rdata.msk_jumbo_rx_ring) 2593 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2594 sc_if->msk_rdata.msk_jumbo_rx_ring, 2595 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2596 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2597 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = 0; 2598 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2599 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2600 } 2601 /* Jumbo Rx buffers. */ 2602 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2603 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2604 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2605 if (jrxd->rx_dmamap) { 2606 bus_dmamap_destroy( 2607 sc_if->msk_cdata.msk_jumbo_rx_tag, 2608 jrxd->rx_dmamap); 2609 jrxd->rx_dmamap = NULL; 2610 } 2611 } 2612 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2613 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2614 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2615 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2616 } 2617 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2618 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2619 } 2620 } 2621 2622 static int 2623 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2624 { 2625 struct msk_txdesc *txd, *txd_last; 2626 struct msk_tx_desc *tx_le; 2627 struct mbuf *m; 2628 bus_dmamap_t map; 2629 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2630 uint32_t control, csum, prod, si; 2631 uint16_t offset, tcp_offset, tso_mtu; 2632 int error, i, nseg, tso; 2633 2634 MSK_IF_LOCK_ASSERT(sc_if); 2635 2636 tcp_offset = offset = 0; 2637 m = *m_head; 2638 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2639 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) || 2640 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 2641 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) { 2642 /* 2643 * Since mbuf has no protocol specific structure information 2644 * in it we have to inspect protocol information here to 2645 * setup TSO and checksum offload. I don't know why Marvell 2646 * made a such decision in chip design because other GigE 2647 * hardwares normally takes care of all these chores in 2648 * hardware. However, TSO performance of Yukon II is very 2649 * good such that it's worth to implement it. 2650 */ 2651 struct ether_header *eh; 2652 struct ip *ip; 2653 struct tcphdr *tcp; 2654 2655 if (M_WRITABLE(m) == 0) { 2656 /* Get a writable copy. */ 2657 m = m_dup(*m_head, M_NOWAIT); 2658 m_freem(*m_head); 2659 if (m == NULL) { 2660 *m_head = NULL; 2661 return (ENOBUFS); 2662 } 2663 *m_head = m; 2664 } 2665 2666 offset = sizeof(struct ether_header); 2667 m = m_pullup(m, offset); 2668 if (m == NULL) { 2669 *m_head = NULL; 2670 return (ENOBUFS); 2671 } 2672 eh = mtod(m, struct ether_header *); 2673 /* Check if hardware VLAN insertion is off. */ 2674 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2675 offset = sizeof(struct ether_vlan_header); 2676 m = m_pullup(m, offset); 2677 if (m == NULL) { 2678 *m_head = NULL; 2679 return (ENOBUFS); 2680 } 2681 } 2682 m = m_pullup(m, offset + sizeof(struct ip)); 2683 if (m == NULL) { 2684 *m_head = NULL; 2685 return (ENOBUFS); 2686 } 2687 ip = (struct ip *)(mtod(m, char *) + offset); 2688 offset += (ip->ip_hl << 2); 2689 tcp_offset = offset; 2690 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2691 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2692 if (m == NULL) { 2693 *m_head = NULL; 2694 return (ENOBUFS); 2695 } 2696 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2697 offset += (tcp->th_off << 2); 2698 } else if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2699 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) && 2700 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2701 /* 2702 * It seems that Yukon II has Tx checksum offload bug 2703 * for small TCP packets that's less than 60 bytes in 2704 * size (e.g. TCP window probe packet, pure ACK packet). 2705 * Common work around like padding with zeros to make 2706 * the frame minimum ethernet frame size didn't work at 2707 * all. 2708 * Instead of disabling checksum offload completely we 2709 * resort to S/W checksum routine when we encounter 2710 * short TCP frames. 2711 * Short UDP packets appear to be handled correctly by 2712 * Yukon II. Also I assume this bug does not happen on 2713 * controllers that use newer descriptor format or 2714 * automatic Tx checksum calculation. 2715 */ 2716 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2717 if (m == NULL) { 2718 *m_head = NULL; 2719 return (ENOBUFS); 2720 } 2721 *(uint16_t *)(m->m_data + offset + 2722 m->m_pkthdr.csum_data) = in_cksum_skip(m, 2723 m->m_pkthdr.len, offset); 2724 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2725 } 2726 *m_head = m; 2727 } 2728 2729 prod = sc_if->msk_cdata.msk_tx_prod; 2730 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2731 txd_last = txd; 2732 map = txd->tx_dmamap; 2733 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2734 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2735 if (error == EFBIG) { 2736 m = m_collapse(*m_head, M_NOWAIT, MSK_MAXTXSEGS); 2737 if (m == NULL) { 2738 m_freem(*m_head); 2739 *m_head = NULL; 2740 return (ENOBUFS); 2741 } 2742 *m_head = m; 2743 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2744 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2745 if (error != 0) { 2746 m_freem(*m_head); 2747 *m_head = NULL; 2748 return (error); 2749 } 2750 } else if (error != 0) 2751 return (error); 2752 if (nseg == 0) { 2753 m_freem(*m_head); 2754 *m_head = NULL; 2755 return (EIO); 2756 } 2757 2758 /* Check number of available descriptors. */ 2759 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2760 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2761 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2762 return (ENOBUFS); 2763 } 2764 2765 control = 0; 2766 tso = 0; 2767 tx_le = NULL; 2768 2769 /* Check TSO support. */ 2770 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2771 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2772 tso_mtu = m->m_pkthdr.tso_segsz; 2773 else 2774 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2775 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2776 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2777 tx_le->msk_addr = htole32(tso_mtu); 2778 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2779 tx_le->msk_control = htole32(OP_MSS | HW_OWNER); 2780 else 2781 tx_le->msk_control = 2782 htole32(OP_LRGLEN | HW_OWNER); 2783 sc_if->msk_cdata.msk_tx_cnt++; 2784 MSK_INC(prod, MSK_TX_RING_CNT); 2785 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2786 } 2787 tso++; 2788 } 2789 /* Check if we have a VLAN tag to insert. */ 2790 if ((m->m_flags & M_VLANTAG) != 0) { 2791 if (tx_le == NULL) { 2792 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2793 tx_le->msk_addr = htole32(0); 2794 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2795 htons(m->m_pkthdr.ether_vtag)); 2796 sc_if->msk_cdata.msk_tx_cnt++; 2797 MSK_INC(prod, MSK_TX_RING_CNT); 2798 } else { 2799 tx_le->msk_control |= htole32(OP_VLAN | 2800 htons(m->m_pkthdr.ether_vtag)); 2801 } 2802 control |= INS_VLAN; 2803 } 2804 /* Check if we have to handle checksum offload. */ 2805 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2806 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0) 2807 control |= CALSUM; 2808 else { 2809 control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2810 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2811 control |= UDPTCP; 2812 /* Checksum write position. */ 2813 csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff; 2814 /* Checksum start position. */ 2815 csum |= (uint32_t)tcp_offset << 16; 2816 if (csum != sc_if->msk_cdata.msk_last_csum) { 2817 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2818 tx_le->msk_addr = htole32(csum); 2819 tx_le->msk_control = htole32(1 << 16 | 2820 (OP_TCPLISW | HW_OWNER)); 2821 sc_if->msk_cdata.msk_tx_cnt++; 2822 MSK_INC(prod, MSK_TX_RING_CNT); 2823 sc_if->msk_cdata.msk_last_csum = csum; 2824 } 2825 } 2826 } 2827 2828 #ifdef MSK_64BIT_DMA 2829 if (MSK_ADDR_HI(txsegs[0].ds_addr) != 2830 sc_if->msk_cdata.msk_tx_high_addr) { 2831 sc_if->msk_cdata.msk_tx_high_addr = 2832 MSK_ADDR_HI(txsegs[0].ds_addr); 2833 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2834 tx_le->msk_addr = htole32(MSK_ADDR_HI(txsegs[0].ds_addr)); 2835 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 2836 sc_if->msk_cdata.msk_tx_cnt++; 2837 MSK_INC(prod, MSK_TX_RING_CNT); 2838 } 2839 #endif 2840 si = prod; 2841 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2842 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2843 if (tso == 0) 2844 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2845 OP_PACKET); 2846 else 2847 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2848 OP_LARGESEND); 2849 sc_if->msk_cdata.msk_tx_cnt++; 2850 MSK_INC(prod, MSK_TX_RING_CNT); 2851 2852 for (i = 1; i < nseg; i++) { 2853 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2854 #ifdef MSK_64BIT_DMA 2855 if (MSK_ADDR_HI(txsegs[i].ds_addr) != 2856 sc_if->msk_cdata.msk_tx_high_addr) { 2857 sc_if->msk_cdata.msk_tx_high_addr = 2858 MSK_ADDR_HI(txsegs[i].ds_addr); 2859 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2860 tx_le->msk_addr = 2861 htole32(MSK_ADDR_HI(txsegs[i].ds_addr)); 2862 tx_le->msk_control = htole32(OP_ADDR64 | HW_OWNER); 2863 sc_if->msk_cdata.msk_tx_cnt++; 2864 MSK_INC(prod, MSK_TX_RING_CNT); 2865 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2866 } 2867 #endif 2868 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2869 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2870 OP_BUFFER | HW_OWNER); 2871 sc_if->msk_cdata.msk_tx_cnt++; 2872 MSK_INC(prod, MSK_TX_RING_CNT); 2873 } 2874 /* Update producer index. */ 2875 sc_if->msk_cdata.msk_tx_prod = prod; 2876 2877 /* Set EOP on the last descriptor. */ 2878 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2879 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2880 tx_le->msk_control |= htole32(EOP); 2881 2882 /* Turn the first descriptor ownership to hardware. */ 2883 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2884 tx_le->msk_control |= htole32(HW_OWNER); 2885 2886 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2887 map = txd_last->tx_dmamap; 2888 txd_last->tx_dmamap = txd->tx_dmamap; 2889 txd->tx_dmamap = map; 2890 txd->tx_m = m; 2891 2892 /* Sync descriptors. */ 2893 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2894 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2895 sc_if->msk_cdata.msk_tx_ring_map, 2896 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2897 2898 return (0); 2899 } 2900 2901 static void 2902 msk_start(struct ifnet *ifp) 2903 { 2904 struct msk_if_softc *sc_if; 2905 2906 sc_if = ifp->if_softc; 2907 MSK_IF_LOCK(sc_if); 2908 msk_start_locked(ifp); 2909 MSK_IF_UNLOCK(sc_if); 2910 } 2911 2912 static void 2913 msk_start_locked(struct ifnet *ifp) 2914 { 2915 struct msk_if_softc *sc_if; 2916 struct mbuf *m_head; 2917 int enq; 2918 2919 sc_if = ifp->if_softc; 2920 MSK_IF_LOCK_ASSERT(sc_if); 2921 2922 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2923 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0) 2924 return; 2925 2926 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2927 sc_if->msk_cdata.msk_tx_cnt < 2928 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2929 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2930 if (m_head == NULL) 2931 break; 2932 /* 2933 * Pack the data into the transmit ring. If we 2934 * don't have room, set the OACTIVE flag and wait 2935 * for the NIC to drain the ring. 2936 */ 2937 if (msk_encap(sc_if, &m_head) != 0) { 2938 if (m_head == NULL) 2939 break; 2940 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2941 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2942 break; 2943 } 2944 2945 enq++; 2946 /* 2947 * If there's a BPF listener, bounce a copy of this frame 2948 * to him. 2949 */ 2950 ETHER_BPF_MTAP(ifp, m_head); 2951 } 2952 2953 if (enq > 0) { 2954 /* Transmit */ 2955 CSR_WRITE_2(sc_if->msk_softc, 2956 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2957 sc_if->msk_cdata.msk_tx_prod); 2958 2959 /* Set a timeout in case the chip goes out to lunch. */ 2960 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2961 } 2962 } 2963 2964 static void 2965 msk_watchdog(struct msk_if_softc *sc_if) 2966 { 2967 struct ifnet *ifp; 2968 2969 MSK_IF_LOCK_ASSERT(sc_if); 2970 2971 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2972 return; 2973 ifp = sc_if->msk_ifp; 2974 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) { 2975 if (bootverbose) 2976 if_printf(sc_if->msk_ifp, "watchdog timeout " 2977 "(missed link)\n"); 2978 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2979 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2980 msk_init_locked(sc_if); 2981 return; 2982 } 2983 2984 if_printf(ifp, "watchdog timeout\n"); 2985 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2986 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2987 msk_init_locked(sc_if); 2988 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2989 msk_start_locked(ifp); 2990 } 2991 2992 static int 2993 mskc_shutdown(device_t dev) 2994 { 2995 struct msk_softc *sc; 2996 int i; 2997 2998 sc = device_get_softc(dev); 2999 MSK_LOCK(sc); 3000 for (i = 0; i < sc->msk_num_port; i++) { 3001 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 3002 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 3003 IFF_DRV_RUNNING) != 0)) 3004 msk_stop(sc->msk_if[i]); 3005 } 3006 MSK_UNLOCK(sc); 3007 3008 /* Put hardware reset. */ 3009 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 3010 return (0); 3011 } 3012 3013 static int 3014 mskc_suspend(device_t dev) 3015 { 3016 struct msk_softc *sc; 3017 int i; 3018 3019 sc = device_get_softc(dev); 3020 3021 MSK_LOCK(sc); 3022 3023 for (i = 0; i < sc->msk_num_port; i++) { 3024 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 3025 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 3026 IFF_DRV_RUNNING) != 0)) 3027 msk_stop(sc->msk_if[i]); 3028 } 3029 3030 /* Disable all interrupts. */ 3031 CSR_WRITE_4(sc, B0_IMSK, 0); 3032 CSR_READ_4(sc, B0_IMSK); 3033 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 3034 CSR_READ_4(sc, B0_HWE_IMSK); 3035 3036 msk_phy_power(sc, MSK_PHY_POWERDOWN); 3037 3038 /* Put hardware reset. */ 3039 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 3040 sc->msk_pflags |= MSK_FLAG_SUSPEND; 3041 3042 MSK_UNLOCK(sc); 3043 3044 return (0); 3045 } 3046 3047 static int 3048 mskc_resume(device_t dev) 3049 { 3050 struct msk_softc *sc; 3051 int i; 3052 3053 sc = device_get_softc(dev); 3054 3055 MSK_LOCK(sc); 3056 3057 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 3058 mskc_reset(sc); 3059 for (i = 0; i < sc->msk_num_port; i++) { 3060 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 3061 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) { 3062 sc->msk_if[i]->msk_ifp->if_drv_flags &= 3063 ~IFF_DRV_RUNNING; 3064 msk_init_locked(sc->msk_if[i]); 3065 } 3066 } 3067 sc->msk_pflags &= ~MSK_FLAG_SUSPEND; 3068 3069 MSK_UNLOCK(sc); 3070 3071 return (0); 3072 } 3073 3074 #ifndef __NO_STRICT_ALIGNMENT 3075 static __inline void 3076 msk_fixup_rx(struct mbuf *m) 3077 { 3078 int i; 3079 uint16_t *src, *dst; 3080 3081 src = mtod(m, uint16_t *); 3082 dst = src - 3; 3083 3084 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3085 *dst++ = *src++; 3086 3087 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN); 3088 } 3089 #endif 3090 3091 static __inline void 3092 msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m) 3093 { 3094 struct ether_header *eh; 3095 struct ip *ip; 3096 struct udphdr *uh; 3097 int32_t hlen, len, pktlen, temp32; 3098 uint16_t csum, *opts; 3099 3100 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) { 3101 if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) { 3102 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3103 if ((control & CSS_IPV4_CSUM_OK) != 0) 3104 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3105 if ((control & (CSS_TCP | CSS_UDP)) != 0 && 3106 (control & (CSS_TCPUDP_CSUM_OK)) != 0) { 3107 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3108 CSUM_PSEUDO_HDR; 3109 m->m_pkthdr.csum_data = 0xffff; 3110 } 3111 } 3112 return; 3113 } 3114 /* 3115 * Marvell Yukon controllers that support OP_RXCHKS has known 3116 * to have various Rx checksum offloading bugs. These 3117 * controllers can be configured to compute simple checksum 3118 * at two different positions. So we can compute IP and TCP/UDP 3119 * checksum at the same time. We intentionally have controller 3120 * compute TCP/UDP checksum twice by specifying the same 3121 * checksum start position and compare the result. If the value 3122 * is different it would indicate the hardware logic was wrong. 3123 */ 3124 if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) { 3125 if (bootverbose) 3126 device_printf(sc_if->msk_if_dev, 3127 "Rx checksum value mismatch!\n"); 3128 return; 3129 } 3130 pktlen = m->m_pkthdr.len; 3131 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 3132 return; 3133 eh = mtod(m, struct ether_header *); 3134 if (eh->ether_type != htons(ETHERTYPE_IP)) 3135 return; 3136 ip = (struct ip *)(eh + 1); 3137 if (ip->ip_v != IPVERSION) 3138 return; 3139 3140 hlen = ip->ip_hl << 2; 3141 pktlen -= sizeof(struct ether_header); 3142 if (hlen < sizeof(struct ip)) 3143 return; 3144 if (ntohs(ip->ip_len) < hlen) 3145 return; 3146 if (ntohs(ip->ip_len) != pktlen) 3147 return; 3148 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 3149 return; /* can't handle fragmented packet. */ 3150 3151 switch (ip->ip_p) { 3152 case IPPROTO_TCP: 3153 if (pktlen < (hlen + sizeof(struct tcphdr))) 3154 return; 3155 break; 3156 case IPPROTO_UDP: 3157 if (pktlen < (hlen + sizeof(struct udphdr))) 3158 return; 3159 uh = (struct udphdr *)((caddr_t)ip + hlen); 3160 if (uh->uh_sum == 0) 3161 return; /* no checksum */ 3162 break; 3163 default: 3164 return; 3165 } 3166 csum = bswap16(sc_if->msk_csum & 0xFFFF); 3167 /* Checksum fixup for IP options. */ 3168 len = hlen - sizeof(struct ip); 3169 if (len > 0) { 3170 opts = (uint16_t *)(ip + 1); 3171 for (; len > 0; len -= sizeof(uint16_t), opts++) { 3172 temp32 = csum - *opts; 3173 temp32 = (temp32 >> 16) + (temp32 & 65535); 3174 csum = temp32 & 65535; 3175 } 3176 } 3177 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 3178 m->m_pkthdr.csum_data = csum; 3179 } 3180 3181 static void 3182 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3183 int len) 3184 { 3185 struct mbuf *m; 3186 struct ifnet *ifp; 3187 struct msk_rxdesc *rxd; 3188 int cons, rxlen; 3189 3190 ifp = sc_if->msk_ifp; 3191 3192 MSK_IF_LOCK_ASSERT(sc_if); 3193 3194 cons = sc_if->msk_cdata.msk_rx_cons; 3195 do { 3196 rxlen = status >> 16; 3197 if ((status & GMR_FS_VLAN) != 0 && 3198 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3199 rxlen -= ETHER_VLAN_ENCAP_LEN; 3200 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) { 3201 /* 3202 * For controllers that returns bogus status code 3203 * just do minimal check and let upper stack 3204 * handle this frame. 3205 */ 3206 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) { 3207 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 3208 msk_discard_rxbuf(sc_if, cons); 3209 break; 3210 } 3211 } else if (len > sc_if->msk_framesize || 3212 ((status & GMR_FS_ANY_ERR) != 0) || 3213 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3214 /* Don't count flow-control packet as errors. */ 3215 if ((status & GMR_FS_GOOD_FC) == 0) 3216 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 3217 msk_discard_rxbuf(sc_if, cons); 3218 break; 3219 } 3220 #ifdef MSK_64BIT_DMA 3221 rxd = &sc_if->msk_cdata.msk_rxdesc[(cons + 1) % 3222 MSK_RX_RING_CNT]; 3223 #else 3224 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 3225 #endif 3226 m = rxd->rx_m; 3227 if (msk_newbuf(sc_if, cons) != 0) { 3228 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3229 /* Reuse old buffer. */ 3230 msk_discard_rxbuf(sc_if, cons); 3231 break; 3232 } 3233 m->m_pkthdr.rcvif = ifp; 3234 m->m_pkthdr.len = m->m_len = len; 3235 #ifndef __NO_STRICT_ALIGNMENT 3236 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3237 msk_fixup_rx(m); 3238 #endif 3239 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 3240 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3241 msk_rxcsum(sc_if, control, m); 3242 /* Check for VLAN tagged packets. */ 3243 if ((status & GMR_FS_VLAN) != 0 && 3244 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3245 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3246 m->m_flags |= M_VLANTAG; 3247 } 3248 MSK_IF_UNLOCK(sc_if); 3249 (*ifp->if_input)(ifp, m); 3250 MSK_IF_LOCK(sc_if); 3251 } while (0); 3252 3253 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 3254 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 3255 } 3256 3257 static void 3258 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3259 int len) 3260 { 3261 struct mbuf *m; 3262 struct ifnet *ifp; 3263 struct msk_rxdesc *jrxd; 3264 int cons, rxlen; 3265 3266 ifp = sc_if->msk_ifp; 3267 3268 MSK_IF_LOCK_ASSERT(sc_if); 3269 3270 cons = sc_if->msk_cdata.msk_rx_cons; 3271 do { 3272 rxlen = status >> 16; 3273 if ((status & GMR_FS_VLAN) != 0 && 3274 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3275 rxlen -= ETHER_VLAN_ENCAP_LEN; 3276 if (len > sc_if->msk_framesize || 3277 ((status & GMR_FS_ANY_ERR) != 0) || 3278 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3279 /* Don't count flow-control packet as errors. */ 3280 if ((status & GMR_FS_GOOD_FC) == 0) 3281 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 3282 msk_discard_jumbo_rxbuf(sc_if, cons); 3283 break; 3284 } 3285 #ifdef MSK_64BIT_DMA 3286 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[(cons + 1) % 3287 MSK_JUMBO_RX_RING_CNT]; 3288 #else 3289 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 3290 #endif 3291 m = jrxd->rx_m; 3292 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3293 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3294 /* Reuse old buffer. */ 3295 msk_discard_jumbo_rxbuf(sc_if, cons); 3296 break; 3297 } 3298 m->m_pkthdr.rcvif = ifp; 3299 m->m_pkthdr.len = m->m_len = len; 3300 #ifndef __NO_STRICT_ALIGNMENT 3301 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3302 msk_fixup_rx(m); 3303 #endif 3304 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 3305 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3306 msk_rxcsum(sc_if, control, m); 3307 /* Check for VLAN tagged packets. */ 3308 if ((status & GMR_FS_VLAN) != 0 && 3309 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3310 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3311 m->m_flags |= M_VLANTAG; 3312 } 3313 MSK_IF_UNLOCK(sc_if); 3314 (*ifp->if_input)(ifp, m); 3315 MSK_IF_LOCK(sc_if); 3316 } while (0); 3317 3318 MSK_RX_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3319 MSK_RX_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3320 } 3321 3322 static void 3323 msk_txeof(struct msk_if_softc *sc_if, int idx) 3324 { 3325 struct msk_txdesc *txd; 3326 struct msk_tx_desc *cur_tx; 3327 struct ifnet *ifp; 3328 uint32_t control; 3329 int cons, prog; 3330 3331 MSK_IF_LOCK_ASSERT(sc_if); 3332 3333 ifp = sc_if->msk_ifp; 3334 3335 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3336 sc_if->msk_cdata.msk_tx_ring_map, 3337 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3338 /* 3339 * Go through our tx ring and free mbufs for those 3340 * frames that have been sent. 3341 */ 3342 cons = sc_if->msk_cdata.msk_tx_cons; 3343 prog = 0; 3344 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3345 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3346 break; 3347 prog++; 3348 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3349 control = le32toh(cur_tx->msk_control); 3350 sc_if->msk_cdata.msk_tx_cnt--; 3351 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3352 if ((control & EOP) == 0) 3353 continue; 3354 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3355 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3356 BUS_DMASYNC_POSTWRITE); 3357 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3358 3359 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 3360 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3361 __func__)); 3362 m_freem(txd->tx_m); 3363 txd->tx_m = NULL; 3364 } 3365 3366 if (prog > 0) { 3367 sc_if->msk_cdata.msk_tx_cons = cons; 3368 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3369 sc_if->msk_watchdog_timer = 0; 3370 /* No need to sync LEs as we didn't update LEs. */ 3371 } 3372 } 3373 3374 static void 3375 msk_tick(void *xsc_if) 3376 { 3377 struct msk_if_softc *sc_if; 3378 struct mii_data *mii; 3379 3380 sc_if = xsc_if; 3381 3382 MSK_IF_LOCK_ASSERT(sc_if); 3383 3384 mii = device_get_softc(sc_if->msk_miibus); 3385 3386 mii_tick(mii); 3387 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) 3388 msk_miibus_statchg(sc_if->msk_if_dev); 3389 msk_handle_events(sc_if->msk_softc); 3390 msk_watchdog(sc_if); 3391 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3392 } 3393 3394 static void 3395 msk_intr_phy(struct msk_if_softc *sc_if) 3396 { 3397 uint16_t status; 3398 3399 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3400 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3401 /* Handle FIFO Underrun/Overflow? */ 3402 if ((status & PHY_M_IS_FIFO_ERROR)) 3403 device_printf(sc_if->msk_if_dev, 3404 "PHY FIFO underrun/overflow.\n"); 3405 } 3406 3407 static void 3408 msk_intr_gmac(struct msk_if_softc *sc_if) 3409 { 3410 struct msk_softc *sc; 3411 uint8_t status; 3412 3413 sc = sc_if->msk_softc; 3414 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3415 3416 /* GMAC Rx FIFO overrun. */ 3417 if ((status & GM_IS_RX_FF_OR) != 0) 3418 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3419 GMF_CLI_RX_FO); 3420 /* GMAC Tx FIFO underrun. */ 3421 if ((status & GM_IS_TX_FF_UR) != 0) { 3422 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3423 GMF_CLI_TX_FU); 3424 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3425 /* 3426 * XXX 3427 * In case of Tx underrun, we may need to flush/reset 3428 * Tx MAC but that would also require resynchronization 3429 * with status LEs. Reinitializing status LEs would 3430 * affect other port in dual MAC configuration so it 3431 * should be avoided as possible as we can. 3432 * Due to lack of documentation it's all vague guess but 3433 * it needs more investigation. 3434 */ 3435 } 3436 } 3437 3438 static void 3439 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3440 { 3441 struct msk_softc *sc; 3442 3443 sc = sc_if->msk_softc; 3444 if ((status & Y2_IS_PAR_RD1) != 0) { 3445 device_printf(sc_if->msk_if_dev, 3446 "RAM buffer read parity error\n"); 3447 /* Clear IRQ. */ 3448 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3449 RI_CLR_RD_PERR); 3450 } 3451 if ((status & Y2_IS_PAR_WR1) != 0) { 3452 device_printf(sc_if->msk_if_dev, 3453 "RAM buffer write parity error\n"); 3454 /* Clear IRQ. */ 3455 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3456 RI_CLR_WR_PERR); 3457 } 3458 if ((status & Y2_IS_PAR_MAC1) != 0) { 3459 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3460 /* Clear IRQ. */ 3461 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3462 GMF_CLI_TX_PE); 3463 } 3464 if ((status & Y2_IS_PAR_RX1) != 0) { 3465 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3466 /* Clear IRQ. */ 3467 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3468 } 3469 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3470 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3471 /* Clear IRQ. */ 3472 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3473 } 3474 } 3475 3476 static void 3477 msk_intr_hwerr(struct msk_softc *sc) 3478 { 3479 uint32_t status; 3480 uint32_t tlphead[4]; 3481 3482 status = CSR_READ_4(sc, B0_HWE_ISRC); 3483 /* Time Stamp timer overflow. */ 3484 if ((status & Y2_IS_TIST_OV) != 0) 3485 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3486 if ((status & Y2_IS_PCI_NEXP) != 0) { 3487 /* 3488 * PCI Express Error occurred which is not described in PEX 3489 * spec. 3490 * This error is also mapped either to Master Abort( 3491 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3492 * can only be cleared there. 3493 */ 3494 device_printf(sc->msk_dev, 3495 "PCI Express protocol violation error\n"); 3496 } 3497 3498 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3499 uint16_t v16; 3500 3501 if ((status & Y2_IS_MST_ERR) != 0) 3502 device_printf(sc->msk_dev, 3503 "unexpected IRQ Status error\n"); 3504 else 3505 device_printf(sc->msk_dev, 3506 "unexpected IRQ Master error\n"); 3507 /* Reset all bits in the PCI status register. */ 3508 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3509 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3510 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3511 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3512 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 3513 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3514 } 3515 3516 /* Check for PCI Express Uncorrectable Error. */ 3517 if ((status & Y2_IS_PCI_EXP) != 0) { 3518 uint32_t v32; 3519 3520 /* 3521 * On PCI Express bus bridges are called root complexes (RC). 3522 * PCI Express errors are recognized by the root complex too, 3523 * which requests the system to handle the problem. After 3524 * error occurrence it may be that no access to the adapter 3525 * may be performed any longer. 3526 */ 3527 3528 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3529 if ((v32 & PEX_UNSUP_REQ) != 0) { 3530 /* Ignore unsupported request error. */ 3531 device_printf(sc->msk_dev, 3532 "Uncorrectable PCI Express error\n"); 3533 } 3534 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3535 int i; 3536 3537 /* Get TLP header form Log Registers. */ 3538 for (i = 0; i < 4; i++) 3539 tlphead[i] = CSR_PCI_READ_4(sc, 3540 PEX_HEADER_LOG + i * 4); 3541 /* Check for vendor defined broadcast message. */ 3542 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3543 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3544 CSR_WRITE_4(sc, B0_HWE_IMSK, 3545 sc->msk_intrhwemask); 3546 CSR_READ_4(sc, B0_HWE_IMSK); 3547 } 3548 } 3549 /* Clear the interrupt. */ 3550 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3551 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3552 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3553 } 3554 3555 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3556 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3557 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3558 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3559 } 3560 3561 static __inline void 3562 msk_rxput(struct msk_if_softc *sc_if) 3563 { 3564 struct msk_softc *sc; 3565 3566 sc = sc_if->msk_softc; 3567 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) 3568 bus_dmamap_sync( 3569 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3570 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3571 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3572 else 3573 bus_dmamap_sync( 3574 sc_if->msk_cdata.msk_rx_ring_tag, 3575 sc_if->msk_cdata.msk_rx_ring_map, 3576 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3577 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3578 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3579 } 3580 3581 static int 3582 msk_handle_events(struct msk_softc *sc) 3583 { 3584 struct msk_if_softc *sc_if; 3585 int rxput[2]; 3586 struct msk_stat_desc *sd; 3587 uint32_t control, status; 3588 int cons, len, port, rxprog; 3589 3590 if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX)) 3591 return (0); 3592 3593 /* Sync status LEs. */ 3594 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3595 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3596 3597 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3598 rxprog = 0; 3599 cons = sc->msk_stat_cons; 3600 for (;;) { 3601 sd = &sc->msk_stat_ring[cons]; 3602 control = le32toh(sd->msk_control); 3603 if ((control & HW_OWNER) == 0) 3604 break; 3605 control &= ~HW_OWNER; 3606 sd->msk_control = htole32(control); 3607 status = le32toh(sd->msk_status); 3608 len = control & STLE_LEN_MASK; 3609 port = (control >> 16) & 0x01; 3610 sc_if = sc->msk_if[port]; 3611 if (sc_if == NULL) { 3612 device_printf(sc->msk_dev, "invalid port opcode " 3613 "0x%08x\n", control & STLE_OP_MASK); 3614 continue; 3615 } 3616 3617 switch (control & STLE_OP_MASK) { 3618 case OP_RXVLAN: 3619 sc_if->msk_vtag = ntohs(len); 3620 break; 3621 case OP_RXCHKSVLAN: 3622 sc_if->msk_vtag = ntohs(len); 3623 /* FALLTHROUGH */ 3624 case OP_RXCHKS: 3625 sc_if->msk_csum = status; 3626 break; 3627 case OP_RXSTAT: 3628 if (!(sc_if->msk_ifp->if_drv_flags & IFF_DRV_RUNNING)) 3629 break; 3630 if (sc_if->msk_framesize > 3631 (MCLBYTES - MSK_RX_BUF_ALIGN)) 3632 msk_jumbo_rxeof(sc_if, status, control, len); 3633 else 3634 msk_rxeof(sc_if, status, control, len); 3635 rxprog++; 3636 /* 3637 * Because there is no way to sync single Rx LE 3638 * put the DMA sync operation off until the end of 3639 * event processing. 3640 */ 3641 rxput[port]++; 3642 /* Update prefetch unit if we've passed water mark. */ 3643 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3644 msk_rxput(sc_if); 3645 rxput[port] = 0; 3646 } 3647 break; 3648 case OP_TXINDEXLE: 3649 if (sc->msk_if[MSK_PORT_A] != NULL) 3650 msk_txeof(sc->msk_if[MSK_PORT_A], 3651 status & STLE_TXA1_MSKL); 3652 if (sc->msk_if[MSK_PORT_B] != NULL) 3653 msk_txeof(sc->msk_if[MSK_PORT_B], 3654 ((status & STLE_TXA2_MSKL) >> 3655 STLE_TXA2_SHIFTL) | 3656 ((len & STLE_TXA2_MSKH) << 3657 STLE_TXA2_SHIFTH)); 3658 break; 3659 default: 3660 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3661 control & STLE_OP_MASK); 3662 break; 3663 } 3664 MSK_INC(cons, sc->msk_stat_count); 3665 if (rxprog > sc->msk_process_limit) 3666 break; 3667 } 3668 3669 sc->msk_stat_cons = cons; 3670 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3671 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3672 3673 if (rxput[MSK_PORT_A] > 0) 3674 msk_rxput(sc->msk_if[MSK_PORT_A]); 3675 if (rxput[MSK_PORT_B] > 0) 3676 msk_rxput(sc->msk_if[MSK_PORT_B]); 3677 3678 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3679 } 3680 3681 static void 3682 msk_intr(void *xsc) 3683 { 3684 struct msk_softc *sc; 3685 struct msk_if_softc *sc_if0, *sc_if1; 3686 struct ifnet *ifp0, *ifp1; 3687 uint32_t status; 3688 int domore; 3689 3690 sc = xsc; 3691 MSK_LOCK(sc); 3692 3693 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3694 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3695 if (status == 0 || status == 0xffffffff || 3696 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || 3697 (status & sc->msk_intrmask) == 0) { 3698 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3699 MSK_UNLOCK(sc); 3700 return; 3701 } 3702 3703 sc_if0 = sc->msk_if[MSK_PORT_A]; 3704 sc_if1 = sc->msk_if[MSK_PORT_B]; 3705 ifp0 = ifp1 = NULL; 3706 if (sc_if0 != NULL) 3707 ifp0 = sc_if0->msk_ifp; 3708 if (sc_if1 != NULL) 3709 ifp1 = sc_if1->msk_ifp; 3710 3711 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3712 msk_intr_phy(sc_if0); 3713 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3714 msk_intr_phy(sc_if1); 3715 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3716 msk_intr_gmac(sc_if0); 3717 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3718 msk_intr_gmac(sc_if1); 3719 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3720 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3721 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3722 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3723 CSR_READ_4(sc, B0_IMSK); 3724 } 3725 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3726 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3727 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3728 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3729 CSR_READ_4(sc, B0_IMSK); 3730 } 3731 if ((status & Y2_IS_HW_ERR) != 0) 3732 msk_intr_hwerr(sc); 3733 3734 domore = msk_handle_events(sc); 3735 if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0) 3736 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3737 3738 /* Reenable interrupts. */ 3739 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3740 3741 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3742 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3743 msk_start_locked(ifp0); 3744 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3745 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3746 msk_start_locked(ifp1); 3747 3748 MSK_UNLOCK(sc); 3749 } 3750 3751 static void 3752 msk_set_tx_stfwd(struct msk_if_softc *sc_if) 3753 { 3754 struct msk_softc *sc; 3755 struct ifnet *ifp; 3756 3757 ifp = sc_if->msk_ifp; 3758 sc = sc_if->msk_softc; 3759 if ((sc->msk_hw_id == CHIP_ID_YUKON_EX && 3760 sc->msk_hw_rev != CHIP_REV_YU_EX_A0) || 3761 sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) { 3762 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3763 TX_STFW_ENA); 3764 } else { 3765 if (ifp->if_mtu > ETHERMTU) { 3766 /* Set Tx GMAC FIFO Almost Empty Threshold. */ 3767 CSR_WRITE_4(sc, 3768 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3769 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3770 /* Disable Store & Forward mode for Tx. */ 3771 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3772 TX_STFW_DIS); 3773 } else { 3774 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3775 TX_STFW_ENA); 3776 } 3777 } 3778 } 3779 3780 static void 3781 msk_init(void *xsc) 3782 { 3783 struct msk_if_softc *sc_if = xsc; 3784 3785 MSK_IF_LOCK(sc_if); 3786 msk_init_locked(sc_if); 3787 MSK_IF_UNLOCK(sc_if); 3788 } 3789 3790 static void 3791 msk_init_locked(struct msk_if_softc *sc_if) 3792 { 3793 struct msk_softc *sc; 3794 struct ifnet *ifp; 3795 struct mii_data *mii; 3796 uint8_t *eaddr; 3797 uint16_t gmac; 3798 uint32_t reg; 3799 int error; 3800 3801 MSK_IF_LOCK_ASSERT(sc_if); 3802 3803 ifp = sc_if->msk_ifp; 3804 sc = sc_if->msk_softc; 3805 mii = device_get_softc(sc_if->msk_miibus); 3806 3807 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3808 return; 3809 3810 error = 0; 3811 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3812 msk_stop(sc_if); 3813 3814 if (ifp->if_mtu < ETHERMTU) 3815 sc_if->msk_framesize = ETHERMTU; 3816 else 3817 sc_if->msk_framesize = ifp->if_mtu; 3818 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3819 if (ifp->if_mtu > ETHERMTU && 3820 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 3821 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 3822 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 3823 } 3824 3825 /* GMAC Control reset. */ 3826 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); 3827 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); 3828 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); 3829 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 3830 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) 3831 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), 3832 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 3833 GMC_BYP_RETR_ON); 3834 3835 /* 3836 * Initialize GMAC first such that speed/duplex/flow-control 3837 * parameters are renegotiated when interface is brought up. 3838 */ 3839 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0); 3840 3841 /* Dummy read the Interrupt Source Register. */ 3842 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3843 3844 /* Clear MIB stats. */ 3845 msk_stats_clear(sc_if); 3846 3847 /* Disable FCS. */ 3848 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3849 3850 /* Setup Transmit Control Register. */ 3851 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3852 3853 /* Setup Transmit Flow Control Register. */ 3854 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3855 3856 /* Setup Transmit Parameter Register. */ 3857 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3858 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3859 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3860 3861 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3862 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3863 3864 if (ifp->if_mtu > ETHERMTU) 3865 gmac |= GM_SMOD_JUMBO_ENA; 3866 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3867 3868 /* Set station address. */ 3869 eaddr = IF_LLADDR(ifp); 3870 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L, 3871 eaddr[0] | (eaddr[1] << 8)); 3872 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M, 3873 eaddr[2] | (eaddr[3] << 8)); 3874 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H, 3875 eaddr[4] | (eaddr[5] << 8)); 3876 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L, 3877 eaddr[0] | (eaddr[1] << 8)); 3878 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M, 3879 eaddr[2] | (eaddr[3] << 8)); 3880 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H, 3881 eaddr[4] | (eaddr[5] << 8)); 3882 3883 /* Disable interrupts for counter overflows. */ 3884 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3885 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3886 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3887 3888 /* Configure Rx MAC FIFO. */ 3889 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3890 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3891 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 3892 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P || 3893 sc->msk_hw_id == CHIP_ID_YUKON_EX) 3894 reg |= GMF_RX_OVER_ON; 3895 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); 3896 3897 /* Set receive filter. */ 3898 msk_rxfilter(sc_if); 3899 3900 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 3901 /* Clear flush mask - HW bug. */ 3902 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0); 3903 } else { 3904 /* Flush Rx MAC FIFO on any flow control or error. */ 3905 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3906 GMR_FS_ANY_ERR); 3907 } 3908 3909 /* 3910 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 3911 * due to hardware hang on receipt of pause frames. 3912 */ 3913 reg = RX_GMF_FL_THR_DEF + 1; 3914 /* Another magic for Yukon FE+ - From Linux. */ 3915 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3916 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) 3917 reg = 0x178; 3918 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); 3919 3920 /* Configure Tx MAC FIFO. */ 3921 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3922 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3923 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3924 3925 /* Configure hardware VLAN tag insertion/stripping. */ 3926 msk_setvlan(sc_if, ifp); 3927 3928 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { 3929 /* Set Rx Pause threshold. */ 3930 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3931 MSK_ECU_LLPP); 3932 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3933 MSK_ECU_ULPP); 3934 /* Configure store-and-forward for Tx. */ 3935 msk_set_tx_stfwd(sc_if); 3936 } 3937 3938 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3939 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 3940 /* Disable dynamic watermark - from Linux. */ 3941 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); 3942 reg &= ~0x03; 3943 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); 3944 } 3945 3946 /* 3947 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3948 * arbiter as we don't use Sync Tx queue. 3949 */ 3950 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3951 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3952 /* Enable the RAM Interface Arbiter. */ 3953 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3954 3955 /* Setup RAM buffer. */ 3956 msk_set_rambuffer(sc_if); 3957 3958 /* Disable Tx sync Queue. */ 3959 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3960 3961 /* Setup Tx Queue Bus Memory Interface. */ 3962 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3963 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3964 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3965 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3966 switch (sc->msk_hw_id) { 3967 case CHIP_ID_YUKON_EC_U: 3968 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3969 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3970 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), 3971 MSK_ECU_TXFF_LEV); 3972 } 3973 break; 3974 case CHIP_ID_YUKON_EX: 3975 /* 3976 * Yukon Extreme seems to have silicon bug for 3977 * automatic Tx checksum calculation capability. 3978 */ 3979 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 3980 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F), 3981 F_TX_CHK_AUTO_OFF); 3982 break; 3983 } 3984 3985 /* Setup Rx Queue Bus Memory Interface. */ 3986 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3987 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3988 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3989 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3990 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3991 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3992 /* MAC Rx RAM Read is controlled by hardware. */ 3993 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3994 } 3995 3996 msk_set_prefetch(sc, sc_if->msk_txq, 3997 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3998 msk_init_tx_ring(sc_if); 3999 4000 /* Disable Rx checksum offload and RSS hash. */ 4001 reg = BMU_DIS_RX_RSS_HASH; 4002 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 4003 (ifp->if_capenable & IFCAP_RXCSUM) != 0) 4004 reg |= BMU_ENA_RX_CHKSUM; 4005 else 4006 reg |= BMU_DIS_RX_CHKSUM; 4007 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg); 4008 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) { 4009 msk_set_prefetch(sc, sc_if->msk_rxq, 4010 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 4011 MSK_JUMBO_RX_RING_CNT - 1); 4012 error = msk_init_jumbo_rx_ring(sc_if); 4013 } else { 4014 msk_set_prefetch(sc, sc_if->msk_rxq, 4015 sc_if->msk_rdata.msk_rx_ring_paddr, 4016 MSK_RX_RING_CNT - 1); 4017 error = msk_init_rx_ring(sc_if); 4018 } 4019 if (error != 0) { 4020 device_printf(sc_if->msk_if_dev, 4021 "initialization failed: no memory for Rx buffers\n"); 4022 msk_stop(sc_if); 4023 return; 4024 } 4025 if (sc->msk_hw_id == CHIP_ID_YUKON_EX || 4026 sc->msk_hw_id == CHIP_ID_YUKON_SUPR) { 4027 /* Disable flushing of non-ASF packets. */ 4028 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 4029 GMF_RX_MACSEC_FLUSH_OFF); 4030 } 4031 4032 /* Configure interrupt handling. */ 4033 if (sc_if->msk_port == MSK_PORT_A) { 4034 sc->msk_intrmask |= Y2_IS_PORT_A; 4035 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 4036 } else { 4037 sc->msk_intrmask |= Y2_IS_PORT_B; 4038 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 4039 } 4040 /* Configure IRQ moderation mask. */ 4041 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask); 4042 if (sc->msk_int_holdoff > 0) { 4043 /* Configure initial IRQ moderation timer value. */ 4044 CSR_WRITE_4(sc, B2_IRQM_INI, 4045 MSK_USECS(sc, sc->msk_int_holdoff)); 4046 CSR_WRITE_4(sc, B2_IRQM_VAL, 4047 MSK_USECS(sc, sc->msk_int_holdoff)); 4048 /* Start IRQ moderation. */ 4049 CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START); 4050 } 4051 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4052 CSR_READ_4(sc, B0_HWE_IMSK); 4053 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4054 CSR_READ_4(sc, B0_IMSK); 4055 4056 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4057 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4058 4059 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4060 mii_mediachg(mii); 4061 4062 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 4063 } 4064 4065 static void 4066 msk_set_rambuffer(struct msk_if_softc *sc_if) 4067 { 4068 struct msk_softc *sc; 4069 int ltpp, utpp; 4070 4071 sc = sc_if->msk_softc; 4072 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 4073 return; 4074 4075 /* Setup Rx Queue. */ 4076 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 4077 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 4078 sc->msk_rxqstart[sc_if->msk_port] / 8); 4079 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 4080 sc->msk_rxqend[sc_if->msk_port] / 8); 4081 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 4082 sc->msk_rxqstart[sc_if->msk_port] / 8); 4083 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 4084 sc->msk_rxqstart[sc_if->msk_port] / 8); 4085 4086 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 4087 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 4088 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 4089 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 4090 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 4091 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 4092 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 4093 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 4094 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 4095 4096 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 4097 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 4098 4099 /* Setup Tx Queue. */ 4100 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 4101 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 4102 sc->msk_txqstart[sc_if->msk_port] / 8); 4103 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 4104 sc->msk_txqend[sc_if->msk_port] / 8); 4105 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 4106 sc->msk_txqstart[sc_if->msk_port] / 8); 4107 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 4108 sc->msk_txqstart[sc_if->msk_port] / 8); 4109 /* Enable Store & Forward for Tx side. */ 4110 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 4111 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 4112 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 4113 } 4114 4115 static void 4116 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 4117 uint32_t count) 4118 { 4119 4120 /* Reset the prefetch unit. */ 4121 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4122 PREF_UNIT_RST_SET); 4123 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4124 PREF_UNIT_RST_CLR); 4125 /* Set LE base address. */ 4126 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 4127 MSK_ADDR_LO(addr)); 4128 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 4129 MSK_ADDR_HI(addr)); 4130 /* Set the list last index. */ 4131 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 4132 count); 4133 /* Turn on prefetch unit. */ 4134 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4135 PREF_UNIT_OP_ON); 4136 /* Dummy read to ensure write. */ 4137 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 4138 } 4139 4140 static void 4141 msk_stop(struct msk_if_softc *sc_if) 4142 { 4143 struct msk_softc *sc; 4144 struct msk_txdesc *txd; 4145 struct msk_rxdesc *rxd; 4146 struct msk_rxdesc *jrxd; 4147 struct ifnet *ifp; 4148 uint32_t val; 4149 int i; 4150 4151 MSK_IF_LOCK_ASSERT(sc_if); 4152 sc = sc_if->msk_softc; 4153 ifp = sc_if->msk_ifp; 4154 4155 callout_stop(&sc_if->msk_tick_ch); 4156 sc_if->msk_watchdog_timer = 0; 4157 4158 /* Disable interrupts. */ 4159 if (sc_if->msk_port == MSK_PORT_A) { 4160 sc->msk_intrmask &= ~Y2_IS_PORT_A; 4161 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 4162 } else { 4163 sc->msk_intrmask &= ~Y2_IS_PORT_B; 4164 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 4165 } 4166 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4167 CSR_READ_4(sc, B0_HWE_IMSK); 4168 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4169 CSR_READ_4(sc, B0_IMSK); 4170 4171 /* Disable Tx/Rx MAC. */ 4172 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4173 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 4174 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 4175 /* Read again to ensure writing. */ 4176 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4177 /* Update stats and clear counters. */ 4178 msk_stats_update(sc_if); 4179 4180 /* Stop Tx BMU. */ 4181 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 4182 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4183 for (i = 0; i < MSK_TIMEOUT; i++) { 4184 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 4185 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4186 BMU_STOP); 4187 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4188 } else 4189 break; 4190 DELAY(1); 4191 } 4192 if (i == MSK_TIMEOUT) 4193 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 4194 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 4195 RB_RST_SET | RB_DIS_OP_MD); 4196 4197 /* Disable all GMAC interrupt. */ 4198 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 4199 /* Disable PHY interrupt. */ 4200 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 4201 4202 /* Disable the RAM Interface Arbiter. */ 4203 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 4204 4205 /* Reset the PCI FIFO of the async Tx queue */ 4206 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4207 BMU_RST_SET | BMU_FIFO_RST); 4208 4209 /* Reset the Tx prefetch units. */ 4210 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 4211 PREF_UNIT_RST_SET); 4212 4213 /* Reset the RAM Buffer async Tx queue. */ 4214 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 4215 4216 /* Reset Tx MAC FIFO. */ 4217 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 4218 /* Set Pause Off. */ 4219 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 4220 4221 /* 4222 * The Rx Stop command will not work for Yukon-2 if the BMU does not 4223 * reach the end of packet and since we can't make sure that we have 4224 * incoming data, we must reset the BMU while it is not during a DMA 4225 * transfer. Since it is possible that the Rx path is still active, 4226 * the Rx RAM buffer will be stopped first, so any possible incoming 4227 * data will not trigger a DMA. After the RAM buffer is stopped, the 4228 * BMU is polled until any DMA in progress is ended and only then it 4229 * will be reset. 4230 */ 4231 4232 /* Disable the RAM Buffer receive queue. */ 4233 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 4234 for (i = 0; i < MSK_TIMEOUT; i++) { 4235 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 4236 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 4237 break; 4238 DELAY(1); 4239 } 4240 if (i == MSK_TIMEOUT) 4241 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 4242 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 4243 BMU_RST_SET | BMU_FIFO_RST); 4244 /* Reset the Rx prefetch unit. */ 4245 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 4246 PREF_UNIT_RST_SET); 4247 /* Reset the RAM Buffer receive queue. */ 4248 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 4249 /* Reset Rx MAC FIFO. */ 4250 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 4251 4252 /* Free Rx and Tx mbufs still in the queues. */ 4253 for (i = 0; i < MSK_RX_RING_CNT; i++) { 4254 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 4255 if (rxd->rx_m != NULL) { 4256 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 4257 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4258 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 4259 rxd->rx_dmamap); 4260 m_freem(rxd->rx_m); 4261 rxd->rx_m = NULL; 4262 } 4263 } 4264 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 4265 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 4266 if (jrxd->rx_m != NULL) { 4267 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 4268 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4269 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 4270 jrxd->rx_dmamap); 4271 m_freem(jrxd->rx_m); 4272 jrxd->rx_m = NULL; 4273 } 4274 } 4275 for (i = 0; i < MSK_TX_RING_CNT; i++) { 4276 txd = &sc_if->msk_cdata.msk_txdesc[i]; 4277 if (txd->tx_m != NULL) { 4278 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 4279 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4280 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 4281 txd->tx_dmamap); 4282 m_freem(txd->tx_m); 4283 txd->tx_m = NULL; 4284 } 4285 } 4286 4287 /* 4288 * Mark the interface down. 4289 */ 4290 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4291 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4292 } 4293 4294 /* 4295 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower 4296 * counter clears high 16 bits of the counter such that accessing 4297 * lower 16 bits should be the last operation. 4298 */ 4299 #define MSK_READ_MIB32(x, y) \ 4300 (((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \ 4301 (uint32_t)GMAC_READ_2(sc, x, y) 4302 #define MSK_READ_MIB64(x, y) \ 4303 (((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \ 4304 (uint64_t)MSK_READ_MIB32(x, y) 4305 4306 static void 4307 msk_stats_clear(struct msk_if_softc *sc_if) 4308 { 4309 struct msk_softc *sc; 4310 uint32_t reg; 4311 uint16_t gmac; 4312 int i; 4313 4314 MSK_IF_LOCK_ASSERT(sc_if); 4315 4316 sc = sc_if->msk_softc; 4317 /* Set MIB Clear Counter Mode. */ 4318 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4319 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4320 /* Read all MIB Counters with Clear Mode set. */ 4321 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t)) 4322 reg = MSK_READ_MIB32(sc_if->msk_port, i); 4323 /* Clear MIB Clear Counter Mode. */ 4324 gmac &= ~GM_PAR_MIB_CLR; 4325 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4326 } 4327 4328 static void 4329 msk_stats_update(struct msk_if_softc *sc_if) 4330 { 4331 struct msk_softc *sc; 4332 struct ifnet *ifp; 4333 struct msk_hw_stats *stats; 4334 uint16_t gmac; 4335 uint32_t reg; 4336 4337 MSK_IF_LOCK_ASSERT(sc_if); 4338 4339 ifp = sc_if->msk_ifp; 4340 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 4341 return; 4342 sc = sc_if->msk_softc; 4343 stats = &sc_if->msk_stats; 4344 /* Set MIB Clear Counter Mode. */ 4345 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4346 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4347 4348 /* Rx stats. */ 4349 stats->rx_ucast_frames += 4350 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK); 4351 stats->rx_bcast_frames += 4352 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK); 4353 stats->rx_pause_frames += 4354 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE); 4355 stats->rx_mcast_frames += 4356 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK); 4357 stats->rx_crc_errs += 4358 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR); 4359 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE1); 4360 stats->rx_good_octets += 4361 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO); 4362 stats->rx_bad_octets += 4363 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO); 4364 stats->rx_runts += 4365 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT); 4366 stats->rx_runt_errs += 4367 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG); 4368 stats->rx_pkts_64 += 4369 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B); 4370 stats->rx_pkts_65_127 += 4371 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B); 4372 stats->rx_pkts_128_255 += 4373 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B); 4374 stats->rx_pkts_256_511 += 4375 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B); 4376 stats->rx_pkts_512_1023 += 4377 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B); 4378 stats->rx_pkts_1024_1518 += 4379 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B); 4380 stats->rx_pkts_1519_max += 4381 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ); 4382 stats->rx_pkts_too_long += 4383 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR); 4384 stats->rx_pkts_jabbers += 4385 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT); 4386 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE2); 4387 stats->rx_fifo_oflows += 4388 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV); 4389 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE3); 4390 4391 /* Tx stats. */ 4392 stats->tx_ucast_frames += 4393 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK); 4394 stats->tx_bcast_frames += 4395 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK); 4396 stats->tx_pause_frames += 4397 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE); 4398 stats->tx_mcast_frames += 4399 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK); 4400 stats->tx_octets += 4401 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO); 4402 stats->tx_pkts_64 += 4403 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B); 4404 stats->tx_pkts_65_127 += 4405 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B); 4406 stats->tx_pkts_128_255 += 4407 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B); 4408 stats->tx_pkts_256_511 += 4409 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B); 4410 stats->tx_pkts_512_1023 += 4411 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B); 4412 stats->tx_pkts_1024_1518 += 4413 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B); 4414 stats->tx_pkts_1519_max += 4415 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ); 4416 reg = MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SPARE1); 4417 stats->tx_colls += 4418 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL); 4419 stats->tx_late_colls += 4420 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL); 4421 stats->tx_excess_colls += 4422 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL); 4423 stats->tx_multi_colls += 4424 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL); 4425 stats->tx_single_colls += 4426 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL); 4427 stats->tx_underflows += 4428 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR); 4429 /* Clear MIB Clear Counter Mode. */ 4430 gmac &= ~GM_PAR_MIB_CLR; 4431 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4432 } 4433 4434 static int 4435 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS) 4436 { 4437 struct msk_softc *sc; 4438 struct msk_if_softc *sc_if; 4439 uint32_t result, *stat; 4440 int off; 4441 4442 sc_if = (struct msk_if_softc *)arg1; 4443 sc = sc_if->msk_softc; 4444 off = arg2; 4445 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off); 4446 4447 MSK_IF_LOCK(sc_if); 4448 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4449 result += *stat; 4450 MSK_IF_UNLOCK(sc_if); 4451 4452 return (sysctl_handle_int(oidp, &result, 0, req)); 4453 } 4454 4455 static int 4456 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS) 4457 { 4458 struct msk_softc *sc; 4459 struct msk_if_softc *sc_if; 4460 uint64_t result, *stat; 4461 int off; 4462 4463 sc_if = (struct msk_if_softc *)arg1; 4464 sc = sc_if->msk_softc; 4465 off = arg2; 4466 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off); 4467 4468 MSK_IF_LOCK(sc_if); 4469 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4470 result += *stat; 4471 MSK_IF_UNLOCK(sc_if); 4472 4473 return (sysctl_handle_64(oidp, &result, 0, req)); 4474 } 4475 4476 #undef MSK_READ_MIB32 4477 #undef MSK_READ_MIB64 4478 4479 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \ 4480 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4481 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \ 4482 "IU", d) 4483 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \ 4484 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_U64 | CTLFLAG_RD, \ 4485 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \ 4486 "QU", d) 4487 4488 static void 4489 msk_sysctl_node(struct msk_if_softc *sc_if) 4490 { 4491 struct sysctl_ctx_list *ctx; 4492 struct sysctl_oid_list *child, *schild; 4493 struct sysctl_oid *tree; 4494 4495 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev); 4496 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev)); 4497 4498 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 4499 NULL, "MSK Statistics"); 4500 schild = SYSCTL_CHILDREN(tree); 4501 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 4502 NULL, "MSK RX Statistics"); 4503 child = SYSCTL_CHILDREN(tree); 4504 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4505 child, rx_ucast_frames, "Good unicast frames"); 4506 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4507 child, rx_bcast_frames, "Good broadcast frames"); 4508 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4509 child, rx_pause_frames, "Pause frames"); 4510 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4511 child, rx_mcast_frames, "Multicast frames"); 4512 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs", 4513 child, rx_crc_errs, "CRC errors"); 4514 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets", 4515 child, rx_good_octets, "Good octets"); 4516 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets", 4517 child, rx_bad_octets, "Bad octets"); 4518 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4519 child, rx_pkts_64, "64 bytes frames"); 4520 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4521 child, rx_pkts_65_127, "65 to 127 bytes frames"); 4522 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4523 child, rx_pkts_128_255, "128 to 255 bytes frames"); 4524 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4525 child, rx_pkts_256_511, "256 to 511 bytes frames"); 4526 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4527 child, rx_pkts_512_1023, "512 to 1023 bytes frames"); 4528 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4529 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4530 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4531 child, rx_pkts_1519_max, "1519 to max frames"); 4532 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long", 4533 child, rx_pkts_too_long, "frames too long"); 4534 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers", 4535 child, rx_pkts_jabbers, "Jabber errors"); 4536 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows", 4537 child, rx_fifo_oflows, "FIFO overflows"); 4538 4539 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 4540 NULL, "MSK TX Statistics"); 4541 child = SYSCTL_CHILDREN(tree); 4542 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4543 child, tx_ucast_frames, "Unicast frames"); 4544 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4545 child, tx_bcast_frames, "Broadcast frames"); 4546 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4547 child, tx_pause_frames, "Pause frames"); 4548 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4549 child, tx_mcast_frames, "Multicast frames"); 4550 MSK_SYSCTL_STAT64(sc_if, ctx, "octets", 4551 child, tx_octets, "Octets"); 4552 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4553 child, tx_pkts_64, "64 bytes frames"); 4554 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4555 child, tx_pkts_65_127, "65 to 127 bytes frames"); 4556 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4557 child, tx_pkts_128_255, "128 to 255 bytes frames"); 4558 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4559 child, tx_pkts_256_511, "256 to 511 bytes frames"); 4560 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4561 child, tx_pkts_512_1023, "512 to 1023 bytes frames"); 4562 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4563 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4564 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4565 child, tx_pkts_1519_max, "1519 to max frames"); 4566 MSK_SYSCTL_STAT32(sc_if, ctx, "colls", 4567 child, tx_colls, "Collisions"); 4568 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls", 4569 child, tx_late_colls, "Late collisions"); 4570 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls", 4571 child, tx_excess_colls, "Excessive collisions"); 4572 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls", 4573 child, tx_multi_colls, "Multiple collisions"); 4574 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls", 4575 child, tx_single_colls, "Single collisions"); 4576 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows", 4577 child, tx_underflows, "FIFO underflows"); 4578 } 4579 4580 #undef MSK_SYSCTL_STAT32 4581 #undef MSK_SYSCTL_STAT64 4582 4583 static int 4584 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4585 { 4586 int error, value; 4587 4588 if (!arg1) 4589 return (EINVAL); 4590 value = *(int *)arg1; 4591 error = sysctl_handle_int(oidp, &value, 0, req); 4592 if (error || !req->newptr) 4593 return (error); 4594 if (value < low || value > high) 4595 return (EINVAL); 4596 *(int *)arg1 = value; 4597 4598 return (0); 4599 } 4600 4601 static int 4602 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4603 { 4604 4605 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4606 MSK_PROC_MAX)); 4607 } 4608