1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 /*- 80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 81 * 82 * Permission to use, copy, modify, and distribute this software for any 83 * purpose with or without fee is hereby granted, provided that the above 84 * copyright notice and this permission notice appear in all copies. 85 * 86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 93 */ 94 95 /* 96 * Device driver for the Marvell Yukon II Ethernet controller. 97 * Due to lack of documentation, this driver is based on the code from 98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 99 */ 100 101 #include <sys/cdefs.h> 102 __FBSDID("$FreeBSD$"); 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/bus.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/sockio.h> 114 #include <sys/queue.h> 115 #include <sys/sysctl.h> 116 117 #include <net/bpf.h> 118 #include <net/ethernet.h> 119 #include <net/if.h> 120 #include <net/if_arp.h> 121 #include <net/if_dl.h> 122 #include <net/if_media.h> 123 #include <net/if_types.h> 124 #include <net/if_vlan_var.h> 125 126 #include <netinet/in.h> 127 #include <netinet/in_systm.h> 128 #include <netinet/ip.h> 129 #include <netinet/tcp.h> 130 #include <netinet/udp.h> 131 132 #include <machine/bus.h> 133 #include <machine/in_cksum.h> 134 #include <machine/resource.h> 135 #include <sys/rman.h> 136 137 #include <dev/mii/mii.h> 138 #include <dev/mii/miivar.h> 139 140 #include <dev/pci/pcireg.h> 141 #include <dev/pci/pcivar.h> 142 143 #include <dev/msk/if_mskreg.h> 144 145 MODULE_DEPEND(msk, pci, 1, 1, 1); 146 MODULE_DEPEND(msk, ether, 1, 1, 1); 147 MODULE_DEPEND(msk, miibus, 1, 1, 1); 148 149 /* "device miibus" required. See GENERIC if you get errors here. */ 150 #include "miibus_if.h" 151 152 /* Tunables. */ 153 static int msi_disable = 0; 154 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 155 static int legacy_intr = 0; 156 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 157 static int jumbo_disable = 0; 158 TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable); 159 160 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 161 162 /* 163 * Devices supported by this driver. 164 */ 165 static struct msk_product { 166 uint16_t msk_vendorid; 167 uint16_t msk_deviceid; 168 const char *msk_name; 169 } msk_products[] = { 170 { VENDORID_SK, DEVICEID_SK_YUKON2, 171 "SK-9Sxx Gigabit Ethernet" }, 172 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 173 "SK-9Exx Gigabit Ethernet"}, 174 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 175 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 176 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 177 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 178 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 179 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 180 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 181 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 182 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 183 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 184 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 185 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 186 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 187 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 188 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 189 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 190 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 191 "Marvell Yukon 88E8035 Fast Ethernet" }, 192 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 193 "Marvell Yukon 88E8036 Fast Ethernet" }, 194 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 195 "Marvell Yukon 88E8038 Fast Ethernet" }, 196 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 197 "Marvell Yukon 88E8039 Fast Ethernet" }, 198 { VENDORID_MARVELL, DEVICEID_MRVL_8040, 199 "Marvell Yukon 88E8040 Fast Ethernet" }, 200 { VENDORID_MARVELL, DEVICEID_MRVL_8040T, 201 "Marvell Yukon 88E8040T Fast Ethernet" }, 202 { VENDORID_MARVELL, DEVICEID_MRVL_8042, 203 "Marvell Yukon 88E8042 Fast Ethernet" }, 204 { VENDORID_MARVELL, DEVICEID_MRVL_8048, 205 "Marvell Yukon 88E8048 Fast Ethernet" }, 206 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 207 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 208 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 209 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 210 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 211 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 212 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 213 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 214 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 215 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 216 { VENDORID_MARVELL, DEVICEID_MRVL_4365, 217 "Marvell Yukon 88E8070 Gigabit Ethernet" }, 218 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 219 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 220 { VENDORID_MARVELL, DEVICEID_MRVL_436B, 221 "Marvell Yukon 88E8071 Gigabit Ethernet" }, 222 { VENDORID_MARVELL, DEVICEID_MRVL_436C, 223 "Marvell Yukon 88E8072 Gigabit Ethernet" }, 224 { VENDORID_MARVELL, DEVICEID_MRVL_4380, 225 "Marvell Yukon 88E8057 Gigabit Ethernet" }, 226 { VENDORID_MARVELL, DEVICEID_MRVL_4381, 227 "Marvell Yukon 88E8059 Gigabit Ethernet" }, 228 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 229 "D-Link 550SX Gigabit Ethernet" }, 230 { VENDORID_DLINK, DEVICEID_DLINK_DGE560SX, 231 "D-Link 560SX Gigabit Ethernet" }, 232 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 233 "D-Link 560T Gigabit Ethernet" } 234 }; 235 236 static const char *model_name[] = { 237 "Yukon XL", 238 "Yukon EC Ultra", 239 "Yukon EX", 240 "Yukon EC", 241 "Yukon FE", 242 "Yukon FE+", 243 "Yukon Supreme", 244 "Yukon Ultra 2", 245 "Yukon Unknown", 246 "Yukon Optima", 247 }; 248 249 static int mskc_probe(device_t); 250 static int mskc_attach(device_t); 251 static int mskc_detach(device_t); 252 static int mskc_shutdown(device_t); 253 static int mskc_setup_rambuffer(struct msk_softc *); 254 static int mskc_suspend(device_t); 255 static int mskc_resume(device_t); 256 static void mskc_reset(struct msk_softc *); 257 258 static int msk_probe(device_t); 259 static int msk_attach(device_t); 260 static int msk_detach(device_t); 261 262 static void msk_tick(void *); 263 static void msk_intr(void *); 264 static void msk_intr_phy(struct msk_if_softc *); 265 static void msk_intr_gmac(struct msk_if_softc *); 266 static __inline void msk_rxput(struct msk_if_softc *); 267 static int msk_handle_events(struct msk_softc *); 268 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 269 static void msk_intr_hwerr(struct msk_softc *); 270 #ifndef __NO_STRICT_ALIGNMENT 271 static __inline void msk_fixup_rx(struct mbuf *); 272 #endif 273 static __inline void msk_rxcsum(struct msk_if_softc *, uint32_t, struct mbuf *); 274 static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 275 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int); 276 static void msk_txeof(struct msk_if_softc *, int); 277 static int msk_encap(struct msk_if_softc *, struct mbuf **); 278 static void msk_start(struct ifnet *); 279 static void msk_start_locked(struct ifnet *); 280 static int msk_ioctl(struct ifnet *, u_long, caddr_t); 281 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 282 static void msk_set_rambuffer(struct msk_if_softc *); 283 static void msk_set_tx_stfwd(struct msk_if_softc *); 284 static void msk_init(void *); 285 static void msk_init_locked(struct msk_if_softc *); 286 static void msk_stop(struct msk_if_softc *); 287 static void msk_watchdog(struct msk_if_softc *); 288 static int msk_mediachange(struct ifnet *); 289 static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 290 static void msk_phy_power(struct msk_softc *, int); 291 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 292 static int msk_status_dma_alloc(struct msk_softc *); 293 static void msk_status_dma_free(struct msk_softc *); 294 static int msk_txrx_dma_alloc(struct msk_if_softc *); 295 static int msk_rx_dma_jalloc(struct msk_if_softc *); 296 static void msk_txrx_dma_free(struct msk_if_softc *); 297 static void msk_rx_dma_jfree(struct msk_if_softc *); 298 static int msk_rx_fill(struct msk_if_softc *, int); 299 static int msk_init_rx_ring(struct msk_if_softc *); 300 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 301 static void msk_init_tx_ring(struct msk_if_softc *); 302 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 303 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 304 static int msk_newbuf(struct msk_if_softc *, int); 305 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 306 307 static int msk_phy_readreg(struct msk_if_softc *, int, int); 308 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 309 static int msk_miibus_readreg(device_t, int, int); 310 static int msk_miibus_writereg(device_t, int, int, int); 311 static void msk_miibus_statchg(device_t); 312 313 static void msk_rxfilter(struct msk_if_softc *); 314 static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 315 316 static void msk_stats_clear(struct msk_if_softc *); 317 static void msk_stats_update(struct msk_if_softc *); 318 static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS); 319 static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS); 320 static void msk_sysctl_node(struct msk_if_softc *); 321 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 322 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 323 324 static device_method_t mskc_methods[] = { 325 /* Device interface */ 326 DEVMETHOD(device_probe, mskc_probe), 327 DEVMETHOD(device_attach, mskc_attach), 328 DEVMETHOD(device_detach, mskc_detach), 329 DEVMETHOD(device_suspend, mskc_suspend), 330 DEVMETHOD(device_resume, mskc_resume), 331 DEVMETHOD(device_shutdown, mskc_shutdown), 332 333 /* bus interface */ 334 DEVMETHOD(bus_print_child, bus_generic_print_child), 335 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 336 337 { NULL, NULL } 338 }; 339 340 static driver_t mskc_driver = { 341 "mskc", 342 mskc_methods, 343 sizeof(struct msk_softc) 344 }; 345 346 static devclass_t mskc_devclass; 347 348 static device_method_t msk_methods[] = { 349 /* Device interface */ 350 DEVMETHOD(device_probe, msk_probe), 351 DEVMETHOD(device_attach, msk_attach), 352 DEVMETHOD(device_detach, msk_detach), 353 DEVMETHOD(device_shutdown, bus_generic_shutdown), 354 355 /* bus interface */ 356 DEVMETHOD(bus_print_child, bus_generic_print_child), 357 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 358 359 /* MII interface */ 360 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 361 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 362 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 363 364 { NULL, NULL } 365 }; 366 367 static driver_t msk_driver = { 368 "msk", 369 msk_methods, 370 sizeof(struct msk_if_softc) 371 }; 372 373 static devclass_t msk_devclass; 374 375 DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0); 376 DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0); 377 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0); 378 379 static struct resource_spec msk_res_spec_io[] = { 380 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 381 { -1, 0, 0 } 382 }; 383 384 static struct resource_spec msk_res_spec_mem[] = { 385 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 386 { -1, 0, 0 } 387 }; 388 389 static struct resource_spec msk_irq_spec_legacy[] = { 390 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 391 { -1, 0, 0 } 392 }; 393 394 static struct resource_spec msk_irq_spec_msi[] = { 395 { SYS_RES_IRQ, 1, RF_ACTIVE }, 396 { -1, 0, 0 } 397 }; 398 399 static int 400 msk_miibus_readreg(device_t dev, int phy, int reg) 401 { 402 struct msk_if_softc *sc_if; 403 404 sc_if = device_get_softc(dev); 405 406 return (msk_phy_readreg(sc_if, phy, reg)); 407 } 408 409 static int 410 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 411 { 412 struct msk_softc *sc; 413 int i, val; 414 415 sc = sc_if->msk_softc; 416 417 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 418 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 419 420 for (i = 0; i < MSK_TIMEOUT; i++) { 421 DELAY(1); 422 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 423 if ((val & GM_SMI_CT_RD_VAL) != 0) { 424 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 425 break; 426 } 427 } 428 429 if (i == MSK_TIMEOUT) { 430 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 431 val = 0; 432 } 433 434 return (val); 435 } 436 437 static int 438 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 439 { 440 struct msk_if_softc *sc_if; 441 442 sc_if = device_get_softc(dev); 443 444 return (msk_phy_writereg(sc_if, phy, reg, val)); 445 } 446 447 static int 448 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 449 { 450 struct msk_softc *sc; 451 int i; 452 453 sc = sc_if->msk_softc; 454 455 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 456 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 457 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 458 for (i = 0; i < MSK_TIMEOUT; i++) { 459 DELAY(1); 460 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 461 GM_SMI_CT_BUSY) == 0) 462 break; 463 } 464 if (i == MSK_TIMEOUT) 465 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 466 467 return (0); 468 } 469 470 static void 471 msk_miibus_statchg(device_t dev) 472 { 473 struct msk_softc *sc; 474 struct msk_if_softc *sc_if; 475 struct mii_data *mii; 476 struct ifnet *ifp; 477 uint32_t gmac; 478 479 sc_if = device_get_softc(dev); 480 sc = sc_if->msk_softc; 481 482 MSK_IF_LOCK_ASSERT(sc_if); 483 484 mii = device_get_softc(sc_if->msk_miibus); 485 ifp = sc_if->msk_ifp; 486 if (mii == NULL || ifp == NULL || 487 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 488 return; 489 490 sc_if->msk_flags &= ~MSK_FLAG_LINK; 491 if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) == 492 (IFM_AVALID | IFM_ACTIVE)) { 493 switch (IFM_SUBTYPE(mii->mii_media_active)) { 494 case IFM_10_T: 495 case IFM_100_TX: 496 sc_if->msk_flags |= MSK_FLAG_LINK; 497 break; 498 case IFM_1000_T: 499 case IFM_1000_SX: 500 case IFM_1000_LX: 501 case IFM_1000_CX: 502 if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0) 503 sc_if->msk_flags |= MSK_FLAG_LINK; 504 break; 505 default: 506 break; 507 } 508 } 509 510 if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) { 511 /* Enable Tx FIFO Underrun. */ 512 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 513 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 514 /* 515 * Because mii(4) notify msk(4) that it detected link status 516 * change, there is no need to enable automatic 517 * speed/flow-control/duplex updates. 518 */ 519 gmac = GM_GPCR_AU_ALL_DIS; 520 switch (IFM_SUBTYPE(mii->mii_media_active)) { 521 case IFM_1000_SX: 522 case IFM_1000_T: 523 gmac |= GM_GPCR_SPEED_1000; 524 break; 525 case IFM_100_TX: 526 gmac |= GM_GPCR_SPEED_100; 527 break; 528 case IFM_10_T: 529 break; 530 } 531 532 if ((IFM_OPTIONS(mii->mii_media_active) & 533 IFM_ETH_RXPAUSE) == 0) 534 gmac |= GM_GPCR_FC_RX_DIS; 535 if ((IFM_OPTIONS(mii->mii_media_active) & 536 IFM_ETH_TXPAUSE) == 0) 537 gmac |= GM_GPCR_FC_TX_DIS; 538 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) 539 gmac |= GM_GPCR_DUP_FULL; 540 else 541 gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS; 542 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 543 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 544 /* Read again to ensure writing. */ 545 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 546 gmac = GMC_PAUSE_OFF; 547 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 548 if ((IFM_OPTIONS(mii->mii_media_active) & 549 IFM_ETH_RXPAUSE) != 0) 550 gmac = GMC_PAUSE_ON; 551 } 552 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 553 554 /* Enable PHY interrupt for FIFO underrun/overflow. */ 555 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 556 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 557 } else { 558 /* 559 * Link state changed to down. 560 * Disable PHY interrupts. 561 */ 562 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 563 /* Disable Rx/Tx MAC. */ 564 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 565 if ((GM_GPCR_RX_ENA | GM_GPCR_TX_ENA) != 0) { 566 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 567 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 568 /* Read again to ensure writing. */ 569 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 570 } 571 } 572 } 573 574 static void 575 msk_rxfilter(struct msk_if_softc *sc_if) 576 { 577 struct msk_softc *sc; 578 struct ifnet *ifp; 579 struct ifmultiaddr *ifma; 580 uint32_t mchash[2]; 581 uint32_t crc; 582 uint16_t mode; 583 584 sc = sc_if->msk_softc; 585 586 MSK_IF_LOCK_ASSERT(sc_if); 587 588 ifp = sc_if->msk_ifp; 589 590 bzero(mchash, sizeof(mchash)); 591 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 592 if ((ifp->if_flags & IFF_PROMISC) != 0) 593 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 594 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 595 mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA; 596 mchash[0] = 0xffff; 597 mchash[1] = 0xffff; 598 } else { 599 mode |= GM_RXCR_UCF_ENA; 600 if_maddr_rlock(ifp); 601 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 602 if (ifma->ifma_addr->sa_family != AF_LINK) 603 continue; 604 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 605 ifma->ifma_addr), ETHER_ADDR_LEN); 606 /* Just want the 6 least significant bits. */ 607 crc &= 0x3f; 608 /* Set the corresponding bit in the hash table. */ 609 mchash[crc >> 5] |= 1 << (crc & 0x1f); 610 } 611 if_maddr_runlock(ifp); 612 if (mchash[0] != 0 || mchash[1] != 0) 613 mode |= GM_RXCR_MCF_ENA; 614 } 615 616 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 617 mchash[0] & 0xffff); 618 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 619 (mchash[0] >> 16) & 0xffff); 620 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 621 mchash[1] & 0xffff); 622 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 623 (mchash[1] >> 16) & 0xffff); 624 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 625 } 626 627 static void 628 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 629 { 630 struct msk_softc *sc; 631 632 sc = sc_if->msk_softc; 633 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 634 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 635 RX_VLAN_STRIP_ON); 636 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 637 TX_VLAN_TAG_ON); 638 } else { 639 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 640 RX_VLAN_STRIP_OFF); 641 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 642 TX_VLAN_TAG_OFF); 643 } 644 } 645 646 static int 647 msk_rx_fill(struct msk_if_softc *sc_if, int jumbo) 648 { 649 uint16_t idx; 650 int i; 651 652 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 653 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 654 /* Wait until controller executes OP_TCPSTART command. */ 655 for (i = 10; i > 0; i--) { 656 DELAY(10); 657 idx = CSR_READ_2(sc_if->msk_softc, 658 Y2_PREF_Q_ADDR(sc_if->msk_rxq, 659 PREF_UNIT_GET_IDX_REG)); 660 if (idx != 0) 661 break; 662 } 663 if (i == 0) { 664 device_printf(sc_if->msk_if_dev, 665 "prefetch unit stuck?\n"); 666 return (ETIMEDOUT); 667 } 668 /* 669 * Fill consumed LE with free buffer. This can be done 670 * in Rx handler but we don't want to add special code 671 * in fast handler. 672 */ 673 if (jumbo > 0) { 674 if (msk_jumbo_newbuf(sc_if, 0) != 0) 675 return (ENOBUFS); 676 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 677 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 678 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 679 } else { 680 if (msk_newbuf(sc_if, 0) != 0) 681 return (ENOBUFS); 682 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 683 sc_if->msk_cdata.msk_rx_ring_map, 684 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 685 } 686 sc_if->msk_cdata.msk_rx_prod = 0; 687 CSR_WRITE_2(sc_if->msk_softc, 688 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 689 sc_if->msk_cdata.msk_rx_prod); 690 } 691 return (0); 692 } 693 694 static int 695 msk_init_rx_ring(struct msk_if_softc *sc_if) 696 { 697 struct msk_ring_data *rd; 698 struct msk_rxdesc *rxd; 699 int i, prod; 700 701 MSK_IF_LOCK_ASSERT(sc_if); 702 703 sc_if->msk_cdata.msk_rx_cons = 0; 704 sc_if->msk_cdata.msk_rx_prod = 0; 705 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 706 707 rd = &sc_if->msk_rdata; 708 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 709 prod = sc_if->msk_cdata.msk_rx_prod; 710 i = 0; 711 /* Have controller know how to compute Rx checksum. */ 712 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 713 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 714 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 715 rxd->rx_m = NULL; 716 rxd->rx_le = &rd->msk_rx_ring[prod]; 717 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 718 ETHER_HDR_LEN); 719 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 720 MSK_INC(prod, MSK_RX_RING_CNT); 721 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 722 i++; 723 } 724 for (; i < MSK_RX_RING_CNT; i++) { 725 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 726 rxd->rx_m = NULL; 727 rxd->rx_le = &rd->msk_rx_ring[prod]; 728 if (msk_newbuf(sc_if, prod) != 0) 729 return (ENOBUFS); 730 MSK_INC(prod, MSK_RX_RING_CNT); 731 } 732 733 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 734 sc_if->msk_cdata.msk_rx_ring_map, 735 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 736 737 /* Update prefetch unit. */ 738 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1; 739 CSR_WRITE_2(sc_if->msk_softc, 740 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 741 sc_if->msk_cdata.msk_rx_prod); 742 if (msk_rx_fill(sc_if, 0) != 0) 743 return (ENOBUFS); 744 return (0); 745 } 746 747 static int 748 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 749 { 750 struct msk_ring_data *rd; 751 struct msk_rxdesc *rxd; 752 int i, prod; 753 754 MSK_IF_LOCK_ASSERT(sc_if); 755 756 sc_if->msk_cdata.msk_rx_cons = 0; 757 sc_if->msk_cdata.msk_rx_prod = 0; 758 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 759 760 rd = &sc_if->msk_rdata; 761 bzero(rd->msk_jumbo_rx_ring, 762 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 763 prod = sc_if->msk_cdata.msk_rx_prod; 764 i = 0; 765 /* Have controller know how to compute Rx checksum. */ 766 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 767 (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) { 768 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 769 rxd->rx_m = NULL; 770 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 771 rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 | 772 ETHER_HDR_LEN); 773 rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER); 774 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 775 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 776 i++; 777 } 778 for (; i < MSK_JUMBO_RX_RING_CNT; i++) { 779 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 780 rxd->rx_m = NULL; 781 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 782 if (msk_jumbo_newbuf(sc_if, prod) != 0) 783 return (ENOBUFS); 784 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 785 } 786 787 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 788 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 789 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 790 791 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1; 792 CSR_WRITE_2(sc_if->msk_softc, 793 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 794 sc_if->msk_cdata.msk_rx_prod); 795 if (msk_rx_fill(sc_if, 1) != 0) 796 return (ENOBUFS); 797 return (0); 798 } 799 800 static void 801 msk_init_tx_ring(struct msk_if_softc *sc_if) 802 { 803 struct msk_ring_data *rd; 804 struct msk_txdesc *txd; 805 int i; 806 807 sc_if->msk_cdata.msk_tso_mtu = 0; 808 sc_if->msk_cdata.msk_last_csum = 0; 809 sc_if->msk_cdata.msk_tx_prod = 0; 810 sc_if->msk_cdata.msk_tx_cons = 0; 811 sc_if->msk_cdata.msk_tx_cnt = 0; 812 813 rd = &sc_if->msk_rdata; 814 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 815 for (i = 0; i < MSK_TX_RING_CNT; i++) { 816 txd = &sc_if->msk_cdata.msk_txdesc[i]; 817 txd->tx_m = NULL; 818 txd->tx_le = &rd->msk_tx_ring[i]; 819 } 820 821 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 822 sc_if->msk_cdata.msk_tx_ring_map, 823 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 824 } 825 826 static __inline void 827 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 828 { 829 struct msk_rx_desc *rx_le; 830 struct msk_rxdesc *rxd; 831 struct mbuf *m; 832 833 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 834 m = rxd->rx_m; 835 rx_le = rxd->rx_le; 836 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 837 } 838 839 static __inline void 840 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 841 { 842 struct msk_rx_desc *rx_le; 843 struct msk_rxdesc *rxd; 844 struct mbuf *m; 845 846 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 847 m = rxd->rx_m; 848 rx_le = rxd->rx_le; 849 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 850 } 851 852 static int 853 msk_newbuf(struct msk_if_softc *sc_if, int idx) 854 { 855 struct msk_rx_desc *rx_le; 856 struct msk_rxdesc *rxd; 857 struct mbuf *m; 858 bus_dma_segment_t segs[1]; 859 bus_dmamap_t map; 860 int nsegs; 861 862 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 863 if (m == NULL) 864 return (ENOBUFS); 865 866 m->m_len = m->m_pkthdr.len = MCLBYTES; 867 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 868 m_adj(m, ETHER_ALIGN); 869 #ifndef __NO_STRICT_ALIGNMENT 870 else 871 m_adj(m, MSK_RX_BUF_ALIGN); 872 #endif 873 874 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 875 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 876 BUS_DMA_NOWAIT) != 0) { 877 m_freem(m); 878 return (ENOBUFS); 879 } 880 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 881 882 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 883 if (rxd->rx_m != NULL) { 884 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 885 BUS_DMASYNC_POSTREAD); 886 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 887 } 888 map = rxd->rx_dmamap; 889 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 890 sc_if->msk_cdata.msk_rx_sparemap = map; 891 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 892 BUS_DMASYNC_PREREAD); 893 rxd->rx_m = m; 894 rx_le = rxd->rx_le; 895 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 896 rx_le->msk_control = 897 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 898 899 return (0); 900 } 901 902 static int 903 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 904 { 905 struct msk_rx_desc *rx_le; 906 struct msk_rxdesc *rxd; 907 struct mbuf *m; 908 bus_dma_segment_t segs[1]; 909 bus_dmamap_t map; 910 int nsegs; 911 912 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 913 if (m == NULL) 914 return (ENOBUFS); 915 if ((m->m_flags & M_EXT) == 0) { 916 m_freem(m); 917 return (ENOBUFS); 918 } 919 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 920 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 921 m_adj(m, ETHER_ALIGN); 922 #ifndef __NO_STRICT_ALIGNMENT 923 else 924 m_adj(m, MSK_RX_BUF_ALIGN); 925 #endif 926 927 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 928 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 929 BUS_DMA_NOWAIT) != 0) { 930 m_freem(m); 931 return (ENOBUFS); 932 } 933 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 934 935 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 936 if (rxd->rx_m != NULL) { 937 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 938 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 939 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 940 rxd->rx_dmamap); 941 } 942 map = rxd->rx_dmamap; 943 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 944 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 945 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 946 BUS_DMASYNC_PREREAD); 947 rxd->rx_m = m; 948 rx_le = rxd->rx_le; 949 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 950 rx_le->msk_control = 951 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 952 953 return (0); 954 } 955 956 /* 957 * Set media options. 958 */ 959 static int 960 msk_mediachange(struct ifnet *ifp) 961 { 962 struct msk_if_softc *sc_if; 963 struct mii_data *mii; 964 int error; 965 966 sc_if = ifp->if_softc; 967 968 MSK_IF_LOCK(sc_if); 969 mii = device_get_softc(sc_if->msk_miibus); 970 error = mii_mediachg(mii); 971 MSK_IF_UNLOCK(sc_if); 972 973 return (error); 974 } 975 976 /* 977 * Report current media status. 978 */ 979 static void 980 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 981 { 982 struct msk_if_softc *sc_if; 983 struct mii_data *mii; 984 985 sc_if = ifp->if_softc; 986 MSK_IF_LOCK(sc_if); 987 if ((ifp->if_flags & IFF_UP) == 0) { 988 MSK_IF_UNLOCK(sc_if); 989 return; 990 } 991 mii = device_get_softc(sc_if->msk_miibus); 992 993 mii_pollstat(mii); 994 MSK_IF_UNLOCK(sc_if); 995 ifmr->ifm_active = mii->mii_media_active; 996 ifmr->ifm_status = mii->mii_media_status; 997 } 998 999 static int 1000 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1001 { 1002 struct msk_if_softc *sc_if; 1003 struct ifreq *ifr; 1004 struct mii_data *mii; 1005 int error, mask, reinit; 1006 1007 sc_if = ifp->if_softc; 1008 ifr = (struct ifreq *)data; 1009 error = 0; 1010 1011 switch(command) { 1012 case SIOCSIFMTU: 1013 MSK_IF_LOCK(sc_if); 1014 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) 1015 error = EINVAL; 1016 else if (ifp->if_mtu != ifr->ifr_mtu) { 1017 if (ifr->ifr_mtu > ETHERMTU) { 1018 if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 1019 error = EINVAL; 1020 MSK_IF_UNLOCK(sc_if); 1021 break; 1022 } 1023 if ((sc_if->msk_flags & 1024 MSK_FLAG_JUMBO_NOCSUM) != 0) { 1025 ifp->if_hwassist &= 1026 ~(MSK_CSUM_FEATURES | CSUM_TSO); 1027 ifp->if_capenable &= 1028 ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1029 VLAN_CAPABILITIES(ifp); 1030 } 1031 } 1032 ifp->if_mtu = ifr->ifr_mtu; 1033 msk_init_locked(sc_if); 1034 } 1035 MSK_IF_UNLOCK(sc_if); 1036 break; 1037 case SIOCSIFFLAGS: 1038 MSK_IF_LOCK(sc_if); 1039 if ((ifp->if_flags & IFF_UP) != 0) { 1040 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 1041 ((ifp->if_flags ^ sc_if->msk_if_flags) & 1042 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1043 msk_rxfilter(sc_if); 1044 else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0) 1045 msk_init_locked(sc_if); 1046 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1047 msk_stop(sc_if); 1048 sc_if->msk_if_flags = ifp->if_flags; 1049 MSK_IF_UNLOCK(sc_if); 1050 break; 1051 case SIOCADDMULTI: 1052 case SIOCDELMULTI: 1053 MSK_IF_LOCK(sc_if); 1054 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1055 msk_rxfilter(sc_if); 1056 MSK_IF_UNLOCK(sc_if); 1057 break; 1058 case SIOCGIFMEDIA: 1059 case SIOCSIFMEDIA: 1060 mii = device_get_softc(sc_if->msk_miibus); 1061 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1062 break; 1063 case SIOCSIFCAP: 1064 reinit = 0; 1065 MSK_IF_LOCK(sc_if); 1066 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1067 if ((mask & IFCAP_TXCSUM) != 0 && 1068 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) { 1069 ifp->if_capenable ^= IFCAP_TXCSUM; 1070 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0) 1071 ifp->if_hwassist |= MSK_CSUM_FEATURES; 1072 else 1073 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 1074 } 1075 if ((mask & IFCAP_RXCSUM) != 0 && 1076 (IFCAP_RXCSUM & ifp->if_capabilities) != 0) { 1077 ifp->if_capenable ^= IFCAP_RXCSUM; 1078 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0) 1079 reinit = 1; 1080 } 1081 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1082 (IFCAP_VLAN_HWCSUM & ifp->if_capabilities) != 0) 1083 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1084 if ((mask & IFCAP_TSO4) != 0 && 1085 (IFCAP_TSO4 & ifp->if_capabilities) != 0) { 1086 ifp->if_capenable ^= IFCAP_TSO4; 1087 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 1088 ifp->if_hwassist |= CSUM_TSO; 1089 else 1090 ifp->if_hwassist &= ~CSUM_TSO; 1091 } 1092 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1093 (IFCAP_VLAN_HWTSO & ifp->if_capabilities) != 0) 1094 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1095 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1096 (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) { 1097 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1098 if ((IFCAP_VLAN_HWTAGGING & ifp->if_capenable) == 0) 1099 ifp->if_capenable &= 1100 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 1101 msk_setvlan(sc_if, ifp); 1102 } 1103 if (ifp->if_mtu > ETHERMTU && 1104 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 1105 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 1106 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1107 } 1108 VLAN_CAPABILITIES(ifp); 1109 if (reinit > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1110 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1111 msk_init_locked(sc_if); 1112 } 1113 MSK_IF_UNLOCK(sc_if); 1114 break; 1115 default: 1116 error = ether_ioctl(ifp, command, data); 1117 break; 1118 } 1119 1120 return (error); 1121 } 1122 1123 static int 1124 mskc_probe(device_t dev) 1125 { 1126 struct msk_product *mp; 1127 uint16_t vendor, devid; 1128 int i; 1129 1130 vendor = pci_get_vendor(dev); 1131 devid = pci_get_device(dev); 1132 mp = msk_products; 1133 for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]); 1134 i++, mp++) { 1135 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1136 device_set_desc(dev, mp->msk_name); 1137 return (BUS_PROBE_DEFAULT); 1138 } 1139 } 1140 1141 return (ENXIO); 1142 } 1143 1144 static int 1145 mskc_setup_rambuffer(struct msk_softc *sc) 1146 { 1147 int next; 1148 int i; 1149 1150 /* Get adapter SRAM size. */ 1151 sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4; 1152 if (bootverbose) 1153 device_printf(sc->msk_dev, 1154 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1155 if (sc->msk_ramsize == 0) 1156 return (0); 1157 1158 sc->msk_pflags |= MSK_FLAG_RAMBUF; 1159 /* 1160 * Give receiver 2/3 of memory and round down to the multiple 1161 * of 1024. Tx/Rx RAM buffer size of Yukon II should be multiple 1162 * of 1024. 1163 */ 1164 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1165 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1166 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1167 sc->msk_rxqstart[i] = next; 1168 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1169 next = sc->msk_rxqend[i] + 1; 1170 sc->msk_txqstart[i] = next; 1171 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1172 next = sc->msk_txqend[i] + 1; 1173 if (bootverbose) { 1174 device_printf(sc->msk_dev, 1175 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1176 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1177 sc->msk_rxqend[i]); 1178 device_printf(sc->msk_dev, 1179 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1180 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1181 sc->msk_txqend[i]); 1182 } 1183 } 1184 1185 return (0); 1186 } 1187 1188 static void 1189 msk_phy_power(struct msk_softc *sc, int mode) 1190 { 1191 uint32_t our, val; 1192 int i; 1193 1194 switch (mode) { 1195 case MSK_PHY_POWERUP: 1196 /* Switch power to VCC (WA for VAUX problem). */ 1197 CSR_WRITE_1(sc, B0_POWER_CTRL, 1198 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1199 /* Disable Core Clock Division, set Clock Select to 0. */ 1200 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1201 1202 val = 0; 1203 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1204 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1205 /* Enable bits are inverted. */ 1206 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1207 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1208 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1209 } 1210 /* 1211 * Enable PCI & Core Clock, enable clock gating for both Links. 1212 */ 1213 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1214 1215 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1216 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1217 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 1218 if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1219 /* Deassert Low Power for 1st PHY. */ 1220 val |= PCI_Y2_PHY1_COMA; 1221 if (sc->msk_num_port > 1) 1222 val |= PCI_Y2_PHY2_COMA; 1223 } 1224 } 1225 /* Release PHY from PowerDown/COMA mode. */ 1226 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1227 switch (sc->msk_hw_id) { 1228 case CHIP_ID_YUKON_EC_U: 1229 case CHIP_ID_YUKON_EX: 1230 case CHIP_ID_YUKON_FE_P: 1231 case CHIP_ID_YUKON_UL_2: 1232 case CHIP_ID_YUKON_OPT: 1233 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF); 1234 1235 /* Enable all clocks. */ 1236 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); 1237 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_4); 1238 our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN| 1239 PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST); 1240 /* Set all bits to 0 except bits 15..12. */ 1241 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, our); 1242 our = CSR_PCI_READ_4(sc, PCI_OUR_REG_5); 1243 our &= PCI_CTL_TIM_VMAIN_AV_MSK; 1244 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, our); 1245 CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0); 1246 /* 1247 * Disable status race, workaround for 1248 * Yukon EC Ultra & Yukon EX. 1249 */ 1250 val = CSR_READ_4(sc, B2_GP_IO); 1251 val |= GLB_GPIO_STAT_RACE_DIS; 1252 CSR_WRITE_4(sc, B2_GP_IO, val); 1253 CSR_READ_4(sc, B2_GP_IO); 1254 break; 1255 default: 1256 break; 1257 } 1258 for (i = 0; i < sc->msk_num_port; i++) { 1259 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1260 GMLC_RST_SET); 1261 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1262 GMLC_RST_CLR); 1263 } 1264 break; 1265 case MSK_PHY_POWERDOWN: 1266 val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); 1267 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1268 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1269 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1270 val &= ~PCI_Y2_PHY1_COMA; 1271 if (sc->msk_num_port > 1) 1272 val &= ~PCI_Y2_PHY2_COMA; 1273 } 1274 CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); 1275 1276 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1277 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1278 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1279 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1280 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1281 /* Enable bits are inverted. */ 1282 val = 0; 1283 } 1284 /* 1285 * Disable PCI & Core Clock, disable clock gating for 1286 * both Links. 1287 */ 1288 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1289 CSR_WRITE_1(sc, B0_POWER_CTRL, 1290 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1291 break; 1292 default: 1293 break; 1294 } 1295 } 1296 1297 static void 1298 mskc_reset(struct msk_softc *sc) 1299 { 1300 bus_addr_t addr; 1301 uint16_t status; 1302 uint32_t val; 1303 int i; 1304 1305 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1306 1307 /* Disable ASF. */ 1308 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) { 1309 status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); 1310 /* Clear AHB bridge & microcontroller reset. */ 1311 status &= ~(Y2_ASF_HCU_CCSR_AHB_RST | 1312 Y2_ASF_HCU_CCSR_CPU_RST_MODE); 1313 /* Clear ASF microcontroller state. */ 1314 status &= ~ Y2_ASF_HCU_CCSR_UC_STATE_MSK; 1315 CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status); 1316 } else 1317 CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1318 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1319 1320 /* 1321 * Since we disabled ASF, S/W reset is required for Power Management. 1322 */ 1323 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1324 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1325 1326 /* Clear all error bits in the PCI status register. */ 1327 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1328 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1329 1330 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1331 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1332 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 1333 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1334 1335 switch (sc->msk_bustype) { 1336 case MSK_PEX_BUS: 1337 /* Clear all PEX errors. */ 1338 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1339 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1340 if ((val & PEX_RX_OV) != 0) { 1341 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1342 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1343 } 1344 break; 1345 case MSK_PCI_BUS: 1346 case MSK_PCIX_BUS: 1347 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1348 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1349 if (val == 0) 1350 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1351 if (sc->msk_bustype == MSK_PCIX_BUS) { 1352 /* Set Cache Line Size opt. */ 1353 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1354 val |= PCI_CLS_OPT; 1355 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1356 } 1357 break; 1358 } 1359 /* Set PHY power state. */ 1360 msk_phy_power(sc, MSK_PHY_POWERUP); 1361 1362 /* Reset GPHY/GMAC Control */ 1363 for (i = 0; i < sc->msk_num_port; i++) { 1364 /* GPHY Control reset. */ 1365 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1366 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1367 /* GMAC Control reset. */ 1368 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1369 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1370 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1371 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) 1372 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), 1373 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 1374 GMC_BYP_RETR_ON); 1375 } 1376 if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) { 1377 /* Disable PCIe PHY powerdown(reg 0x80, bit7). */ 1378 CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080); 1379 } 1380 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1381 1382 /* LED On. */ 1383 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1384 1385 /* Clear TWSI IRQ. */ 1386 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1387 1388 /* Turn off hardware timer. */ 1389 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1390 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1391 1392 /* Turn off descriptor polling. */ 1393 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1394 1395 /* Turn off time stamps. */ 1396 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1397 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1398 1399 /* Configure timeout values. */ 1400 for (i = 0; i < sc->msk_num_port; i++) { 1401 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1402 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1403 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1404 MSK_RI_TO_53); 1405 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1406 MSK_RI_TO_53); 1407 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1408 MSK_RI_TO_53); 1409 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1410 MSK_RI_TO_53); 1411 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1412 MSK_RI_TO_53); 1413 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1414 MSK_RI_TO_53); 1415 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1416 MSK_RI_TO_53); 1417 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1418 MSK_RI_TO_53); 1419 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1420 MSK_RI_TO_53); 1421 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1422 MSK_RI_TO_53); 1423 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1424 MSK_RI_TO_53); 1425 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1426 MSK_RI_TO_53); 1427 } 1428 1429 /* Disable all interrupts. */ 1430 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1431 CSR_READ_4(sc, B0_HWE_IMSK); 1432 CSR_WRITE_4(sc, B0_IMSK, 0); 1433 CSR_READ_4(sc, B0_IMSK); 1434 1435 /* 1436 * On dual port PCI-X card, there is an problem where status 1437 * can be received out of order due to split transactions. 1438 */ 1439 if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) { 1440 uint16_t pcix_cmd; 1441 1442 pcix_cmd = pci_read_config(sc->msk_dev, 1443 sc->msk_pcixcap + PCIXR_COMMAND, 2); 1444 /* Clear Max Outstanding Split Transactions. */ 1445 pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS; 1446 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1447 pci_write_config(sc->msk_dev, 1448 sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2); 1449 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1450 } 1451 if (sc->msk_expcap != 0) { 1452 /* Change Max. Read Request Size to 2048 bytes. */ 1453 if (pci_get_max_read_req(sc->msk_dev) == 512) 1454 pci_set_max_read_req(sc->msk_dev, 2048); 1455 } 1456 1457 /* Clear status list. */ 1458 bzero(sc->msk_stat_ring, 1459 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT); 1460 sc->msk_stat_cons = 0; 1461 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1462 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1463 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1464 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1465 /* Set the status list base address. */ 1466 addr = sc->msk_stat_ring_paddr; 1467 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1468 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1469 /* Set the status list last index. */ 1470 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1); 1471 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1472 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1473 /* WA for dev. #4.3 */ 1474 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1475 /* WA for dev. #4.18 */ 1476 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1477 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1478 } else { 1479 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1480 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1481 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1482 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1483 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1484 else 1485 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1486 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1487 } 1488 /* 1489 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1490 */ 1491 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1492 1493 /* Enable status unit. */ 1494 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1495 1496 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1497 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1498 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1499 } 1500 1501 static int 1502 msk_probe(device_t dev) 1503 { 1504 struct msk_softc *sc; 1505 char desc[100]; 1506 1507 sc = device_get_softc(device_get_parent(dev)); 1508 /* 1509 * Not much to do here. We always know there will be 1510 * at least one GMAC present, and if there are two, 1511 * mskc_attach() will create a second device instance 1512 * for us. 1513 */ 1514 snprintf(desc, sizeof(desc), 1515 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1516 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1517 sc->msk_hw_rev); 1518 device_set_desc_copy(dev, desc); 1519 1520 return (BUS_PROBE_DEFAULT); 1521 } 1522 1523 static int 1524 msk_attach(device_t dev) 1525 { 1526 struct msk_softc *sc; 1527 struct msk_if_softc *sc_if; 1528 struct ifnet *ifp; 1529 struct msk_mii_data *mmd; 1530 int i, port, error; 1531 uint8_t eaddr[6]; 1532 1533 if (dev == NULL) 1534 return (EINVAL); 1535 1536 error = 0; 1537 sc_if = device_get_softc(dev); 1538 sc = device_get_softc(device_get_parent(dev)); 1539 mmd = device_get_ivars(dev); 1540 port = mmd->port; 1541 1542 sc_if->msk_if_dev = dev; 1543 sc_if->msk_port = port; 1544 sc_if->msk_softc = sc; 1545 sc_if->msk_flags = sc->msk_pflags; 1546 sc->msk_if[port] = sc_if; 1547 /* Setup Tx/Rx queue register offsets. */ 1548 if (port == MSK_PORT_A) { 1549 sc_if->msk_txq = Q_XA1; 1550 sc_if->msk_txsq = Q_XS1; 1551 sc_if->msk_rxq = Q_R1; 1552 } else { 1553 sc_if->msk_txq = Q_XA2; 1554 sc_if->msk_txsq = Q_XS2; 1555 sc_if->msk_rxq = Q_R2; 1556 } 1557 1558 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1559 msk_sysctl_node(sc_if); 1560 1561 if ((error = msk_txrx_dma_alloc(sc_if) != 0)) 1562 goto fail; 1563 msk_rx_dma_jalloc(sc_if); 1564 1565 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1566 if (ifp == NULL) { 1567 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1568 error = ENOSPC; 1569 goto fail; 1570 } 1571 ifp->if_softc = sc_if; 1572 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1573 ifp->if_mtu = ETHERMTU; 1574 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1575 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1576 /* 1577 * Enable Rx checksum offloading if controller supports 1578 * new descriptor formant and controller is not Yukon XL. 1579 */ 1580 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 1581 sc->msk_hw_id != CHIP_ID_YUKON_XL) 1582 ifp->if_capabilities |= IFCAP_RXCSUM; 1583 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1584 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1585 ifp->if_capabilities |= IFCAP_RXCSUM; 1586 ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO; 1587 ifp->if_capenable = ifp->if_capabilities; 1588 ifp->if_ioctl = msk_ioctl; 1589 ifp->if_start = msk_start; 1590 ifp->if_init = msk_init; 1591 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1592 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1; 1593 IFQ_SET_READY(&ifp->if_snd); 1594 /* 1595 * Get station address for this interface. Note that 1596 * dual port cards actually come with three station 1597 * addresses: one for each port, plus an extra. The 1598 * extra one is used by the SysKonnect driver software 1599 * as a 'virtual' station address for when both ports 1600 * are operating in failover mode. Currently we don't 1601 * use this extra address. 1602 */ 1603 MSK_IF_LOCK(sc_if); 1604 for (i = 0; i < ETHER_ADDR_LEN; i++) 1605 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1606 1607 /* 1608 * Call MI attach routine. Can't hold locks when calling into ether_*. 1609 */ 1610 MSK_IF_UNLOCK(sc_if); 1611 ether_ifattach(ifp, eaddr); 1612 MSK_IF_LOCK(sc_if); 1613 1614 /* VLAN capability setup */ 1615 ifp->if_capabilities |= IFCAP_VLAN_MTU; 1616 if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) { 1617 /* 1618 * Due to Tx checksum offload hardware bugs, msk(4) manually 1619 * computes checksum for short frames. For VLAN tagged frames 1620 * this workaround does not work so disable checksum offload 1621 * for VLAN interface. 1622 */ 1623 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO; 1624 /* 1625 * Enable Rx checksum offloading for VLAN tagged frames 1626 * if controller support new descriptor format. 1627 */ 1628 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 && 1629 (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0) 1630 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1631 } 1632 ifp->if_capenable = ifp->if_capabilities; 1633 1634 /* 1635 * Tell the upper layer(s) we support long frames. 1636 * Must appear after the call to ether_ifattach() because 1637 * ether_ifattach() sets ifi_hdrlen to the default value. 1638 */ 1639 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1640 1641 /* 1642 * Do miibus setup. 1643 */ 1644 MSK_IF_UNLOCK(sc_if); 1645 error = mii_attach(dev, &sc_if->msk_miibus, ifp, msk_mediachange, 1646 msk_mediastatus, BMSR_DEFCAPMASK, PHY_ADDR_MARV, MII_OFFSET_ANY, 1647 mmd->mii_flags); 1648 if (error != 0) { 1649 device_printf(sc_if->msk_if_dev, "attaching PHYs failed\n"); 1650 ether_ifdetach(ifp); 1651 error = ENXIO; 1652 goto fail; 1653 } 1654 1655 fail: 1656 if (error != 0) { 1657 /* Access should be ok even though lock has been dropped */ 1658 sc->msk_if[port] = NULL; 1659 msk_detach(dev); 1660 } 1661 1662 return (error); 1663 } 1664 1665 /* 1666 * Attach the interface. Allocate softc structures, do ifmedia 1667 * setup and ethernet/BPF attach. 1668 */ 1669 static int 1670 mskc_attach(device_t dev) 1671 { 1672 struct msk_softc *sc; 1673 struct msk_mii_data *mmd; 1674 int error, msic, msir, reg; 1675 1676 sc = device_get_softc(dev); 1677 sc->msk_dev = dev; 1678 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1679 MTX_DEF); 1680 1681 /* 1682 * Map control/status registers. 1683 */ 1684 pci_enable_busmaster(dev); 1685 1686 /* Allocate I/O resource */ 1687 #ifdef MSK_USEIOSPACE 1688 sc->msk_res_spec = msk_res_spec_io; 1689 #else 1690 sc->msk_res_spec = msk_res_spec_mem; 1691 #endif 1692 sc->msk_irq_spec = msk_irq_spec_legacy; 1693 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1694 if (error) { 1695 if (sc->msk_res_spec == msk_res_spec_mem) 1696 sc->msk_res_spec = msk_res_spec_io; 1697 else 1698 sc->msk_res_spec = msk_res_spec_mem; 1699 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1700 if (error) { 1701 device_printf(dev, "couldn't allocate %s resources\n", 1702 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1703 "I/O"); 1704 mtx_destroy(&sc->msk_mtx); 1705 return (ENXIO); 1706 } 1707 } 1708 1709 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1710 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1711 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1712 /* Bail out if chip is not recognized. */ 1713 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1714 sc->msk_hw_id > CHIP_ID_YUKON_OPT || 1715 sc->msk_hw_id == CHIP_ID_YUKON_SUPR || 1716 sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) { 1717 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1718 sc->msk_hw_id, sc->msk_hw_rev); 1719 mtx_destroy(&sc->msk_mtx); 1720 return (ENXIO); 1721 } 1722 1723 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1724 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1725 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 1726 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1727 "max number of Rx events to process"); 1728 1729 sc->msk_process_limit = MSK_PROC_DEFAULT; 1730 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1731 "process_limit", &sc->msk_process_limit); 1732 if (error == 0) { 1733 if (sc->msk_process_limit < MSK_PROC_MIN || 1734 sc->msk_process_limit > MSK_PROC_MAX) { 1735 device_printf(dev, "process_limit value out of range; " 1736 "using default: %d\n", MSK_PROC_DEFAULT); 1737 sc->msk_process_limit = MSK_PROC_DEFAULT; 1738 } 1739 } 1740 1741 sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT; 1742 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 1743 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 1744 "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0, 1745 "Maximum number of time to delay interrupts"); 1746 resource_int_value(device_get_name(dev), device_get_unit(dev), 1747 "int_holdoff", &sc->msk_int_holdoff); 1748 1749 /* Soft reset. */ 1750 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1751 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1752 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1753 /* Check number of MACs. */ 1754 sc->msk_num_port = 1; 1755 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1756 CFG_DUAL_MAC_MSK) { 1757 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1758 sc->msk_num_port++; 1759 } 1760 1761 /* Check bus type. */ 1762 if (pci_find_cap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) { 1763 sc->msk_bustype = MSK_PEX_BUS; 1764 sc->msk_expcap = reg; 1765 } else if (pci_find_cap(sc->msk_dev, PCIY_PCIX, ®) == 0) { 1766 sc->msk_bustype = MSK_PCIX_BUS; 1767 sc->msk_pcixcap = reg; 1768 } else 1769 sc->msk_bustype = MSK_PCI_BUS; 1770 1771 switch (sc->msk_hw_id) { 1772 case CHIP_ID_YUKON_EC: 1773 sc->msk_clock = 125; /* 125 MHz */ 1774 sc->msk_pflags |= MSK_FLAG_JUMBO; 1775 break; 1776 case CHIP_ID_YUKON_EC_U: 1777 sc->msk_clock = 125; /* 125 MHz */ 1778 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM; 1779 break; 1780 case CHIP_ID_YUKON_EX: 1781 sc->msk_clock = 125; /* 125 MHz */ 1782 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 | 1783 MSK_FLAG_AUTOTX_CSUM; 1784 /* 1785 * Yukon Extreme seems to have silicon bug for 1786 * automatic Tx checksum calculation capability. 1787 */ 1788 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 1789 sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM; 1790 /* 1791 * Yukon Extreme A0 could not use store-and-forward 1792 * for jumbo frames, so disable Tx checksum 1793 * offloading for jumbo frames. 1794 */ 1795 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 1796 sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM; 1797 break; 1798 case CHIP_ID_YUKON_FE: 1799 sc->msk_clock = 100; /* 100 MHz */ 1800 sc->msk_pflags |= MSK_FLAG_FASTETHER; 1801 break; 1802 case CHIP_ID_YUKON_FE_P: 1803 sc->msk_clock = 50; /* 50 MHz */ 1804 sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 | 1805 MSK_FLAG_AUTOTX_CSUM; 1806 if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 1807 /* 1808 * XXX 1809 * FE+ A0 has status LE writeback bug so msk(4) 1810 * does not rely on status word of received frame 1811 * in msk_rxeof() which in turn disables all 1812 * hardware assistance bits reported by the status 1813 * word as well as validity of the received frame. 1814 * Just pass received frames to upper stack with 1815 * minimal test and let upper stack handle them. 1816 */ 1817 sc->msk_pflags |= MSK_FLAG_NOHWVLAN | 1818 MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM; 1819 } 1820 break; 1821 case CHIP_ID_YUKON_XL: 1822 sc->msk_clock = 156; /* 156 MHz */ 1823 sc->msk_pflags |= MSK_FLAG_JUMBO; 1824 break; 1825 case CHIP_ID_YUKON_UL_2: 1826 sc->msk_clock = 125; /* 125 MHz */ 1827 sc->msk_pflags |= MSK_FLAG_JUMBO; 1828 break; 1829 case CHIP_ID_YUKON_OPT: 1830 sc->msk_clock = 125; /* 125 MHz */ 1831 sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2; 1832 break; 1833 default: 1834 sc->msk_clock = 156; /* 156 MHz */ 1835 break; 1836 } 1837 1838 /* Allocate IRQ resources. */ 1839 msic = pci_msi_count(dev); 1840 if (bootverbose) 1841 device_printf(dev, "MSI count : %d\n", msic); 1842 if (legacy_intr != 0) 1843 msi_disable = 1; 1844 if (msi_disable == 0 && msic > 0) { 1845 msir = 1; 1846 if (pci_alloc_msi(dev, &msir) == 0) { 1847 if (msir == 1) { 1848 sc->msk_pflags |= MSK_FLAG_MSI; 1849 sc->msk_irq_spec = msk_irq_spec_msi; 1850 } else 1851 pci_release_msi(dev); 1852 } 1853 } 1854 1855 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1856 if (error) { 1857 device_printf(dev, "couldn't allocate IRQ resources\n"); 1858 goto fail; 1859 } 1860 1861 if ((error = msk_status_dma_alloc(sc)) != 0) 1862 goto fail; 1863 1864 /* Set base interrupt mask. */ 1865 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1866 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1867 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1868 1869 /* Reset the adapter. */ 1870 mskc_reset(sc); 1871 1872 if ((error = mskc_setup_rambuffer(sc)) != 0) 1873 goto fail; 1874 1875 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1876 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1877 device_printf(dev, "failed to add child for PORT_A\n"); 1878 error = ENXIO; 1879 goto fail; 1880 } 1881 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1882 if (mmd == NULL) { 1883 device_printf(dev, "failed to allocate memory for " 1884 "ivars of PORT_A\n"); 1885 error = ENXIO; 1886 goto fail; 1887 } 1888 mmd->port = MSK_PORT_A; 1889 mmd->pmd = sc->msk_pmd; 1890 mmd->mii_flags |= MIIF_DOPAUSE; 1891 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1892 mmd->mii_flags |= MIIF_HAVEFIBER; 1893 if (sc->msk_pmd == 'P') 1894 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1895 device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd); 1896 1897 if (sc->msk_num_port > 1) { 1898 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1899 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1900 device_printf(dev, "failed to add child for PORT_B\n"); 1901 error = ENXIO; 1902 goto fail; 1903 } 1904 mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO); 1905 if (mmd == NULL) { 1906 device_printf(dev, "failed to allocate memory for " 1907 "ivars of PORT_B\n"); 1908 error = ENXIO; 1909 goto fail; 1910 } 1911 mmd->port = MSK_PORT_B; 1912 mmd->pmd = sc->msk_pmd; 1913 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1914 mmd->mii_flags |= MIIF_HAVEFIBER; 1915 if (sc->msk_pmd == 'P') 1916 mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0; 1917 device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd); 1918 } 1919 1920 error = bus_generic_attach(dev); 1921 if (error) { 1922 device_printf(dev, "failed to attach port(s)\n"); 1923 goto fail; 1924 } 1925 1926 /* Hook interrupt last to avoid having to lock softc. */ 1927 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1928 INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand); 1929 if (error != 0) { 1930 device_printf(dev, "couldn't set up interrupt handler\n"); 1931 goto fail; 1932 } 1933 fail: 1934 if (error != 0) 1935 mskc_detach(dev); 1936 1937 return (error); 1938 } 1939 1940 /* 1941 * Shutdown hardware and free up resources. This can be called any 1942 * time after the mutex has been initialized. It is called in both 1943 * the error case in attach and the normal detach case so it needs 1944 * to be careful about only freeing resources that have actually been 1945 * allocated. 1946 */ 1947 static int 1948 msk_detach(device_t dev) 1949 { 1950 struct msk_softc *sc; 1951 struct msk_if_softc *sc_if; 1952 struct ifnet *ifp; 1953 1954 sc_if = device_get_softc(dev); 1955 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 1956 ("msk mutex not initialized in msk_detach")); 1957 MSK_IF_LOCK(sc_if); 1958 1959 ifp = sc_if->msk_ifp; 1960 if (device_is_attached(dev)) { 1961 /* XXX */ 1962 sc_if->msk_flags |= MSK_FLAG_DETACH; 1963 msk_stop(sc_if); 1964 /* Can't hold locks while calling detach. */ 1965 MSK_IF_UNLOCK(sc_if); 1966 callout_drain(&sc_if->msk_tick_ch); 1967 if (ifp) 1968 ether_ifdetach(ifp); 1969 MSK_IF_LOCK(sc_if); 1970 } 1971 1972 /* 1973 * We're generally called from mskc_detach() which is using 1974 * device_delete_child() to get to here. It's already trashed 1975 * miibus for us, so don't do it here or we'll panic. 1976 * 1977 * if (sc_if->msk_miibus != NULL) { 1978 * device_delete_child(dev, sc_if->msk_miibus); 1979 * sc_if->msk_miibus = NULL; 1980 * } 1981 */ 1982 1983 msk_rx_dma_jfree(sc_if); 1984 msk_txrx_dma_free(sc_if); 1985 bus_generic_detach(dev); 1986 1987 if (ifp) 1988 if_free(ifp); 1989 sc = sc_if->msk_softc; 1990 sc->msk_if[sc_if->msk_port] = NULL; 1991 MSK_IF_UNLOCK(sc_if); 1992 1993 return (0); 1994 } 1995 1996 static int 1997 mskc_detach(device_t dev) 1998 { 1999 struct msk_softc *sc; 2000 2001 sc = device_get_softc(dev); 2002 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 2003 2004 if (device_is_alive(dev)) { 2005 if (sc->msk_devs[MSK_PORT_A] != NULL) { 2006 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 2007 M_DEVBUF); 2008 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 2009 } 2010 if (sc->msk_devs[MSK_PORT_B] != NULL) { 2011 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 2012 M_DEVBUF); 2013 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 2014 } 2015 bus_generic_detach(dev); 2016 } 2017 2018 /* Disable all interrupts. */ 2019 CSR_WRITE_4(sc, B0_IMSK, 0); 2020 CSR_READ_4(sc, B0_IMSK); 2021 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2022 CSR_READ_4(sc, B0_HWE_IMSK); 2023 2024 /* LED Off. */ 2025 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 2026 2027 /* Put hardware reset. */ 2028 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2029 2030 msk_status_dma_free(sc); 2031 2032 if (sc->msk_intrhand) { 2033 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand); 2034 sc->msk_intrhand = NULL; 2035 } 2036 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 2037 if ((sc->msk_pflags & MSK_FLAG_MSI) != 0) 2038 pci_release_msi(dev); 2039 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 2040 mtx_destroy(&sc->msk_mtx); 2041 2042 return (0); 2043 } 2044 2045 struct msk_dmamap_arg { 2046 bus_addr_t msk_busaddr; 2047 }; 2048 2049 static void 2050 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 2051 { 2052 struct msk_dmamap_arg *ctx; 2053 2054 if (error != 0) 2055 return; 2056 ctx = arg; 2057 ctx->msk_busaddr = segs[0].ds_addr; 2058 } 2059 2060 /* Create status DMA region. */ 2061 static int 2062 msk_status_dma_alloc(struct msk_softc *sc) 2063 { 2064 struct msk_dmamap_arg ctx; 2065 int error; 2066 2067 error = bus_dma_tag_create( 2068 bus_get_dma_tag(sc->msk_dev), /* parent */ 2069 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 2070 BUS_SPACE_MAXADDR, /* lowaddr */ 2071 BUS_SPACE_MAXADDR, /* highaddr */ 2072 NULL, NULL, /* filter, filterarg */ 2073 MSK_STAT_RING_SZ, /* maxsize */ 2074 1, /* nsegments */ 2075 MSK_STAT_RING_SZ, /* maxsegsize */ 2076 0, /* flags */ 2077 NULL, NULL, /* lockfunc, lockarg */ 2078 &sc->msk_stat_tag); 2079 if (error != 0) { 2080 device_printf(sc->msk_dev, 2081 "failed to create status DMA tag\n"); 2082 return (error); 2083 } 2084 2085 /* Allocate DMA'able memory and load the DMA map for status ring. */ 2086 error = bus_dmamem_alloc(sc->msk_stat_tag, 2087 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 2088 BUS_DMA_ZERO, &sc->msk_stat_map); 2089 if (error != 0) { 2090 device_printf(sc->msk_dev, 2091 "failed to allocate DMA'able memory for status ring\n"); 2092 return (error); 2093 } 2094 2095 ctx.msk_busaddr = 0; 2096 error = bus_dmamap_load(sc->msk_stat_tag, 2097 sc->msk_stat_map, sc->msk_stat_ring, MSK_STAT_RING_SZ, 2098 msk_dmamap_cb, &ctx, 0); 2099 if (error != 0) { 2100 device_printf(sc->msk_dev, 2101 "failed to load DMA'able memory for status ring\n"); 2102 return (error); 2103 } 2104 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 2105 2106 return (0); 2107 } 2108 2109 static void 2110 msk_status_dma_free(struct msk_softc *sc) 2111 { 2112 2113 /* Destroy status block. */ 2114 if (sc->msk_stat_tag) { 2115 if (sc->msk_stat_map) { 2116 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 2117 if (sc->msk_stat_ring) { 2118 bus_dmamem_free(sc->msk_stat_tag, 2119 sc->msk_stat_ring, sc->msk_stat_map); 2120 sc->msk_stat_ring = NULL; 2121 } 2122 sc->msk_stat_map = NULL; 2123 } 2124 bus_dma_tag_destroy(sc->msk_stat_tag); 2125 sc->msk_stat_tag = NULL; 2126 } 2127 } 2128 2129 static int 2130 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 2131 { 2132 struct msk_dmamap_arg ctx; 2133 struct msk_txdesc *txd; 2134 struct msk_rxdesc *rxd; 2135 bus_size_t rxalign; 2136 int error, i; 2137 2138 /* Create parent DMA tag. */ 2139 /* 2140 * XXX 2141 * It seems that Yukon II supports full 64bits DMA operations. But 2142 * it needs two descriptors(list elements) for 64bits DMA operations. 2143 * Since we don't know what DMA address mappings(32bits or 64bits) 2144 * would be used in advance for each mbufs, we limits its DMA space 2145 * to be in range of 32bits address space. Otherwise, we should check 2146 * what DMA address is used and chain another descriptor for the 2147 * 64bits DMA operation. This also means descriptor ring size is 2148 * variable. Limiting DMA address to be in 32bit address space greatly 2149 * simplifies descriptor handling and possibly would increase 2150 * performance a bit due to efficient handling of descriptors. 2151 * Apart from harassing checksum offloading mechanisms, it seems 2152 * it's really bad idea to use a separate descriptor for 64bit 2153 * DMA operation to save small descriptor memory. Anyway, I've 2154 * never seen these exotic scheme on ethernet interface hardware. 2155 */ 2156 error = bus_dma_tag_create( 2157 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2158 1, 0, /* alignment, boundary */ 2159 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2160 BUS_SPACE_MAXADDR, /* highaddr */ 2161 NULL, NULL, /* filter, filterarg */ 2162 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2163 0, /* nsegments */ 2164 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2165 0, /* flags */ 2166 NULL, NULL, /* lockfunc, lockarg */ 2167 &sc_if->msk_cdata.msk_parent_tag); 2168 if (error != 0) { 2169 device_printf(sc_if->msk_if_dev, 2170 "failed to create parent DMA tag\n"); 2171 goto fail; 2172 } 2173 /* Create tag for Tx ring. */ 2174 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2175 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2176 BUS_SPACE_MAXADDR, /* lowaddr */ 2177 BUS_SPACE_MAXADDR, /* highaddr */ 2178 NULL, NULL, /* filter, filterarg */ 2179 MSK_TX_RING_SZ, /* maxsize */ 2180 1, /* nsegments */ 2181 MSK_TX_RING_SZ, /* maxsegsize */ 2182 0, /* flags */ 2183 NULL, NULL, /* lockfunc, lockarg */ 2184 &sc_if->msk_cdata.msk_tx_ring_tag); 2185 if (error != 0) { 2186 device_printf(sc_if->msk_if_dev, 2187 "failed to create Tx ring DMA tag\n"); 2188 goto fail; 2189 } 2190 2191 /* Create tag for Rx ring. */ 2192 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2193 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2194 BUS_SPACE_MAXADDR, /* lowaddr */ 2195 BUS_SPACE_MAXADDR, /* highaddr */ 2196 NULL, NULL, /* filter, filterarg */ 2197 MSK_RX_RING_SZ, /* maxsize */ 2198 1, /* nsegments */ 2199 MSK_RX_RING_SZ, /* maxsegsize */ 2200 0, /* flags */ 2201 NULL, NULL, /* lockfunc, lockarg */ 2202 &sc_if->msk_cdata.msk_rx_ring_tag); 2203 if (error != 0) { 2204 device_printf(sc_if->msk_if_dev, 2205 "failed to create Rx ring DMA tag\n"); 2206 goto fail; 2207 } 2208 2209 /* Create tag for Tx buffers. */ 2210 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2211 1, 0, /* alignment, boundary */ 2212 BUS_SPACE_MAXADDR, /* lowaddr */ 2213 BUS_SPACE_MAXADDR, /* highaddr */ 2214 NULL, NULL, /* filter, filterarg */ 2215 MSK_TSO_MAXSIZE, /* maxsize */ 2216 MSK_MAXTXSEGS, /* nsegments */ 2217 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2218 0, /* flags */ 2219 NULL, NULL, /* lockfunc, lockarg */ 2220 &sc_if->msk_cdata.msk_tx_tag); 2221 if (error != 0) { 2222 device_printf(sc_if->msk_if_dev, 2223 "failed to create Tx DMA tag\n"); 2224 goto fail; 2225 } 2226 2227 rxalign = 1; 2228 /* 2229 * Workaround hardware hang which seems to happen when Rx buffer 2230 * is not aligned on multiple of FIFO word(8 bytes). 2231 */ 2232 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2233 rxalign = MSK_RX_BUF_ALIGN; 2234 /* Create tag for Rx buffers. */ 2235 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2236 rxalign, 0, /* alignment, boundary */ 2237 BUS_SPACE_MAXADDR, /* lowaddr */ 2238 BUS_SPACE_MAXADDR, /* highaddr */ 2239 NULL, NULL, /* filter, filterarg */ 2240 MCLBYTES, /* maxsize */ 2241 1, /* nsegments */ 2242 MCLBYTES, /* maxsegsize */ 2243 0, /* flags */ 2244 NULL, NULL, /* lockfunc, lockarg */ 2245 &sc_if->msk_cdata.msk_rx_tag); 2246 if (error != 0) { 2247 device_printf(sc_if->msk_if_dev, 2248 "failed to create Rx DMA tag\n"); 2249 goto fail; 2250 } 2251 2252 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2253 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2254 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2255 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2256 if (error != 0) { 2257 device_printf(sc_if->msk_if_dev, 2258 "failed to allocate DMA'able memory for Tx ring\n"); 2259 goto fail; 2260 } 2261 2262 ctx.msk_busaddr = 0; 2263 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2264 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2265 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2266 if (error != 0) { 2267 device_printf(sc_if->msk_if_dev, 2268 "failed to load DMA'able memory for Tx ring\n"); 2269 goto fail; 2270 } 2271 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2272 2273 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2274 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2275 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2276 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2277 if (error != 0) { 2278 device_printf(sc_if->msk_if_dev, 2279 "failed to allocate DMA'able memory for Rx ring\n"); 2280 goto fail; 2281 } 2282 2283 ctx.msk_busaddr = 0; 2284 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2285 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2286 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2287 if (error != 0) { 2288 device_printf(sc_if->msk_if_dev, 2289 "failed to load DMA'able memory for Rx ring\n"); 2290 goto fail; 2291 } 2292 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2293 2294 /* Create DMA maps for Tx buffers. */ 2295 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2296 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2297 txd->tx_m = NULL; 2298 txd->tx_dmamap = NULL; 2299 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2300 &txd->tx_dmamap); 2301 if (error != 0) { 2302 device_printf(sc_if->msk_if_dev, 2303 "failed to create Tx dmamap\n"); 2304 goto fail; 2305 } 2306 } 2307 /* Create DMA maps for Rx buffers. */ 2308 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2309 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2310 device_printf(sc_if->msk_if_dev, 2311 "failed to create spare Rx dmamap\n"); 2312 goto fail; 2313 } 2314 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2315 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2316 rxd->rx_m = NULL; 2317 rxd->rx_dmamap = NULL; 2318 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2319 &rxd->rx_dmamap); 2320 if (error != 0) { 2321 device_printf(sc_if->msk_if_dev, 2322 "failed to create Rx dmamap\n"); 2323 goto fail; 2324 } 2325 } 2326 2327 fail: 2328 return (error); 2329 } 2330 2331 static int 2332 msk_rx_dma_jalloc(struct msk_if_softc *sc_if) 2333 { 2334 struct msk_dmamap_arg ctx; 2335 struct msk_rxdesc *jrxd; 2336 bus_size_t rxalign; 2337 int error, i; 2338 2339 if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) { 2340 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2341 device_printf(sc_if->msk_if_dev, 2342 "disabling jumbo frame support\n"); 2343 return (0); 2344 } 2345 /* Create tag for jumbo Rx ring. */ 2346 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2347 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2348 BUS_SPACE_MAXADDR, /* lowaddr */ 2349 BUS_SPACE_MAXADDR, /* highaddr */ 2350 NULL, NULL, /* filter, filterarg */ 2351 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2352 1, /* nsegments */ 2353 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2354 0, /* flags */ 2355 NULL, NULL, /* lockfunc, lockarg */ 2356 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2357 if (error != 0) { 2358 device_printf(sc_if->msk_if_dev, 2359 "failed to create jumbo Rx ring DMA tag\n"); 2360 goto jumbo_fail; 2361 } 2362 2363 rxalign = 1; 2364 /* 2365 * Workaround hardware hang which seems to happen when Rx buffer 2366 * is not aligned on multiple of FIFO word(8 bytes). 2367 */ 2368 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 2369 rxalign = MSK_RX_BUF_ALIGN; 2370 /* Create tag for jumbo Rx buffers. */ 2371 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2372 rxalign, 0, /* alignment, boundary */ 2373 BUS_SPACE_MAXADDR, /* lowaddr */ 2374 BUS_SPACE_MAXADDR, /* highaddr */ 2375 NULL, NULL, /* filter, filterarg */ 2376 MJUM9BYTES, /* maxsize */ 2377 1, /* nsegments */ 2378 MJUM9BYTES, /* maxsegsize */ 2379 0, /* flags */ 2380 NULL, NULL, /* lockfunc, lockarg */ 2381 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2382 if (error != 0) { 2383 device_printf(sc_if->msk_if_dev, 2384 "failed to create jumbo Rx DMA tag\n"); 2385 goto jumbo_fail; 2386 } 2387 2388 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2389 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2390 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2391 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2392 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2393 if (error != 0) { 2394 device_printf(sc_if->msk_if_dev, 2395 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2396 goto jumbo_fail; 2397 } 2398 2399 ctx.msk_busaddr = 0; 2400 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2401 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2402 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2403 msk_dmamap_cb, &ctx, 0); 2404 if (error != 0) { 2405 device_printf(sc_if->msk_if_dev, 2406 "failed to load DMA'able memory for jumbo Rx ring\n"); 2407 goto jumbo_fail; 2408 } 2409 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2410 2411 /* Create DMA maps for jumbo Rx buffers. */ 2412 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2413 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2414 device_printf(sc_if->msk_if_dev, 2415 "failed to create spare jumbo Rx dmamap\n"); 2416 goto jumbo_fail; 2417 } 2418 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2419 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2420 jrxd->rx_m = NULL; 2421 jrxd->rx_dmamap = NULL; 2422 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2423 &jrxd->rx_dmamap); 2424 if (error != 0) { 2425 device_printf(sc_if->msk_if_dev, 2426 "failed to create jumbo Rx dmamap\n"); 2427 goto jumbo_fail; 2428 } 2429 } 2430 2431 return (0); 2432 2433 jumbo_fail: 2434 msk_rx_dma_jfree(sc_if); 2435 device_printf(sc_if->msk_if_dev, "disabling jumbo frame support " 2436 "due to resource shortage\n"); 2437 sc_if->msk_flags &= ~MSK_FLAG_JUMBO; 2438 return (error); 2439 } 2440 2441 static void 2442 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2443 { 2444 struct msk_txdesc *txd; 2445 struct msk_rxdesc *rxd; 2446 int i; 2447 2448 /* Tx ring. */ 2449 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2450 if (sc_if->msk_cdata.msk_tx_ring_map) 2451 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2452 sc_if->msk_cdata.msk_tx_ring_map); 2453 if (sc_if->msk_cdata.msk_tx_ring_map && 2454 sc_if->msk_rdata.msk_tx_ring) 2455 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2456 sc_if->msk_rdata.msk_tx_ring, 2457 sc_if->msk_cdata.msk_tx_ring_map); 2458 sc_if->msk_rdata.msk_tx_ring = NULL; 2459 sc_if->msk_cdata.msk_tx_ring_map = NULL; 2460 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2461 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2462 } 2463 /* Rx ring. */ 2464 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2465 if (sc_if->msk_cdata.msk_rx_ring_map) 2466 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2467 sc_if->msk_cdata.msk_rx_ring_map); 2468 if (sc_if->msk_cdata.msk_rx_ring_map && 2469 sc_if->msk_rdata.msk_rx_ring) 2470 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2471 sc_if->msk_rdata.msk_rx_ring, 2472 sc_if->msk_cdata.msk_rx_ring_map); 2473 sc_if->msk_rdata.msk_rx_ring = NULL; 2474 sc_if->msk_cdata.msk_rx_ring_map = NULL; 2475 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2476 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2477 } 2478 /* Tx buffers. */ 2479 if (sc_if->msk_cdata.msk_tx_tag) { 2480 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2481 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2482 if (txd->tx_dmamap) { 2483 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2484 txd->tx_dmamap); 2485 txd->tx_dmamap = NULL; 2486 } 2487 } 2488 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2489 sc_if->msk_cdata.msk_tx_tag = NULL; 2490 } 2491 /* Rx buffers. */ 2492 if (sc_if->msk_cdata.msk_rx_tag) { 2493 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2494 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2495 if (rxd->rx_dmamap) { 2496 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2497 rxd->rx_dmamap); 2498 rxd->rx_dmamap = NULL; 2499 } 2500 } 2501 if (sc_if->msk_cdata.msk_rx_sparemap) { 2502 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2503 sc_if->msk_cdata.msk_rx_sparemap); 2504 sc_if->msk_cdata.msk_rx_sparemap = 0; 2505 } 2506 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2507 sc_if->msk_cdata.msk_rx_tag = NULL; 2508 } 2509 if (sc_if->msk_cdata.msk_parent_tag) { 2510 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2511 sc_if->msk_cdata.msk_parent_tag = NULL; 2512 } 2513 } 2514 2515 static void 2516 msk_rx_dma_jfree(struct msk_if_softc *sc_if) 2517 { 2518 struct msk_rxdesc *jrxd; 2519 int i; 2520 2521 /* Jumbo Rx ring. */ 2522 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2523 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map) 2524 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2525 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2526 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map && 2527 sc_if->msk_rdata.msk_jumbo_rx_ring) 2528 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2529 sc_if->msk_rdata.msk_jumbo_rx_ring, 2530 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2531 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2532 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL; 2533 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2534 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2535 } 2536 /* Jumbo Rx buffers. */ 2537 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2538 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2539 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2540 if (jrxd->rx_dmamap) { 2541 bus_dmamap_destroy( 2542 sc_if->msk_cdata.msk_jumbo_rx_tag, 2543 jrxd->rx_dmamap); 2544 jrxd->rx_dmamap = NULL; 2545 } 2546 } 2547 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2548 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2549 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2550 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2551 } 2552 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2553 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2554 } 2555 } 2556 2557 static int 2558 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2559 { 2560 struct msk_txdesc *txd, *txd_last; 2561 struct msk_tx_desc *tx_le; 2562 struct mbuf *m; 2563 bus_dmamap_t map; 2564 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2565 uint32_t control, csum, prod, si; 2566 uint16_t offset, tcp_offset, tso_mtu; 2567 int error, i, nseg, tso; 2568 2569 MSK_IF_LOCK_ASSERT(sc_if); 2570 2571 tcp_offset = offset = 0; 2572 m = *m_head; 2573 if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2574 (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) || 2575 ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 2576 (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) { 2577 /* 2578 * Since mbuf has no protocol specific structure information 2579 * in it we have to inspect protocol information here to 2580 * setup TSO and checksum offload. I don't know why Marvell 2581 * made a such decision in chip design because other GigE 2582 * hardwares normally takes care of all these chores in 2583 * hardware. However, TSO performance of Yukon II is very 2584 * good such that it's worth to implement it. 2585 */ 2586 struct ether_header *eh; 2587 struct ip *ip; 2588 struct tcphdr *tcp; 2589 2590 if (M_WRITABLE(m) == 0) { 2591 /* Get a writable copy. */ 2592 m = m_dup(*m_head, M_DONTWAIT); 2593 m_freem(*m_head); 2594 if (m == NULL) { 2595 *m_head = NULL; 2596 return (ENOBUFS); 2597 } 2598 *m_head = m; 2599 } 2600 2601 offset = sizeof(struct ether_header); 2602 m = m_pullup(m, offset); 2603 if (m == NULL) { 2604 *m_head = NULL; 2605 return (ENOBUFS); 2606 } 2607 eh = mtod(m, struct ether_header *); 2608 /* Check if hardware VLAN insertion is off. */ 2609 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2610 offset = sizeof(struct ether_vlan_header); 2611 m = m_pullup(m, offset); 2612 if (m == NULL) { 2613 *m_head = NULL; 2614 return (ENOBUFS); 2615 } 2616 } 2617 m = m_pullup(m, offset + sizeof(struct ip)); 2618 if (m == NULL) { 2619 *m_head = NULL; 2620 return (ENOBUFS); 2621 } 2622 ip = (struct ip *)(mtod(m, char *) + offset); 2623 offset += (ip->ip_hl << 2); 2624 tcp_offset = offset; 2625 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2626 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2627 if (m == NULL) { 2628 *m_head = NULL; 2629 return (ENOBUFS); 2630 } 2631 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2632 offset += (tcp->th_off << 2); 2633 } else if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 && 2634 (m->m_pkthdr.len < MSK_MIN_FRAMELEN) && 2635 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2636 /* 2637 * It seems that Yukon II has Tx checksum offload bug 2638 * for small TCP packets that's less than 60 bytes in 2639 * size (e.g. TCP window probe packet, pure ACK packet). 2640 * Common work around like padding with zeros to make 2641 * the frame minimum ethernet frame size didn't work at 2642 * all. 2643 * Instead of disabling checksum offload completely we 2644 * resort to S/W checksum routine when we encounter 2645 * short TCP frames. 2646 * Short UDP packets appear to be handled correctly by 2647 * Yukon II. Also I assume this bug does not happen on 2648 * controllers that use newer descriptor format or 2649 * automatic Tx checksum calculation. 2650 */ 2651 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2652 if (m == NULL) { 2653 *m_head = NULL; 2654 return (ENOBUFS); 2655 } 2656 *(uint16_t *)(m->m_data + offset + 2657 m->m_pkthdr.csum_data) = in_cksum_skip(m, 2658 m->m_pkthdr.len, offset); 2659 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2660 } 2661 *m_head = m; 2662 } 2663 2664 prod = sc_if->msk_cdata.msk_tx_prod; 2665 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2666 txd_last = txd; 2667 map = txd->tx_dmamap; 2668 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2669 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2670 if (error == EFBIG) { 2671 m = m_collapse(*m_head, M_DONTWAIT, MSK_MAXTXSEGS); 2672 if (m == NULL) { 2673 m_freem(*m_head); 2674 *m_head = NULL; 2675 return (ENOBUFS); 2676 } 2677 *m_head = m; 2678 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2679 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2680 if (error != 0) { 2681 m_freem(*m_head); 2682 *m_head = NULL; 2683 return (error); 2684 } 2685 } else if (error != 0) 2686 return (error); 2687 if (nseg == 0) { 2688 m_freem(*m_head); 2689 *m_head = NULL; 2690 return (EIO); 2691 } 2692 2693 /* Check number of available descriptors. */ 2694 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2695 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2696 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2697 return (ENOBUFS); 2698 } 2699 2700 control = 0; 2701 tso = 0; 2702 tx_le = NULL; 2703 2704 /* Check TSO support. */ 2705 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2706 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2707 tso_mtu = m->m_pkthdr.tso_segsz; 2708 else 2709 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2710 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2711 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2712 tx_le->msk_addr = htole32(tso_mtu); 2713 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) 2714 tx_le->msk_control = htole32(OP_MSS | HW_OWNER); 2715 else 2716 tx_le->msk_control = 2717 htole32(OP_LRGLEN | HW_OWNER); 2718 sc_if->msk_cdata.msk_tx_cnt++; 2719 MSK_INC(prod, MSK_TX_RING_CNT); 2720 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2721 } 2722 tso++; 2723 } 2724 /* Check if we have a VLAN tag to insert. */ 2725 if ((m->m_flags & M_VLANTAG) != 0) { 2726 if (tx_le == NULL) { 2727 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2728 tx_le->msk_addr = htole32(0); 2729 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2730 htons(m->m_pkthdr.ether_vtag)); 2731 sc_if->msk_cdata.msk_tx_cnt++; 2732 MSK_INC(prod, MSK_TX_RING_CNT); 2733 } else { 2734 tx_le->msk_control |= htole32(OP_VLAN | 2735 htons(m->m_pkthdr.ether_vtag)); 2736 } 2737 control |= INS_VLAN; 2738 } 2739 /* Check if we have to handle checksum offload. */ 2740 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2741 if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0) 2742 control |= CALSUM; 2743 else { 2744 control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2745 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2746 control |= UDPTCP; 2747 /* Checksum write position. */ 2748 csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff; 2749 /* Checksum start position. */ 2750 csum |= (uint32_t)tcp_offset << 16; 2751 if (csum != sc_if->msk_cdata.msk_last_csum) { 2752 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2753 tx_le->msk_addr = htole32(csum); 2754 tx_le->msk_control = htole32(1 << 16 | 2755 (OP_TCPLISW | HW_OWNER)); 2756 sc_if->msk_cdata.msk_tx_cnt++; 2757 MSK_INC(prod, MSK_TX_RING_CNT); 2758 sc_if->msk_cdata.msk_last_csum = csum; 2759 } 2760 } 2761 } 2762 2763 si = prod; 2764 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2765 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2766 if (tso == 0) 2767 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2768 OP_PACKET); 2769 else 2770 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2771 OP_LARGESEND); 2772 sc_if->msk_cdata.msk_tx_cnt++; 2773 MSK_INC(prod, MSK_TX_RING_CNT); 2774 2775 for (i = 1; i < nseg; i++) { 2776 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2777 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2778 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2779 OP_BUFFER | HW_OWNER); 2780 sc_if->msk_cdata.msk_tx_cnt++; 2781 MSK_INC(prod, MSK_TX_RING_CNT); 2782 } 2783 /* Update producer index. */ 2784 sc_if->msk_cdata.msk_tx_prod = prod; 2785 2786 /* Set EOP on the last descriptor. */ 2787 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2788 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2789 tx_le->msk_control |= htole32(EOP); 2790 2791 /* Turn the first descriptor ownership to hardware. */ 2792 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2793 tx_le->msk_control |= htole32(HW_OWNER); 2794 2795 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2796 map = txd_last->tx_dmamap; 2797 txd_last->tx_dmamap = txd->tx_dmamap; 2798 txd->tx_dmamap = map; 2799 txd->tx_m = m; 2800 2801 /* Sync descriptors. */ 2802 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2803 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2804 sc_if->msk_cdata.msk_tx_ring_map, 2805 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2806 2807 return (0); 2808 } 2809 2810 static void 2811 msk_start(struct ifnet *ifp) 2812 { 2813 struct msk_if_softc *sc_if; 2814 2815 sc_if = ifp->if_softc; 2816 MSK_IF_LOCK(sc_if); 2817 msk_start_locked(ifp); 2818 MSK_IF_UNLOCK(sc_if); 2819 } 2820 2821 static void 2822 msk_start_locked(struct ifnet *ifp) 2823 { 2824 struct msk_if_softc *sc_if; 2825 struct mbuf *m_head; 2826 int enq; 2827 2828 sc_if = ifp->if_softc; 2829 MSK_IF_LOCK_ASSERT(sc_if); 2830 2831 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2832 IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0) 2833 return; 2834 2835 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2836 sc_if->msk_cdata.msk_tx_cnt < 2837 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2838 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2839 if (m_head == NULL) 2840 break; 2841 /* 2842 * Pack the data into the transmit ring. If we 2843 * don't have room, set the OACTIVE flag and wait 2844 * for the NIC to drain the ring. 2845 */ 2846 if (msk_encap(sc_if, &m_head) != 0) { 2847 if (m_head == NULL) 2848 break; 2849 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2850 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2851 break; 2852 } 2853 2854 enq++; 2855 /* 2856 * If there's a BPF listener, bounce a copy of this frame 2857 * to him. 2858 */ 2859 ETHER_BPF_MTAP(ifp, m_head); 2860 } 2861 2862 if (enq > 0) { 2863 /* Transmit */ 2864 CSR_WRITE_2(sc_if->msk_softc, 2865 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2866 sc_if->msk_cdata.msk_tx_prod); 2867 2868 /* Set a timeout in case the chip goes out to lunch. */ 2869 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2870 } 2871 } 2872 2873 static void 2874 msk_watchdog(struct msk_if_softc *sc_if) 2875 { 2876 struct ifnet *ifp; 2877 2878 MSK_IF_LOCK_ASSERT(sc_if); 2879 2880 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2881 return; 2882 ifp = sc_if->msk_ifp; 2883 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) { 2884 if (bootverbose) 2885 if_printf(sc_if->msk_ifp, "watchdog timeout " 2886 "(missed link)\n"); 2887 ifp->if_oerrors++; 2888 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2889 msk_init_locked(sc_if); 2890 return; 2891 } 2892 2893 if_printf(ifp, "watchdog timeout\n"); 2894 ifp->if_oerrors++; 2895 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2896 msk_init_locked(sc_if); 2897 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2898 msk_start_locked(ifp); 2899 } 2900 2901 static int 2902 mskc_shutdown(device_t dev) 2903 { 2904 struct msk_softc *sc; 2905 int i; 2906 2907 sc = device_get_softc(dev); 2908 MSK_LOCK(sc); 2909 for (i = 0; i < sc->msk_num_port; i++) { 2910 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2911 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 2912 IFF_DRV_RUNNING) != 0)) 2913 msk_stop(sc->msk_if[i]); 2914 } 2915 MSK_UNLOCK(sc); 2916 2917 /* Put hardware reset. */ 2918 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2919 return (0); 2920 } 2921 2922 static int 2923 mskc_suspend(device_t dev) 2924 { 2925 struct msk_softc *sc; 2926 int i; 2927 2928 sc = device_get_softc(dev); 2929 2930 MSK_LOCK(sc); 2931 2932 for (i = 0; i < sc->msk_num_port; i++) { 2933 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2934 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 2935 IFF_DRV_RUNNING) != 0)) 2936 msk_stop(sc->msk_if[i]); 2937 } 2938 2939 /* Disable all interrupts. */ 2940 CSR_WRITE_4(sc, B0_IMSK, 0); 2941 CSR_READ_4(sc, B0_IMSK); 2942 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2943 CSR_READ_4(sc, B0_HWE_IMSK); 2944 2945 msk_phy_power(sc, MSK_PHY_POWERDOWN); 2946 2947 /* Put hardware reset. */ 2948 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2949 sc->msk_pflags |= MSK_FLAG_SUSPEND; 2950 2951 MSK_UNLOCK(sc); 2952 2953 return (0); 2954 } 2955 2956 static int 2957 mskc_resume(device_t dev) 2958 { 2959 struct msk_softc *sc; 2960 int i; 2961 2962 sc = device_get_softc(dev); 2963 2964 MSK_LOCK(sc); 2965 2966 mskc_reset(sc); 2967 for (i = 0; i < sc->msk_num_port; i++) { 2968 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2969 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) { 2970 sc->msk_if[i]->msk_ifp->if_drv_flags &= 2971 ~IFF_DRV_RUNNING; 2972 msk_init_locked(sc->msk_if[i]); 2973 } 2974 } 2975 sc->msk_pflags &= ~MSK_FLAG_SUSPEND; 2976 2977 MSK_UNLOCK(sc); 2978 2979 return (0); 2980 } 2981 2982 #ifndef __NO_STRICT_ALIGNMENT 2983 static __inline void 2984 msk_fixup_rx(struct mbuf *m) 2985 { 2986 int i; 2987 uint16_t *src, *dst; 2988 2989 src = mtod(m, uint16_t *); 2990 dst = src - 3; 2991 2992 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2993 *dst++ = *src++; 2994 2995 m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN); 2996 } 2997 #endif 2998 2999 static __inline void 3000 msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m) 3001 { 3002 struct ether_header *eh; 3003 struct ip *ip; 3004 struct udphdr *uh; 3005 int32_t hlen, len, pktlen, temp32; 3006 uint16_t csum, *opts; 3007 3008 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) { 3009 if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) { 3010 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3011 if ((control & CSS_IPV4_CSUM_OK) != 0) 3012 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3013 if ((control & (CSS_TCP | CSS_UDP)) != 0 && 3014 (control & (CSS_TCPUDP_CSUM_OK)) != 0) { 3015 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 3016 CSUM_PSEUDO_HDR; 3017 m->m_pkthdr.csum_data = 0xffff; 3018 } 3019 } 3020 return; 3021 } 3022 /* 3023 * Marvell Yukon controllers that support OP_RXCHKS has known 3024 * to have various Rx checksum offloading bugs. These 3025 * controllers can be configured to compute simple checksum 3026 * at two different positions. So we can compute IP and TCP/UDP 3027 * checksum at the same time. We intentionally have controller 3028 * compute TCP/UDP checksum twice by specifying the same 3029 * checksum start position and compare the result. If the value 3030 * is different it would indicate the hardware logic was wrong. 3031 */ 3032 if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) { 3033 if (bootverbose) 3034 device_printf(sc_if->msk_if_dev, 3035 "Rx checksum value mismatch!\n"); 3036 return; 3037 } 3038 pktlen = m->m_pkthdr.len; 3039 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 3040 return; 3041 eh = mtod(m, struct ether_header *); 3042 if (eh->ether_type != htons(ETHERTYPE_IP)) 3043 return; 3044 ip = (struct ip *)(eh + 1); 3045 if (ip->ip_v != IPVERSION) 3046 return; 3047 3048 hlen = ip->ip_hl << 2; 3049 pktlen -= sizeof(struct ether_header); 3050 if (hlen < sizeof(struct ip)) 3051 return; 3052 if (ntohs(ip->ip_len) < hlen) 3053 return; 3054 if (ntohs(ip->ip_len) != pktlen) 3055 return; 3056 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 3057 return; /* can't handle fragmented packet. */ 3058 3059 switch (ip->ip_p) { 3060 case IPPROTO_TCP: 3061 if (pktlen < (hlen + sizeof(struct tcphdr))) 3062 return; 3063 break; 3064 case IPPROTO_UDP: 3065 if (pktlen < (hlen + sizeof(struct udphdr))) 3066 return; 3067 uh = (struct udphdr *)((caddr_t)ip + hlen); 3068 if (uh->uh_sum == 0) 3069 return; /* no checksum */ 3070 break; 3071 default: 3072 return; 3073 } 3074 csum = bswap16(sc_if->msk_csum & 0xFFFF); 3075 /* Checksum fixup for IP options. */ 3076 len = hlen - sizeof(struct ip); 3077 if (len > 0) { 3078 opts = (uint16_t *)(ip + 1); 3079 for (; len > 0; len -= sizeof(uint16_t), opts++) { 3080 temp32 = csum - *opts; 3081 temp32 = (temp32 >> 16) + (temp32 & 65535); 3082 csum = temp32 & 65535; 3083 } 3084 } 3085 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 3086 m->m_pkthdr.csum_data = csum; 3087 } 3088 3089 static void 3090 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3091 int len) 3092 { 3093 struct mbuf *m; 3094 struct ifnet *ifp; 3095 struct msk_rxdesc *rxd; 3096 int cons, rxlen; 3097 3098 ifp = sc_if->msk_ifp; 3099 3100 MSK_IF_LOCK_ASSERT(sc_if); 3101 3102 cons = sc_if->msk_cdata.msk_rx_cons; 3103 do { 3104 rxlen = status >> 16; 3105 if ((status & GMR_FS_VLAN) != 0 && 3106 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3107 rxlen -= ETHER_VLAN_ENCAP_LEN; 3108 if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) { 3109 /* 3110 * For controllers that returns bogus status code 3111 * just do minimal check and let upper stack 3112 * handle this frame. 3113 */ 3114 if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) { 3115 ifp->if_ierrors++; 3116 msk_discard_rxbuf(sc_if, cons); 3117 break; 3118 } 3119 } else if (len > sc_if->msk_framesize || 3120 ((status & GMR_FS_ANY_ERR) != 0) || 3121 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3122 /* Don't count flow-control packet as errors. */ 3123 if ((status & GMR_FS_GOOD_FC) == 0) 3124 ifp->if_ierrors++; 3125 msk_discard_rxbuf(sc_if, cons); 3126 break; 3127 } 3128 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 3129 m = rxd->rx_m; 3130 if (msk_newbuf(sc_if, cons) != 0) { 3131 ifp->if_iqdrops++; 3132 /* Reuse old buffer. */ 3133 msk_discard_rxbuf(sc_if, cons); 3134 break; 3135 } 3136 m->m_pkthdr.rcvif = ifp; 3137 m->m_pkthdr.len = m->m_len = len; 3138 #ifndef __NO_STRICT_ALIGNMENT 3139 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3140 msk_fixup_rx(m); 3141 #endif 3142 ifp->if_ipackets++; 3143 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3144 msk_rxcsum(sc_if, control, m); 3145 /* Check for VLAN tagged packets. */ 3146 if ((status & GMR_FS_VLAN) != 0 && 3147 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3148 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3149 m->m_flags |= M_VLANTAG; 3150 } 3151 MSK_IF_UNLOCK(sc_if); 3152 (*ifp->if_input)(ifp, m); 3153 MSK_IF_LOCK(sc_if); 3154 } while (0); 3155 3156 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 3157 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 3158 } 3159 3160 static void 3161 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control, 3162 int len) 3163 { 3164 struct mbuf *m; 3165 struct ifnet *ifp; 3166 struct msk_rxdesc *jrxd; 3167 int cons, rxlen; 3168 3169 ifp = sc_if->msk_ifp; 3170 3171 MSK_IF_LOCK_ASSERT(sc_if); 3172 3173 cons = sc_if->msk_cdata.msk_rx_cons; 3174 do { 3175 rxlen = status >> 16; 3176 if ((status & GMR_FS_VLAN) != 0 && 3177 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3178 rxlen -= ETHER_VLAN_ENCAP_LEN; 3179 if (len > sc_if->msk_framesize || 3180 ((status & GMR_FS_ANY_ERR) != 0) || 3181 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3182 /* Don't count flow-control packet as errors. */ 3183 if ((status & GMR_FS_GOOD_FC) == 0) 3184 ifp->if_ierrors++; 3185 msk_discard_jumbo_rxbuf(sc_if, cons); 3186 break; 3187 } 3188 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 3189 m = jrxd->rx_m; 3190 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3191 ifp->if_iqdrops++; 3192 /* Reuse old buffer. */ 3193 msk_discard_jumbo_rxbuf(sc_if, cons); 3194 break; 3195 } 3196 m->m_pkthdr.rcvif = ifp; 3197 m->m_pkthdr.len = m->m_len = len; 3198 #ifndef __NO_STRICT_ALIGNMENT 3199 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0) 3200 msk_fixup_rx(m); 3201 #endif 3202 ifp->if_ipackets++; 3203 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3204 msk_rxcsum(sc_if, control, m); 3205 /* Check for VLAN tagged packets. */ 3206 if ((status & GMR_FS_VLAN) != 0 && 3207 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3208 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3209 m->m_flags |= M_VLANTAG; 3210 } 3211 MSK_IF_UNLOCK(sc_if); 3212 (*ifp->if_input)(ifp, m); 3213 MSK_IF_LOCK(sc_if); 3214 } while (0); 3215 3216 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3217 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3218 } 3219 3220 static void 3221 msk_txeof(struct msk_if_softc *sc_if, int idx) 3222 { 3223 struct msk_txdesc *txd; 3224 struct msk_tx_desc *cur_tx; 3225 struct ifnet *ifp; 3226 uint32_t control; 3227 int cons, prog; 3228 3229 MSK_IF_LOCK_ASSERT(sc_if); 3230 3231 ifp = sc_if->msk_ifp; 3232 3233 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3234 sc_if->msk_cdata.msk_tx_ring_map, 3235 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3236 /* 3237 * Go through our tx ring and free mbufs for those 3238 * frames that have been sent. 3239 */ 3240 cons = sc_if->msk_cdata.msk_tx_cons; 3241 prog = 0; 3242 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3243 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3244 break; 3245 prog++; 3246 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3247 control = le32toh(cur_tx->msk_control); 3248 sc_if->msk_cdata.msk_tx_cnt--; 3249 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3250 if ((control & EOP) == 0) 3251 continue; 3252 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3253 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3254 BUS_DMASYNC_POSTWRITE); 3255 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3256 3257 ifp->if_opackets++; 3258 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3259 __func__)); 3260 m_freem(txd->tx_m); 3261 txd->tx_m = NULL; 3262 } 3263 3264 if (prog > 0) { 3265 sc_if->msk_cdata.msk_tx_cons = cons; 3266 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3267 sc_if->msk_watchdog_timer = 0; 3268 /* No need to sync LEs as we didn't update LEs. */ 3269 } 3270 } 3271 3272 static void 3273 msk_tick(void *xsc_if) 3274 { 3275 struct msk_if_softc *sc_if; 3276 struct mii_data *mii; 3277 3278 sc_if = xsc_if; 3279 3280 MSK_IF_LOCK_ASSERT(sc_if); 3281 3282 mii = device_get_softc(sc_if->msk_miibus); 3283 3284 mii_tick(mii); 3285 if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) 3286 msk_miibus_statchg(sc_if->msk_if_dev); 3287 msk_handle_events(sc_if->msk_softc); 3288 msk_watchdog(sc_if); 3289 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3290 } 3291 3292 static void 3293 msk_intr_phy(struct msk_if_softc *sc_if) 3294 { 3295 uint16_t status; 3296 3297 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3298 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3299 /* Handle FIFO Underrun/Overflow? */ 3300 if ((status & PHY_M_IS_FIFO_ERROR)) 3301 device_printf(sc_if->msk_if_dev, 3302 "PHY FIFO underrun/overflow.\n"); 3303 } 3304 3305 static void 3306 msk_intr_gmac(struct msk_if_softc *sc_if) 3307 { 3308 struct msk_softc *sc; 3309 uint8_t status; 3310 3311 sc = sc_if->msk_softc; 3312 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3313 3314 /* GMAC Rx FIFO overrun. */ 3315 if ((status & GM_IS_RX_FF_OR) != 0) 3316 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3317 GMF_CLI_RX_FO); 3318 /* GMAC Tx FIFO underrun. */ 3319 if ((status & GM_IS_TX_FF_UR) != 0) { 3320 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3321 GMF_CLI_TX_FU); 3322 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3323 /* 3324 * XXX 3325 * In case of Tx underrun, we may need to flush/reset 3326 * Tx MAC but that would also require resynchronization 3327 * with status LEs. Reinitializing status LEs would 3328 * affect other port in dual MAC configuration so it 3329 * should be avoided as possible as we can. 3330 * Due to lack of documentation it's all vague guess but 3331 * it needs more investigation. 3332 */ 3333 } 3334 } 3335 3336 static void 3337 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3338 { 3339 struct msk_softc *sc; 3340 3341 sc = sc_if->msk_softc; 3342 if ((status & Y2_IS_PAR_RD1) != 0) { 3343 device_printf(sc_if->msk_if_dev, 3344 "RAM buffer read parity error\n"); 3345 /* Clear IRQ. */ 3346 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3347 RI_CLR_RD_PERR); 3348 } 3349 if ((status & Y2_IS_PAR_WR1) != 0) { 3350 device_printf(sc_if->msk_if_dev, 3351 "RAM buffer write parity error\n"); 3352 /* Clear IRQ. */ 3353 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3354 RI_CLR_WR_PERR); 3355 } 3356 if ((status & Y2_IS_PAR_MAC1) != 0) { 3357 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3358 /* Clear IRQ. */ 3359 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3360 GMF_CLI_TX_PE); 3361 } 3362 if ((status & Y2_IS_PAR_RX1) != 0) { 3363 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3364 /* Clear IRQ. */ 3365 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3366 } 3367 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3368 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3369 /* Clear IRQ. */ 3370 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3371 } 3372 } 3373 3374 static void 3375 msk_intr_hwerr(struct msk_softc *sc) 3376 { 3377 uint32_t status; 3378 uint32_t tlphead[4]; 3379 3380 status = CSR_READ_4(sc, B0_HWE_ISRC); 3381 /* Time Stamp timer overflow. */ 3382 if ((status & Y2_IS_TIST_OV) != 0) 3383 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3384 if ((status & Y2_IS_PCI_NEXP) != 0) { 3385 /* 3386 * PCI Express Error occured which is not described in PEX 3387 * spec. 3388 * This error is also mapped either to Master Abort( 3389 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3390 * can only be cleared there. 3391 */ 3392 device_printf(sc->msk_dev, 3393 "PCI Express protocol violation error\n"); 3394 } 3395 3396 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3397 uint16_t v16; 3398 3399 if ((status & Y2_IS_MST_ERR) != 0) 3400 device_printf(sc->msk_dev, 3401 "unexpected IRQ Status error\n"); 3402 else 3403 device_printf(sc->msk_dev, 3404 "unexpected IRQ Master error\n"); 3405 /* Reset all bits in the PCI status register. */ 3406 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3407 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3408 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3409 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3410 PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2); 3411 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3412 } 3413 3414 /* Check for PCI Express Uncorrectable Error. */ 3415 if ((status & Y2_IS_PCI_EXP) != 0) { 3416 uint32_t v32; 3417 3418 /* 3419 * On PCI Express bus bridges are called root complexes (RC). 3420 * PCI Express errors are recognized by the root complex too, 3421 * which requests the system to handle the problem. After 3422 * error occurence it may be that no access to the adapter 3423 * may be performed any longer. 3424 */ 3425 3426 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3427 if ((v32 & PEX_UNSUP_REQ) != 0) { 3428 /* Ignore unsupported request error. */ 3429 device_printf(sc->msk_dev, 3430 "Uncorrectable PCI Express error\n"); 3431 } 3432 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3433 int i; 3434 3435 /* Get TLP header form Log Registers. */ 3436 for (i = 0; i < 4; i++) 3437 tlphead[i] = CSR_PCI_READ_4(sc, 3438 PEX_HEADER_LOG + i * 4); 3439 /* Check for vendor defined broadcast message. */ 3440 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3441 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3442 CSR_WRITE_4(sc, B0_HWE_IMSK, 3443 sc->msk_intrhwemask); 3444 CSR_READ_4(sc, B0_HWE_IMSK); 3445 } 3446 } 3447 /* Clear the interrupt. */ 3448 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3449 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3450 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3451 } 3452 3453 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3454 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3455 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3456 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3457 } 3458 3459 static __inline void 3460 msk_rxput(struct msk_if_softc *sc_if) 3461 { 3462 struct msk_softc *sc; 3463 3464 sc = sc_if->msk_softc; 3465 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) 3466 bus_dmamap_sync( 3467 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3468 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3469 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3470 else 3471 bus_dmamap_sync( 3472 sc_if->msk_cdata.msk_rx_ring_tag, 3473 sc_if->msk_cdata.msk_rx_ring_map, 3474 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3475 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3476 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3477 } 3478 3479 static int 3480 msk_handle_events(struct msk_softc *sc) 3481 { 3482 struct msk_if_softc *sc_if; 3483 int rxput[2]; 3484 struct msk_stat_desc *sd; 3485 uint32_t control, status; 3486 int cons, len, port, rxprog; 3487 3488 if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX)) 3489 return (0); 3490 3491 /* Sync status LEs. */ 3492 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3493 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3494 3495 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3496 rxprog = 0; 3497 cons = sc->msk_stat_cons; 3498 for (;;) { 3499 sd = &sc->msk_stat_ring[cons]; 3500 control = le32toh(sd->msk_control); 3501 if ((control & HW_OWNER) == 0) 3502 break; 3503 control &= ~HW_OWNER; 3504 sd->msk_control = htole32(control); 3505 status = le32toh(sd->msk_status); 3506 len = control & STLE_LEN_MASK; 3507 port = (control >> 16) & 0x01; 3508 sc_if = sc->msk_if[port]; 3509 if (sc_if == NULL) { 3510 device_printf(sc->msk_dev, "invalid port opcode " 3511 "0x%08x\n", control & STLE_OP_MASK); 3512 continue; 3513 } 3514 3515 switch (control & STLE_OP_MASK) { 3516 case OP_RXVLAN: 3517 sc_if->msk_vtag = ntohs(len); 3518 break; 3519 case OP_RXCHKSVLAN: 3520 sc_if->msk_vtag = ntohs(len); 3521 /* FALLTHROUGH */ 3522 case OP_RXCHKS: 3523 sc_if->msk_csum = status; 3524 break; 3525 case OP_RXSTAT: 3526 if (!(sc_if->msk_ifp->if_drv_flags & IFF_DRV_RUNNING)) 3527 break; 3528 if (sc_if->msk_framesize > 3529 (MCLBYTES - MSK_RX_BUF_ALIGN)) 3530 msk_jumbo_rxeof(sc_if, status, control, len); 3531 else 3532 msk_rxeof(sc_if, status, control, len); 3533 rxprog++; 3534 /* 3535 * Because there is no way to sync single Rx LE 3536 * put the DMA sync operation off until the end of 3537 * event processing. 3538 */ 3539 rxput[port]++; 3540 /* Update prefetch unit if we've passed water mark. */ 3541 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3542 msk_rxput(sc_if); 3543 rxput[port] = 0; 3544 } 3545 break; 3546 case OP_TXINDEXLE: 3547 if (sc->msk_if[MSK_PORT_A] != NULL) 3548 msk_txeof(sc->msk_if[MSK_PORT_A], 3549 status & STLE_TXA1_MSKL); 3550 if (sc->msk_if[MSK_PORT_B] != NULL) 3551 msk_txeof(sc->msk_if[MSK_PORT_B], 3552 ((status & STLE_TXA2_MSKL) >> 3553 STLE_TXA2_SHIFTL) | 3554 ((len & STLE_TXA2_MSKH) << 3555 STLE_TXA2_SHIFTH)); 3556 break; 3557 default: 3558 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3559 control & STLE_OP_MASK); 3560 break; 3561 } 3562 MSK_INC(cons, MSK_STAT_RING_CNT); 3563 if (rxprog > sc->msk_process_limit) 3564 break; 3565 } 3566 3567 sc->msk_stat_cons = cons; 3568 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3569 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3570 3571 if (rxput[MSK_PORT_A] > 0) 3572 msk_rxput(sc->msk_if[MSK_PORT_A]); 3573 if (rxput[MSK_PORT_B] > 0) 3574 msk_rxput(sc->msk_if[MSK_PORT_B]); 3575 3576 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3577 } 3578 3579 static void 3580 msk_intr(void *xsc) 3581 { 3582 struct msk_softc *sc; 3583 struct msk_if_softc *sc_if0, *sc_if1; 3584 struct ifnet *ifp0, *ifp1; 3585 uint32_t status; 3586 int domore; 3587 3588 sc = xsc; 3589 MSK_LOCK(sc); 3590 3591 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3592 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3593 if (status == 0 || status == 0xffffffff || 3594 (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 || 3595 (status & sc->msk_intrmask) == 0) { 3596 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3597 MSK_UNLOCK(sc); 3598 return; 3599 } 3600 3601 sc_if0 = sc->msk_if[MSK_PORT_A]; 3602 sc_if1 = sc->msk_if[MSK_PORT_B]; 3603 ifp0 = ifp1 = NULL; 3604 if (sc_if0 != NULL) 3605 ifp0 = sc_if0->msk_ifp; 3606 if (sc_if1 != NULL) 3607 ifp1 = sc_if1->msk_ifp; 3608 3609 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3610 msk_intr_phy(sc_if0); 3611 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3612 msk_intr_phy(sc_if1); 3613 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3614 msk_intr_gmac(sc_if0); 3615 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3616 msk_intr_gmac(sc_if1); 3617 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3618 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3619 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3620 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3621 CSR_READ_4(sc, B0_IMSK); 3622 } 3623 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3624 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3625 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3626 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3627 CSR_READ_4(sc, B0_IMSK); 3628 } 3629 if ((status & Y2_IS_HW_ERR) != 0) 3630 msk_intr_hwerr(sc); 3631 3632 domore = msk_handle_events(sc); 3633 if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0) 3634 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3635 3636 /* Reenable interrupts. */ 3637 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3638 3639 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3640 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3641 msk_start_locked(ifp0); 3642 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3643 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3644 msk_start_locked(ifp1); 3645 3646 MSK_UNLOCK(sc); 3647 } 3648 3649 static void 3650 msk_set_tx_stfwd(struct msk_if_softc *sc_if) 3651 { 3652 struct msk_softc *sc; 3653 struct ifnet *ifp; 3654 3655 ifp = sc_if->msk_ifp; 3656 sc = sc_if->msk_softc; 3657 switch (sc->msk_hw_id) { 3658 case CHIP_ID_YUKON_EX: 3659 if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0) 3660 goto yukon_ex_workaround; 3661 if (ifp->if_mtu > ETHERMTU) 3662 CSR_WRITE_4(sc, 3663 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3664 TX_JUMBO_ENA | TX_STFW_ENA); 3665 else 3666 CSR_WRITE_4(sc, 3667 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3668 TX_JUMBO_DIS | TX_STFW_ENA); 3669 break; 3670 default: 3671 yukon_ex_workaround: 3672 if (ifp->if_mtu > ETHERMTU) { 3673 /* Set Tx GMAC FIFO Almost Empty Threshold. */ 3674 CSR_WRITE_4(sc, 3675 MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3676 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3677 /* Disable Store & Forward mode for Tx. */ 3678 CSR_WRITE_4(sc, 3679 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3680 TX_JUMBO_ENA | TX_STFW_DIS); 3681 } else { 3682 /* Enable Store & Forward mode for Tx. */ 3683 CSR_WRITE_4(sc, 3684 MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3685 TX_JUMBO_DIS | TX_STFW_ENA); 3686 } 3687 break; 3688 } 3689 } 3690 3691 static void 3692 msk_init(void *xsc) 3693 { 3694 struct msk_if_softc *sc_if = xsc; 3695 3696 MSK_IF_LOCK(sc_if); 3697 msk_init_locked(sc_if); 3698 MSK_IF_UNLOCK(sc_if); 3699 } 3700 3701 static void 3702 msk_init_locked(struct msk_if_softc *sc_if) 3703 { 3704 struct msk_softc *sc; 3705 struct ifnet *ifp; 3706 struct mii_data *mii; 3707 uint8_t *eaddr; 3708 uint16_t gmac; 3709 uint32_t reg; 3710 int error; 3711 3712 MSK_IF_LOCK_ASSERT(sc_if); 3713 3714 ifp = sc_if->msk_ifp; 3715 sc = sc_if->msk_softc; 3716 mii = device_get_softc(sc_if->msk_miibus); 3717 3718 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3719 return; 3720 3721 error = 0; 3722 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3723 msk_stop(sc_if); 3724 3725 if (ifp->if_mtu < ETHERMTU) 3726 sc_if->msk_framesize = ETHERMTU; 3727 else 3728 sc_if->msk_framesize = ifp->if_mtu; 3729 sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN; 3730 if (ifp->if_mtu > ETHERMTU && 3731 (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) { 3732 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 3733 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 3734 } 3735 3736 /* GMAC Control reset. */ 3737 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET); 3738 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR); 3739 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF); 3740 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) 3741 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), 3742 GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON | 3743 GMC_BYP_RETR_ON); 3744 3745 /* 3746 * Initialize GMAC first such that speed/duplex/flow-control 3747 * parameters are renegotiated when interface is brought up. 3748 */ 3749 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0); 3750 3751 /* Dummy read the Interrupt Source Register. */ 3752 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3753 3754 /* Clear MIB stats. */ 3755 msk_stats_clear(sc_if); 3756 3757 /* Disable FCS. */ 3758 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3759 3760 /* Setup Transmit Control Register. */ 3761 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3762 3763 /* Setup Transmit Flow Control Register. */ 3764 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3765 3766 /* Setup Transmit Parameter Register. */ 3767 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3768 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3769 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3770 3771 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3772 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3773 3774 if (ifp->if_mtu > ETHERMTU) 3775 gmac |= GM_SMOD_JUMBO_ENA; 3776 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3777 3778 /* Set station address. */ 3779 eaddr = IF_LLADDR(ifp); 3780 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L, 3781 eaddr[0] | (eaddr[1] << 8)); 3782 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M, 3783 eaddr[2] | (eaddr[3] << 8)); 3784 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H, 3785 eaddr[4] | (eaddr[5] << 8)); 3786 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L, 3787 eaddr[0] | (eaddr[1] << 8)); 3788 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M, 3789 eaddr[2] | (eaddr[3] << 8)); 3790 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H, 3791 eaddr[4] | (eaddr[5] << 8)); 3792 3793 /* Disable interrupts for counter overflows. */ 3794 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3795 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3796 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3797 3798 /* Configure Rx MAC FIFO. */ 3799 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3800 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3801 reg = GMF_OPER_ON | GMF_RX_F_FL_ON; 3802 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P || 3803 sc->msk_hw_id == CHIP_ID_YUKON_EX) 3804 reg |= GMF_RX_OVER_ON; 3805 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg); 3806 3807 /* Set receive filter. */ 3808 msk_rxfilter(sc_if); 3809 3810 if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { 3811 /* Clear flush mask - HW bug. */ 3812 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0); 3813 } else { 3814 /* Flush Rx MAC FIFO on any flow control or error. */ 3815 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3816 GMR_FS_ANY_ERR); 3817 } 3818 3819 /* 3820 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 3821 * due to hardware hang on receipt of pause frames. 3822 */ 3823 reg = RX_GMF_FL_THR_DEF + 1; 3824 /* Another magic for Yukon FE+ - From Linux. */ 3825 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3826 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) 3827 reg = 0x178; 3828 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg); 3829 3830 /* Configure Tx MAC FIFO. */ 3831 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3832 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3833 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3834 3835 /* Configure hardware VLAN tag insertion/stripping. */ 3836 msk_setvlan(sc_if, ifp); 3837 3838 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) { 3839 /* Set Rx Pause threshold. */ 3840 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3841 MSK_ECU_LLPP); 3842 CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3843 MSK_ECU_ULPP); 3844 /* Configure store-and-forward for Tx. */ 3845 msk_set_tx_stfwd(sc_if); 3846 } 3847 3848 if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P && 3849 sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) { 3850 /* Disable dynamic watermark - from Linux. */ 3851 reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA)); 3852 reg &= ~0x03; 3853 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg); 3854 } 3855 3856 /* 3857 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3858 * arbiter as we don't use Sync Tx queue. 3859 */ 3860 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3861 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3862 /* Enable the RAM Interface Arbiter. */ 3863 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3864 3865 /* Setup RAM buffer. */ 3866 msk_set_rambuffer(sc_if); 3867 3868 /* Disable Tx sync Queue. */ 3869 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3870 3871 /* Setup Tx Queue Bus Memory Interface. */ 3872 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3873 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3874 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3875 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3876 switch (sc->msk_hw_id) { 3877 case CHIP_ID_YUKON_EC_U: 3878 if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3879 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3880 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), 3881 MSK_ECU_TXFF_LEV); 3882 } 3883 break; 3884 case CHIP_ID_YUKON_EX: 3885 /* 3886 * Yukon Extreme seems to have silicon bug for 3887 * automatic Tx checksum calculation capability. 3888 */ 3889 if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0) 3890 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F), 3891 F_TX_CHK_AUTO_OFF); 3892 break; 3893 } 3894 3895 /* Setup Rx Queue Bus Memory Interface. */ 3896 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3897 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3898 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3899 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3900 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3901 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3902 /* MAC Rx RAM Read is controlled by hardware. */ 3903 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3904 } 3905 3906 msk_set_prefetch(sc, sc_if->msk_txq, 3907 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3908 msk_init_tx_ring(sc_if); 3909 3910 /* Disable Rx checksum offload and RSS hash. */ 3911 reg = BMU_DIS_RX_RSS_HASH; 3912 if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 && 3913 (ifp->if_capenable & IFCAP_RXCSUM) != 0) 3914 reg |= BMU_ENA_RX_CHKSUM; 3915 else 3916 reg |= BMU_DIS_RX_CHKSUM; 3917 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg); 3918 if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) { 3919 msk_set_prefetch(sc, sc_if->msk_rxq, 3920 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 3921 MSK_JUMBO_RX_RING_CNT - 1); 3922 error = msk_init_jumbo_rx_ring(sc_if); 3923 } else { 3924 msk_set_prefetch(sc, sc_if->msk_rxq, 3925 sc_if->msk_rdata.msk_rx_ring_paddr, 3926 MSK_RX_RING_CNT - 1); 3927 error = msk_init_rx_ring(sc_if); 3928 } 3929 if (error != 0) { 3930 device_printf(sc_if->msk_if_dev, 3931 "initialization failed: no memory for Rx buffers\n"); 3932 msk_stop(sc_if); 3933 return; 3934 } 3935 if (sc->msk_hw_id == CHIP_ID_YUKON_EX) { 3936 /* Disable flushing of non-ASF packets. */ 3937 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3938 GMF_RX_MACSEC_FLUSH_OFF); 3939 } 3940 3941 /* Configure interrupt handling. */ 3942 if (sc_if->msk_port == MSK_PORT_A) { 3943 sc->msk_intrmask |= Y2_IS_PORT_A; 3944 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 3945 } else { 3946 sc->msk_intrmask |= Y2_IS_PORT_B; 3947 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 3948 } 3949 /* Configure IRQ moderation mask. */ 3950 CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask); 3951 if (sc->msk_int_holdoff > 0) { 3952 /* Configure initial IRQ moderation timer value. */ 3953 CSR_WRITE_4(sc, B2_IRQM_INI, 3954 MSK_USECS(sc, sc->msk_int_holdoff)); 3955 CSR_WRITE_4(sc, B2_IRQM_VAL, 3956 MSK_USECS(sc, sc->msk_int_holdoff)); 3957 /* Start IRQ moderation. */ 3958 CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START); 3959 } 3960 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3961 CSR_READ_4(sc, B0_HWE_IMSK); 3962 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3963 CSR_READ_4(sc, B0_IMSK); 3964 3965 sc_if->msk_flags &= ~MSK_FLAG_LINK; 3966 mii_mediachg(mii); 3967 3968 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3969 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3970 3971 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3972 } 3973 3974 static void 3975 msk_set_rambuffer(struct msk_if_softc *sc_if) 3976 { 3977 struct msk_softc *sc; 3978 int ltpp, utpp; 3979 3980 sc = sc_if->msk_softc; 3981 if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) 3982 return; 3983 3984 /* Setup Rx Queue. */ 3985 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 3986 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 3987 sc->msk_rxqstart[sc_if->msk_port] / 8); 3988 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 3989 sc->msk_rxqend[sc_if->msk_port] / 8); 3990 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 3991 sc->msk_rxqstart[sc_if->msk_port] / 8); 3992 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 3993 sc->msk_rxqstart[sc_if->msk_port] / 8); 3994 3995 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3996 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 3997 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3998 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 3999 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 4000 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 4001 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 4002 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 4003 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 4004 4005 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 4006 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 4007 4008 /* Setup Tx Queue. */ 4009 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 4010 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 4011 sc->msk_txqstart[sc_if->msk_port] / 8); 4012 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 4013 sc->msk_txqend[sc_if->msk_port] / 8); 4014 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 4015 sc->msk_txqstart[sc_if->msk_port] / 8); 4016 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 4017 sc->msk_txqstart[sc_if->msk_port] / 8); 4018 /* Enable Store & Forward for Tx side. */ 4019 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 4020 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 4021 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 4022 } 4023 4024 static void 4025 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 4026 uint32_t count) 4027 { 4028 4029 /* Reset the prefetch unit. */ 4030 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4031 PREF_UNIT_RST_SET); 4032 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4033 PREF_UNIT_RST_CLR); 4034 /* Set LE base address. */ 4035 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 4036 MSK_ADDR_LO(addr)); 4037 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 4038 MSK_ADDR_HI(addr)); 4039 /* Set the list last index. */ 4040 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 4041 count); 4042 /* Turn on prefetch unit. */ 4043 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 4044 PREF_UNIT_OP_ON); 4045 /* Dummy read to ensure write. */ 4046 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 4047 } 4048 4049 static void 4050 msk_stop(struct msk_if_softc *sc_if) 4051 { 4052 struct msk_softc *sc; 4053 struct msk_txdesc *txd; 4054 struct msk_rxdesc *rxd; 4055 struct msk_rxdesc *jrxd; 4056 struct ifnet *ifp; 4057 uint32_t val; 4058 int i; 4059 4060 MSK_IF_LOCK_ASSERT(sc_if); 4061 sc = sc_if->msk_softc; 4062 ifp = sc_if->msk_ifp; 4063 4064 callout_stop(&sc_if->msk_tick_ch); 4065 sc_if->msk_watchdog_timer = 0; 4066 4067 /* Disable interrupts. */ 4068 if (sc_if->msk_port == MSK_PORT_A) { 4069 sc->msk_intrmask &= ~Y2_IS_PORT_A; 4070 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 4071 } else { 4072 sc->msk_intrmask &= ~Y2_IS_PORT_B; 4073 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 4074 } 4075 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 4076 CSR_READ_4(sc, B0_HWE_IMSK); 4077 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 4078 CSR_READ_4(sc, B0_IMSK); 4079 4080 /* Disable Tx/Rx MAC. */ 4081 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4082 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 4083 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 4084 /* Read again to ensure writing. */ 4085 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 4086 /* Update stats and clear counters. */ 4087 msk_stats_update(sc_if); 4088 4089 /* Stop Tx BMU. */ 4090 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 4091 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4092 for (i = 0; i < MSK_TIMEOUT; i++) { 4093 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 4094 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4095 BMU_STOP); 4096 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 4097 } else 4098 break; 4099 DELAY(1); 4100 } 4101 if (i == MSK_TIMEOUT) 4102 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 4103 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 4104 RB_RST_SET | RB_DIS_OP_MD); 4105 4106 /* Disable all GMAC interrupt. */ 4107 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 4108 /* Disable PHY interrupt. */ 4109 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 4110 4111 /* Disable the RAM Interface Arbiter. */ 4112 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 4113 4114 /* Reset the PCI FIFO of the async Tx queue */ 4115 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4116 BMU_RST_SET | BMU_FIFO_RST); 4117 4118 /* Reset the Tx prefetch units. */ 4119 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 4120 PREF_UNIT_RST_SET); 4121 4122 /* Reset the RAM Buffer async Tx queue. */ 4123 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 4124 4125 /* Reset Tx MAC FIFO. */ 4126 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 4127 /* Set Pause Off. */ 4128 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 4129 4130 /* 4131 * The Rx Stop command will not work for Yukon-2 if the BMU does not 4132 * reach the end of packet and since we can't make sure that we have 4133 * incoming data, we must reset the BMU while it is not during a DMA 4134 * transfer. Since it is possible that the Rx path is still active, 4135 * the Rx RAM buffer will be stopped first, so any possible incoming 4136 * data will not trigger a DMA. After the RAM buffer is stopped, the 4137 * BMU is polled until any DMA in progress is ended and only then it 4138 * will be reset. 4139 */ 4140 4141 /* Disable the RAM Buffer receive queue. */ 4142 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 4143 for (i = 0; i < MSK_TIMEOUT; i++) { 4144 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 4145 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 4146 break; 4147 DELAY(1); 4148 } 4149 if (i == MSK_TIMEOUT) 4150 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 4151 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 4152 BMU_RST_SET | BMU_FIFO_RST); 4153 /* Reset the Rx prefetch unit. */ 4154 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 4155 PREF_UNIT_RST_SET); 4156 /* Reset the RAM Buffer receive queue. */ 4157 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 4158 /* Reset Rx MAC FIFO. */ 4159 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 4160 4161 /* Free Rx and Tx mbufs still in the queues. */ 4162 for (i = 0; i < MSK_RX_RING_CNT; i++) { 4163 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 4164 if (rxd->rx_m != NULL) { 4165 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 4166 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4167 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 4168 rxd->rx_dmamap); 4169 m_freem(rxd->rx_m); 4170 rxd->rx_m = NULL; 4171 } 4172 } 4173 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 4174 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 4175 if (jrxd->rx_m != NULL) { 4176 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 4177 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4178 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 4179 jrxd->rx_dmamap); 4180 m_freem(jrxd->rx_m); 4181 jrxd->rx_m = NULL; 4182 } 4183 } 4184 for (i = 0; i < MSK_TX_RING_CNT; i++) { 4185 txd = &sc_if->msk_cdata.msk_txdesc[i]; 4186 if (txd->tx_m != NULL) { 4187 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 4188 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4189 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 4190 txd->tx_dmamap); 4191 m_freem(txd->tx_m); 4192 txd->tx_m = NULL; 4193 } 4194 } 4195 4196 /* 4197 * Mark the interface down. 4198 */ 4199 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4200 sc_if->msk_flags &= ~MSK_FLAG_LINK; 4201 } 4202 4203 /* 4204 * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower 4205 * counter clears high 16 bits of the counter such that accessing 4206 * lower 16 bits should be the last operation. 4207 */ 4208 #define MSK_READ_MIB32(x, y) \ 4209 (((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) + \ 4210 (uint32_t)GMAC_READ_2(sc, x, y) 4211 #define MSK_READ_MIB64(x, y) \ 4212 (((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) + \ 4213 (uint64_t)MSK_READ_MIB32(x, y) 4214 4215 static void 4216 msk_stats_clear(struct msk_if_softc *sc_if) 4217 { 4218 struct msk_softc *sc; 4219 uint32_t reg; 4220 uint16_t gmac; 4221 int i; 4222 4223 MSK_IF_LOCK_ASSERT(sc_if); 4224 4225 sc = sc_if->msk_softc; 4226 /* Set MIB Clear Counter Mode. */ 4227 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4228 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4229 /* Read all MIB Counters with Clear Mode set. */ 4230 for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t)) 4231 reg = MSK_READ_MIB32(sc_if->msk_port, i); 4232 /* Clear MIB Clear Counter Mode. */ 4233 gmac &= ~GM_PAR_MIB_CLR; 4234 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4235 } 4236 4237 static void 4238 msk_stats_update(struct msk_if_softc *sc_if) 4239 { 4240 struct msk_softc *sc; 4241 struct ifnet *ifp; 4242 struct msk_hw_stats *stats; 4243 uint16_t gmac; 4244 uint32_t reg; 4245 4246 MSK_IF_LOCK_ASSERT(sc_if); 4247 4248 ifp = sc_if->msk_ifp; 4249 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 4250 return; 4251 sc = sc_if->msk_softc; 4252 stats = &sc_if->msk_stats; 4253 /* Set MIB Clear Counter Mode. */ 4254 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 4255 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 4256 4257 /* Rx stats. */ 4258 stats->rx_ucast_frames += 4259 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK); 4260 stats->rx_bcast_frames += 4261 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK); 4262 stats->rx_pause_frames += 4263 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE); 4264 stats->rx_mcast_frames += 4265 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK); 4266 stats->rx_crc_errs += 4267 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR); 4268 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE1); 4269 stats->rx_good_octets += 4270 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO); 4271 stats->rx_bad_octets += 4272 MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO); 4273 stats->rx_runts += 4274 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT); 4275 stats->rx_runt_errs += 4276 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG); 4277 stats->rx_pkts_64 += 4278 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B); 4279 stats->rx_pkts_65_127 += 4280 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B); 4281 stats->rx_pkts_128_255 += 4282 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B); 4283 stats->rx_pkts_256_511 += 4284 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B); 4285 stats->rx_pkts_512_1023 += 4286 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B); 4287 stats->rx_pkts_1024_1518 += 4288 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B); 4289 stats->rx_pkts_1519_max += 4290 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ); 4291 stats->rx_pkts_too_long += 4292 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR); 4293 stats->rx_pkts_jabbers += 4294 MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT); 4295 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE2); 4296 stats->rx_fifo_oflows += 4297 MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV); 4298 reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE3); 4299 4300 /* Tx stats. */ 4301 stats->tx_ucast_frames += 4302 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK); 4303 stats->tx_bcast_frames += 4304 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK); 4305 stats->tx_pause_frames += 4306 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE); 4307 stats->tx_mcast_frames += 4308 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK); 4309 stats->tx_octets += 4310 MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO); 4311 stats->tx_pkts_64 += 4312 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B); 4313 stats->tx_pkts_65_127 += 4314 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B); 4315 stats->tx_pkts_128_255 += 4316 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B); 4317 stats->tx_pkts_256_511 += 4318 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B); 4319 stats->tx_pkts_512_1023 += 4320 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B); 4321 stats->tx_pkts_1024_1518 += 4322 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B); 4323 stats->tx_pkts_1519_max += 4324 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ); 4325 reg = MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SPARE1); 4326 stats->tx_colls += 4327 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL); 4328 stats->tx_late_colls += 4329 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL); 4330 stats->tx_excess_colls += 4331 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL); 4332 stats->tx_multi_colls += 4333 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL); 4334 stats->tx_single_colls += 4335 MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL); 4336 stats->tx_underflows += 4337 MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR); 4338 /* Clear MIB Clear Counter Mode. */ 4339 gmac &= ~GM_PAR_MIB_CLR; 4340 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 4341 } 4342 4343 static int 4344 msk_sysctl_stat32(SYSCTL_HANDLER_ARGS) 4345 { 4346 struct msk_softc *sc; 4347 struct msk_if_softc *sc_if; 4348 uint32_t result, *stat; 4349 int off; 4350 4351 sc_if = (struct msk_if_softc *)arg1; 4352 sc = sc_if->msk_softc; 4353 off = arg2; 4354 stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off); 4355 4356 MSK_IF_LOCK(sc_if); 4357 result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4358 result += *stat; 4359 MSK_IF_UNLOCK(sc_if); 4360 4361 return (sysctl_handle_int(oidp, &result, 0, req)); 4362 } 4363 4364 static int 4365 msk_sysctl_stat64(SYSCTL_HANDLER_ARGS) 4366 { 4367 struct msk_softc *sc; 4368 struct msk_if_softc *sc_if; 4369 uint64_t result, *stat; 4370 int off; 4371 4372 sc_if = (struct msk_if_softc *)arg1; 4373 sc = sc_if->msk_softc; 4374 off = arg2; 4375 stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off); 4376 4377 MSK_IF_LOCK(sc_if); 4378 result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2); 4379 result += *stat; 4380 MSK_IF_UNLOCK(sc_if); 4381 4382 return (sysctl_handle_64(oidp, &result, 0, req)); 4383 } 4384 4385 #undef MSK_READ_MIB32 4386 #undef MSK_READ_MIB64 4387 4388 #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) \ 4389 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, \ 4390 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32, \ 4391 "IU", d) 4392 #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) \ 4393 SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_U64 | CTLFLAG_RD, \ 4394 sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64, \ 4395 "QU", d) 4396 4397 static void 4398 msk_sysctl_node(struct msk_if_softc *sc_if) 4399 { 4400 struct sysctl_ctx_list *ctx; 4401 struct sysctl_oid_list *child, *schild; 4402 struct sysctl_oid *tree; 4403 4404 ctx = device_get_sysctl_ctx(sc_if->msk_if_dev); 4405 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev)); 4406 4407 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 4408 NULL, "MSK Statistics"); 4409 schild = child = SYSCTL_CHILDREN(tree); 4410 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD, 4411 NULL, "MSK RX Statistics"); 4412 child = SYSCTL_CHILDREN(tree); 4413 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4414 child, rx_ucast_frames, "Good unicast frames"); 4415 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4416 child, rx_bcast_frames, "Good broadcast frames"); 4417 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4418 child, rx_pause_frames, "Pause frames"); 4419 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4420 child, rx_mcast_frames, "Multicast frames"); 4421 MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs", 4422 child, rx_crc_errs, "CRC errors"); 4423 MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets", 4424 child, rx_good_octets, "Good octets"); 4425 MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets", 4426 child, rx_bad_octets, "Bad octets"); 4427 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4428 child, rx_pkts_64, "64 bytes frames"); 4429 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4430 child, rx_pkts_65_127, "65 to 127 bytes frames"); 4431 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4432 child, rx_pkts_128_255, "128 to 255 bytes frames"); 4433 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4434 child, rx_pkts_256_511, "256 to 511 bytes frames"); 4435 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4436 child, rx_pkts_512_1023, "512 to 1023 bytes frames"); 4437 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4438 child, rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4439 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4440 child, rx_pkts_1519_max, "1519 to max frames"); 4441 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long", 4442 child, rx_pkts_too_long, "frames too long"); 4443 MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers", 4444 child, rx_pkts_jabbers, "Jabber errors"); 4445 MSK_SYSCTL_STAT32(sc_if, ctx, "overflows", 4446 child, rx_fifo_oflows, "FIFO overflows"); 4447 4448 tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD, 4449 NULL, "MSK TX Statistics"); 4450 child = SYSCTL_CHILDREN(tree); 4451 MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames", 4452 child, tx_ucast_frames, "Unicast frames"); 4453 MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames", 4454 child, tx_bcast_frames, "Broadcast frames"); 4455 MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames", 4456 child, tx_pause_frames, "Pause frames"); 4457 MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames", 4458 child, tx_mcast_frames, "Multicast frames"); 4459 MSK_SYSCTL_STAT64(sc_if, ctx, "octets", 4460 child, tx_octets, "Octets"); 4461 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64", 4462 child, tx_pkts_64, "64 bytes frames"); 4463 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127", 4464 child, tx_pkts_65_127, "65 to 127 bytes frames"); 4465 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255", 4466 child, tx_pkts_128_255, "128 to 255 bytes frames"); 4467 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511", 4468 child, tx_pkts_256_511, "256 to 511 bytes frames"); 4469 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023", 4470 child, tx_pkts_512_1023, "512 to 1023 bytes frames"); 4471 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518", 4472 child, tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 4473 MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max", 4474 child, tx_pkts_1519_max, "1519 to max frames"); 4475 MSK_SYSCTL_STAT32(sc_if, ctx, "colls", 4476 child, tx_colls, "Collisions"); 4477 MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls", 4478 child, tx_late_colls, "Late collisions"); 4479 MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls", 4480 child, tx_excess_colls, "Excessive collisions"); 4481 MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls", 4482 child, tx_multi_colls, "Multiple collisions"); 4483 MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls", 4484 child, tx_single_colls, "Single collisions"); 4485 MSK_SYSCTL_STAT32(sc_if, ctx, "underflows", 4486 child, tx_underflows, "FIFO underflows"); 4487 } 4488 4489 #undef MSK_SYSCTL_STAT32 4490 #undef MSK_SYSCTL_STAT64 4491 4492 static int 4493 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4494 { 4495 int error, value; 4496 4497 if (!arg1) 4498 return (EINVAL); 4499 value = *(int *)arg1; 4500 error = sysctl_handle_int(oidp, &value, 0, req); 4501 if (error || !req->newptr) 4502 return (error); 4503 if (value < low || value > high) 4504 return (EINVAL); 4505 *(int *)arg1 = value; 4506 4507 return (0); 4508 } 4509 4510 static int 4511 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4512 { 4513 4514 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4515 MSK_PROC_MAX)); 4516 } 4517