1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 /*- 80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 81 * 82 * Permission to use, copy, modify, and distribute this software for any 83 * purpose with or without fee is hereby granted, provided that the above 84 * copyright notice and this permission notice appear in all copies. 85 * 86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 93 */ 94 95 /* 96 * Device driver for the Marvell Yukon II Ethernet controller. 97 * Due to lack of documentation, this driver is based on the code from 98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 99 */ 100 101 #include <sys/cdefs.h> 102 __FBSDID("$FreeBSD$"); 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/bus.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/sockio.h> 114 #include <sys/queue.h> 115 #include <sys/sysctl.h> 116 #include <sys/taskqueue.h> 117 118 #include <net/bpf.h> 119 #include <net/ethernet.h> 120 #include <net/if.h> 121 #include <net/if_arp.h> 122 #include <net/if_dl.h> 123 #include <net/if_media.h> 124 #include <net/if_types.h> 125 #include <net/if_vlan_var.h> 126 127 #include <netinet/in.h> 128 #include <netinet/in_systm.h> 129 #include <netinet/ip.h> 130 #include <netinet/tcp.h> 131 #include <netinet/udp.h> 132 133 #include <machine/bus.h> 134 #include <machine/in_cksum.h> 135 #include <machine/resource.h> 136 #include <sys/rman.h> 137 138 #include <dev/mii/mii.h> 139 #include <dev/mii/miivar.h> 140 #include <dev/mii/brgphyreg.h> 141 142 #include <dev/pci/pcireg.h> 143 #include <dev/pci/pcivar.h> 144 145 #include <dev/msk/if_mskreg.h> 146 147 MODULE_DEPEND(msk, pci, 1, 1, 1); 148 MODULE_DEPEND(msk, ether, 1, 1, 1); 149 MODULE_DEPEND(msk, miibus, 1, 1, 1); 150 151 /* "device miibus" required. See GENERIC if you get errors here. */ 152 #include "miibus_if.h" 153 154 /* Tunables. */ 155 static int msi_disable = 0; 156 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 157 static int legacy_intr = 0; 158 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 159 160 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 161 162 /* 163 * Devices supported by this driver. 164 */ 165 static struct msk_product { 166 uint16_t msk_vendorid; 167 uint16_t msk_deviceid; 168 const char *msk_name; 169 } msk_products[] = { 170 { VENDORID_SK, DEVICEID_SK_YUKON2, 171 "SK-9Sxx Gigabit Ethernet" }, 172 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 173 "SK-9Exx Gigabit Ethernet"}, 174 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 175 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 176 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 177 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 178 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 179 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 180 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 181 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 182 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 183 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 184 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 185 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 186 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 187 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 188 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 189 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 190 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 191 "Marvell Yukon 88E8035 Gigabit Ethernet" }, 192 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 193 "Marvell Yukon 88E8036 Gigabit Ethernet" }, 194 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 195 "Marvell Yukon 88E8038 Gigabit Ethernet" }, 196 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 197 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 198 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 199 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 200 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 201 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 202 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 203 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 204 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 205 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 206 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 207 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 208 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 209 "D-Link 550SX Gigabit Ethernet" }, 210 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 211 "D-Link 560T Gigabit Ethernet" } 212 }; 213 214 static const char *model_name[] = { 215 "Yukon XL", 216 "Yukon EC Ultra", 217 "Yukon Unknown", 218 "Yukon EC", 219 "Yukon FE" 220 }; 221 222 static int mskc_probe(device_t); 223 static int mskc_attach(device_t); 224 static int mskc_detach(device_t); 225 static int mskc_shutdown(device_t); 226 static int mskc_setup_rambuffer(struct msk_softc *); 227 static int mskc_suspend(device_t); 228 static int mskc_resume(device_t); 229 static void mskc_reset(struct msk_softc *); 230 231 static int msk_probe(device_t); 232 static int msk_attach(device_t); 233 static int msk_detach(device_t); 234 235 static void msk_tick(void *); 236 static void msk_legacy_intr(void *); 237 static int msk_intr(void *); 238 static void msk_int_task(void *, int); 239 static void msk_intr_phy(struct msk_if_softc *); 240 static void msk_intr_gmac(struct msk_if_softc *); 241 static __inline void msk_rxput(struct msk_if_softc *); 242 static int msk_handle_events(struct msk_softc *); 243 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 244 static void msk_intr_hwerr(struct msk_softc *); 245 static void msk_rxeof(struct msk_if_softc *, uint32_t, int); 246 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, int); 247 static void msk_txeof(struct msk_if_softc *, int); 248 static struct mbuf *msk_defrag(struct mbuf *, int, int); 249 static int msk_encap(struct msk_if_softc *, struct mbuf **); 250 static void msk_tx_task(void *, int); 251 static void msk_start(struct ifnet *); 252 static int msk_ioctl(struct ifnet *, u_long, caddr_t); 253 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 254 static void msk_set_rambuffer(struct msk_if_softc *); 255 static void msk_init(void *); 256 static void msk_init_locked(struct msk_if_softc *); 257 static void msk_stop(struct msk_if_softc *); 258 static void msk_watchdog(struct msk_if_softc *); 259 static int msk_mediachange(struct ifnet *); 260 static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 261 static void msk_phy_power(struct msk_softc *, int); 262 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 263 static int msk_status_dma_alloc(struct msk_softc *); 264 static void msk_status_dma_free(struct msk_softc *); 265 static int msk_txrx_dma_alloc(struct msk_if_softc *); 266 static void msk_txrx_dma_free(struct msk_if_softc *); 267 static void *msk_jalloc(struct msk_if_softc *); 268 static void msk_jfree(void *, void *); 269 static int msk_init_rx_ring(struct msk_if_softc *); 270 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 271 static void msk_init_tx_ring(struct msk_if_softc *); 272 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 273 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 274 static int msk_newbuf(struct msk_if_softc *, int); 275 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 276 277 static int msk_phy_readreg(struct msk_if_softc *, int, int); 278 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 279 static int msk_miibus_readreg(device_t, int, int); 280 static int msk_miibus_writereg(device_t, int, int, int); 281 static void msk_miibus_statchg(device_t); 282 static void msk_link_task(void *, int); 283 284 static void msk_setmulti(struct msk_if_softc *); 285 static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 286 static void msk_setpromisc(struct msk_if_softc *); 287 288 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 289 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 290 291 static device_method_t mskc_methods[] = { 292 /* Device interface */ 293 DEVMETHOD(device_probe, mskc_probe), 294 DEVMETHOD(device_attach, mskc_attach), 295 DEVMETHOD(device_detach, mskc_detach), 296 DEVMETHOD(device_suspend, mskc_suspend), 297 DEVMETHOD(device_resume, mskc_resume), 298 DEVMETHOD(device_shutdown, mskc_shutdown), 299 300 /* bus interface */ 301 DEVMETHOD(bus_print_child, bus_generic_print_child), 302 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 303 304 { NULL, NULL } 305 }; 306 307 static driver_t mskc_driver = { 308 "mskc", 309 mskc_methods, 310 sizeof(struct msk_softc) 311 }; 312 313 static devclass_t mskc_devclass; 314 315 static device_method_t msk_methods[] = { 316 /* Device interface */ 317 DEVMETHOD(device_probe, msk_probe), 318 DEVMETHOD(device_attach, msk_attach), 319 DEVMETHOD(device_detach, msk_detach), 320 DEVMETHOD(device_shutdown, bus_generic_shutdown), 321 322 /* bus interface */ 323 DEVMETHOD(bus_print_child, bus_generic_print_child), 324 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 325 326 /* MII interface */ 327 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 328 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 329 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 330 331 { NULL, NULL } 332 }; 333 334 static driver_t msk_driver = { 335 "msk", 336 msk_methods, 337 sizeof(struct msk_if_softc) 338 }; 339 340 static devclass_t msk_devclass; 341 342 DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0); 343 DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0); 344 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0); 345 346 static struct resource_spec msk_res_spec_io[] = { 347 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 348 { -1, 0, 0 } 349 }; 350 351 static struct resource_spec msk_res_spec_mem[] = { 352 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 353 { -1, 0, 0 } 354 }; 355 356 static struct resource_spec msk_irq_spec_legacy[] = { 357 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 358 { -1, 0, 0 } 359 }; 360 361 static struct resource_spec msk_irq_spec_msi[] = { 362 { SYS_RES_IRQ, 1, RF_ACTIVE }, 363 { -1, 0, 0 } 364 }; 365 366 static struct resource_spec msk_irq_spec_msi2[] = { 367 { SYS_RES_IRQ, 1, RF_ACTIVE }, 368 { SYS_RES_IRQ, 2, RF_ACTIVE }, 369 { -1, 0, 0 } 370 }; 371 372 static int 373 msk_miibus_readreg(device_t dev, int phy, int reg) 374 { 375 struct msk_if_softc *sc_if; 376 377 if (phy != PHY_ADDR_MARV) 378 return (0); 379 380 sc_if = device_get_softc(dev); 381 382 return (msk_phy_readreg(sc_if, phy, reg)); 383 } 384 385 static int 386 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 387 { 388 struct msk_softc *sc; 389 int i, val; 390 391 sc = sc_if->msk_softc; 392 393 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 394 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 395 396 for (i = 0; i < MSK_TIMEOUT; i++) { 397 DELAY(1); 398 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 399 if ((val & GM_SMI_CT_RD_VAL) != 0) { 400 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 401 break; 402 } 403 } 404 405 if (i == MSK_TIMEOUT) { 406 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 407 val = 0; 408 } 409 410 return (val); 411 } 412 413 static int 414 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 415 { 416 struct msk_if_softc *sc_if; 417 418 if (phy != PHY_ADDR_MARV) 419 return (0); 420 421 sc_if = device_get_softc(dev); 422 423 return (msk_phy_writereg(sc_if, phy, reg, val)); 424 } 425 426 static int 427 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 428 { 429 struct msk_softc *sc; 430 int i; 431 432 sc = sc_if->msk_softc; 433 434 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 435 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 436 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 437 for (i = 0; i < MSK_TIMEOUT; i++) { 438 DELAY(1); 439 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 440 GM_SMI_CT_BUSY) == 0) 441 break; 442 } 443 if (i == MSK_TIMEOUT) 444 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 445 446 return (0); 447 } 448 449 static void 450 msk_miibus_statchg(device_t dev) 451 { 452 struct msk_if_softc *sc_if; 453 454 sc_if = device_get_softc(dev); 455 taskqueue_enqueue(taskqueue_swi, &sc_if->msk_link_task); 456 } 457 458 static void 459 msk_link_task(void *arg, int pending) 460 { 461 struct msk_softc *sc; 462 struct msk_if_softc *sc_if; 463 struct mii_data *mii; 464 struct ifnet *ifp; 465 uint32_t gmac; 466 467 sc_if = (struct msk_if_softc *)arg; 468 sc = sc_if->msk_softc; 469 470 MSK_IF_LOCK(sc_if); 471 472 mii = device_get_softc(sc_if->msk_miibus); 473 ifp = sc_if->msk_ifp; 474 if (mii == NULL || ifp == NULL) { 475 MSK_IF_UNLOCK(sc_if); 476 return; 477 } 478 479 if (mii->mii_media_status & IFM_ACTIVE) { 480 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 481 sc_if->msk_link = 1; 482 } else 483 sc_if->msk_link = 0; 484 485 if (sc_if->msk_link != 0) { 486 /* Enable Tx FIFO Underrun. */ 487 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 488 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 489 /* 490 * Because mii(4) notify msk(4) that it detected link status 491 * change, there is no need to enable automatic 492 * speed/flow-control/duplex updates. 493 */ 494 gmac = GM_GPCR_AU_ALL_DIS; 495 switch (IFM_SUBTYPE(mii->mii_media_active)) { 496 case IFM_1000_SX: 497 case IFM_1000_T: 498 gmac |= GM_GPCR_SPEED_1000; 499 break; 500 case IFM_100_TX: 501 gmac |= GM_GPCR_SPEED_100; 502 break; 503 case IFM_10_T: 504 break; 505 } 506 507 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0) 508 gmac |= GM_GPCR_DUP_FULL; 509 /* Disable Rx flow control. */ 510 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) == 0) 511 gmac |= GM_GPCR_FC_RX_DIS; 512 /* Disable Tx flow control. */ 513 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) == 0) 514 gmac |= GM_GPCR_FC_TX_DIS; 515 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 516 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 517 /* Read again to ensure writing. */ 518 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 519 520 gmac = GMC_PAUSE_ON; 521 if (((mii->mii_media_active & IFM_GMASK) & 522 (IFM_FLAG0 | IFM_FLAG1)) == 0) 523 gmac = GMC_PAUSE_OFF; 524 /* Diable pause for 10/100 Mbps in half-duplex mode. */ 525 if ((((mii->mii_media_active & IFM_GMASK) & IFM_FDX) == 0) && 526 (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX || 527 IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)) 528 gmac = GMC_PAUSE_OFF; 529 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 530 531 /* Enable PHY interrupt for FIFO underrun/overflow. */ 532 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 533 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 534 } else { 535 /* 536 * Link state changed to down. 537 * Disable PHY interrupts. 538 */ 539 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 540 /* Disable Rx/Tx MAC. */ 541 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 542 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 543 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 544 /* Read again to ensure writing. */ 545 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 546 } 547 548 MSK_IF_UNLOCK(sc_if); 549 } 550 551 static void 552 msk_setmulti(struct msk_if_softc *sc_if) 553 { 554 struct msk_softc *sc; 555 struct ifnet *ifp; 556 struct ifmultiaddr *ifma; 557 uint32_t mchash[2]; 558 uint32_t crc; 559 uint16_t mode; 560 561 sc = sc_if->msk_softc; 562 563 MSK_IF_LOCK_ASSERT(sc_if); 564 565 ifp = sc_if->msk_ifp; 566 567 bzero(mchash, sizeof(mchash)); 568 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 569 mode |= GM_RXCR_UCF_ENA; 570 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 571 if ((ifp->if_flags & IFF_PROMISC) != 0) 572 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 573 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 574 mchash[0] = 0xffff; 575 mchash[1] = 0xffff; 576 } 577 } else { 578 IF_ADDR_LOCK(ifp); 579 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 580 if (ifma->ifma_addr->sa_family != AF_LINK) 581 continue; 582 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 583 ifma->ifma_addr), ETHER_ADDR_LEN); 584 /* Just want the 6 least significant bits. */ 585 crc &= 0x3f; 586 /* Set the corresponding bit in the hash table. */ 587 mchash[crc >> 5] |= 1 << (crc & 0x1f); 588 } 589 IF_ADDR_UNLOCK(ifp); 590 mode |= GM_RXCR_MCF_ENA; 591 } 592 593 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 594 mchash[0] & 0xffff); 595 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 596 (mchash[0] >> 16) & 0xffff); 597 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 598 mchash[1] & 0xffff); 599 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 600 (mchash[1] >> 16) & 0xffff); 601 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 602 } 603 604 static void 605 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 606 { 607 struct msk_softc *sc; 608 609 sc = sc_if->msk_softc; 610 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 611 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 612 RX_VLAN_STRIP_ON); 613 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 614 TX_VLAN_TAG_ON); 615 } else { 616 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 617 RX_VLAN_STRIP_OFF); 618 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 619 TX_VLAN_TAG_OFF); 620 } 621 } 622 623 static void 624 msk_setpromisc(struct msk_if_softc *sc_if) 625 { 626 struct msk_softc *sc; 627 struct ifnet *ifp; 628 uint16_t mode; 629 630 MSK_IF_LOCK_ASSERT(sc_if); 631 632 sc = sc_if->msk_softc; 633 ifp = sc_if->msk_ifp; 634 635 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 636 if (ifp->if_flags & IFF_PROMISC) 637 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 638 else 639 mode |= (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 640 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 641 } 642 643 static int 644 msk_init_rx_ring(struct msk_if_softc *sc_if) 645 { 646 struct msk_ring_data *rd; 647 struct msk_rxdesc *rxd; 648 int i, prod; 649 650 MSK_IF_LOCK_ASSERT(sc_if); 651 652 sc_if->msk_cdata.msk_rx_cons = 0; 653 sc_if->msk_cdata.msk_rx_prod = 0; 654 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 655 656 rd = &sc_if->msk_rdata; 657 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 658 prod = sc_if->msk_cdata.msk_rx_prod; 659 for (i = 0; i < MSK_RX_RING_CNT; i++) { 660 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 661 rxd->rx_m = NULL; 662 rxd->rx_le = &rd->msk_rx_ring[prod]; 663 if (msk_newbuf(sc_if, prod) != 0) 664 return (ENOBUFS); 665 MSK_INC(prod, MSK_RX_RING_CNT); 666 } 667 668 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 669 sc_if->msk_cdata.msk_rx_ring_map, 670 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 671 672 /* Update prefetch unit. */ 673 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1; 674 CSR_WRITE_2(sc_if->msk_softc, 675 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 676 sc_if->msk_cdata.msk_rx_prod); 677 678 return (0); 679 } 680 681 static int 682 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 683 { 684 struct msk_ring_data *rd; 685 struct msk_rxdesc *rxd; 686 int i, prod; 687 688 MSK_IF_LOCK_ASSERT(sc_if); 689 690 sc_if->msk_cdata.msk_rx_cons = 0; 691 sc_if->msk_cdata.msk_rx_prod = 0; 692 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 693 694 rd = &sc_if->msk_rdata; 695 bzero(rd->msk_jumbo_rx_ring, 696 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 697 prod = sc_if->msk_cdata.msk_rx_prod; 698 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 699 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 700 rxd->rx_m = NULL; 701 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 702 if (msk_jumbo_newbuf(sc_if, prod) != 0) 703 return (ENOBUFS); 704 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 705 } 706 707 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 708 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 709 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 710 711 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1; 712 CSR_WRITE_2(sc_if->msk_softc, 713 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 714 sc_if->msk_cdata.msk_rx_prod); 715 716 return (0); 717 } 718 719 static void 720 msk_init_tx_ring(struct msk_if_softc *sc_if) 721 { 722 struct msk_ring_data *rd; 723 struct msk_txdesc *txd; 724 int i; 725 726 sc_if->msk_cdata.msk_tso_mtu = 0; 727 sc_if->msk_cdata.msk_tx_prod = 0; 728 sc_if->msk_cdata.msk_tx_cons = 0; 729 sc_if->msk_cdata.msk_tx_cnt = 0; 730 731 rd = &sc_if->msk_rdata; 732 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 733 for (i = 0; i < MSK_TX_RING_CNT; i++) { 734 txd = &sc_if->msk_cdata.msk_txdesc[i]; 735 txd->tx_m = NULL; 736 txd->tx_le = &rd->msk_tx_ring[i]; 737 } 738 739 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 740 sc_if->msk_cdata.msk_tx_ring_map, 741 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 742 } 743 744 static __inline void 745 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 746 { 747 struct msk_rx_desc *rx_le; 748 struct msk_rxdesc *rxd; 749 struct mbuf *m; 750 751 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 752 m = rxd->rx_m; 753 rx_le = rxd->rx_le; 754 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 755 } 756 757 static __inline void 758 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 759 { 760 struct msk_rx_desc *rx_le; 761 struct msk_rxdesc *rxd; 762 struct mbuf *m; 763 764 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 765 m = rxd->rx_m; 766 rx_le = rxd->rx_le; 767 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 768 } 769 770 static int 771 msk_newbuf(struct msk_if_softc *sc_if, int idx) 772 { 773 struct msk_rx_desc *rx_le; 774 struct msk_rxdesc *rxd; 775 struct mbuf *m; 776 bus_dma_segment_t segs[1]; 777 bus_dmamap_t map; 778 int nsegs; 779 780 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 781 if (m == NULL) 782 return (ENOBUFS); 783 784 m->m_len = m->m_pkthdr.len = MCLBYTES; 785 m_adj(m, ETHER_ALIGN); 786 787 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 788 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 789 BUS_DMA_NOWAIT) != 0) { 790 m_freem(m); 791 return (ENOBUFS); 792 } 793 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 794 795 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 796 if (rxd->rx_m != NULL) { 797 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 798 BUS_DMASYNC_POSTREAD); 799 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 800 } 801 map = rxd->rx_dmamap; 802 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 803 sc_if->msk_cdata.msk_rx_sparemap = map; 804 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 805 BUS_DMASYNC_PREREAD); 806 rxd->rx_m = m; 807 rx_le = rxd->rx_le; 808 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 809 rx_le->msk_control = 810 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 811 812 return (0); 813 } 814 815 static int 816 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 817 { 818 struct msk_rx_desc *rx_le; 819 struct msk_rxdesc *rxd; 820 struct mbuf *m; 821 bus_dma_segment_t segs[1]; 822 bus_dmamap_t map; 823 int nsegs; 824 void *buf; 825 826 MGETHDR(m, M_DONTWAIT, MT_DATA); 827 if (m == NULL) 828 return (ENOBUFS); 829 buf = msk_jalloc(sc_if); 830 if (buf == NULL) { 831 m_freem(m); 832 return (ENOBUFS); 833 } 834 /* Attach the buffer to the mbuf. */ 835 MEXTADD(m, buf, MSK_JLEN, msk_jfree, (struct msk_if_softc *)sc_if, 0, 836 EXT_NET_DRV); 837 if ((m->m_flags & M_EXT) == 0) { 838 m_freem(m); 839 return (ENOBUFS); 840 } 841 m->m_pkthdr.len = m->m_len = MSK_JLEN; 842 m_adj(m, ETHER_ALIGN); 843 844 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 845 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 846 BUS_DMA_NOWAIT) != 0) { 847 m_freem(m); 848 return (ENOBUFS); 849 } 850 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 851 852 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 853 if (rxd->rx_m != NULL) { 854 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 855 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 856 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 857 rxd->rx_dmamap); 858 } 859 map = rxd->rx_dmamap; 860 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 861 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 862 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 863 BUS_DMASYNC_PREREAD); 864 rxd->rx_m = m; 865 rx_le = rxd->rx_le; 866 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 867 rx_le->msk_control = 868 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 869 870 return (0); 871 } 872 873 /* 874 * Set media options. 875 */ 876 static int 877 msk_mediachange(struct ifnet *ifp) 878 { 879 struct msk_if_softc *sc_if; 880 struct mii_data *mii; 881 882 sc_if = ifp->if_softc; 883 884 MSK_IF_LOCK(sc_if); 885 mii = device_get_softc(sc_if->msk_miibus); 886 mii_mediachg(mii); 887 MSK_IF_UNLOCK(sc_if); 888 889 return (0); 890 } 891 892 /* 893 * Report current media status. 894 */ 895 static void 896 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 897 { 898 struct msk_if_softc *sc_if; 899 struct mii_data *mii; 900 901 sc_if = ifp->if_softc; 902 MSK_IF_LOCK(sc_if); 903 mii = device_get_softc(sc_if->msk_miibus); 904 905 mii_pollstat(mii); 906 MSK_IF_UNLOCK(sc_if); 907 ifmr->ifm_active = mii->mii_media_active; 908 ifmr->ifm_status = mii->mii_media_status; 909 } 910 911 static int 912 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 913 { 914 struct msk_if_softc *sc_if; 915 struct ifreq *ifr; 916 struct mii_data *mii; 917 int error, mask; 918 919 sc_if = ifp->if_softc; 920 ifr = (struct ifreq *)data; 921 error = 0; 922 923 switch(command) { 924 case SIOCSIFMTU: 925 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) { 926 error = EINVAL; 927 break; 928 } 929 if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE && 930 ifr->ifr_mtu > MSK_MAX_FRAMELEN) { 931 error = EINVAL; 932 break; 933 } 934 MSK_IF_LOCK(sc_if); 935 ifp->if_mtu = ifr->ifr_mtu; 936 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 937 msk_init_locked(sc_if); 938 MSK_IF_UNLOCK(sc_if); 939 break; 940 case SIOCSIFFLAGS: 941 MSK_IF_LOCK(sc_if); 942 if ((ifp->if_flags & IFF_UP) != 0) { 943 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 944 if (((ifp->if_flags ^ sc_if->msk_if_flags) 945 & IFF_PROMISC) != 0) { 946 msk_setpromisc(sc_if); 947 msk_setmulti(sc_if); 948 } 949 } else { 950 if (sc_if->msk_detach == 0) 951 msk_init_locked(sc_if); 952 } 953 } else { 954 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 955 msk_stop(sc_if); 956 } 957 sc_if->msk_if_flags = ifp->if_flags; 958 MSK_IF_UNLOCK(sc_if); 959 break; 960 case SIOCADDMULTI: 961 case SIOCDELMULTI: 962 MSK_IF_LOCK(sc_if); 963 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 964 msk_setmulti(sc_if); 965 MSK_IF_UNLOCK(sc_if); 966 break; 967 case SIOCGIFMEDIA: 968 case SIOCSIFMEDIA: 969 mii = device_get_softc(sc_if->msk_miibus); 970 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 971 break; 972 case SIOCSIFCAP: 973 MSK_IF_LOCK(sc_if); 974 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 975 if ((mask & IFCAP_TXCSUM) != 0) { 976 ifp->if_capenable ^= IFCAP_TXCSUM; 977 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0 && 978 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) 979 ifp->if_hwassist |= MSK_CSUM_FEATURES; 980 else 981 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 982 } 983 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) { 984 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 985 msk_setvlan(sc_if, ifp); 986 } 987 988 if ((mask & IFCAP_TSO4) != 0) { 989 ifp->if_capenable ^= IFCAP_TSO4; 990 if ((IFCAP_TSO4 & ifp->if_capenable) != 0 && 991 (IFCAP_TSO4 & ifp->if_capabilities) != 0) 992 ifp->if_hwassist |= CSUM_TSO; 993 else 994 ifp->if_hwassist &= ~CSUM_TSO; 995 } 996 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN && 997 sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 998 /* 999 * In Yukon EC Ultra, TSO & checksum offload is not 1000 * supported for jumbo frame. 1001 */ 1002 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 1003 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1004 } 1005 1006 VLAN_CAPABILITIES(ifp); 1007 MSK_IF_UNLOCK(sc_if); 1008 break; 1009 default: 1010 error = ether_ioctl(ifp, command, data); 1011 break; 1012 } 1013 1014 return (error); 1015 } 1016 1017 static int 1018 mskc_probe(device_t dev) 1019 { 1020 struct msk_product *mp; 1021 uint16_t vendor, devid; 1022 int i; 1023 1024 vendor = pci_get_vendor(dev); 1025 devid = pci_get_device(dev); 1026 mp = msk_products; 1027 for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]); 1028 i++, mp++) { 1029 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1030 device_set_desc(dev, mp->msk_name); 1031 return (BUS_PROBE_DEFAULT); 1032 } 1033 } 1034 1035 return (ENXIO); 1036 } 1037 1038 static int 1039 mskc_setup_rambuffer(struct msk_softc *sc) 1040 { 1041 int next; 1042 int i; 1043 uint8_t val; 1044 1045 /* Get adapter SRAM size. */ 1046 val = CSR_READ_1(sc, B2_E_0); 1047 sc->msk_ramsize = (val == 0) ? 128 : val * 4; 1048 if (bootverbose) 1049 device_printf(sc->msk_dev, 1050 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1051 /* 1052 * Give receiver 2/3 of memory and round down to the multiple 1053 * of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple 1054 * of 1024. 1055 */ 1056 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1057 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1058 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1059 sc->msk_rxqstart[i] = next; 1060 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1061 next = sc->msk_rxqend[i] + 1; 1062 sc->msk_txqstart[i] = next; 1063 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1064 next = sc->msk_txqend[i] + 1; 1065 if (bootverbose) { 1066 device_printf(sc->msk_dev, 1067 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1068 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1069 sc->msk_rxqend[i]); 1070 device_printf(sc->msk_dev, 1071 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1072 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1073 sc->msk_txqend[i]); 1074 } 1075 } 1076 1077 return (0); 1078 } 1079 1080 static void 1081 msk_phy_power(struct msk_softc *sc, int mode) 1082 { 1083 uint32_t val; 1084 int i; 1085 1086 switch (mode) { 1087 case MSK_PHY_POWERUP: 1088 /* Switch power to VCC (WA for VAUX problem). */ 1089 CSR_WRITE_1(sc, B0_POWER_CTRL, 1090 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1091 /* Disable Core Clock Division, set Clock Select to 0. */ 1092 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1093 1094 val = 0; 1095 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1096 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1097 /* Enable bits are inverted. */ 1098 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1099 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1100 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1101 } 1102 /* 1103 * Enable PCI & Core Clock, enable clock gating for both Links. 1104 */ 1105 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1106 1107 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1108 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1109 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1110 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1111 /* Deassert Low Power for 1st PHY. */ 1112 val |= PCI_Y2_PHY1_COMA; 1113 if (sc->msk_num_port > 1) 1114 val |= PCI_Y2_PHY2_COMA; 1115 } else if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 1116 uint32_t our; 1117 1118 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); 1119 1120 /* Enable all clocks. */ 1121 pci_write_config(sc->msk_dev, PCI_OUR_REG_3, 0, 4); 1122 our = pci_read_config(sc->msk_dev, PCI_OUR_REG_4, 4); 1123 our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN| 1124 PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST); 1125 /* Set all bits to 0 except bits 15..12. */ 1126 pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4); 1127 /* Set to default value. */ 1128 pci_write_config(sc->msk_dev, PCI_OUR_REG_5, 0, 4); 1129 } 1130 /* Release PHY from PowerDown/COMA mode. */ 1131 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1132 for (i = 0; i < sc->msk_num_port; i++) { 1133 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1134 GMLC_RST_SET); 1135 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1136 GMLC_RST_CLR); 1137 } 1138 break; 1139 case MSK_PHY_POWERDOWN: 1140 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1141 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1142 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1143 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1144 val &= ~PCI_Y2_PHY1_COMA; 1145 if (sc->msk_num_port > 1) 1146 val &= ~PCI_Y2_PHY2_COMA; 1147 } 1148 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1149 1150 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1151 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1152 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1153 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1154 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1155 /* Enable bits are inverted. */ 1156 val = 0; 1157 } 1158 /* 1159 * Disable PCI & Core Clock, disable clock gating for 1160 * both Links. 1161 */ 1162 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1163 CSR_WRITE_1(sc, B0_POWER_CTRL, 1164 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1165 break; 1166 default: 1167 break; 1168 } 1169 } 1170 1171 static void 1172 mskc_reset(struct msk_softc *sc) 1173 { 1174 bus_addr_t addr; 1175 uint16_t status; 1176 uint32_t val; 1177 int i; 1178 1179 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1180 1181 /* Disable ASF. */ 1182 if (sc->msk_hw_id < CHIP_ID_YUKON_XL) { 1183 CSR_WRITE_4(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1184 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1185 } 1186 /* 1187 * Since we disabled ASF, S/W reset is required for Power Management. 1188 */ 1189 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1190 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1191 1192 /* Clear all error bits in the PCI status register. */ 1193 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1194 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1195 1196 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1197 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1198 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 1199 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1200 1201 switch (sc->msk_bustype) { 1202 case MSK_PEX_BUS: 1203 /* Clear all PEX errors. */ 1204 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1205 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1206 if ((val & PEX_RX_OV) != 0) { 1207 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1208 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1209 } 1210 break; 1211 case MSK_PCI_BUS: 1212 case MSK_PCIX_BUS: 1213 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1214 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1215 if (val == 0) 1216 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1217 if (sc->msk_bustype == MSK_PCIX_BUS) { 1218 /* Set Cache Line Size opt. */ 1219 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1220 val |= PCI_CLS_OPT; 1221 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1222 } 1223 break; 1224 } 1225 /* Set PHY power state. */ 1226 msk_phy_power(sc, MSK_PHY_POWERUP); 1227 1228 /* Reset GPHY/GMAC Control */ 1229 for (i = 0; i < sc->msk_num_port; i++) { 1230 /* GPHY Control reset. */ 1231 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1232 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1233 /* GMAC Control reset. */ 1234 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1235 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1236 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1237 } 1238 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1239 1240 /* LED On. */ 1241 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1242 1243 /* Clear TWSI IRQ. */ 1244 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1245 1246 /* Turn off hardware timer. */ 1247 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1248 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1249 1250 /* Turn off descriptor polling. */ 1251 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1252 1253 /* Turn off time stamps. */ 1254 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1255 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1256 1257 /* Configure timeout values. */ 1258 for (i = 0; i < sc->msk_num_port; i++) { 1259 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1260 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1261 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1262 MSK_RI_TO_53); 1263 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1264 MSK_RI_TO_53); 1265 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1266 MSK_RI_TO_53); 1267 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1268 MSK_RI_TO_53); 1269 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1270 MSK_RI_TO_53); 1271 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1272 MSK_RI_TO_53); 1273 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1274 MSK_RI_TO_53); 1275 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1276 MSK_RI_TO_53); 1277 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1278 MSK_RI_TO_53); 1279 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1280 MSK_RI_TO_53); 1281 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1282 MSK_RI_TO_53); 1283 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1284 MSK_RI_TO_53); 1285 } 1286 1287 /* Disable all interrupts. */ 1288 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1289 CSR_READ_4(sc, B0_HWE_IMSK); 1290 CSR_WRITE_4(sc, B0_IMSK, 0); 1291 CSR_READ_4(sc, B0_IMSK); 1292 1293 /* 1294 * On dual port PCI-X card, there is an problem where status 1295 * can be received out of order due to split transactions. 1296 */ 1297 if (sc->msk_bustype == MSK_PCIX_BUS && sc->msk_num_port > 1) { 1298 int pcix; 1299 uint16_t pcix_cmd; 1300 1301 if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, &pcix) == 0) { 1302 pcix_cmd = pci_read_config(sc->msk_dev, pcix + 2, 2); 1303 /* Clear Max Outstanding Split Transactions. */ 1304 pcix_cmd &= ~0x70; 1305 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1306 pci_write_config(sc->msk_dev, pcix + 2, pcix_cmd, 2); 1307 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1308 } 1309 } 1310 if (sc->msk_bustype == MSK_PEX_BUS) { 1311 uint16_t v, width; 1312 1313 v = pci_read_config(sc->msk_dev, PEX_DEV_CTRL, 2); 1314 /* Change Max. Read Request Size to 4096 bytes. */ 1315 v &= ~PEX_DC_MAX_RRS_MSK; 1316 v |= PEX_DC_MAX_RD_RQ_SIZE(5); 1317 pci_write_config(sc->msk_dev, PEX_DEV_CTRL, v, 2); 1318 width = pci_read_config(sc->msk_dev, PEX_LNK_STAT, 2); 1319 width = (width & PEX_LS_LINK_WI_MSK) >> 4; 1320 v = pci_read_config(sc->msk_dev, PEX_LNK_CAP, 2); 1321 v = (v & PEX_LS_LINK_WI_MSK) >> 4; 1322 if (v != width) 1323 device_printf(sc->msk_dev, 1324 "negotiated width of link(x%d) != " 1325 "max. width of link(x%d)\n", width, v); 1326 } 1327 1328 /* Clear status list. */ 1329 bzero(sc->msk_stat_ring, 1330 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT); 1331 sc->msk_stat_cons = 0; 1332 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1333 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1334 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1335 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1336 /* Set the status list base address. */ 1337 addr = sc->msk_stat_ring_paddr; 1338 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1339 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1340 /* Set the status list last index. */ 1341 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1); 1342 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1343 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1344 /* WA for dev. #4.3 */ 1345 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1346 /* WA for dev. #4.18 */ 1347 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1348 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1349 } else { 1350 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1351 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1352 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1353 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1354 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1355 else 1356 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1357 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1358 } 1359 /* 1360 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1361 */ 1362 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1363 1364 /* Enable status unit. */ 1365 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1366 1367 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1368 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1369 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1370 } 1371 1372 static int 1373 msk_probe(device_t dev) 1374 { 1375 struct msk_softc *sc; 1376 char desc[100]; 1377 1378 sc = device_get_softc(device_get_parent(dev)); 1379 /* 1380 * Not much to do here. We always know there will be 1381 * at least one GMAC present, and if there are two, 1382 * mskc_attach() will create a second device instance 1383 * for us. 1384 */ 1385 snprintf(desc, sizeof(desc), 1386 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1387 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1388 sc->msk_hw_rev); 1389 device_set_desc_copy(dev, desc); 1390 1391 return (BUS_PROBE_DEFAULT); 1392 } 1393 1394 static int 1395 msk_attach(device_t dev) 1396 { 1397 struct msk_softc *sc; 1398 struct msk_if_softc *sc_if; 1399 struct ifnet *ifp; 1400 int i, port, error; 1401 uint8_t eaddr[6]; 1402 1403 if (dev == NULL) 1404 return (EINVAL); 1405 1406 error = 0; 1407 sc_if = device_get_softc(dev); 1408 sc = device_get_softc(device_get_parent(dev)); 1409 port = *(int *)device_get_ivars(dev); 1410 1411 sc_if->msk_if_dev = dev; 1412 sc_if->msk_port = port; 1413 sc_if->msk_softc = sc; 1414 sc->msk_if[port] = sc_if; 1415 /* Setup Tx/Rx queue register offsets. */ 1416 if (port == MSK_PORT_A) { 1417 sc_if->msk_txq = Q_XA1; 1418 sc_if->msk_txsq = Q_XS1; 1419 sc_if->msk_rxq = Q_R1; 1420 } else { 1421 sc_if->msk_txq = Q_XA2; 1422 sc_if->msk_txsq = Q_XS2; 1423 sc_if->msk_rxq = Q_R2; 1424 } 1425 1426 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1427 TASK_INIT(&sc_if->msk_link_task, 0, msk_link_task, sc_if); 1428 1429 if ((error = msk_txrx_dma_alloc(sc_if) != 0)) 1430 goto fail; 1431 1432 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1433 if (ifp == NULL) { 1434 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1435 error = ENOSPC; 1436 goto fail; 1437 } 1438 ifp->if_softc = sc_if; 1439 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1440 ifp->if_mtu = ETHERMTU; 1441 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1442 /* 1443 * IFCAP_RXCSUM capability is intentionally disabled as the hardware 1444 * has serious bug in Rx checksum offload for all Yukon II family 1445 * hardware. It seems there is a workaround to make it work somtimes. 1446 * However, the workaround also have to check OP code sequences to 1447 * verify whether the OP code is correct. Sometimes it should compute 1448 * IP/TCP/UDP checksum in driver in order to verify correctness of 1449 * checksum computed by hardware. If you have to compute checksum 1450 * with software to verify the hardware's checksum why have hardware 1451 * compute the checksum? I think there is no reason to spend time to 1452 * make Rx checksum offload work on Yukon II hardware. 1453 */ 1454 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1455 ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO; 1456 ifp->if_capenable = ifp->if_capabilities; 1457 ifp->if_ioctl = msk_ioctl; 1458 ifp->if_start = msk_start; 1459 ifp->if_timer = 0; 1460 ifp->if_watchdog = NULL; 1461 ifp->if_init = msk_init; 1462 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1463 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1; 1464 IFQ_SET_READY(&ifp->if_snd); 1465 1466 TASK_INIT(&sc_if->msk_tx_task, 1, msk_tx_task, ifp); 1467 1468 /* 1469 * Get station address for this interface. Note that 1470 * dual port cards actually come with three station 1471 * addresses: one for each port, plus an extra. The 1472 * extra one is used by the SysKonnect driver software 1473 * as a 'virtual' station address for when both ports 1474 * are operating in failover mode. Currently we don't 1475 * use this extra address. 1476 */ 1477 MSK_IF_LOCK(sc_if); 1478 for (i = 0; i < ETHER_ADDR_LEN; i++) 1479 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1480 1481 /* 1482 * Call MI attach routine. Can't hold locks when calling into ether_*. 1483 */ 1484 MSK_IF_UNLOCK(sc_if); 1485 ether_ifattach(ifp, eaddr); 1486 MSK_IF_LOCK(sc_if); 1487 1488 /* VLAN capability setup */ 1489 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1490 if (ifp->if_capabilities & IFCAP_HWCSUM) 1491 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1492 ifp->if_capenable = ifp->if_capabilities; 1493 1494 /* 1495 * Tell the upper layer(s) we support long frames. 1496 * Must appear after the call to ether_ifattach() because 1497 * ether_ifattach() sets ifi_hdrlen to the default value. 1498 */ 1499 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1500 1501 sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN + 1502 ETHER_VLAN_ENCAP_LEN; 1503 1504 /* 1505 * Do miibus setup. 1506 */ 1507 MSK_IF_UNLOCK(sc_if); 1508 error = mii_phy_probe(dev, &sc_if->msk_miibus, msk_mediachange, 1509 msk_mediastatus); 1510 if (error != 0) { 1511 device_printf(sc_if->msk_if_dev, "no PHY found!\n"); 1512 ether_ifdetach(ifp); 1513 error = ENXIO; 1514 goto fail; 1515 } 1516 1517 fail: 1518 if (error != 0) { 1519 /* Access should be ok even though lock has been dropped */ 1520 sc->msk_if[port] = NULL; 1521 msk_detach(dev); 1522 } 1523 1524 return (error); 1525 } 1526 1527 /* 1528 * Attach the interface. Allocate softc structures, do ifmedia 1529 * setup and ethernet/BPF attach. 1530 */ 1531 static int 1532 mskc_attach(device_t dev) 1533 { 1534 struct msk_softc *sc; 1535 int error, msic, msir, *port, reg; 1536 1537 sc = device_get_softc(dev); 1538 sc->msk_dev = dev; 1539 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1540 MTX_DEF); 1541 1542 /* 1543 * Map control/status registers. 1544 */ 1545 pci_enable_busmaster(dev); 1546 1547 /* Allocate I/O resource */ 1548 #ifdef MSK_USEIOSPACE 1549 sc->msk_res_spec = msk_res_spec_io; 1550 #else 1551 sc->msk_res_spec = msk_res_spec_mem; 1552 #endif 1553 sc->msk_irq_spec = msk_irq_spec_legacy; 1554 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1555 if (error) { 1556 if (sc->msk_res_spec == msk_res_spec_mem) 1557 sc->msk_res_spec = msk_res_spec_io; 1558 else 1559 sc->msk_res_spec = msk_res_spec_mem; 1560 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1561 if (error) { 1562 device_printf(dev, "couldn't allocate %s resources\n", 1563 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1564 "I/O"); 1565 mtx_destroy(&sc->msk_mtx); 1566 return (ENXIO); 1567 } 1568 } 1569 1570 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1571 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1572 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1573 /* Bail out if chip is not recognized. */ 1574 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1575 sc->msk_hw_id > CHIP_ID_YUKON_FE) { 1576 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1577 sc->msk_hw_id, sc->msk_hw_rev); 1578 mtx_destroy(&sc->msk_mtx); 1579 return (ENXIO); 1580 } 1581 1582 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1583 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1584 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 1585 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1586 "max number of Rx events to process"); 1587 1588 sc->msk_process_limit = MSK_PROC_DEFAULT; 1589 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1590 "process_limit", &sc->msk_process_limit); 1591 if (error == 0) { 1592 if (sc->msk_process_limit < MSK_PROC_MIN || 1593 sc->msk_process_limit > MSK_PROC_MAX) { 1594 device_printf(dev, "process_limit value out of range; " 1595 "using default: %d\n", MSK_PROC_DEFAULT); 1596 sc->msk_process_limit = MSK_PROC_DEFAULT; 1597 } 1598 } 1599 1600 /* Soft reset. */ 1601 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1602 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1603 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1604 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1605 sc->msk_coppertype = 0; 1606 else 1607 sc->msk_coppertype = 1; 1608 /* Check number of MACs. */ 1609 sc->msk_num_port = 1; 1610 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1611 CFG_DUAL_MAC_MSK) { 1612 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1613 sc->msk_num_port++; 1614 } 1615 1616 /* Check bus type. */ 1617 if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) 1618 sc->msk_bustype = MSK_PEX_BUS; 1619 else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0) 1620 sc->msk_bustype = MSK_PCIX_BUS; 1621 else 1622 sc->msk_bustype = MSK_PCI_BUS; 1623 1624 switch (sc->msk_hw_id) { 1625 case CHIP_ID_YUKON_EC: 1626 case CHIP_ID_YUKON_EC_U: 1627 sc->msk_clock = 125; /* 125 Mhz */ 1628 break; 1629 case CHIP_ID_YUKON_FE: 1630 sc->msk_clock = 100; /* 100 Mhz */ 1631 break; 1632 case CHIP_ID_YUKON_XL: 1633 sc->msk_clock = 156; /* 156 Mhz */ 1634 break; 1635 default: 1636 sc->msk_clock = 156; /* 156 Mhz */ 1637 break; 1638 } 1639 1640 /* Allocate IRQ resources. */ 1641 msic = pci_msi_count(dev); 1642 if (bootverbose) 1643 device_printf(dev, "MSI count : %d\n", msic); 1644 /* 1645 * The Yukon II reports it can handle two messages, one for each 1646 * possible port. We go ahead and allocate two messages and only 1647 * setup a handler for both if we have a dual port card. 1648 * 1649 * XXX: I haven't untangled the interrupt handler to handle dual 1650 * port cards with separate MSI messages, so for now I disable MSI 1651 * on dual port cards. 1652 */ 1653 if (legacy_intr != 0) 1654 msi_disable = 1; 1655 if (msi_disable == 0) { 1656 switch (msic) { 1657 case 2: 1658 case 1: /* 88E8058 reports 1 MSI message */ 1659 msir = msic; 1660 if (sc->msk_num_port == 1 && 1661 pci_alloc_msi(dev, &msir) == 0) { 1662 if (msic == msir) { 1663 sc->msk_msi = 1; 1664 sc->msk_irq_spec = msic == 2 ? 1665 msk_irq_spec_msi2 : 1666 msk_irq_spec_msi; 1667 } else 1668 pci_release_msi(dev); 1669 } 1670 break; 1671 default: 1672 device_printf(dev, 1673 "Unexpected number of MSI messages : %d\n", msic); 1674 break; 1675 } 1676 } 1677 1678 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1679 if (error) { 1680 device_printf(dev, "couldn't allocate IRQ resources\n"); 1681 goto fail; 1682 } 1683 1684 if ((error = msk_status_dma_alloc(sc)) != 0) 1685 goto fail; 1686 1687 /* Set base interrupt mask. */ 1688 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1689 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1690 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1691 1692 /* Reset the adapter. */ 1693 mskc_reset(sc); 1694 1695 if ((error = mskc_setup_rambuffer(sc)) != 0) 1696 goto fail; 1697 1698 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1699 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1700 device_printf(dev, "failed to add child for PORT_A\n"); 1701 error = ENXIO; 1702 goto fail; 1703 } 1704 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1705 if (port == NULL) { 1706 device_printf(dev, "failed to allocate memory for " 1707 "ivars of PORT_A\n"); 1708 error = ENXIO; 1709 goto fail; 1710 } 1711 *port = MSK_PORT_A; 1712 device_set_ivars(sc->msk_devs[MSK_PORT_A], port); 1713 1714 if (sc->msk_num_port > 1) { 1715 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1716 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1717 device_printf(dev, "failed to add child for PORT_B\n"); 1718 error = ENXIO; 1719 goto fail; 1720 } 1721 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1722 if (port == NULL) { 1723 device_printf(dev, "failed to allocate memory for " 1724 "ivars of PORT_B\n"); 1725 error = ENXIO; 1726 goto fail; 1727 } 1728 *port = MSK_PORT_B; 1729 device_set_ivars(sc->msk_devs[MSK_PORT_B], port); 1730 } 1731 1732 error = bus_generic_attach(dev); 1733 if (error) { 1734 device_printf(dev, "failed to attach port(s)\n"); 1735 goto fail; 1736 } 1737 1738 /* Hook interrupt last to avoid having to lock softc. */ 1739 if (legacy_intr) 1740 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1741 INTR_MPSAFE, NULL, msk_legacy_intr, sc, 1742 &sc->msk_intrhand[0]); 1743 else { 1744 TASK_INIT(&sc->msk_int_task, 0, msk_int_task, sc); 1745 sc->msk_tq = taskqueue_create_fast("msk_taskq", M_WAITOK, 1746 taskqueue_thread_enqueue, &sc->msk_tq); 1747 taskqueue_start_threads(&sc->msk_tq, 1, PI_NET, "%s taskq", 1748 device_get_nameunit(sc->msk_dev)); 1749 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1750 INTR_MPSAFE, msk_intr, NULL, sc, &sc->msk_intrhand[0]); 1751 } 1752 1753 if (error != 0) { 1754 device_printf(dev, "couldn't set up interrupt handler\n"); 1755 if (legacy_intr == 0) 1756 taskqueue_free(sc->msk_tq); 1757 sc->msk_tq = NULL; 1758 goto fail; 1759 } 1760 fail: 1761 if (error != 0) 1762 mskc_detach(dev); 1763 1764 return (error); 1765 } 1766 1767 /* 1768 * Shutdown hardware and free up resources. This can be called any 1769 * time after the mutex has been initialized. It is called in both 1770 * the error case in attach and the normal detach case so it needs 1771 * to be careful about only freeing resources that have actually been 1772 * allocated. 1773 */ 1774 static int 1775 msk_detach(device_t dev) 1776 { 1777 struct msk_softc *sc; 1778 struct msk_if_softc *sc_if; 1779 struct ifnet *ifp; 1780 1781 sc_if = device_get_softc(dev); 1782 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 1783 ("msk mutex not initialized in msk_detach")); 1784 MSK_IF_LOCK(sc_if); 1785 1786 ifp = sc_if->msk_ifp; 1787 if (device_is_attached(dev)) { 1788 /* XXX */ 1789 sc_if->msk_detach = 1; 1790 msk_stop(sc_if); 1791 /* Can't hold locks while calling detach. */ 1792 MSK_IF_UNLOCK(sc_if); 1793 callout_drain(&sc_if->msk_tick_ch); 1794 taskqueue_drain(taskqueue_fast, &sc_if->msk_tx_task); 1795 taskqueue_drain(taskqueue_swi, &sc_if->msk_link_task); 1796 ether_ifdetach(ifp); 1797 MSK_IF_LOCK(sc_if); 1798 } 1799 1800 /* 1801 * We're generally called from mskc_detach() which is using 1802 * device_delete_child() to get to here. It's already trashed 1803 * miibus for us, so don't do it here or we'll panic. 1804 * 1805 * if (sc_if->msk_miibus != NULL) { 1806 * device_delete_child(dev, sc_if->msk_miibus); 1807 * sc_if->msk_miibus = NULL; 1808 * } 1809 */ 1810 1811 msk_txrx_dma_free(sc_if); 1812 bus_generic_detach(dev); 1813 1814 if (ifp) 1815 if_free(ifp); 1816 sc = sc_if->msk_softc; 1817 sc->msk_if[sc_if->msk_port] = NULL; 1818 MSK_IF_UNLOCK(sc_if); 1819 1820 return (0); 1821 } 1822 1823 static int 1824 mskc_detach(device_t dev) 1825 { 1826 struct msk_softc *sc; 1827 1828 sc = device_get_softc(dev); 1829 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 1830 1831 if (device_is_alive(dev)) { 1832 if (sc->msk_devs[MSK_PORT_A] != NULL) { 1833 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 1834 M_DEVBUF); 1835 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 1836 } 1837 if (sc->msk_devs[MSK_PORT_B] != NULL) { 1838 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 1839 M_DEVBUF); 1840 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 1841 } 1842 bus_generic_detach(dev); 1843 } 1844 1845 /* Disable all interrupts. */ 1846 CSR_WRITE_4(sc, B0_IMSK, 0); 1847 CSR_READ_4(sc, B0_IMSK); 1848 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1849 CSR_READ_4(sc, B0_HWE_IMSK); 1850 1851 /* LED Off. */ 1852 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 1853 1854 /* Put hardware reset. */ 1855 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1856 1857 msk_status_dma_free(sc); 1858 1859 if (legacy_intr == 0 && sc->msk_tq != NULL) { 1860 taskqueue_drain(sc->msk_tq, &sc->msk_int_task); 1861 taskqueue_free(sc->msk_tq); 1862 sc->msk_tq = NULL; 1863 } 1864 if (sc->msk_intrhand[0]) { 1865 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]); 1866 sc->msk_intrhand[0] = NULL; 1867 } 1868 if (sc->msk_intrhand[1]) { 1869 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]); 1870 sc->msk_intrhand[1] = NULL; 1871 } 1872 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1873 if (sc->msk_msi) 1874 pci_release_msi(dev); 1875 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 1876 mtx_destroy(&sc->msk_mtx); 1877 1878 return (0); 1879 } 1880 1881 struct msk_dmamap_arg { 1882 bus_addr_t msk_busaddr; 1883 }; 1884 1885 static void 1886 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1887 { 1888 struct msk_dmamap_arg *ctx; 1889 1890 if (error != 0) 1891 return; 1892 ctx = arg; 1893 ctx->msk_busaddr = segs[0].ds_addr; 1894 } 1895 1896 /* Create status DMA region. */ 1897 static int 1898 msk_status_dma_alloc(struct msk_softc *sc) 1899 { 1900 struct msk_dmamap_arg ctx; 1901 int error; 1902 1903 error = bus_dma_tag_create( 1904 bus_get_dma_tag(sc->msk_dev), /* parent */ 1905 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 1906 BUS_SPACE_MAXADDR, /* lowaddr */ 1907 BUS_SPACE_MAXADDR, /* highaddr */ 1908 NULL, NULL, /* filter, filterarg */ 1909 MSK_STAT_RING_SZ, /* maxsize */ 1910 1, /* nsegments */ 1911 MSK_STAT_RING_SZ, /* maxsegsize */ 1912 0, /* flags */ 1913 NULL, NULL, /* lockfunc, lockarg */ 1914 &sc->msk_stat_tag); 1915 if (error != 0) { 1916 device_printf(sc->msk_dev, 1917 "failed to create status DMA tag\n"); 1918 return (error); 1919 } 1920 1921 /* Allocate DMA'able memory and load the DMA map for status ring. */ 1922 error = bus_dmamem_alloc(sc->msk_stat_tag, 1923 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 1924 BUS_DMA_ZERO, &sc->msk_stat_map); 1925 if (error != 0) { 1926 device_printf(sc->msk_dev, 1927 "failed to allocate DMA'able memory for status ring\n"); 1928 return (error); 1929 } 1930 1931 ctx.msk_busaddr = 0; 1932 error = bus_dmamap_load(sc->msk_stat_tag, 1933 sc->msk_stat_map, sc->msk_stat_ring, MSK_STAT_RING_SZ, 1934 msk_dmamap_cb, &ctx, 0); 1935 if (error != 0) { 1936 device_printf(sc->msk_dev, 1937 "failed to load DMA'able memory for status ring\n"); 1938 return (error); 1939 } 1940 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 1941 1942 return (0); 1943 } 1944 1945 static void 1946 msk_status_dma_free(struct msk_softc *sc) 1947 { 1948 1949 /* Destroy status block. */ 1950 if (sc->msk_stat_tag) { 1951 if (sc->msk_stat_map) { 1952 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 1953 if (sc->msk_stat_ring) { 1954 bus_dmamem_free(sc->msk_stat_tag, 1955 sc->msk_stat_ring, sc->msk_stat_map); 1956 sc->msk_stat_ring = NULL; 1957 } 1958 sc->msk_stat_map = NULL; 1959 } 1960 bus_dma_tag_destroy(sc->msk_stat_tag); 1961 sc->msk_stat_tag = NULL; 1962 } 1963 } 1964 1965 static int 1966 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 1967 { 1968 struct msk_dmamap_arg ctx; 1969 struct msk_txdesc *txd; 1970 struct msk_rxdesc *rxd; 1971 struct msk_rxdesc *jrxd; 1972 struct msk_jpool_entry *entry; 1973 uint8_t *ptr; 1974 int error, i; 1975 1976 mtx_init(&sc_if->msk_jlist_mtx, "msk_jlist_mtx", NULL, MTX_DEF); 1977 SLIST_INIT(&sc_if->msk_jfree_listhead); 1978 SLIST_INIT(&sc_if->msk_jinuse_listhead); 1979 1980 /* Create parent DMA tag. */ 1981 /* 1982 * XXX 1983 * It seems that Yukon II supports full 64bits DMA operations. But 1984 * it needs two descriptors(list elements) for 64bits DMA operations. 1985 * Since we don't know what DMA address mappings(32bits or 64bits) 1986 * would be used in advance for each mbufs, we limits its DMA space 1987 * to be in range of 32bits address space. Otherwise, we should check 1988 * what DMA address is used and chain another descriptor for the 1989 * 64bits DMA operation. This also means descriptor ring size is 1990 * variable. Limiting DMA address to be in 32bit address space greatly 1991 * simplyfies descriptor handling and possibly would increase 1992 * performance a bit due to efficient handling of descriptors. 1993 * Apart from harassing checksum offloading mechanisms, it seems 1994 * it's really bad idea to use a seperate descriptor for 64bit 1995 * DMA operation to save small descriptor memory. Anyway, I've 1996 * never seen these exotic scheme on ethernet interface hardware. 1997 */ 1998 error = bus_dma_tag_create( 1999 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2000 1, 0, /* alignment, boundary */ 2001 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2002 BUS_SPACE_MAXADDR, /* highaddr */ 2003 NULL, NULL, /* filter, filterarg */ 2004 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2005 0, /* nsegments */ 2006 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2007 0, /* flags */ 2008 NULL, NULL, /* lockfunc, lockarg */ 2009 &sc_if->msk_cdata.msk_parent_tag); 2010 if (error != 0) { 2011 device_printf(sc_if->msk_if_dev, 2012 "failed to create parent DMA tag\n"); 2013 goto fail; 2014 } 2015 /* Create tag for Tx ring. */ 2016 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2017 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2018 BUS_SPACE_MAXADDR, /* lowaddr */ 2019 BUS_SPACE_MAXADDR, /* highaddr */ 2020 NULL, NULL, /* filter, filterarg */ 2021 MSK_TX_RING_SZ, /* maxsize */ 2022 1, /* nsegments */ 2023 MSK_TX_RING_SZ, /* maxsegsize */ 2024 0, /* flags */ 2025 NULL, NULL, /* lockfunc, lockarg */ 2026 &sc_if->msk_cdata.msk_tx_ring_tag); 2027 if (error != 0) { 2028 device_printf(sc_if->msk_if_dev, 2029 "failed to create Tx ring DMA tag\n"); 2030 goto fail; 2031 } 2032 2033 /* Create tag for Rx ring. */ 2034 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2035 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2036 BUS_SPACE_MAXADDR, /* lowaddr */ 2037 BUS_SPACE_MAXADDR, /* highaddr */ 2038 NULL, NULL, /* filter, filterarg */ 2039 MSK_RX_RING_SZ, /* maxsize */ 2040 1, /* nsegments */ 2041 MSK_RX_RING_SZ, /* maxsegsize */ 2042 0, /* flags */ 2043 NULL, NULL, /* lockfunc, lockarg */ 2044 &sc_if->msk_cdata.msk_rx_ring_tag); 2045 if (error != 0) { 2046 device_printf(sc_if->msk_if_dev, 2047 "failed to create Rx ring DMA tag\n"); 2048 goto fail; 2049 } 2050 2051 /* Create tag for jumbo Rx ring. */ 2052 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2053 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2054 BUS_SPACE_MAXADDR, /* lowaddr */ 2055 BUS_SPACE_MAXADDR, /* highaddr */ 2056 NULL, NULL, /* filter, filterarg */ 2057 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2058 1, /* nsegments */ 2059 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2060 0, /* flags */ 2061 NULL, NULL, /* lockfunc, lockarg */ 2062 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2063 if (error != 0) { 2064 device_printf(sc_if->msk_if_dev, 2065 "failed to create jumbo Rx ring DMA tag\n"); 2066 goto fail; 2067 } 2068 2069 /* Create tag for jumbo buffer blocks. */ 2070 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2071 PAGE_SIZE, 0, /* alignment, boundary */ 2072 BUS_SPACE_MAXADDR, /* lowaddr */ 2073 BUS_SPACE_MAXADDR, /* highaddr */ 2074 NULL, NULL, /* filter, filterarg */ 2075 MSK_JMEM, /* maxsize */ 2076 1, /* nsegments */ 2077 MSK_JMEM, /* maxsegsize */ 2078 0, /* flags */ 2079 NULL, NULL, /* lockfunc, lockarg */ 2080 &sc_if->msk_cdata.msk_jumbo_tag); 2081 if (error != 0) { 2082 device_printf(sc_if->msk_if_dev, 2083 "failed to create jumbo Rx buffer block DMA tag\n"); 2084 goto fail; 2085 } 2086 2087 /* Create tag for Tx buffers. */ 2088 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2089 1, 0, /* alignment, boundary */ 2090 BUS_SPACE_MAXADDR, /* lowaddr */ 2091 BUS_SPACE_MAXADDR, /* highaddr */ 2092 NULL, NULL, /* filter, filterarg */ 2093 MSK_TSO_MAXSIZE, /* maxsize */ 2094 MSK_MAXTXSEGS, /* nsegments */ 2095 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2096 0, /* flags */ 2097 NULL, NULL, /* lockfunc, lockarg */ 2098 &sc_if->msk_cdata.msk_tx_tag); 2099 if (error != 0) { 2100 device_printf(sc_if->msk_if_dev, 2101 "failed to create Tx DMA tag\n"); 2102 goto fail; 2103 } 2104 2105 /* Create tag for Rx buffers. */ 2106 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2107 1, 0, /* alignment, boundary */ 2108 BUS_SPACE_MAXADDR, /* lowaddr */ 2109 BUS_SPACE_MAXADDR, /* highaddr */ 2110 NULL, NULL, /* filter, filterarg */ 2111 MCLBYTES, /* maxsize */ 2112 1, /* nsegments */ 2113 MCLBYTES, /* maxsegsize */ 2114 0, /* flags */ 2115 NULL, NULL, /* lockfunc, lockarg */ 2116 &sc_if->msk_cdata.msk_rx_tag); 2117 if (error != 0) { 2118 device_printf(sc_if->msk_if_dev, 2119 "failed to create Rx DMA tag\n"); 2120 goto fail; 2121 } 2122 2123 /* Create tag for jumbo Rx buffers. */ 2124 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2125 PAGE_SIZE, 0, /* alignment, boundary */ 2126 BUS_SPACE_MAXADDR, /* lowaddr */ 2127 BUS_SPACE_MAXADDR, /* highaddr */ 2128 NULL, NULL, /* filter, filterarg */ 2129 MCLBYTES * MSK_MAXRXSEGS, /* maxsize */ 2130 MSK_MAXRXSEGS, /* nsegments */ 2131 MSK_JLEN, /* maxsegsize */ 2132 0, /* flags */ 2133 NULL, NULL, /* lockfunc, lockarg */ 2134 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2135 if (error != 0) { 2136 device_printf(sc_if->msk_if_dev, 2137 "failed to create jumbo Rx DMA tag\n"); 2138 goto fail; 2139 } 2140 2141 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2142 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2143 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2144 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2145 if (error != 0) { 2146 device_printf(sc_if->msk_if_dev, 2147 "failed to allocate DMA'able memory for Tx ring\n"); 2148 goto fail; 2149 } 2150 2151 ctx.msk_busaddr = 0; 2152 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2153 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2154 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2155 if (error != 0) { 2156 device_printf(sc_if->msk_if_dev, 2157 "failed to load DMA'able memory for Tx ring\n"); 2158 goto fail; 2159 } 2160 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2161 2162 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2163 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2164 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2165 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2166 if (error != 0) { 2167 device_printf(sc_if->msk_if_dev, 2168 "failed to allocate DMA'able memory for Rx ring\n"); 2169 goto fail; 2170 } 2171 2172 ctx.msk_busaddr = 0; 2173 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2174 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2175 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2176 if (error != 0) { 2177 device_printf(sc_if->msk_if_dev, 2178 "failed to load DMA'able memory for Rx ring\n"); 2179 goto fail; 2180 } 2181 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2182 2183 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2184 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2185 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2186 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2187 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2188 if (error != 0) { 2189 device_printf(sc_if->msk_if_dev, 2190 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2191 goto fail; 2192 } 2193 2194 ctx.msk_busaddr = 0; 2195 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2196 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2197 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2198 msk_dmamap_cb, &ctx, 0); 2199 if (error != 0) { 2200 device_printf(sc_if->msk_if_dev, 2201 "failed to load DMA'able memory for jumbo Rx ring\n"); 2202 goto fail; 2203 } 2204 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2205 2206 /* Create DMA maps for Tx buffers. */ 2207 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2208 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2209 txd->tx_m = NULL; 2210 txd->tx_dmamap = NULL; 2211 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2212 &txd->tx_dmamap); 2213 if (error != 0) { 2214 device_printf(sc_if->msk_if_dev, 2215 "failed to create Tx dmamap\n"); 2216 goto fail; 2217 } 2218 } 2219 /* Create DMA maps for Rx buffers. */ 2220 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2221 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2222 device_printf(sc_if->msk_if_dev, 2223 "failed to create spare Rx dmamap\n"); 2224 goto fail; 2225 } 2226 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2227 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2228 rxd->rx_m = NULL; 2229 rxd->rx_dmamap = NULL; 2230 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2231 &rxd->rx_dmamap); 2232 if (error != 0) { 2233 device_printf(sc_if->msk_if_dev, 2234 "failed to create Rx dmamap\n"); 2235 goto fail; 2236 } 2237 } 2238 /* Create DMA maps for jumbo Rx buffers. */ 2239 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2240 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2241 device_printf(sc_if->msk_if_dev, 2242 "failed to create spare jumbo Rx dmamap\n"); 2243 goto fail; 2244 } 2245 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2246 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2247 jrxd->rx_m = NULL; 2248 jrxd->rx_dmamap = NULL; 2249 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2250 &jrxd->rx_dmamap); 2251 if (error != 0) { 2252 device_printf(sc_if->msk_if_dev, 2253 "failed to create jumbo Rx dmamap\n"); 2254 goto fail; 2255 } 2256 } 2257 2258 /* Allocate DMA'able memory and load the DMA map for jumbo buf. */ 2259 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_tag, 2260 (void **)&sc_if->msk_rdata.msk_jumbo_buf, 2261 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2262 &sc_if->msk_cdata.msk_jumbo_map); 2263 if (error != 0) { 2264 device_printf(sc_if->msk_if_dev, 2265 "failed to allocate DMA'able memory for jumbo buf\n"); 2266 goto fail; 2267 } 2268 2269 ctx.msk_busaddr = 0; 2270 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_tag, 2271 sc_if->msk_cdata.msk_jumbo_map, sc_if->msk_rdata.msk_jumbo_buf, 2272 MSK_JMEM, msk_dmamap_cb, &ctx, 0); 2273 if (error != 0) { 2274 device_printf(sc_if->msk_if_dev, 2275 "failed to load DMA'able memory for jumbobuf\n"); 2276 goto fail; 2277 } 2278 sc_if->msk_rdata.msk_jumbo_buf_paddr = ctx.msk_busaddr; 2279 2280 /* 2281 * Now divide it up into 9K pieces and save the addresses 2282 * in an array. 2283 */ 2284 ptr = sc_if->msk_rdata.msk_jumbo_buf; 2285 for (i = 0; i < MSK_JSLOTS; i++) { 2286 sc_if->msk_cdata.msk_jslots[i] = ptr; 2287 ptr += MSK_JLEN; 2288 entry = malloc(sizeof(struct msk_jpool_entry), 2289 M_DEVBUF, M_WAITOK); 2290 if (entry == NULL) { 2291 device_printf(sc_if->msk_if_dev, 2292 "no memory for jumbo buffers!\n"); 2293 error = ENOMEM; 2294 goto fail; 2295 } 2296 entry->slot = i; 2297 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, 2298 jpool_entries); 2299 } 2300 2301 fail: 2302 return (error); 2303 } 2304 2305 static void 2306 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2307 { 2308 struct msk_txdesc *txd; 2309 struct msk_rxdesc *rxd; 2310 struct msk_rxdesc *jrxd; 2311 struct msk_jpool_entry *entry; 2312 int i; 2313 2314 MSK_JLIST_LOCK(sc_if); 2315 while ((entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead))) { 2316 device_printf(sc_if->msk_if_dev, 2317 "asked to free buffer that is in use!\n"); 2318 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries); 2319 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, 2320 jpool_entries); 2321 } 2322 2323 while (!SLIST_EMPTY(&sc_if->msk_jfree_listhead)) { 2324 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead); 2325 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries); 2326 free(entry, M_DEVBUF); 2327 } 2328 MSK_JLIST_UNLOCK(sc_if); 2329 2330 /* Destroy jumbo buffer block. */ 2331 if (sc_if->msk_cdata.msk_jumbo_map) 2332 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_tag, 2333 sc_if->msk_cdata.msk_jumbo_map); 2334 2335 if (sc_if->msk_rdata.msk_jumbo_buf) { 2336 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_tag, 2337 sc_if->msk_rdata.msk_jumbo_buf, 2338 sc_if->msk_cdata.msk_jumbo_map); 2339 sc_if->msk_rdata.msk_jumbo_buf = NULL; 2340 sc_if->msk_cdata.msk_jumbo_map = NULL; 2341 } 2342 2343 /* Tx ring. */ 2344 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2345 if (sc_if->msk_cdata.msk_tx_ring_map) 2346 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2347 sc_if->msk_cdata.msk_tx_ring_map); 2348 if (sc_if->msk_cdata.msk_tx_ring_map && 2349 sc_if->msk_rdata.msk_tx_ring) 2350 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2351 sc_if->msk_rdata.msk_tx_ring, 2352 sc_if->msk_cdata.msk_tx_ring_map); 2353 sc_if->msk_rdata.msk_tx_ring = NULL; 2354 sc_if->msk_cdata.msk_tx_ring_map = NULL; 2355 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2356 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2357 } 2358 /* Rx ring. */ 2359 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2360 if (sc_if->msk_cdata.msk_rx_ring_map) 2361 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2362 sc_if->msk_cdata.msk_rx_ring_map); 2363 if (sc_if->msk_cdata.msk_rx_ring_map && 2364 sc_if->msk_rdata.msk_rx_ring) 2365 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2366 sc_if->msk_rdata.msk_rx_ring, 2367 sc_if->msk_cdata.msk_rx_ring_map); 2368 sc_if->msk_rdata.msk_rx_ring = NULL; 2369 sc_if->msk_cdata.msk_rx_ring_map = NULL; 2370 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2371 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2372 } 2373 /* Jumbo Rx ring. */ 2374 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2375 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map) 2376 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2377 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2378 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map && 2379 sc_if->msk_rdata.msk_jumbo_rx_ring) 2380 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2381 sc_if->msk_rdata.msk_jumbo_rx_ring, 2382 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2383 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2384 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL; 2385 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2386 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2387 } 2388 /* Tx buffers. */ 2389 if (sc_if->msk_cdata.msk_tx_tag) { 2390 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2391 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2392 if (txd->tx_dmamap) { 2393 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2394 txd->tx_dmamap); 2395 txd->tx_dmamap = NULL; 2396 } 2397 } 2398 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2399 sc_if->msk_cdata.msk_tx_tag = NULL; 2400 } 2401 /* Rx buffers. */ 2402 if (sc_if->msk_cdata.msk_rx_tag) { 2403 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2404 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2405 if (rxd->rx_dmamap) { 2406 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2407 rxd->rx_dmamap); 2408 rxd->rx_dmamap = NULL; 2409 } 2410 } 2411 if (sc_if->msk_cdata.msk_rx_sparemap) { 2412 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2413 sc_if->msk_cdata.msk_rx_sparemap); 2414 sc_if->msk_cdata.msk_rx_sparemap = 0; 2415 } 2416 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2417 sc_if->msk_cdata.msk_rx_tag = NULL; 2418 } 2419 /* Jumbo Rx buffers. */ 2420 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2421 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2422 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2423 if (jrxd->rx_dmamap) { 2424 bus_dmamap_destroy( 2425 sc_if->msk_cdata.msk_jumbo_rx_tag, 2426 jrxd->rx_dmamap); 2427 jrxd->rx_dmamap = NULL; 2428 } 2429 } 2430 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2431 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2432 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2433 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2434 } 2435 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2436 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2437 } 2438 2439 if (sc_if->msk_cdata.msk_parent_tag) { 2440 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2441 sc_if->msk_cdata.msk_parent_tag = NULL; 2442 } 2443 mtx_destroy(&sc_if->msk_jlist_mtx); 2444 } 2445 2446 /* 2447 * Allocate a jumbo buffer. 2448 */ 2449 static void * 2450 msk_jalloc(struct msk_if_softc *sc_if) 2451 { 2452 struct msk_jpool_entry *entry; 2453 2454 MSK_JLIST_LOCK(sc_if); 2455 2456 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead); 2457 2458 if (entry == NULL) { 2459 MSK_JLIST_UNLOCK(sc_if); 2460 return (NULL); 2461 } 2462 2463 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries); 2464 SLIST_INSERT_HEAD(&sc_if->msk_jinuse_listhead, entry, jpool_entries); 2465 2466 MSK_JLIST_UNLOCK(sc_if); 2467 2468 return (sc_if->msk_cdata.msk_jslots[entry->slot]); 2469 } 2470 2471 /* 2472 * Release a jumbo buffer. 2473 */ 2474 static void 2475 msk_jfree(void *buf, void *args) 2476 { 2477 struct msk_if_softc *sc_if; 2478 struct msk_jpool_entry *entry; 2479 int i; 2480 2481 /* Extract the softc struct pointer. */ 2482 sc_if = (struct msk_if_softc *)args; 2483 KASSERT(sc_if != NULL, ("%s: can't find softc pointer!", __func__)); 2484 2485 MSK_JLIST_LOCK(sc_if); 2486 /* Calculate the slot this buffer belongs to. */ 2487 i = ((vm_offset_t)buf 2488 - (vm_offset_t)sc_if->msk_rdata.msk_jumbo_buf) / MSK_JLEN; 2489 KASSERT(i >= 0 && i < MSK_JSLOTS, 2490 ("%s: asked to free buffer that we don't manage!", __func__)); 2491 2492 entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead); 2493 KASSERT(entry != NULL, ("%s: buffer not in use!", __func__)); 2494 entry->slot = i; 2495 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries); 2496 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, jpool_entries); 2497 if (SLIST_EMPTY(&sc_if->msk_jinuse_listhead)) 2498 wakeup(sc_if); 2499 2500 MSK_JLIST_UNLOCK(sc_if); 2501 } 2502 2503 /* 2504 * It's copy of ath_defrag(ath(4)). 2505 * 2506 * Defragment an mbuf chain, returning at most maxfrags separate 2507 * mbufs+clusters. If this is not possible NULL is returned and 2508 * the original mbuf chain is left in it's present (potentially 2509 * modified) state. We use two techniques: collapsing consecutive 2510 * mbufs and replacing consecutive mbufs by a cluster. 2511 */ 2512 static struct mbuf * 2513 msk_defrag(struct mbuf *m0, int how, int maxfrags) 2514 { 2515 struct mbuf *m, *n, *n2, **prev; 2516 u_int curfrags; 2517 2518 /* 2519 * Calculate the current number of frags. 2520 */ 2521 curfrags = 0; 2522 for (m = m0; m != NULL; m = m->m_next) 2523 curfrags++; 2524 /* 2525 * First, try to collapse mbufs. Note that we always collapse 2526 * towards the front so we don't need to deal with moving the 2527 * pkthdr. This may be suboptimal if the first mbuf has much 2528 * less data than the following. 2529 */ 2530 m = m0; 2531 again: 2532 for (;;) { 2533 n = m->m_next; 2534 if (n == NULL) 2535 break; 2536 if ((m->m_flags & M_RDONLY) == 0 && 2537 n->m_len < M_TRAILINGSPACE(m)) { 2538 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len, 2539 n->m_len); 2540 m->m_len += n->m_len; 2541 m->m_next = n->m_next; 2542 m_free(n); 2543 if (--curfrags <= maxfrags) 2544 return (m0); 2545 } else 2546 m = n; 2547 } 2548 KASSERT(maxfrags > 1, 2549 ("maxfrags %u, but normal collapse failed", maxfrags)); 2550 /* 2551 * Collapse consecutive mbufs to a cluster. 2552 */ 2553 prev = &m0->m_next; /* NB: not the first mbuf */ 2554 while ((n = *prev) != NULL) { 2555 if ((n2 = n->m_next) != NULL && 2556 n->m_len + n2->m_len < MCLBYTES) { 2557 m = m_getcl(how, MT_DATA, 0); 2558 if (m == NULL) 2559 goto bad; 2560 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 2561 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 2562 n2->m_len); 2563 m->m_len = n->m_len + n2->m_len; 2564 m->m_next = n2->m_next; 2565 *prev = m; 2566 m_free(n); 2567 m_free(n2); 2568 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 2569 return m0; 2570 /* 2571 * Still not there, try the normal collapse 2572 * again before we allocate another cluster. 2573 */ 2574 goto again; 2575 } 2576 prev = &n->m_next; 2577 } 2578 /* 2579 * No place where we can collapse to a cluster; punt. 2580 * This can occur if, for example, you request 2 frags 2581 * but the packet requires that both be clusters (we 2582 * never reallocate the first mbuf to avoid moving the 2583 * packet header). 2584 */ 2585 bad: 2586 return (NULL); 2587 } 2588 2589 static int 2590 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2591 { 2592 struct msk_txdesc *txd, *txd_last; 2593 struct msk_tx_desc *tx_le; 2594 struct mbuf *m; 2595 bus_dmamap_t map; 2596 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2597 uint32_t control, prod, si; 2598 uint16_t offset, tcp_offset, tso_mtu; 2599 int error, i, nseg, tso; 2600 2601 MSK_IF_LOCK_ASSERT(sc_if); 2602 2603 tcp_offset = offset = 0; 2604 m = *m_head; 2605 if ((m->m_pkthdr.csum_flags & (MSK_CSUM_FEATURES | CSUM_TSO)) != 0) { 2606 /* 2607 * Since mbuf has no protocol specific structure information 2608 * in it we have to inspect protocol information here to 2609 * setup TSO and checksum offload. I don't know why Marvell 2610 * made a such decision in chip design because other GigE 2611 * hardwares normally takes care of all these chores in 2612 * hardware. However, TSO performance of Yukon II is very 2613 * good such that it's worth to implement it. 2614 */ 2615 struct ether_header *eh; 2616 struct ip *ip; 2617 struct tcphdr *tcp; 2618 2619 /* TODO check for M_WRITABLE(m) */ 2620 2621 offset = sizeof(struct ether_header); 2622 m = m_pullup(m, offset); 2623 if (m == NULL) { 2624 *m_head = NULL; 2625 return (ENOBUFS); 2626 } 2627 eh = mtod(m, struct ether_header *); 2628 /* Check if hardware VLAN insertion is off. */ 2629 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2630 offset = sizeof(struct ether_vlan_header); 2631 m = m_pullup(m, offset); 2632 if (m == NULL) { 2633 *m_head = NULL; 2634 return (ENOBUFS); 2635 } 2636 } 2637 m = m_pullup(m, offset + sizeof(struct ip)); 2638 if (m == NULL) { 2639 *m_head = NULL; 2640 return (ENOBUFS); 2641 } 2642 ip = (struct ip *)(mtod(m, char *) + offset); 2643 offset += (ip->ip_hl << 2); 2644 tcp_offset = offset; 2645 /* 2646 * It seems that Yukon II has Tx checksum offload bug for 2647 * small TCP packets that's less than 60 bytes in size 2648 * (e.g. TCP window probe packet, pure ACK packet). 2649 * Common work around like padding with zeros to make the 2650 * frame minimum ethernet frame size didn't work at all. 2651 * Instead of disabling checksum offload completely we 2652 * resort to S/W checksum routine when we encounter short 2653 * TCP frames. 2654 * Short UDP packets appear to be handled correctly by 2655 * Yukon II. 2656 */ 2657 if (m->m_pkthdr.len < MSK_MIN_FRAMELEN && 2658 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2659 uint16_t csum; 2660 2661 csum = in_cksum_skip(m, ntohs(ip->ip_len) + offset - 2662 (ip->ip_hl << 2), offset); 2663 *(uint16_t *)(m->m_data + offset + 2664 m->m_pkthdr.csum_data) = csum; 2665 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2666 } 2667 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2668 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2669 if (m == NULL) { 2670 *m_head = NULL; 2671 return (ENOBUFS); 2672 } 2673 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2674 offset += (tcp->th_off << 2); 2675 } 2676 *m_head = m; 2677 } 2678 2679 prod = sc_if->msk_cdata.msk_tx_prod; 2680 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2681 txd_last = txd; 2682 map = txd->tx_dmamap; 2683 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2684 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2685 if (error == EFBIG) { 2686 m = msk_defrag(*m_head, M_DONTWAIT, MSK_MAXTXSEGS); 2687 if (m == NULL) { 2688 m_freem(*m_head); 2689 *m_head = NULL; 2690 return (ENOBUFS); 2691 } 2692 *m_head = m; 2693 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2694 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2695 if (error != 0) { 2696 m_freem(*m_head); 2697 *m_head = NULL; 2698 return (error); 2699 } 2700 } else if (error != 0) 2701 return (error); 2702 if (nseg == 0) { 2703 m_freem(*m_head); 2704 *m_head = NULL; 2705 return (EIO); 2706 } 2707 2708 /* Check number of available descriptors. */ 2709 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2710 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2711 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2712 return (ENOBUFS); 2713 } 2714 2715 control = 0; 2716 tso = 0; 2717 tx_le = NULL; 2718 2719 /* Check TSO support. */ 2720 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2721 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2722 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2723 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2724 tx_le->msk_addr = htole32(tso_mtu); 2725 tx_le->msk_control = htole32(OP_LRGLEN | HW_OWNER); 2726 sc_if->msk_cdata.msk_tx_cnt++; 2727 MSK_INC(prod, MSK_TX_RING_CNT); 2728 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2729 } 2730 tso++; 2731 } 2732 /* Check if we have a VLAN tag to insert. */ 2733 if ((m->m_flags & M_VLANTAG) != 0) { 2734 if (tso == 0) { 2735 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2736 tx_le->msk_addr = htole32(0); 2737 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2738 htons(m->m_pkthdr.ether_vtag)); 2739 sc_if->msk_cdata.msk_tx_cnt++; 2740 MSK_INC(prod, MSK_TX_RING_CNT); 2741 } else { 2742 tx_le->msk_control |= htole32(OP_VLAN | 2743 htons(m->m_pkthdr.ether_vtag)); 2744 } 2745 control |= INS_VLAN; 2746 } 2747 /* Check if we have to handle checksum offload. */ 2748 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2749 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2750 tx_le->msk_addr = htole32(((tcp_offset + m->m_pkthdr.csum_data) 2751 & 0xffff) | ((uint32_t)tcp_offset << 16)); 2752 tx_le->msk_control = htole32(1 << 16 | (OP_TCPLISW | HW_OWNER)); 2753 control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2754 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2755 control |= UDPTCP; 2756 sc_if->msk_cdata.msk_tx_cnt++; 2757 MSK_INC(prod, MSK_TX_RING_CNT); 2758 } 2759 2760 si = prod; 2761 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2762 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2763 if (tso == 0) 2764 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2765 OP_PACKET); 2766 else 2767 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2768 OP_LARGESEND); 2769 sc_if->msk_cdata.msk_tx_cnt++; 2770 MSK_INC(prod, MSK_TX_RING_CNT); 2771 2772 for (i = 1; i < nseg; i++) { 2773 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2774 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2775 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2776 OP_BUFFER | HW_OWNER); 2777 sc_if->msk_cdata.msk_tx_cnt++; 2778 MSK_INC(prod, MSK_TX_RING_CNT); 2779 } 2780 /* Update producer index. */ 2781 sc_if->msk_cdata.msk_tx_prod = prod; 2782 2783 /* Set EOP on the last desciptor. */ 2784 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2785 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2786 tx_le->msk_control |= htole32(EOP); 2787 2788 /* Turn the first descriptor ownership to hardware. */ 2789 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2790 tx_le->msk_control |= htole32(HW_OWNER); 2791 2792 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2793 map = txd_last->tx_dmamap; 2794 txd_last->tx_dmamap = txd->tx_dmamap; 2795 txd->tx_dmamap = map; 2796 txd->tx_m = m; 2797 2798 /* Sync descriptors. */ 2799 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2800 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2801 sc_if->msk_cdata.msk_tx_ring_map, 2802 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2803 2804 return (0); 2805 } 2806 2807 static void 2808 msk_tx_task(void *arg, int pending) 2809 { 2810 struct ifnet *ifp; 2811 2812 ifp = arg; 2813 msk_start(ifp); 2814 } 2815 2816 static void 2817 msk_start(struct ifnet *ifp) 2818 { 2819 struct msk_if_softc *sc_if; 2820 struct mbuf *m_head; 2821 int enq; 2822 2823 sc_if = ifp->if_softc; 2824 2825 MSK_IF_LOCK(sc_if); 2826 2827 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2828 IFF_DRV_RUNNING || sc_if->msk_link == 0) { 2829 MSK_IF_UNLOCK(sc_if); 2830 return; 2831 } 2832 2833 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2834 sc_if->msk_cdata.msk_tx_cnt < 2835 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2836 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2837 if (m_head == NULL) 2838 break; 2839 /* 2840 * Pack the data into the transmit ring. If we 2841 * don't have room, set the OACTIVE flag and wait 2842 * for the NIC to drain the ring. 2843 */ 2844 if (msk_encap(sc_if, &m_head) != 0) { 2845 if (m_head == NULL) 2846 break; 2847 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2848 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2849 break; 2850 } 2851 2852 enq++; 2853 /* 2854 * If there's a BPF listener, bounce a copy of this frame 2855 * to him. 2856 */ 2857 ETHER_BPF_MTAP(ifp, m_head); 2858 } 2859 2860 if (enq > 0) { 2861 /* Transmit */ 2862 CSR_WRITE_2(sc_if->msk_softc, 2863 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2864 sc_if->msk_cdata.msk_tx_prod); 2865 2866 /* Set a timeout in case the chip goes out to lunch. */ 2867 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2868 } 2869 2870 MSK_IF_UNLOCK(sc_if); 2871 } 2872 2873 static void 2874 msk_watchdog(struct msk_if_softc *sc_if) 2875 { 2876 struct ifnet *ifp; 2877 uint32_t ridx; 2878 int idx; 2879 2880 MSK_IF_LOCK_ASSERT(sc_if); 2881 2882 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2883 return; 2884 ifp = sc_if->msk_ifp; 2885 if (sc_if->msk_link == 0) { 2886 if (bootverbose) 2887 if_printf(sc_if->msk_ifp, "watchdog timeout " 2888 "(missed link)\n"); 2889 ifp->if_oerrors++; 2890 msk_init_locked(sc_if); 2891 return; 2892 } 2893 2894 /* 2895 * Reclaim first as there is a possibility of losing Tx completion 2896 * interrupts. 2897 */ 2898 ridx = sc_if->msk_port == MSK_PORT_A ? STAT_TXA1_RIDX : STAT_TXA2_RIDX; 2899 idx = CSR_READ_2(sc_if->msk_softc, ridx); 2900 if (sc_if->msk_cdata.msk_tx_cons != idx) { 2901 msk_txeof(sc_if, idx); 2902 if (sc_if->msk_cdata.msk_tx_cnt == 0) { 2903 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2904 "-- recovering\n"); 2905 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2906 taskqueue_enqueue(taskqueue_fast, 2907 &sc_if->msk_tx_task); 2908 return; 2909 } 2910 } 2911 2912 if_printf(ifp, "watchdog timeout\n"); 2913 ifp->if_oerrors++; 2914 msk_init_locked(sc_if); 2915 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2916 taskqueue_enqueue(taskqueue_fast, &sc_if->msk_tx_task); 2917 } 2918 2919 static int 2920 mskc_shutdown(device_t dev) 2921 { 2922 struct msk_softc *sc; 2923 int i; 2924 2925 sc = device_get_softc(dev); 2926 MSK_LOCK(sc); 2927 for (i = 0; i < sc->msk_num_port; i++) { 2928 if (sc->msk_if[i] != NULL) 2929 msk_stop(sc->msk_if[i]); 2930 } 2931 2932 /* Disable all interrupts. */ 2933 CSR_WRITE_4(sc, B0_IMSK, 0); 2934 CSR_READ_4(sc, B0_IMSK); 2935 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2936 CSR_READ_4(sc, B0_HWE_IMSK); 2937 2938 /* Put hardware reset. */ 2939 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2940 2941 MSK_UNLOCK(sc); 2942 return (0); 2943 } 2944 2945 static int 2946 mskc_suspend(device_t dev) 2947 { 2948 struct msk_softc *sc; 2949 int i; 2950 2951 sc = device_get_softc(dev); 2952 2953 MSK_LOCK(sc); 2954 2955 for (i = 0; i < sc->msk_num_port; i++) { 2956 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2957 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 2958 IFF_DRV_RUNNING) != 0)) 2959 msk_stop(sc->msk_if[i]); 2960 } 2961 2962 /* Disable all interrupts. */ 2963 CSR_WRITE_4(sc, B0_IMSK, 0); 2964 CSR_READ_4(sc, B0_IMSK); 2965 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2966 CSR_READ_4(sc, B0_HWE_IMSK); 2967 2968 msk_phy_power(sc, MSK_PHY_POWERDOWN); 2969 2970 /* Put hardware reset. */ 2971 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2972 sc->msk_suspended = 1; 2973 2974 MSK_UNLOCK(sc); 2975 2976 return (0); 2977 } 2978 2979 static int 2980 mskc_resume(device_t dev) 2981 { 2982 struct msk_softc *sc; 2983 int i; 2984 2985 sc = device_get_softc(dev); 2986 2987 MSK_LOCK(sc); 2988 2989 mskc_reset(sc); 2990 for (i = 0; i < sc->msk_num_port; i++) { 2991 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2992 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) 2993 msk_init_locked(sc->msk_if[i]); 2994 } 2995 sc->msk_suspended = 0; 2996 2997 MSK_UNLOCK(sc); 2998 2999 return (0); 3000 } 3001 3002 static void 3003 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len) 3004 { 3005 struct mbuf *m; 3006 struct ifnet *ifp; 3007 struct msk_rxdesc *rxd; 3008 int cons, rxlen; 3009 3010 ifp = sc_if->msk_ifp; 3011 3012 MSK_IF_LOCK_ASSERT(sc_if); 3013 3014 cons = sc_if->msk_cdata.msk_rx_cons; 3015 do { 3016 rxlen = status >> 16; 3017 if ((status & GMR_FS_VLAN) != 0 && 3018 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3019 rxlen -= ETHER_VLAN_ENCAP_LEN; 3020 if (len > sc_if->msk_framesize || 3021 ((status & GMR_FS_ANY_ERR) != 0) || 3022 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3023 /* Don't count flow-control packet as errors. */ 3024 if ((status & GMR_FS_GOOD_FC) == 0) 3025 ifp->if_ierrors++; 3026 msk_discard_rxbuf(sc_if, cons); 3027 break; 3028 } 3029 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 3030 m = rxd->rx_m; 3031 if (msk_newbuf(sc_if, cons) != 0) { 3032 ifp->if_iqdrops++; 3033 /* Reuse old buffer. */ 3034 msk_discard_rxbuf(sc_if, cons); 3035 break; 3036 } 3037 m->m_pkthdr.rcvif = ifp; 3038 m->m_pkthdr.len = m->m_len = len; 3039 ifp->if_ipackets++; 3040 /* Check for VLAN tagged packets. */ 3041 if ((status & GMR_FS_VLAN) != 0 && 3042 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3043 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3044 m->m_flags |= M_VLANTAG; 3045 } 3046 MSK_IF_UNLOCK(sc_if); 3047 (*ifp->if_input)(ifp, m); 3048 MSK_IF_LOCK(sc_if); 3049 } while (0); 3050 3051 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 3052 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 3053 } 3054 3055 static void 3056 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len) 3057 { 3058 struct mbuf *m; 3059 struct ifnet *ifp; 3060 struct msk_rxdesc *jrxd; 3061 int cons, rxlen; 3062 3063 ifp = sc_if->msk_ifp; 3064 3065 MSK_IF_LOCK_ASSERT(sc_if); 3066 3067 cons = sc_if->msk_cdata.msk_rx_cons; 3068 do { 3069 rxlen = status >> 16; 3070 if ((status & GMR_FS_VLAN) != 0 && 3071 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3072 rxlen -= ETHER_VLAN_ENCAP_LEN; 3073 if (len > sc_if->msk_framesize || 3074 ((status & GMR_FS_ANY_ERR) != 0) || 3075 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3076 /* Don't count flow-control packet as errors. */ 3077 if ((status & GMR_FS_GOOD_FC) == 0) 3078 ifp->if_ierrors++; 3079 msk_discard_jumbo_rxbuf(sc_if, cons); 3080 break; 3081 } 3082 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 3083 m = jrxd->rx_m; 3084 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3085 ifp->if_iqdrops++; 3086 /* Reuse old buffer. */ 3087 msk_discard_jumbo_rxbuf(sc_if, cons); 3088 break; 3089 } 3090 m->m_pkthdr.rcvif = ifp; 3091 m->m_pkthdr.len = m->m_len = len; 3092 ifp->if_ipackets++; 3093 /* Check for VLAN tagged packets. */ 3094 if ((status & GMR_FS_VLAN) != 0 && 3095 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3096 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3097 m->m_flags |= M_VLANTAG; 3098 } 3099 MSK_IF_UNLOCK(sc_if); 3100 (*ifp->if_input)(ifp, m); 3101 MSK_IF_LOCK(sc_if); 3102 } while (0); 3103 3104 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3105 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3106 } 3107 3108 static void 3109 msk_txeof(struct msk_if_softc *sc_if, int idx) 3110 { 3111 struct msk_txdesc *txd; 3112 struct msk_tx_desc *cur_tx; 3113 struct ifnet *ifp; 3114 uint32_t control; 3115 int cons, prog; 3116 3117 MSK_IF_LOCK_ASSERT(sc_if); 3118 3119 ifp = sc_if->msk_ifp; 3120 3121 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3122 sc_if->msk_cdata.msk_tx_ring_map, 3123 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3124 /* 3125 * Go through our tx ring and free mbufs for those 3126 * frames that have been sent. 3127 */ 3128 cons = sc_if->msk_cdata.msk_tx_cons; 3129 prog = 0; 3130 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3131 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3132 break; 3133 prog++; 3134 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3135 control = le32toh(cur_tx->msk_control); 3136 sc_if->msk_cdata.msk_tx_cnt--; 3137 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3138 if ((control & EOP) == 0) 3139 continue; 3140 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3141 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3142 BUS_DMASYNC_POSTWRITE); 3143 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3144 3145 ifp->if_opackets++; 3146 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3147 __func__)); 3148 m_freem(txd->tx_m); 3149 txd->tx_m = NULL; 3150 } 3151 3152 if (prog > 0) { 3153 sc_if->msk_cdata.msk_tx_cons = cons; 3154 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3155 sc_if->msk_watchdog_timer = 0; 3156 /* No need to sync LEs as we didn't update LEs. */ 3157 } 3158 } 3159 3160 static void 3161 msk_tick(void *xsc_if) 3162 { 3163 struct msk_if_softc *sc_if; 3164 struct mii_data *mii; 3165 3166 sc_if = xsc_if; 3167 3168 MSK_IF_LOCK_ASSERT(sc_if); 3169 3170 mii = device_get_softc(sc_if->msk_miibus); 3171 3172 mii_tick(mii); 3173 msk_watchdog(sc_if); 3174 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3175 } 3176 3177 static void 3178 msk_intr_phy(struct msk_if_softc *sc_if) 3179 { 3180 uint16_t status; 3181 3182 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3183 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3184 /* Handle FIFO Underrun/Overflow? */ 3185 if ((status & PHY_M_IS_FIFO_ERROR)) 3186 device_printf(sc_if->msk_if_dev, 3187 "PHY FIFO underrun/overflow.\n"); 3188 } 3189 3190 static void 3191 msk_intr_gmac(struct msk_if_softc *sc_if) 3192 { 3193 struct msk_softc *sc; 3194 uint8_t status; 3195 3196 sc = sc_if->msk_softc; 3197 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3198 3199 /* GMAC Rx FIFO overrun. */ 3200 if ((status & GM_IS_RX_FF_OR) != 0) { 3201 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3202 GMF_CLI_RX_FO); 3203 device_printf(sc_if->msk_if_dev, "Rx FIFO overrun!\n"); 3204 } 3205 /* GMAC Tx FIFO underrun. */ 3206 if ((status & GM_IS_TX_FF_UR) != 0) { 3207 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3208 GMF_CLI_TX_FU); 3209 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3210 /* 3211 * XXX 3212 * In case of Tx underrun, we may need to flush/reset 3213 * Tx MAC but that would also require resynchronization 3214 * with status LEs. Reintializing status LEs would 3215 * affect other port in dual MAC configuration so it 3216 * should be avoided as possible as we can. 3217 * Due to lack of documentation it's all vague guess but 3218 * it needs more investigation. 3219 */ 3220 } 3221 } 3222 3223 static void 3224 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3225 { 3226 struct msk_softc *sc; 3227 3228 sc = sc_if->msk_softc; 3229 if ((status & Y2_IS_PAR_RD1) != 0) { 3230 device_printf(sc_if->msk_if_dev, 3231 "RAM buffer read parity error\n"); 3232 /* Clear IRQ. */ 3233 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3234 RI_CLR_RD_PERR); 3235 } 3236 if ((status & Y2_IS_PAR_WR1) != 0) { 3237 device_printf(sc_if->msk_if_dev, 3238 "RAM buffer write parity error\n"); 3239 /* Clear IRQ. */ 3240 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3241 RI_CLR_WR_PERR); 3242 } 3243 if ((status & Y2_IS_PAR_MAC1) != 0) { 3244 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3245 /* Clear IRQ. */ 3246 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3247 GMF_CLI_TX_PE); 3248 } 3249 if ((status & Y2_IS_PAR_RX1) != 0) { 3250 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3251 /* Clear IRQ. */ 3252 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3253 } 3254 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3255 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3256 /* Clear IRQ. */ 3257 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3258 } 3259 } 3260 3261 static void 3262 msk_intr_hwerr(struct msk_softc *sc) 3263 { 3264 uint32_t status; 3265 uint32_t tlphead[4]; 3266 3267 status = CSR_READ_4(sc, B0_HWE_ISRC); 3268 /* Time Stamp timer overflow. */ 3269 if ((status & Y2_IS_TIST_OV) != 0) 3270 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3271 if ((status & Y2_IS_PCI_NEXP) != 0) { 3272 /* 3273 * PCI Express Error occured which is not described in PEX 3274 * spec. 3275 * This error is also mapped either to Master Abort( 3276 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3277 * can only be cleared there. 3278 */ 3279 device_printf(sc->msk_dev, 3280 "PCI Express protocol violation error\n"); 3281 } 3282 3283 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3284 uint16_t v16; 3285 3286 if ((status & Y2_IS_MST_ERR) != 0) 3287 device_printf(sc->msk_dev, 3288 "unexpected IRQ Status error\n"); 3289 else 3290 device_printf(sc->msk_dev, 3291 "unexpected IRQ Master error\n"); 3292 /* Reset all bits in the PCI status register. */ 3293 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3294 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3295 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3296 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3297 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 3298 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3299 } 3300 3301 /* Check for PCI Express Uncorrectable Error. */ 3302 if ((status & Y2_IS_PCI_EXP) != 0) { 3303 uint32_t v32; 3304 3305 /* 3306 * On PCI Express bus bridges are called root complexes (RC). 3307 * PCI Express errors are recognized by the root complex too, 3308 * which requests the system to handle the problem. After 3309 * error occurence it may be that no access to the adapter 3310 * may be performed any longer. 3311 */ 3312 3313 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3314 if ((v32 & PEX_UNSUP_REQ) != 0) { 3315 /* Ignore unsupported request error. */ 3316 device_printf(sc->msk_dev, 3317 "Uncorrectable PCI Express error\n"); 3318 } 3319 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3320 int i; 3321 3322 /* Get TLP header form Log Registers. */ 3323 for (i = 0; i < 4; i++) 3324 tlphead[i] = CSR_PCI_READ_4(sc, 3325 PEX_HEADER_LOG + i * 4); 3326 /* Check for vendor defined broadcast message. */ 3327 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3328 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3329 CSR_WRITE_4(sc, B0_HWE_IMSK, 3330 sc->msk_intrhwemask); 3331 CSR_READ_4(sc, B0_HWE_IMSK); 3332 } 3333 } 3334 /* Clear the interrupt. */ 3335 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3336 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3337 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3338 } 3339 3340 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3341 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3342 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3343 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3344 } 3345 3346 static __inline void 3347 msk_rxput(struct msk_if_softc *sc_if) 3348 { 3349 struct msk_softc *sc; 3350 3351 sc = sc_if->msk_softc; 3352 if (sc_if->msk_framesize >(MCLBYTES - ETHER_HDR_LEN)) 3353 bus_dmamap_sync( 3354 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3355 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3356 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3357 else 3358 bus_dmamap_sync( 3359 sc_if->msk_cdata.msk_rx_ring_tag, 3360 sc_if->msk_cdata.msk_rx_ring_map, 3361 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3362 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3363 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3364 } 3365 3366 static int 3367 msk_handle_events(struct msk_softc *sc) 3368 { 3369 struct msk_if_softc *sc_if; 3370 int rxput[2]; 3371 struct msk_stat_desc *sd; 3372 uint32_t control, status; 3373 int cons, idx, len, port, rxprog; 3374 3375 idx = CSR_READ_2(sc, STAT_PUT_IDX); 3376 if (idx == sc->msk_stat_cons) 3377 return (0); 3378 3379 /* Sync status LEs. */ 3380 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3381 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3382 /* XXX Sync Rx LEs here. */ 3383 3384 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3385 3386 rxprog = 0; 3387 for (cons = sc->msk_stat_cons; cons != idx;) { 3388 sd = &sc->msk_stat_ring[cons]; 3389 control = le32toh(sd->msk_control); 3390 if ((control & HW_OWNER) == 0) 3391 break; 3392 /* 3393 * Marvell's FreeBSD driver updates status LE after clearing 3394 * HW_OWNER. However we don't have a way to sync single LE 3395 * with bus_dma(9) API. bus_dma(9) provides a way to sync 3396 * an entire DMA map. So don't sync LE until we have a better 3397 * way to sync LEs. 3398 */ 3399 control &= ~HW_OWNER; 3400 sd->msk_control = htole32(control); 3401 status = le32toh(sd->msk_status); 3402 len = control & STLE_LEN_MASK; 3403 port = (control >> 16) & 0x01; 3404 sc_if = sc->msk_if[port]; 3405 if (sc_if == NULL) { 3406 device_printf(sc->msk_dev, "invalid port opcode " 3407 "0x%08x\n", control & STLE_OP_MASK); 3408 continue; 3409 } 3410 3411 switch (control & STLE_OP_MASK) { 3412 case OP_RXVLAN: 3413 sc_if->msk_vtag = ntohs(len); 3414 break; 3415 case OP_RXCHKSVLAN: 3416 sc_if->msk_vtag = ntohs(len); 3417 break; 3418 case OP_RXSTAT: 3419 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) 3420 msk_jumbo_rxeof(sc_if, status, len); 3421 else 3422 msk_rxeof(sc_if, status, len); 3423 rxprog++; 3424 /* 3425 * Because there is no way to sync single Rx LE 3426 * put the DMA sync operation off until the end of 3427 * event processing. 3428 */ 3429 rxput[port]++; 3430 /* Update prefetch unit if we've passed water mark. */ 3431 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3432 msk_rxput(sc_if); 3433 rxput[port] = 0; 3434 } 3435 break; 3436 case OP_TXINDEXLE: 3437 if (sc->msk_if[MSK_PORT_A] != NULL) 3438 msk_txeof(sc->msk_if[MSK_PORT_A], 3439 status & STLE_TXA1_MSKL); 3440 if (sc->msk_if[MSK_PORT_B] != NULL) 3441 msk_txeof(sc->msk_if[MSK_PORT_B], 3442 ((status & STLE_TXA2_MSKL) >> 3443 STLE_TXA2_SHIFTL) | 3444 ((len & STLE_TXA2_MSKH) << 3445 STLE_TXA2_SHIFTH)); 3446 break; 3447 default: 3448 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3449 control & STLE_OP_MASK); 3450 break; 3451 } 3452 MSK_INC(cons, MSK_STAT_RING_CNT); 3453 if (rxprog > sc->msk_process_limit) 3454 break; 3455 } 3456 3457 sc->msk_stat_cons = cons; 3458 /* XXX We should sync status LEs here. See above notes. */ 3459 3460 if (rxput[MSK_PORT_A] > 0) 3461 msk_rxput(sc->msk_if[MSK_PORT_A]); 3462 if (rxput[MSK_PORT_B] > 0) 3463 msk_rxput(sc->msk_if[MSK_PORT_B]); 3464 3465 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3466 } 3467 3468 /* Legacy interrupt handler for shared interrupt. */ 3469 static void 3470 msk_legacy_intr(void *xsc) 3471 { 3472 struct msk_softc *sc; 3473 struct msk_if_softc *sc_if0, *sc_if1; 3474 struct ifnet *ifp0, *ifp1; 3475 uint32_t status; 3476 3477 sc = xsc; 3478 MSK_LOCK(sc); 3479 3480 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3481 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3482 if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 || 3483 (status & sc->msk_intrmask) == 0) { 3484 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3485 return; 3486 } 3487 3488 sc_if0 = sc->msk_if[MSK_PORT_A]; 3489 sc_if1 = sc->msk_if[MSK_PORT_B]; 3490 ifp0 = ifp1 = NULL; 3491 if (sc_if0 != NULL) 3492 ifp0 = sc_if0->msk_ifp; 3493 if (sc_if1 != NULL) 3494 ifp1 = sc_if1->msk_ifp; 3495 3496 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3497 msk_intr_phy(sc_if0); 3498 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3499 msk_intr_phy(sc_if1); 3500 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3501 msk_intr_gmac(sc_if0); 3502 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3503 msk_intr_gmac(sc_if1); 3504 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3505 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3506 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3507 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3508 CSR_READ_4(sc, B0_IMSK); 3509 } 3510 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3511 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3512 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3513 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3514 CSR_READ_4(sc, B0_IMSK); 3515 } 3516 if ((status & Y2_IS_HW_ERR) != 0) 3517 msk_intr_hwerr(sc); 3518 3519 while (msk_handle_events(sc) != 0) 3520 ; 3521 if ((status & Y2_IS_STAT_BMU) != 0) 3522 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3523 3524 /* Reenable interrupts. */ 3525 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3526 3527 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3528 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3529 taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task); 3530 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3531 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3532 taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task); 3533 3534 MSK_UNLOCK(sc); 3535 } 3536 3537 static int 3538 msk_intr(void *xsc) 3539 { 3540 struct msk_softc *sc; 3541 uint32_t status; 3542 3543 sc = xsc; 3544 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3545 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3546 if (status == 0 || status == 0xffffffff) { 3547 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3548 return (FILTER_STRAY); 3549 } 3550 3551 taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task); 3552 return (FILTER_HANDLED); 3553 } 3554 3555 static void 3556 msk_int_task(void *arg, int pending) 3557 { 3558 struct msk_softc *sc; 3559 struct msk_if_softc *sc_if0, *sc_if1; 3560 struct ifnet *ifp0, *ifp1; 3561 uint32_t status; 3562 int domore; 3563 3564 sc = arg; 3565 MSK_LOCK(sc); 3566 3567 /* Get interrupt source. */ 3568 status = CSR_READ_4(sc, B0_ISRC); 3569 if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 || 3570 (status & sc->msk_intrmask) == 0) 3571 goto done; 3572 3573 sc_if0 = sc->msk_if[MSK_PORT_A]; 3574 sc_if1 = sc->msk_if[MSK_PORT_B]; 3575 ifp0 = ifp1 = NULL; 3576 if (sc_if0 != NULL) 3577 ifp0 = sc_if0->msk_ifp; 3578 if (sc_if1 != NULL) 3579 ifp1 = sc_if1->msk_ifp; 3580 3581 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3582 msk_intr_phy(sc_if0); 3583 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3584 msk_intr_phy(sc_if1); 3585 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3586 msk_intr_gmac(sc_if0); 3587 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3588 msk_intr_gmac(sc_if1); 3589 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3590 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3591 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3592 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3593 CSR_READ_4(sc, B0_IMSK); 3594 } 3595 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3596 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3597 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3598 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3599 CSR_READ_4(sc, B0_IMSK); 3600 } 3601 if ((status & Y2_IS_HW_ERR) != 0) 3602 msk_intr_hwerr(sc); 3603 3604 domore = msk_handle_events(sc); 3605 if ((status & Y2_IS_STAT_BMU) != 0) 3606 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3607 3608 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3609 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3610 taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task); 3611 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3612 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3613 taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task); 3614 3615 if (domore > 0) { 3616 taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task); 3617 MSK_UNLOCK(sc); 3618 return; 3619 } 3620 done: 3621 MSK_UNLOCK(sc); 3622 3623 /* Reenable interrupts. */ 3624 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3625 } 3626 3627 static void 3628 msk_init(void *xsc) 3629 { 3630 struct msk_if_softc *sc_if = xsc; 3631 3632 MSK_IF_LOCK(sc_if); 3633 msk_init_locked(sc_if); 3634 MSK_IF_UNLOCK(sc_if); 3635 } 3636 3637 static void 3638 msk_init_locked(struct msk_if_softc *sc_if) 3639 { 3640 struct msk_softc *sc; 3641 struct ifnet *ifp; 3642 struct mii_data *mii; 3643 uint16_t eaddr[ETHER_ADDR_LEN / 2]; 3644 uint16_t gmac; 3645 int error, i; 3646 3647 MSK_IF_LOCK_ASSERT(sc_if); 3648 3649 ifp = sc_if->msk_ifp; 3650 sc = sc_if->msk_softc; 3651 mii = device_get_softc(sc_if->msk_miibus); 3652 3653 error = 0; 3654 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3655 msk_stop(sc_if); 3656 3657 sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN + 3658 ETHER_VLAN_ENCAP_LEN; 3659 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN && 3660 sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 3661 /* 3662 * In Yukon EC Ultra, TSO & checksum offload is not 3663 * supported for jumbo frame. 3664 */ 3665 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 3666 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 3667 } 3668 3669 /* 3670 * Initialize GMAC first. 3671 * Without this initialization, Rx MAC did not work as expected 3672 * and Rx MAC garbled status LEs and it resulted in out-of-order 3673 * or duplicated frame delivery which in turn showed very poor 3674 * Rx performance.(I had to write a packet analysis code that 3675 * could be embeded in driver to diagnose this issue.) 3676 * I've spent almost 2 months to fix this issue. If I have had 3677 * datasheet for Yukon II I wouldn't have encountered this. :-( 3678 */ 3679 gmac = GM_GPCR_SPEED_100 | GM_GPCR_SPEED_1000 | GM_GPCR_DUP_FULL; 3680 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 3681 3682 /* Dummy read the Interrupt Source Register. */ 3683 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3684 3685 /* Set MIB Clear Counter Mode. */ 3686 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 3687 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 3688 /* Read all MIB Counters with Clear Mode set. */ 3689 for (i = 0; i < GM_MIB_CNT_SIZE; i++) 3690 GMAC_READ_2(sc, sc_if->msk_port, GM_MIB_CNT_BASE + 8 * i); 3691 /* Clear MIB Clear Counter Mode. */ 3692 gmac &= ~GM_PAR_MIB_CLR; 3693 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 3694 3695 /* Disable FCS. */ 3696 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3697 3698 /* Setup Transmit Control Register. */ 3699 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3700 3701 /* Setup Transmit Flow Control Register. */ 3702 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3703 3704 /* Setup Transmit Parameter Register. */ 3705 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3706 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3707 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3708 3709 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3710 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3711 3712 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) 3713 gmac |= GM_SMOD_JUMBO_ENA; 3714 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3715 3716 /* Set station address. */ 3717 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3718 for (i = 0; i < ETHER_ADDR_LEN /2; i++) 3719 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L + i * 4, 3720 eaddr[i]); 3721 for (i = 0; i < ETHER_ADDR_LEN /2; i++) 3722 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L + i * 4, 3723 eaddr[i]); 3724 3725 /* Disable interrupts for counter overflows. */ 3726 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3727 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3728 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3729 3730 /* Configure Rx MAC FIFO. */ 3731 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3732 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3733 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3734 GMF_OPER_ON | GMF_RX_F_FL_ON); 3735 3736 /* Set promiscuous mode. */ 3737 msk_setpromisc(sc_if); 3738 3739 /* Set multicast filter. */ 3740 msk_setmulti(sc_if); 3741 3742 /* Flush Rx MAC FIFO on any flow control or error. */ 3743 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3744 GMR_FS_ANY_ERR); 3745 3746 /* Set Rx FIFO flush threshold to 64 bytes. */ 3747 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), 3748 RX_GMF_FL_THR_DEF); 3749 3750 /* Configure Tx MAC FIFO. */ 3751 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3752 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3753 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3754 3755 /* Configure hardware VLAN tag insertion/stripping. */ 3756 msk_setvlan(sc_if, ifp); 3757 3758 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 3759 /* Set Rx Pause threshould. */ 3760 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3761 MSK_ECU_LLPP); 3762 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3763 MSK_ECU_ULPP); 3764 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) { 3765 /* 3766 * Set Tx GMAC FIFO Almost Empty Threshold. 3767 */ 3768 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3769 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3770 /* Disable Store & Forward mode for Tx. */ 3771 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3772 TX_JUMBO_ENA | TX_STFW_DIS); 3773 } else { 3774 /* Enable Store & Forward mode for Tx. */ 3775 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3776 TX_JUMBO_DIS | TX_STFW_ENA); 3777 } 3778 } 3779 3780 /* 3781 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3782 * arbiter as we don't use Sync Tx queue. 3783 */ 3784 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3785 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3786 /* Enable the RAM Interface Arbiter. */ 3787 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3788 3789 /* Setup RAM buffer. */ 3790 msk_set_rambuffer(sc_if); 3791 3792 /* Disable Tx sync Queue. */ 3793 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3794 3795 /* Setup Tx Queue Bus Memory Interface. */ 3796 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3797 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3798 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3799 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3800 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3801 sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3802 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3803 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), MSK_ECU_TXFF_LEV); 3804 } 3805 3806 /* Setup Rx Queue Bus Memory Interface. */ 3807 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3808 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3809 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3810 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3811 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3812 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3813 /* MAC Rx RAM Read is controlled by hardware. */ 3814 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3815 } 3816 3817 msk_set_prefetch(sc, sc_if->msk_txq, 3818 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3819 msk_init_tx_ring(sc_if); 3820 3821 /* Disable Rx checksum offload and RSS hash. */ 3822 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 3823 BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH); 3824 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) { 3825 msk_set_prefetch(sc, sc_if->msk_rxq, 3826 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 3827 MSK_JUMBO_RX_RING_CNT - 1); 3828 error = msk_init_jumbo_rx_ring(sc_if); 3829 } else { 3830 msk_set_prefetch(sc, sc_if->msk_rxq, 3831 sc_if->msk_rdata.msk_rx_ring_paddr, 3832 MSK_RX_RING_CNT - 1); 3833 error = msk_init_rx_ring(sc_if); 3834 } 3835 if (error != 0) { 3836 device_printf(sc_if->msk_if_dev, 3837 "initialization failed: no memory for Rx buffers\n"); 3838 msk_stop(sc_if); 3839 return; 3840 } 3841 3842 /* Configure interrupt handling. */ 3843 if (sc_if->msk_port == MSK_PORT_A) { 3844 sc->msk_intrmask |= Y2_IS_PORT_A; 3845 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 3846 } else { 3847 sc->msk_intrmask |= Y2_IS_PORT_B; 3848 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 3849 } 3850 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3851 CSR_READ_4(sc, B0_HWE_IMSK); 3852 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3853 CSR_READ_4(sc, B0_IMSK); 3854 3855 sc_if->msk_link = 0; 3856 mii_mediachg(mii); 3857 3858 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3859 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3860 3861 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3862 } 3863 3864 static void 3865 msk_set_rambuffer(struct msk_if_softc *sc_if) 3866 { 3867 struct msk_softc *sc; 3868 int ltpp, utpp; 3869 3870 sc = sc_if->msk_softc; 3871 3872 /* Setup Rx Queue. */ 3873 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 3874 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 3875 sc->msk_rxqstart[sc_if->msk_port] / 8); 3876 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 3877 sc->msk_rxqend[sc_if->msk_port] / 8); 3878 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 3879 sc->msk_rxqstart[sc_if->msk_port] / 8); 3880 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 3881 sc->msk_rxqstart[sc_if->msk_port] / 8); 3882 3883 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3884 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 3885 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3886 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 3887 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 3888 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 3889 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 3890 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 3891 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 3892 3893 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 3894 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 3895 3896 /* Setup Tx Queue. */ 3897 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 3898 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 3899 sc->msk_txqstart[sc_if->msk_port] / 8); 3900 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 3901 sc->msk_txqend[sc_if->msk_port] / 8); 3902 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 3903 sc->msk_txqstart[sc_if->msk_port] / 8); 3904 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 3905 sc->msk_txqstart[sc_if->msk_port] / 8); 3906 /* Enable Store & Forward for Tx side. */ 3907 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 3908 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 3909 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 3910 } 3911 3912 static void 3913 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 3914 uint32_t count) 3915 { 3916 3917 /* Reset the prefetch unit. */ 3918 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3919 PREF_UNIT_RST_SET); 3920 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3921 PREF_UNIT_RST_CLR); 3922 /* Set LE base address. */ 3923 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 3924 MSK_ADDR_LO(addr)); 3925 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 3926 MSK_ADDR_HI(addr)); 3927 /* Set the list last index. */ 3928 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 3929 count); 3930 /* Turn on prefetch unit. */ 3931 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3932 PREF_UNIT_OP_ON); 3933 /* Dummy read to ensure write. */ 3934 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 3935 } 3936 3937 static void 3938 msk_stop(struct msk_if_softc *sc_if) 3939 { 3940 struct msk_softc *sc; 3941 struct msk_txdesc *txd; 3942 struct msk_rxdesc *rxd; 3943 struct msk_rxdesc *jrxd; 3944 struct ifnet *ifp; 3945 uint32_t val; 3946 int i; 3947 3948 MSK_IF_LOCK_ASSERT(sc_if); 3949 sc = sc_if->msk_softc; 3950 ifp = sc_if->msk_ifp; 3951 3952 callout_stop(&sc_if->msk_tick_ch); 3953 sc_if->msk_watchdog_timer = 0; 3954 3955 /* Disable interrupts. */ 3956 if (sc_if->msk_port == MSK_PORT_A) { 3957 sc->msk_intrmask &= ~Y2_IS_PORT_A; 3958 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 3959 } else { 3960 sc->msk_intrmask &= ~Y2_IS_PORT_B; 3961 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 3962 } 3963 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3964 CSR_READ_4(sc, B0_HWE_IMSK); 3965 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3966 CSR_READ_4(sc, B0_IMSK); 3967 3968 /* Disable Tx/Rx MAC. */ 3969 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 3970 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 3971 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 3972 /* Read again to ensure writing. */ 3973 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 3974 3975 /* Stop Tx BMU. */ 3976 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 3977 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 3978 for (i = 0; i < MSK_TIMEOUT; i++) { 3979 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 3980 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 3981 BMU_STOP); 3982 CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 3983 } else 3984 break; 3985 DELAY(1); 3986 } 3987 if (i == MSK_TIMEOUT) 3988 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 3989 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 3990 RB_RST_SET | RB_DIS_OP_MD); 3991 3992 /* Disable all GMAC interrupt. */ 3993 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 3994 /* Disable PHY interrupt. */ 3995 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 3996 3997 /* Disable the RAM Interface Arbiter. */ 3998 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 3999 4000 /* Reset the PCI FIFO of the async Tx queue */ 4001 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4002 BMU_RST_SET | BMU_FIFO_RST); 4003 4004 /* Reset the Tx prefetch units. */ 4005 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 4006 PREF_UNIT_RST_SET); 4007 4008 /* Reset the RAM Buffer async Tx queue. */ 4009 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 4010 4011 /* Reset Tx MAC FIFO. */ 4012 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 4013 /* Set Pause Off. */ 4014 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 4015 4016 /* 4017 * The Rx Stop command will not work for Yukon-2 if the BMU does not 4018 * reach the end of packet and since we can't make sure that we have 4019 * incoming data, we must reset the BMU while it is not during a DMA 4020 * transfer. Since it is possible that the Rx path is still active, 4021 * the Rx RAM buffer will be stopped first, so any possible incoming 4022 * data will not trigger a DMA. After the RAM buffer is stopped, the 4023 * BMU is polled until any DMA in progress is ended and only then it 4024 * will be reset. 4025 */ 4026 4027 /* Disable the RAM Buffer receive queue. */ 4028 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 4029 for (i = 0; i < MSK_TIMEOUT; i++) { 4030 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 4031 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 4032 break; 4033 DELAY(1); 4034 } 4035 if (i == MSK_TIMEOUT) 4036 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 4037 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 4038 BMU_RST_SET | BMU_FIFO_RST); 4039 /* Reset the Rx prefetch unit. */ 4040 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 4041 PREF_UNIT_RST_SET); 4042 /* Reset the RAM Buffer receive queue. */ 4043 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 4044 /* Reset Rx MAC FIFO. */ 4045 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 4046 4047 /* Free Rx and Tx mbufs still in the queues. */ 4048 for (i = 0; i < MSK_RX_RING_CNT; i++) { 4049 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 4050 if (rxd->rx_m != NULL) { 4051 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 4052 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4053 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 4054 rxd->rx_dmamap); 4055 m_freem(rxd->rx_m); 4056 rxd->rx_m = NULL; 4057 } 4058 } 4059 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 4060 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 4061 if (jrxd->rx_m != NULL) { 4062 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 4063 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4064 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 4065 jrxd->rx_dmamap); 4066 m_freem(jrxd->rx_m); 4067 jrxd->rx_m = NULL; 4068 } 4069 } 4070 for (i = 0; i < MSK_TX_RING_CNT; i++) { 4071 txd = &sc_if->msk_cdata.msk_txdesc[i]; 4072 if (txd->tx_m != NULL) { 4073 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 4074 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4075 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 4076 txd->tx_dmamap); 4077 m_freem(txd->tx_m); 4078 txd->tx_m = NULL; 4079 } 4080 } 4081 4082 /* 4083 * Mark the interface down. 4084 */ 4085 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4086 sc_if->msk_link = 0; 4087 } 4088 4089 static int 4090 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4091 { 4092 int error, value; 4093 4094 if (!arg1) 4095 return (EINVAL); 4096 value = *(int *)arg1; 4097 error = sysctl_handle_int(oidp, &value, 0, req); 4098 if (error || !req->newptr) 4099 return (error); 4100 if (value < low || value > high) 4101 return (EINVAL); 4102 *(int *)arg1 = value; 4103 4104 return (0); 4105 } 4106 4107 static int 4108 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4109 { 4110 4111 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4112 MSK_PROC_MAX)); 4113 } 4114