1 /****************************************************************************** 2 * 3 * Name : sky2.c 4 * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 5 * Version: $Revision: 1.23 $ 6 * Date : $Date: 2005/12/22 09:04:11 $ 7 * Purpose: Main driver source file 8 * 9 *****************************************************************************/ 10 11 /****************************************************************************** 12 * 13 * LICENSE: 14 * Copyright (C) Marvell International Ltd. and/or its affiliates 15 * 16 * The computer program files contained in this folder ("Files") 17 * are provided to you under the BSD-type license terms provided 18 * below, and any use of such Files and any derivative works 19 * thereof created by you shall be governed by the following terms 20 * and conditions: 21 * 22 * - Redistributions of source code must retain the above copyright 23 * notice, this list of conditions and the following disclaimer. 24 * - Redistributions in binary form must reproduce the above 25 * copyright notice, this list of conditions and the following 26 * disclaimer in the documentation and/or other materials provided 27 * with the distribution. 28 * - Neither the name of Marvell nor the names of its contributors 29 * may be used to endorse or promote products derived from this 30 * software without specific prior written permission. 31 * 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 33 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 34 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 35 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 36 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 37 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 38 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 39 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 41 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 42 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 43 * OF THE POSSIBILITY OF SUCH DAMAGE. 44 * /LICENSE 45 * 46 *****************************************************************************/ 47 48 /*- 49 * Copyright (c) 1997, 1998, 1999, 2000 50 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 51 * 52 * Redistribution and use in source and binary forms, with or without 53 * modification, are permitted provided that the following conditions 54 * are met: 55 * 1. Redistributions of source code must retain the above copyright 56 * notice, this list of conditions and the following disclaimer. 57 * 2. Redistributions in binary form must reproduce the above copyright 58 * notice, this list of conditions and the following disclaimer in the 59 * documentation and/or other materials provided with the distribution. 60 * 3. All advertising materials mentioning features or use of this software 61 * must display the following acknowledgement: 62 * This product includes software developed by Bill Paul. 63 * 4. Neither the name of the author nor the names of any co-contributors 64 * may be used to endorse or promote products derived from this software 65 * without specific prior written permission. 66 * 67 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 68 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 69 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 70 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 71 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 72 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 73 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 74 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 75 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 76 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 77 * THE POSSIBILITY OF SUCH DAMAGE. 78 */ 79 /*- 80 * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 81 * 82 * Permission to use, copy, modify, and distribute this software for any 83 * purpose with or without fee is hereby granted, provided that the above 84 * copyright notice and this permission notice appear in all copies. 85 * 86 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 87 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 88 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 89 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 90 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 91 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 92 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 93 */ 94 95 /* 96 * Device driver for the Marvell Yukon II Ethernet controller. 97 * Due to lack of documentation, this driver is based on the code from 98 * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 99 */ 100 101 #include <sys/cdefs.h> 102 __FBSDID("$FreeBSD$"); 103 104 #include <sys/param.h> 105 #include <sys/systm.h> 106 #include <sys/bus.h> 107 #include <sys/endian.h> 108 #include <sys/mbuf.h> 109 #include <sys/malloc.h> 110 #include <sys/kernel.h> 111 #include <sys/module.h> 112 #include <sys/socket.h> 113 #include <sys/sockio.h> 114 #include <sys/queue.h> 115 #include <sys/sysctl.h> 116 #include <sys/taskqueue.h> 117 118 #include <net/bpf.h> 119 #include <net/ethernet.h> 120 #include <net/if.h> 121 #include <net/if_arp.h> 122 #include <net/if_dl.h> 123 #include <net/if_media.h> 124 #include <net/if_types.h> 125 #include <net/if_vlan_var.h> 126 127 #include <netinet/in.h> 128 #include <netinet/in_systm.h> 129 #include <netinet/ip.h> 130 #include <netinet/tcp.h> 131 #include <netinet/udp.h> 132 133 #include <machine/bus.h> 134 #include <machine/in_cksum.h> 135 #include <machine/resource.h> 136 #include <sys/rman.h> 137 138 #include <dev/mii/mii.h> 139 #include <dev/mii/miivar.h> 140 #include <dev/mii/brgphyreg.h> 141 142 #include <dev/pci/pcireg.h> 143 #include <dev/pci/pcivar.h> 144 145 #include <dev/msk/if_mskreg.h> 146 147 MODULE_DEPEND(msk, pci, 1, 1, 1); 148 MODULE_DEPEND(msk, ether, 1, 1, 1); 149 MODULE_DEPEND(msk, miibus, 1, 1, 1); 150 151 /* "device miibus" required. See GENERIC if you get errors here. */ 152 #include "miibus_if.h" 153 154 /* Tunables. */ 155 static int msi_disable = 0; 156 TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 157 static int legacy_intr = 0; 158 TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 159 160 #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 161 162 /* 163 * Devices supported by this driver. 164 */ 165 static struct msk_product { 166 uint16_t msk_vendorid; 167 uint16_t msk_deviceid; 168 const char *msk_name; 169 } msk_products[] = { 170 { VENDORID_SK, DEVICEID_SK_YUKON2, 171 "SK-9Sxx Gigabit Ethernet" }, 172 { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 173 "SK-9Exx Gigabit Ethernet"}, 174 { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 175 "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 176 { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 177 "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 178 { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 179 "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 180 { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 181 "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 182 { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 183 "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 184 { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 185 "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 186 { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 187 "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 188 { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 189 "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 190 { VENDORID_MARVELL, DEVICEID_MRVL_8035, 191 "Marvell Yukon 88E8035 Gigabit Ethernet" }, 192 { VENDORID_MARVELL, DEVICEID_MRVL_8036, 193 "Marvell Yukon 88E8036 Gigabit Ethernet" }, 194 { VENDORID_MARVELL, DEVICEID_MRVL_8038, 195 "Marvell Yukon 88E8038 Gigabit Ethernet" }, 196 { VENDORID_MARVELL, DEVICEID_MRVL_8039, 197 "Marvell Yukon 88E8039 Gigabit Ethernet" }, 198 { VENDORID_MARVELL, DEVICEID_MRVL_4361, 199 "Marvell Yukon 88E8050 Gigabit Ethernet" }, 200 { VENDORID_MARVELL, DEVICEID_MRVL_4360, 201 "Marvell Yukon 88E8052 Gigabit Ethernet" }, 202 { VENDORID_MARVELL, DEVICEID_MRVL_4362, 203 "Marvell Yukon 88E8053 Gigabit Ethernet" }, 204 { VENDORID_MARVELL, DEVICEID_MRVL_4363, 205 "Marvell Yukon 88E8055 Gigabit Ethernet" }, 206 { VENDORID_MARVELL, DEVICEID_MRVL_4364, 207 "Marvell Yukon 88E8056 Gigabit Ethernet" }, 208 { VENDORID_MARVELL, DEVICEID_MRVL_436A, 209 "Marvell Yukon 88E8058 Gigabit Ethernet" }, 210 { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 211 "D-Link 550SX Gigabit Ethernet" }, 212 { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 213 "D-Link 560T Gigabit Ethernet" } 214 }; 215 216 static const char *model_name[] = { 217 "Yukon XL", 218 "Yukon EC Ultra", 219 "Yukon Unknown", 220 "Yukon EC", 221 "Yukon FE" 222 }; 223 224 static int mskc_probe(device_t); 225 static int mskc_attach(device_t); 226 static int mskc_detach(device_t); 227 static int mskc_shutdown(device_t); 228 static int mskc_setup_rambuffer(struct msk_softc *); 229 static int mskc_suspend(device_t); 230 static int mskc_resume(device_t); 231 static void mskc_reset(struct msk_softc *); 232 233 static int msk_probe(device_t); 234 static int msk_attach(device_t); 235 static int msk_detach(device_t); 236 237 static void msk_tick(void *); 238 static void msk_legacy_intr(void *); 239 static int msk_intr(void *); 240 static void msk_int_task(void *, int); 241 static void msk_intr_phy(struct msk_if_softc *); 242 static void msk_intr_gmac(struct msk_if_softc *); 243 static __inline void msk_rxput(struct msk_if_softc *); 244 static int msk_handle_events(struct msk_softc *); 245 static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 246 static void msk_intr_hwerr(struct msk_softc *); 247 static void msk_rxeof(struct msk_if_softc *, uint32_t, int); 248 static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, int); 249 static void msk_txeof(struct msk_if_softc *, int); 250 static struct mbuf *msk_defrag(struct mbuf *, int, int); 251 static int msk_encap(struct msk_if_softc *, struct mbuf **); 252 static void msk_tx_task(void *, int); 253 static void msk_start(struct ifnet *); 254 static int msk_ioctl(struct ifnet *, u_long, caddr_t); 255 static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 256 static void msk_set_rambuffer(struct msk_if_softc *); 257 static void msk_init(void *); 258 static void msk_init_locked(struct msk_if_softc *); 259 static void msk_stop(struct msk_if_softc *); 260 static void msk_watchdog(struct msk_if_softc *); 261 static int msk_mediachange(struct ifnet *); 262 static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 263 static void msk_phy_power(struct msk_softc *, int); 264 static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 265 static int msk_status_dma_alloc(struct msk_softc *); 266 static void msk_status_dma_free(struct msk_softc *); 267 static int msk_txrx_dma_alloc(struct msk_if_softc *); 268 static void msk_txrx_dma_free(struct msk_if_softc *); 269 static void *msk_jalloc(struct msk_if_softc *); 270 static void msk_jfree(void *, void *); 271 static int msk_init_rx_ring(struct msk_if_softc *); 272 static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 273 static void msk_init_tx_ring(struct msk_if_softc *); 274 static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 275 static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 276 static int msk_newbuf(struct msk_if_softc *, int); 277 static int msk_jumbo_newbuf(struct msk_if_softc *, int); 278 279 static int msk_phy_readreg(struct msk_if_softc *, int, int); 280 static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 281 static int msk_miibus_readreg(device_t, int, int); 282 static int msk_miibus_writereg(device_t, int, int, int); 283 static void msk_miibus_statchg(device_t); 284 static void msk_link_task(void *, int); 285 286 static void msk_setmulti(struct msk_if_softc *); 287 static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 288 static void msk_setpromisc(struct msk_if_softc *); 289 290 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 291 static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 292 293 static device_method_t mskc_methods[] = { 294 /* Device interface */ 295 DEVMETHOD(device_probe, mskc_probe), 296 DEVMETHOD(device_attach, mskc_attach), 297 DEVMETHOD(device_detach, mskc_detach), 298 DEVMETHOD(device_suspend, mskc_suspend), 299 DEVMETHOD(device_resume, mskc_resume), 300 DEVMETHOD(device_shutdown, mskc_shutdown), 301 302 /* bus interface */ 303 DEVMETHOD(bus_print_child, bus_generic_print_child), 304 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 305 306 { NULL, NULL } 307 }; 308 309 static driver_t mskc_driver = { 310 "mskc", 311 mskc_methods, 312 sizeof(struct msk_softc) 313 }; 314 315 static devclass_t mskc_devclass; 316 317 static device_method_t msk_methods[] = { 318 /* Device interface */ 319 DEVMETHOD(device_probe, msk_probe), 320 DEVMETHOD(device_attach, msk_attach), 321 DEVMETHOD(device_detach, msk_detach), 322 DEVMETHOD(device_shutdown, bus_generic_shutdown), 323 324 /* bus interface */ 325 DEVMETHOD(bus_print_child, bus_generic_print_child), 326 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 327 328 /* MII interface */ 329 DEVMETHOD(miibus_readreg, msk_miibus_readreg), 330 DEVMETHOD(miibus_writereg, msk_miibus_writereg), 331 DEVMETHOD(miibus_statchg, msk_miibus_statchg), 332 333 { NULL, NULL } 334 }; 335 336 static driver_t msk_driver = { 337 "msk", 338 msk_methods, 339 sizeof(struct msk_if_softc) 340 }; 341 342 static devclass_t msk_devclass; 343 344 DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0); 345 DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0); 346 DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0); 347 348 static struct resource_spec msk_res_spec_io[] = { 349 { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 350 { -1, 0, 0 } 351 }; 352 353 static struct resource_spec msk_res_spec_mem[] = { 354 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 355 { -1, 0, 0 } 356 }; 357 358 static struct resource_spec msk_irq_spec_legacy[] = { 359 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 360 { -1, 0, 0 } 361 }; 362 363 static struct resource_spec msk_irq_spec_msi[] = { 364 { SYS_RES_IRQ, 1, RF_ACTIVE }, 365 { -1, 0, 0 } 366 }; 367 368 static struct resource_spec msk_irq_spec_msi2[] = { 369 { SYS_RES_IRQ, 1, RF_ACTIVE }, 370 { SYS_RES_IRQ, 2, RF_ACTIVE }, 371 { -1, 0, 0 } 372 }; 373 374 static int 375 msk_miibus_readreg(device_t dev, int phy, int reg) 376 { 377 struct msk_if_softc *sc_if; 378 379 if (phy != PHY_ADDR_MARV) 380 return (0); 381 382 sc_if = device_get_softc(dev); 383 384 return (msk_phy_readreg(sc_if, phy, reg)); 385 } 386 387 static int 388 msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 389 { 390 struct msk_softc *sc; 391 int i, val; 392 393 sc = sc_if->msk_softc; 394 395 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 396 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 397 398 for (i = 0; i < MSK_TIMEOUT; i++) { 399 DELAY(1); 400 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 401 if ((val & GM_SMI_CT_RD_VAL) != 0) { 402 val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 403 break; 404 } 405 } 406 407 if (i == MSK_TIMEOUT) { 408 if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 409 val = 0; 410 } 411 412 return (val); 413 } 414 415 static int 416 msk_miibus_writereg(device_t dev, int phy, int reg, int val) 417 { 418 struct msk_if_softc *sc_if; 419 420 if (phy != PHY_ADDR_MARV) 421 return (0); 422 423 sc_if = device_get_softc(dev); 424 425 return (msk_phy_writereg(sc_if, phy, reg, val)); 426 } 427 428 static int 429 msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 430 { 431 struct msk_softc *sc; 432 int i; 433 434 sc = sc_if->msk_softc; 435 436 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 437 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 438 GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 439 for (i = 0; i < MSK_TIMEOUT; i++) { 440 DELAY(1); 441 if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 442 GM_SMI_CT_BUSY) == 0) 443 break; 444 } 445 if (i == MSK_TIMEOUT) 446 if_printf(sc_if->msk_ifp, "phy write timeout\n"); 447 448 return (0); 449 } 450 451 static void 452 msk_miibus_statchg(device_t dev) 453 { 454 struct msk_if_softc *sc_if; 455 456 sc_if = device_get_softc(dev); 457 taskqueue_enqueue(taskqueue_swi, &sc_if->msk_link_task); 458 } 459 460 static void 461 msk_link_task(void *arg, int pending) 462 { 463 struct msk_softc *sc; 464 struct msk_if_softc *sc_if; 465 struct mii_data *mii; 466 struct ifnet *ifp; 467 uint32_t gmac; 468 469 sc_if = (struct msk_if_softc *)arg; 470 sc = sc_if->msk_softc; 471 472 MSK_IF_LOCK(sc_if); 473 474 mii = device_get_softc(sc_if->msk_miibus); 475 ifp = sc_if->msk_ifp; 476 if (mii == NULL || ifp == NULL) { 477 MSK_IF_UNLOCK(sc_if); 478 return; 479 } 480 481 if (mii->mii_media_status & IFM_ACTIVE) { 482 if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 483 sc_if->msk_link = 1; 484 } else 485 sc_if->msk_link = 0; 486 487 if (sc_if->msk_link != 0) { 488 /* Enable Tx FIFO Underrun. */ 489 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 490 GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 491 /* 492 * Because mii(4) notify msk(4) that it detected link status 493 * change, there is no need to enable automatic 494 * speed/flow-control/duplex updates. 495 */ 496 gmac = GM_GPCR_AU_ALL_DIS; 497 switch (IFM_SUBTYPE(mii->mii_media_active)) { 498 case IFM_1000_SX: 499 case IFM_1000_T: 500 gmac |= GM_GPCR_SPEED_1000; 501 break; 502 case IFM_100_TX: 503 gmac |= GM_GPCR_SPEED_100; 504 break; 505 case IFM_10_T: 506 break; 507 } 508 509 if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0) 510 gmac |= GM_GPCR_DUP_FULL; 511 /* Disable Rx flow control. */ 512 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) == 0) 513 gmac |= GM_GPCR_FC_RX_DIS; 514 /* Disable Tx flow control. */ 515 if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) == 0) 516 gmac |= GM_GPCR_FC_TX_DIS; 517 gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 518 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 519 /* Read again to ensure writing. */ 520 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 521 522 gmac = GMC_PAUSE_ON; 523 if (((mii->mii_media_active & IFM_GMASK) & 524 (IFM_FLAG0 | IFM_FLAG1)) == 0) 525 gmac = GMC_PAUSE_OFF; 526 /* Diable pause for 10/100 Mbps in half-duplex mode. */ 527 if ((((mii->mii_media_active & IFM_GMASK) & IFM_FDX) == 0) && 528 (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX || 529 IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)) 530 gmac = GMC_PAUSE_OFF; 531 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 532 533 /* Enable PHY interrupt for FIFO underrun/overflow. */ 534 msk_phy_writereg(sc_if, PHY_ADDR_MARV, 535 PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 536 } else { 537 /* 538 * Link state changed to down. 539 * Disable PHY interrupts. 540 */ 541 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 542 /* Disable Rx/Tx MAC. */ 543 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 544 gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 545 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 546 /* Read again to ensure writing. */ 547 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 548 } 549 550 MSK_IF_UNLOCK(sc_if); 551 } 552 553 static void 554 msk_setmulti(struct msk_if_softc *sc_if) 555 { 556 struct msk_softc *sc; 557 struct ifnet *ifp; 558 struct ifmultiaddr *ifma; 559 uint32_t mchash[2]; 560 uint32_t crc; 561 uint16_t mode; 562 563 sc = sc_if->msk_softc; 564 565 MSK_IF_LOCK_ASSERT(sc_if); 566 567 ifp = sc_if->msk_ifp; 568 569 bzero(mchash, sizeof(mchash)); 570 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 571 mode |= GM_RXCR_UCF_ENA; 572 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 573 if ((ifp->if_flags & IFF_PROMISC) != 0) 574 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 575 else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 576 mchash[0] = 0xffff; 577 mchash[1] = 0xffff; 578 } 579 } else { 580 IF_ADDR_LOCK(ifp); 581 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 582 if (ifma->ifma_addr->sa_family != AF_LINK) 583 continue; 584 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 585 ifma->ifma_addr), ETHER_ADDR_LEN); 586 /* Just want the 6 least significant bits. */ 587 crc &= 0x3f; 588 /* Set the corresponding bit in the hash table. */ 589 mchash[crc >> 5] |= 1 << (crc & 0x1f); 590 } 591 IF_ADDR_UNLOCK(ifp); 592 mode |= GM_RXCR_MCF_ENA; 593 } 594 595 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 596 mchash[0] & 0xffff); 597 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 598 (mchash[0] >> 16) & 0xffff); 599 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 600 mchash[1] & 0xffff); 601 GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 602 (mchash[1] >> 16) & 0xffff); 603 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 604 } 605 606 static void 607 msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 608 { 609 struct msk_softc *sc; 610 611 sc = sc_if->msk_softc; 612 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 613 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 614 RX_VLAN_STRIP_ON); 615 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 616 TX_VLAN_TAG_ON); 617 } else { 618 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 619 RX_VLAN_STRIP_OFF); 620 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 621 TX_VLAN_TAG_OFF); 622 } 623 } 624 625 static void 626 msk_setpromisc(struct msk_if_softc *sc_if) 627 { 628 struct msk_softc *sc; 629 struct ifnet *ifp; 630 uint16_t mode; 631 632 MSK_IF_LOCK_ASSERT(sc_if); 633 634 sc = sc_if->msk_softc; 635 ifp = sc_if->msk_ifp; 636 637 mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 638 if (ifp->if_flags & IFF_PROMISC) 639 mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 640 else 641 mode |= (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 642 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 643 } 644 645 static int 646 msk_init_rx_ring(struct msk_if_softc *sc_if) 647 { 648 struct msk_ring_data *rd; 649 struct msk_rxdesc *rxd; 650 int i, prod; 651 652 MSK_IF_LOCK_ASSERT(sc_if); 653 654 sc_if->msk_cdata.msk_rx_cons = 0; 655 sc_if->msk_cdata.msk_rx_prod = 0; 656 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 657 658 rd = &sc_if->msk_rdata; 659 bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 660 prod = sc_if->msk_cdata.msk_rx_prod; 661 for (i = 0; i < MSK_RX_RING_CNT; i++) { 662 rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 663 rxd->rx_m = NULL; 664 rxd->rx_le = &rd->msk_rx_ring[prod]; 665 if (msk_newbuf(sc_if, prod) != 0) 666 return (ENOBUFS); 667 MSK_INC(prod, MSK_RX_RING_CNT); 668 } 669 670 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 671 sc_if->msk_cdata.msk_rx_ring_map, 672 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 673 674 /* Update prefetch unit. */ 675 sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1; 676 CSR_WRITE_2(sc_if->msk_softc, 677 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 678 sc_if->msk_cdata.msk_rx_prod); 679 680 return (0); 681 } 682 683 static int 684 msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 685 { 686 struct msk_ring_data *rd; 687 struct msk_rxdesc *rxd; 688 int i, prod; 689 690 MSK_IF_LOCK_ASSERT(sc_if); 691 692 sc_if->msk_cdata.msk_rx_cons = 0; 693 sc_if->msk_cdata.msk_rx_prod = 0; 694 sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 695 696 rd = &sc_if->msk_rdata; 697 bzero(rd->msk_jumbo_rx_ring, 698 sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 699 prod = sc_if->msk_cdata.msk_rx_prod; 700 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 701 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 702 rxd->rx_m = NULL; 703 rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 704 if (msk_jumbo_newbuf(sc_if, prod) != 0) 705 return (ENOBUFS); 706 MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 707 } 708 709 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 710 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 711 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 712 713 sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1; 714 CSR_WRITE_2(sc_if->msk_softc, 715 Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 716 sc_if->msk_cdata.msk_rx_prod); 717 718 return (0); 719 } 720 721 static void 722 msk_init_tx_ring(struct msk_if_softc *sc_if) 723 { 724 struct msk_ring_data *rd; 725 struct msk_txdesc *txd; 726 int i; 727 728 sc_if->msk_cdata.msk_tso_mtu = 0; 729 sc_if->msk_cdata.msk_tx_prod = 0; 730 sc_if->msk_cdata.msk_tx_cons = 0; 731 sc_if->msk_cdata.msk_tx_cnt = 0; 732 733 rd = &sc_if->msk_rdata; 734 bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 735 for (i = 0; i < MSK_TX_RING_CNT; i++) { 736 txd = &sc_if->msk_cdata.msk_txdesc[i]; 737 txd->tx_m = NULL; 738 txd->tx_le = &rd->msk_tx_ring[i]; 739 } 740 741 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 742 sc_if->msk_cdata.msk_tx_ring_map, 743 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 744 } 745 746 static __inline void 747 msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 748 { 749 struct msk_rx_desc *rx_le; 750 struct msk_rxdesc *rxd; 751 struct mbuf *m; 752 753 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 754 m = rxd->rx_m; 755 rx_le = rxd->rx_le; 756 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 757 } 758 759 static __inline void 760 msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 761 { 762 struct msk_rx_desc *rx_le; 763 struct msk_rxdesc *rxd; 764 struct mbuf *m; 765 766 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 767 m = rxd->rx_m; 768 rx_le = rxd->rx_le; 769 rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 770 } 771 772 static int 773 msk_newbuf(struct msk_if_softc *sc_if, int idx) 774 { 775 struct msk_rx_desc *rx_le; 776 struct msk_rxdesc *rxd; 777 struct mbuf *m; 778 bus_dma_segment_t segs[1]; 779 bus_dmamap_t map; 780 int nsegs; 781 782 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 783 if (m == NULL) 784 return (ENOBUFS); 785 786 m->m_len = m->m_pkthdr.len = MCLBYTES; 787 m_adj(m, ETHER_ALIGN); 788 789 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 790 sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 791 BUS_DMA_NOWAIT) != 0) { 792 m_freem(m); 793 return (ENOBUFS); 794 } 795 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 796 797 rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 798 if (rxd->rx_m != NULL) { 799 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 800 BUS_DMASYNC_POSTREAD); 801 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 802 } 803 map = rxd->rx_dmamap; 804 rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 805 sc_if->msk_cdata.msk_rx_sparemap = map; 806 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 807 BUS_DMASYNC_PREREAD); 808 rxd->rx_m = m; 809 rx_le = rxd->rx_le; 810 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 811 rx_le->msk_control = 812 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 813 814 return (0); 815 } 816 817 static int 818 msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 819 { 820 struct msk_rx_desc *rx_le; 821 struct msk_rxdesc *rxd; 822 struct mbuf *m; 823 bus_dma_segment_t segs[1]; 824 bus_dmamap_t map; 825 int nsegs; 826 void *buf; 827 828 MGETHDR(m, M_DONTWAIT, MT_DATA); 829 if (m == NULL) 830 return (ENOBUFS); 831 buf = msk_jalloc(sc_if); 832 if (buf == NULL) { 833 m_freem(m); 834 return (ENOBUFS); 835 } 836 /* Attach the buffer to the mbuf. */ 837 MEXTADD(m, buf, MSK_JLEN, msk_jfree, (struct msk_if_softc *)sc_if, 0, 838 EXT_NET_DRV); 839 if ((m->m_flags & M_EXT) == 0) { 840 m_freem(m); 841 return (ENOBUFS); 842 } 843 m->m_pkthdr.len = m->m_len = MSK_JLEN; 844 m_adj(m, ETHER_ALIGN); 845 846 if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 847 sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 848 BUS_DMA_NOWAIT) != 0) { 849 m_freem(m); 850 return (ENOBUFS); 851 } 852 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 853 854 rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 855 if (rxd->rx_m != NULL) { 856 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 857 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 858 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 859 rxd->rx_dmamap); 860 } 861 map = rxd->rx_dmamap; 862 rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 863 sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 864 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 865 BUS_DMASYNC_PREREAD); 866 rxd->rx_m = m; 867 rx_le = rxd->rx_le; 868 rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 869 rx_le->msk_control = 870 htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 871 872 return (0); 873 } 874 875 /* 876 * Set media options. 877 */ 878 static int 879 msk_mediachange(struct ifnet *ifp) 880 { 881 struct msk_if_softc *sc_if; 882 struct mii_data *mii; 883 884 sc_if = ifp->if_softc; 885 886 MSK_IF_LOCK(sc_if); 887 mii = device_get_softc(sc_if->msk_miibus); 888 mii_mediachg(mii); 889 MSK_IF_UNLOCK(sc_if); 890 891 return (0); 892 } 893 894 /* 895 * Report current media status. 896 */ 897 static void 898 msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 899 { 900 struct msk_if_softc *sc_if; 901 struct mii_data *mii; 902 903 sc_if = ifp->if_softc; 904 MSK_IF_LOCK(sc_if); 905 mii = device_get_softc(sc_if->msk_miibus); 906 907 mii_pollstat(mii); 908 MSK_IF_UNLOCK(sc_if); 909 ifmr->ifm_active = mii->mii_media_active; 910 ifmr->ifm_status = mii->mii_media_status; 911 } 912 913 static int 914 msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 915 { 916 struct msk_if_softc *sc_if; 917 struct ifreq *ifr; 918 struct mii_data *mii; 919 int error, mask; 920 921 sc_if = ifp->if_softc; 922 ifr = (struct ifreq *)data; 923 error = 0; 924 925 switch(command) { 926 case SIOCSIFMTU: 927 if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) { 928 error = EINVAL; 929 break; 930 } 931 if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE && 932 ifr->ifr_mtu > MSK_MAX_FRAMELEN) { 933 error = EINVAL; 934 break; 935 } 936 MSK_IF_LOCK(sc_if); 937 ifp->if_mtu = ifr->ifr_mtu; 938 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 939 msk_init_locked(sc_if); 940 MSK_IF_UNLOCK(sc_if); 941 break; 942 case SIOCSIFFLAGS: 943 MSK_IF_LOCK(sc_if); 944 if ((ifp->if_flags & IFF_UP) != 0) { 945 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 946 if (((ifp->if_flags ^ sc_if->msk_if_flags) 947 & IFF_PROMISC) != 0) { 948 msk_setpromisc(sc_if); 949 msk_setmulti(sc_if); 950 } 951 } else { 952 if (sc_if->msk_detach == 0) 953 msk_init_locked(sc_if); 954 } 955 } else { 956 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 957 msk_stop(sc_if); 958 } 959 sc_if->msk_if_flags = ifp->if_flags; 960 MSK_IF_UNLOCK(sc_if); 961 break; 962 case SIOCADDMULTI: 963 case SIOCDELMULTI: 964 MSK_IF_LOCK(sc_if); 965 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 966 msk_setmulti(sc_if); 967 MSK_IF_UNLOCK(sc_if); 968 break; 969 case SIOCGIFMEDIA: 970 case SIOCSIFMEDIA: 971 mii = device_get_softc(sc_if->msk_miibus); 972 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 973 break; 974 case SIOCSIFCAP: 975 MSK_IF_LOCK(sc_if); 976 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 977 if ((mask & IFCAP_TXCSUM) != 0) { 978 ifp->if_capenable ^= IFCAP_TXCSUM; 979 if ((IFCAP_TXCSUM & ifp->if_capenable) != 0 && 980 (IFCAP_TXCSUM & ifp->if_capabilities) != 0) 981 ifp->if_hwassist |= MSK_CSUM_FEATURES; 982 else 983 ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 984 } 985 if ((mask & IFCAP_VLAN_HWTAGGING) != 0) { 986 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 987 msk_setvlan(sc_if, ifp); 988 } 989 990 if ((mask & IFCAP_TSO4) != 0) { 991 ifp->if_capenable ^= IFCAP_TSO4; 992 if ((IFCAP_TSO4 & ifp->if_capenable) != 0 && 993 (IFCAP_TSO4 & ifp->if_capabilities) != 0) 994 ifp->if_hwassist |= CSUM_TSO; 995 else 996 ifp->if_hwassist &= ~CSUM_TSO; 997 } 998 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN && 999 sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 1000 /* 1001 * In Yukon EC Ultra, TSO & checksum offload is not 1002 * supported for jumbo frame. 1003 */ 1004 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 1005 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1006 } 1007 1008 VLAN_CAPABILITIES(ifp); 1009 MSK_IF_UNLOCK(sc_if); 1010 break; 1011 default: 1012 error = ether_ioctl(ifp, command, data); 1013 break; 1014 } 1015 1016 return (error); 1017 } 1018 1019 static int 1020 mskc_probe(device_t dev) 1021 { 1022 struct msk_product *mp; 1023 uint16_t vendor, devid; 1024 int i; 1025 1026 vendor = pci_get_vendor(dev); 1027 devid = pci_get_device(dev); 1028 mp = msk_products; 1029 for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]); 1030 i++, mp++) { 1031 if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 1032 device_set_desc(dev, mp->msk_name); 1033 return (BUS_PROBE_DEFAULT); 1034 } 1035 } 1036 1037 return (ENXIO); 1038 } 1039 1040 static int 1041 mskc_setup_rambuffer(struct msk_softc *sc) 1042 { 1043 int next; 1044 int i; 1045 uint8_t val; 1046 1047 /* Get adapter SRAM size. */ 1048 val = CSR_READ_1(sc, B2_E_0); 1049 sc->msk_ramsize = (val == 0) ? 128 : val * 4; 1050 if (bootverbose) 1051 device_printf(sc->msk_dev, 1052 "RAM buffer size : %dKB\n", sc->msk_ramsize); 1053 /* 1054 * Give receiver 2/3 of memory and round down to the multiple 1055 * of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple 1056 * of 1024. 1057 */ 1058 sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1059 sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 1060 for (i = 0, next = 0; i < sc->msk_num_port; i++) { 1061 sc->msk_rxqstart[i] = next; 1062 sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 1063 next = sc->msk_rxqend[i] + 1; 1064 sc->msk_txqstart[i] = next; 1065 sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 1066 next = sc->msk_txqend[i] + 1; 1067 if (bootverbose) { 1068 device_printf(sc->msk_dev, 1069 "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1070 sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 1071 sc->msk_rxqend[i]); 1072 device_printf(sc->msk_dev, 1073 "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1074 sc->msk_txqsize / 1024, sc->msk_txqstart[i], 1075 sc->msk_txqend[i]); 1076 } 1077 } 1078 1079 return (0); 1080 } 1081 1082 static void 1083 msk_phy_power(struct msk_softc *sc, int mode) 1084 { 1085 uint32_t val; 1086 int i; 1087 1088 switch (mode) { 1089 case MSK_PHY_POWERUP: 1090 /* Switch power to VCC (WA for VAUX problem). */ 1091 CSR_WRITE_1(sc, B0_POWER_CTRL, 1092 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 1093 /* Disable Core Clock Division, set Clock Select to 0. */ 1094 CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 1095 1096 val = 0; 1097 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1098 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1099 /* Enable bits are inverted. */ 1100 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1101 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1102 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1103 } 1104 /* 1105 * Enable PCI & Core Clock, enable clock gating for both Links. 1106 */ 1107 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1108 1109 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1110 val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 1111 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1112 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1113 /* Deassert Low Power for 1st PHY. */ 1114 val |= PCI_Y2_PHY1_COMA; 1115 if (sc->msk_num_port > 1) 1116 val |= PCI_Y2_PHY2_COMA; 1117 } else if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 1118 uint32_t our; 1119 1120 CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); 1121 1122 /* Enable all clocks. */ 1123 pci_write_config(sc->msk_dev, PCI_OUR_REG_3, 0, 4); 1124 our = pci_read_config(sc->msk_dev, PCI_OUR_REG_4, 4); 1125 our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN| 1126 PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST); 1127 /* Set all bits to 0 except bits 15..12. */ 1128 pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4); 1129 /* Set to default value. */ 1130 pci_write_config(sc->msk_dev, PCI_OUR_REG_5, 0, 4); 1131 } 1132 /* Release PHY from PowerDown/COMA mode. */ 1133 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1134 for (i = 0; i < sc->msk_num_port; i++) { 1135 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1136 GMLC_RST_SET); 1137 CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 1138 GMLC_RST_CLR); 1139 } 1140 break; 1141 case MSK_PHY_POWERDOWN: 1142 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1143 val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 1144 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1145 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1146 val &= ~PCI_Y2_PHY1_COMA; 1147 if (sc->msk_num_port > 1) 1148 val &= ~PCI_Y2_PHY2_COMA; 1149 } 1150 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1151 1152 val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 1153 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 1154 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 1155 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1156 sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 1157 /* Enable bits are inverted. */ 1158 val = 0; 1159 } 1160 /* 1161 * Disable PCI & Core Clock, disable clock gating for 1162 * both Links. 1163 */ 1164 CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 1165 CSR_WRITE_1(sc, B0_POWER_CTRL, 1166 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 1167 break; 1168 default: 1169 break; 1170 } 1171 } 1172 1173 static void 1174 mskc_reset(struct msk_softc *sc) 1175 { 1176 bus_addr_t addr; 1177 uint16_t status; 1178 uint32_t val; 1179 int i; 1180 1181 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1182 1183 /* Disable ASF. */ 1184 if (sc->msk_hw_id < CHIP_ID_YUKON_XL) { 1185 CSR_WRITE_4(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 1186 CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 1187 } 1188 /* 1189 * Since we disabled ASF, S/W reset is required for Power Management. 1190 */ 1191 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1192 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1193 1194 /* Clear all error bits in the PCI status register. */ 1195 status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 1196 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1197 1198 pci_write_config(sc->msk_dev, PCIR_STATUS, status | 1199 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 1200 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 1201 CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 1202 1203 switch (sc->msk_bustype) { 1204 case MSK_PEX_BUS: 1205 /* Clear all PEX errors. */ 1206 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 1207 val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 1208 if ((val & PEX_RX_OV) != 0) { 1209 sc->msk_intrmask &= ~Y2_IS_HW_ERR; 1210 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 1211 } 1212 break; 1213 case MSK_PCI_BUS: 1214 case MSK_PCIX_BUS: 1215 /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 1216 val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 1217 if (val == 0) 1218 pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 1219 if (sc->msk_bustype == MSK_PCIX_BUS) { 1220 /* Set Cache Line Size opt. */ 1221 val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 1222 val |= PCI_CLS_OPT; 1223 pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 1224 } 1225 break; 1226 } 1227 /* Set PHY power state. */ 1228 msk_phy_power(sc, MSK_PHY_POWERUP); 1229 1230 /* Reset GPHY/GMAC Control */ 1231 for (i = 0; i < sc->msk_num_port; i++) { 1232 /* GPHY Control reset. */ 1233 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 1234 CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 1235 /* GMAC Control reset. */ 1236 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 1237 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 1238 CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 1239 } 1240 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1241 1242 /* LED On. */ 1243 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 1244 1245 /* Clear TWSI IRQ. */ 1246 CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 1247 1248 /* Turn off hardware timer. */ 1249 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 1250 CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 1251 1252 /* Turn off descriptor polling. */ 1253 CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 1254 1255 /* Turn off time stamps. */ 1256 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 1257 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 1258 1259 /* Configure timeout values. */ 1260 for (i = 0; i < sc->msk_num_port; i++) { 1261 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 1262 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 1263 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 1264 MSK_RI_TO_53); 1265 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 1266 MSK_RI_TO_53); 1267 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 1268 MSK_RI_TO_53); 1269 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 1270 MSK_RI_TO_53); 1271 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 1272 MSK_RI_TO_53); 1273 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 1274 MSK_RI_TO_53); 1275 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 1276 MSK_RI_TO_53); 1277 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 1278 MSK_RI_TO_53); 1279 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 1280 MSK_RI_TO_53); 1281 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 1282 MSK_RI_TO_53); 1283 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 1284 MSK_RI_TO_53); 1285 CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 1286 MSK_RI_TO_53); 1287 } 1288 1289 /* Disable all interrupts. */ 1290 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1291 CSR_READ_4(sc, B0_HWE_IMSK); 1292 CSR_WRITE_4(sc, B0_IMSK, 0); 1293 CSR_READ_4(sc, B0_IMSK); 1294 1295 /* 1296 * On dual port PCI-X card, there is an problem where status 1297 * can be received out of order due to split transactions. 1298 */ 1299 if (sc->msk_bustype == MSK_PCIX_BUS && sc->msk_num_port > 1) { 1300 int pcix; 1301 uint16_t pcix_cmd; 1302 1303 if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, &pcix) == 0) { 1304 pcix_cmd = pci_read_config(sc->msk_dev, pcix + 2, 2); 1305 /* Clear Max Outstanding Split Transactions. */ 1306 pcix_cmd &= ~0x70; 1307 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 1308 pci_write_config(sc->msk_dev, pcix + 2, pcix_cmd, 2); 1309 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 1310 } 1311 } 1312 if (sc->msk_bustype == MSK_PEX_BUS) { 1313 uint16_t v, width; 1314 1315 v = pci_read_config(sc->msk_dev, PEX_DEV_CTRL, 2); 1316 /* Change Max. Read Request Size to 4096 bytes. */ 1317 v &= ~PEX_DC_MAX_RRS_MSK; 1318 v |= PEX_DC_MAX_RD_RQ_SIZE(5); 1319 pci_write_config(sc->msk_dev, PEX_DEV_CTRL, v, 2); 1320 width = pci_read_config(sc->msk_dev, PEX_LNK_STAT, 2); 1321 width = (width & PEX_LS_LINK_WI_MSK) >> 4; 1322 v = pci_read_config(sc->msk_dev, PEX_LNK_CAP, 2); 1323 v = (v & PEX_LS_LINK_WI_MSK) >> 4; 1324 if (v != width) 1325 device_printf(sc->msk_dev, 1326 "negotiated width of link(x%d) != " 1327 "max. width of link(x%d)\n", width, v); 1328 } 1329 1330 /* Clear status list. */ 1331 bzero(sc->msk_stat_ring, 1332 sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT); 1333 sc->msk_stat_cons = 0; 1334 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 1335 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1336 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 1337 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 1338 /* Set the status list base address. */ 1339 addr = sc->msk_stat_ring_paddr; 1340 CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 1341 CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 1342 /* Set the status list last index. */ 1343 CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1); 1344 if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1345 sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 1346 /* WA for dev. #4.3 */ 1347 CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 1348 /* WA for dev. #4.18 */ 1349 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 1350 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 1351 } else { 1352 CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 1353 CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1354 if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1355 sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1356 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1357 else 1358 CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 1359 CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 1360 } 1361 /* 1362 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 1363 */ 1364 CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 1365 1366 /* Enable status unit. */ 1367 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 1368 1369 CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 1370 CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 1371 CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 1372 } 1373 1374 static int 1375 msk_probe(device_t dev) 1376 { 1377 struct msk_softc *sc; 1378 char desc[100]; 1379 1380 sc = device_get_softc(device_get_parent(dev)); 1381 /* 1382 * Not much to do here. We always know there will be 1383 * at least one GMAC present, and if there are two, 1384 * mskc_attach() will create a second device instance 1385 * for us. 1386 */ 1387 snprintf(desc, sizeof(desc), 1388 "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 1389 model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 1390 sc->msk_hw_rev); 1391 device_set_desc_copy(dev, desc); 1392 1393 return (BUS_PROBE_DEFAULT); 1394 } 1395 1396 static int 1397 msk_attach(device_t dev) 1398 { 1399 struct msk_softc *sc; 1400 struct msk_if_softc *sc_if; 1401 struct ifnet *ifp; 1402 int i, port, error; 1403 uint8_t eaddr[6]; 1404 1405 if (dev == NULL) 1406 return (EINVAL); 1407 1408 error = 0; 1409 sc_if = device_get_softc(dev); 1410 sc = device_get_softc(device_get_parent(dev)); 1411 port = *(int *)device_get_ivars(dev); 1412 1413 sc_if->msk_if_dev = dev; 1414 sc_if->msk_port = port; 1415 sc_if->msk_softc = sc; 1416 sc->msk_if[port] = sc_if; 1417 /* Setup Tx/Rx queue register offsets. */ 1418 if (port == MSK_PORT_A) { 1419 sc_if->msk_txq = Q_XA1; 1420 sc_if->msk_txsq = Q_XS1; 1421 sc_if->msk_rxq = Q_R1; 1422 } else { 1423 sc_if->msk_txq = Q_XA2; 1424 sc_if->msk_txsq = Q_XS2; 1425 sc_if->msk_rxq = Q_R2; 1426 } 1427 1428 callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 1429 TASK_INIT(&sc_if->msk_link_task, 0, msk_link_task, sc_if); 1430 1431 if ((error = msk_txrx_dma_alloc(sc_if) != 0)) 1432 goto fail; 1433 1434 ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 1435 if (ifp == NULL) { 1436 device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 1437 error = ENOSPC; 1438 goto fail; 1439 } 1440 ifp->if_softc = sc_if; 1441 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1442 ifp->if_mtu = ETHERMTU; 1443 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1444 /* 1445 * IFCAP_RXCSUM capability is intentionally disabled as the hardware 1446 * has serious bug in Rx checksum offload for all Yukon II family 1447 * hardware. It seems there is a workaround to make it work somtimes. 1448 * However, the workaround also have to check OP code sequences to 1449 * verify whether the OP code is correct. Sometimes it should compute 1450 * IP/TCP/UDP checksum in driver in order to verify correctness of 1451 * checksum computed by hardware. If you have to compute checksum 1452 * with software to verify the hardware's checksum why have hardware 1453 * compute the checksum? I think there is no reason to spend time to 1454 * make Rx checksum offload work on Yukon II hardware. 1455 */ 1456 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1457 ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO; 1458 ifp->if_capenable = ifp->if_capabilities; 1459 ifp->if_ioctl = msk_ioctl; 1460 ifp->if_start = msk_start; 1461 ifp->if_timer = 0; 1462 ifp->if_watchdog = NULL; 1463 ifp->if_init = msk_init; 1464 IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 1465 ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1; 1466 IFQ_SET_READY(&ifp->if_snd); 1467 1468 TASK_INIT(&sc_if->msk_tx_task, 1, msk_tx_task, ifp); 1469 1470 /* 1471 * Get station address for this interface. Note that 1472 * dual port cards actually come with three station 1473 * addresses: one for each port, plus an extra. The 1474 * extra one is used by the SysKonnect driver software 1475 * as a 'virtual' station address for when both ports 1476 * are operating in failover mode. Currently we don't 1477 * use this extra address. 1478 */ 1479 MSK_IF_LOCK(sc_if); 1480 for (i = 0; i < ETHER_ADDR_LEN; i++) 1481 eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 1482 1483 /* 1484 * Call MI attach routine. Can't hold locks when calling into ether_*. 1485 */ 1486 MSK_IF_UNLOCK(sc_if); 1487 ether_ifattach(ifp, eaddr); 1488 MSK_IF_LOCK(sc_if); 1489 1490 /* VLAN capability setup */ 1491 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1492 if (ifp->if_capabilities & IFCAP_HWCSUM) 1493 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1494 ifp->if_capenable = ifp->if_capabilities; 1495 1496 /* 1497 * Tell the upper layer(s) we support long frames. 1498 * Must appear after the call to ether_ifattach() because 1499 * ether_ifattach() sets ifi_hdrlen to the default value. 1500 */ 1501 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1502 1503 sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN + 1504 ETHER_VLAN_ENCAP_LEN; 1505 1506 /* 1507 * Do miibus setup. 1508 */ 1509 MSK_IF_UNLOCK(sc_if); 1510 error = mii_phy_probe(dev, &sc_if->msk_miibus, msk_mediachange, 1511 msk_mediastatus); 1512 if (error != 0) { 1513 device_printf(sc_if->msk_if_dev, "no PHY found!\n"); 1514 ether_ifdetach(ifp); 1515 error = ENXIO; 1516 goto fail; 1517 } 1518 1519 fail: 1520 if (error != 0) { 1521 /* Access should be ok even though lock has been dropped */ 1522 sc->msk_if[port] = NULL; 1523 msk_detach(dev); 1524 } 1525 1526 return (error); 1527 } 1528 1529 /* 1530 * Attach the interface. Allocate softc structures, do ifmedia 1531 * setup and ethernet/BPF attach. 1532 */ 1533 static int 1534 mskc_attach(device_t dev) 1535 { 1536 struct msk_softc *sc; 1537 int error, msic, msir, *port, reg; 1538 1539 sc = device_get_softc(dev); 1540 sc->msk_dev = dev; 1541 mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1542 MTX_DEF); 1543 1544 /* 1545 * Map control/status registers. 1546 */ 1547 pci_enable_busmaster(dev); 1548 1549 /* Allocate I/O resource */ 1550 #ifdef MSK_USEIOSPACE 1551 sc->msk_res_spec = msk_res_spec_io; 1552 #else 1553 sc->msk_res_spec = msk_res_spec_mem; 1554 #endif 1555 sc->msk_irq_spec = msk_irq_spec_legacy; 1556 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1557 if (error) { 1558 if (sc->msk_res_spec == msk_res_spec_mem) 1559 sc->msk_res_spec = msk_res_spec_io; 1560 else 1561 sc->msk_res_spec = msk_res_spec_mem; 1562 error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 1563 if (error) { 1564 device_printf(dev, "couldn't allocate %s resources\n", 1565 sc->msk_res_spec == msk_res_spec_mem ? "memory" : 1566 "I/O"); 1567 mtx_destroy(&sc->msk_mtx); 1568 return (ENXIO); 1569 } 1570 } 1571 1572 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1573 sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 1574 sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 1575 /* Bail out if chip is not recognized. */ 1576 if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 1577 sc->msk_hw_id > CHIP_ID_YUKON_FE) { 1578 device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 1579 sc->msk_hw_id, sc->msk_hw_rev); 1580 mtx_destroy(&sc->msk_mtx); 1581 return (ENXIO); 1582 } 1583 1584 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 1585 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 1586 OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 1587 &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 1588 "max number of Rx events to process"); 1589 1590 sc->msk_process_limit = MSK_PROC_DEFAULT; 1591 error = resource_int_value(device_get_name(dev), device_get_unit(dev), 1592 "process_limit", &sc->msk_process_limit); 1593 if (error == 0) { 1594 if (sc->msk_process_limit < MSK_PROC_MIN || 1595 sc->msk_process_limit > MSK_PROC_MAX) { 1596 device_printf(dev, "process_limit value out of range; " 1597 "using default: %d\n", MSK_PROC_DEFAULT); 1598 sc->msk_process_limit = MSK_PROC_DEFAULT; 1599 } 1600 } 1601 1602 /* Soft reset. */ 1603 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1604 CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 1605 sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 1606 if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 1607 sc->msk_coppertype = 0; 1608 else 1609 sc->msk_coppertype = 1; 1610 /* Check number of MACs. */ 1611 sc->msk_num_port = 1; 1612 if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 1613 CFG_DUAL_MAC_MSK) { 1614 if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 1615 sc->msk_num_port++; 1616 } 1617 1618 /* Check bus type. */ 1619 if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) 1620 sc->msk_bustype = MSK_PEX_BUS; 1621 else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0) 1622 sc->msk_bustype = MSK_PCIX_BUS; 1623 else 1624 sc->msk_bustype = MSK_PCI_BUS; 1625 1626 switch (sc->msk_hw_id) { 1627 case CHIP_ID_YUKON_EC: 1628 case CHIP_ID_YUKON_EC_U: 1629 sc->msk_clock = 125; /* 125 Mhz */ 1630 break; 1631 case CHIP_ID_YUKON_FE: 1632 sc->msk_clock = 100; /* 100 Mhz */ 1633 break; 1634 case CHIP_ID_YUKON_XL: 1635 sc->msk_clock = 156; /* 156 Mhz */ 1636 break; 1637 default: 1638 sc->msk_clock = 156; /* 156 Mhz */ 1639 break; 1640 } 1641 1642 /* Allocate IRQ resources. */ 1643 msic = pci_msi_count(dev); 1644 if (bootverbose) 1645 device_printf(dev, "MSI count : %d\n", msic); 1646 /* 1647 * The Yukon II reports it can handle two messages, one for each 1648 * possible port. We go ahead and allocate two messages and only 1649 * setup a handler for both if we have a dual port card. 1650 * 1651 * XXX: I haven't untangled the interrupt handler to handle dual 1652 * port cards with separate MSI messages, so for now I disable MSI 1653 * on dual port cards. 1654 */ 1655 if (legacy_intr != 0) 1656 msi_disable = 1; 1657 if (msi_disable == 0) { 1658 switch (msic) { 1659 case 2: 1660 case 1: /* 88E8058 reports 1 MSI message */ 1661 msir = msic; 1662 if (sc->msk_num_port == 1 && 1663 pci_alloc_msi(dev, &msir) == 0) { 1664 if (msic == msir) { 1665 sc->msk_msi = 1; 1666 sc->msk_irq_spec = msic == 2 ? 1667 msk_irq_spec_msi2 : 1668 msk_irq_spec_msi; 1669 } else 1670 pci_release_msi(dev); 1671 } 1672 break; 1673 default: 1674 device_printf(dev, 1675 "Unexpected number of MSI messages : %d\n", msic); 1676 break; 1677 } 1678 } 1679 1680 error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1681 if (error) { 1682 device_printf(dev, "couldn't allocate IRQ resources\n"); 1683 goto fail; 1684 } 1685 1686 if ((error = msk_status_dma_alloc(sc)) != 0) 1687 goto fail; 1688 1689 /* Set base interrupt mask. */ 1690 sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 1691 sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 1692 Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 1693 1694 /* Reset the adapter. */ 1695 mskc_reset(sc); 1696 1697 if ((error = mskc_setup_rambuffer(sc)) != 0) 1698 goto fail; 1699 1700 sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 1701 if (sc->msk_devs[MSK_PORT_A] == NULL) { 1702 device_printf(dev, "failed to add child for PORT_A\n"); 1703 error = ENXIO; 1704 goto fail; 1705 } 1706 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1707 if (port == NULL) { 1708 device_printf(dev, "failed to allocate memory for " 1709 "ivars of PORT_A\n"); 1710 error = ENXIO; 1711 goto fail; 1712 } 1713 *port = MSK_PORT_A; 1714 device_set_ivars(sc->msk_devs[MSK_PORT_A], port); 1715 1716 if (sc->msk_num_port > 1) { 1717 sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 1718 if (sc->msk_devs[MSK_PORT_B] == NULL) { 1719 device_printf(dev, "failed to add child for PORT_B\n"); 1720 error = ENXIO; 1721 goto fail; 1722 } 1723 port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 1724 if (port == NULL) { 1725 device_printf(dev, "failed to allocate memory for " 1726 "ivars of PORT_B\n"); 1727 error = ENXIO; 1728 goto fail; 1729 } 1730 *port = MSK_PORT_B; 1731 device_set_ivars(sc->msk_devs[MSK_PORT_B], port); 1732 } 1733 1734 error = bus_generic_attach(dev); 1735 if (error) { 1736 device_printf(dev, "failed to attach port(s)\n"); 1737 goto fail; 1738 } 1739 1740 /* Hook interrupt last to avoid having to lock softc. */ 1741 if (legacy_intr) 1742 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1743 INTR_MPSAFE, NULL, msk_legacy_intr, sc, 1744 &sc->msk_intrhand[0]); 1745 else { 1746 TASK_INIT(&sc->msk_int_task, 0, msk_int_task, sc); 1747 sc->msk_tq = taskqueue_create_fast("msk_taskq", M_WAITOK, 1748 taskqueue_thread_enqueue, &sc->msk_tq); 1749 taskqueue_start_threads(&sc->msk_tq, 1, PI_NET, "%s taskq", 1750 device_get_nameunit(sc->msk_dev)); 1751 error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1752 INTR_MPSAFE, msk_intr, NULL, sc, &sc->msk_intrhand[0]); 1753 } 1754 1755 if (error != 0) { 1756 device_printf(dev, "couldn't set up interrupt handler\n"); 1757 if (legacy_intr == 0) 1758 taskqueue_free(sc->msk_tq); 1759 sc->msk_tq = NULL; 1760 goto fail; 1761 } 1762 fail: 1763 if (error != 0) 1764 mskc_detach(dev); 1765 1766 return (error); 1767 } 1768 1769 /* 1770 * Shutdown hardware and free up resources. This can be called any 1771 * time after the mutex has been initialized. It is called in both 1772 * the error case in attach and the normal detach case so it needs 1773 * to be careful about only freeing resources that have actually been 1774 * allocated. 1775 */ 1776 static int 1777 msk_detach(device_t dev) 1778 { 1779 struct msk_softc *sc; 1780 struct msk_if_softc *sc_if; 1781 struct ifnet *ifp; 1782 1783 sc_if = device_get_softc(dev); 1784 KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 1785 ("msk mutex not initialized in msk_detach")); 1786 MSK_IF_LOCK(sc_if); 1787 1788 ifp = sc_if->msk_ifp; 1789 if (device_is_attached(dev)) { 1790 /* XXX */ 1791 sc_if->msk_detach = 1; 1792 msk_stop(sc_if); 1793 /* Can't hold locks while calling detach. */ 1794 MSK_IF_UNLOCK(sc_if); 1795 callout_drain(&sc_if->msk_tick_ch); 1796 taskqueue_drain(taskqueue_fast, &sc_if->msk_tx_task); 1797 taskqueue_drain(taskqueue_swi, &sc_if->msk_link_task); 1798 ether_ifdetach(ifp); 1799 MSK_IF_LOCK(sc_if); 1800 } 1801 1802 /* 1803 * We're generally called from mskc_detach() which is using 1804 * device_delete_child() to get to here. It's already trashed 1805 * miibus for us, so don't do it here or we'll panic. 1806 * 1807 * if (sc_if->msk_miibus != NULL) { 1808 * device_delete_child(dev, sc_if->msk_miibus); 1809 * sc_if->msk_miibus = NULL; 1810 * } 1811 */ 1812 1813 msk_txrx_dma_free(sc_if); 1814 bus_generic_detach(dev); 1815 1816 if (ifp) 1817 if_free(ifp); 1818 sc = sc_if->msk_softc; 1819 sc->msk_if[sc_if->msk_port] = NULL; 1820 MSK_IF_UNLOCK(sc_if); 1821 1822 return (0); 1823 } 1824 1825 static int 1826 mskc_detach(device_t dev) 1827 { 1828 struct msk_softc *sc; 1829 1830 sc = device_get_softc(dev); 1831 KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 1832 1833 if (device_is_alive(dev)) { 1834 if (sc->msk_devs[MSK_PORT_A] != NULL) { 1835 free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 1836 M_DEVBUF); 1837 device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 1838 } 1839 if (sc->msk_devs[MSK_PORT_B] != NULL) { 1840 free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 1841 M_DEVBUF); 1842 device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 1843 } 1844 bus_generic_detach(dev); 1845 } 1846 1847 /* Disable all interrupts. */ 1848 CSR_WRITE_4(sc, B0_IMSK, 0); 1849 CSR_READ_4(sc, B0_IMSK); 1850 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 1851 CSR_READ_4(sc, B0_HWE_IMSK); 1852 1853 /* LED Off. */ 1854 CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 1855 1856 /* Put hardware reset. */ 1857 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 1858 1859 msk_status_dma_free(sc); 1860 1861 if (legacy_intr == 0 && sc->msk_tq != NULL) { 1862 taskqueue_drain(sc->msk_tq, &sc->msk_int_task); 1863 taskqueue_free(sc->msk_tq); 1864 sc->msk_tq = NULL; 1865 } 1866 if (sc->msk_intrhand[0]) { 1867 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]); 1868 sc->msk_intrhand[0] = NULL; 1869 } 1870 if (sc->msk_intrhand[1]) { 1871 bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]); 1872 sc->msk_intrhand[1] = NULL; 1873 } 1874 bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1875 if (sc->msk_msi) 1876 pci_release_msi(dev); 1877 bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 1878 mtx_destroy(&sc->msk_mtx); 1879 1880 return (0); 1881 } 1882 1883 struct msk_dmamap_arg { 1884 bus_addr_t msk_busaddr; 1885 }; 1886 1887 static void 1888 msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1889 { 1890 struct msk_dmamap_arg *ctx; 1891 1892 if (error != 0) 1893 return; 1894 ctx = arg; 1895 ctx->msk_busaddr = segs[0].ds_addr; 1896 } 1897 1898 /* Create status DMA region. */ 1899 static int 1900 msk_status_dma_alloc(struct msk_softc *sc) 1901 { 1902 struct msk_dmamap_arg ctx; 1903 int error; 1904 1905 error = bus_dma_tag_create( 1906 bus_get_dma_tag(sc->msk_dev), /* parent */ 1907 MSK_STAT_ALIGN, 0, /* alignment, boundary */ 1908 BUS_SPACE_MAXADDR, /* lowaddr */ 1909 BUS_SPACE_MAXADDR, /* highaddr */ 1910 NULL, NULL, /* filter, filterarg */ 1911 MSK_STAT_RING_SZ, /* maxsize */ 1912 1, /* nsegments */ 1913 MSK_STAT_RING_SZ, /* maxsegsize */ 1914 0, /* flags */ 1915 NULL, NULL, /* lockfunc, lockarg */ 1916 &sc->msk_stat_tag); 1917 if (error != 0) { 1918 device_printf(sc->msk_dev, 1919 "failed to create status DMA tag\n"); 1920 return (error); 1921 } 1922 1923 /* Allocate DMA'able memory and load the DMA map for status ring. */ 1924 error = bus_dmamem_alloc(sc->msk_stat_tag, 1925 (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 1926 BUS_DMA_ZERO, &sc->msk_stat_map); 1927 if (error != 0) { 1928 device_printf(sc->msk_dev, 1929 "failed to allocate DMA'able memory for status ring\n"); 1930 return (error); 1931 } 1932 1933 ctx.msk_busaddr = 0; 1934 error = bus_dmamap_load(sc->msk_stat_tag, 1935 sc->msk_stat_map, sc->msk_stat_ring, MSK_STAT_RING_SZ, 1936 msk_dmamap_cb, &ctx, 0); 1937 if (error != 0) { 1938 device_printf(sc->msk_dev, 1939 "failed to load DMA'able memory for status ring\n"); 1940 return (error); 1941 } 1942 sc->msk_stat_ring_paddr = ctx.msk_busaddr; 1943 1944 return (0); 1945 } 1946 1947 static void 1948 msk_status_dma_free(struct msk_softc *sc) 1949 { 1950 1951 /* Destroy status block. */ 1952 if (sc->msk_stat_tag) { 1953 if (sc->msk_stat_map) { 1954 bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 1955 if (sc->msk_stat_ring) { 1956 bus_dmamem_free(sc->msk_stat_tag, 1957 sc->msk_stat_ring, sc->msk_stat_map); 1958 sc->msk_stat_ring = NULL; 1959 } 1960 sc->msk_stat_map = NULL; 1961 } 1962 bus_dma_tag_destroy(sc->msk_stat_tag); 1963 sc->msk_stat_tag = NULL; 1964 } 1965 } 1966 1967 static int 1968 msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 1969 { 1970 struct msk_dmamap_arg ctx; 1971 struct msk_txdesc *txd; 1972 struct msk_rxdesc *rxd; 1973 struct msk_rxdesc *jrxd; 1974 struct msk_jpool_entry *entry; 1975 uint8_t *ptr; 1976 int error, i; 1977 1978 mtx_init(&sc_if->msk_jlist_mtx, "msk_jlist_mtx", NULL, MTX_DEF); 1979 SLIST_INIT(&sc_if->msk_jfree_listhead); 1980 SLIST_INIT(&sc_if->msk_jinuse_listhead); 1981 1982 /* Create parent DMA tag. */ 1983 /* 1984 * XXX 1985 * It seems that Yukon II supports full 64bits DMA operations. But 1986 * it needs two descriptors(list elements) for 64bits DMA operations. 1987 * Since we don't know what DMA address mappings(32bits or 64bits) 1988 * would be used in advance for each mbufs, we limits its DMA space 1989 * to be in range of 32bits address space. Otherwise, we should check 1990 * what DMA address is used and chain another descriptor for the 1991 * 64bits DMA operation. This also means descriptor ring size is 1992 * variable. Limiting DMA address to be in 32bit address space greatly 1993 * simplyfies descriptor handling and possibly would increase 1994 * performance a bit due to efficient handling of descriptors. 1995 * Apart from harassing checksum offloading mechanisms, it seems 1996 * it's really bad idea to use a seperate descriptor for 64bit 1997 * DMA operation to save small descriptor memory. Anyway, I've 1998 * never seen these exotic scheme on ethernet interface hardware. 1999 */ 2000 error = bus_dma_tag_create( 2001 bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 2002 1, 0, /* alignment, boundary */ 2003 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2004 BUS_SPACE_MAXADDR, /* highaddr */ 2005 NULL, NULL, /* filter, filterarg */ 2006 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2007 0, /* nsegments */ 2008 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2009 0, /* flags */ 2010 NULL, NULL, /* lockfunc, lockarg */ 2011 &sc_if->msk_cdata.msk_parent_tag); 2012 if (error != 0) { 2013 device_printf(sc_if->msk_if_dev, 2014 "failed to create parent DMA tag\n"); 2015 goto fail; 2016 } 2017 /* Create tag for Tx ring. */ 2018 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2019 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2020 BUS_SPACE_MAXADDR, /* lowaddr */ 2021 BUS_SPACE_MAXADDR, /* highaddr */ 2022 NULL, NULL, /* filter, filterarg */ 2023 MSK_TX_RING_SZ, /* maxsize */ 2024 1, /* nsegments */ 2025 MSK_TX_RING_SZ, /* maxsegsize */ 2026 0, /* flags */ 2027 NULL, NULL, /* lockfunc, lockarg */ 2028 &sc_if->msk_cdata.msk_tx_ring_tag); 2029 if (error != 0) { 2030 device_printf(sc_if->msk_if_dev, 2031 "failed to create Tx ring DMA tag\n"); 2032 goto fail; 2033 } 2034 2035 /* Create tag for Rx ring. */ 2036 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2037 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2038 BUS_SPACE_MAXADDR, /* lowaddr */ 2039 BUS_SPACE_MAXADDR, /* highaddr */ 2040 NULL, NULL, /* filter, filterarg */ 2041 MSK_RX_RING_SZ, /* maxsize */ 2042 1, /* nsegments */ 2043 MSK_RX_RING_SZ, /* maxsegsize */ 2044 0, /* flags */ 2045 NULL, NULL, /* lockfunc, lockarg */ 2046 &sc_if->msk_cdata.msk_rx_ring_tag); 2047 if (error != 0) { 2048 device_printf(sc_if->msk_if_dev, 2049 "failed to create Rx ring DMA tag\n"); 2050 goto fail; 2051 } 2052 2053 /* Create tag for jumbo Rx ring. */ 2054 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2055 MSK_RING_ALIGN, 0, /* alignment, boundary */ 2056 BUS_SPACE_MAXADDR, /* lowaddr */ 2057 BUS_SPACE_MAXADDR, /* highaddr */ 2058 NULL, NULL, /* filter, filterarg */ 2059 MSK_JUMBO_RX_RING_SZ, /* maxsize */ 2060 1, /* nsegments */ 2061 MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 2062 0, /* flags */ 2063 NULL, NULL, /* lockfunc, lockarg */ 2064 &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2065 if (error != 0) { 2066 device_printf(sc_if->msk_if_dev, 2067 "failed to create jumbo Rx ring DMA tag\n"); 2068 goto fail; 2069 } 2070 2071 /* Create tag for jumbo buffer blocks. */ 2072 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2073 PAGE_SIZE, 0, /* alignment, boundary */ 2074 BUS_SPACE_MAXADDR, /* lowaddr */ 2075 BUS_SPACE_MAXADDR, /* highaddr */ 2076 NULL, NULL, /* filter, filterarg */ 2077 MSK_JMEM, /* maxsize */ 2078 1, /* nsegments */ 2079 MSK_JMEM, /* maxsegsize */ 2080 0, /* flags */ 2081 NULL, NULL, /* lockfunc, lockarg */ 2082 &sc_if->msk_cdata.msk_jumbo_tag); 2083 if (error != 0) { 2084 device_printf(sc_if->msk_if_dev, 2085 "failed to create jumbo Rx buffer block DMA tag\n"); 2086 goto fail; 2087 } 2088 2089 /* Create tag for Tx buffers. */ 2090 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2091 1, 0, /* alignment, boundary */ 2092 BUS_SPACE_MAXADDR, /* lowaddr */ 2093 BUS_SPACE_MAXADDR, /* highaddr */ 2094 NULL, NULL, /* filter, filterarg */ 2095 MSK_TSO_MAXSIZE, /* maxsize */ 2096 MSK_MAXTXSEGS, /* nsegments */ 2097 MSK_TSO_MAXSGSIZE, /* maxsegsize */ 2098 0, /* flags */ 2099 NULL, NULL, /* lockfunc, lockarg */ 2100 &sc_if->msk_cdata.msk_tx_tag); 2101 if (error != 0) { 2102 device_printf(sc_if->msk_if_dev, 2103 "failed to create Tx DMA tag\n"); 2104 goto fail; 2105 } 2106 2107 /* Create tag for Rx buffers. */ 2108 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2109 1, 0, /* alignment, boundary */ 2110 BUS_SPACE_MAXADDR, /* lowaddr */ 2111 BUS_SPACE_MAXADDR, /* highaddr */ 2112 NULL, NULL, /* filter, filterarg */ 2113 MCLBYTES, /* maxsize */ 2114 1, /* nsegments */ 2115 MCLBYTES, /* maxsegsize */ 2116 0, /* flags */ 2117 NULL, NULL, /* lockfunc, lockarg */ 2118 &sc_if->msk_cdata.msk_rx_tag); 2119 if (error != 0) { 2120 device_printf(sc_if->msk_if_dev, 2121 "failed to create Rx DMA tag\n"); 2122 goto fail; 2123 } 2124 2125 /* Create tag for jumbo Rx buffers. */ 2126 error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 2127 PAGE_SIZE, 0, /* alignment, boundary */ 2128 BUS_SPACE_MAXADDR, /* lowaddr */ 2129 BUS_SPACE_MAXADDR, /* highaddr */ 2130 NULL, NULL, /* filter, filterarg */ 2131 MCLBYTES * MSK_MAXRXSEGS, /* maxsize */ 2132 MSK_MAXRXSEGS, /* nsegments */ 2133 MSK_JLEN, /* maxsegsize */ 2134 0, /* flags */ 2135 NULL, NULL, /* lockfunc, lockarg */ 2136 &sc_if->msk_cdata.msk_jumbo_rx_tag); 2137 if (error != 0) { 2138 device_printf(sc_if->msk_if_dev, 2139 "failed to create jumbo Rx DMA tag\n"); 2140 goto fail; 2141 } 2142 2143 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2144 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 2145 (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 2146 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 2147 if (error != 0) { 2148 device_printf(sc_if->msk_if_dev, 2149 "failed to allocate DMA'able memory for Tx ring\n"); 2150 goto fail; 2151 } 2152 2153 ctx.msk_busaddr = 0; 2154 error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 2155 sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 2156 MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2157 if (error != 0) { 2158 device_printf(sc_if->msk_if_dev, 2159 "failed to load DMA'able memory for Tx ring\n"); 2160 goto fail; 2161 } 2162 sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 2163 2164 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2165 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 2166 (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 2167 BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 2168 if (error != 0) { 2169 device_printf(sc_if->msk_if_dev, 2170 "failed to allocate DMA'able memory for Rx ring\n"); 2171 goto fail; 2172 } 2173 2174 ctx.msk_busaddr = 0; 2175 error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 2176 sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 2177 MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, 0); 2178 if (error != 0) { 2179 device_printf(sc_if->msk_if_dev, 2180 "failed to load DMA'able memory for Rx ring\n"); 2181 goto fail; 2182 } 2183 sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 2184 2185 /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 2186 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2187 (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 2188 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2189 &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2190 if (error != 0) { 2191 device_printf(sc_if->msk_if_dev, 2192 "failed to allocate DMA'able memory for jumbo Rx ring\n"); 2193 goto fail; 2194 } 2195 2196 ctx.msk_busaddr = 0; 2197 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2198 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 2199 sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 2200 msk_dmamap_cb, &ctx, 0); 2201 if (error != 0) { 2202 device_printf(sc_if->msk_if_dev, 2203 "failed to load DMA'able memory for jumbo Rx ring\n"); 2204 goto fail; 2205 } 2206 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 2207 2208 /* Create DMA maps for Tx buffers. */ 2209 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2210 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2211 txd->tx_m = NULL; 2212 txd->tx_dmamap = NULL; 2213 error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 2214 &txd->tx_dmamap); 2215 if (error != 0) { 2216 device_printf(sc_if->msk_if_dev, 2217 "failed to create Tx dmamap\n"); 2218 goto fail; 2219 } 2220 } 2221 /* Create DMA maps for Rx buffers. */ 2222 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2223 &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 2224 device_printf(sc_if->msk_if_dev, 2225 "failed to create spare Rx dmamap\n"); 2226 goto fail; 2227 } 2228 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2229 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2230 rxd->rx_m = NULL; 2231 rxd->rx_dmamap = NULL; 2232 error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 2233 &rxd->rx_dmamap); 2234 if (error != 0) { 2235 device_printf(sc_if->msk_if_dev, 2236 "failed to create Rx dmamap\n"); 2237 goto fail; 2238 } 2239 } 2240 /* Create DMA maps for jumbo Rx buffers. */ 2241 if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2242 &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 2243 device_printf(sc_if->msk_if_dev, 2244 "failed to create spare jumbo Rx dmamap\n"); 2245 goto fail; 2246 } 2247 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2248 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2249 jrxd->rx_m = NULL; 2250 jrxd->rx_dmamap = NULL; 2251 error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 2252 &jrxd->rx_dmamap); 2253 if (error != 0) { 2254 device_printf(sc_if->msk_if_dev, 2255 "failed to create jumbo Rx dmamap\n"); 2256 goto fail; 2257 } 2258 } 2259 2260 /* Allocate DMA'able memory and load the DMA map for jumbo buf. */ 2261 error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_tag, 2262 (void **)&sc_if->msk_rdata.msk_jumbo_buf, 2263 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 2264 &sc_if->msk_cdata.msk_jumbo_map); 2265 if (error != 0) { 2266 device_printf(sc_if->msk_if_dev, 2267 "failed to allocate DMA'able memory for jumbo buf\n"); 2268 goto fail; 2269 } 2270 2271 ctx.msk_busaddr = 0; 2272 error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_tag, 2273 sc_if->msk_cdata.msk_jumbo_map, sc_if->msk_rdata.msk_jumbo_buf, 2274 MSK_JMEM, msk_dmamap_cb, &ctx, 0); 2275 if (error != 0) { 2276 device_printf(sc_if->msk_if_dev, 2277 "failed to load DMA'able memory for jumbobuf\n"); 2278 goto fail; 2279 } 2280 sc_if->msk_rdata.msk_jumbo_buf_paddr = ctx.msk_busaddr; 2281 2282 /* 2283 * Now divide it up into 9K pieces and save the addresses 2284 * in an array. 2285 */ 2286 ptr = sc_if->msk_rdata.msk_jumbo_buf; 2287 for (i = 0; i < MSK_JSLOTS; i++) { 2288 sc_if->msk_cdata.msk_jslots[i] = ptr; 2289 ptr += MSK_JLEN; 2290 entry = malloc(sizeof(struct msk_jpool_entry), 2291 M_DEVBUF, M_WAITOK); 2292 if (entry == NULL) { 2293 device_printf(sc_if->msk_if_dev, 2294 "no memory for jumbo buffers!\n"); 2295 error = ENOMEM; 2296 goto fail; 2297 } 2298 entry->slot = i; 2299 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, 2300 jpool_entries); 2301 } 2302 2303 fail: 2304 return (error); 2305 } 2306 2307 static void 2308 msk_txrx_dma_free(struct msk_if_softc *sc_if) 2309 { 2310 struct msk_txdesc *txd; 2311 struct msk_rxdesc *rxd; 2312 struct msk_rxdesc *jrxd; 2313 struct msk_jpool_entry *entry; 2314 int i; 2315 2316 MSK_JLIST_LOCK(sc_if); 2317 while ((entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead))) { 2318 device_printf(sc_if->msk_if_dev, 2319 "asked to free buffer that is in use!\n"); 2320 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries); 2321 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, 2322 jpool_entries); 2323 } 2324 2325 while (!SLIST_EMPTY(&sc_if->msk_jfree_listhead)) { 2326 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead); 2327 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries); 2328 free(entry, M_DEVBUF); 2329 } 2330 MSK_JLIST_UNLOCK(sc_if); 2331 2332 /* Destroy jumbo buffer block. */ 2333 if (sc_if->msk_cdata.msk_jumbo_map) 2334 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_tag, 2335 sc_if->msk_cdata.msk_jumbo_map); 2336 2337 if (sc_if->msk_rdata.msk_jumbo_buf) { 2338 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_tag, 2339 sc_if->msk_rdata.msk_jumbo_buf, 2340 sc_if->msk_cdata.msk_jumbo_map); 2341 sc_if->msk_rdata.msk_jumbo_buf = NULL; 2342 sc_if->msk_cdata.msk_jumbo_map = NULL; 2343 } 2344 2345 /* Tx ring. */ 2346 if (sc_if->msk_cdata.msk_tx_ring_tag) { 2347 if (sc_if->msk_cdata.msk_tx_ring_map) 2348 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 2349 sc_if->msk_cdata.msk_tx_ring_map); 2350 if (sc_if->msk_cdata.msk_tx_ring_map && 2351 sc_if->msk_rdata.msk_tx_ring) 2352 bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 2353 sc_if->msk_rdata.msk_tx_ring, 2354 sc_if->msk_cdata.msk_tx_ring_map); 2355 sc_if->msk_rdata.msk_tx_ring = NULL; 2356 sc_if->msk_cdata.msk_tx_ring_map = NULL; 2357 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 2358 sc_if->msk_cdata.msk_tx_ring_tag = NULL; 2359 } 2360 /* Rx ring. */ 2361 if (sc_if->msk_cdata.msk_rx_ring_tag) { 2362 if (sc_if->msk_cdata.msk_rx_ring_map) 2363 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 2364 sc_if->msk_cdata.msk_rx_ring_map); 2365 if (sc_if->msk_cdata.msk_rx_ring_map && 2366 sc_if->msk_rdata.msk_rx_ring) 2367 bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 2368 sc_if->msk_rdata.msk_rx_ring, 2369 sc_if->msk_cdata.msk_rx_ring_map); 2370 sc_if->msk_rdata.msk_rx_ring = NULL; 2371 sc_if->msk_cdata.msk_rx_ring_map = NULL; 2372 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 2373 sc_if->msk_cdata.msk_rx_ring_tag = NULL; 2374 } 2375 /* Jumbo Rx ring. */ 2376 if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 2377 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map) 2378 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2379 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2380 if (sc_if->msk_cdata.msk_jumbo_rx_ring_map && 2381 sc_if->msk_rdata.msk_jumbo_rx_ring) 2382 bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 2383 sc_if->msk_rdata.msk_jumbo_rx_ring, 2384 sc_if->msk_cdata.msk_jumbo_rx_ring_map); 2385 sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 2386 sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL; 2387 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 2388 sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 2389 } 2390 /* Tx buffers. */ 2391 if (sc_if->msk_cdata.msk_tx_tag) { 2392 for (i = 0; i < MSK_TX_RING_CNT; i++) { 2393 txd = &sc_if->msk_cdata.msk_txdesc[i]; 2394 if (txd->tx_dmamap) { 2395 bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 2396 txd->tx_dmamap); 2397 txd->tx_dmamap = NULL; 2398 } 2399 } 2400 bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 2401 sc_if->msk_cdata.msk_tx_tag = NULL; 2402 } 2403 /* Rx buffers. */ 2404 if (sc_if->msk_cdata.msk_rx_tag) { 2405 for (i = 0; i < MSK_RX_RING_CNT; i++) { 2406 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 2407 if (rxd->rx_dmamap) { 2408 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2409 rxd->rx_dmamap); 2410 rxd->rx_dmamap = NULL; 2411 } 2412 } 2413 if (sc_if->msk_cdata.msk_rx_sparemap) { 2414 bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 2415 sc_if->msk_cdata.msk_rx_sparemap); 2416 sc_if->msk_cdata.msk_rx_sparemap = 0; 2417 } 2418 bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 2419 sc_if->msk_cdata.msk_rx_tag = NULL; 2420 } 2421 /* Jumbo Rx buffers. */ 2422 if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 2423 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 2424 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 2425 if (jrxd->rx_dmamap) { 2426 bus_dmamap_destroy( 2427 sc_if->msk_cdata.msk_jumbo_rx_tag, 2428 jrxd->rx_dmamap); 2429 jrxd->rx_dmamap = NULL; 2430 } 2431 } 2432 if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 2433 bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 2434 sc_if->msk_cdata.msk_jumbo_rx_sparemap); 2435 sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 2436 } 2437 bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 2438 sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 2439 } 2440 2441 if (sc_if->msk_cdata.msk_parent_tag) { 2442 bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 2443 sc_if->msk_cdata.msk_parent_tag = NULL; 2444 } 2445 mtx_destroy(&sc_if->msk_jlist_mtx); 2446 } 2447 2448 /* 2449 * Allocate a jumbo buffer. 2450 */ 2451 static void * 2452 msk_jalloc(struct msk_if_softc *sc_if) 2453 { 2454 struct msk_jpool_entry *entry; 2455 2456 MSK_JLIST_LOCK(sc_if); 2457 2458 entry = SLIST_FIRST(&sc_if->msk_jfree_listhead); 2459 2460 if (entry == NULL) { 2461 MSK_JLIST_UNLOCK(sc_if); 2462 return (NULL); 2463 } 2464 2465 SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries); 2466 SLIST_INSERT_HEAD(&sc_if->msk_jinuse_listhead, entry, jpool_entries); 2467 2468 MSK_JLIST_UNLOCK(sc_if); 2469 2470 return (sc_if->msk_cdata.msk_jslots[entry->slot]); 2471 } 2472 2473 /* 2474 * Release a jumbo buffer. 2475 */ 2476 static void 2477 msk_jfree(void *buf, void *args) 2478 { 2479 struct msk_if_softc *sc_if; 2480 struct msk_jpool_entry *entry; 2481 int i; 2482 2483 /* Extract the softc struct pointer. */ 2484 sc_if = (struct msk_if_softc *)args; 2485 KASSERT(sc_if != NULL, ("%s: can't find softc pointer!", __func__)); 2486 2487 MSK_JLIST_LOCK(sc_if); 2488 /* Calculate the slot this buffer belongs to. */ 2489 i = ((vm_offset_t)buf 2490 - (vm_offset_t)sc_if->msk_rdata.msk_jumbo_buf) / MSK_JLEN; 2491 KASSERT(i >= 0 && i < MSK_JSLOTS, 2492 ("%s: asked to free buffer that we don't manage!", __func__)); 2493 2494 entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead); 2495 KASSERT(entry != NULL, ("%s: buffer not in use!", __func__)); 2496 entry->slot = i; 2497 SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries); 2498 SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, jpool_entries); 2499 if (SLIST_EMPTY(&sc_if->msk_jinuse_listhead)) 2500 wakeup(sc_if); 2501 2502 MSK_JLIST_UNLOCK(sc_if); 2503 } 2504 2505 /* 2506 * It's copy of ath_defrag(ath(4)). 2507 * 2508 * Defragment an mbuf chain, returning at most maxfrags separate 2509 * mbufs+clusters. If this is not possible NULL is returned and 2510 * the original mbuf chain is left in it's present (potentially 2511 * modified) state. We use two techniques: collapsing consecutive 2512 * mbufs and replacing consecutive mbufs by a cluster. 2513 */ 2514 static struct mbuf * 2515 msk_defrag(struct mbuf *m0, int how, int maxfrags) 2516 { 2517 struct mbuf *m, *n, *n2, **prev; 2518 u_int curfrags; 2519 2520 /* 2521 * Calculate the current number of frags. 2522 */ 2523 curfrags = 0; 2524 for (m = m0; m != NULL; m = m->m_next) 2525 curfrags++; 2526 /* 2527 * First, try to collapse mbufs. Note that we always collapse 2528 * towards the front so we don't need to deal with moving the 2529 * pkthdr. This may be suboptimal if the first mbuf has much 2530 * less data than the following. 2531 */ 2532 m = m0; 2533 again: 2534 for (;;) { 2535 n = m->m_next; 2536 if (n == NULL) 2537 break; 2538 if ((m->m_flags & M_RDONLY) == 0 && 2539 n->m_len < M_TRAILINGSPACE(m)) { 2540 bcopy(mtod(n, void *), mtod(m, char *) + m->m_len, 2541 n->m_len); 2542 m->m_len += n->m_len; 2543 m->m_next = n->m_next; 2544 m_free(n); 2545 if (--curfrags <= maxfrags) 2546 return (m0); 2547 } else 2548 m = n; 2549 } 2550 KASSERT(maxfrags > 1, 2551 ("maxfrags %u, but normal collapse failed", maxfrags)); 2552 /* 2553 * Collapse consecutive mbufs to a cluster. 2554 */ 2555 prev = &m0->m_next; /* NB: not the first mbuf */ 2556 while ((n = *prev) != NULL) { 2557 if ((n2 = n->m_next) != NULL && 2558 n->m_len + n2->m_len < MCLBYTES) { 2559 m = m_getcl(how, MT_DATA, 0); 2560 if (m == NULL) 2561 goto bad; 2562 bcopy(mtod(n, void *), mtod(m, void *), n->m_len); 2563 bcopy(mtod(n2, void *), mtod(m, char *) + n->m_len, 2564 n2->m_len); 2565 m->m_len = n->m_len + n2->m_len; 2566 m->m_next = n2->m_next; 2567 *prev = m; 2568 m_free(n); 2569 m_free(n2); 2570 if (--curfrags <= maxfrags) /* +1 cl -2 mbufs */ 2571 return m0; 2572 /* 2573 * Still not there, try the normal collapse 2574 * again before we allocate another cluster. 2575 */ 2576 goto again; 2577 } 2578 prev = &n->m_next; 2579 } 2580 /* 2581 * No place where we can collapse to a cluster; punt. 2582 * This can occur if, for example, you request 2 frags 2583 * but the packet requires that both be clusters (we 2584 * never reallocate the first mbuf to avoid moving the 2585 * packet header). 2586 */ 2587 bad: 2588 return (NULL); 2589 } 2590 2591 static int 2592 msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 2593 { 2594 struct msk_txdesc *txd, *txd_last; 2595 struct msk_tx_desc *tx_le; 2596 struct mbuf *m; 2597 bus_dmamap_t map; 2598 bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 2599 uint32_t control, prod, si; 2600 uint16_t offset, tcp_offset, tso_mtu; 2601 int error, i, nseg, tso; 2602 2603 MSK_IF_LOCK_ASSERT(sc_if); 2604 2605 tcp_offset = offset = 0; 2606 m = *m_head; 2607 if ((m->m_pkthdr.csum_flags & (MSK_CSUM_FEATURES | CSUM_TSO)) != 0) { 2608 /* 2609 * Since mbuf has no protocol specific structure information 2610 * in it we have to inspect protocol information here to 2611 * setup TSO and checksum offload. I don't know why Marvell 2612 * made a such decision in chip design because other GigE 2613 * hardwares normally takes care of all these chores in 2614 * hardware. However, TSO performance of Yukon II is very 2615 * good such that it's worth to implement it. 2616 */ 2617 struct ether_header *eh; 2618 struct ip *ip; 2619 struct tcphdr *tcp; 2620 2621 /* TODO check for M_WRITABLE(m) */ 2622 2623 offset = sizeof(struct ether_header); 2624 m = m_pullup(m, offset); 2625 if (m == NULL) { 2626 *m_head = NULL; 2627 return (ENOBUFS); 2628 } 2629 eh = mtod(m, struct ether_header *); 2630 /* Check if hardware VLAN insertion is off. */ 2631 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2632 offset = sizeof(struct ether_vlan_header); 2633 m = m_pullup(m, offset); 2634 if (m == NULL) { 2635 *m_head = NULL; 2636 return (ENOBUFS); 2637 } 2638 } 2639 m = m_pullup(m, offset + sizeof(struct ip)); 2640 if (m == NULL) { 2641 *m_head = NULL; 2642 return (ENOBUFS); 2643 } 2644 ip = (struct ip *)(mtod(m, char *) + offset); 2645 offset += (ip->ip_hl << 2); 2646 tcp_offset = offset; 2647 /* 2648 * It seems that Yukon II has Tx checksum offload bug for 2649 * small TCP packets that's less than 60 bytes in size 2650 * (e.g. TCP window probe packet, pure ACK packet). 2651 * Common work around like padding with zeros to make the 2652 * frame minimum ethernet frame size didn't work at all. 2653 * Instead of disabling checksum offload completely we 2654 * resort to S/W checksum routine when we encounter short 2655 * TCP frames. 2656 * Short UDP packets appear to be handled correctly by 2657 * Yukon II. 2658 */ 2659 if (m->m_pkthdr.len < MSK_MIN_FRAMELEN && 2660 (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2661 uint16_t csum; 2662 2663 csum = in_cksum_skip(m, ntohs(ip->ip_len) + offset - 2664 (ip->ip_hl << 2), offset); 2665 *(uint16_t *)(m->m_data + offset + 2666 m->m_pkthdr.csum_data) = csum; 2667 m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2668 } 2669 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2670 m = m_pullup(m, offset + sizeof(struct tcphdr)); 2671 if (m == NULL) { 2672 *m_head = NULL; 2673 return (ENOBUFS); 2674 } 2675 tcp = (struct tcphdr *)(mtod(m, char *) + offset); 2676 offset += (tcp->th_off << 2); 2677 } 2678 *m_head = m; 2679 } 2680 2681 prod = sc_if->msk_cdata.msk_tx_prod; 2682 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2683 txd_last = txd; 2684 map = txd->tx_dmamap; 2685 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 2686 *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2687 if (error == EFBIG) { 2688 m = msk_defrag(*m_head, M_DONTWAIT, MSK_MAXTXSEGS); 2689 if (m == NULL) { 2690 m_freem(*m_head); 2691 *m_head = NULL; 2692 return (ENOBUFS); 2693 } 2694 *m_head = m; 2695 error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 2696 map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 2697 if (error != 0) { 2698 m_freem(*m_head); 2699 *m_head = NULL; 2700 return (error); 2701 } 2702 } else if (error != 0) 2703 return (error); 2704 if (nseg == 0) { 2705 m_freem(*m_head); 2706 *m_head = NULL; 2707 return (EIO); 2708 } 2709 2710 /* Check number of available descriptors. */ 2711 if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 2712 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 2713 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 2714 return (ENOBUFS); 2715 } 2716 2717 control = 0; 2718 tso = 0; 2719 tx_le = NULL; 2720 2721 /* Check TSO support. */ 2722 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2723 tso_mtu = offset + m->m_pkthdr.tso_segsz; 2724 if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 2725 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2726 tx_le->msk_addr = htole32(tso_mtu); 2727 tx_le->msk_control = htole32(OP_LRGLEN | HW_OWNER); 2728 sc_if->msk_cdata.msk_tx_cnt++; 2729 MSK_INC(prod, MSK_TX_RING_CNT); 2730 sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 2731 } 2732 tso++; 2733 } 2734 /* Check if we have a VLAN tag to insert. */ 2735 if ((m->m_flags & M_VLANTAG) != 0) { 2736 if (tso == 0) { 2737 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2738 tx_le->msk_addr = htole32(0); 2739 tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 2740 htons(m->m_pkthdr.ether_vtag)); 2741 sc_if->msk_cdata.msk_tx_cnt++; 2742 MSK_INC(prod, MSK_TX_RING_CNT); 2743 } else { 2744 tx_le->msk_control |= htole32(OP_VLAN | 2745 htons(m->m_pkthdr.ether_vtag)); 2746 } 2747 control |= INS_VLAN; 2748 } 2749 /* Check if we have to handle checksum offload. */ 2750 if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 2751 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2752 tx_le->msk_addr = htole32(((tcp_offset + m->m_pkthdr.csum_data) 2753 & 0xffff) | ((uint32_t)tcp_offset << 16)); 2754 tx_le->msk_control = htole32(1 << 16 | (OP_TCPLISW | HW_OWNER)); 2755 control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 2756 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2757 control |= UDPTCP; 2758 sc_if->msk_cdata.msk_tx_cnt++; 2759 MSK_INC(prod, MSK_TX_RING_CNT); 2760 } 2761 2762 si = prod; 2763 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2764 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 2765 if (tso == 0) 2766 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2767 OP_PACKET); 2768 else 2769 tx_le->msk_control = htole32(txsegs[0].ds_len | control | 2770 OP_LARGESEND); 2771 sc_if->msk_cdata.msk_tx_cnt++; 2772 MSK_INC(prod, MSK_TX_RING_CNT); 2773 2774 for (i = 1; i < nseg; i++) { 2775 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2776 tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 2777 tx_le->msk_control = htole32(txsegs[i].ds_len | control | 2778 OP_BUFFER | HW_OWNER); 2779 sc_if->msk_cdata.msk_tx_cnt++; 2780 MSK_INC(prod, MSK_TX_RING_CNT); 2781 } 2782 /* Update producer index. */ 2783 sc_if->msk_cdata.msk_tx_prod = prod; 2784 2785 /* Set EOP on the last desciptor. */ 2786 prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 2787 tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 2788 tx_le->msk_control |= htole32(EOP); 2789 2790 /* Turn the first descriptor ownership to hardware. */ 2791 tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 2792 tx_le->msk_control |= htole32(HW_OWNER); 2793 2794 txd = &sc_if->msk_cdata.msk_txdesc[prod]; 2795 map = txd_last->tx_dmamap; 2796 txd_last->tx_dmamap = txd->tx_dmamap; 2797 txd->tx_dmamap = map; 2798 txd->tx_m = m; 2799 2800 /* Sync descriptors. */ 2801 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 2802 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 2803 sc_if->msk_cdata.msk_tx_ring_map, 2804 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2805 2806 return (0); 2807 } 2808 2809 static void 2810 msk_tx_task(void *arg, int pending) 2811 { 2812 struct ifnet *ifp; 2813 2814 ifp = arg; 2815 msk_start(ifp); 2816 } 2817 2818 static void 2819 msk_start(struct ifnet *ifp) 2820 { 2821 struct msk_if_softc *sc_if; 2822 struct mbuf *m_head; 2823 int enq; 2824 2825 sc_if = ifp->if_softc; 2826 2827 MSK_IF_LOCK(sc_if); 2828 2829 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2830 IFF_DRV_RUNNING || sc_if->msk_link == 0) { 2831 MSK_IF_UNLOCK(sc_if); 2832 return; 2833 } 2834 2835 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2836 sc_if->msk_cdata.msk_tx_cnt < 2837 (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 2838 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2839 if (m_head == NULL) 2840 break; 2841 /* 2842 * Pack the data into the transmit ring. If we 2843 * don't have room, set the OACTIVE flag and wait 2844 * for the NIC to drain the ring. 2845 */ 2846 if (msk_encap(sc_if, &m_head) != 0) { 2847 if (m_head == NULL) 2848 break; 2849 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2850 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2851 break; 2852 } 2853 2854 enq++; 2855 /* 2856 * If there's a BPF listener, bounce a copy of this frame 2857 * to him. 2858 */ 2859 ETHER_BPF_MTAP(ifp, m_head); 2860 } 2861 2862 if (enq > 0) { 2863 /* Transmit */ 2864 CSR_WRITE_2(sc_if->msk_softc, 2865 Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 2866 sc_if->msk_cdata.msk_tx_prod); 2867 2868 /* Set a timeout in case the chip goes out to lunch. */ 2869 sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 2870 } 2871 2872 MSK_IF_UNLOCK(sc_if); 2873 } 2874 2875 static void 2876 msk_watchdog(struct msk_if_softc *sc_if) 2877 { 2878 struct ifnet *ifp; 2879 uint32_t ridx; 2880 int idx; 2881 2882 MSK_IF_LOCK_ASSERT(sc_if); 2883 2884 if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 2885 return; 2886 ifp = sc_if->msk_ifp; 2887 if (sc_if->msk_link == 0) { 2888 if (bootverbose) 2889 if_printf(sc_if->msk_ifp, "watchdog timeout " 2890 "(missed link)\n"); 2891 ifp->if_oerrors++; 2892 msk_init_locked(sc_if); 2893 return; 2894 } 2895 2896 /* 2897 * Reclaim first as there is a possibility of losing Tx completion 2898 * interrupts. 2899 */ 2900 ridx = sc_if->msk_port == MSK_PORT_A ? STAT_TXA1_RIDX : STAT_TXA2_RIDX; 2901 idx = CSR_READ_2(sc_if->msk_softc, ridx); 2902 if (sc_if->msk_cdata.msk_tx_cons != idx) { 2903 msk_txeof(sc_if, idx); 2904 if (sc_if->msk_cdata.msk_tx_cnt == 0) { 2905 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 2906 "-- recovering\n"); 2907 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2908 taskqueue_enqueue(taskqueue_fast, 2909 &sc_if->msk_tx_task); 2910 return; 2911 } 2912 } 2913 2914 if_printf(ifp, "watchdog timeout\n"); 2915 ifp->if_oerrors++; 2916 msk_init_locked(sc_if); 2917 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2918 taskqueue_enqueue(taskqueue_fast, &sc_if->msk_tx_task); 2919 } 2920 2921 static int 2922 mskc_shutdown(device_t dev) 2923 { 2924 struct msk_softc *sc; 2925 int i; 2926 2927 sc = device_get_softc(dev); 2928 MSK_LOCK(sc); 2929 for (i = 0; i < sc->msk_num_port; i++) { 2930 if (sc->msk_if[i] != NULL) 2931 msk_stop(sc->msk_if[i]); 2932 } 2933 2934 /* Disable all interrupts. */ 2935 CSR_WRITE_4(sc, B0_IMSK, 0); 2936 CSR_READ_4(sc, B0_IMSK); 2937 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2938 CSR_READ_4(sc, B0_HWE_IMSK); 2939 2940 /* Put hardware reset. */ 2941 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2942 2943 MSK_UNLOCK(sc); 2944 return (0); 2945 } 2946 2947 static int 2948 mskc_suspend(device_t dev) 2949 { 2950 struct msk_softc *sc; 2951 int i; 2952 2953 sc = device_get_softc(dev); 2954 2955 MSK_LOCK(sc); 2956 2957 for (i = 0; i < sc->msk_num_port; i++) { 2958 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2959 ((sc->msk_if[i]->msk_ifp->if_drv_flags & 2960 IFF_DRV_RUNNING) != 0)) 2961 msk_stop(sc->msk_if[i]); 2962 } 2963 2964 /* Disable all interrupts. */ 2965 CSR_WRITE_4(sc, B0_IMSK, 0); 2966 CSR_READ_4(sc, B0_IMSK); 2967 CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 2968 CSR_READ_4(sc, B0_HWE_IMSK); 2969 2970 msk_phy_power(sc, MSK_PHY_POWERDOWN); 2971 2972 /* Put hardware reset. */ 2973 CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 2974 sc->msk_suspended = 1; 2975 2976 MSK_UNLOCK(sc); 2977 2978 return (0); 2979 } 2980 2981 static int 2982 mskc_resume(device_t dev) 2983 { 2984 struct msk_softc *sc; 2985 int i; 2986 2987 sc = device_get_softc(dev); 2988 2989 MSK_LOCK(sc); 2990 2991 mskc_reset(sc); 2992 for (i = 0; i < sc->msk_num_port; i++) { 2993 if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 2994 ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) 2995 msk_init_locked(sc->msk_if[i]); 2996 } 2997 sc->msk_suspended = 0; 2998 2999 MSK_UNLOCK(sc); 3000 3001 return (0); 3002 } 3003 3004 static void 3005 msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len) 3006 { 3007 struct mbuf *m; 3008 struct ifnet *ifp; 3009 struct msk_rxdesc *rxd; 3010 int cons, rxlen; 3011 3012 ifp = sc_if->msk_ifp; 3013 3014 MSK_IF_LOCK_ASSERT(sc_if); 3015 3016 cons = sc_if->msk_cdata.msk_rx_cons; 3017 do { 3018 rxlen = status >> 16; 3019 if ((status & GMR_FS_VLAN) != 0 && 3020 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3021 rxlen -= ETHER_VLAN_ENCAP_LEN; 3022 if (len > sc_if->msk_framesize || 3023 ((status & GMR_FS_ANY_ERR) != 0) || 3024 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3025 /* Don't count flow-control packet as errors. */ 3026 if ((status & GMR_FS_GOOD_FC) == 0) 3027 ifp->if_ierrors++; 3028 msk_discard_rxbuf(sc_if, cons); 3029 break; 3030 } 3031 rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 3032 m = rxd->rx_m; 3033 if (msk_newbuf(sc_if, cons) != 0) { 3034 ifp->if_iqdrops++; 3035 /* Reuse old buffer. */ 3036 msk_discard_rxbuf(sc_if, cons); 3037 break; 3038 } 3039 m->m_pkthdr.rcvif = ifp; 3040 m->m_pkthdr.len = m->m_len = len; 3041 ifp->if_ipackets++; 3042 /* Check for VLAN tagged packets. */ 3043 if ((status & GMR_FS_VLAN) != 0 && 3044 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3045 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3046 m->m_flags |= M_VLANTAG; 3047 } 3048 MSK_IF_UNLOCK(sc_if); 3049 (*ifp->if_input)(ifp, m); 3050 MSK_IF_LOCK(sc_if); 3051 } while (0); 3052 3053 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 3054 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 3055 } 3056 3057 static void 3058 msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len) 3059 { 3060 struct mbuf *m; 3061 struct ifnet *ifp; 3062 struct msk_rxdesc *jrxd; 3063 int cons, rxlen; 3064 3065 ifp = sc_if->msk_ifp; 3066 3067 MSK_IF_LOCK_ASSERT(sc_if); 3068 3069 cons = sc_if->msk_cdata.msk_rx_cons; 3070 do { 3071 rxlen = status >> 16; 3072 if ((status & GMR_FS_VLAN) != 0 && 3073 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3074 rxlen -= ETHER_VLAN_ENCAP_LEN; 3075 if (len > sc_if->msk_framesize || 3076 ((status & GMR_FS_ANY_ERR) != 0) || 3077 ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 3078 /* Don't count flow-control packet as errors. */ 3079 if ((status & GMR_FS_GOOD_FC) == 0) 3080 ifp->if_ierrors++; 3081 msk_discard_jumbo_rxbuf(sc_if, cons); 3082 break; 3083 } 3084 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 3085 m = jrxd->rx_m; 3086 if (msk_jumbo_newbuf(sc_if, cons) != 0) { 3087 ifp->if_iqdrops++; 3088 /* Reuse old buffer. */ 3089 msk_discard_jumbo_rxbuf(sc_if, cons); 3090 break; 3091 } 3092 m->m_pkthdr.rcvif = ifp; 3093 m->m_pkthdr.len = m->m_len = len; 3094 ifp->if_ipackets++; 3095 /* Check for VLAN tagged packets. */ 3096 if ((status & GMR_FS_VLAN) != 0 && 3097 (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 3098 m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 3099 m->m_flags |= M_VLANTAG; 3100 } 3101 MSK_IF_UNLOCK(sc_if); 3102 (*ifp->if_input)(ifp, m); 3103 MSK_IF_LOCK(sc_if); 3104 } while (0); 3105 3106 MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 3107 MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 3108 } 3109 3110 static void 3111 msk_txeof(struct msk_if_softc *sc_if, int idx) 3112 { 3113 struct msk_txdesc *txd; 3114 struct msk_tx_desc *cur_tx; 3115 struct ifnet *ifp; 3116 uint32_t control; 3117 int cons, prog; 3118 3119 MSK_IF_LOCK_ASSERT(sc_if); 3120 3121 ifp = sc_if->msk_ifp; 3122 3123 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 3124 sc_if->msk_cdata.msk_tx_ring_map, 3125 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3126 /* 3127 * Go through our tx ring and free mbufs for those 3128 * frames that have been sent. 3129 */ 3130 cons = sc_if->msk_cdata.msk_tx_cons; 3131 prog = 0; 3132 for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 3133 if (sc_if->msk_cdata.msk_tx_cnt <= 0) 3134 break; 3135 prog++; 3136 cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 3137 control = le32toh(cur_tx->msk_control); 3138 sc_if->msk_cdata.msk_tx_cnt--; 3139 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3140 if ((control & EOP) == 0) 3141 continue; 3142 txd = &sc_if->msk_cdata.msk_txdesc[cons]; 3143 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 3144 BUS_DMASYNC_POSTWRITE); 3145 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 3146 3147 ifp->if_opackets++; 3148 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 3149 __func__)); 3150 m_freem(txd->tx_m); 3151 txd->tx_m = NULL; 3152 } 3153 3154 if (prog > 0) { 3155 sc_if->msk_cdata.msk_tx_cons = cons; 3156 if (sc_if->msk_cdata.msk_tx_cnt == 0) 3157 sc_if->msk_watchdog_timer = 0; 3158 /* No need to sync LEs as we didn't update LEs. */ 3159 } 3160 } 3161 3162 static void 3163 msk_tick(void *xsc_if) 3164 { 3165 struct msk_if_softc *sc_if; 3166 struct mii_data *mii; 3167 3168 sc_if = xsc_if; 3169 3170 MSK_IF_LOCK_ASSERT(sc_if); 3171 3172 mii = device_get_softc(sc_if->msk_miibus); 3173 3174 mii_tick(mii); 3175 msk_watchdog(sc_if); 3176 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3177 } 3178 3179 static void 3180 msk_intr_phy(struct msk_if_softc *sc_if) 3181 { 3182 uint16_t status; 3183 3184 msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3185 status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3186 /* Handle FIFO Underrun/Overflow? */ 3187 if ((status & PHY_M_IS_FIFO_ERROR)) 3188 device_printf(sc_if->msk_if_dev, 3189 "PHY FIFO underrun/overflow.\n"); 3190 } 3191 3192 static void 3193 msk_intr_gmac(struct msk_if_softc *sc_if) 3194 { 3195 struct msk_softc *sc; 3196 uint8_t status; 3197 3198 sc = sc_if->msk_softc; 3199 status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3200 3201 /* GMAC Rx FIFO overrun. */ 3202 if ((status & GM_IS_RX_FF_OR) != 0) { 3203 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3204 GMF_CLI_RX_FO); 3205 device_printf(sc_if->msk_if_dev, "Rx FIFO overrun!\n"); 3206 } 3207 /* GMAC Tx FIFO underrun. */ 3208 if ((status & GM_IS_TX_FF_UR) != 0) { 3209 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3210 GMF_CLI_TX_FU); 3211 device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 3212 /* 3213 * XXX 3214 * In case of Tx underrun, we may need to flush/reset 3215 * Tx MAC but that would also require resynchronization 3216 * with status LEs. Reintializing status LEs would 3217 * affect other port in dual MAC configuration so it 3218 * should be avoided as possible as we can. 3219 * Due to lack of documentation it's all vague guess but 3220 * it needs more investigation. 3221 */ 3222 } 3223 } 3224 3225 static void 3226 msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 3227 { 3228 struct msk_softc *sc; 3229 3230 sc = sc_if->msk_softc; 3231 if ((status & Y2_IS_PAR_RD1) != 0) { 3232 device_printf(sc_if->msk_if_dev, 3233 "RAM buffer read parity error\n"); 3234 /* Clear IRQ. */ 3235 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3236 RI_CLR_RD_PERR); 3237 } 3238 if ((status & Y2_IS_PAR_WR1) != 0) { 3239 device_printf(sc_if->msk_if_dev, 3240 "RAM buffer write parity error\n"); 3241 /* Clear IRQ. */ 3242 CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 3243 RI_CLR_WR_PERR); 3244 } 3245 if ((status & Y2_IS_PAR_MAC1) != 0) { 3246 device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 3247 /* Clear IRQ. */ 3248 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3249 GMF_CLI_TX_PE); 3250 } 3251 if ((status & Y2_IS_PAR_RX1) != 0) { 3252 device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 3253 /* Clear IRQ. */ 3254 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 3255 } 3256 if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 3257 device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 3258 /* Clear IRQ. */ 3259 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 3260 } 3261 } 3262 3263 static void 3264 msk_intr_hwerr(struct msk_softc *sc) 3265 { 3266 uint32_t status; 3267 uint32_t tlphead[4]; 3268 3269 status = CSR_READ_4(sc, B0_HWE_ISRC); 3270 /* Time Stamp timer overflow. */ 3271 if ((status & Y2_IS_TIST_OV) != 0) 3272 CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 3273 if ((status & Y2_IS_PCI_NEXP) != 0) { 3274 /* 3275 * PCI Express Error occured which is not described in PEX 3276 * spec. 3277 * This error is also mapped either to Master Abort( 3278 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 3279 * can only be cleared there. 3280 */ 3281 device_printf(sc->msk_dev, 3282 "PCI Express protocol violation error\n"); 3283 } 3284 3285 if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 3286 uint16_t v16; 3287 3288 if ((status & Y2_IS_MST_ERR) != 0) 3289 device_printf(sc->msk_dev, 3290 "unexpected IRQ Status error\n"); 3291 else 3292 device_printf(sc->msk_dev, 3293 "unexpected IRQ Master error\n"); 3294 /* Reset all bits in the PCI status register. */ 3295 v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 3296 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3297 pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 3298 PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 3299 PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 3300 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3301 } 3302 3303 /* Check for PCI Express Uncorrectable Error. */ 3304 if ((status & Y2_IS_PCI_EXP) != 0) { 3305 uint32_t v32; 3306 3307 /* 3308 * On PCI Express bus bridges are called root complexes (RC). 3309 * PCI Express errors are recognized by the root complex too, 3310 * which requests the system to handle the problem. After 3311 * error occurence it may be that no access to the adapter 3312 * may be performed any longer. 3313 */ 3314 3315 v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 3316 if ((v32 & PEX_UNSUP_REQ) != 0) { 3317 /* Ignore unsupported request error. */ 3318 device_printf(sc->msk_dev, 3319 "Uncorrectable PCI Express error\n"); 3320 } 3321 if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 3322 int i; 3323 3324 /* Get TLP header form Log Registers. */ 3325 for (i = 0; i < 4; i++) 3326 tlphead[i] = CSR_PCI_READ_4(sc, 3327 PEX_HEADER_LOG + i * 4); 3328 /* Check for vendor defined broadcast message. */ 3329 if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 3330 sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 3331 CSR_WRITE_4(sc, B0_HWE_IMSK, 3332 sc->msk_intrhwemask); 3333 CSR_READ_4(sc, B0_HWE_IMSK); 3334 } 3335 } 3336 /* Clear the interrupt. */ 3337 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 3338 CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 3339 CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 3340 } 3341 3342 if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 3343 msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 3344 if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 3345 msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 3346 } 3347 3348 static __inline void 3349 msk_rxput(struct msk_if_softc *sc_if) 3350 { 3351 struct msk_softc *sc; 3352 3353 sc = sc_if->msk_softc; 3354 if (sc_if->msk_framesize >(MCLBYTES - ETHER_HDR_LEN)) 3355 bus_dmamap_sync( 3356 sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 3357 sc_if->msk_cdata.msk_jumbo_rx_ring_map, 3358 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3359 else 3360 bus_dmamap_sync( 3361 sc_if->msk_cdata.msk_rx_ring_tag, 3362 sc_if->msk_cdata.msk_rx_ring_map, 3363 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3364 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 3365 PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 3366 } 3367 3368 static int 3369 msk_handle_events(struct msk_softc *sc) 3370 { 3371 struct msk_if_softc *sc_if; 3372 int rxput[2]; 3373 struct msk_stat_desc *sd; 3374 uint32_t control, status; 3375 int cons, idx, len, port, rxprog; 3376 3377 idx = CSR_READ_2(sc, STAT_PUT_IDX); 3378 if (idx == sc->msk_stat_cons) 3379 return (0); 3380 3381 /* Sync status LEs. */ 3382 bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 3383 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3384 /* XXX Sync Rx LEs here. */ 3385 3386 rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 3387 3388 rxprog = 0; 3389 for (cons = sc->msk_stat_cons; cons != idx;) { 3390 sd = &sc->msk_stat_ring[cons]; 3391 control = le32toh(sd->msk_control); 3392 if ((control & HW_OWNER) == 0) 3393 break; 3394 /* 3395 * Marvell's FreeBSD driver updates status LE after clearing 3396 * HW_OWNER. However we don't have a way to sync single LE 3397 * with bus_dma(9) API. bus_dma(9) provides a way to sync 3398 * an entire DMA map. So don't sync LE until we have a better 3399 * way to sync LEs. 3400 */ 3401 control &= ~HW_OWNER; 3402 sd->msk_control = htole32(control); 3403 status = le32toh(sd->msk_status); 3404 len = control & STLE_LEN_MASK; 3405 port = (control >> 16) & 0x01; 3406 sc_if = sc->msk_if[port]; 3407 if (sc_if == NULL) { 3408 device_printf(sc->msk_dev, "invalid port opcode " 3409 "0x%08x\n", control & STLE_OP_MASK); 3410 continue; 3411 } 3412 3413 switch (control & STLE_OP_MASK) { 3414 case OP_RXVLAN: 3415 sc_if->msk_vtag = ntohs(len); 3416 break; 3417 case OP_RXCHKSVLAN: 3418 sc_if->msk_vtag = ntohs(len); 3419 break; 3420 case OP_RXSTAT: 3421 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) 3422 msk_jumbo_rxeof(sc_if, status, len); 3423 else 3424 msk_rxeof(sc_if, status, len); 3425 rxprog++; 3426 /* 3427 * Because there is no way to sync single Rx LE 3428 * put the DMA sync operation off until the end of 3429 * event processing. 3430 */ 3431 rxput[port]++; 3432 /* Update prefetch unit if we've passed water mark. */ 3433 if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 3434 msk_rxput(sc_if); 3435 rxput[port] = 0; 3436 } 3437 break; 3438 case OP_TXINDEXLE: 3439 if (sc->msk_if[MSK_PORT_A] != NULL) 3440 msk_txeof(sc->msk_if[MSK_PORT_A], 3441 status & STLE_TXA1_MSKL); 3442 if (sc->msk_if[MSK_PORT_B] != NULL) 3443 msk_txeof(sc->msk_if[MSK_PORT_B], 3444 ((status & STLE_TXA2_MSKL) >> 3445 STLE_TXA2_SHIFTL) | 3446 ((len & STLE_TXA2_MSKH) << 3447 STLE_TXA2_SHIFTH)); 3448 break; 3449 default: 3450 device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 3451 control & STLE_OP_MASK); 3452 break; 3453 } 3454 MSK_INC(cons, MSK_STAT_RING_CNT); 3455 if (rxprog > sc->msk_process_limit) 3456 break; 3457 } 3458 3459 sc->msk_stat_cons = cons; 3460 /* XXX We should sync status LEs here. See above notes. */ 3461 3462 if (rxput[MSK_PORT_A] > 0) 3463 msk_rxput(sc->msk_if[MSK_PORT_A]); 3464 if (rxput[MSK_PORT_B] > 0) 3465 msk_rxput(sc->msk_if[MSK_PORT_B]); 3466 3467 return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 3468 } 3469 3470 /* Legacy interrupt handler for shared interrupt. */ 3471 static void 3472 msk_legacy_intr(void *xsc) 3473 { 3474 struct msk_softc *sc; 3475 struct msk_if_softc *sc_if0, *sc_if1; 3476 struct ifnet *ifp0, *ifp1; 3477 uint32_t status; 3478 3479 sc = xsc; 3480 MSK_LOCK(sc); 3481 3482 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3483 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3484 if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 || 3485 (status & sc->msk_intrmask) == 0) { 3486 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3487 return; 3488 } 3489 3490 sc_if0 = sc->msk_if[MSK_PORT_A]; 3491 sc_if1 = sc->msk_if[MSK_PORT_B]; 3492 ifp0 = ifp1 = NULL; 3493 if (sc_if0 != NULL) 3494 ifp0 = sc_if0->msk_ifp; 3495 if (sc_if1 != NULL) 3496 ifp1 = sc_if1->msk_ifp; 3497 3498 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3499 msk_intr_phy(sc_if0); 3500 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3501 msk_intr_phy(sc_if1); 3502 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3503 msk_intr_gmac(sc_if0); 3504 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3505 msk_intr_gmac(sc_if1); 3506 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3507 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3508 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3509 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3510 CSR_READ_4(sc, B0_IMSK); 3511 } 3512 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3513 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3514 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3515 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3516 CSR_READ_4(sc, B0_IMSK); 3517 } 3518 if ((status & Y2_IS_HW_ERR) != 0) 3519 msk_intr_hwerr(sc); 3520 3521 while (msk_handle_events(sc) != 0) 3522 ; 3523 if ((status & Y2_IS_STAT_BMU) != 0) 3524 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3525 3526 /* Reenable interrupts. */ 3527 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3528 3529 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3530 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3531 taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task); 3532 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3533 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3534 taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task); 3535 3536 MSK_UNLOCK(sc); 3537 } 3538 3539 static int 3540 msk_intr(void *xsc) 3541 { 3542 struct msk_softc *sc; 3543 uint32_t status; 3544 3545 sc = xsc; 3546 status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 3547 /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 3548 if (status == 0 || status == 0xffffffff) { 3549 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3550 return (FILTER_STRAY); 3551 } 3552 3553 taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task); 3554 return (FILTER_HANDLED); 3555 } 3556 3557 static void 3558 msk_int_task(void *arg, int pending) 3559 { 3560 struct msk_softc *sc; 3561 struct msk_if_softc *sc_if0, *sc_if1; 3562 struct ifnet *ifp0, *ifp1; 3563 uint32_t status; 3564 int domore; 3565 3566 sc = arg; 3567 MSK_LOCK(sc); 3568 3569 /* Get interrupt source. */ 3570 status = CSR_READ_4(sc, B0_ISRC); 3571 if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 || 3572 (status & sc->msk_intrmask) == 0) 3573 goto done; 3574 3575 sc_if0 = sc->msk_if[MSK_PORT_A]; 3576 sc_if1 = sc->msk_if[MSK_PORT_B]; 3577 ifp0 = ifp1 = NULL; 3578 if (sc_if0 != NULL) 3579 ifp0 = sc_if0->msk_ifp; 3580 if (sc_if1 != NULL) 3581 ifp1 = sc_if1->msk_ifp; 3582 3583 if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 3584 msk_intr_phy(sc_if0); 3585 if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 3586 msk_intr_phy(sc_if1); 3587 if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 3588 msk_intr_gmac(sc_if0); 3589 if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 3590 msk_intr_gmac(sc_if1); 3591 if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 3592 device_printf(sc->msk_dev, "Rx descriptor error\n"); 3593 sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 3594 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3595 CSR_READ_4(sc, B0_IMSK); 3596 } 3597 if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 3598 device_printf(sc->msk_dev, "Tx descriptor error\n"); 3599 sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 3600 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3601 CSR_READ_4(sc, B0_IMSK); 3602 } 3603 if ((status & Y2_IS_HW_ERR) != 0) 3604 msk_intr_hwerr(sc); 3605 3606 domore = msk_handle_events(sc); 3607 if ((status & Y2_IS_STAT_BMU) != 0) 3608 CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 3609 3610 if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3611 !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 3612 taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task); 3613 if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3614 !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 3615 taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task); 3616 3617 if (domore > 0) { 3618 taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task); 3619 MSK_UNLOCK(sc); 3620 return; 3621 } 3622 done: 3623 MSK_UNLOCK(sc); 3624 3625 /* Reenable interrupts. */ 3626 CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3627 } 3628 3629 static void 3630 msk_init(void *xsc) 3631 { 3632 struct msk_if_softc *sc_if = xsc; 3633 3634 MSK_IF_LOCK(sc_if); 3635 msk_init_locked(sc_if); 3636 MSK_IF_UNLOCK(sc_if); 3637 } 3638 3639 static void 3640 msk_init_locked(struct msk_if_softc *sc_if) 3641 { 3642 struct msk_softc *sc; 3643 struct ifnet *ifp; 3644 struct mii_data *mii; 3645 uint16_t eaddr[ETHER_ADDR_LEN / 2]; 3646 uint16_t gmac; 3647 int error, i; 3648 3649 MSK_IF_LOCK_ASSERT(sc_if); 3650 3651 ifp = sc_if->msk_ifp; 3652 sc = sc_if->msk_softc; 3653 mii = device_get_softc(sc_if->msk_miibus); 3654 3655 error = 0; 3656 /* Cancel pending I/O and free all Rx/Tx buffers. */ 3657 msk_stop(sc_if); 3658 3659 sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN + 3660 ETHER_VLAN_ENCAP_LEN; 3661 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN && 3662 sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 3663 /* 3664 * In Yukon EC Ultra, TSO & checksum offload is not 3665 * supported for jumbo frame. 3666 */ 3667 ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 3668 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 3669 } 3670 3671 /* 3672 * Initialize GMAC first. 3673 * Without this initialization, Rx MAC did not work as expected 3674 * and Rx MAC garbled status LEs and it resulted in out-of-order 3675 * or duplicated frame delivery which in turn showed very poor 3676 * Rx performance.(I had to write a packet analysis code that 3677 * could be embeded in driver to diagnose this issue.) 3678 * I've spent almost 2 months to fix this issue. If I have had 3679 * datasheet for Yukon II I wouldn't have encountered this. :-( 3680 */ 3681 gmac = GM_GPCR_SPEED_100 | GM_GPCR_SPEED_1000 | GM_GPCR_DUP_FULL; 3682 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 3683 3684 /* Dummy read the Interrupt Source Register. */ 3685 CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 3686 3687 /* Set MIB Clear Counter Mode. */ 3688 gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 3689 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 3690 /* Read all MIB Counters with Clear Mode set. */ 3691 for (i = 0; i < GM_MIB_CNT_SIZE; i++) 3692 GMAC_READ_2(sc, sc_if->msk_port, GM_MIB_CNT_BASE + 8 * i); 3693 /* Clear MIB Clear Counter Mode. */ 3694 gmac &= ~GM_PAR_MIB_CLR; 3695 GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 3696 3697 /* Disable FCS. */ 3698 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 3699 3700 /* Setup Transmit Control Register. */ 3701 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 3702 3703 /* Setup Transmit Flow Control Register. */ 3704 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 3705 3706 /* Setup Transmit Parameter Register. */ 3707 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 3708 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 3709 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 3710 3711 gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 3712 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 3713 3714 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) 3715 gmac |= GM_SMOD_JUMBO_ENA; 3716 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 3717 3718 /* Set station address. */ 3719 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3720 for (i = 0; i < ETHER_ADDR_LEN /2; i++) 3721 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L + i * 4, 3722 eaddr[i]); 3723 for (i = 0; i < ETHER_ADDR_LEN /2; i++) 3724 GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L + i * 4, 3725 eaddr[i]); 3726 3727 /* Disable interrupts for counter overflows. */ 3728 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 3729 GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 3730 GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 3731 3732 /* Configure Rx MAC FIFO. */ 3733 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 3734 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 3735 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 3736 GMF_OPER_ON | GMF_RX_F_FL_ON); 3737 3738 /* Set promiscuous mode. */ 3739 msk_setpromisc(sc_if); 3740 3741 /* Set multicast filter. */ 3742 msk_setmulti(sc_if); 3743 3744 /* Flush Rx MAC FIFO on any flow control or error. */ 3745 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 3746 GMR_FS_ANY_ERR); 3747 3748 /* Set Rx FIFO flush threshold to 64 bytes. */ 3749 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), 3750 RX_GMF_FL_THR_DEF); 3751 3752 /* Configure Tx MAC FIFO. */ 3753 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 3754 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 3755 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 3756 3757 /* Configure hardware VLAN tag insertion/stripping. */ 3758 msk_setvlan(sc_if, ifp); 3759 3760 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 3761 /* Set Rx Pause threshould. */ 3762 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 3763 MSK_ECU_LLPP); 3764 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 3765 MSK_ECU_ULPP); 3766 if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) { 3767 /* 3768 * Set Tx GMAC FIFO Almost Empty Threshold. 3769 */ 3770 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3771 MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 3772 /* Disable Store & Forward mode for Tx. */ 3773 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3774 TX_JUMBO_ENA | TX_STFW_DIS); 3775 } else { 3776 /* Enable Store & Forward mode for Tx. */ 3777 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3778 TX_JUMBO_DIS | TX_STFW_ENA); 3779 } 3780 } 3781 3782 /* 3783 * Disable Force Sync bit and Alloc bit in Tx RAM interface 3784 * arbiter as we don't use Sync Tx queue. 3785 */ 3786 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 3787 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 3788 /* Enable the RAM Interface Arbiter. */ 3789 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 3790 3791 /* Setup RAM buffer. */ 3792 msk_set_rambuffer(sc_if); 3793 3794 /* Disable Tx sync Queue. */ 3795 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 3796 3797 /* Setup Tx Queue Bus Memory Interface. */ 3798 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 3799 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 3800 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 3801 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 3802 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3803 sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 3804 /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 3805 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), MSK_ECU_TXFF_LEV); 3806 } 3807 3808 /* Setup Rx Queue Bus Memory Interface. */ 3809 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 3810 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 3811 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 3812 CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 3813 if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 3814 sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 3815 /* MAC Rx RAM Read is controlled by hardware. */ 3816 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 3817 } 3818 3819 msk_set_prefetch(sc, sc_if->msk_txq, 3820 sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 3821 msk_init_tx_ring(sc_if); 3822 3823 /* Disable Rx checksum offload and RSS hash. */ 3824 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 3825 BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH); 3826 if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) { 3827 msk_set_prefetch(sc, sc_if->msk_rxq, 3828 sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 3829 MSK_JUMBO_RX_RING_CNT - 1); 3830 error = msk_init_jumbo_rx_ring(sc_if); 3831 } else { 3832 msk_set_prefetch(sc, sc_if->msk_rxq, 3833 sc_if->msk_rdata.msk_rx_ring_paddr, 3834 MSK_RX_RING_CNT - 1); 3835 error = msk_init_rx_ring(sc_if); 3836 } 3837 if (error != 0) { 3838 device_printf(sc_if->msk_if_dev, 3839 "initialization failed: no memory for Rx buffers\n"); 3840 msk_stop(sc_if); 3841 return; 3842 } 3843 3844 /* Configure interrupt handling. */ 3845 if (sc_if->msk_port == MSK_PORT_A) { 3846 sc->msk_intrmask |= Y2_IS_PORT_A; 3847 sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 3848 } else { 3849 sc->msk_intrmask |= Y2_IS_PORT_B; 3850 sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 3851 } 3852 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3853 CSR_READ_4(sc, B0_HWE_IMSK); 3854 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3855 CSR_READ_4(sc, B0_IMSK); 3856 3857 sc_if->msk_link = 0; 3858 mii_mediachg(mii); 3859 3860 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3861 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3862 3863 callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 3864 } 3865 3866 static void 3867 msk_set_rambuffer(struct msk_if_softc *sc_if) 3868 { 3869 struct msk_softc *sc; 3870 int ltpp, utpp; 3871 3872 sc = sc_if->msk_softc; 3873 3874 /* Setup Rx Queue. */ 3875 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 3876 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 3877 sc->msk_rxqstart[sc_if->msk_port] / 8); 3878 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 3879 sc->msk_rxqend[sc_if->msk_port] / 8); 3880 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 3881 sc->msk_rxqstart[sc_if->msk_port] / 8); 3882 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 3883 sc->msk_rxqstart[sc_if->msk_port] / 8); 3884 3885 utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3886 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 3887 ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 3888 sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 3889 if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 3890 ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 3891 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 3892 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 3893 /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 3894 3895 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 3896 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 3897 3898 /* Setup Tx Queue. */ 3899 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 3900 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 3901 sc->msk_txqstart[sc_if->msk_port] / 8); 3902 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 3903 sc->msk_txqend[sc_if->msk_port] / 8); 3904 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 3905 sc->msk_txqstart[sc_if->msk_port] / 8); 3906 CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 3907 sc->msk_txqstart[sc_if->msk_port] / 8); 3908 /* Enable Store & Forward for Tx side. */ 3909 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 3910 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 3911 CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 3912 } 3913 3914 static void 3915 msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 3916 uint32_t count) 3917 { 3918 3919 /* Reset the prefetch unit. */ 3920 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3921 PREF_UNIT_RST_SET); 3922 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3923 PREF_UNIT_RST_CLR); 3924 /* Set LE base address. */ 3925 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 3926 MSK_ADDR_LO(addr)); 3927 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 3928 MSK_ADDR_HI(addr)); 3929 /* Set the list last index. */ 3930 CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 3931 count); 3932 /* Turn on prefetch unit. */ 3933 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 3934 PREF_UNIT_OP_ON); 3935 /* Dummy read to ensure write. */ 3936 CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 3937 } 3938 3939 static void 3940 msk_stop(struct msk_if_softc *sc_if) 3941 { 3942 struct msk_softc *sc; 3943 struct msk_txdesc *txd; 3944 struct msk_rxdesc *rxd; 3945 struct msk_rxdesc *jrxd; 3946 struct ifnet *ifp; 3947 uint32_t val; 3948 int i; 3949 3950 MSK_IF_LOCK_ASSERT(sc_if); 3951 sc = sc_if->msk_softc; 3952 ifp = sc_if->msk_ifp; 3953 3954 callout_stop(&sc_if->msk_tick_ch); 3955 sc_if->msk_watchdog_timer = 0; 3956 3957 /* Disable interrupts. */ 3958 if (sc_if->msk_port == MSK_PORT_A) { 3959 sc->msk_intrmask &= ~Y2_IS_PORT_A; 3960 sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 3961 } else { 3962 sc->msk_intrmask &= ~Y2_IS_PORT_B; 3963 sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 3964 } 3965 CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 3966 CSR_READ_4(sc, B0_HWE_IMSK); 3967 CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 3968 CSR_READ_4(sc, B0_IMSK); 3969 3970 /* Disable Tx/Rx MAC. */ 3971 val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 3972 val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 3973 GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 3974 /* Read again to ensure writing. */ 3975 GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 3976 3977 /* Stop Tx BMU. */ 3978 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 3979 val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 3980 for (i = 0; i < MSK_TIMEOUT; i++) { 3981 if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 3982 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 3983 BMU_STOP); 3984 CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 3985 } else 3986 break; 3987 DELAY(1); 3988 } 3989 if (i == MSK_TIMEOUT) 3990 device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 3991 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 3992 RB_RST_SET | RB_DIS_OP_MD); 3993 3994 /* Disable all GMAC interrupt. */ 3995 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 3996 /* Disable PHY interrupt. */ 3997 msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 3998 3999 /* Disable the RAM Interface Arbiter. */ 4000 CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 4001 4002 /* Reset the PCI FIFO of the async Tx queue */ 4003 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 4004 BMU_RST_SET | BMU_FIFO_RST); 4005 4006 /* Reset the Tx prefetch units. */ 4007 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 4008 PREF_UNIT_RST_SET); 4009 4010 /* Reset the RAM Buffer async Tx queue. */ 4011 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 4012 4013 /* Reset Tx MAC FIFO. */ 4014 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 4015 /* Set Pause Off. */ 4016 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 4017 4018 /* 4019 * The Rx Stop command will not work for Yukon-2 if the BMU does not 4020 * reach the end of packet and since we can't make sure that we have 4021 * incoming data, we must reset the BMU while it is not during a DMA 4022 * transfer. Since it is possible that the Rx path is still active, 4023 * the Rx RAM buffer will be stopped first, so any possible incoming 4024 * data will not trigger a DMA. After the RAM buffer is stopped, the 4025 * BMU is polled until any DMA in progress is ended and only then it 4026 * will be reset. 4027 */ 4028 4029 /* Disable the RAM Buffer receive queue. */ 4030 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 4031 for (i = 0; i < MSK_TIMEOUT; i++) { 4032 if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 4033 CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 4034 break; 4035 DELAY(1); 4036 } 4037 if (i == MSK_TIMEOUT) 4038 device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 4039 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 4040 BMU_RST_SET | BMU_FIFO_RST); 4041 /* Reset the Rx prefetch unit. */ 4042 CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 4043 PREF_UNIT_RST_SET); 4044 /* Reset the RAM Buffer receive queue. */ 4045 CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 4046 /* Reset Rx MAC FIFO. */ 4047 CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 4048 4049 /* Free Rx and Tx mbufs still in the queues. */ 4050 for (i = 0; i < MSK_RX_RING_CNT; i++) { 4051 rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 4052 if (rxd->rx_m != NULL) { 4053 bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 4054 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4055 bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 4056 rxd->rx_dmamap); 4057 m_freem(rxd->rx_m); 4058 rxd->rx_m = NULL; 4059 } 4060 } 4061 for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 4062 jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 4063 if (jrxd->rx_m != NULL) { 4064 bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 4065 jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4066 bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 4067 jrxd->rx_dmamap); 4068 m_freem(jrxd->rx_m); 4069 jrxd->rx_m = NULL; 4070 } 4071 } 4072 for (i = 0; i < MSK_TX_RING_CNT; i++) { 4073 txd = &sc_if->msk_cdata.msk_txdesc[i]; 4074 if (txd->tx_m != NULL) { 4075 bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 4076 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4077 bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 4078 txd->tx_dmamap); 4079 m_freem(txd->tx_m); 4080 txd->tx_m = NULL; 4081 } 4082 } 4083 4084 /* 4085 * Mark the interface down. 4086 */ 4087 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4088 sc_if->msk_link = 0; 4089 } 4090 4091 static int 4092 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4093 { 4094 int error, value; 4095 4096 if (!arg1) 4097 return (EINVAL); 4098 value = *(int *)arg1; 4099 error = sysctl_handle_int(oidp, &value, 0, req); 4100 if (error || !req->newptr) 4101 return (error); 4102 if (value < low || value > high) 4103 return (EINVAL); 4104 *(int *)arg1 = value; 4105 4106 return (0); 4107 } 4108 4109 static int 4110 sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 4111 { 4112 4113 return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 4114 MSK_PROC_MAX)); 4115 } 4116