xref: /freebsd/sys/dev/msk/if_msk.c (revision c6a34f768e4e3873c69d5a9f345d01a8fabc186c)
10dbe28b3SPyun YongHyeon /******************************************************************************
20dbe28b3SPyun YongHyeon  *
30dbe28b3SPyun YongHyeon  * Name   : sky2.c
40dbe28b3SPyun YongHyeon  * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x
50dbe28b3SPyun YongHyeon  * Version: $Revision: 1.23 $
60dbe28b3SPyun YongHyeon  * Date   : $Date: 2005/12/22 09:04:11 $
70dbe28b3SPyun YongHyeon  * Purpose: Main driver source file
80dbe28b3SPyun YongHyeon  *
90dbe28b3SPyun YongHyeon  *****************************************************************************/
100dbe28b3SPyun YongHyeon 
110dbe28b3SPyun YongHyeon /******************************************************************************
120dbe28b3SPyun YongHyeon  *
130dbe28b3SPyun YongHyeon  *	LICENSE:
140dbe28b3SPyun YongHyeon  *	Copyright (C) Marvell International Ltd. and/or its affiliates
150dbe28b3SPyun YongHyeon  *
160dbe28b3SPyun YongHyeon  *	The computer program files contained in this folder ("Files")
170dbe28b3SPyun YongHyeon  *	are provided to you under the BSD-type license terms provided
180dbe28b3SPyun YongHyeon  *	below, and any use of such Files and any derivative works
190dbe28b3SPyun YongHyeon  *	thereof created by you shall be governed by the following terms
200dbe28b3SPyun YongHyeon  *	and conditions:
210dbe28b3SPyun YongHyeon  *
220dbe28b3SPyun YongHyeon  *	- Redistributions of source code must retain the above copyright
230dbe28b3SPyun YongHyeon  *	  notice, this list of conditions and the following disclaimer.
240dbe28b3SPyun YongHyeon  *	- Redistributions in binary form must reproduce the above
250dbe28b3SPyun YongHyeon  *	  copyright notice, this list of conditions and the following
260dbe28b3SPyun YongHyeon  *	  disclaimer in the documentation and/or other materials provided
270dbe28b3SPyun YongHyeon  *	  with the distribution.
280dbe28b3SPyun YongHyeon  *	- Neither the name of Marvell nor the names of its contributors
290dbe28b3SPyun YongHyeon  *	  may be used to endorse or promote products derived from this
300dbe28b3SPyun YongHyeon  *	  software without specific prior written permission.
310dbe28b3SPyun YongHyeon  *
320dbe28b3SPyun YongHyeon  *	THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
330dbe28b3SPyun YongHyeon  *	"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
340dbe28b3SPyun YongHyeon  *	LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
350dbe28b3SPyun YongHyeon  *	FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
360dbe28b3SPyun YongHyeon  *	COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
370dbe28b3SPyun YongHyeon  *	INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
380dbe28b3SPyun YongHyeon  *	BUT NOT LIMITED TO, PROCUREMENT OF  SUBSTITUTE GOODS OR SERVICES;
390dbe28b3SPyun YongHyeon  *	LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
400dbe28b3SPyun YongHyeon  *	HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
410dbe28b3SPyun YongHyeon  *	STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
420dbe28b3SPyun YongHyeon  *	ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
430dbe28b3SPyun YongHyeon  *	OF THE POSSIBILITY OF SUCH DAMAGE.
440dbe28b3SPyun YongHyeon  *	/LICENSE
450dbe28b3SPyun YongHyeon  *
460dbe28b3SPyun YongHyeon  *****************************************************************************/
470dbe28b3SPyun YongHyeon 
480dbe28b3SPyun YongHyeon /*-
490dbe28b3SPyun YongHyeon  * Copyright (c) 1997, 1998, 1999, 2000
500dbe28b3SPyun YongHyeon  *	Bill Paul <wpaul@ctr.columbia.edu>.  All rights reserved.
510dbe28b3SPyun YongHyeon  *
520dbe28b3SPyun YongHyeon  * Redistribution and use in source and binary forms, with or without
530dbe28b3SPyun YongHyeon  * modification, are permitted provided that the following conditions
540dbe28b3SPyun YongHyeon  * are met:
550dbe28b3SPyun YongHyeon  * 1. Redistributions of source code must retain the above copyright
560dbe28b3SPyun YongHyeon  *    notice, this list of conditions and the following disclaimer.
570dbe28b3SPyun YongHyeon  * 2. Redistributions in binary form must reproduce the above copyright
580dbe28b3SPyun YongHyeon  *    notice, this list of conditions and the following disclaimer in the
590dbe28b3SPyun YongHyeon  *    documentation and/or other materials provided with the distribution.
600dbe28b3SPyun YongHyeon  * 3. All advertising materials mentioning features or use of this software
610dbe28b3SPyun YongHyeon  *    must display the following acknowledgement:
620dbe28b3SPyun YongHyeon  *	This product includes software developed by Bill Paul.
630dbe28b3SPyun YongHyeon  * 4. Neither the name of the author nor the names of any co-contributors
640dbe28b3SPyun YongHyeon  *    may be used to endorse or promote products derived from this software
650dbe28b3SPyun YongHyeon  *    without specific prior written permission.
660dbe28b3SPyun YongHyeon  *
670dbe28b3SPyun YongHyeon  * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
680dbe28b3SPyun YongHyeon  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
690dbe28b3SPyun YongHyeon  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
700dbe28b3SPyun YongHyeon  * ARE DISCLAIMED.  IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
710dbe28b3SPyun YongHyeon  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
720dbe28b3SPyun YongHyeon  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
730dbe28b3SPyun YongHyeon  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
740dbe28b3SPyun YongHyeon  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
750dbe28b3SPyun YongHyeon  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
760dbe28b3SPyun YongHyeon  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
770dbe28b3SPyun YongHyeon  * THE POSSIBILITY OF SUCH DAMAGE.
780dbe28b3SPyun YongHyeon  */
790dbe28b3SPyun YongHyeon /*-
800dbe28b3SPyun YongHyeon  * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu>
810dbe28b3SPyun YongHyeon  *
820dbe28b3SPyun YongHyeon  * Permission to use, copy, modify, and distribute this software for any
830dbe28b3SPyun YongHyeon  * purpose with or without fee is hereby granted, provided that the above
840dbe28b3SPyun YongHyeon  * copyright notice and this permission notice appear in all copies.
850dbe28b3SPyun YongHyeon  *
860dbe28b3SPyun YongHyeon  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
870dbe28b3SPyun YongHyeon  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
880dbe28b3SPyun YongHyeon  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
890dbe28b3SPyun YongHyeon  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
900dbe28b3SPyun YongHyeon  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
910dbe28b3SPyun YongHyeon  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
920dbe28b3SPyun YongHyeon  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
930dbe28b3SPyun YongHyeon  */
940dbe28b3SPyun YongHyeon 
950dbe28b3SPyun YongHyeon /*
960dbe28b3SPyun YongHyeon  * Device driver for the Marvell Yukon II Ethernet controller.
970dbe28b3SPyun YongHyeon  * Due to lack of documentation, this driver is based on the code from
980dbe28b3SPyun YongHyeon  * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x.
990dbe28b3SPyun YongHyeon  */
1000dbe28b3SPyun YongHyeon 
1010dbe28b3SPyun YongHyeon #include <sys/cdefs.h>
1020dbe28b3SPyun YongHyeon __FBSDID("$FreeBSD$");
1030dbe28b3SPyun YongHyeon 
1040dbe28b3SPyun YongHyeon #include <sys/param.h>
1050dbe28b3SPyun YongHyeon #include <sys/systm.h>
1060dbe28b3SPyun YongHyeon #include <sys/bus.h>
1070dbe28b3SPyun YongHyeon #include <sys/endian.h>
1080dbe28b3SPyun YongHyeon #include <sys/mbuf.h>
1090dbe28b3SPyun YongHyeon #include <sys/malloc.h>
1100dbe28b3SPyun YongHyeon #include <sys/kernel.h>
1110dbe28b3SPyun YongHyeon #include <sys/module.h>
1120dbe28b3SPyun YongHyeon #include <sys/socket.h>
1130dbe28b3SPyun YongHyeon #include <sys/sockio.h>
1140dbe28b3SPyun YongHyeon #include <sys/queue.h>
1150dbe28b3SPyun YongHyeon #include <sys/sysctl.h>
1160dbe28b3SPyun YongHyeon 
1170dbe28b3SPyun YongHyeon #include <net/bpf.h>
1180dbe28b3SPyun YongHyeon #include <net/ethernet.h>
1190dbe28b3SPyun YongHyeon #include <net/if.h>
12067784314SPoul-Henning Kamp #include <net/if_arp.h>
1210dbe28b3SPyun YongHyeon #include <net/if_dl.h>
1220dbe28b3SPyun YongHyeon #include <net/if_media.h>
1230dbe28b3SPyun YongHyeon #include <net/if_types.h>
1240dbe28b3SPyun YongHyeon #include <net/if_vlan_var.h>
1250dbe28b3SPyun YongHyeon 
1260dbe28b3SPyun YongHyeon #include <netinet/in.h>
12767784314SPoul-Henning Kamp #include <netinet/in_systm.h>
1280dbe28b3SPyun YongHyeon #include <netinet/ip.h>
1290dbe28b3SPyun YongHyeon #include <netinet/tcp.h>
13067784314SPoul-Henning Kamp #include <netinet/udp.h>
1310dbe28b3SPyun YongHyeon 
1320dbe28b3SPyun YongHyeon #include <machine/bus.h>
133b5898b80SPyun YongHyeon #include <machine/in_cksum.h>
1340dbe28b3SPyun YongHyeon #include <machine/resource.h>
1350dbe28b3SPyun YongHyeon #include <sys/rman.h>
1360dbe28b3SPyun YongHyeon 
13767784314SPoul-Henning Kamp #include <dev/mii/mii.h>
1380dbe28b3SPyun YongHyeon #include <dev/mii/miivar.h>
1390dbe28b3SPyun YongHyeon 
1400dbe28b3SPyun YongHyeon #include <dev/pci/pcireg.h>
1410dbe28b3SPyun YongHyeon #include <dev/pci/pcivar.h>
1420dbe28b3SPyun YongHyeon 
1430dbe28b3SPyun YongHyeon #include <dev/msk/if_mskreg.h>
1440dbe28b3SPyun YongHyeon 
1450dbe28b3SPyun YongHyeon MODULE_DEPEND(msk, pci, 1, 1, 1);
1460dbe28b3SPyun YongHyeon MODULE_DEPEND(msk, ether, 1, 1, 1);
1470dbe28b3SPyun YongHyeon MODULE_DEPEND(msk, miibus, 1, 1, 1);
1480dbe28b3SPyun YongHyeon 
1490dbe28b3SPyun YongHyeon /* "device miibus" required.  See GENERIC if you get errors here. */
1500dbe28b3SPyun YongHyeon #include "miibus_if.h"
1510dbe28b3SPyun YongHyeon 
1520dbe28b3SPyun YongHyeon /* Tunables. */
1530dbe28b3SPyun YongHyeon static int msi_disable = 0;
1540dbe28b3SPyun YongHyeon TUNABLE_INT("hw.msk.msi_disable", &msi_disable);
15553dcfbd1SPyun YongHyeon static int legacy_intr = 0;
15653dcfbd1SPyun YongHyeon TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr);
15785b340cbSPyun YongHyeon static int jumbo_disable = 0;
15885b340cbSPyun YongHyeon TUNABLE_INT("hw.msk.jumbo_disable", &jumbo_disable);
1590dbe28b3SPyun YongHyeon 
1600dbe28b3SPyun YongHyeon #define MSK_CSUM_FEATURES	(CSUM_TCP | CSUM_UDP)
1610dbe28b3SPyun YongHyeon 
1620dbe28b3SPyun YongHyeon /*
1630dbe28b3SPyun YongHyeon  * Devices supported by this driver.
1640dbe28b3SPyun YongHyeon  */
1650dbe28b3SPyun YongHyeon static struct msk_product {
1660dbe28b3SPyun YongHyeon 	uint16_t	msk_vendorid;
1670dbe28b3SPyun YongHyeon 	uint16_t	msk_deviceid;
1680dbe28b3SPyun YongHyeon 	const char	*msk_name;
1690dbe28b3SPyun YongHyeon } msk_products[] = {
1700dbe28b3SPyun YongHyeon 	{ VENDORID_SK, DEVICEID_SK_YUKON2,
1710dbe28b3SPyun YongHyeon 	    "SK-9Sxx Gigabit Ethernet" },
1720dbe28b3SPyun YongHyeon 	{ VENDORID_SK, DEVICEID_SK_YUKON2_EXPR,
1730dbe28b3SPyun YongHyeon 	    "SK-9Exx Gigabit Ethernet"},
1740dbe28b3SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_8021CU,
1750dbe28b3SPyun YongHyeon 	    "Marvell Yukon 88E8021CU Gigabit Ethernet" },
1760dbe28b3SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_8021X,
1770dbe28b3SPyun YongHyeon 	    "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" },
1780dbe28b3SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_8022CU,
1790dbe28b3SPyun YongHyeon 	    "Marvell Yukon 88E8022CU Gigabit Ethernet" },
1800dbe28b3SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_8022X,
1810dbe28b3SPyun YongHyeon 	    "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" },
1820dbe28b3SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_8061CU,
1830dbe28b3SPyun YongHyeon 	    "Marvell Yukon 88E8061CU Gigabit Ethernet" },
1840dbe28b3SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_8061X,
1850dbe28b3SPyun YongHyeon 	    "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" },
1860dbe28b3SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_8062CU,
1870dbe28b3SPyun YongHyeon 	    "Marvell Yukon 88E8062CU Gigabit Ethernet" },
1880dbe28b3SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_8062X,
1890dbe28b3SPyun YongHyeon 	    "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" },
1900dbe28b3SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_8035,
191f972d4c6SPyun YongHyeon 	    "Marvell Yukon 88E8035 Fast Ethernet" },
1920dbe28b3SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_8036,
193f972d4c6SPyun YongHyeon 	    "Marvell Yukon 88E8036 Fast Ethernet" },
1940dbe28b3SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_8038,
195f972d4c6SPyun YongHyeon 	    "Marvell Yukon 88E8038 Fast Ethernet" },
19628d34c0eSRemko Lodder 	{ VENDORID_MARVELL, DEVICEID_MRVL_8039,
197f972d4c6SPyun YongHyeon 	    "Marvell Yukon 88E8039 Fast Ethernet" },
19812909985SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_8040,
19912909985SPyun YongHyeon 	    "Marvell Yukon 88E8040 Fast Ethernet" },
20012909985SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_8040T,
20112909985SPyun YongHyeon 	    "Marvell Yukon 88E8040T Fast Ethernet" },
2020e0ed74fSUlf Lilleengen 	{ VENDORID_MARVELL, DEVICEID_MRVL_8042,
2030e0ed74fSUlf Lilleengen 	    "Marvell Yukon 88E8042 Fast Ethernet" },
20412909985SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_8048,
20512909985SPyun YongHyeon 	    "Marvell Yukon 88E8048 Fast Ethernet" },
2060dbe28b3SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_4361,
2070dbe28b3SPyun YongHyeon 	    "Marvell Yukon 88E8050 Gigabit Ethernet" },
2080dbe28b3SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_4360,
2090dbe28b3SPyun YongHyeon 	    "Marvell Yukon 88E8052 Gigabit Ethernet" },
2100dbe28b3SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_4362,
2110dbe28b3SPyun YongHyeon 	    "Marvell Yukon 88E8053 Gigabit Ethernet" },
2120dbe28b3SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_4363,
2130dbe28b3SPyun YongHyeon 	    "Marvell Yukon 88E8055 Gigabit Ethernet" },
2140dbe28b3SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_4364,
2150dbe28b3SPyun YongHyeon 	    "Marvell Yukon 88E8056 Gigabit Ethernet" },
216a56fe1f0SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_4365,
217a56fe1f0SPyun YongHyeon 	    "Marvell Yukon 88E8070 Gigabit Ethernet" },
21875ef16dfSPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_436A,
21975ef16dfSPyun YongHyeon 	    "Marvell Yukon 88E8058 Gigabit Ethernet" },
220a56fe1f0SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_436B,
221a56fe1f0SPyun YongHyeon 	    "Marvell Yukon 88E8071 Gigabit Ethernet" },
222a56fe1f0SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_436C,
223a56fe1f0SPyun YongHyeon 	    "Marvell Yukon 88E8072 Gigabit Ethernet" },
22476202a16SPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_4380,
22576202a16SPyun YongHyeon 	    "Marvell Yukon 88E8057 Gigabit Ethernet" },
226e19bd6eeSPyun YongHyeon 	{ VENDORID_MARVELL, DEVICEID_MRVL_4381,
227e19bd6eeSPyun YongHyeon 	    "Marvell Yukon 88E8059 Gigabit Ethernet" },
2280dbe28b3SPyun YongHyeon 	{ VENDORID_DLINK, DEVICEID_DLINK_DGE550SX,
2290dbe28b3SPyun YongHyeon 	    "D-Link 550SX Gigabit Ethernet" },
23060d3251aSPyun YongHyeon 	{ VENDORID_DLINK, DEVICEID_DLINK_DGE560SX,
23160d3251aSPyun YongHyeon 	    "D-Link 560SX Gigabit Ethernet" },
2320dbe28b3SPyun YongHyeon 	{ VENDORID_DLINK, DEVICEID_DLINK_DGE560T,
2330dbe28b3SPyun YongHyeon 	    "D-Link 560T Gigabit Ethernet" }
2340dbe28b3SPyun YongHyeon };
2350dbe28b3SPyun YongHyeon 
2360dbe28b3SPyun YongHyeon static const char *model_name[] = {
2370dbe28b3SPyun YongHyeon 	"Yukon XL",
2380dbe28b3SPyun YongHyeon         "Yukon EC Ultra",
239daf29227SPyun YongHyeon         "Yukon EX",
2400dbe28b3SPyun YongHyeon         "Yukon EC",
24161708f4cSPyun YongHyeon         "Yukon FE",
24276202a16SPyun YongHyeon         "Yukon FE+",
24376202a16SPyun YongHyeon         "Yukon Supreme",
244e19bd6eeSPyun YongHyeon         "Yukon Ultra 2",
245e19bd6eeSPyun YongHyeon         "Yukon Unknown",
246e19bd6eeSPyun YongHyeon         "Yukon Optima",
2470dbe28b3SPyun YongHyeon };
2480dbe28b3SPyun YongHyeon 
2490dbe28b3SPyun YongHyeon static int mskc_probe(device_t);
2500dbe28b3SPyun YongHyeon static int mskc_attach(device_t);
2510dbe28b3SPyun YongHyeon static int mskc_detach(device_t);
2526a087a87SPyun YongHyeon static int mskc_shutdown(device_t);
2530dbe28b3SPyun YongHyeon static int mskc_setup_rambuffer(struct msk_softc *);
2540dbe28b3SPyun YongHyeon static int mskc_suspend(device_t);
2550dbe28b3SPyun YongHyeon static int mskc_resume(device_t);
2560dbe28b3SPyun YongHyeon static void mskc_reset(struct msk_softc *);
2570dbe28b3SPyun YongHyeon 
2580dbe28b3SPyun YongHyeon static int msk_probe(device_t);
2590dbe28b3SPyun YongHyeon static int msk_attach(device_t);
2600dbe28b3SPyun YongHyeon static int msk_detach(device_t);
2610dbe28b3SPyun YongHyeon 
2620dbe28b3SPyun YongHyeon static void msk_tick(void *);
263c876b43fSPyun YongHyeon static void msk_intr(void *);
2640dbe28b3SPyun YongHyeon static void msk_intr_phy(struct msk_if_softc *);
2650dbe28b3SPyun YongHyeon static void msk_intr_gmac(struct msk_if_softc *);
2660dbe28b3SPyun YongHyeon static __inline void msk_rxput(struct msk_if_softc *);
2670dbe28b3SPyun YongHyeon static int msk_handle_events(struct msk_softc *);
2680dbe28b3SPyun YongHyeon static void msk_handle_hwerr(struct msk_if_softc *, uint32_t);
2690dbe28b3SPyun YongHyeon static void msk_intr_hwerr(struct msk_softc *);
27083c04c93SPyun YongHyeon #ifndef __NO_STRICT_ALIGNMENT
27183c04c93SPyun YongHyeon static __inline void msk_fixup_rx(struct mbuf *);
27283c04c93SPyun YongHyeon #endif
273388214e4SPyun YongHyeon static __inline void msk_rxcsum(struct msk_if_softc *, uint32_t, struct mbuf *);
274efb74172SPyun YongHyeon static void msk_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int);
275efb74172SPyun YongHyeon static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, uint32_t, int);
2760dbe28b3SPyun YongHyeon static void msk_txeof(struct msk_if_softc *, int);
2770dbe28b3SPyun YongHyeon static int msk_encap(struct msk_if_softc *, struct mbuf **);
2780dbe28b3SPyun YongHyeon static void msk_start(struct ifnet *);
279c876b43fSPyun YongHyeon static void msk_start_locked(struct ifnet *);
2800dbe28b3SPyun YongHyeon static int msk_ioctl(struct ifnet *, u_long, caddr_t);
2810dbe28b3SPyun YongHyeon static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t);
2820dbe28b3SPyun YongHyeon static void msk_set_rambuffer(struct msk_if_softc *);
283efb74172SPyun YongHyeon static void msk_set_tx_stfwd(struct msk_if_softc *);
2840dbe28b3SPyun YongHyeon static void msk_init(void *);
2850dbe28b3SPyun YongHyeon static void msk_init_locked(struct msk_if_softc *);
2860dbe28b3SPyun YongHyeon static void msk_stop(struct msk_if_softc *);
2872271eac7SPyun YongHyeon static void msk_watchdog(struct msk_if_softc *);
2880dbe28b3SPyun YongHyeon static int msk_mediachange(struct ifnet *);
2890dbe28b3SPyun YongHyeon static void msk_mediastatus(struct ifnet *, struct ifmediareq *);
2900dbe28b3SPyun YongHyeon static void msk_phy_power(struct msk_softc *, int);
2910dbe28b3SPyun YongHyeon static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int);
2920dbe28b3SPyun YongHyeon static int msk_status_dma_alloc(struct msk_softc *);
2930dbe28b3SPyun YongHyeon static void msk_status_dma_free(struct msk_softc *);
2940dbe28b3SPyun YongHyeon static int msk_txrx_dma_alloc(struct msk_if_softc *);
29585b340cbSPyun YongHyeon static int msk_rx_dma_jalloc(struct msk_if_softc *);
2960dbe28b3SPyun YongHyeon static void msk_txrx_dma_free(struct msk_if_softc *);
29785b340cbSPyun YongHyeon static void msk_rx_dma_jfree(struct msk_if_softc *);
298388214e4SPyun YongHyeon static int msk_rx_fill(struct msk_if_softc *, int);
2990dbe28b3SPyun YongHyeon static int msk_init_rx_ring(struct msk_if_softc *);
3000dbe28b3SPyun YongHyeon static int msk_init_jumbo_rx_ring(struct msk_if_softc *);
3010dbe28b3SPyun YongHyeon static void msk_init_tx_ring(struct msk_if_softc *);
3020dbe28b3SPyun YongHyeon static __inline void msk_discard_rxbuf(struct msk_if_softc *, int);
3030dbe28b3SPyun YongHyeon static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int);
3040dbe28b3SPyun YongHyeon static int msk_newbuf(struct msk_if_softc *, int);
3050dbe28b3SPyun YongHyeon static int msk_jumbo_newbuf(struct msk_if_softc *, int);
3060dbe28b3SPyun YongHyeon 
3070dbe28b3SPyun YongHyeon static int msk_phy_readreg(struct msk_if_softc *, int, int);
3080dbe28b3SPyun YongHyeon static int msk_phy_writereg(struct msk_if_softc *, int, int, int);
3090dbe28b3SPyun YongHyeon static int msk_miibus_readreg(device_t, int, int);
3100dbe28b3SPyun YongHyeon static int msk_miibus_writereg(device_t, int, int, int);
3110dbe28b3SPyun YongHyeon static void msk_miibus_statchg(device_t);
3120dbe28b3SPyun YongHyeon 
3136d6588a1SPyun YongHyeon static void msk_rxfilter(struct msk_if_softc *);
3140dbe28b3SPyun YongHyeon static void msk_setvlan(struct msk_if_softc *, struct ifnet *);
3150dbe28b3SPyun YongHyeon 
3163a91ee71SPyun YongHyeon static void msk_stats_clear(struct msk_if_softc *);
3173a91ee71SPyun YongHyeon static void msk_stats_update(struct msk_if_softc *);
3183a91ee71SPyun YongHyeon static int msk_sysctl_stat32(SYSCTL_HANDLER_ARGS);
3193a91ee71SPyun YongHyeon static int msk_sysctl_stat64(SYSCTL_HANDLER_ARGS);
3203a91ee71SPyun YongHyeon static void msk_sysctl_node(struct msk_if_softc *);
3210dbe28b3SPyun YongHyeon static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
3220dbe28b3SPyun YongHyeon static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS);
3230dbe28b3SPyun YongHyeon 
3240dbe28b3SPyun YongHyeon static device_method_t mskc_methods[] = {
3250dbe28b3SPyun YongHyeon 	/* Device interface */
3260dbe28b3SPyun YongHyeon 	DEVMETHOD(device_probe,		mskc_probe),
3270dbe28b3SPyun YongHyeon 	DEVMETHOD(device_attach,	mskc_attach),
3280dbe28b3SPyun YongHyeon 	DEVMETHOD(device_detach,	mskc_detach),
3290dbe28b3SPyun YongHyeon 	DEVMETHOD(device_suspend,	mskc_suspend),
3300dbe28b3SPyun YongHyeon 	DEVMETHOD(device_resume,	mskc_resume),
3310dbe28b3SPyun YongHyeon 	DEVMETHOD(device_shutdown,	mskc_shutdown),
3320dbe28b3SPyun YongHyeon 
3330dbe28b3SPyun YongHyeon 	/* bus interface */
3340dbe28b3SPyun YongHyeon 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
3350dbe28b3SPyun YongHyeon 	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
3360dbe28b3SPyun YongHyeon 
3370dbe28b3SPyun YongHyeon 	{ NULL, NULL }
3380dbe28b3SPyun YongHyeon };
3390dbe28b3SPyun YongHyeon 
3400dbe28b3SPyun YongHyeon static driver_t mskc_driver = {
3410dbe28b3SPyun YongHyeon 	"mskc",
3420dbe28b3SPyun YongHyeon 	mskc_methods,
3430dbe28b3SPyun YongHyeon 	sizeof(struct msk_softc)
3440dbe28b3SPyun YongHyeon };
3450dbe28b3SPyun YongHyeon 
3460dbe28b3SPyun YongHyeon static devclass_t mskc_devclass;
3470dbe28b3SPyun YongHyeon 
3480dbe28b3SPyun YongHyeon static device_method_t msk_methods[] = {
3490dbe28b3SPyun YongHyeon 	/* Device interface */
3500dbe28b3SPyun YongHyeon 	DEVMETHOD(device_probe,		msk_probe),
3510dbe28b3SPyun YongHyeon 	DEVMETHOD(device_attach,	msk_attach),
3520dbe28b3SPyun YongHyeon 	DEVMETHOD(device_detach,	msk_detach),
3530dbe28b3SPyun YongHyeon 	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
3540dbe28b3SPyun YongHyeon 
3550dbe28b3SPyun YongHyeon 	/* bus interface */
3560dbe28b3SPyun YongHyeon 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
3570dbe28b3SPyun YongHyeon 	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
3580dbe28b3SPyun YongHyeon 
3590dbe28b3SPyun YongHyeon 	/* MII interface */
3600dbe28b3SPyun YongHyeon 	DEVMETHOD(miibus_readreg,	msk_miibus_readreg),
3610dbe28b3SPyun YongHyeon 	DEVMETHOD(miibus_writereg,	msk_miibus_writereg),
3620dbe28b3SPyun YongHyeon 	DEVMETHOD(miibus_statchg,	msk_miibus_statchg),
3630dbe28b3SPyun YongHyeon 
3640dbe28b3SPyun YongHyeon 	{ NULL, NULL }
3650dbe28b3SPyun YongHyeon };
3660dbe28b3SPyun YongHyeon 
3670dbe28b3SPyun YongHyeon static driver_t msk_driver = {
3680dbe28b3SPyun YongHyeon 	"msk",
3690dbe28b3SPyun YongHyeon 	msk_methods,
3700dbe28b3SPyun YongHyeon 	sizeof(struct msk_if_softc)
3710dbe28b3SPyun YongHyeon };
3720dbe28b3SPyun YongHyeon 
3730dbe28b3SPyun YongHyeon static devclass_t msk_devclass;
3740dbe28b3SPyun YongHyeon 
3750dbe28b3SPyun YongHyeon DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0);
3760dbe28b3SPyun YongHyeon DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0);
3770dbe28b3SPyun YongHyeon DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0);
3780dbe28b3SPyun YongHyeon 
3790dbe28b3SPyun YongHyeon static struct resource_spec msk_res_spec_io[] = {
3800dbe28b3SPyun YongHyeon 	{ SYS_RES_IOPORT,	PCIR_BAR(1),	RF_ACTIVE },
3810dbe28b3SPyun YongHyeon 	{ -1,			0,		0 }
3820dbe28b3SPyun YongHyeon };
3830dbe28b3SPyun YongHyeon 
3840dbe28b3SPyun YongHyeon static struct resource_spec msk_res_spec_mem[] = {
3850dbe28b3SPyun YongHyeon 	{ SYS_RES_MEMORY,	PCIR_BAR(0),	RF_ACTIVE },
386298946a9SPyun YongHyeon 	{ -1,			0,		0 }
387298946a9SPyun YongHyeon };
388298946a9SPyun YongHyeon 
389298946a9SPyun YongHyeon static struct resource_spec msk_irq_spec_legacy[] = {
3900dbe28b3SPyun YongHyeon 	{ SYS_RES_IRQ,		0,		RF_ACTIVE | RF_SHAREABLE },
3910dbe28b3SPyun YongHyeon 	{ -1,			0,		0 }
3920dbe28b3SPyun YongHyeon };
3930dbe28b3SPyun YongHyeon 
394298946a9SPyun YongHyeon static struct resource_spec msk_irq_spec_msi[] = {
395298946a9SPyun YongHyeon 	{ SYS_RES_IRQ,		1,		RF_ACTIVE },
3968463d7a0SPyun YongHyeon 	{ -1,			0,		0 }
3978463d7a0SPyun YongHyeon };
3988463d7a0SPyun YongHyeon 
3990dbe28b3SPyun YongHyeon static int
4000dbe28b3SPyun YongHyeon msk_miibus_readreg(device_t dev, int phy, int reg)
4010dbe28b3SPyun YongHyeon {
4020dbe28b3SPyun YongHyeon 	struct msk_if_softc *sc_if;
4030dbe28b3SPyun YongHyeon 
4040dbe28b3SPyun YongHyeon 	sc_if = device_get_softc(dev);
4050dbe28b3SPyun YongHyeon 
4060dbe28b3SPyun YongHyeon 	return (msk_phy_readreg(sc_if, phy, reg));
4070dbe28b3SPyun YongHyeon }
4080dbe28b3SPyun YongHyeon 
4090dbe28b3SPyun YongHyeon static int
4100dbe28b3SPyun YongHyeon msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg)
4110dbe28b3SPyun YongHyeon {
4120dbe28b3SPyun YongHyeon 	struct msk_softc *sc;
4130dbe28b3SPyun YongHyeon 	int i, val;
4140dbe28b3SPyun YongHyeon 
4150dbe28b3SPyun YongHyeon 	sc = sc_if->msk_softc;
4160dbe28b3SPyun YongHyeon 
4170dbe28b3SPyun YongHyeon         GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
4180dbe28b3SPyun YongHyeon 	    GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
4190dbe28b3SPyun YongHyeon 
4200dbe28b3SPyun YongHyeon 	for (i = 0; i < MSK_TIMEOUT; i++) {
4210dbe28b3SPyun YongHyeon 		DELAY(1);
4220dbe28b3SPyun YongHyeon 		val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL);
4230dbe28b3SPyun YongHyeon 		if ((val & GM_SMI_CT_RD_VAL) != 0) {
4240dbe28b3SPyun YongHyeon 			val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA);
4250dbe28b3SPyun YongHyeon 			break;
4260dbe28b3SPyun YongHyeon 		}
4270dbe28b3SPyun YongHyeon 	}
4280dbe28b3SPyun YongHyeon 
4290dbe28b3SPyun YongHyeon 	if (i == MSK_TIMEOUT) {
4300dbe28b3SPyun YongHyeon 		if_printf(sc_if->msk_ifp, "phy failed to come ready\n");
4310dbe28b3SPyun YongHyeon 		val = 0;
4320dbe28b3SPyun YongHyeon 	}
4330dbe28b3SPyun YongHyeon 
4340dbe28b3SPyun YongHyeon 	return (val);
4350dbe28b3SPyun YongHyeon }
4360dbe28b3SPyun YongHyeon 
4370dbe28b3SPyun YongHyeon static int
4380dbe28b3SPyun YongHyeon msk_miibus_writereg(device_t dev, int phy, int reg, int val)
4390dbe28b3SPyun YongHyeon {
4400dbe28b3SPyun YongHyeon 	struct msk_if_softc *sc_if;
4410dbe28b3SPyun YongHyeon 
4420dbe28b3SPyun YongHyeon 	sc_if = device_get_softc(dev);
4430dbe28b3SPyun YongHyeon 
4440dbe28b3SPyun YongHyeon 	return (msk_phy_writereg(sc_if, phy, reg, val));
4450dbe28b3SPyun YongHyeon }
4460dbe28b3SPyun YongHyeon 
4470dbe28b3SPyun YongHyeon static int
4480dbe28b3SPyun YongHyeon msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val)
4490dbe28b3SPyun YongHyeon {
4500dbe28b3SPyun YongHyeon 	struct msk_softc *sc;
4510dbe28b3SPyun YongHyeon 	int i;
4520dbe28b3SPyun YongHyeon 
4530dbe28b3SPyun YongHyeon 	sc = sc_if->msk_softc;
4540dbe28b3SPyun YongHyeon 
4550dbe28b3SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val);
4560dbe28b3SPyun YongHyeon         GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL,
4570dbe28b3SPyun YongHyeon 	    GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg));
4580dbe28b3SPyun YongHyeon 	for (i = 0; i < MSK_TIMEOUT; i++) {
4590dbe28b3SPyun YongHyeon 		DELAY(1);
4600dbe28b3SPyun YongHyeon 		if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) &
4610dbe28b3SPyun YongHyeon 		    GM_SMI_CT_BUSY) == 0)
4620dbe28b3SPyun YongHyeon 			break;
4630dbe28b3SPyun YongHyeon 	}
4640dbe28b3SPyun YongHyeon 	if (i == MSK_TIMEOUT)
4650dbe28b3SPyun YongHyeon 		if_printf(sc_if->msk_ifp, "phy write timeout\n");
4660dbe28b3SPyun YongHyeon 
4670dbe28b3SPyun YongHyeon 	return (0);
4680dbe28b3SPyun YongHyeon }
4690dbe28b3SPyun YongHyeon 
4700dbe28b3SPyun YongHyeon static void
4710dbe28b3SPyun YongHyeon msk_miibus_statchg(device_t dev)
4720dbe28b3SPyun YongHyeon {
4730dbe28b3SPyun YongHyeon 	struct msk_softc *sc;
4740dbe28b3SPyun YongHyeon 	struct msk_if_softc *sc_if;
4750dbe28b3SPyun YongHyeon 	struct mii_data *mii;
4760dbe28b3SPyun YongHyeon 	struct ifnet *ifp;
477bf59599fSPyun YongHyeon 	uint32_t gmac;
4780dbe28b3SPyun YongHyeon 
47919585f45SPyun YongHyeon 	sc_if = device_get_softc(dev);
4800dbe28b3SPyun YongHyeon 	sc = sc_if->msk_softc;
4810dbe28b3SPyun YongHyeon 
4824b76fe63SPyun YongHyeon 	MSK_IF_LOCK_ASSERT(sc_if);
4830dbe28b3SPyun YongHyeon 
4840dbe28b3SPyun YongHyeon 	mii = device_get_softc(sc_if->msk_miibus);
4850dbe28b3SPyun YongHyeon 	ifp = sc_if->msk_ifp;
48619585f45SPyun YongHyeon 	if (mii == NULL || ifp == NULL ||
48719585f45SPyun YongHyeon 	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
4880dbe28b3SPyun YongHyeon 		return;
4890dbe28b3SPyun YongHyeon 
490ab7df1e4SPyun YongHyeon 	sc_if->msk_flags &= ~MSK_FLAG_LINK;
4916c4d62e1SPyun YongHyeon 	if ((mii->mii_media_status & (IFM_AVALID | IFM_ACTIVE)) ==
4926c4d62e1SPyun YongHyeon 	    (IFM_AVALID | IFM_ACTIVE)) {
4936c4d62e1SPyun YongHyeon 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
4946c4d62e1SPyun YongHyeon 		case IFM_10_T:
4956c4d62e1SPyun YongHyeon 		case IFM_100_TX:
4966c4d62e1SPyun YongHyeon 			sc_if->msk_flags |= MSK_FLAG_LINK;
4976c4d62e1SPyun YongHyeon 			break;
4986c4d62e1SPyun YongHyeon 		case IFM_1000_T:
4996c4d62e1SPyun YongHyeon 		case IFM_1000_SX:
5006c4d62e1SPyun YongHyeon 		case IFM_1000_LX:
5016c4d62e1SPyun YongHyeon 		case IFM_1000_CX:
5026c4d62e1SPyun YongHyeon 			if ((sc_if->msk_flags & MSK_FLAG_FASTETHER) == 0)
5036c4d62e1SPyun YongHyeon 				sc_if->msk_flags |= MSK_FLAG_LINK;
5046c4d62e1SPyun YongHyeon 			break;
5056c4d62e1SPyun YongHyeon 		default:
5066c4d62e1SPyun YongHyeon 			break;
5076c4d62e1SPyun YongHyeon 		}
5086c4d62e1SPyun YongHyeon 	}
5090dbe28b3SPyun YongHyeon 
510ab7df1e4SPyun YongHyeon 	if ((sc_if->msk_flags & MSK_FLAG_LINK) != 0) {
5110dbe28b3SPyun YongHyeon 		/* Enable Tx FIFO Underrun. */
5120dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK),
5130dbe28b3SPyun YongHyeon 		    GM_IS_TX_FF_UR | GM_IS_RX_FF_OR);
514bf59599fSPyun YongHyeon 		/*
515bf59599fSPyun YongHyeon 		 * Because mii(4) notify msk(4) that it detected link status
516bf59599fSPyun YongHyeon 		 * change, there is no need to enable automatic
517bf59599fSPyun YongHyeon 		 * speed/flow-control/duplex updates.
518bf59599fSPyun YongHyeon 		 */
519bf59599fSPyun YongHyeon 		gmac = GM_GPCR_AU_ALL_DIS;
5200dbe28b3SPyun YongHyeon 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
5210dbe28b3SPyun YongHyeon 		case IFM_1000_SX:
5220dbe28b3SPyun YongHyeon 		case IFM_1000_T:
5230dbe28b3SPyun YongHyeon 			gmac |= GM_GPCR_SPEED_1000;
5240dbe28b3SPyun YongHyeon 			break;
5250dbe28b3SPyun YongHyeon 		case IFM_100_TX:
5260dbe28b3SPyun YongHyeon 			gmac |= GM_GPCR_SPEED_100;
5270dbe28b3SPyun YongHyeon 			break;
5280dbe28b3SPyun YongHyeon 		case IFM_10_T:
5290dbe28b3SPyun YongHyeon 			break;
5300dbe28b3SPyun YongHyeon 		}
5310dbe28b3SPyun YongHyeon 
532efd4fc3fSMarius Strobl 		if ((IFM_OPTIONS(mii->mii_media_active) &
533efd4fc3fSMarius Strobl 		    IFM_ETH_RXPAUSE) == 0)
534bf59599fSPyun YongHyeon 			gmac |= GM_GPCR_FC_RX_DIS;
535efd4fc3fSMarius Strobl 		if ((IFM_OPTIONS(mii->mii_media_active) &
536efd4fc3fSMarius Strobl 		     IFM_ETH_TXPAUSE) == 0)
537bf59599fSPyun YongHyeon 			gmac |= GM_GPCR_FC_TX_DIS;
53842f3ea9fSPyun YongHyeon 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0)
53942f3ea9fSPyun YongHyeon 			gmac |= GM_GPCR_DUP_FULL;
54042f3ea9fSPyun YongHyeon 		else
54142f3ea9fSPyun YongHyeon 			gmac |= GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS;
5420dbe28b3SPyun YongHyeon 		gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
5430dbe28b3SPyun YongHyeon 		GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
5440dbe28b3SPyun YongHyeon 		/* Read again to ensure writing. */
5450dbe28b3SPyun YongHyeon 		GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
54642f3ea9fSPyun YongHyeon 		gmac = GMC_PAUSE_OFF;
54742f3ea9fSPyun YongHyeon 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
548efd4fc3fSMarius Strobl 			if ((IFM_OPTIONS(mii->mii_media_active) &
549efd4fc3fSMarius Strobl 			    IFM_ETH_RXPAUSE) != 0)
5500dbe28b3SPyun YongHyeon 				gmac = GMC_PAUSE_ON;
55142f3ea9fSPyun YongHyeon 		}
5520dbe28b3SPyun YongHyeon 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac);
5530dbe28b3SPyun YongHyeon 
5540dbe28b3SPyun YongHyeon 		/* Enable PHY interrupt for FIFO underrun/overflow. */
5550dbe28b3SPyun YongHyeon 		msk_phy_writereg(sc_if, PHY_ADDR_MARV,
5560dbe28b3SPyun YongHyeon 		    PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR);
5570dbe28b3SPyun YongHyeon 	} else {
5580dbe28b3SPyun YongHyeon 		/*
5590dbe28b3SPyun YongHyeon 		 * Link state changed to down.
5600dbe28b3SPyun YongHyeon 		 * Disable PHY interrupts.
5610dbe28b3SPyun YongHyeon 		 */
562431e606dSPyun YongHyeon 		msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
5630dbe28b3SPyun YongHyeon 		/* Disable Rx/Tx MAC. */
564bf59599fSPyun YongHyeon 		gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
5656c4d62e1SPyun YongHyeon 		if ((GM_GPCR_RX_ENA | GM_GPCR_TX_ENA) != 0) {
5660dbe28b3SPyun YongHyeon 			gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
5670dbe28b3SPyun YongHyeon 			GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac);
5680dbe28b3SPyun YongHyeon 			/* Read again to ensure writing. */
5690dbe28b3SPyun YongHyeon 			GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
5700dbe28b3SPyun YongHyeon 		}
5710dbe28b3SPyun YongHyeon 	}
5726c4d62e1SPyun YongHyeon }
5730dbe28b3SPyun YongHyeon 
5740dbe28b3SPyun YongHyeon static void
5756d6588a1SPyun YongHyeon msk_rxfilter(struct msk_if_softc *sc_if)
5760dbe28b3SPyun YongHyeon {
5770dbe28b3SPyun YongHyeon 	struct msk_softc *sc;
5780dbe28b3SPyun YongHyeon 	struct ifnet *ifp;
5790dbe28b3SPyun YongHyeon 	struct ifmultiaddr *ifma;
5800dbe28b3SPyun YongHyeon 	uint32_t mchash[2];
5810dbe28b3SPyun YongHyeon 	uint32_t crc;
5820dbe28b3SPyun YongHyeon 	uint16_t mode;
5830dbe28b3SPyun YongHyeon 
5840dbe28b3SPyun YongHyeon 	sc = sc_if->msk_softc;
5850dbe28b3SPyun YongHyeon 
5860dbe28b3SPyun YongHyeon 	MSK_IF_LOCK_ASSERT(sc_if);
5870dbe28b3SPyun YongHyeon 
5880dbe28b3SPyun YongHyeon 	ifp = sc_if->msk_ifp;
5890dbe28b3SPyun YongHyeon 
5900dbe28b3SPyun YongHyeon 	bzero(mchash, sizeof(mchash));
5910dbe28b3SPyun YongHyeon 	mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL);
5920dbe28b3SPyun YongHyeon 	if ((ifp->if_flags & IFF_PROMISC) != 0)
5930dbe28b3SPyun YongHyeon 		mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
5940dbe28b3SPyun YongHyeon 	else if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
5956d6588a1SPyun YongHyeon 		mode |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
5960dbe28b3SPyun YongHyeon 		mchash[0] = 0xffff;
5970dbe28b3SPyun YongHyeon 		mchash[1] = 0xffff;
5980dbe28b3SPyun YongHyeon 	} else {
5996d6588a1SPyun YongHyeon 		mode |= GM_RXCR_UCF_ENA;
600eb956cd0SRobert Watson 		if_maddr_rlock(ifp);
6010dbe28b3SPyun YongHyeon 		TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
6020dbe28b3SPyun YongHyeon 			if (ifma->ifma_addr->sa_family != AF_LINK)
6030dbe28b3SPyun YongHyeon 				continue;
6040dbe28b3SPyun YongHyeon 			crc = ether_crc32_be(LLADDR((struct sockaddr_dl *)
6050dbe28b3SPyun YongHyeon 			    ifma->ifma_addr), ETHER_ADDR_LEN);
6060dbe28b3SPyun YongHyeon 			/* Just want the 6 least significant bits. */
6070dbe28b3SPyun YongHyeon 			crc &= 0x3f;
6080dbe28b3SPyun YongHyeon 			/* Set the corresponding bit in the hash table. */
6090dbe28b3SPyun YongHyeon 			mchash[crc >> 5] |= 1 << (crc & 0x1f);
6100dbe28b3SPyun YongHyeon 		}
611eb956cd0SRobert Watson 		if_maddr_runlock(ifp);
6126d6588a1SPyun YongHyeon 		if (mchash[0] != 0 || mchash[1] != 0)
6130dbe28b3SPyun YongHyeon 			mode |= GM_RXCR_MCF_ENA;
6140dbe28b3SPyun YongHyeon 	}
6150dbe28b3SPyun YongHyeon 
6160dbe28b3SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1,
6170dbe28b3SPyun YongHyeon 	    mchash[0] & 0xffff);
6180dbe28b3SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2,
6190dbe28b3SPyun YongHyeon 	    (mchash[0] >> 16) & 0xffff);
6200dbe28b3SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3,
6210dbe28b3SPyun YongHyeon 	    mchash[1] & 0xffff);
6220dbe28b3SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4,
6230dbe28b3SPyun YongHyeon 	    (mchash[1] >> 16) & 0xffff);
6240dbe28b3SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode);
6250dbe28b3SPyun YongHyeon }
6260dbe28b3SPyun YongHyeon 
6270dbe28b3SPyun YongHyeon static void
6280dbe28b3SPyun YongHyeon msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp)
6290dbe28b3SPyun YongHyeon {
6300dbe28b3SPyun YongHyeon 	struct msk_softc *sc;
6310dbe28b3SPyun YongHyeon 
6320dbe28b3SPyun YongHyeon 	sc = sc_if->msk_softc;
6330dbe28b3SPyun YongHyeon 	if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
6340dbe28b3SPyun YongHyeon 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
6350dbe28b3SPyun YongHyeon 		    RX_VLAN_STRIP_ON);
6360dbe28b3SPyun YongHyeon 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
6370dbe28b3SPyun YongHyeon 		    TX_VLAN_TAG_ON);
6380dbe28b3SPyun YongHyeon 	} else {
6390dbe28b3SPyun YongHyeon 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
6400dbe28b3SPyun YongHyeon 		    RX_VLAN_STRIP_OFF);
6410dbe28b3SPyun YongHyeon 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
6420dbe28b3SPyun YongHyeon 		    TX_VLAN_TAG_OFF);
6430dbe28b3SPyun YongHyeon 	}
6440dbe28b3SPyun YongHyeon }
6450dbe28b3SPyun YongHyeon 
6460dbe28b3SPyun YongHyeon static int
647388214e4SPyun YongHyeon msk_rx_fill(struct msk_if_softc *sc_if, int jumbo)
648388214e4SPyun YongHyeon {
649388214e4SPyun YongHyeon 	uint16_t idx;
650388214e4SPyun YongHyeon 	int i;
651388214e4SPyun YongHyeon 
652388214e4SPyun YongHyeon 	if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
653388214e4SPyun YongHyeon 	    (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) {
654388214e4SPyun YongHyeon 		/* Wait until controller executes OP_TCPSTART command. */
655388214e4SPyun YongHyeon 		for (i = 10; i > 0; i--) {
656388214e4SPyun YongHyeon 			DELAY(10);
657388214e4SPyun YongHyeon 			idx = CSR_READ_2(sc_if->msk_softc,
658388214e4SPyun YongHyeon 			    Y2_PREF_Q_ADDR(sc_if->msk_rxq,
659388214e4SPyun YongHyeon 			    PREF_UNIT_GET_IDX_REG));
660388214e4SPyun YongHyeon 			if (idx != 0)
661388214e4SPyun YongHyeon 				break;
662388214e4SPyun YongHyeon 		}
663388214e4SPyun YongHyeon 		if (i == 0) {
664388214e4SPyun YongHyeon 			device_printf(sc_if->msk_if_dev,
665388214e4SPyun YongHyeon 			    "prefetch unit stuck?\n");
666388214e4SPyun YongHyeon 			return (ETIMEDOUT);
667388214e4SPyun YongHyeon 		}
668388214e4SPyun YongHyeon 		/*
669388214e4SPyun YongHyeon 		 * Fill consumed LE with free buffer. This can be done
670388214e4SPyun YongHyeon 		 * in Rx handler but we don't want to add special code
671388214e4SPyun YongHyeon 		 * in fast handler.
672388214e4SPyun YongHyeon 		 */
673388214e4SPyun YongHyeon 		if (jumbo > 0) {
674388214e4SPyun YongHyeon 			if (msk_jumbo_newbuf(sc_if, 0) != 0)
675388214e4SPyun YongHyeon 				return (ENOBUFS);
676388214e4SPyun YongHyeon 			bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
677388214e4SPyun YongHyeon 			    sc_if->msk_cdata.msk_jumbo_rx_ring_map,
678388214e4SPyun YongHyeon 			    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
679388214e4SPyun YongHyeon 		} else {
680388214e4SPyun YongHyeon 			if (msk_newbuf(sc_if, 0) != 0)
681388214e4SPyun YongHyeon 				return (ENOBUFS);
682388214e4SPyun YongHyeon 			bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag,
683388214e4SPyun YongHyeon 			    sc_if->msk_cdata.msk_rx_ring_map,
684388214e4SPyun YongHyeon 			    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
685388214e4SPyun YongHyeon 		}
686388214e4SPyun YongHyeon 		sc_if->msk_cdata.msk_rx_prod = 0;
687388214e4SPyun YongHyeon 		CSR_WRITE_2(sc_if->msk_softc,
688388214e4SPyun YongHyeon 		    Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
689388214e4SPyun YongHyeon 		    sc_if->msk_cdata.msk_rx_prod);
690388214e4SPyun YongHyeon 	}
691388214e4SPyun YongHyeon 	return (0);
692388214e4SPyun YongHyeon }
693388214e4SPyun YongHyeon 
694388214e4SPyun YongHyeon static int
6950dbe28b3SPyun YongHyeon msk_init_rx_ring(struct msk_if_softc *sc_if)
6960dbe28b3SPyun YongHyeon {
6970dbe28b3SPyun YongHyeon 	struct msk_ring_data *rd;
6980dbe28b3SPyun YongHyeon 	struct msk_rxdesc *rxd;
6990dbe28b3SPyun YongHyeon 	int i, prod;
7000dbe28b3SPyun YongHyeon 
7010dbe28b3SPyun YongHyeon 	MSK_IF_LOCK_ASSERT(sc_if);
7020dbe28b3SPyun YongHyeon 
7030dbe28b3SPyun YongHyeon 	sc_if->msk_cdata.msk_rx_cons = 0;
7040dbe28b3SPyun YongHyeon 	sc_if->msk_cdata.msk_rx_prod = 0;
7050dbe28b3SPyun YongHyeon 	sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
7060dbe28b3SPyun YongHyeon 
7070dbe28b3SPyun YongHyeon 	rd = &sc_if->msk_rdata;
7080dbe28b3SPyun YongHyeon 	bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT);
7090dbe28b3SPyun YongHyeon 	prod = sc_if->msk_cdata.msk_rx_prod;
710388214e4SPyun YongHyeon 	i = 0;
711388214e4SPyun YongHyeon 	/* Have controller know how to compute Rx checksum. */
712388214e4SPyun YongHyeon 	if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
713388214e4SPyun YongHyeon 	    (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) {
714388214e4SPyun YongHyeon 		rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
715388214e4SPyun YongHyeon 		rxd->rx_m = NULL;
716388214e4SPyun YongHyeon 		rxd->rx_le = &rd->msk_rx_ring[prod];
717388214e4SPyun YongHyeon 		rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
718388214e4SPyun YongHyeon 		    ETHER_HDR_LEN);
719388214e4SPyun YongHyeon 		rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
720388214e4SPyun YongHyeon 		MSK_INC(prod, MSK_RX_RING_CNT);
721388214e4SPyun YongHyeon 		MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
722388214e4SPyun YongHyeon 		i++;
723388214e4SPyun YongHyeon 	}
724388214e4SPyun YongHyeon 	for (; i < MSK_RX_RING_CNT; i++) {
7250dbe28b3SPyun YongHyeon 		rxd = &sc_if->msk_cdata.msk_rxdesc[prod];
7260dbe28b3SPyun YongHyeon 		rxd->rx_m = NULL;
7270dbe28b3SPyun YongHyeon 		rxd->rx_le = &rd->msk_rx_ring[prod];
7280dbe28b3SPyun YongHyeon 		if (msk_newbuf(sc_if, prod) != 0)
7290dbe28b3SPyun YongHyeon 			return (ENOBUFS);
7300dbe28b3SPyun YongHyeon 		MSK_INC(prod, MSK_RX_RING_CNT);
7310dbe28b3SPyun YongHyeon 	}
7320dbe28b3SPyun YongHyeon 
7330dbe28b3SPyun YongHyeon 	bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag,
7340dbe28b3SPyun YongHyeon 	    sc_if->msk_cdata.msk_rx_ring_map,
7350dbe28b3SPyun YongHyeon 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
7360dbe28b3SPyun YongHyeon 
7370dbe28b3SPyun YongHyeon 	/* Update prefetch unit. */
7380dbe28b3SPyun YongHyeon 	sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1;
7390dbe28b3SPyun YongHyeon 	CSR_WRITE_2(sc_if->msk_softc,
7400dbe28b3SPyun YongHyeon 	    Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
7410dbe28b3SPyun YongHyeon 	    sc_if->msk_cdata.msk_rx_prod);
742388214e4SPyun YongHyeon 	if (msk_rx_fill(sc_if, 0) != 0)
743388214e4SPyun YongHyeon 		return (ENOBUFS);
7440dbe28b3SPyun YongHyeon 	return (0);
7450dbe28b3SPyun YongHyeon }
7460dbe28b3SPyun YongHyeon 
7470dbe28b3SPyun YongHyeon static int
7480dbe28b3SPyun YongHyeon msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if)
7490dbe28b3SPyun YongHyeon {
7500dbe28b3SPyun YongHyeon 	struct msk_ring_data *rd;
7510dbe28b3SPyun YongHyeon 	struct msk_rxdesc *rxd;
7520dbe28b3SPyun YongHyeon 	int i, prod;
7530dbe28b3SPyun YongHyeon 
7540dbe28b3SPyun YongHyeon 	MSK_IF_LOCK_ASSERT(sc_if);
7550dbe28b3SPyun YongHyeon 
7560dbe28b3SPyun YongHyeon 	sc_if->msk_cdata.msk_rx_cons = 0;
7570dbe28b3SPyun YongHyeon 	sc_if->msk_cdata.msk_rx_prod = 0;
7580dbe28b3SPyun YongHyeon 	sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM;
7590dbe28b3SPyun YongHyeon 
7600dbe28b3SPyun YongHyeon 	rd = &sc_if->msk_rdata;
7610dbe28b3SPyun YongHyeon 	bzero(rd->msk_jumbo_rx_ring,
7620dbe28b3SPyun YongHyeon 	    sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT);
7630dbe28b3SPyun YongHyeon 	prod = sc_if->msk_cdata.msk_rx_prod;
764388214e4SPyun YongHyeon 	i = 0;
765388214e4SPyun YongHyeon 	/* Have controller know how to compute Rx checksum. */
766388214e4SPyun YongHyeon 	if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
767388214e4SPyun YongHyeon 	    (sc_if->msk_ifp->if_capenable & IFCAP_RXCSUM) != 0) {
768388214e4SPyun YongHyeon 		rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
769388214e4SPyun YongHyeon 		rxd->rx_m = NULL;
770388214e4SPyun YongHyeon 		rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
771388214e4SPyun YongHyeon 		rxd->rx_le->msk_addr = htole32(ETHER_HDR_LEN << 16 |
772388214e4SPyun YongHyeon 		    ETHER_HDR_LEN);
773388214e4SPyun YongHyeon 		rxd->rx_le->msk_control = htole32(OP_TCPSTART | HW_OWNER);
774388214e4SPyun YongHyeon 		MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
775388214e4SPyun YongHyeon 		MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
776388214e4SPyun YongHyeon 		i++;
777388214e4SPyun YongHyeon 	}
778388214e4SPyun YongHyeon 	for (; i < MSK_JUMBO_RX_RING_CNT; i++) {
7790dbe28b3SPyun YongHyeon 		rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod];
7800dbe28b3SPyun YongHyeon 		rxd->rx_m = NULL;
7810dbe28b3SPyun YongHyeon 		rxd->rx_le = &rd->msk_jumbo_rx_ring[prod];
7820dbe28b3SPyun YongHyeon 		if (msk_jumbo_newbuf(sc_if, prod) != 0)
7830dbe28b3SPyun YongHyeon 			return (ENOBUFS);
7840dbe28b3SPyun YongHyeon 		MSK_INC(prod, MSK_JUMBO_RX_RING_CNT);
7850dbe28b3SPyun YongHyeon 	}
7860dbe28b3SPyun YongHyeon 
7870dbe28b3SPyun YongHyeon 	bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
7880dbe28b3SPyun YongHyeon 	    sc_if->msk_cdata.msk_jumbo_rx_ring_map,
7890dbe28b3SPyun YongHyeon 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
7900dbe28b3SPyun YongHyeon 
7910dbe28b3SPyun YongHyeon 	sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1;
7920dbe28b3SPyun YongHyeon 	CSR_WRITE_2(sc_if->msk_softc,
7930dbe28b3SPyun YongHyeon 	    Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG),
7940dbe28b3SPyun YongHyeon 	    sc_if->msk_cdata.msk_rx_prod);
795388214e4SPyun YongHyeon 	if (msk_rx_fill(sc_if, 1) != 0)
796388214e4SPyun YongHyeon 		return (ENOBUFS);
7970dbe28b3SPyun YongHyeon 	return (0);
7980dbe28b3SPyun YongHyeon }
7990dbe28b3SPyun YongHyeon 
8000dbe28b3SPyun YongHyeon static void
8010dbe28b3SPyun YongHyeon msk_init_tx_ring(struct msk_if_softc *sc_if)
8020dbe28b3SPyun YongHyeon {
8030dbe28b3SPyun YongHyeon 	struct msk_ring_data *rd;
8040dbe28b3SPyun YongHyeon 	struct msk_txdesc *txd;
8050dbe28b3SPyun YongHyeon 	int i;
8060dbe28b3SPyun YongHyeon 
8070dbe28b3SPyun YongHyeon 	sc_if->msk_cdata.msk_tso_mtu = 0;
8081b7757c0SPyun YongHyeon 	sc_if->msk_cdata.msk_last_csum = 0;
8090dbe28b3SPyun YongHyeon 	sc_if->msk_cdata.msk_tx_prod = 0;
8100dbe28b3SPyun YongHyeon 	sc_if->msk_cdata.msk_tx_cons = 0;
8110dbe28b3SPyun YongHyeon 	sc_if->msk_cdata.msk_tx_cnt = 0;
8120dbe28b3SPyun YongHyeon 
8130dbe28b3SPyun YongHyeon 	rd = &sc_if->msk_rdata;
8140dbe28b3SPyun YongHyeon 	bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT);
8150dbe28b3SPyun YongHyeon 	for (i = 0; i < MSK_TX_RING_CNT; i++) {
8160dbe28b3SPyun YongHyeon 		txd = &sc_if->msk_cdata.msk_txdesc[i];
8170dbe28b3SPyun YongHyeon 		txd->tx_m = NULL;
8180dbe28b3SPyun YongHyeon 		txd->tx_le = &rd->msk_tx_ring[i];
8190dbe28b3SPyun YongHyeon 	}
8200dbe28b3SPyun YongHyeon 
8210dbe28b3SPyun YongHyeon 	bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
8220dbe28b3SPyun YongHyeon 	    sc_if->msk_cdata.msk_tx_ring_map,
8230dbe28b3SPyun YongHyeon 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
8240dbe28b3SPyun YongHyeon }
8250dbe28b3SPyun YongHyeon 
8260dbe28b3SPyun YongHyeon static __inline void
8270dbe28b3SPyun YongHyeon msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx)
8280dbe28b3SPyun YongHyeon {
8290dbe28b3SPyun YongHyeon 	struct msk_rx_desc *rx_le;
8300dbe28b3SPyun YongHyeon 	struct msk_rxdesc *rxd;
8310dbe28b3SPyun YongHyeon 	struct mbuf *m;
8320dbe28b3SPyun YongHyeon 
8330dbe28b3SPyun YongHyeon 	rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
8340dbe28b3SPyun YongHyeon 	m = rxd->rx_m;
8350dbe28b3SPyun YongHyeon 	rx_le = rxd->rx_le;
8360dbe28b3SPyun YongHyeon 	rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
8370dbe28b3SPyun YongHyeon }
8380dbe28b3SPyun YongHyeon 
8390dbe28b3SPyun YongHyeon static __inline void
8400dbe28b3SPyun YongHyeon msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int	idx)
8410dbe28b3SPyun YongHyeon {
8420dbe28b3SPyun YongHyeon 	struct msk_rx_desc *rx_le;
8430dbe28b3SPyun YongHyeon 	struct msk_rxdesc *rxd;
8440dbe28b3SPyun YongHyeon 	struct mbuf *m;
8450dbe28b3SPyun YongHyeon 
8460dbe28b3SPyun YongHyeon 	rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
8470dbe28b3SPyun YongHyeon 	m = rxd->rx_m;
8480dbe28b3SPyun YongHyeon 	rx_le = rxd->rx_le;
8490dbe28b3SPyun YongHyeon 	rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER);
8500dbe28b3SPyun YongHyeon }
8510dbe28b3SPyun YongHyeon 
8520dbe28b3SPyun YongHyeon static int
8530dbe28b3SPyun YongHyeon msk_newbuf(struct msk_if_softc *sc_if, int idx)
8540dbe28b3SPyun YongHyeon {
8550dbe28b3SPyun YongHyeon 	struct msk_rx_desc *rx_le;
8560dbe28b3SPyun YongHyeon 	struct msk_rxdesc *rxd;
8570dbe28b3SPyun YongHyeon 	struct mbuf *m;
8580dbe28b3SPyun YongHyeon 	bus_dma_segment_t segs[1];
8590dbe28b3SPyun YongHyeon 	bus_dmamap_t map;
8600dbe28b3SPyun YongHyeon 	int nsegs;
8610dbe28b3SPyun YongHyeon 
8620dbe28b3SPyun YongHyeon 	m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
8630dbe28b3SPyun YongHyeon 	if (m == NULL)
8640dbe28b3SPyun YongHyeon 		return (ENOBUFS);
8650dbe28b3SPyun YongHyeon 
8660dbe28b3SPyun YongHyeon 	m->m_len = m->m_pkthdr.len = MCLBYTES;
86783c04c93SPyun YongHyeon 	if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
8680dbe28b3SPyun YongHyeon 		m_adj(m, ETHER_ALIGN);
86983c04c93SPyun YongHyeon #ifndef __NO_STRICT_ALIGNMENT
87083c04c93SPyun YongHyeon 	else
87183c04c93SPyun YongHyeon 		m_adj(m, MSK_RX_BUF_ALIGN);
87283c04c93SPyun YongHyeon #endif
8730dbe28b3SPyun YongHyeon 
8740dbe28b3SPyun YongHyeon 	if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag,
8750dbe28b3SPyun YongHyeon 	    sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs,
8760dbe28b3SPyun YongHyeon 	    BUS_DMA_NOWAIT) != 0) {
8770dbe28b3SPyun YongHyeon 		m_freem(m);
8780dbe28b3SPyun YongHyeon 		return (ENOBUFS);
8790dbe28b3SPyun YongHyeon 	}
8800dbe28b3SPyun YongHyeon 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
8810dbe28b3SPyun YongHyeon 
8820dbe28b3SPyun YongHyeon 	rxd = &sc_if->msk_cdata.msk_rxdesc[idx];
8830dbe28b3SPyun YongHyeon 	if (rxd->rx_m != NULL) {
8840dbe28b3SPyun YongHyeon 		bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
8850dbe28b3SPyun YongHyeon 		    BUS_DMASYNC_POSTREAD);
8860dbe28b3SPyun YongHyeon 		bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap);
8870dbe28b3SPyun YongHyeon 	}
8880dbe28b3SPyun YongHyeon 	map = rxd->rx_dmamap;
8890dbe28b3SPyun YongHyeon 	rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap;
8900dbe28b3SPyun YongHyeon 	sc_if->msk_cdata.msk_rx_sparemap = map;
8910dbe28b3SPyun YongHyeon 	bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap,
8920dbe28b3SPyun YongHyeon 	    BUS_DMASYNC_PREREAD);
8930dbe28b3SPyun YongHyeon 	rxd->rx_m = m;
8940dbe28b3SPyun YongHyeon 	rx_le = rxd->rx_le;
8950dbe28b3SPyun YongHyeon 	rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr));
8960dbe28b3SPyun YongHyeon 	rx_le->msk_control =
8970dbe28b3SPyun YongHyeon 	    htole32(segs[0].ds_len | OP_PACKET | HW_OWNER);
8980dbe28b3SPyun YongHyeon 
8990dbe28b3SPyun YongHyeon 	return (0);
9000dbe28b3SPyun YongHyeon }
9010dbe28b3SPyun YongHyeon 
9020dbe28b3SPyun YongHyeon static int
9030dbe28b3SPyun YongHyeon msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx)
9040dbe28b3SPyun YongHyeon {
9050dbe28b3SPyun YongHyeon 	struct msk_rx_desc *rx_le;
9060dbe28b3SPyun YongHyeon 	struct msk_rxdesc *rxd;
9070dbe28b3SPyun YongHyeon 	struct mbuf *m;
9080dbe28b3SPyun YongHyeon 	bus_dma_segment_t segs[1];
9090dbe28b3SPyun YongHyeon 	bus_dmamap_t map;
9100dbe28b3SPyun YongHyeon 	int nsegs;
9110dbe28b3SPyun YongHyeon 
91285b340cbSPyun YongHyeon 	m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES);
9130dbe28b3SPyun YongHyeon 	if (m == NULL)
9140dbe28b3SPyun YongHyeon 		return (ENOBUFS);
9150dbe28b3SPyun YongHyeon 	if ((m->m_flags & M_EXT) == 0) {
9160dbe28b3SPyun YongHyeon 		m_freem(m);
9170dbe28b3SPyun YongHyeon 		return (ENOBUFS);
9180dbe28b3SPyun YongHyeon 	}
91985b340cbSPyun YongHyeon 	m->m_len = m->m_pkthdr.len = MJUM9BYTES;
92083c04c93SPyun YongHyeon 	if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
9210dbe28b3SPyun YongHyeon 		m_adj(m, ETHER_ALIGN);
92283c04c93SPyun YongHyeon #ifndef __NO_STRICT_ALIGNMENT
92383c04c93SPyun YongHyeon 	else
92483c04c93SPyun YongHyeon 		m_adj(m, MSK_RX_BUF_ALIGN);
92583c04c93SPyun YongHyeon #endif
9260dbe28b3SPyun YongHyeon 
9270dbe28b3SPyun YongHyeon 	if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag,
9280dbe28b3SPyun YongHyeon 	    sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs,
9290dbe28b3SPyun YongHyeon 	    BUS_DMA_NOWAIT) != 0) {
9300dbe28b3SPyun YongHyeon 		m_freem(m);
9310dbe28b3SPyun YongHyeon 		return (ENOBUFS);
9320dbe28b3SPyun YongHyeon 	}
9330dbe28b3SPyun YongHyeon 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
9340dbe28b3SPyun YongHyeon 
9350dbe28b3SPyun YongHyeon 	rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx];
9360dbe28b3SPyun YongHyeon 	if (rxd->rx_m != NULL) {
9370dbe28b3SPyun YongHyeon 		bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
9380dbe28b3SPyun YongHyeon 		    rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
9390dbe28b3SPyun YongHyeon 		bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
9400dbe28b3SPyun YongHyeon 		    rxd->rx_dmamap);
9410dbe28b3SPyun YongHyeon 	}
9420dbe28b3SPyun YongHyeon 	map = rxd->rx_dmamap;
9430dbe28b3SPyun YongHyeon 	rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap;
9440dbe28b3SPyun YongHyeon 	sc_if->msk_cdata.msk_jumbo_rx_sparemap = map;
9450dbe28b3SPyun YongHyeon 	bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap,
9460dbe28b3SPyun YongHyeon 	    BUS_DMASYNC_PREREAD);
9470dbe28b3SPyun YongHyeon 	rxd->rx_m = m;
9480dbe28b3SPyun YongHyeon 	rx_le = rxd->rx_le;
9490dbe28b3SPyun YongHyeon 	rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr));
9500dbe28b3SPyun YongHyeon 	rx_le->msk_control =
9510dbe28b3SPyun YongHyeon 	    htole32(segs[0].ds_len | OP_PACKET | HW_OWNER);
9520dbe28b3SPyun YongHyeon 
9530dbe28b3SPyun YongHyeon 	return (0);
9540dbe28b3SPyun YongHyeon }
9550dbe28b3SPyun YongHyeon 
9560dbe28b3SPyun YongHyeon /*
9570dbe28b3SPyun YongHyeon  * Set media options.
9580dbe28b3SPyun YongHyeon  */
9590dbe28b3SPyun YongHyeon static int
9600dbe28b3SPyun YongHyeon msk_mediachange(struct ifnet *ifp)
9610dbe28b3SPyun YongHyeon {
9620dbe28b3SPyun YongHyeon 	struct msk_if_softc *sc_if;
9630dbe28b3SPyun YongHyeon 	struct mii_data	*mii;
964325c534eSPyun YongHyeon 	int error;
9650dbe28b3SPyun YongHyeon 
9660dbe28b3SPyun YongHyeon 	sc_if = ifp->if_softc;
9670dbe28b3SPyun YongHyeon 
9680dbe28b3SPyun YongHyeon 	MSK_IF_LOCK(sc_if);
9690dbe28b3SPyun YongHyeon 	mii = device_get_softc(sc_if->msk_miibus);
970325c534eSPyun YongHyeon 	error = mii_mediachg(mii);
9710dbe28b3SPyun YongHyeon 	MSK_IF_UNLOCK(sc_if);
9720dbe28b3SPyun YongHyeon 
973325c534eSPyun YongHyeon 	return (error);
9740dbe28b3SPyun YongHyeon }
9750dbe28b3SPyun YongHyeon 
9760dbe28b3SPyun YongHyeon /*
9770dbe28b3SPyun YongHyeon  * Report current media status.
9780dbe28b3SPyun YongHyeon  */
9790dbe28b3SPyun YongHyeon static void
9800dbe28b3SPyun YongHyeon msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
9810dbe28b3SPyun YongHyeon {
9820dbe28b3SPyun YongHyeon 	struct msk_if_softc *sc_if;
9830dbe28b3SPyun YongHyeon 	struct mii_data	*mii;
9840dbe28b3SPyun YongHyeon 
9850dbe28b3SPyun YongHyeon 	sc_if = ifp->if_softc;
9860dbe28b3SPyun YongHyeon 	MSK_IF_LOCK(sc_if);
9876f5a0d1fSPyun YongHyeon 	if ((ifp->if_flags & IFF_UP) == 0) {
9886f5a0d1fSPyun YongHyeon 		MSK_IF_UNLOCK(sc_if);
9896f5a0d1fSPyun YongHyeon 		return;
9906f5a0d1fSPyun YongHyeon 	}
9910dbe28b3SPyun YongHyeon 	mii = device_get_softc(sc_if->msk_miibus);
9920dbe28b3SPyun YongHyeon 
9930dbe28b3SPyun YongHyeon 	mii_pollstat(mii);
9940dbe28b3SPyun YongHyeon 	MSK_IF_UNLOCK(sc_if);
9950dbe28b3SPyun YongHyeon 	ifmr->ifm_active = mii->mii_media_active;
9960dbe28b3SPyun YongHyeon 	ifmr->ifm_status = mii->mii_media_status;
9970dbe28b3SPyun YongHyeon }
9980dbe28b3SPyun YongHyeon 
9990dbe28b3SPyun YongHyeon static int
10000dbe28b3SPyun YongHyeon msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
10010dbe28b3SPyun YongHyeon {
10020dbe28b3SPyun YongHyeon 	struct msk_if_softc *sc_if;
10030dbe28b3SPyun YongHyeon 	struct ifreq *ifr;
10040dbe28b3SPyun YongHyeon 	struct mii_data	*mii;
1005388214e4SPyun YongHyeon 	int error, mask, reinit;
10060dbe28b3SPyun YongHyeon 
10070dbe28b3SPyun YongHyeon 	sc_if = ifp->if_softc;
10080dbe28b3SPyun YongHyeon 	ifr = (struct ifreq *)data;
10090dbe28b3SPyun YongHyeon 	error = 0;
10100dbe28b3SPyun YongHyeon 
10110dbe28b3SPyun YongHyeon 	switch(command) {
10120dbe28b3SPyun YongHyeon 	case SIOCSIFMTU:
1013e2b16603SPyun YongHyeon 		MSK_IF_LOCK(sc_if);
101485b340cbSPyun YongHyeon 		if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN)
10150dbe28b3SPyun YongHyeon 			error = EINVAL;
101685b340cbSPyun YongHyeon 		else if (ifp->if_mtu != ifr->ifr_mtu) {
1017e2b16603SPyun YongHyeon  			if (ifr->ifr_mtu > ETHERMTU) {
1018e2b16603SPyun YongHyeon 				if ((sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) {
10190dbe28b3SPyun YongHyeon 					error = EINVAL;
10200dbe28b3SPyun YongHyeon 					MSK_IF_UNLOCK(sc_if);
1021e2b16603SPyun YongHyeon 					break;
1022e2b16603SPyun YongHyeon 				}
1023e2b16603SPyun YongHyeon 				if ((sc_if->msk_flags &
1024e2b16603SPyun YongHyeon 				    MSK_FLAG_JUMBO_NOCSUM) != 0) {
1025e2b16603SPyun YongHyeon 					ifp->if_hwassist &=
1026e2b16603SPyun YongHyeon 					    ~(MSK_CSUM_FEATURES | CSUM_TSO);
1027e2b16603SPyun YongHyeon 					ifp->if_capenable &=
1028e2b16603SPyun YongHyeon 					    ~(IFCAP_TSO4 | IFCAP_TXCSUM);
1029e2b16603SPyun YongHyeon 					VLAN_CAPABILITIES(ifp);
103085b340cbSPyun YongHyeon 				}
103185b340cbSPyun YongHyeon 			}
1032e2b16603SPyun YongHyeon 			ifp->if_mtu = ifr->ifr_mtu;
1033e2b16603SPyun YongHyeon 			msk_init_locked(sc_if);
1034e2b16603SPyun YongHyeon 		}
1035e2b16603SPyun YongHyeon 		MSK_IF_UNLOCK(sc_if);
10360dbe28b3SPyun YongHyeon 		break;
10370dbe28b3SPyun YongHyeon 	case SIOCSIFFLAGS:
10380dbe28b3SPyun YongHyeon 		MSK_IF_LOCK(sc_if);
10390dbe28b3SPyun YongHyeon 		if ((ifp->if_flags & IFF_UP) != 0) {
1040b7e1e144SPyun YongHyeon 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
1041b7e1e144SPyun YongHyeon 			    ((ifp->if_flags ^ sc_if->msk_if_flags) &
1042b7e1e144SPyun YongHyeon 			    (IFF_PROMISC | IFF_ALLMULTI)) != 0)
10436d6588a1SPyun YongHyeon 				msk_rxfilter(sc_if);
1044b7e1e144SPyun YongHyeon 			else if ((sc_if->msk_flags & MSK_FLAG_DETACH) == 0)
10450dbe28b3SPyun YongHyeon 				msk_init_locked(sc_if);
1046b7e1e144SPyun YongHyeon 		} else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
10470dbe28b3SPyun YongHyeon 			msk_stop(sc_if);
10480dbe28b3SPyun YongHyeon 		sc_if->msk_if_flags = ifp->if_flags;
10490dbe28b3SPyun YongHyeon 		MSK_IF_UNLOCK(sc_if);
10500dbe28b3SPyun YongHyeon 		break;
10510dbe28b3SPyun YongHyeon 	case SIOCADDMULTI:
10520dbe28b3SPyun YongHyeon 	case SIOCDELMULTI:
10530dbe28b3SPyun YongHyeon 		MSK_IF_LOCK(sc_if);
10540dbe28b3SPyun YongHyeon 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
10556d6588a1SPyun YongHyeon 			msk_rxfilter(sc_if);
10560dbe28b3SPyun YongHyeon 		MSK_IF_UNLOCK(sc_if);
10570dbe28b3SPyun YongHyeon 		break;
10580dbe28b3SPyun YongHyeon 	case SIOCGIFMEDIA:
10590dbe28b3SPyun YongHyeon 	case SIOCSIFMEDIA:
10600dbe28b3SPyun YongHyeon 		mii = device_get_softc(sc_if->msk_miibus);
10610dbe28b3SPyun YongHyeon 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
10620dbe28b3SPyun YongHyeon 		break;
10630dbe28b3SPyun YongHyeon 	case SIOCSIFCAP:
1064388214e4SPyun YongHyeon 		reinit = 0;
10650dbe28b3SPyun YongHyeon 		MSK_IF_LOCK(sc_if);
10660dbe28b3SPyun YongHyeon 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
106798e02aebSPyun YongHyeon 		if ((mask & IFCAP_TXCSUM) != 0 &&
106898e02aebSPyun YongHyeon 		    (IFCAP_TXCSUM & ifp->if_capabilities) != 0) {
10690dbe28b3SPyun YongHyeon 			ifp->if_capenable ^= IFCAP_TXCSUM;
107098e02aebSPyun YongHyeon 			if ((IFCAP_TXCSUM & ifp->if_capenable) != 0)
10710dbe28b3SPyun YongHyeon 				ifp->if_hwassist |= MSK_CSUM_FEATURES;
10720dbe28b3SPyun YongHyeon 			else
10730dbe28b3SPyun YongHyeon 				ifp->if_hwassist &= ~MSK_CSUM_FEATURES;
10740dbe28b3SPyun YongHyeon 		}
1075efb74172SPyun YongHyeon 		if ((mask & IFCAP_RXCSUM) != 0 &&
1076388214e4SPyun YongHyeon 		    (IFCAP_RXCSUM & ifp->if_capabilities) != 0) {
1077efb74172SPyun YongHyeon 			ifp->if_capenable ^= IFCAP_RXCSUM;
1078388214e4SPyun YongHyeon 			if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0)
1079388214e4SPyun YongHyeon 				reinit = 1;
1080388214e4SPyun YongHyeon 		}
1081efb74172SPyun YongHyeon 		if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
1082efb74172SPyun YongHyeon 		    (IFCAP_VLAN_HWCSUM & ifp->if_capabilities) != 0)
1083efb74172SPyun YongHyeon 			ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
108498e02aebSPyun YongHyeon 		if ((mask & IFCAP_TSO4) != 0 &&
108598e02aebSPyun YongHyeon 		    (IFCAP_TSO4 & ifp->if_capabilities) != 0) {
10860dbe28b3SPyun YongHyeon 			ifp->if_capenable ^= IFCAP_TSO4;
108798e02aebSPyun YongHyeon 			if ((IFCAP_TSO4 & ifp->if_capenable) != 0)
10880dbe28b3SPyun YongHyeon 				ifp->if_hwassist |= CSUM_TSO;
10890dbe28b3SPyun YongHyeon 			else
10900dbe28b3SPyun YongHyeon 				ifp->if_hwassist &= ~CSUM_TSO;
10910dbe28b3SPyun YongHyeon 		}
10924858893bSPyun YongHyeon 		if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
10934858893bSPyun YongHyeon 		    (IFCAP_VLAN_HWTSO & ifp->if_capabilities) != 0)
10944858893bSPyun YongHyeon 			ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
10954858893bSPyun YongHyeon 		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
10964858893bSPyun YongHyeon 		    (IFCAP_VLAN_HWTAGGING & ifp->if_capabilities) != 0) {
10974858893bSPyun YongHyeon 			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
10984858893bSPyun YongHyeon 			if ((IFCAP_VLAN_HWTAGGING & ifp->if_capenable) == 0)
10993edfecaaSPyun YongHyeon 				ifp->if_capenable &=
11003edfecaaSPyun YongHyeon 				    ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM);
11014858893bSPyun YongHyeon 			msk_setvlan(sc_if, ifp);
11024858893bSPyun YongHyeon 		}
110385b340cbSPyun YongHyeon 		if (ifp->if_mtu > ETHERMTU &&
1104e2b16603SPyun YongHyeon 		    (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) {
1105a109c74fSPyun YongHyeon 			ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO);
1106a109c74fSPyun YongHyeon 			ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM);
1107a109c74fSPyun YongHyeon 		}
11080dbe28b3SPyun YongHyeon 		VLAN_CAPABILITIES(ifp);
1109388214e4SPyun YongHyeon 		if (reinit > 0 && (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1110388214e4SPyun YongHyeon 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1111388214e4SPyun YongHyeon 			msk_init_locked(sc_if);
1112388214e4SPyun YongHyeon 		}
11130dbe28b3SPyun YongHyeon 		MSK_IF_UNLOCK(sc_if);
11140dbe28b3SPyun YongHyeon 		break;
11150dbe28b3SPyun YongHyeon 	default:
11160dbe28b3SPyun YongHyeon 		error = ether_ioctl(ifp, command, data);
11170dbe28b3SPyun YongHyeon 		break;
11180dbe28b3SPyun YongHyeon 	}
11190dbe28b3SPyun YongHyeon 
11200dbe28b3SPyun YongHyeon 	return (error);
11210dbe28b3SPyun YongHyeon }
11220dbe28b3SPyun YongHyeon 
11230dbe28b3SPyun YongHyeon static int
11240dbe28b3SPyun YongHyeon mskc_probe(device_t dev)
11250dbe28b3SPyun YongHyeon {
11260dbe28b3SPyun YongHyeon 	struct msk_product *mp;
11270dbe28b3SPyun YongHyeon 	uint16_t vendor, devid;
11280dbe28b3SPyun YongHyeon 	int i;
11290dbe28b3SPyun YongHyeon 
11300dbe28b3SPyun YongHyeon 	vendor = pci_get_vendor(dev);
11310dbe28b3SPyun YongHyeon 	devid = pci_get_device(dev);
11320dbe28b3SPyun YongHyeon 	mp = msk_products;
11330dbe28b3SPyun YongHyeon 	for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]);
11340dbe28b3SPyun YongHyeon 	    i++, mp++) {
11350dbe28b3SPyun YongHyeon 		if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) {
11360dbe28b3SPyun YongHyeon 			device_set_desc(dev, mp->msk_name);
11370dbe28b3SPyun YongHyeon 			return (BUS_PROBE_DEFAULT);
11380dbe28b3SPyun YongHyeon 		}
11390dbe28b3SPyun YongHyeon 	}
11400dbe28b3SPyun YongHyeon 
11410dbe28b3SPyun YongHyeon 	return (ENXIO);
11420dbe28b3SPyun YongHyeon }
11430dbe28b3SPyun YongHyeon 
11440dbe28b3SPyun YongHyeon static int
11450dbe28b3SPyun YongHyeon mskc_setup_rambuffer(struct msk_softc *sc)
11460dbe28b3SPyun YongHyeon {
1147e4a5f4e0SPyun YongHyeon 	int next;
11480dbe28b3SPyun YongHyeon 	int i;
11490dbe28b3SPyun YongHyeon 
11500dbe28b3SPyun YongHyeon 	/* Get adapter SRAM size. */
115183c04c93SPyun YongHyeon 	sc->msk_ramsize = CSR_READ_1(sc, B2_E_0) * 4;
11520dbe28b3SPyun YongHyeon 	if (bootverbose)
11530dbe28b3SPyun YongHyeon 		device_printf(sc->msk_dev,
11540dbe28b3SPyun YongHyeon 		    "RAM buffer size : %dKB\n", sc->msk_ramsize);
115583c04c93SPyun YongHyeon 	if (sc->msk_ramsize == 0)
115683c04c93SPyun YongHyeon 		return (0);
115783c04c93SPyun YongHyeon 
115883c04c93SPyun YongHyeon 	sc->msk_pflags |= MSK_FLAG_RAMBUF;
11590dbe28b3SPyun YongHyeon 	/*
1160e4a5f4e0SPyun YongHyeon 	 * Give receiver 2/3 of memory and round down to the multiple
1161b1ce21c6SRebecca Cran 	 * of 1024. Tx/Rx RAM buffer size of Yukon II should be multiple
1162e4a5f4e0SPyun YongHyeon 	 * of 1024.
11630dbe28b3SPyun YongHyeon 	 */
1164e4a5f4e0SPyun YongHyeon 	sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024);
1165e4a5f4e0SPyun YongHyeon 	sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize;
11660dbe28b3SPyun YongHyeon 	for (i = 0, next = 0; i < sc->msk_num_port; i++) {
11670dbe28b3SPyun YongHyeon 		sc->msk_rxqstart[i] = next;
1168e4a5f4e0SPyun YongHyeon 		sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1;
11690dbe28b3SPyun YongHyeon 		next = sc->msk_rxqend[i] + 1;
11700dbe28b3SPyun YongHyeon 		sc->msk_txqstart[i] = next;
1171e4a5f4e0SPyun YongHyeon 		sc->msk_txqend[i] = next + sc->msk_txqsize - 1;
11720dbe28b3SPyun YongHyeon 		next = sc->msk_txqend[i] + 1;
11730dbe28b3SPyun YongHyeon 		if (bootverbose) {
11740dbe28b3SPyun YongHyeon 			device_printf(sc->msk_dev,
11750dbe28b3SPyun YongHyeon 			    "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i,
1176e4a5f4e0SPyun YongHyeon 			    sc->msk_rxqsize / 1024, sc->msk_rxqstart[i],
11770dbe28b3SPyun YongHyeon 			    sc->msk_rxqend[i]);
11780dbe28b3SPyun YongHyeon 			device_printf(sc->msk_dev,
11790dbe28b3SPyun YongHyeon 			    "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i,
1180e4a5f4e0SPyun YongHyeon 			    sc->msk_txqsize / 1024, sc->msk_txqstart[i],
11810dbe28b3SPyun YongHyeon 			    sc->msk_txqend[i]);
11820dbe28b3SPyun YongHyeon 		}
11830dbe28b3SPyun YongHyeon 	}
11840dbe28b3SPyun YongHyeon 
11850dbe28b3SPyun YongHyeon 	return (0);
11860dbe28b3SPyun YongHyeon }
11870dbe28b3SPyun YongHyeon 
11880dbe28b3SPyun YongHyeon static void
11890dbe28b3SPyun YongHyeon msk_phy_power(struct msk_softc *sc, int mode)
11900dbe28b3SPyun YongHyeon {
1191846e6d79SPyun YongHyeon 	uint32_t our, val;
11920dbe28b3SPyun YongHyeon 	int i;
11930dbe28b3SPyun YongHyeon 
11940dbe28b3SPyun YongHyeon 	switch (mode) {
11950dbe28b3SPyun YongHyeon 	case MSK_PHY_POWERUP:
11960dbe28b3SPyun YongHyeon 		/* Switch power to VCC (WA for VAUX problem). */
11970dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, B0_POWER_CTRL,
11980dbe28b3SPyun YongHyeon 		    PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
11990dbe28b3SPyun YongHyeon 		/* Disable Core Clock Division, set Clock Select to 0. */
12000dbe28b3SPyun YongHyeon 		CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
12010dbe28b3SPyun YongHyeon 
12020dbe28b3SPyun YongHyeon 		val = 0;
12030dbe28b3SPyun YongHyeon 		if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
12040dbe28b3SPyun YongHyeon 		    sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
12050dbe28b3SPyun YongHyeon 			/* Enable bits are inverted. */
12060dbe28b3SPyun YongHyeon 			val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
12070dbe28b3SPyun YongHyeon 			      Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
12080dbe28b3SPyun YongHyeon 			      Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
12090dbe28b3SPyun YongHyeon 		}
12100dbe28b3SPyun YongHyeon 		/*
12110dbe28b3SPyun YongHyeon 		 * Enable PCI & Core Clock, enable clock gating for both Links.
12120dbe28b3SPyun YongHyeon 		 */
12130dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
12140dbe28b3SPyun YongHyeon 
1215*c6a34f76SPyun YongHyeon 		our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
1216*c6a34f76SPyun YongHyeon 		our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD);
1217daf29227SPyun YongHyeon 		if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
1218846e6d79SPyun YongHyeon 			if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
12190dbe28b3SPyun YongHyeon 				/* Deassert Low Power for 1st PHY. */
1220*c6a34f76SPyun YongHyeon 				our |= PCI_Y2_PHY1_COMA;
12210dbe28b3SPyun YongHyeon 				if (sc->msk_num_port > 1)
1222*c6a34f76SPyun YongHyeon 					our |= PCI_Y2_PHY2_COMA;
1223846e6d79SPyun YongHyeon 			}
1224daf29227SPyun YongHyeon 		}
1225*c6a34f76SPyun YongHyeon 		if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U ||
1226*c6a34f76SPyun YongHyeon 		    sc->msk_hw_id == CHIP_ID_YUKON_EX ||
1227*c6a34f76SPyun YongHyeon 		    sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) {
1228*c6a34f76SPyun YongHyeon 			val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4);
1229*c6a34f76SPyun YongHyeon 			val &= (PCI_FORCE_ASPM_REQUEST |
1230*c6a34f76SPyun YongHyeon 			    PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY |
1231*c6a34f76SPyun YongHyeon 			    PCI_ASPM_CLKRUN_REQUEST);
12320dbe28b3SPyun YongHyeon 			/* Set all bits to 0 except bits 15..12. */
1233*c6a34f76SPyun YongHyeon 			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val);
1234*c6a34f76SPyun YongHyeon 			val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5);
1235*c6a34f76SPyun YongHyeon 			val &= PCI_CTL_TIM_VMAIN_AV_MSK;
1236*c6a34f76SPyun YongHyeon 			CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val);
1237b45923a6SPyun YongHyeon 			CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0);
1238*c6a34f76SPyun YongHyeon 			CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON);
1239daf29227SPyun YongHyeon 			/*
1240daf29227SPyun YongHyeon 			 * Disable status race, workaround for
1241daf29227SPyun YongHyeon 			 * Yukon EC Ultra & Yukon EX.
1242daf29227SPyun YongHyeon 			 */
1243daf29227SPyun YongHyeon 			val = CSR_READ_4(sc, B2_GP_IO);
1244daf29227SPyun YongHyeon 			val |= GLB_GPIO_STAT_RACE_DIS;
1245daf29227SPyun YongHyeon 			CSR_WRITE_4(sc, B2_GP_IO, val);
1246daf29227SPyun YongHyeon 			CSR_READ_4(sc, B2_GP_IO);
12470dbe28b3SPyun YongHyeon 		}
1248*c6a34f76SPyun YongHyeon 		/* Release PHY from PowerDown/COMA mode. */
1249*c6a34f76SPyun YongHyeon 		CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our);
1250*c6a34f76SPyun YongHyeon 
12510dbe28b3SPyun YongHyeon 		for (i = 0; i < sc->msk_num_port; i++) {
12520dbe28b3SPyun YongHyeon 			CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
12530dbe28b3SPyun YongHyeon 			    GMLC_RST_SET);
12540dbe28b3SPyun YongHyeon 			CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL),
12550dbe28b3SPyun YongHyeon 			    GMLC_RST_CLR);
12560dbe28b3SPyun YongHyeon 		}
12570dbe28b3SPyun YongHyeon 		break;
12580dbe28b3SPyun YongHyeon 	case MSK_PHY_POWERDOWN:
1259b45923a6SPyun YongHyeon 		val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1);
12600dbe28b3SPyun YongHyeon 		val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD;
12610dbe28b3SPyun YongHyeon 		if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
12620dbe28b3SPyun YongHyeon 		    sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
12630dbe28b3SPyun YongHyeon 			val &= ~PCI_Y2_PHY1_COMA;
12640dbe28b3SPyun YongHyeon 			if (sc->msk_num_port > 1)
12650dbe28b3SPyun YongHyeon 				val &= ~PCI_Y2_PHY2_COMA;
12660dbe28b3SPyun YongHyeon 		}
1267b45923a6SPyun YongHyeon 		CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val);
12680dbe28b3SPyun YongHyeon 
12690dbe28b3SPyun YongHyeon 		val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
12700dbe28b3SPyun YongHyeon 		      Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
12710dbe28b3SPyun YongHyeon 		      Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS;
12720dbe28b3SPyun YongHyeon 		if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
12730dbe28b3SPyun YongHyeon 		    sc->msk_hw_rev > CHIP_REV_YU_XL_A1) {
12740dbe28b3SPyun YongHyeon 			/* Enable bits are inverted. */
12750dbe28b3SPyun YongHyeon 			val = 0;
12760dbe28b3SPyun YongHyeon 		}
12770dbe28b3SPyun YongHyeon 		/*
12780dbe28b3SPyun YongHyeon 		 * Disable PCI & Core Clock, disable clock gating for
12790dbe28b3SPyun YongHyeon 		 * both Links.
12800dbe28b3SPyun YongHyeon 		 */
12810dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val);
12820dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, B0_POWER_CTRL,
12830dbe28b3SPyun YongHyeon 		    PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
12840dbe28b3SPyun YongHyeon 		break;
12850dbe28b3SPyun YongHyeon 	default:
12860dbe28b3SPyun YongHyeon 		break;
12870dbe28b3SPyun YongHyeon 	}
12880dbe28b3SPyun YongHyeon }
12890dbe28b3SPyun YongHyeon 
12900dbe28b3SPyun YongHyeon static void
12910dbe28b3SPyun YongHyeon mskc_reset(struct msk_softc *sc)
12920dbe28b3SPyun YongHyeon {
12930dbe28b3SPyun YongHyeon 	bus_addr_t addr;
12940dbe28b3SPyun YongHyeon 	uint16_t status;
12950dbe28b3SPyun YongHyeon 	uint32_t val;
1296d91192e3SPyun YongHyeon 	int i, initram;
12970dbe28b3SPyun YongHyeon 
12980dbe28b3SPyun YongHyeon 	/* Disable ASF. */
1299daf29227SPyun YongHyeon 	if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
1300daf29227SPyun YongHyeon 		status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR);
1301daf29227SPyun YongHyeon 		/* Clear AHB bridge & microcontroller reset. */
1302daf29227SPyun YongHyeon 		status &= ~(Y2_ASF_HCU_CCSR_AHB_RST |
1303daf29227SPyun YongHyeon 		    Y2_ASF_HCU_CCSR_CPU_RST_MODE);
1304daf29227SPyun YongHyeon 		/* Clear ASF microcontroller state. */
1305daf29227SPyun YongHyeon 		status &= ~ Y2_ASF_HCU_CCSR_UC_STATE_MSK;
1306daf29227SPyun YongHyeon 		CSR_WRITE_2(sc, B28_Y2_ASF_HCU_CCSR, status);
1307daf29227SPyun YongHyeon 	} else
1308daf29227SPyun YongHyeon 		CSR_WRITE_1(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
13090dbe28b3SPyun YongHyeon 	CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE);
1310daf29227SPyun YongHyeon 
13110dbe28b3SPyun YongHyeon 	/*
13120dbe28b3SPyun YongHyeon 	 * Since we disabled ASF, S/W reset is required for Power Management.
13130dbe28b3SPyun YongHyeon 	 */
13140dbe28b3SPyun YongHyeon 	CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
13150dbe28b3SPyun YongHyeon 	CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
13160dbe28b3SPyun YongHyeon 
13170dbe28b3SPyun YongHyeon 	/* Clear all error bits in the PCI status register. */
13180dbe28b3SPyun YongHyeon 	status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
13190dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
13200dbe28b3SPyun YongHyeon 
13210dbe28b3SPyun YongHyeon 	pci_write_config(sc->msk_dev, PCIR_STATUS, status |
13220dbe28b3SPyun YongHyeon 	    PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
1323d1a02e09SJohn Baldwin 	    PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2);
13240dbe28b3SPyun YongHyeon 	CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR);
13250dbe28b3SPyun YongHyeon 
13260dbe28b3SPyun YongHyeon 	switch (sc->msk_bustype) {
13270dbe28b3SPyun YongHyeon 	case MSK_PEX_BUS:
13280dbe28b3SPyun YongHyeon 		/* Clear all PEX errors. */
13290dbe28b3SPyun YongHyeon 		CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
13300dbe28b3SPyun YongHyeon 		val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
13310dbe28b3SPyun YongHyeon 		if ((val & PEX_RX_OV) != 0) {
13320dbe28b3SPyun YongHyeon 			sc->msk_intrmask &= ~Y2_IS_HW_ERR;
13330dbe28b3SPyun YongHyeon 			sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
13340dbe28b3SPyun YongHyeon 		}
13350dbe28b3SPyun YongHyeon 		break;
13360dbe28b3SPyun YongHyeon 	case MSK_PCI_BUS:
13370dbe28b3SPyun YongHyeon 	case MSK_PCIX_BUS:
13380dbe28b3SPyun YongHyeon 		/* Set Cache Line Size to 2(8bytes) if configured to 0. */
13390dbe28b3SPyun YongHyeon 		val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1);
13400dbe28b3SPyun YongHyeon 		if (val == 0)
13410dbe28b3SPyun YongHyeon 			pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1);
13420dbe28b3SPyun YongHyeon 		if (sc->msk_bustype == MSK_PCIX_BUS) {
13430dbe28b3SPyun YongHyeon 			/* Set Cache Line Size opt. */
13440dbe28b3SPyun YongHyeon 			val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4);
13450dbe28b3SPyun YongHyeon 			val |= PCI_CLS_OPT;
13460dbe28b3SPyun YongHyeon 			pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4);
13470dbe28b3SPyun YongHyeon 		}
13480dbe28b3SPyun YongHyeon 		break;
13490dbe28b3SPyun YongHyeon 	}
13500dbe28b3SPyun YongHyeon 	/* Set PHY power state. */
13510dbe28b3SPyun YongHyeon 	msk_phy_power(sc, MSK_PHY_POWERUP);
13520dbe28b3SPyun YongHyeon 
13530dbe28b3SPyun YongHyeon 	/* Reset GPHY/GMAC Control */
13540dbe28b3SPyun YongHyeon 	for (i = 0; i < sc->msk_num_port; i++) {
13550dbe28b3SPyun YongHyeon 		/* GPHY Control reset. */
135610e71e22SPyun YongHyeon 		CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET);
135710e71e22SPyun YongHyeon 		CSR_WRITE_1(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR);
13580dbe28b3SPyun YongHyeon 		/* GMAC Control reset. */
13590dbe28b3SPyun YongHyeon 		CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET);
13600dbe28b3SPyun YongHyeon 		CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR);
13610dbe28b3SPyun YongHyeon 		CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF);
1362daf29227SPyun YongHyeon 		if (sc->msk_hw_id == CHIP_ID_YUKON_EX)
1363daf29227SPyun YongHyeon 			CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL),
1364daf29227SPyun YongHyeon 			    GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON |
1365daf29227SPyun YongHyeon 			    GMC_BYP_RETR_ON);
13660dbe28b3SPyun YongHyeon 	}
1367e19bd6eeSPyun YongHyeon 	if (sc->msk_hw_id == CHIP_ID_YUKON_OPT && sc->msk_hw_rev == 0) {
1368e19bd6eeSPyun YongHyeon 		/* Disable PCIe PHY powerdown(reg 0x80, bit7). */
1369e19bd6eeSPyun YongHyeon 		CSR_WRITE_4(sc, Y2_PEX_PHY_DATA, (0x0080 << 16) | 0x0080);
1370e19bd6eeSPyun YongHyeon 	}
13710dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
13720dbe28b3SPyun YongHyeon 
13730dbe28b3SPyun YongHyeon 	/* LED On. */
13740dbe28b3SPyun YongHyeon 	CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON);
13750dbe28b3SPyun YongHyeon 
13760dbe28b3SPyun YongHyeon 	/* Clear TWSI IRQ. */
13770dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ);
13780dbe28b3SPyun YongHyeon 
13790dbe28b3SPyun YongHyeon 	/* Turn off hardware timer. */
13800dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP);
13810dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ);
13820dbe28b3SPyun YongHyeon 
13830dbe28b3SPyun YongHyeon 	/* Turn off descriptor polling. */
13840dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP);
13850dbe28b3SPyun YongHyeon 
13860dbe28b3SPyun YongHyeon 	/* Turn off time stamps. */
13870dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP);
13880dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
13890dbe28b3SPyun YongHyeon 
1390d91192e3SPyun YongHyeon 	initram = 0;
1391d91192e3SPyun YongHyeon 	if (sc->msk_hw_id == CHIP_ID_YUKON_XL ||
1392d91192e3SPyun YongHyeon 	    sc->msk_hw_id == CHIP_ID_YUKON_EC ||
1393d91192e3SPyun YongHyeon 	    sc->msk_hw_id == CHIP_ID_YUKON_FE)
1394d91192e3SPyun YongHyeon 		initram++;
1395d91192e3SPyun YongHyeon 
13960dbe28b3SPyun YongHyeon 	/* Configure timeout values. */
1397d91192e3SPyun YongHyeon 	for (i = 0; initram > 0 && i < sc->msk_num_port; i++) {
13980dbe28b3SPyun YongHyeon 		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET);
13990dbe28b3SPyun YongHyeon 		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
14000dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1),
14010dbe28b3SPyun YongHyeon 		    MSK_RI_TO_53);
14020dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1),
14030dbe28b3SPyun YongHyeon 		    MSK_RI_TO_53);
14040dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1),
14050dbe28b3SPyun YongHyeon 		    MSK_RI_TO_53);
14060dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1),
14070dbe28b3SPyun YongHyeon 		    MSK_RI_TO_53);
14080dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1),
14090dbe28b3SPyun YongHyeon 		    MSK_RI_TO_53);
14100dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1),
14110dbe28b3SPyun YongHyeon 		    MSK_RI_TO_53);
14120dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2),
14130dbe28b3SPyun YongHyeon 		    MSK_RI_TO_53);
14140dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2),
14150dbe28b3SPyun YongHyeon 		    MSK_RI_TO_53);
14160dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2),
14170dbe28b3SPyun YongHyeon 		    MSK_RI_TO_53);
14180dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2),
14190dbe28b3SPyun YongHyeon 		    MSK_RI_TO_53);
14200dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2),
14210dbe28b3SPyun YongHyeon 		    MSK_RI_TO_53);
14220dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2),
14230dbe28b3SPyun YongHyeon 		    MSK_RI_TO_53);
14240dbe28b3SPyun YongHyeon 	}
14250dbe28b3SPyun YongHyeon 
14260dbe28b3SPyun YongHyeon 	/* Disable all interrupts. */
14270dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
14280dbe28b3SPyun YongHyeon 	CSR_READ_4(sc, B0_HWE_IMSK);
14290dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, B0_IMSK, 0);
14300dbe28b3SPyun YongHyeon 	CSR_READ_4(sc, B0_IMSK);
14310dbe28b3SPyun YongHyeon 
14320dbe28b3SPyun YongHyeon         /*
14330dbe28b3SPyun YongHyeon          * On dual port PCI-X card, there is an problem where status
14340dbe28b3SPyun YongHyeon          * can be received out of order due to split transactions.
14350dbe28b3SPyun YongHyeon          */
14367420e9dcSPyun YongHyeon 	if (sc->msk_pcixcap != 0 && sc->msk_num_port > 1) {
14370dbe28b3SPyun YongHyeon 		uint16_t pcix_cmd;
14380dbe28b3SPyun YongHyeon 
14397420e9dcSPyun YongHyeon 		pcix_cmd = pci_read_config(sc->msk_dev,
14407420e9dcSPyun YongHyeon 		    sc->msk_pcixcap + PCIXR_COMMAND, 2);
14410dbe28b3SPyun YongHyeon 		/* Clear Max Outstanding Split Transactions. */
14427420e9dcSPyun YongHyeon 		pcix_cmd &= ~PCIXM_COMMAND_MAX_SPLITS;
14430dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
14447420e9dcSPyun YongHyeon 		pci_write_config(sc->msk_dev,
14457420e9dcSPyun YongHyeon 		    sc->msk_pcixcap + PCIXR_COMMAND, pcix_cmd, 2);
14460dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
14470dbe28b3SPyun YongHyeon         }
14487420e9dcSPyun YongHyeon 	if (sc->msk_expcap != 0) {
14497420e9dcSPyun YongHyeon 		/* Change Max. Read Request Size to 2048 bytes. */
14507420e9dcSPyun YongHyeon 		if (pci_get_max_read_req(sc->msk_dev) == 512)
14517420e9dcSPyun YongHyeon 			pci_set_max_read_req(sc->msk_dev, 2048);
14520dbe28b3SPyun YongHyeon 	}
14530dbe28b3SPyun YongHyeon 
14540dbe28b3SPyun YongHyeon 	/* Clear status list. */
14550dbe28b3SPyun YongHyeon 	bzero(sc->msk_stat_ring,
14560dbe28b3SPyun YongHyeon 	    sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT);
14570dbe28b3SPyun YongHyeon 	sc->msk_stat_cons = 0;
14580dbe28b3SPyun YongHyeon 	bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
14590dbe28b3SPyun YongHyeon 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
14600dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET);
14610dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR);
14620dbe28b3SPyun YongHyeon 	/* Set the status list base address. */
14630dbe28b3SPyun YongHyeon 	addr = sc->msk_stat_ring_paddr;
14640dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr));
14650dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr));
14660dbe28b3SPyun YongHyeon 	/* Set the status list last index. */
14670dbe28b3SPyun YongHyeon 	CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1);
1468cfd540e7SPyun YongHyeon 	if (sc->msk_hw_id == CHIP_ID_YUKON_EC &&
1469cfd540e7SPyun YongHyeon 	    sc->msk_hw_rev == CHIP_REV_YU_EC_A1) {
14700dbe28b3SPyun YongHyeon 		/* WA for dev. #4.3 */
14710dbe28b3SPyun YongHyeon 		CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK);
14720dbe28b3SPyun YongHyeon 		/* WA for dev. #4.18 */
14730dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21);
14740dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07);
14750dbe28b3SPyun YongHyeon 	} else {
14760dbe28b3SPyun YongHyeon 		CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a);
14770dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10);
1478cfd540e7SPyun YongHyeon 		if (sc->msk_hw_id == CHIP_ID_YUKON_XL &&
1479cfd540e7SPyun YongHyeon 		    sc->msk_hw_rev == CHIP_REV_YU_XL_A0)
1480cfd540e7SPyun YongHyeon 			CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04);
1481cfd540e7SPyun YongHyeon 		else
1482cfd540e7SPyun YongHyeon 			CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10);
14830dbe28b3SPyun YongHyeon 		CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190);
14840dbe28b3SPyun YongHyeon 	}
14850dbe28b3SPyun YongHyeon 	/*
14860dbe28b3SPyun YongHyeon 	 * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI.
14870dbe28b3SPyun YongHyeon 	 */
14880dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000));
14890dbe28b3SPyun YongHyeon 
14900dbe28b3SPyun YongHyeon 	/* Enable status unit. */
14910dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON);
14920dbe28b3SPyun YongHyeon 
14930dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START);
14940dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START);
14950dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START);
14960dbe28b3SPyun YongHyeon }
14970dbe28b3SPyun YongHyeon 
14980dbe28b3SPyun YongHyeon static int
14990dbe28b3SPyun YongHyeon msk_probe(device_t dev)
15000dbe28b3SPyun YongHyeon {
15010dbe28b3SPyun YongHyeon 	struct msk_softc *sc;
15020dbe28b3SPyun YongHyeon 	char desc[100];
15030dbe28b3SPyun YongHyeon 
15040dbe28b3SPyun YongHyeon 	sc = device_get_softc(device_get_parent(dev));
15050dbe28b3SPyun YongHyeon 	/*
15060dbe28b3SPyun YongHyeon 	 * Not much to do here. We always know there will be
15070dbe28b3SPyun YongHyeon 	 * at least one GMAC present, and if there are two,
15080dbe28b3SPyun YongHyeon 	 * mskc_attach() will create a second device instance
15090dbe28b3SPyun YongHyeon 	 * for us.
15100dbe28b3SPyun YongHyeon 	 */
15110dbe28b3SPyun YongHyeon 	snprintf(desc, sizeof(desc),
15120dbe28b3SPyun YongHyeon 	    "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x",
15130dbe28b3SPyun YongHyeon 	    model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id,
15140dbe28b3SPyun YongHyeon 	    sc->msk_hw_rev);
15150dbe28b3SPyun YongHyeon 	device_set_desc_copy(dev, desc);
15160dbe28b3SPyun YongHyeon 
15170dbe28b3SPyun YongHyeon 	return (BUS_PROBE_DEFAULT);
15180dbe28b3SPyun YongHyeon }
15190dbe28b3SPyun YongHyeon 
15200dbe28b3SPyun YongHyeon static int
15210dbe28b3SPyun YongHyeon msk_attach(device_t dev)
15220dbe28b3SPyun YongHyeon {
15230dbe28b3SPyun YongHyeon 	struct msk_softc *sc;
15240dbe28b3SPyun YongHyeon 	struct msk_if_softc *sc_if;
15250dbe28b3SPyun YongHyeon 	struct ifnet *ifp;
1526fcb62a8bSPyun YongHyeon 	struct msk_mii_data *mmd;
15270dbe28b3SPyun YongHyeon 	int i, port, error;
15280dbe28b3SPyun YongHyeon 	uint8_t eaddr[6];
15290dbe28b3SPyun YongHyeon 
15300dbe28b3SPyun YongHyeon 	if (dev == NULL)
15310dbe28b3SPyun YongHyeon 		return (EINVAL);
15320dbe28b3SPyun YongHyeon 
15330dbe28b3SPyun YongHyeon 	error = 0;
15340dbe28b3SPyun YongHyeon 	sc_if = device_get_softc(dev);
15350dbe28b3SPyun YongHyeon 	sc = device_get_softc(device_get_parent(dev));
1536fcb62a8bSPyun YongHyeon 	mmd = device_get_ivars(dev);
1537fcb62a8bSPyun YongHyeon 	port = mmd->port;
15380dbe28b3SPyun YongHyeon 
15390dbe28b3SPyun YongHyeon 	sc_if->msk_if_dev = dev;
15400dbe28b3SPyun YongHyeon 	sc_if->msk_port = port;
15410dbe28b3SPyun YongHyeon 	sc_if->msk_softc = sc;
154283c04c93SPyun YongHyeon 	sc_if->msk_flags = sc->msk_pflags;
15430dbe28b3SPyun YongHyeon 	sc->msk_if[port] = sc_if;
15440dbe28b3SPyun YongHyeon 	/* Setup Tx/Rx queue register offsets. */
15450dbe28b3SPyun YongHyeon 	if (port == MSK_PORT_A) {
15460dbe28b3SPyun YongHyeon 		sc_if->msk_txq = Q_XA1;
15470dbe28b3SPyun YongHyeon 		sc_if->msk_txsq = Q_XS1;
15480dbe28b3SPyun YongHyeon 		sc_if->msk_rxq = Q_R1;
15490dbe28b3SPyun YongHyeon 	} else {
15500dbe28b3SPyun YongHyeon 		sc_if->msk_txq = Q_XA2;
15510dbe28b3SPyun YongHyeon 		sc_if->msk_txsq = Q_XS2;
15520dbe28b3SPyun YongHyeon 		sc_if->msk_rxq = Q_R2;
15530dbe28b3SPyun YongHyeon 	}
15540dbe28b3SPyun YongHyeon 
15550dbe28b3SPyun YongHyeon 	callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0);
15563a91ee71SPyun YongHyeon 	msk_sysctl_node(sc_if);
15570dbe28b3SPyun YongHyeon 
15580dbe28b3SPyun YongHyeon 	if ((error = msk_txrx_dma_alloc(sc_if) != 0))
15590dbe28b3SPyun YongHyeon 		goto fail;
156085b340cbSPyun YongHyeon 	msk_rx_dma_jalloc(sc_if);
15610dbe28b3SPyun YongHyeon 
15620dbe28b3SPyun YongHyeon 	ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER);
15630dbe28b3SPyun YongHyeon 	if (ifp == NULL) {
15640dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev, "can not if_alloc()\n");
15650dbe28b3SPyun YongHyeon 		error = ENOSPC;
15660dbe28b3SPyun YongHyeon 		goto fail;
15670dbe28b3SPyun YongHyeon 	}
15680dbe28b3SPyun YongHyeon 	ifp->if_softc = sc_if;
15690dbe28b3SPyun YongHyeon 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
15700dbe28b3SPyun YongHyeon 	ifp->if_mtu = ETHERMTU;
15710dbe28b3SPyun YongHyeon 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1572a109c74fSPyun YongHyeon 	ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4;
1573efb74172SPyun YongHyeon 	/*
1574388214e4SPyun YongHyeon 	 * Enable Rx checksum offloading if controller supports
1575388214e4SPyun YongHyeon 	 * new descriptor formant and controller is not Yukon XL.
1576efb74172SPyun YongHyeon 	 */
1577388214e4SPyun YongHyeon 	if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
1578388214e4SPyun YongHyeon 	    sc->msk_hw_id != CHIP_ID_YUKON_XL)
1579388214e4SPyun YongHyeon 		ifp->if_capabilities |= IFCAP_RXCSUM;
1580efb74172SPyun YongHyeon 	if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 &&
1581efb74172SPyun YongHyeon 	    (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0)
1582efb74172SPyun YongHyeon 		ifp->if_capabilities |= IFCAP_RXCSUM;
1583a109c74fSPyun YongHyeon 	ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO;
15840dbe28b3SPyun YongHyeon 	ifp->if_capenable = ifp->if_capabilities;
15850dbe28b3SPyun YongHyeon 	ifp->if_ioctl = msk_ioctl;
15860dbe28b3SPyun YongHyeon 	ifp->if_start = msk_start;
15870dbe28b3SPyun YongHyeon 	ifp->if_init = msk_init;
15880dbe28b3SPyun YongHyeon 	IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1);
15890dbe28b3SPyun YongHyeon 	ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1;
15900dbe28b3SPyun YongHyeon 	IFQ_SET_READY(&ifp->if_snd);
15910dbe28b3SPyun YongHyeon 	/*
15920dbe28b3SPyun YongHyeon 	 * Get station address for this interface. Note that
15930dbe28b3SPyun YongHyeon 	 * dual port cards actually come with three station
15940dbe28b3SPyun YongHyeon 	 * addresses: one for each port, plus an extra. The
15950dbe28b3SPyun YongHyeon 	 * extra one is used by the SysKonnect driver software
15960dbe28b3SPyun YongHyeon 	 * as a 'virtual' station address for when both ports
15970dbe28b3SPyun YongHyeon 	 * are operating in failover mode. Currently we don't
15980dbe28b3SPyun YongHyeon 	 * use this extra address.
15990dbe28b3SPyun YongHyeon 	 */
16000dbe28b3SPyun YongHyeon 	MSK_IF_LOCK(sc_if);
16010dbe28b3SPyun YongHyeon 	for (i = 0; i < ETHER_ADDR_LEN; i++)
16020dbe28b3SPyun YongHyeon 		eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i);
16030dbe28b3SPyun YongHyeon 
16040dbe28b3SPyun YongHyeon 	/*
16050dbe28b3SPyun YongHyeon 	 * Call MI attach routine.  Can't hold locks when calling into ether_*.
16060dbe28b3SPyun YongHyeon 	 */
16070dbe28b3SPyun YongHyeon 	MSK_IF_UNLOCK(sc_if);
16080dbe28b3SPyun YongHyeon 	ether_ifattach(ifp, eaddr);
16090dbe28b3SPyun YongHyeon 	MSK_IF_LOCK(sc_if);
16100dbe28b3SPyun YongHyeon 
1611224003b7SPyun YongHyeon 	/* VLAN capability setup */
1612224003b7SPyun YongHyeon 	ifp->if_capabilities |= IFCAP_VLAN_MTU;
1613224003b7SPyun YongHyeon 	if ((sc_if->msk_flags & MSK_FLAG_NOHWVLAN) == 0) {
161406ff0944SPyun YongHyeon 		/*
161506ff0944SPyun YongHyeon 		 * Due to Tx checksum offload hardware bugs, msk(4) manually
161606ff0944SPyun YongHyeon 		 * computes checksum for short frames. For VLAN tagged frames
161706ff0944SPyun YongHyeon 		 * this workaround does not work so disable checksum offload
161806ff0944SPyun YongHyeon 		 * for VLAN interface.
161906ff0944SPyun YongHyeon 		 */
16204858893bSPyun YongHyeon         	ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWTSO;
1621efb74172SPyun YongHyeon 		/*
1622b1ce21c6SRebecca Cran 		 * Enable Rx checksum offloading for VLAN tagged frames
1623efb74172SPyun YongHyeon 		 * if controller support new descriptor format.
1624efb74172SPyun YongHyeon 		 */
1625efb74172SPyun YongHyeon 		if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0 &&
1626efb74172SPyun YongHyeon 		    (sc_if->msk_flags & MSK_FLAG_NORX_CSUM) == 0)
1627efb74172SPyun YongHyeon 			ifp->if_capabilities |= IFCAP_VLAN_HWCSUM;
1628224003b7SPyun YongHyeon 	}
16290dbe28b3SPyun YongHyeon 	ifp->if_capenable = ifp->if_capabilities;
16300dbe28b3SPyun YongHyeon 
16310dbe28b3SPyun YongHyeon 	/*
16320dbe28b3SPyun YongHyeon 	 * Tell the upper layer(s) we support long frames.
16330dbe28b3SPyun YongHyeon 	 * Must appear after the call to ether_ifattach() because
16340dbe28b3SPyun YongHyeon 	 * ether_ifattach() sets ifi_hdrlen to the default value.
16350dbe28b3SPyun YongHyeon 	 */
16360dbe28b3SPyun YongHyeon         ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
16370dbe28b3SPyun YongHyeon 
16380dbe28b3SPyun YongHyeon 	/*
16390dbe28b3SPyun YongHyeon 	 * Do miibus setup.
16400dbe28b3SPyun YongHyeon 	 */
16410dbe28b3SPyun YongHyeon 	MSK_IF_UNLOCK(sc_if);
16428e5d93dbSMarius Strobl 	error = mii_attach(dev, &sc_if->msk_miibus, ifp, msk_mediachange,
16438e5d93dbSMarius Strobl 	    msk_mediastatus, BMSR_DEFCAPMASK, PHY_ADDR_MARV, MII_OFFSET_ANY,
16448e5d93dbSMarius Strobl 	    mmd->mii_flags);
16450dbe28b3SPyun YongHyeon 	if (error != 0) {
16468e5d93dbSMarius Strobl 		device_printf(sc_if->msk_if_dev, "attaching PHYs failed\n");
16470dbe28b3SPyun YongHyeon 		ether_ifdetach(ifp);
16480dbe28b3SPyun YongHyeon 		error = ENXIO;
16490dbe28b3SPyun YongHyeon 		goto fail;
16500dbe28b3SPyun YongHyeon 	}
16510dbe28b3SPyun YongHyeon 
16520dbe28b3SPyun YongHyeon fail:
16530dbe28b3SPyun YongHyeon 	if (error != 0) {
16540dbe28b3SPyun YongHyeon 		/* Access should be ok even though lock has been dropped */
16550dbe28b3SPyun YongHyeon 		sc->msk_if[port] = NULL;
16560dbe28b3SPyun YongHyeon 		msk_detach(dev);
16570dbe28b3SPyun YongHyeon 	}
16580dbe28b3SPyun YongHyeon 
16590dbe28b3SPyun YongHyeon 	return (error);
16600dbe28b3SPyun YongHyeon }
16610dbe28b3SPyun YongHyeon 
16620dbe28b3SPyun YongHyeon /*
16630dbe28b3SPyun YongHyeon  * Attach the interface. Allocate softc structures, do ifmedia
16640dbe28b3SPyun YongHyeon  * setup and ethernet/BPF attach.
16650dbe28b3SPyun YongHyeon  */
16660dbe28b3SPyun YongHyeon static int
16670dbe28b3SPyun YongHyeon mskc_attach(device_t dev)
16680dbe28b3SPyun YongHyeon {
16690dbe28b3SPyun YongHyeon 	struct msk_softc *sc;
1670fcb62a8bSPyun YongHyeon 	struct msk_mii_data *mmd;
1671fcb62a8bSPyun YongHyeon 	int error, msic, msir, reg;
16720dbe28b3SPyun YongHyeon 
16730dbe28b3SPyun YongHyeon 	sc = device_get_softc(dev);
16740dbe28b3SPyun YongHyeon 	sc->msk_dev = dev;
16750dbe28b3SPyun YongHyeon 	mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
16760dbe28b3SPyun YongHyeon 	    MTX_DEF);
16770dbe28b3SPyun YongHyeon 
16780dbe28b3SPyun YongHyeon 	/*
16790dbe28b3SPyun YongHyeon 	 * Map control/status registers.
16800dbe28b3SPyun YongHyeon 	 */
16810dbe28b3SPyun YongHyeon 	pci_enable_busmaster(dev);
16820dbe28b3SPyun YongHyeon 
1683298946a9SPyun YongHyeon 	/* Allocate I/O resource */
16840dbe28b3SPyun YongHyeon #ifdef MSK_USEIOSPACE
16850dbe28b3SPyun YongHyeon 	sc->msk_res_spec = msk_res_spec_io;
16860dbe28b3SPyun YongHyeon #else
16870dbe28b3SPyun YongHyeon 	sc->msk_res_spec = msk_res_spec_mem;
16880dbe28b3SPyun YongHyeon #endif
1689a485f97aSPyun YongHyeon 	sc->msk_irq_spec = msk_irq_spec_legacy;
16900dbe28b3SPyun YongHyeon 	error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res);
16910dbe28b3SPyun YongHyeon 	if (error) {
16920dbe28b3SPyun YongHyeon 		if (sc->msk_res_spec == msk_res_spec_mem)
16930dbe28b3SPyun YongHyeon 			sc->msk_res_spec = msk_res_spec_io;
16940dbe28b3SPyun YongHyeon 		else
16950dbe28b3SPyun YongHyeon 			sc->msk_res_spec = msk_res_spec_mem;
16960dbe28b3SPyun YongHyeon 		error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res);
16970dbe28b3SPyun YongHyeon 		if (error) {
16980dbe28b3SPyun YongHyeon 			device_printf(dev, "couldn't allocate %s resources\n",
16990dbe28b3SPyun YongHyeon 			    sc->msk_res_spec == msk_res_spec_mem ? "memory" :
17000dbe28b3SPyun YongHyeon 			    "I/O");
17010dbe28b3SPyun YongHyeon 			mtx_destroy(&sc->msk_mtx);
17020dbe28b3SPyun YongHyeon 			return (ENXIO);
17030dbe28b3SPyun YongHyeon 		}
17040dbe28b3SPyun YongHyeon 	}
17050dbe28b3SPyun YongHyeon 
1706*c6a34f76SPyun YongHyeon 	/* Enable all clocks before accessing any registers. */
1707*c6a34f76SPyun YongHyeon 	CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
1708*c6a34f76SPyun YongHyeon 
17090dbe28b3SPyun YongHyeon 	CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR);
17100dbe28b3SPyun YongHyeon 	sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID);
17110dbe28b3SPyun YongHyeon 	sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f;
17120dbe28b3SPyun YongHyeon 	/* Bail out if chip is not recognized. */
17130dbe28b3SPyun YongHyeon 	if (sc->msk_hw_id < CHIP_ID_YUKON_XL ||
1714e19bd6eeSPyun YongHyeon 	    sc->msk_hw_id > CHIP_ID_YUKON_OPT ||
1715e19bd6eeSPyun YongHyeon 	    sc->msk_hw_id == CHIP_ID_YUKON_SUPR ||
1716e19bd6eeSPyun YongHyeon 	    sc->msk_hw_id == CHIP_ID_YUKON_UNKNOWN) {
17170dbe28b3SPyun YongHyeon 		device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n",
17180dbe28b3SPyun YongHyeon 		    sc->msk_hw_id, sc->msk_hw_rev);
1719ad6d01d1SPyun YongHyeon 		mtx_destroy(&sc->msk_mtx);
1720ad6d01d1SPyun YongHyeon 		return (ENXIO);
17210dbe28b3SPyun YongHyeon 	}
17220dbe28b3SPyun YongHyeon 
17230dbe28b3SPyun YongHyeon 	SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
17240dbe28b3SPyun YongHyeon 	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
17250dbe28b3SPyun YongHyeon 	    OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW,
17260dbe28b3SPyun YongHyeon 	    &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I",
17270dbe28b3SPyun YongHyeon 	    "max number of Rx events to process");
17280dbe28b3SPyun YongHyeon 
17290dbe28b3SPyun YongHyeon 	sc->msk_process_limit = MSK_PROC_DEFAULT;
17300dbe28b3SPyun YongHyeon 	error = resource_int_value(device_get_name(dev), device_get_unit(dev),
17310dbe28b3SPyun YongHyeon 	    "process_limit", &sc->msk_process_limit);
17320dbe28b3SPyun YongHyeon 	if (error == 0) {
17330dbe28b3SPyun YongHyeon 		if (sc->msk_process_limit < MSK_PROC_MIN ||
17340dbe28b3SPyun YongHyeon 		    sc->msk_process_limit > MSK_PROC_MAX) {
17350dbe28b3SPyun YongHyeon 			device_printf(dev, "process_limit value out of range; "
17360dbe28b3SPyun YongHyeon 			    "using default: %d\n", MSK_PROC_DEFAULT);
17370dbe28b3SPyun YongHyeon 			sc->msk_process_limit = MSK_PROC_DEFAULT;
17380dbe28b3SPyun YongHyeon 		}
17390dbe28b3SPyun YongHyeon 	}
17400dbe28b3SPyun YongHyeon 
1741cf570c1fSPyun YongHyeon 	sc->msk_int_holdoff = MSK_INT_HOLDOFF_DEFAULT;
1742cf570c1fSPyun YongHyeon 	SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
1743cf570c1fSPyun YongHyeon 	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
1744cf570c1fSPyun YongHyeon 	    "int_holdoff", CTLFLAG_RW, &sc->msk_int_holdoff, 0,
1745cf570c1fSPyun YongHyeon 	    "Maximum number of time to delay interrupts");
1746cf570c1fSPyun YongHyeon 	resource_int_value(device_get_name(dev), device_get_unit(dev),
1747cf570c1fSPyun YongHyeon 	    "int_holdoff", &sc->msk_int_holdoff);
1748cf570c1fSPyun YongHyeon 
17490dbe28b3SPyun YongHyeon 	sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP);
17500dbe28b3SPyun YongHyeon 	/* Check number of MACs. */
17510dbe28b3SPyun YongHyeon 	sc->msk_num_port = 1;
17520dbe28b3SPyun YongHyeon 	if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) ==
17530dbe28b3SPyun YongHyeon 	    CFG_DUAL_MAC_MSK) {
17540dbe28b3SPyun YongHyeon 		if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
17550dbe28b3SPyun YongHyeon 			sc->msk_num_port++;
17560dbe28b3SPyun YongHyeon 	}
17570dbe28b3SPyun YongHyeon 
17580dbe28b3SPyun YongHyeon 	/* Check bus type. */
17593b0a4aefSJohn Baldwin 	if (pci_find_cap(sc->msk_dev, PCIY_EXPRESS, &reg) == 0) {
17600dbe28b3SPyun YongHyeon 		sc->msk_bustype = MSK_PEX_BUS;
17617420e9dcSPyun YongHyeon 		sc->msk_expcap = reg;
17623b0a4aefSJohn Baldwin 	} else if (pci_find_cap(sc->msk_dev, PCIY_PCIX, &reg) == 0) {
17630dbe28b3SPyun YongHyeon 		sc->msk_bustype = MSK_PCIX_BUS;
17647420e9dcSPyun YongHyeon 		sc->msk_pcixcap = reg;
17657420e9dcSPyun YongHyeon 	} else
17660dbe28b3SPyun YongHyeon 		sc->msk_bustype = MSK_PCI_BUS;
17670dbe28b3SPyun YongHyeon 
17680dbe28b3SPyun YongHyeon 	switch (sc->msk_hw_id) {
17690dbe28b3SPyun YongHyeon 	case CHIP_ID_YUKON_EC:
1770a91981e4SPyun YongHyeon 		sc->msk_clock = 125;	/* 125 MHz */
1771e2b16603SPyun YongHyeon 		sc->msk_pflags |= MSK_FLAG_JUMBO;
1772e2b16603SPyun YongHyeon 		break;
17730dbe28b3SPyun YongHyeon 	case CHIP_ID_YUKON_EC_U:
1774a91981e4SPyun YongHyeon 		sc->msk_clock = 125;	/* 125 MHz */
1775e2b16603SPyun YongHyeon 		sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_JUMBO_NOCSUM;
17760dbe28b3SPyun YongHyeon 		break;
1777daf29227SPyun YongHyeon 	case CHIP_ID_YUKON_EX:
1778a91981e4SPyun YongHyeon 		sc->msk_clock = 125;	/* 125 MHz */
1779ebb25bfaSPyun YongHyeon 		sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2 |
1780ebb25bfaSPyun YongHyeon 		    MSK_FLAG_AUTOTX_CSUM;
1781ebb25bfaSPyun YongHyeon 		/*
1782ebb25bfaSPyun YongHyeon 		 * Yukon Extreme seems to have silicon bug for
1783ebb25bfaSPyun YongHyeon 		 * automatic Tx checksum calculation capability.
1784ebb25bfaSPyun YongHyeon 		 */
1785ebb25bfaSPyun YongHyeon 		if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0)
1786ebb25bfaSPyun YongHyeon 			sc->msk_pflags &= ~MSK_FLAG_AUTOTX_CSUM;
1787ebb25bfaSPyun YongHyeon 		/*
1788ebb25bfaSPyun YongHyeon 		 * Yukon Extreme A0 could not use store-and-forward
1789ebb25bfaSPyun YongHyeon 		 * for jumbo frames, so disable Tx checksum
1790ebb25bfaSPyun YongHyeon 		 * offloading for jumbo frames.
1791ebb25bfaSPyun YongHyeon 		 */
1792ebb25bfaSPyun YongHyeon 		if (sc->msk_hw_rev == CHIP_REV_YU_EX_A0)
1793ebb25bfaSPyun YongHyeon 			sc->msk_pflags |= MSK_FLAG_JUMBO_NOCSUM;
1794daf29227SPyun YongHyeon 		break;
17950dbe28b3SPyun YongHyeon 	case CHIP_ID_YUKON_FE:
1796a91981e4SPyun YongHyeon 		sc->msk_clock = 100;	/* 100 MHz */
1797e2b16603SPyun YongHyeon 		sc->msk_pflags |= MSK_FLAG_FASTETHER;
17980dbe28b3SPyun YongHyeon 		break;
179961708f4cSPyun YongHyeon 	case CHIP_ID_YUKON_FE_P:
1800a91981e4SPyun YongHyeon 		sc->msk_clock = 50;	/* 50 MHz */
1801ebb25bfaSPyun YongHyeon 		sc->msk_pflags |= MSK_FLAG_FASTETHER | MSK_FLAG_DESCV2 |
1802ebb25bfaSPyun YongHyeon 		    MSK_FLAG_AUTOTX_CSUM;
1803224003b7SPyun YongHyeon 		if (sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
1804224003b7SPyun YongHyeon 			/*
1805224003b7SPyun YongHyeon 			 * XXX
1806224003b7SPyun YongHyeon 			 * FE+ A0 has status LE writeback bug so msk(4)
1807224003b7SPyun YongHyeon 			 * does not rely on status word of received frame
1808224003b7SPyun YongHyeon 			 * in msk_rxeof() which in turn disables all
1809224003b7SPyun YongHyeon 			 * hardware assistance bits reported by the status
1810b1ce21c6SRebecca Cran 			 * word as well as validity of the received frame.
1811224003b7SPyun YongHyeon 			 * Just pass received frames to upper stack with
1812224003b7SPyun YongHyeon 			 * minimal test and let upper stack handle them.
1813224003b7SPyun YongHyeon 			 */
1814efb74172SPyun YongHyeon 			sc->msk_pflags |= MSK_FLAG_NOHWVLAN |
1815efb74172SPyun YongHyeon 			    MSK_FLAG_NORXCHK | MSK_FLAG_NORX_CSUM;
1816224003b7SPyun YongHyeon 		}
181761708f4cSPyun YongHyeon 		break;
18180dbe28b3SPyun YongHyeon 	case CHIP_ID_YUKON_XL:
1819a91981e4SPyun YongHyeon 		sc->msk_clock = 156;	/* 156 MHz */
1820e2b16603SPyun YongHyeon 		sc->msk_pflags |= MSK_FLAG_JUMBO;
18210dbe28b3SPyun YongHyeon 		break;
182276202a16SPyun YongHyeon 	case CHIP_ID_YUKON_UL_2:
182384e3651eSPyun YongHyeon 		sc->msk_clock = 125;	/* 125 MHz */
182476202a16SPyun YongHyeon 		sc->msk_pflags |= MSK_FLAG_JUMBO;
182576202a16SPyun YongHyeon 		break;
1826e19bd6eeSPyun YongHyeon 	case CHIP_ID_YUKON_OPT:
1827e19bd6eeSPyun YongHyeon 		sc->msk_clock = 125;	/* 125 MHz */
1828e19bd6eeSPyun YongHyeon 		sc->msk_pflags |= MSK_FLAG_JUMBO | MSK_FLAG_DESCV2;
1829e19bd6eeSPyun YongHyeon 		break;
18300dbe28b3SPyun YongHyeon 	default:
1831a91981e4SPyun YongHyeon 		sc->msk_clock = 156;	/* 156 MHz */
1832cfd540e7SPyun YongHyeon 		break;
18330dbe28b3SPyun YongHyeon 	}
18340dbe28b3SPyun YongHyeon 
1835298946a9SPyun YongHyeon 	/* Allocate IRQ resources. */
1836298946a9SPyun YongHyeon 	msic = pci_msi_count(dev);
1837298946a9SPyun YongHyeon 	if (bootverbose)
1838298946a9SPyun YongHyeon 		device_printf(dev, "MSI count : %d\n", msic);
183953dcfbd1SPyun YongHyeon 	if (legacy_intr != 0)
184053dcfbd1SPyun YongHyeon 		msi_disable = 1;
1841c72f075aSPyun YongHyeon 	if (msi_disable == 0 && msic > 0) {
1842c72f075aSPyun YongHyeon 		msir = 1;
1843c72f075aSPyun YongHyeon 		if (pci_alloc_msi(dev, &msir) == 0) {
1844c72f075aSPyun YongHyeon 			if (msir == 1) {
18457a76e8a4SPyun YongHyeon 				sc->msk_pflags |= MSK_FLAG_MSI;
1846c72f075aSPyun YongHyeon 				sc->msk_irq_spec = msk_irq_spec_msi;
18476ec27c17SPyun YongHyeon 			} else
1848298946a9SPyun YongHyeon 				pci_release_msi(dev);
1849298946a9SPyun YongHyeon 		}
18508463d7a0SPyun YongHyeon 	}
1851298946a9SPyun YongHyeon 
1852298946a9SPyun YongHyeon 	error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq);
1853298946a9SPyun YongHyeon 	if (error) {
1854298946a9SPyun YongHyeon 		device_printf(dev, "couldn't allocate IRQ resources\n");
1855298946a9SPyun YongHyeon 		goto fail;
1856298946a9SPyun YongHyeon 	}
1857298946a9SPyun YongHyeon 
18580dbe28b3SPyun YongHyeon 	if ((error = msk_status_dma_alloc(sc)) != 0)
18590dbe28b3SPyun YongHyeon 		goto fail;
18600dbe28b3SPyun YongHyeon 
18610dbe28b3SPyun YongHyeon 	/* Set base interrupt mask. */
18620dbe28b3SPyun YongHyeon 	sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU;
18630dbe28b3SPyun YongHyeon 	sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR |
18640dbe28b3SPyun YongHyeon 	    Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP;
18650dbe28b3SPyun YongHyeon 
18660dbe28b3SPyun YongHyeon 	/* Reset the adapter. */
18670dbe28b3SPyun YongHyeon 	mskc_reset(sc);
18680dbe28b3SPyun YongHyeon 
18690dbe28b3SPyun YongHyeon 	if ((error = mskc_setup_rambuffer(sc)) != 0)
18700dbe28b3SPyun YongHyeon 		goto fail;
18710dbe28b3SPyun YongHyeon 
18720dbe28b3SPyun YongHyeon 	sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1);
18730dbe28b3SPyun YongHyeon 	if (sc->msk_devs[MSK_PORT_A] == NULL) {
18740dbe28b3SPyun YongHyeon 		device_printf(dev, "failed to add child for PORT_A\n");
18750dbe28b3SPyun YongHyeon 		error = ENXIO;
18760dbe28b3SPyun YongHyeon 		goto fail;
18770dbe28b3SPyun YongHyeon 	}
1878fcb62a8bSPyun YongHyeon 	mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO);
1879fcb62a8bSPyun YongHyeon 	if (mmd == NULL) {
18800dbe28b3SPyun YongHyeon 		device_printf(dev, "failed to allocate memory for "
18810dbe28b3SPyun YongHyeon 		    "ivars of PORT_A\n");
18820dbe28b3SPyun YongHyeon 		error = ENXIO;
18830dbe28b3SPyun YongHyeon 		goto fail;
18840dbe28b3SPyun YongHyeon 	}
1885fcb62a8bSPyun YongHyeon 	mmd->port = MSK_PORT_A;
1886fcb62a8bSPyun YongHyeon 	mmd->pmd = sc->msk_pmd;
1887efd4fc3fSMarius Strobl 	mmd->mii_flags |= MIIF_DOPAUSE;
18888e5d93dbSMarius Strobl 	if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
1889fcb62a8bSPyun YongHyeon 		mmd->mii_flags |= MIIF_HAVEFIBER;
18908e5d93dbSMarius Strobl 	if (sc->msk_pmd == 'P')
18918e5d93dbSMarius Strobl 		mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0;
1892fcb62a8bSPyun YongHyeon 	device_set_ivars(sc->msk_devs[MSK_PORT_A], mmd);
18930dbe28b3SPyun YongHyeon 
18940dbe28b3SPyun YongHyeon 	if (sc->msk_num_port > 1) {
18950dbe28b3SPyun YongHyeon 		sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1);
18960dbe28b3SPyun YongHyeon 		if (sc->msk_devs[MSK_PORT_B] == NULL) {
18970dbe28b3SPyun YongHyeon 			device_printf(dev, "failed to add child for PORT_B\n");
18980dbe28b3SPyun YongHyeon 			error = ENXIO;
18990dbe28b3SPyun YongHyeon 			goto fail;
19000dbe28b3SPyun YongHyeon 		}
1901fcb62a8bSPyun YongHyeon 		mmd = malloc(sizeof(struct msk_mii_data), M_DEVBUF, M_WAITOK | M_ZERO);
1902fcb62a8bSPyun YongHyeon 		if (mmd == NULL) {
19030dbe28b3SPyun YongHyeon 			device_printf(dev, "failed to allocate memory for "
19040dbe28b3SPyun YongHyeon 			    "ivars of PORT_B\n");
19050dbe28b3SPyun YongHyeon 			error = ENXIO;
19060dbe28b3SPyun YongHyeon 			goto fail;
19070dbe28b3SPyun YongHyeon 		}
1908fcb62a8bSPyun YongHyeon 		mmd->port = MSK_PORT_B;
1909fcb62a8bSPyun YongHyeon 		mmd->pmd = sc->msk_pmd;
19108e5d93dbSMarius Strobl 	 	if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S')
1911fcb62a8bSPyun YongHyeon 			mmd->mii_flags |= MIIF_HAVEFIBER;
19128e5d93dbSMarius Strobl 	 	if (sc->msk_pmd == 'P')
19138e5d93dbSMarius Strobl 			mmd->mii_flags |= MIIF_HAVEFIBER | MIIF_MACPRIV0;
1914fcb62a8bSPyun YongHyeon 		device_set_ivars(sc->msk_devs[MSK_PORT_B], mmd);
19150dbe28b3SPyun YongHyeon 	}
19160dbe28b3SPyun YongHyeon 
19170dbe28b3SPyun YongHyeon 	error = bus_generic_attach(dev);
19180dbe28b3SPyun YongHyeon 	if (error) {
19190dbe28b3SPyun YongHyeon 		device_printf(dev, "failed to attach port(s)\n");
19200dbe28b3SPyun YongHyeon 		goto fail;
19210dbe28b3SPyun YongHyeon 	}
19220dbe28b3SPyun YongHyeon 
192353dcfbd1SPyun YongHyeon 	/* Hook interrupt last to avoid having to lock softc. */
192453dcfbd1SPyun YongHyeon 	error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET |
1925c876b43fSPyun YongHyeon 	    INTR_MPSAFE, NULL, msk_intr, sc, &sc->msk_intrhand);
19260dbe28b3SPyun YongHyeon 	if (error != 0) {
19270dbe28b3SPyun YongHyeon 		device_printf(dev, "couldn't set up interrupt handler\n");
19280dbe28b3SPyun YongHyeon 		goto fail;
19290dbe28b3SPyun YongHyeon 	}
19300dbe28b3SPyun YongHyeon fail:
19310dbe28b3SPyun YongHyeon 	if (error != 0)
19320dbe28b3SPyun YongHyeon 		mskc_detach(dev);
19330dbe28b3SPyun YongHyeon 
19340dbe28b3SPyun YongHyeon 	return (error);
19350dbe28b3SPyun YongHyeon }
19360dbe28b3SPyun YongHyeon 
19370dbe28b3SPyun YongHyeon /*
19380dbe28b3SPyun YongHyeon  * Shutdown hardware and free up resources. This can be called any
19390dbe28b3SPyun YongHyeon  * time after the mutex has been initialized. It is called in both
19400dbe28b3SPyun YongHyeon  * the error case in attach and the normal detach case so it needs
19410dbe28b3SPyun YongHyeon  * to be careful about only freeing resources that have actually been
19420dbe28b3SPyun YongHyeon  * allocated.
19430dbe28b3SPyun YongHyeon  */
19440dbe28b3SPyun YongHyeon static int
19450dbe28b3SPyun YongHyeon msk_detach(device_t dev)
19460dbe28b3SPyun YongHyeon {
19470dbe28b3SPyun YongHyeon 	struct msk_softc *sc;
19480dbe28b3SPyun YongHyeon 	struct msk_if_softc *sc_if;
19490dbe28b3SPyun YongHyeon 	struct ifnet *ifp;
19500dbe28b3SPyun YongHyeon 
19510dbe28b3SPyun YongHyeon 	sc_if = device_get_softc(dev);
19520dbe28b3SPyun YongHyeon 	KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx),
19530dbe28b3SPyun YongHyeon 	    ("msk mutex not initialized in msk_detach"));
19540dbe28b3SPyun YongHyeon 	MSK_IF_LOCK(sc_if);
19550dbe28b3SPyun YongHyeon 
19560dbe28b3SPyun YongHyeon 	ifp = sc_if->msk_ifp;
19570dbe28b3SPyun YongHyeon 	if (device_is_attached(dev)) {
19580dbe28b3SPyun YongHyeon 		/* XXX */
19597a76e8a4SPyun YongHyeon 		sc_if->msk_flags |= MSK_FLAG_DETACH;
19600dbe28b3SPyun YongHyeon 		msk_stop(sc_if);
19610dbe28b3SPyun YongHyeon 		/* Can't hold locks while calling detach. */
19620dbe28b3SPyun YongHyeon 		MSK_IF_UNLOCK(sc_if);
19630dbe28b3SPyun YongHyeon 		callout_drain(&sc_if->msk_tick_ch);
19644c5a247bSGleb Smirnoff 		if (ifp)
19650dbe28b3SPyun YongHyeon 			ether_ifdetach(ifp);
19660dbe28b3SPyun YongHyeon 		MSK_IF_LOCK(sc_if);
19670dbe28b3SPyun YongHyeon 	}
19680dbe28b3SPyun YongHyeon 
19690dbe28b3SPyun YongHyeon 	/*
19700dbe28b3SPyun YongHyeon 	 * We're generally called from mskc_detach() which is using
19710dbe28b3SPyun YongHyeon 	 * device_delete_child() to get to here. It's already trashed
19720dbe28b3SPyun YongHyeon 	 * miibus for us, so don't do it here or we'll panic.
19730dbe28b3SPyun YongHyeon 	 *
19740dbe28b3SPyun YongHyeon 	 * if (sc_if->msk_miibus != NULL) {
19750dbe28b3SPyun YongHyeon 	 * 	device_delete_child(dev, sc_if->msk_miibus);
19760dbe28b3SPyun YongHyeon 	 * 	sc_if->msk_miibus = NULL;
19770dbe28b3SPyun YongHyeon 	 * }
19780dbe28b3SPyun YongHyeon 	 */
19790dbe28b3SPyun YongHyeon 
198085b340cbSPyun YongHyeon 	msk_rx_dma_jfree(sc_if);
19810dbe28b3SPyun YongHyeon 	msk_txrx_dma_free(sc_if);
19820dbe28b3SPyun YongHyeon 	bus_generic_detach(dev);
19830dbe28b3SPyun YongHyeon 
19840dbe28b3SPyun YongHyeon 	if (ifp)
19850dbe28b3SPyun YongHyeon 		if_free(ifp);
19860dbe28b3SPyun YongHyeon 	sc = sc_if->msk_softc;
19870dbe28b3SPyun YongHyeon 	sc->msk_if[sc_if->msk_port] = NULL;
19880dbe28b3SPyun YongHyeon 	MSK_IF_UNLOCK(sc_if);
19890dbe28b3SPyun YongHyeon 
19900dbe28b3SPyun YongHyeon 	return (0);
19910dbe28b3SPyun YongHyeon }
19920dbe28b3SPyun YongHyeon 
19930dbe28b3SPyun YongHyeon static int
19940dbe28b3SPyun YongHyeon mskc_detach(device_t dev)
19950dbe28b3SPyun YongHyeon {
19960dbe28b3SPyun YongHyeon 	struct msk_softc *sc;
19970dbe28b3SPyun YongHyeon 
19980dbe28b3SPyun YongHyeon 	sc = device_get_softc(dev);
19990dbe28b3SPyun YongHyeon 	KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized"));
20000dbe28b3SPyun YongHyeon 
20010dbe28b3SPyun YongHyeon 	if (device_is_alive(dev)) {
20020dbe28b3SPyun YongHyeon 		if (sc->msk_devs[MSK_PORT_A] != NULL) {
20030dbe28b3SPyun YongHyeon 			free(device_get_ivars(sc->msk_devs[MSK_PORT_A]),
20040dbe28b3SPyun YongHyeon 			    M_DEVBUF);
20050dbe28b3SPyun YongHyeon 			device_delete_child(dev, sc->msk_devs[MSK_PORT_A]);
20060dbe28b3SPyun YongHyeon 		}
20070dbe28b3SPyun YongHyeon 		if (sc->msk_devs[MSK_PORT_B] != NULL) {
20080dbe28b3SPyun YongHyeon 			free(device_get_ivars(sc->msk_devs[MSK_PORT_B]),
20090dbe28b3SPyun YongHyeon 			    M_DEVBUF);
20100dbe28b3SPyun YongHyeon 			device_delete_child(dev, sc->msk_devs[MSK_PORT_B]);
20110dbe28b3SPyun YongHyeon 		}
20120dbe28b3SPyun YongHyeon 		bus_generic_detach(dev);
20130dbe28b3SPyun YongHyeon 	}
20140dbe28b3SPyun YongHyeon 
20150dbe28b3SPyun YongHyeon 	/* Disable all interrupts. */
20160dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, B0_IMSK, 0);
20170dbe28b3SPyun YongHyeon 	CSR_READ_4(sc, B0_IMSK);
20180dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
20190dbe28b3SPyun YongHyeon 	CSR_READ_4(sc, B0_HWE_IMSK);
20200dbe28b3SPyun YongHyeon 
20210dbe28b3SPyun YongHyeon 	/* LED Off. */
20220dbe28b3SPyun YongHyeon 	CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF);
20230dbe28b3SPyun YongHyeon 
20240dbe28b3SPyun YongHyeon 	/* Put hardware reset. */
20250dbe28b3SPyun YongHyeon 	CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
20260dbe28b3SPyun YongHyeon 
20270dbe28b3SPyun YongHyeon 	msk_status_dma_free(sc);
20280dbe28b3SPyun YongHyeon 
2029c72f075aSPyun YongHyeon 	if (sc->msk_intrhand) {
2030c72f075aSPyun YongHyeon 		bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand);
2031c72f075aSPyun YongHyeon 		sc->msk_intrhand = NULL;
2032298946a9SPyun YongHyeon 	}
2033298946a9SPyun YongHyeon 	bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq);
20347a76e8a4SPyun YongHyeon 	if ((sc->msk_pflags & MSK_FLAG_MSI) != 0)
20350dbe28b3SPyun YongHyeon 		pci_release_msi(dev);
20360dbe28b3SPyun YongHyeon 	bus_release_resources(dev, sc->msk_res_spec, sc->msk_res);
20370dbe28b3SPyun YongHyeon 	mtx_destroy(&sc->msk_mtx);
20380dbe28b3SPyun YongHyeon 
20390dbe28b3SPyun YongHyeon 	return (0);
20400dbe28b3SPyun YongHyeon }
20410dbe28b3SPyun YongHyeon 
20420dbe28b3SPyun YongHyeon struct msk_dmamap_arg {
20430dbe28b3SPyun YongHyeon 	bus_addr_t	msk_busaddr;
20440dbe28b3SPyun YongHyeon };
20450dbe28b3SPyun YongHyeon 
20460dbe28b3SPyun YongHyeon static void
20470dbe28b3SPyun YongHyeon msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
20480dbe28b3SPyun YongHyeon {
20490dbe28b3SPyun YongHyeon 	struct msk_dmamap_arg *ctx;
20500dbe28b3SPyun YongHyeon 
20510dbe28b3SPyun YongHyeon 	if (error != 0)
20520dbe28b3SPyun YongHyeon 		return;
20530dbe28b3SPyun YongHyeon 	ctx = arg;
20540dbe28b3SPyun YongHyeon 	ctx->msk_busaddr = segs[0].ds_addr;
20550dbe28b3SPyun YongHyeon }
20560dbe28b3SPyun YongHyeon 
20570dbe28b3SPyun YongHyeon /* Create status DMA region. */
20580dbe28b3SPyun YongHyeon static int
20590dbe28b3SPyun YongHyeon msk_status_dma_alloc(struct msk_softc *sc)
20600dbe28b3SPyun YongHyeon {
20610dbe28b3SPyun YongHyeon 	struct msk_dmamap_arg ctx;
20620dbe28b3SPyun YongHyeon 	int error;
20630dbe28b3SPyun YongHyeon 
20640dbe28b3SPyun YongHyeon 	error = bus_dma_tag_create(
20650dbe28b3SPyun YongHyeon 		    bus_get_dma_tag(sc->msk_dev),	/* parent */
20660dbe28b3SPyun YongHyeon 		    MSK_STAT_ALIGN, 0,		/* alignment, boundary */
20670dbe28b3SPyun YongHyeon 		    BUS_SPACE_MAXADDR,		/* lowaddr */
20680dbe28b3SPyun YongHyeon 		    BUS_SPACE_MAXADDR,		/* highaddr */
20690dbe28b3SPyun YongHyeon 		    NULL, NULL,			/* filter, filterarg */
20700dbe28b3SPyun YongHyeon 		    MSK_STAT_RING_SZ,		/* maxsize */
20710dbe28b3SPyun YongHyeon 		    1,				/* nsegments */
20720dbe28b3SPyun YongHyeon 		    MSK_STAT_RING_SZ,		/* maxsegsize */
20730dbe28b3SPyun YongHyeon 		    0,				/* flags */
20740dbe28b3SPyun YongHyeon 		    NULL, NULL,			/* lockfunc, lockarg */
20750dbe28b3SPyun YongHyeon 		    &sc->msk_stat_tag);
20760dbe28b3SPyun YongHyeon 	if (error != 0) {
20770dbe28b3SPyun YongHyeon 		device_printf(sc->msk_dev,
20780dbe28b3SPyun YongHyeon 		    "failed to create status DMA tag\n");
20790dbe28b3SPyun YongHyeon 		return (error);
20800dbe28b3SPyun YongHyeon 	}
20810dbe28b3SPyun YongHyeon 
20820dbe28b3SPyun YongHyeon 	/* Allocate DMA'able memory and load the DMA map for status ring. */
20830dbe28b3SPyun YongHyeon 	error = bus_dmamem_alloc(sc->msk_stat_tag,
20840dbe28b3SPyun YongHyeon 	    (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT |
20850dbe28b3SPyun YongHyeon 	    BUS_DMA_ZERO, &sc->msk_stat_map);
20860dbe28b3SPyun YongHyeon 	if (error != 0) {
20870dbe28b3SPyun YongHyeon 		device_printf(sc->msk_dev,
20880dbe28b3SPyun YongHyeon 		    "failed to allocate DMA'able memory for status ring\n");
20890dbe28b3SPyun YongHyeon 		return (error);
20900dbe28b3SPyun YongHyeon 	}
20910dbe28b3SPyun YongHyeon 
20920dbe28b3SPyun YongHyeon 	ctx.msk_busaddr = 0;
20930dbe28b3SPyun YongHyeon 	error = bus_dmamap_load(sc->msk_stat_tag,
20940dbe28b3SPyun YongHyeon 	    sc->msk_stat_map, sc->msk_stat_ring, MSK_STAT_RING_SZ,
20950dbe28b3SPyun YongHyeon 	    msk_dmamap_cb, &ctx, 0);
20960dbe28b3SPyun YongHyeon 	if (error != 0) {
20970dbe28b3SPyun YongHyeon 		device_printf(sc->msk_dev,
20980dbe28b3SPyun YongHyeon 		    "failed to load DMA'able memory for status ring\n");
20990dbe28b3SPyun YongHyeon 		return (error);
21000dbe28b3SPyun YongHyeon 	}
21010dbe28b3SPyun YongHyeon 	sc->msk_stat_ring_paddr = ctx.msk_busaddr;
21020dbe28b3SPyun YongHyeon 
21030dbe28b3SPyun YongHyeon 	return (0);
21040dbe28b3SPyun YongHyeon }
21050dbe28b3SPyun YongHyeon 
21060dbe28b3SPyun YongHyeon static void
21070dbe28b3SPyun YongHyeon msk_status_dma_free(struct msk_softc *sc)
21080dbe28b3SPyun YongHyeon {
21090dbe28b3SPyun YongHyeon 
21100dbe28b3SPyun YongHyeon 	/* Destroy status block. */
21110dbe28b3SPyun YongHyeon 	if (sc->msk_stat_tag) {
21120dbe28b3SPyun YongHyeon 		if (sc->msk_stat_map) {
21130dbe28b3SPyun YongHyeon 			bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map);
21140dbe28b3SPyun YongHyeon 			if (sc->msk_stat_ring) {
21150dbe28b3SPyun YongHyeon 				bus_dmamem_free(sc->msk_stat_tag,
21160dbe28b3SPyun YongHyeon 				    sc->msk_stat_ring, sc->msk_stat_map);
21170dbe28b3SPyun YongHyeon 				sc->msk_stat_ring = NULL;
21180dbe28b3SPyun YongHyeon 			}
21190dbe28b3SPyun YongHyeon 			sc->msk_stat_map = NULL;
21200dbe28b3SPyun YongHyeon 		}
21210dbe28b3SPyun YongHyeon 		bus_dma_tag_destroy(sc->msk_stat_tag);
21220dbe28b3SPyun YongHyeon 		sc->msk_stat_tag = NULL;
21230dbe28b3SPyun YongHyeon 	}
21240dbe28b3SPyun YongHyeon }
21250dbe28b3SPyun YongHyeon 
21260dbe28b3SPyun YongHyeon static int
21270dbe28b3SPyun YongHyeon msk_txrx_dma_alloc(struct msk_if_softc *sc_if)
21280dbe28b3SPyun YongHyeon {
21290dbe28b3SPyun YongHyeon 	struct msk_dmamap_arg ctx;
21300dbe28b3SPyun YongHyeon 	struct msk_txdesc *txd;
21310dbe28b3SPyun YongHyeon 	struct msk_rxdesc *rxd;
213283c04c93SPyun YongHyeon 	bus_size_t rxalign;
21330dbe28b3SPyun YongHyeon 	int error, i;
21340dbe28b3SPyun YongHyeon 
21350dbe28b3SPyun YongHyeon 	/* Create parent DMA tag. */
21360dbe28b3SPyun YongHyeon 	/*
21370dbe28b3SPyun YongHyeon 	 * XXX
21380dbe28b3SPyun YongHyeon 	 * It seems that Yukon II supports full 64bits DMA operations. But
21390dbe28b3SPyun YongHyeon 	 * it needs two descriptors(list elements) for 64bits DMA operations.
21400dbe28b3SPyun YongHyeon 	 * Since we don't know what DMA address mappings(32bits or 64bits)
21410dbe28b3SPyun YongHyeon 	 * would be used in advance for each mbufs, we limits its DMA space
21420dbe28b3SPyun YongHyeon 	 * to be in range of 32bits address space. Otherwise, we should check
21430dbe28b3SPyun YongHyeon 	 * what DMA address is used and chain another descriptor for the
21440dbe28b3SPyun YongHyeon 	 * 64bits DMA operation. This also means descriptor ring size is
21450dbe28b3SPyun YongHyeon 	 * variable. Limiting DMA address to be in 32bit address space greatly
2146b1ce21c6SRebecca Cran 	 * simplifies descriptor handling and possibly would increase
21470dbe28b3SPyun YongHyeon 	 * performance a bit due to efficient handling of descriptors.
21480dbe28b3SPyun YongHyeon 	 * Apart from harassing checksum offloading mechanisms, it seems
2149b1ce21c6SRebecca Cran 	 * it's really bad idea to use a separate descriptor for 64bit
21500dbe28b3SPyun YongHyeon 	 * DMA operation to save small descriptor memory. Anyway, I've
21510dbe28b3SPyun YongHyeon 	 * never seen these exotic scheme on ethernet interface hardware.
21520dbe28b3SPyun YongHyeon 	 */
21530dbe28b3SPyun YongHyeon 	error = bus_dma_tag_create(
21540dbe28b3SPyun YongHyeon 		    bus_get_dma_tag(sc_if->msk_if_dev),	/* parent */
21550dbe28b3SPyun YongHyeon 		    1, 0,			/* alignment, boundary */
21560dbe28b3SPyun YongHyeon 		    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
21570dbe28b3SPyun YongHyeon 		    BUS_SPACE_MAXADDR,		/* highaddr */
21580dbe28b3SPyun YongHyeon 		    NULL, NULL,			/* filter, filterarg */
21590dbe28b3SPyun YongHyeon 		    BUS_SPACE_MAXSIZE_32BIT,	/* maxsize */
21600dbe28b3SPyun YongHyeon 		    0,				/* nsegments */
21610dbe28b3SPyun YongHyeon 		    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
21620dbe28b3SPyun YongHyeon 		    0,				/* flags */
21630dbe28b3SPyun YongHyeon 		    NULL, NULL,			/* lockfunc, lockarg */
21640dbe28b3SPyun YongHyeon 		    &sc_if->msk_cdata.msk_parent_tag);
21650dbe28b3SPyun YongHyeon 	if (error != 0) {
21660dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev,
21670dbe28b3SPyun YongHyeon 		    "failed to create parent DMA tag\n");
21680dbe28b3SPyun YongHyeon 		goto fail;
21690dbe28b3SPyun YongHyeon 	}
21700dbe28b3SPyun YongHyeon 	/* Create tag for Tx ring. */
21710dbe28b3SPyun YongHyeon 	error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
21720dbe28b3SPyun YongHyeon 		    MSK_RING_ALIGN, 0,		/* alignment, boundary */
21730dbe28b3SPyun YongHyeon 		    BUS_SPACE_MAXADDR,		/* lowaddr */
21740dbe28b3SPyun YongHyeon 		    BUS_SPACE_MAXADDR,		/* highaddr */
21750dbe28b3SPyun YongHyeon 		    NULL, NULL,			/* filter, filterarg */
21760dbe28b3SPyun YongHyeon 		    MSK_TX_RING_SZ,		/* maxsize */
21770dbe28b3SPyun YongHyeon 		    1,				/* nsegments */
21780dbe28b3SPyun YongHyeon 		    MSK_TX_RING_SZ,		/* maxsegsize */
21790dbe28b3SPyun YongHyeon 		    0,				/* flags */
21800dbe28b3SPyun YongHyeon 		    NULL, NULL,			/* lockfunc, lockarg */
21810dbe28b3SPyun YongHyeon 		    &sc_if->msk_cdata.msk_tx_ring_tag);
21820dbe28b3SPyun YongHyeon 	if (error != 0) {
21830dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev,
21840dbe28b3SPyun YongHyeon 		    "failed to create Tx ring DMA tag\n");
21850dbe28b3SPyun YongHyeon 		goto fail;
21860dbe28b3SPyun YongHyeon 	}
21870dbe28b3SPyun YongHyeon 
21880dbe28b3SPyun YongHyeon 	/* Create tag for Rx ring. */
21890dbe28b3SPyun YongHyeon 	error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
21900dbe28b3SPyun YongHyeon 		    MSK_RING_ALIGN, 0,		/* alignment, boundary */
21910dbe28b3SPyun YongHyeon 		    BUS_SPACE_MAXADDR,		/* lowaddr */
21920dbe28b3SPyun YongHyeon 		    BUS_SPACE_MAXADDR,		/* highaddr */
21930dbe28b3SPyun YongHyeon 		    NULL, NULL,			/* filter, filterarg */
21940dbe28b3SPyun YongHyeon 		    MSK_RX_RING_SZ,		/* maxsize */
21950dbe28b3SPyun YongHyeon 		    1,				/* nsegments */
21960dbe28b3SPyun YongHyeon 		    MSK_RX_RING_SZ,		/* maxsegsize */
21970dbe28b3SPyun YongHyeon 		    0,				/* flags */
21980dbe28b3SPyun YongHyeon 		    NULL, NULL,			/* lockfunc, lockarg */
21990dbe28b3SPyun YongHyeon 		    &sc_if->msk_cdata.msk_rx_ring_tag);
22000dbe28b3SPyun YongHyeon 	if (error != 0) {
22010dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev,
22020dbe28b3SPyun YongHyeon 		    "failed to create Rx ring DMA tag\n");
22030dbe28b3SPyun YongHyeon 		goto fail;
22040dbe28b3SPyun YongHyeon 	}
22050dbe28b3SPyun YongHyeon 
22060dbe28b3SPyun YongHyeon 	/* Create tag for Tx buffers. */
22070dbe28b3SPyun YongHyeon 	error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
22080dbe28b3SPyun YongHyeon 		    1, 0,			/* alignment, boundary */
22090dbe28b3SPyun YongHyeon 		    BUS_SPACE_MAXADDR,		/* lowaddr */
22100dbe28b3SPyun YongHyeon 		    BUS_SPACE_MAXADDR,		/* highaddr */
22110dbe28b3SPyun YongHyeon 		    NULL, NULL,			/* filter, filterarg */
22128b51df84SPyun YongHyeon 		    MSK_TSO_MAXSIZE,		/* maxsize */
22130dbe28b3SPyun YongHyeon 		    MSK_MAXTXSEGS,		/* nsegments */
22148b51df84SPyun YongHyeon 		    MSK_TSO_MAXSGSIZE,		/* maxsegsize */
22150dbe28b3SPyun YongHyeon 		    0,				/* flags */
22160dbe28b3SPyun YongHyeon 		    NULL, NULL,			/* lockfunc, lockarg */
22170dbe28b3SPyun YongHyeon 		    &sc_if->msk_cdata.msk_tx_tag);
22180dbe28b3SPyun YongHyeon 	if (error != 0) {
22190dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev,
22200dbe28b3SPyun YongHyeon 		    "failed to create Tx DMA tag\n");
22210dbe28b3SPyun YongHyeon 		goto fail;
22220dbe28b3SPyun YongHyeon 	}
22230dbe28b3SPyun YongHyeon 
222483c04c93SPyun YongHyeon 	rxalign = 1;
222583c04c93SPyun YongHyeon 	/*
222683c04c93SPyun YongHyeon 	 * Workaround hardware hang which seems to happen when Rx buffer
222783c04c93SPyun YongHyeon 	 * is not aligned on multiple of FIFO word(8 bytes).
222883c04c93SPyun YongHyeon 	 */
222983c04c93SPyun YongHyeon 	if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
223083c04c93SPyun YongHyeon 		rxalign = MSK_RX_BUF_ALIGN;
22310dbe28b3SPyun YongHyeon 	/* Create tag for Rx buffers. */
22320dbe28b3SPyun YongHyeon 	error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
223383c04c93SPyun YongHyeon 		    rxalign, 0,			/* alignment, boundary */
22340dbe28b3SPyun YongHyeon 		    BUS_SPACE_MAXADDR,		/* lowaddr */
22350dbe28b3SPyun YongHyeon 		    BUS_SPACE_MAXADDR,		/* highaddr */
22360dbe28b3SPyun YongHyeon 		    NULL, NULL,			/* filter, filterarg */
22370dbe28b3SPyun YongHyeon 		    MCLBYTES,			/* maxsize */
22380dbe28b3SPyun YongHyeon 		    1,				/* nsegments */
22390dbe28b3SPyun YongHyeon 		    MCLBYTES,			/* maxsegsize */
22400dbe28b3SPyun YongHyeon 		    0,				/* flags */
22410dbe28b3SPyun YongHyeon 		    NULL, NULL,			/* lockfunc, lockarg */
22420dbe28b3SPyun YongHyeon 		    &sc_if->msk_cdata.msk_rx_tag);
22430dbe28b3SPyun YongHyeon 	if (error != 0) {
22440dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev,
22450dbe28b3SPyun YongHyeon 		    "failed to create Rx DMA tag\n");
22460dbe28b3SPyun YongHyeon 		goto fail;
22470dbe28b3SPyun YongHyeon 	}
22480dbe28b3SPyun YongHyeon 
22490dbe28b3SPyun YongHyeon 	/* Allocate DMA'able memory and load the DMA map for Tx ring. */
22500dbe28b3SPyun YongHyeon 	error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag,
22510dbe28b3SPyun YongHyeon 	    (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK |
22520dbe28b3SPyun YongHyeon 	    BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map);
22530dbe28b3SPyun YongHyeon 	if (error != 0) {
22540dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev,
22550dbe28b3SPyun YongHyeon 		    "failed to allocate DMA'able memory for Tx ring\n");
22560dbe28b3SPyun YongHyeon 		goto fail;
22570dbe28b3SPyun YongHyeon 	}
22580dbe28b3SPyun YongHyeon 
22590dbe28b3SPyun YongHyeon 	ctx.msk_busaddr = 0;
22600dbe28b3SPyun YongHyeon 	error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag,
22610dbe28b3SPyun YongHyeon 	    sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring,
22620dbe28b3SPyun YongHyeon 	    MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, 0);
22630dbe28b3SPyun YongHyeon 	if (error != 0) {
22640dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev,
22650dbe28b3SPyun YongHyeon 		    "failed to load DMA'able memory for Tx ring\n");
22660dbe28b3SPyun YongHyeon 		goto fail;
22670dbe28b3SPyun YongHyeon 	}
22680dbe28b3SPyun YongHyeon 	sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr;
22690dbe28b3SPyun YongHyeon 
22700dbe28b3SPyun YongHyeon 	/* Allocate DMA'able memory and load the DMA map for Rx ring. */
22710dbe28b3SPyun YongHyeon 	error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag,
22720dbe28b3SPyun YongHyeon 	    (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK |
22730dbe28b3SPyun YongHyeon 	    BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map);
22740dbe28b3SPyun YongHyeon 	if (error != 0) {
22750dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev,
22760dbe28b3SPyun YongHyeon 		    "failed to allocate DMA'able memory for Rx ring\n");
22770dbe28b3SPyun YongHyeon 		goto fail;
22780dbe28b3SPyun YongHyeon 	}
22790dbe28b3SPyun YongHyeon 
22800dbe28b3SPyun YongHyeon 	ctx.msk_busaddr = 0;
22810dbe28b3SPyun YongHyeon 	error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag,
22820dbe28b3SPyun YongHyeon 	    sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring,
22830dbe28b3SPyun YongHyeon 	    MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, 0);
22840dbe28b3SPyun YongHyeon 	if (error != 0) {
22850dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev,
22860dbe28b3SPyun YongHyeon 		    "failed to load DMA'able memory for Rx ring\n");
22870dbe28b3SPyun YongHyeon 		goto fail;
22880dbe28b3SPyun YongHyeon 	}
22890dbe28b3SPyun YongHyeon 	sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr;
22900dbe28b3SPyun YongHyeon 
22910dbe28b3SPyun YongHyeon 	/* Create DMA maps for Tx buffers. */
22920dbe28b3SPyun YongHyeon 	for (i = 0; i < MSK_TX_RING_CNT; i++) {
22930dbe28b3SPyun YongHyeon 		txd = &sc_if->msk_cdata.msk_txdesc[i];
22940dbe28b3SPyun YongHyeon 		txd->tx_m = NULL;
22950dbe28b3SPyun YongHyeon 		txd->tx_dmamap = NULL;
22960dbe28b3SPyun YongHyeon 		error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0,
22970dbe28b3SPyun YongHyeon 		    &txd->tx_dmamap);
22980dbe28b3SPyun YongHyeon 		if (error != 0) {
22990dbe28b3SPyun YongHyeon 			device_printf(sc_if->msk_if_dev,
23000dbe28b3SPyun YongHyeon 			    "failed to create Tx dmamap\n");
23010dbe28b3SPyun YongHyeon 			goto fail;
23020dbe28b3SPyun YongHyeon 		}
23030dbe28b3SPyun YongHyeon 	}
23040dbe28b3SPyun YongHyeon 	/* Create DMA maps for Rx buffers. */
23050dbe28b3SPyun YongHyeon 	if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0,
23060dbe28b3SPyun YongHyeon 	    &sc_if->msk_cdata.msk_rx_sparemap)) != 0) {
23070dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev,
23080dbe28b3SPyun YongHyeon 		    "failed to create spare Rx dmamap\n");
23090dbe28b3SPyun YongHyeon 		goto fail;
23100dbe28b3SPyun YongHyeon 	}
23110dbe28b3SPyun YongHyeon 	for (i = 0; i < MSK_RX_RING_CNT; i++) {
23120dbe28b3SPyun YongHyeon 		rxd = &sc_if->msk_cdata.msk_rxdesc[i];
23130dbe28b3SPyun YongHyeon 		rxd->rx_m = NULL;
23140dbe28b3SPyun YongHyeon 		rxd->rx_dmamap = NULL;
23150dbe28b3SPyun YongHyeon 		error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0,
23160dbe28b3SPyun YongHyeon 		    &rxd->rx_dmamap);
23170dbe28b3SPyun YongHyeon 		if (error != 0) {
23180dbe28b3SPyun YongHyeon 			device_printf(sc_if->msk_if_dev,
23190dbe28b3SPyun YongHyeon 			    "failed to create Rx dmamap\n");
23200dbe28b3SPyun YongHyeon 			goto fail;
23210dbe28b3SPyun YongHyeon 		}
23220dbe28b3SPyun YongHyeon 	}
232385b340cbSPyun YongHyeon 
232485b340cbSPyun YongHyeon fail:
232585b340cbSPyun YongHyeon 	return (error);
232685b340cbSPyun YongHyeon }
232785b340cbSPyun YongHyeon 
232885b340cbSPyun YongHyeon static int
232985b340cbSPyun YongHyeon msk_rx_dma_jalloc(struct msk_if_softc *sc_if)
233085b340cbSPyun YongHyeon {
233185b340cbSPyun YongHyeon 	struct msk_dmamap_arg ctx;
233285b340cbSPyun YongHyeon 	struct msk_rxdesc *jrxd;
233385b340cbSPyun YongHyeon 	bus_size_t rxalign;
233485b340cbSPyun YongHyeon 	int error, i;
233585b340cbSPyun YongHyeon 
2336e2b16603SPyun YongHyeon 	if (jumbo_disable != 0 || (sc_if->msk_flags & MSK_FLAG_JUMBO) == 0) {
2337e2b16603SPyun YongHyeon 		sc_if->msk_flags &= ~MSK_FLAG_JUMBO;
233885b340cbSPyun YongHyeon 		device_printf(sc_if->msk_if_dev,
233985b340cbSPyun YongHyeon 		    "disabling jumbo frame support\n");
234085b340cbSPyun YongHyeon 		return (0);
234185b340cbSPyun YongHyeon 	}
234285b340cbSPyun YongHyeon 	/* Create tag for jumbo Rx ring. */
234385b340cbSPyun YongHyeon 	error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
234485b340cbSPyun YongHyeon 		    MSK_RING_ALIGN, 0,		/* alignment, boundary */
234585b340cbSPyun YongHyeon 		    BUS_SPACE_MAXADDR,		/* lowaddr */
234685b340cbSPyun YongHyeon 		    BUS_SPACE_MAXADDR,		/* highaddr */
234785b340cbSPyun YongHyeon 		    NULL, NULL,			/* filter, filterarg */
234885b340cbSPyun YongHyeon 		    MSK_JUMBO_RX_RING_SZ,	/* maxsize */
234985b340cbSPyun YongHyeon 		    1,				/* nsegments */
235085b340cbSPyun YongHyeon 		    MSK_JUMBO_RX_RING_SZ,	/* maxsegsize */
235185b340cbSPyun YongHyeon 		    0,				/* flags */
235285b340cbSPyun YongHyeon 		    NULL, NULL,			/* lockfunc, lockarg */
235385b340cbSPyun YongHyeon 		    &sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
235485b340cbSPyun YongHyeon 	if (error != 0) {
235585b340cbSPyun YongHyeon 		device_printf(sc_if->msk_if_dev,
235685b340cbSPyun YongHyeon 		    "failed to create jumbo Rx ring DMA tag\n");
235785b340cbSPyun YongHyeon 		goto jumbo_fail;
235885b340cbSPyun YongHyeon 	}
235985b340cbSPyun YongHyeon 
236085b340cbSPyun YongHyeon 	rxalign = 1;
236185b340cbSPyun YongHyeon 	/*
236285b340cbSPyun YongHyeon 	 * Workaround hardware hang which seems to happen when Rx buffer
236385b340cbSPyun YongHyeon 	 * is not aligned on multiple of FIFO word(8 bytes).
236485b340cbSPyun YongHyeon 	 */
236585b340cbSPyun YongHyeon 	if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
236685b340cbSPyun YongHyeon 		rxalign = MSK_RX_BUF_ALIGN;
236785b340cbSPyun YongHyeon 	/* Create tag for jumbo Rx buffers. */
236885b340cbSPyun YongHyeon 	error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */
236985b340cbSPyun YongHyeon 		    rxalign, 0,			/* alignment, boundary */
237085b340cbSPyun YongHyeon 		    BUS_SPACE_MAXADDR,		/* lowaddr */
237185b340cbSPyun YongHyeon 		    BUS_SPACE_MAXADDR,		/* highaddr */
237285b340cbSPyun YongHyeon 		    NULL, NULL,			/* filter, filterarg */
237385b340cbSPyun YongHyeon 		    MJUM9BYTES,			/* maxsize */
237485b340cbSPyun YongHyeon 		    1,				/* nsegments */
237585b340cbSPyun YongHyeon 		    MJUM9BYTES,			/* maxsegsize */
237685b340cbSPyun YongHyeon 		    0,				/* flags */
237785b340cbSPyun YongHyeon 		    NULL, NULL,			/* lockfunc, lockarg */
237885b340cbSPyun YongHyeon 		    &sc_if->msk_cdata.msk_jumbo_rx_tag);
237985b340cbSPyun YongHyeon 	if (error != 0) {
238085b340cbSPyun YongHyeon 		device_printf(sc_if->msk_if_dev,
238185b340cbSPyun YongHyeon 		    "failed to create jumbo Rx DMA tag\n");
238285b340cbSPyun YongHyeon 		goto jumbo_fail;
238385b340cbSPyun YongHyeon 	}
238485b340cbSPyun YongHyeon 
238585b340cbSPyun YongHyeon 	/* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */
238685b340cbSPyun YongHyeon 	error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
238785b340cbSPyun YongHyeon 	    (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring,
238885b340cbSPyun YongHyeon 	    BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO,
238985b340cbSPyun YongHyeon 	    &sc_if->msk_cdata.msk_jumbo_rx_ring_map);
239085b340cbSPyun YongHyeon 	if (error != 0) {
239185b340cbSPyun YongHyeon 		device_printf(sc_if->msk_if_dev,
239285b340cbSPyun YongHyeon 		    "failed to allocate DMA'able memory for jumbo Rx ring\n");
239385b340cbSPyun YongHyeon 		goto jumbo_fail;
239485b340cbSPyun YongHyeon 	}
239585b340cbSPyun YongHyeon 
239685b340cbSPyun YongHyeon 	ctx.msk_busaddr = 0;
239785b340cbSPyun YongHyeon 	error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
239885b340cbSPyun YongHyeon 	    sc_if->msk_cdata.msk_jumbo_rx_ring_map,
239985b340cbSPyun YongHyeon 	    sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ,
240085b340cbSPyun YongHyeon 	    msk_dmamap_cb, &ctx, 0);
240185b340cbSPyun YongHyeon 	if (error != 0) {
240285b340cbSPyun YongHyeon 		device_printf(sc_if->msk_if_dev,
240385b340cbSPyun YongHyeon 		    "failed to load DMA'able memory for jumbo Rx ring\n");
240485b340cbSPyun YongHyeon 		goto jumbo_fail;
240585b340cbSPyun YongHyeon 	}
240685b340cbSPyun YongHyeon 	sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr;
240785b340cbSPyun YongHyeon 
24080dbe28b3SPyun YongHyeon 	/* Create DMA maps for jumbo Rx buffers. */
24090dbe28b3SPyun YongHyeon 	if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
24100dbe28b3SPyun YongHyeon 	    &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) {
24110dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev,
24120dbe28b3SPyun YongHyeon 		    "failed to create spare jumbo Rx dmamap\n");
241385b340cbSPyun YongHyeon 		goto jumbo_fail;
24140dbe28b3SPyun YongHyeon 	}
24150dbe28b3SPyun YongHyeon 	for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
24160dbe28b3SPyun YongHyeon 		jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
24170dbe28b3SPyun YongHyeon 		jrxd->rx_m = NULL;
24180dbe28b3SPyun YongHyeon 		jrxd->rx_dmamap = NULL;
24190dbe28b3SPyun YongHyeon 		error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0,
24200dbe28b3SPyun YongHyeon 		    &jrxd->rx_dmamap);
24210dbe28b3SPyun YongHyeon 		if (error != 0) {
24220dbe28b3SPyun YongHyeon 			device_printf(sc_if->msk_if_dev,
24230dbe28b3SPyun YongHyeon 			    "failed to create jumbo Rx dmamap\n");
242485b340cbSPyun YongHyeon 			goto jumbo_fail;
24250dbe28b3SPyun YongHyeon 		}
24260dbe28b3SPyun YongHyeon 	}
24270dbe28b3SPyun YongHyeon 
242885b340cbSPyun YongHyeon 	return (0);
24290dbe28b3SPyun YongHyeon 
243085b340cbSPyun YongHyeon jumbo_fail:
243185b340cbSPyun YongHyeon 	msk_rx_dma_jfree(sc_if);
243285b340cbSPyun YongHyeon 	device_printf(sc_if->msk_if_dev, "disabling jumbo frame support "
243385b340cbSPyun YongHyeon 	    "due to resource shortage\n");
2434e2b16603SPyun YongHyeon 	sc_if->msk_flags &= ~MSK_FLAG_JUMBO;
24350dbe28b3SPyun YongHyeon 	return (error);
24360dbe28b3SPyun YongHyeon }
24370dbe28b3SPyun YongHyeon 
24380dbe28b3SPyun YongHyeon static void
24390dbe28b3SPyun YongHyeon msk_txrx_dma_free(struct msk_if_softc *sc_if)
24400dbe28b3SPyun YongHyeon {
24410dbe28b3SPyun YongHyeon 	struct msk_txdesc *txd;
24420dbe28b3SPyun YongHyeon 	struct msk_rxdesc *rxd;
24430dbe28b3SPyun YongHyeon 	int i;
24440dbe28b3SPyun YongHyeon 
24450dbe28b3SPyun YongHyeon 	/* Tx ring. */
24460dbe28b3SPyun YongHyeon 	if (sc_if->msk_cdata.msk_tx_ring_tag) {
24470dbe28b3SPyun YongHyeon 		if (sc_if->msk_cdata.msk_tx_ring_map)
24480dbe28b3SPyun YongHyeon 			bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag,
24490dbe28b3SPyun YongHyeon 			    sc_if->msk_cdata.msk_tx_ring_map);
24500dbe28b3SPyun YongHyeon 		if (sc_if->msk_cdata.msk_tx_ring_map &&
24510dbe28b3SPyun YongHyeon 		    sc_if->msk_rdata.msk_tx_ring)
24520dbe28b3SPyun YongHyeon 			bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag,
24530dbe28b3SPyun YongHyeon 			    sc_if->msk_rdata.msk_tx_ring,
24540dbe28b3SPyun YongHyeon 			    sc_if->msk_cdata.msk_tx_ring_map);
24550dbe28b3SPyun YongHyeon 		sc_if->msk_rdata.msk_tx_ring = NULL;
24560dbe28b3SPyun YongHyeon 		sc_if->msk_cdata.msk_tx_ring_map = NULL;
24570dbe28b3SPyun YongHyeon 		bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag);
24580dbe28b3SPyun YongHyeon 		sc_if->msk_cdata.msk_tx_ring_tag = NULL;
24590dbe28b3SPyun YongHyeon 	}
24600dbe28b3SPyun YongHyeon 	/* Rx ring. */
24610dbe28b3SPyun YongHyeon 	if (sc_if->msk_cdata.msk_rx_ring_tag) {
24620dbe28b3SPyun YongHyeon 		if (sc_if->msk_cdata.msk_rx_ring_map)
24630dbe28b3SPyun YongHyeon 			bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag,
24640dbe28b3SPyun YongHyeon 			    sc_if->msk_cdata.msk_rx_ring_map);
24650dbe28b3SPyun YongHyeon 		if (sc_if->msk_cdata.msk_rx_ring_map &&
24660dbe28b3SPyun YongHyeon 		    sc_if->msk_rdata.msk_rx_ring)
24670dbe28b3SPyun YongHyeon 			bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag,
24680dbe28b3SPyun YongHyeon 			    sc_if->msk_rdata.msk_rx_ring,
24690dbe28b3SPyun YongHyeon 			    sc_if->msk_cdata.msk_rx_ring_map);
24700dbe28b3SPyun YongHyeon 		sc_if->msk_rdata.msk_rx_ring = NULL;
24710dbe28b3SPyun YongHyeon 		sc_if->msk_cdata.msk_rx_ring_map = NULL;
24720dbe28b3SPyun YongHyeon 		bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag);
24730dbe28b3SPyun YongHyeon 		sc_if->msk_cdata.msk_rx_ring_tag = NULL;
24740dbe28b3SPyun YongHyeon 	}
24750dbe28b3SPyun YongHyeon 	/* Tx buffers. */
24760dbe28b3SPyun YongHyeon 	if (sc_if->msk_cdata.msk_tx_tag) {
24770dbe28b3SPyun YongHyeon 		for (i = 0; i < MSK_TX_RING_CNT; i++) {
24780dbe28b3SPyun YongHyeon 			txd = &sc_if->msk_cdata.msk_txdesc[i];
24790dbe28b3SPyun YongHyeon 			if (txd->tx_dmamap) {
24800dbe28b3SPyun YongHyeon 				bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag,
24810dbe28b3SPyun YongHyeon 				    txd->tx_dmamap);
24820dbe28b3SPyun YongHyeon 				txd->tx_dmamap = NULL;
24830dbe28b3SPyun YongHyeon 			}
24840dbe28b3SPyun YongHyeon 		}
24850dbe28b3SPyun YongHyeon 		bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag);
24860dbe28b3SPyun YongHyeon 		sc_if->msk_cdata.msk_tx_tag = NULL;
24870dbe28b3SPyun YongHyeon 	}
24880dbe28b3SPyun YongHyeon 	/* Rx buffers. */
24890dbe28b3SPyun YongHyeon 	if (sc_if->msk_cdata.msk_rx_tag) {
24900dbe28b3SPyun YongHyeon 		for (i = 0; i < MSK_RX_RING_CNT; i++) {
24910dbe28b3SPyun YongHyeon 			rxd = &sc_if->msk_cdata.msk_rxdesc[i];
24920dbe28b3SPyun YongHyeon 			if (rxd->rx_dmamap) {
24930dbe28b3SPyun YongHyeon 				bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
24940dbe28b3SPyun YongHyeon 				    rxd->rx_dmamap);
24950dbe28b3SPyun YongHyeon 				rxd->rx_dmamap = NULL;
24960dbe28b3SPyun YongHyeon 			}
24970dbe28b3SPyun YongHyeon 		}
24980dbe28b3SPyun YongHyeon 		if (sc_if->msk_cdata.msk_rx_sparemap) {
24990dbe28b3SPyun YongHyeon 			bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag,
25000dbe28b3SPyun YongHyeon 			    sc_if->msk_cdata.msk_rx_sparemap);
25010dbe28b3SPyun YongHyeon 			sc_if->msk_cdata.msk_rx_sparemap = 0;
25020dbe28b3SPyun YongHyeon 		}
25030dbe28b3SPyun YongHyeon 		bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag);
25040dbe28b3SPyun YongHyeon 		sc_if->msk_cdata.msk_rx_tag = NULL;
25050dbe28b3SPyun YongHyeon 	}
250685b340cbSPyun YongHyeon 	if (sc_if->msk_cdata.msk_parent_tag) {
250785b340cbSPyun YongHyeon 		bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag);
250885b340cbSPyun YongHyeon 		sc_if->msk_cdata.msk_parent_tag = NULL;
250985b340cbSPyun YongHyeon 	}
251085b340cbSPyun YongHyeon }
251185b340cbSPyun YongHyeon 
251285b340cbSPyun YongHyeon static void
251385b340cbSPyun YongHyeon msk_rx_dma_jfree(struct msk_if_softc *sc_if)
251485b340cbSPyun YongHyeon {
251585b340cbSPyun YongHyeon 	struct msk_rxdesc *jrxd;
251685b340cbSPyun YongHyeon 	int i;
251785b340cbSPyun YongHyeon 
251885b340cbSPyun YongHyeon 	/* Jumbo Rx ring. */
251985b340cbSPyun YongHyeon 	if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) {
252085b340cbSPyun YongHyeon 		if (sc_if->msk_cdata.msk_jumbo_rx_ring_map)
252185b340cbSPyun YongHyeon 			bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
252285b340cbSPyun YongHyeon 			    sc_if->msk_cdata.msk_jumbo_rx_ring_map);
252385b340cbSPyun YongHyeon 		if (sc_if->msk_cdata.msk_jumbo_rx_ring_map &&
252485b340cbSPyun YongHyeon 		    sc_if->msk_rdata.msk_jumbo_rx_ring)
252585b340cbSPyun YongHyeon 			bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
252685b340cbSPyun YongHyeon 			    sc_if->msk_rdata.msk_jumbo_rx_ring,
252785b340cbSPyun YongHyeon 			    sc_if->msk_cdata.msk_jumbo_rx_ring_map);
252885b340cbSPyun YongHyeon 		sc_if->msk_rdata.msk_jumbo_rx_ring = NULL;
252985b340cbSPyun YongHyeon 		sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL;
253085b340cbSPyun YongHyeon 		bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag);
253185b340cbSPyun YongHyeon 		sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL;
253285b340cbSPyun YongHyeon 	}
25330dbe28b3SPyun YongHyeon 	/* Jumbo Rx buffers. */
25340dbe28b3SPyun YongHyeon 	if (sc_if->msk_cdata.msk_jumbo_rx_tag) {
25350dbe28b3SPyun YongHyeon 		for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
25360dbe28b3SPyun YongHyeon 			jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
25370dbe28b3SPyun YongHyeon 			if (jrxd->rx_dmamap) {
25380dbe28b3SPyun YongHyeon 				bus_dmamap_destroy(
25390dbe28b3SPyun YongHyeon 				    sc_if->msk_cdata.msk_jumbo_rx_tag,
25400dbe28b3SPyun YongHyeon 				    jrxd->rx_dmamap);
25410dbe28b3SPyun YongHyeon 				jrxd->rx_dmamap = NULL;
25420dbe28b3SPyun YongHyeon 			}
25430dbe28b3SPyun YongHyeon 		}
25440dbe28b3SPyun YongHyeon 		if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) {
25450dbe28b3SPyun YongHyeon 			bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag,
25460dbe28b3SPyun YongHyeon 			    sc_if->msk_cdata.msk_jumbo_rx_sparemap);
25470dbe28b3SPyun YongHyeon 			sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0;
25480dbe28b3SPyun YongHyeon 		}
25490dbe28b3SPyun YongHyeon 		bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag);
25500dbe28b3SPyun YongHyeon 		sc_if->msk_cdata.msk_jumbo_rx_tag = NULL;
25510dbe28b3SPyun YongHyeon 	}
25520dbe28b3SPyun YongHyeon }
25530dbe28b3SPyun YongHyeon 
25540dbe28b3SPyun YongHyeon static int
25550dbe28b3SPyun YongHyeon msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head)
25560dbe28b3SPyun YongHyeon {
25570dbe28b3SPyun YongHyeon 	struct msk_txdesc *txd, *txd_last;
25580dbe28b3SPyun YongHyeon 	struct msk_tx_desc *tx_le;
25590dbe28b3SPyun YongHyeon 	struct mbuf *m;
25600dbe28b3SPyun YongHyeon 	bus_dmamap_t map;
25610dbe28b3SPyun YongHyeon 	bus_dma_segment_t txsegs[MSK_MAXTXSEGS];
25621b7757c0SPyun YongHyeon 	uint32_t control, csum, prod, si;
25630dbe28b3SPyun YongHyeon 	uint16_t offset, tcp_offset, tso_mtu;
25640dbe28b3SPyun YongHyeon 	int error, i, nseg, tso;
25650dbe28b3SPyun YongHyeon 
25660dbe28b3SPyun YongHyeon 	MSK_IF_LOCK_ASSERT(sc_if);
25670dbe28b3SPyun YongHyeon 
25680dbe28b3SPyun YongHyeon 	tcp_offset = offset = 0;
25690dbe28b3SPyun YongHyeon 	m = *m_head;
2570ebb25bfaSPyun YongHyeon 	if (((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 &&
2571ebb25bfaSPyun YongHyeon 	    (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) ||
2572ebb25bfaSPyun YongHyeon 	    ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
2573ebb25bfaSPyun YongHyeon 	    (m->m_pkthdr.csum_flags & CSUM_TSO) != 0)) {
25740dbe28b3SPyun YongHyeon 		/*
25750dbe28b3SPyun YongHyeon 		 * Since mbuf has no protocol specific structure information
25760dbe28b3SPyun YongHyeon 		 * in it we have to inspect protocol information here to
25770dbe28b3SPyun YongHyeon 		 * setup TSO and checksum offload. I don't know why Marvell
25780dbe28b3SPyun YongHyeon 		 * made a such decision in chip design because other GigE
25790dbe28b3SPyun YongHyeon 		 * hardwares normally takes care of all these chores in
25800dbe28b3SPyun YongHyeon 		 * hardware. However, TSO performance of Yukon II is very
25810dbe28b3SPyun YongHyeon 		 * good such that it's worth to implement it.
25820dbe28b3SPyun YongHyeon 		 */
25830dbe28b3SPyun YongHyeon 		struct ether_header *eh;
25840dbe28b3SPyun YongHyeon 		struct ip *ip;
25850dbe28b3SPyun YongHyeon 		struct tcphdr *tcp;
25860dbe28b3SPyun YongHyeon 
2587ad415775SPyun YongHyeon 		if (M_WRITABLE(m) == 0) {
2588ad415775SPyun YongHyeon 			/* Get a writable copy. */
2589ad415775SPyun YongHyeon 			m = m_dup(*m_head, M_DONTWAIT);
2590ad415775SPyun YongHyeon 			m_freem(*m_head);
2591ad415775SPyun YongHyeon 			if (m == NULL) {
2592ad415775SPyun YongHyeon 				*m_head = NULL;
2593ad415775SPyun YongHyeon 				return (ENOBUFS);
2594ad415775SPyun YongHyeon 			}
2595ad415775SPyun YongHyeon 			*m_head = m;
2596ad415775SPyun YongHyeon 		}
25970dbe28b3SPyun YongHyeon 
25980dbe28b3SPyun YongHyeon 		offset = sizeof(struct ether_header);
25990dbe28b3SPyun YongHyeon 		m = m_pullup(m, offset);
26000dbe28b3SPyun YongHyeon 		if (m == NULL) {
26010dbe28b3SPyun YongHyeon 			*m_head = NULL;
26020dbe28b3SPyun YongHyeon 			return (ENOBUFS);
26030dbe28b3SPyun YongHyeon 		}
26040dbe28b3SPyun YongHyeon 		eh = mtod(m, struct ether_header *);
26050dbe28b3SPyun YongHyeon 		/* Check if hardware VLAN insertion is off. */
26060dbe28b3SPyun YongHyeon 		if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
26070dbe28b3SPyun YongHyeon 			offset = sizeof(struct ether_vlan_header);
26080dbe28b3SPyun YongHyeon 			m = m_pullup(m, offset);
26090dbe28b3SPyun YongHyeon 			if (m == NULL) {
26100dbe28b3SPyun YongHyeon 				*m_head = NULL;
26110dbe28b3SPyun YongHyeon 				return (ENOBUFS);
26120dbe28b3SPyun YongHyeon 			}
2613b5898b80SPyun YongHyeon 		}
26140dbe28b3SPyun YongHyeon 		m = m_pullup(m, offset + sizeof(struct ip));
26150dbe28b3SPyun YongHyeon 		if (m == NULL) {
26160dbe28b3SPyun YongHyeon 			*m_head = NULL;
26170dbe28b3SPyun YongHyeon 			return (ENOBUFS);
26180dbe28b3SPyun YongHyeon 		}
2619b5898b80SPyun YongHyeon 		ip = (struct ip *)(mtod(m, char *) + offset);
26200dbe28b3SPyun YongHyeon 		offset += (ip->ip_hl << 2);
26210dbe28b3SPyun YongHyeon 		tcp_offset = offset;
26226da6d0a9SPyun YongHyeon 		if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
26236da6d0a9SPyun YongHyeon 			m = m_pullup(m, offset + sizeof(struct tcphdr));
26246da6d0a9SPyun YongHyeon 			if (m == NULL) {
26256da6d0a9SPyun YongHyeon 				*m_head = NULL;
26266da6d0a9SPyun YongHyeon 				return (ENOBUFS);
26276da6d0a9SPyun YongHyeon 			}
26286da6d0a9SPyun YongHyeon 			tcp = (struct tcphdr *)(mtod(m, char *) + offset);
26296da6d0a9SPyun YongHyeon 			offset += (tcp->th_off << 2);
26306da6d0a9SPyun YongHyeon 		} else if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) == 0 &&
26316da6d0a9SPyun YongHyeon 		    (m->m_pkthdr.len < MSK_MIN_FRAMELEN) &&
26326da6d0a9SPyun YongHyeon 		    (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) {
2633b5898b80SPyun YongHyeon 			/*
26346da6d0a9SPyun YongHyeon 			 * It seems that Yukon II has Tx checksum offload bug
26356da6d0a9SPyun YongHyeon 			 * for small TCP packets that's less than 60 bytes in
26366da6d0a9SPyun YongHyeon 			 * size (e.g. TCP window probe packet, pure ACK packet).
26376da6d0a9SPyun YongHyeon 			 * Common work around like padding with zeros to make
26386da6d0a9SPyun YongHyeon 			 * the frame minimum ethernet frame size didn't work at
26396da6d0a9SPyun YongHyeon 			 * all.
2640b5898b80SPyun YongHyeon 			 * Instead of disabling checksum offload completely we
26416da6d0a9SPyun YongHyeon 			 * resort to S/W checksum routine when we encounter
26426da6d0a9SPyun YongHyeon 			 * short TCP frames.
2643b5898b80SPyun YongHyeon 			 * Short UDP packets appear to be handled correctly by
2644ebb25bfaSPyun YongHyeon 			 * Yukon II. Also I assume this bug does not happen on
2645ebb25bfaSPyun YongHyeon 			 * controllers that use newer descriptor format or
2646b1ce21c6SRebecca Cran 			 * automatic Tx checksum calculation.
2647b5898b80SPyun YongHyeon 			 */
2648925da971SPyun YongHyeon 			m = m_pullup(m, offset + sizeof(struct tcphdr));
2649925da971SPyun YongHyeon 			if (m == NULL) {
2650925da971SPyun YongHyeon 				*m_head = NULL;
2651925da971SPyun YongHyeon 				return (ENOBUFS);
2652925da971SPyun YongHyeon 			}
2653b5898b80SPyun YongHyeon 			*(uint16_t *)(m->m_data + offset +
2654f9ad2b2fSPyun YongHyeon 			    m->m_pkthdr.csum_data) = in_cksum_skip(m,
2655f9ad2b2fSPyun YongHyeon 			    m->m_pkthdr.len, offset);
2656b5898b80SPyun YongHyeon 			m->m_pkthdr.csum_flags &= ~CSUM_TCP;
2657b5898b80SPyun YongHyeon 		}
26580dbe28b3SPyun YongHyeon 		*m_head = m;
26590dbe28b3SPyun YongHyeon 	}
26600dbe28b3SPyun YongHyeon 
26610dbe28b3SPyun YongHyeon 	prod = sc_if->msk_cdata.msk_tx_prod;
26620dbe28b3SPyun YongHyeon 	txd = &sc_if->msk_cdata.msk_txdesc[prod];
26630dbe28b3SPyun YongHyeon 	txd_last = txd;
26640dbe28b3SPyun YongHyeon 	map = txd->tx_dmamap;
26650dbe28b3SPyun YongHyeon 	error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map,
26660dbe28b3SPyun YongHyeon 	    *m_head, txsegs, &nseg, BUS_DMA_NOWAIT);
26670dbe28b3SPyun YongHyeon 	if (error == EFBIG) {
2668304a4c6fSJohn Baldwin 		m = m_collapse(*m_head, M_DONTWAIT, MSK_MAXTXSEGS);
26690dbe28b3SPyun YongHyeon 		if (m == NULL) {
26700dbe28b3SPyun YongHyeon 			m_freem(*m_head);
26710dbe28b3SPyun YongHyeon 			*m_head = NULL;
26720dbe28b3SPyun YongHyeon 			return (ENOBUFS);
26730dbe28b3SPyun YongHyeon 		}
26740dbe28b3SPyun YongHyeon 		*m_head = m;
26750dbe28b3SPyun YongHyeon 		error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag,
26760dbe28b3SPyun YongHyeon 		    map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT);
26770dbe28b3SPyun YongHyeon 		if (error != 0) {
26780dbe28b3SPyun YongHyeon 			m_freem(*m_head);
26790dbe28b3SPyun YongHyeon 			*m_head = NULL;
26800dbe28b3SPyun YongHyeon 			return (error);
26810dbe28b3SPyun YongHyeon 		}
26820dbe28b3SPyun YongHyeon 	} else if (error != 0)
26830dbe28b3SPyun YongHyeon 		return (error);
26840dbe28b3SPyun YongHyeon 	if (nseg == 0) {
26850dbe28b3SPyun YongHyeon 		m_freem(*m_head);
26860dbe28b3SPyun YongHyeon 		*m_head = NULL;
26870dbe28b3SPyun YongHyeon 		return (EIO);
26880dbe28b3SPyun YongHyeon 	}
26890dbe28b3SPyun YongHyeon 
26900dbe28b3SPyun YongHyeon 	/* Check number of available descriptors. */
26910dbe28b3SPyun YongHyeon 	if (sc_if->msk_cdata.msk_tx_cnt + nseg >=
26920dbe28b3SPyun YongHyeon 	    (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) {
26930dbe28b3SPyun YongHyeon 		bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map);
26940dbe28b3SPyun YongHyeon 		return (ENOBUFS);
26950dbe28b3SPyun YongHyeon 	}
26960dbe28b3SPyun YongHyeon 
26970dbe28b3SPyun YongHyeon 	control = 0;
26980dbe28b3SPyun YongHyeon 	tso = 0;
26990dbe28b3SPyun YongHyeon 	tx_le = NULL;
27000dbe28b3SPyun YongHyeon 
27010dbe28b3SPyun YongHyeon 	/* Check TSO support. */
27020dbe28b3SPyun YongHyeon 	if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
2703262e9dcfSPyun YongHyeon 		if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0)
2704262e9dcfSPyun YongHyeon 			tso_mtu = m->m_pkthdr.tso_segsz;
2705262e9dcfSPyun YongHyeon 		else
27060dbe28b3SPyun YongHyeon 			tso_mtu = offset + m->m_pkthdr.tso_segsz;
27070dbe28b3SPyun YongHyeon 		if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) {
27080dbe28b3SPyun YongHyeon 			tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
27090dbe28b3SPyun YongHyeon 			tx_le->msk_addr = htole32(tso_mtu);
2710262e9dcfSPyun YongHyeon 			if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0)
2711262e9dcfSPyun YongHyeon 				tx_le->msk_control = htole32(OP_MSS | HW_OWNER);
2712262e9dcfSPyun YongHyeon 			else
2713262e9dcfSPyun YongHyeon 				tx_le->msk_control =
2714262e9dcfSPyun YongHyeon 				    htole32(OP_LRGLEN | HW_OWNER);
27150dbe28b3SPyun YongHyeon 			sc_if->msk_cdata.msk_tx_cnt++;
27160dbe28b3SPyun YongHyeon 			MSK_INC(prod, MSK_TX_RING_CNT);
27170dbe28b3SPyun YongHyeon 			sc_if->msk_cdata.msk_tso_mtu = tso_mtu;
27180dbe28b3SPyun YongHyeon 		}
27190dbe28b3SPyun YongHyeon 		tso++;
27200dbe28b3SPyun YongHyeon 	}
27210dbe28b3SPyun YongHyeon 	/* Check if we have a VLAN tag to insert. */
27220dbe28b3SPyun YongHyeon 	if ((m->m_flags & M_VLANTAG) != 0) {
2723d06930afSPyun YongHyeon 		if (tx_le == NULL) {
27240dbe28b3SPyun YongHyeon 			tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
27250dbe28b3SPyun YongHyeon 			tx_le->msk_addr = htole32(0);
27260dbe28b3SPyun YongHyeon 			tx_le->msk_control = htole32(OP_VLAN | HW_OWNER |
27270dbe28b3SPyun YongHyeon 			    htons(m->m_pkthdr.ether_vtag));
27280dbe28b3SPyun YongHyeon 			sc_if->msk_cdata.msk_tx_cnt++;
27290dbe28b3SPyun YongHyeon 			MSK_INC(prod, MSK_TX_RING_CNT);
27300dbe28b3SPyun YongHyeon 		} else {
27310dbe28b3SPyun YongHyeon 			tx_le->msk_control |= htole32(OP_VLAN |
27320dbe28b3SPyun YongHyeon 			    htons(m->m_pkthdr.ether_vtag));
27330dbe28b3SPyun YongHyeon 		}
27340dbe28b3SPyun YongHyeon 		control |= INS_VLAN;
27350dbe28b3SPyun YongHyeon 	}
27360dbe28b3SPyun YongHyeon 	/* Check if we have to handle checksum offload. */
27370dbe28b3SPyun YongHyeon 	if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) {
2738ebb25bfaSPyun YongHyeon 		if ((sc_if->msk_flags & MSK_FLAG_AUTOTX_CSUM) != 0)
2739262e9dcfSPyun YongHyeon 			control |= CALSUM;
2740262e9dcfSPyun YongHyeon 		else {
27411b7757c0SPyun YongHyeon 			control |= CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
27420dbe28b3SPyun YongHyeon 			if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0)
27430dbe28b3SPyun YongHyeon 				control |= UDPTCP;
27441b7757c0SPyun YongHyeon 			/* Checksum write position. */
27451b7757c0SPyun YongHyeon 			csum = (tcp_offset + m->m_pkthdr.csum_data) & 0xffff;
27461b7757c0SPyun YongHyeon 			/* Checksum start position. */
27471b7757c0SPyun YongHyeon 			csum |= (uint32_t)tcp_offset << 16;
27481b7757c0SPyun YongHyeon 			if (csum != sc_if->msk_cdata.msk_last_csum) {
27491b7757c0SPyun YongHyeon 				tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
27501b7757c0SPyun YongHyeon 				tx_le->msk_addr = htole32(csum);
27511b7757c0SPyun YongHyeon 				tx_le->msk_control = htole32(1 << 16 |
27521b7757c0SPyun YongHyeon 				    (OP_TCPLISW | HW_OWNER));
27530dbe28b3SPyun YongHyeon 				sc_if->msk_cdata.msk_tx_cnt++;
27540dbe28b3SPyun YongHyeon 				MSK_INC(prod, MSK_TX_RING_CNT);
27551b7757c0SPyun YongHyeon 				sc_if->msk_cdata.msk_last_csum = csum;
27561b7757c0SPyun YongHyeon 			}
27570dbe28b3SPyun YongHyeon 		}
2758262e9dcfSPyun YongHyeon 	}
27590dbe28b3SPyun YongHyeon 
27600dbe28b3SPyun YongHyeon 	si = prod;
27610dbe28b3SPyun YongHyeon 	tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
27620dbe28b3SPyun YongHyeon 	tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr));
27630dbe28b3SPyun YongHyeon 	if (tso == 0)
27640dbe28b3SPyun YongHyeon 		tx_le->msk_control = htole32(txsegs[0].ds_len | control |
27650dbe28b3SPyun YongHyeon 		    OP_PACKET);
27660dbe28b3SPyun YongHyeon 	else
27670dbe28b3SPyun YongHyeon 		tx_le->msk_control = htole32(txsegs[0].ds_len | control |
27680dbe28b3SPyun YongHyeon 		    OP_LARGESEND);
27690dbe28b3SPyun YongHyeon 	sc_if->msk_cdata.msk_tx_cnt++;
27700dbe28b3SPyun YongHyeon 	MSK_INC(prod, MSK_TX_RING_CNT);
27710dbe28b3SPyun YongHyeon 
27720dbe28b3SPyun YongHyeon 	for (i = 1; i < nseg; i++) {
27730dbe28b3SPyun YongHyeon 		tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
27740dbe28b3SPyun YongHyeon 		tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr));
27750dbe28b3SPyun YongHyeon 		tx_le->msk_control = htole32(txsegs[i].ds_len | control |
27760dbe28b3SPyun YongHyeon 		    OP_BUFFER | HW_OWNER);
27770dbe28b3SPyun YongHyeon 		sc_if->msk_cdata.msk_tx_cnt++;
27780dbe28b3SPyun YongHyeon 		MSK_INC(prod, MSK_TX_RING_CNT);
27790dbe28b3SPyun YongHyeon 	}
27800dbe28b3SPyun YongHyeon 	/* Update producer index. */
27810dbe28b3SPyun YongHyeon 	sc_if->msk_cdata.msk_tx_prod = prod;
27820dbe28b3SPyun YongHyeon 
2783b1ce21c6SRebecca Cran 	/* Set EOP on the last descriptor. */
27840dbe28b3SPyun YongHyeon 	prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT;
27850dbe28b3SPyun YongHyeon 	tx_le = &sc_if->msk_rdata.msk_tx_ring[prod];
27860dbe28b3SPyun YongHyeon 	tx_le->msk_control |= htole32(EOP);
27870dbe28b3SPyun YongHyeon 
27880dbe28b3SPyun YongHyeon 	/* Turn the first descriptor ownership to hardware. */
27890dbe28b3SPyun YongHyeon 	tx_le = &sc_if->msk_rdata.msk_tx_ring[si];
27900dbe28b3SPyun YongHyeon 	tx_le->msk_control |= htole32(HW_OWNER);
27910dbe28b3SPyun YongHyeon 
27920dbe28b3SPyun YongHyeon 	txd = &sc_if->msk_cdata.msk_txdesc[prod];
27930dbe28b3SPyun YongHyeon 	map = txd_last->tx_dmamap;
27940dbe28b3SPyun YongHyeon 	txd_last->tx_dmamap = txd->tx_dmamap;
27950dbe28b3SPyun YongHyeon 	txd->tx_dmamap = map;
27960dbe28b3SPyun YongHyeon 	txd->tx_m = m;
27970dbe28b3SPyun YongHyeon 
27980dbe28b3SPyun YongHyeon 	/* Sync descriptors. */
27990dbe28b3SPyun YongHyeon 	bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE);
28000dbe28b3SPyun YongHyeon 	bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
28010dbe28b3SPyun YongHyeon 	    sc_if->msk_cdata.msk_tx_ring_map,
28020dbe28b3SPyun YongHyeon 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
28030dbe28b3SPyun YongHyeon 
28040dbe28b3SPyun YongHyeon 	return (0);
28050dbe28b3SPyun YongHyeon }
28060dbe28b3SPyun YongHyeon 
28070dbe28b3SPyun YongHyeon static void
2808c876b43fSPyun YongHyeon msk_start(struct ifnet *ifp)
28090dbe28b3SPyun YongHyeon {
2810c876b43fSPyun YongHyeon 	struct msk_if_softc *sc_if;
28110dbe28b3SPyun YongHyeon 
2812c876b43fSPyun YongHyeon 	sc_if = ifp->if_softc;
2813c876b43fSPyun YongHyeon 	MSK_IF_LOCK(sc_if);
2814c876b43fSPyun YongHyeon 	msk_start_locked(ifp);
2815c876b43fSPyun YongHyeon 	MSK_IF_UNLOCK(sc_if);
28160dbe28b3SPyun YongHyeon }
28170dbe28b3SPyun YongHyeon 
28180dbe28b3SPyun YongHyeon static void
2819c876b43fSPyun YongHyeon msk_start_locked(struct ifnet *ifp)
28200dbe28b3SPyun YongHyeon {
28210dbe28b3SPyun YongHyeon 	struct msk_if_softc *sc_if;
28220dbe28b3SPyun YongHyeon 	struct mbuf *m_head;
28230dbe28b3SPyun YongHyeon 	int enq;
28240dbe28b3SPyun YongHyeon 
28250dbe28b3SPyun YongHyeon 	sc_if = ifp->if_softc;
2826c876b43fSPyun YongHyeon 	MSK_IF_LOCK_ASSERT(sc_if);
28270dbe28b3SPyun YongHyeon 
28280dbe28b3SPyun YongHyeon 	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
2829c876b43fSPyun YongHyeon 	    IFF_DRV_RUNNING || (sc_if->msk_flags & MSK_FLAG_LINK) == 0)
28300dbe28b3SPyun YongHyeon 		return;
28310dbe28b3SPyun YongHyeon 
28320dbe28b3SPyun YongHyeon 	for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
28330dbe28b3SPyun YongHyeon 	    sc_if->msk_cdata.msk_tx_cnt <
28340dbe28b3SPyun YongHyeon 	    (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) {
28350dbe28b3SPyun YongHyeon 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
28360dbe28b3SPyun YongHyeon 		if (m_head == NULL)
28370dbe28b3SPyun YongHyeon 			break;
28380dbe28b3SPyun YongHyeon 		/*
28390dbe28b3SPyun YongHyeon 		 * Pack the data into the transmit ring. If we
28400dbe28b3SPyun YongHyeon 		 * don't have room, set the OACTIVE flag and wait
28410dbe28b3SPyun YongHyeon 		 * for the NIC to drain the ring.
28420dbe28b3SPyun YongHyeon 		 */
28430dbe28b3SPyun YongHyeon 		if (msk_encap(sc_if, &m_head) != 0) {
28440dbe28b3SPyun YongHyeon 			if (m_head == NULL)
28450dbe28b3SPyun YongHyeon 				break;
28460dbe28b3SPyun YongHyeon 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
28470dbe28b3SPyun YongHyeon 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
28480dbe28b3SPyun YongHyeon 			break;
28490dbe28b3SPyun YongHyeon 		}
28500dbe28b3SPyun YongHyeon 
28510dbe28b3SPyun YongHyeon 		enq++;
28520dbe28b3SPyun YongHyeon 		/*
28530dbe28b3SPyun YongHyeon 		 * If there's a BPF listener, bounce a copy of this frame
28540dbe28b3SPyun YongHyeon 		 * to him.
28550dbe28b3SPyun YongHyeon 		 */
285659a0d28bSChristian S.J. Peron 		ETHER_BPF_MTAP(ifp, m_head);
28570dbe28b3SPyun YongHyeon 	}
28580dbe28b3SPyun YongHyeon 
28590dbe28b3SPyun YongHyeon 	if (enq > 0) {
28600dbe28b3SPyun YongHyeon 		/* Transmit */
28610dbe28b3SPyun YongHyeon 		CSR_WRITE_2(sc_if->msk_softc,
28620dbe28b3SPyun YongHyeon 		    Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG),
28630dbe28b3SPyun YongHyeon 		    sc_if->msk_cdata.msk_tx_prod);
28640dbe28b3SPyun YongHyeon 
28650dbe28b3SPyun YongHyeon 		/* Set a timeout in case the chip goes out to lunch. */
28662271eac7SPyun YongHyeon 		sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT;
28670dbe28b3SPyun YongHyeon 	}
28680dbe28b3SPyun YongHyeon }
28690dbe28b3SPyun YongHyeon 
28700dbe28b3SPyun YongHyeon static void
28712271eac7SPyun YongHyeon msk_watchdog(struct msk_if_softc *sc_if)
28720dbe28b3SPyun YongHyeon {
28730dbe28b3SPyun YongHyeon 	struct ifnet *ifp;
28740dbe28b3SPyun YongHyeon 
28750dbe28b3SPyun YongHyeon 	MSK_IF_LOCK_ASSERT(sc_if);
28760dbe28b3SPyun YongHyeon 
28772271eac7SPyun YongHyeon 	if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer)
28782271eac7SPyun YongHyeon 		return;
28790dbe28b3SPyun YongHyeon 	ifp = sc_if->msk_ifp;
2880ab7df1e4SPyun YongHyeon 	if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0) {
28810dbe28b3SPyun YongHyeon 		if (bootverbose)
28820dbe28b3SPyun YongHyeon 			if_printf(sc_if->msk_ifp, "watchdog timeout "
28830dbe28b3SPyun YongHyeon 			   "(missed link)\n");
28840dbe28b3SPyun YongHyeon 		ifp->if_oerrors++;
288589e22666SPyun YongHyeon 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
28860dbe28b3SPyun YongHyeon 		msk_init_locked(sc_if);
28870dbe28b3SPyun YongHyeon 		return;
28880dbe28b3SPyun YongHyeon 	}
28890dbe28b3SPyun YongHyeon 
28900dbe28b3SPyun YongHyeon 	if_printf(ifp, "watchdog timeout\n");
28910dbe28b3SPyun YongHyeon 	ifp->if_oerrors++;
289289e22666SPyun YongHyeon 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
28930dbe28b3SPyun YongHyeon 	msk_init_locked(sc_if);
28940dbe28b3SPyun YongHyeon 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2895c876b43fSPyun YongHyeon 		msk_start_locked(ifp);
28960dbe28b3SPyun YongHyeon }
28970dbe28b3SPyun YongHyeon 
28986a087a87SPyun YongHyeon static int
28990dbe28b3SPyun YongHyeon mskc_shutdown(device_t dev)
29000dbe28b3SPyun YongHyeon {
29010dbe28b3SPyun YongHyeon 	struct msk_softc *sc;
29020dbe28b3SPyun YongHyeon 	int i;
29030dbe28b3SPyun YongHyeon 
29040dbe28b3SPyun YongHyeon 	sc = device_get_softc(dev);
29050dbe28b3SPyun YongHyeon 	MSK_LOCK(sc);
29060dbe28b3SPyun YongHyeon 	for (i = 0; i < sc->msk_num_port; i++) {
290731fefd0dSPyun YongHyeon 		if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
290831fefd0dSPyun YongHyeon 		    ((sc->msk_if[i]->msk_ifp->if_drv_flags &
290931fefd0dSPyun YongHyeon 		    IFF_DRV_RUNNING) != 0))
29100dbe28b3SPyun YongHyeon 			msk_stop(sc->msk_if[i]);
29110dbe28b3SPyun YongHyeon 	}
291231fefd0dSPyun YongHyeon 	MSK_UNLOCK(sc);
29130dbe28b3SPyun YongHyeon 
29140dbe28b3SPyun YongHyeon 	/* Put hardware reset. */
29150dbe28b3SPyun YongHyeon 	CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
29166a087a87SPyun YongHyeon 	return (0);
29170dbe28b3SPyun YongHyeon }
29180dbe28b3SPyun YongHyeon 
29190dbe28b3SPyun YongHyeon static int
29200dbe28b3SPyun YongHyeon mskc_suspend(device_t dev)
29210dbe28b3SPyun YongHyeon {
29220dbe28b3SPyun YongHyeon 	struct msk_softc *sc;
29230dbe28b3SPyun YongHyeon 	int i;
29240dbe28b3SPyun YongHyeon 
29250dbe28b3SPyun YongHyeon 	sc = device_get_softc(dev);
29260dbe28b3SPyun YongHyeon 
29270dbe28b3SPyun YongHyeon 	MSK_LOCK(sc);
29280dbe28b3SPyun YongHyeon 
29290dbe28b3SPyun YongHyeon 	for (i = 0; i < sc->msk_num_port; i++) {
29300dbe28b3SPyun YongHyeon 		if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
29310dbe28b3SPyun YongHyeon 		    ((sc->msk_if[i]->msk_ifp->if_drv_flags &
29320dbe28b3SPyun YongHyeon 		    IFF_DRV_RUNNING) != 0))
29330dbe28b3SPyun YongHyeon 			msk_stop(sc->msk_if[i]);
29340dbe28b3SPyun YongHyeon 	}
29350dbe28b3SPyun YongHyeon 
29360dbe28b3SPyun YongHyeon 	/* Disable all interrupts. */
29370dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, B0_IMSK, 0);
29380dbe28b3SPyun YongHyeon 	CSR_READ_4(sc, B0_IMSK);
29390dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, B0_HWE_IMSK, 0);
29400dbe28b3SPyun YongHyeon 	CSR_READ_4(sc, B0_HWE_IMSK);
29410dbe28b3SPyun YongHyeon 
29420dbe28b3SPyun YongHyeon 	msk_phy_power(sc, MSK_PHY_POWERDOWN);
29430dbe28b3SPyun YongHyeon 
29440dbe28b3SPyun YongHyeon 	/* Put hardware reset. */
29450dbe28b3SPyun YongHyeon 	CSR_WRITE_2(sc, B0_CTST, CS_RST_SET);
2946ab7df1e4SPyun YongHyeon 	sc->msk_pflags |= MSK_FLAG_SUSPEND;
29470dbe28b3SPyun YongHyeon 
29480dbe28b3SPyun YongHyeon 	MSK_UNLOCK(sc);
29490dbe28b3SPyun YongHyeon 
29500dbe28b3SPyun YongHyeon 	return (0);
29510dbe28b3SPyun YongHyeon }
29520dbe28b3SPyun YongHyeon 
29530dbe28b3SPyun YongHyeon static int
29540dbe28b3SPyun YongHyeon mskc_resume(device_t dev)
29550dbe28b3SPyun YongHyeon {
29560dbe28b3SPyun YongHyeon 	struct msk_softc *sc;
29570dbe28b3SPyun YongHyeon 	int i;
29580dbe28b3SPyun YongHyeon 
29590dbe28b3SPyun YongHyeon 	sc = device_get_softc(dev);
29600dbe28b3SPyun YongHyeon 
29610dbe28b3SPyun YongHyeon 	MSK_LOCK(sc);
29620dbe28b3SPyun YongHyeon 
2963*c6a34f76SPyun YongHyeon 	CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0);
29640dbe28b3SPyun YongHyeon 	mskc_reset(sc);
29650dbe28b3SPyun YongHyeon 	for (i = 0; i < sc->msk_num_port; i++) {
29660dbe28b3SPyun YongHyeon 		if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&
296789e22666SPyun YongHyeon 		    ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) {
296889e22666SPyun YongHyeon 			sc->msk_if[i]->msk_ifp->if_drv_flags &=
296989e22666SPyun YongHyeon 			    ~IFF_DRV_RUNNING;
29700dbe28b3SPyun YongHyeon 			msk_init_locked(sc->msk_if[i]);
29710dbe28b3SPyun YongHyeon 		}
297289e22666SPyun YongHyeon 	}
297340d6bed8SPyun YongHyeon 	sc->msk_pflags &= ~MSK_FLAG_SUSPEND;
29740dbe28b3SPyun YongHyeon 
29750dbe28b3SPyun YongHyeon 	MSK_UNLOCK(sc);
29760dbe28b3SPyun YongHyeon 
29770dbe28b3SPyun YongHyeon 	return (0);
29780dbe28b3SPyun YongHyeon }
29790dbe28b3SPyun YongHyeon 
298083c04c93SPyun YongHyeon #ifndef __NO_STRICT_ALIGNMENT
298183c04c93SPyun YongHyeon static __inline void
298283c04c93SPyun YongHyeon msk_fixup_rx(struct mbuf *m)
298383c04c93SPyun YongHyeon {
298483c04c93SPyun YongHyeon         int i;
298583c04c93SPyun YongHyeon         uint16_t *src, *dst;
298683c04c93SPyun YongHyeon 
298783c04c93SPyun YongHyeon 	src = mtod(m, uint16_t *);
298883c04c93SPyun YongHyeon 	dst = src - 3;
298983c04c93SPyun YongHyeon 
299083c04c93SPyun YongHyeon 	for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++)
299183c04c93SPyun YongHyeon 		*dst++ = *src++;
299283c04c93SPyun YongHyeon 
299383c04c93SPyun YongHyeon 	m->m_data -= (MSK_RX_BUF_ALIGN - ETHER_ALIGN);
299483c04c93SPyun YongHyeon }
299583c04c93SPyun YongHyeon #endif
299683c04c93SPyun YongHyeon 
2997388214e4SPyun YongHyeon static __inline void
2998388214e4SPyun YongHyeon msk_rxcsum(struct msk_if_softc *sc_if, uint32_t control, struct mbuf *m)
2999388214e4SPyun YongHyeon {
3000388214e4SPyun YongHyeon 	struct ether_header *eh;
3001388214e4SPyun YongHyeon 	struct ip *ip;
3002388214e4SPyun YongHyeon 	struct udphdr *uh;
3003388214e4SPyun YongHyeon 	int32_t hlen, len, pktlen, temp32;
3004388214e4SPyun YongHyeon 	uint16_t csum, *opts;
3005388214e4SPyun YongHyeon 
3006388214e4SPyun YongHyeon 	if ((sc_if->msk_flags & MSK_FLAG_DESCV2) != 0) {
3007388214e4SPyun YongHyeon 		if ((control & (CSS_IPV4 | CSS_IPFRAG)) == CSS_IPV4) {
3008388214e4SPyun YongHyeon 			m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
3009388214e4SPyun YongHyeon 			if ((control & CSS_IPV4_CSUM_OK) != 0)
3010388214e4SPyun YongHyeon 				m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
3011388214e4SPyun YongHyeon 			if ((control & (CSS_TCP | CSS_UDP)) != 0 &&
3012388214e4SPyun YongHyeon 			    (control & (CSS_TCPUDP_CSUM_OK)) != 0) {
3013388214e4SPyun YongHyeon 				m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
3014388214e4SPyun YongHyeon 				    CSUM_PSEUDO_HDR;
3015388214e4SPyun YongHyeon 				m->m_pkthdr.csum_data = 0xffff;
3016388214e4SPyun YongHyeon 			}
3017388214e4SPyun YongHyeon 		}
3018388214e4SPyun YongHyeon 		return;
3019388214e4SPyun YongHyeon 	}
3020388214e4SPyun YongHyeon 	/*
3021388214e4SPyun YongHyeon 	 * Marvell Yukon controllers that support OP_RXCHKS has known
3022388214e4SPyun YongHyeon 	 * to have various Rx checksum offloading bugs. These
3023388214e4SPyun YongHyeon 	 * controllers can be configured to compute simple checksum
3024388214e4SPyun YongHyeon 	 * at two different positions. So we can compute IP and TCP/UDP
3025388214e4SPyun YongHyeon 	 * checksum at the same time. We intentionally have controller
3026388214e4SPyun YongHyeon 	 * compute TCP/UDP checksum twice by specifying the same
3027388214e4SPyun YongHyeon 	 * checksum start position and compare the result. If the value
3028388214e4SPyun YongHyeon 	 * is different it would indicate the hardware logic was wrong.
3029388214e4SPyun YongHyeon 	 */
3030388214e4SPyun YongHyeon 	if ((sc_if->msk_csum & 0xFFFF) != (sc_if->msk_csum >> 16)) {
3031388214e4SPyun YongHyeon 		if (bootverbose)
3032388214e4SPyun YongHyeon 			device_printf(sc_if->msk_if_dev,
3033388214e4SPyun YongHyeon 			    "Rx checksum value mismatch!\n");
3034388214e4SPyun YongHyeon 		return;
3035388214e4SPyun YongHyeon 	}
3036388214e4SPyun YongHyeon 	pktlen = m->m_pkthdr.len;
3037388214e4SPyun YongHyeon 	if (pktlen < sizeof(struct ether_header) + sizeof(struct ip))
3038388214e4SPyun YongHyeon 		return;
3039388214e4SPyun YongHyeon 	eh = mtod(m, struct ether_header *);
3040388214e4SPyun YongHyeon 	if (eh->ether_type != htons(ETHERTYPE_IP))
3041388214e4SPyun YongHyeon 		return;
3042388214e4SPyun YongHyeon 	ip = (struct ip *)(eh + 1);
3043388214e4SPyun YongHyeon 	if (ip->ip_v != IPVERSION)
3044388214e4SPyun YongHyeon 		return;
3045388214e4SPyun YongHyeon 
3046388214e4SPyun YongHyeon 	hlen = ip->ip_hl << 2;
3047388214e4SPyun YongHyeon 	pktlen -= sizeof(struct ether_header);
3048388214e4SPyun YongHyeon 	if (hlen < sizeof(struct ip))
3049388214e4SPyun YongHyeon 		return;
3050388214e4SPyun YongHyeon 	if (ntohs(ip->ip_len) < hlen)
3051388214e4SPyun YongHyeon 		return;
3052388214e4SPyun YongHyeon 	if (ntohs(ip->ip_len) != pktlen)
3053388214e4SPyun YongHyeon 		return;
3054388214e4SPyun YongHyeon 	if (ip->ip_off & htons(IP_MF | IP_OFFMASK))
3055388214e4SPyun YongHyeon 		return;	/* can't handle fragmented packet. */
3056388214e4SPyun YongHyeon 
3057388214e4SPyun YongHyeon 	switch (ip->ip_p) {
3058388214e4SPyun YongHyeon 	case IPPROTO_TCP:
3059388214e4SPyun YongHyeon 		if (pktlen < (hlen + sizeof(struct tcphdr)))
3060388214e4SPyun YongHyeon 			return;
3061388214e4SPyun YongHyeon 		break;
3062388214e4SPyun YongHyeon 	case IPPROTO_UDP:
3063388214e4SPyun YongHyeon 		if (pktlen < (hlen + sizeof(struct udphdr)))
3064388214e4SPyun YongHyeon 			return;
3065388214e4SPyun YongHyeon 		uh = (struct udphdr *)((caddr_t)ip + hlen);
3066388214e4SPyun YongHyeon 		if (uh->uh_sum == 0)
3067388214e4SPyun YongHyeon 			return; /* no checksum */
3068388214e4SPyun YongHyeon 		break;
3069388214e4SPyun YongHyeon 	default:
3070388214e4SPyun YongHyeon 		return;
3071388214e4SPyun YongHyeon 	}
30723c5571b3SPyun YongHyeon 	csum = bswap16(sc_if->msk_csum & 0xFFFF);
3073388214e4SPyun YongHyeon 	/* Checksum fixup for IP options. */
3074388214e4SPyun YongHyeon 	len = hlen - sizeof(struct ip);
3075388214e4SPyun YongHyeon 	if (len > 0) {
3076388214e4SPyun YongHyeon 		opts = (uint16_t *)(ip + 1);
3077388214e4SPyun YongHyeon 		for (; len > 0; len -= sizeof(uint16_t), opts++) {
3078388214e4SPyun YongHyeon 			temp32 = csum - *opts;
3079388214e4SPyun YongHyeon 			temp32 = (temp32 >> 16) + (temp32 & 65535);
3080388214e4SPyun YongHyeon 			csum = temp32 & 65535;
3081388214e4SPyun YongHyeon 		}
3082388214e4SPyun YongHyeon 	}
3083388214e4SPyun YongHyeon 	m->m_pkthdr.csum_flags |= CSUM_DATA_VALID;
3084388214e4SPyun YongHyeon 	m->m_pkthdr.csum_data = csum;
3085388214e4SPyun YongHyeon }
3086388214e4SPyun YongHyeon 
30870dbe28b3SPyun YongHyeon static void
3088efb74172SPyun YongHyeon msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control,
3089efb74172SPyun YongHyeon     int len)
30900dbe28b3SPyun YongHyeon {
30910dbe28b3SPyun YongHyeon 	struct mbuf *m;
30920dbe28b3SPyun YongHyeon 	struct ifnet *ifp;
30930dbe28b3SPyun YongHyeon 	struct msk_rxdesc *rxd;
30940dbe28b3SPyun YongHyeon 	int cons, rxlen;
30950dbe28b3SPyun YongHyeon 
30960dbe28b3SPyun YongHyeon 	ifp = sc_if->msk_ifp;
30970dbe28b3SPyun YongHyeon 
30980dbe28b3SPyun YongHyeon 	MSK_IF_LOCK_ASSERT(sc_if);
30990dbe28b3SPyun YongHyeon 
31000dbe28b3SPyun YongHyeon 	cons = sc_if->msk_cdata.msk_rx_cons;
31010dbe28b3SPyun YongHyeon 	do {
31020dbe28b3SPyun YongHyeon 		rxlen = status >> 16;
310371e88667SPyun YongHyeon 		if ((status & GMR_FS_VLAN) != 0 &&
310471e88667SPyun YongHyeon 		    (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
31050dbe28b3SPyun YongHyeon 			rxlen -= ETHER_VLAN_ENCAP_LEN;
3106224003b7SPyun YongHyeon 		if ((sc_if->msk_flags & MSK_FLAG_NORXCHK) != 0) {
3107224003b7SPyun YongHyeon 			/*
3108224003b7SPyun YongHyeon 			 * For controllers that returns bogus status code
3109224003b7SPyun YongHyeon 			 * just do minimal check and let upper stack
3110224003b7SPyun YongHyeon 			 * handle this frame.
3111224003b7SPyun YongHyeon 			 */
3112224003b7SPyun YongHyeon 			if (len > MSK_MAX_FRAMELEN || len < ETHER_HDR_LEN) {
3113224003b7SPyun YongHyeon 				ifp->if_ierrors++;
3114224003b7SPyun YongHyeon 				msk_discard_rxbuf(sc_if, cons);
3115224003b7SPyun YongHyeon 				break;
3116224003b7SPyun YongHyeon 			}
3117224003b7SPyun YongHyeon 		} else if (len > sc_if->msk_framesize ||
31180dbe28b3SPyun YongHyeon 		    ((status & GMR_FS_ANY_ERR) != 0) ||
31190dbe28b3SPyun YongHyeon 		    ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
31200dbe28b3SPyun YongHyeon 			/* Don't count flow-control packet as errors. */
31210dbe28b3SPyun YongHyeon 			if ((status & GMR_FS_GOOD_FC) == 0)
31220dbe28b3SPyun YongHyeon 				ifp->if_ierrors++;
31230dbe28b3SPyun YongHyeon 			msk_discard_rxbuf(sc_if, cons);
31240dbe28b3SPyun YongHyeon 			break;
31250dbe28b3SPyun YongHyeon 		}
31260dbe28b3SPyun YongHyeon 		rxd = &sc_if->msk_cdata.msk_rxdesc[cons];
31270dbe28b3SPyun YongHyeon 		m = rxd->rx_m;
31280dbe28b3SPyun YongHyeon 		if (msk_newbuf(sc_if, cons) != 0) {
31290dbe28b3SPyun YongHyeon 			ifp->if_iqdrops++;
31300dbe28b3SPyun YongHyeon 			/* Reuse old buffer. */
31310dbe28b3SPyun YongHyeon 			msk_discard_rxbuf(sc_if, cons);
31320dbe28b3SPyun YongHyeon 			break;
31330dbe28b3SPyun YongHyeon 		}
31340dbe28b3SPyun YongHyeon 		m->m_pkthdr.rcvif = ifp;
31350dbe28b3SPyun YongHyeon 		m->m_pkthdr.len = m->m_len = len;
313683c04c93SPyun YongHyeon #ifndef __NO_STRICT_ALIGNMENT
313783c04c93SPyun YongHyeon 		if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
313883c04c93SPyun YongHyeon 			msk_fixup_rx(m);
313983c04c93SPyun YongHyeon #endif
31400dbe28b3SPyun YongHyeon 		ifp->if_ipackets++;
3141388214e4SPyun YongHyeon 		if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
3142388214e4SPyun YongHyeon 			msk_rxcsum(sc_if, control, m);
31430dbe28b3SPyun YongHyeon 		/* Check for VLAN tagged packets. */
31440dbe28b3SPyun YongHyeon 		if ((status & GMR_FS_VLAN) != 0 &&
31450dbe28b3SPyun YongHyeon 		    (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
31460dbe28b3SPyun YongHyeon 			m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
31470dbe28b3SPyun YongHyeon 			m->m_flags |= M_VLANTAG;
31480dbe28b3SPyun YongHyeon 		}
31490dbe28b3SPyun YongHyeon 		MSK_IF_UNLOCK(sc_if);
31500dbe28b3SPyun YongHyeon 		(*ifp->if_input)(ifp, m);
31510dbe28b3SPyun YongHyeon 		MSK_IF_LOCK(sc_if);
31520dbe28b3SPyun YongHyeon 	} while (0);
31530dbe28b3SPyun YongHyeon 
31540dbe28b3SPyun YongHyeon 	MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT);
31550dbe28b3SPyun YongHyeon 	MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT);
31560dbe28b3SPyun YongHyeon }
31570dbe28b3SPyun YongHyeon 
31580dbe28b3SPyun YongHyeon static void
3159efb74172SPyun YongHyeon msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, uint32_t control,
3160efb74172SPyun YongHyeon     int len)
31610dbe28b3SPyun YongHyeon {
31620dbe28b3SPyun YongHyeon 	struct mbuf *m;
31630dbe28b3SPyun YongHyeon 	struct ifnet *ifp;
31640dbe28b3SPyun YongHyeon 	struct msk_rxdesc *jrxd;
31650dbe28b3SPyun YongHyeon 	int cons, rxlen;
31660dbe28b3SPyun YongHyeon 
31670dbe28b3SPyun YongHyeon 	ifp = sc_if->msk_ifp;
31680dbe28b3SPyun YongHyeon 
31690dbe28b3SPyun YongHyeon 	MSK_IF_LOCK_ASSERT(sc_if);
31700dbe28b3SPyun YongHyeon 
31710dbe28b3SPyun YongHyeon 	cons = sc_if->msk_cdata.msk_rx_cons;
31720dbe28b3SPyun YongHyeon 	do {
31730dbe28b3SPyun YongHyeon 		rxlen = status >> 16;
317471e88667SPyun YongHyeon 		if ((status & GMR_FS_VLAN) != 0 &&
317571e88667SPyun YongHyeon 		    (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
31760dbe28b3SPyun YongHyeon 			rxlen -= ETHER_VLAN_ENCAP_LEN;
31770dbe28b3SPyun YongHyeon 		if (len > sc_if->msk_framesize ||
31780dbe28b3SPyun YongHyeon 		    ((status & GMR_FS_ANY_ERR) != 0) ||
31790dbe28b3SPyun YongHyeon 		    ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) {
31800dbe28b3SPyun YongHyeon 			/* Don't count flow-control packet as errors. */
31810dbe28b3SPyun YongHyeon 			if ((status & GMR_FS_GOOD_FC) == 0)
31820dbe28b3SPyun YongHyeon 				ifp->if_ierrors++;
31830dbe28b3SPyun YongHyeon 			msk_discard_jumbo_rxbuf(sc_if, cons);
31840dbe28b3SPyun YongHyeon 			break;
31850dbe28b3SPyun YongHyeon 		}
31860dbe28b3SPyun YongHyeon 		jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons];
31870dbe28b3SPyun YongHyeon 		m = jrxd->rx_m;
31880dbe28b3SPyun YongHyeon 		if (msk_jumbo_newbuf(sc_if, cons) != 0) {
31890dbe28b3SPyun YongHyeon 			ifp->if_iqdrops++;
31900dbe28b3SPyun YongHyeon 			/* Reuse old buffer. */
31910dbe28b3SPyun YongHyeon 			msk_discard_jumbo_rxbuf(sc_if, cons);
31920dbe28b3SPyun YongHyeon 			break;
31930dbe28b3SPyun YongHyeon 		}
31940dbe28b3SPyun YongHyeon 		m->m_pkthdr.rcvif = ifp;
31950dbe28b3SPyun YongHyeon 		m->m_pkthdr.len = m->m_len = len;
319683c04c93SPyun YongHyeon #ifndef __NO_STRICT_ALIGNMENT
319783c04c93SPyun YongHyeon 		if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) != 0)
319883c04c93SPyun YongHyeon 			msk_fixup_rx(m);
319983c04c93SPyun YongHyeon #endif
32000dbe28b3SPyun YongHyeon 		ifp->if_ipackets++;
3201388214e4SPyun YongHyeon 		if ((ifp->if_capenable & IFCAP_RXCSUM) != 0)
3202388214e4SPyun YongHyeon 			msk_rxcsum(sc_if, control, m);
32030dbe28b3SPyun YongHyeon 		/* Check for VLAN tagged packets. */
32040dbe28b3SPyun YongHyeon 		if ((status & GMR_FS_VLAN) != 0 &&
32050dbe28b3SPyun YongHyeon 		    (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) {
32060dbe28b3SPyun YongHyeon 			m->m_pkthdr.ether_vtag = sc_if->msk_vtag;
32070dbe28b3SPyun YongHyeon 			m->m_flags |= M_VLANTAG;
32080dbe28b3SPyun YongHyeon 		}
32090dbe28b3SPyun YongHyeon 		MSK_IF_UNLOCK(sc_if);
32100dbe28b3SPyun YongHyeon 		(*ifp->if_input)(ifp, m);
32110dbe28b3SPyun YongHyeon 		MSK_IF_LOCK(sc_if);
32120dbe28b3SPyun YongHyeon 	} while (0);
32130dbe28b3SPyun YongHyeon 
32140dbe28b3SPyun YongHyeon 	MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT);
32150dbe28b3SPyun YongHyeon 	MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT);
32160dbe28b3SPyun YongHyeon }
32170dbe28b3SPyun YongHyeon 
32180dbe28b3SPyun YongHyeon static void
32190dbe28b3SPyun YongHyeon msk_txeof(struct msk_if_softc *sc_if, int idx)
32200dbe28b3SPyun YongHyeon {
32210dbe28b3SPyun YongHyeon 	struct msk_txdesc *txd;
32220dbe28b3SPyun YongHyeon 	struct msk_tx_desc *cur_tx;
32230dbe28b3SPyun YongHyeon 	struct ifnet *ifp;
32240dbe28b3SPyun YongHyeon 	uint32_t control;
32250dbe28b3SPyun YongHyeon 	int cons, prog;
32260dbe28b3SPyun YongHyeon 
32270dbe28b3SPyun YongHyeon 	MSK_IF_LOCK_ASSERT(sc_if);
32280dbe28b3SPyun YongHyeon 
32290dbe28b3SPyun YongHyeon 	ifp = sc_if->msk_ifp;
32300dbe28b3SPyun YongHyeon 
32310dbe28b3SPyun YongHyeon 	bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag,
32320dbe28b3SPyun YongHyeon 	    sc_if->msk_cdata.msk_tx_ring_map,
32330dbe28b3SPyun YongHyeon 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
32340dbe28b3SPyun YongHyeon 	/*
32350dbe28b3SPyun YongHyeon 	 * Go through our tx ring and free mbufs for those
32360dbe28b3SPyun YongHyeon 	 * frames that have been sent.
32370dbe28b3SPyun YongHyeon 	 */
32380dbe28b3SPyun YongHyeon 	cons = sc_if->msk_cdata.msk_tx_cons;
32390dbe28b3SPyun YongHyeon 	prog = 0;
32400dbe28b3SPyun YongHyeon 	for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) {
32410dbe28b3SPyun YongHyeon 		if (sc_if->msk_cdata.msk_tx_cnt <= 0)
32420dbe28b3SPyun YongHyeon 			break;
32430dbe28b3SPyun YongHyeon 		prog++;
32440dbe28b3SPyun YongHyeon 		cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons];
32450dbe28b3SPyun YongHyeon 		control = le32toh(cur_tx->msk_control);
32460dbe28b3SPyun YongHyeon 		sc_if->msk_cdata.msk_tx_cnt--;
32470dbe28b3SPyun YongHyeon 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
32480dbe28b3SPyun YongHyeon 		if ((control & EOP) == 0)
32490dbe28b3SPyun YongHyeon 			continue;
32500dbe28b3SPyun YongHyeon 		txd = &sc_if->msk_cdata.msk_txdesc[cons];
32510dbe28b3SPyun YongHyeon 		bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap,
32520dbe28b3SPyun YongHyeon 		    BUS_DMASYNC_POSTWRITE);
32530dbe28b3SPyun YongHyeon 		bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap);
32540dbe28b3SPyun YongHyeon 
32550dbe28b3SPyun YongHyeon 		ifp->if_opackets++;
32560dbe28b3SPyun YongHyeon 		KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!",
32570dbe28b3SPyun YongHyeon 		    __func__));
32580dbe28b3SPyun YongHyeon 		m_freem(txd->tx_m);
32590dbe28b3SPyun YongHyeon 		txd->tx_m = NULL;
32600dbe28b3SPyun YongHyeon 	}
32610dbe28b3SPyun YongHyeon 
32620dbe28b3SPyun YongHyeon 	if (prog > 0) {
32630dbe28b3SPyun YongHyeon 		sc_if->msk_cdata.msk_tx_cons = cons;
32640dbe28b3SPyun YongHyeon 		if (sc_if->msk_cdata.msk_tx_cnt == 0)
32652271eac7SPyun YongHyeon 			sc_if->msk_watchdog_timer = 0;
32660dbe28b3SPyun YongHyeon 		/* No need to sync LEs as we didn't update LEs. */
32670dbe28b3SPyun YongHyeon 	}
32680dbe28b3SPyun YongHyeon }
32690dbe28b3SPyun YongHyeon 
32700dbe28b3SPyun YongHyeon static void
32710dbe28b3SPyun YongHyeon msk_tick(void *xsc_if)
32720dbe28b3SPyun YongHyeon {
32730dbe28b3SPyun YongHyeon 	struct msk_if_softc *sc_if;
32740dbe28b3SPyun YongHyeon 	struct mii_data *mii;
32750dbe28b3SPyun YongHyeon 
32760dbe28b3SPyun YongHyeon 	sc_if = xsc_if;
32770dbe28b3SPyun YongHyeon 
32780dbe28b3SPyun YongHyeon 	MSK_IF_LOCK_ASSERT(sc_if);
32790dbe28b3SPyun YongHyeon 
32800dbe28b3SPyun YongHyeon 	mii = device_get_softc(sc_if->msk_miibus);
32810dbe28b3SPyun YongHyeon 
32820dbe28b3SPyun YongHyeon 	mii_tick(mii);
328377e6010fSPyun YongHyeon 	if ((sc_if->msk_flags & MSK_FLAG_LINK) == 0)
328477e6010fSPyun YongHyeon 		msk_miibus_statchg(sc_if->msk_if_dev);
3285cf570c1fSPyun YongHyeon 	msk_handle_events(sc_if->msk_softc);
32862271eac7SPyun YongHyeon 	msk_watchdog(sc_if);
32870dbe28b3SPyun YongHyeon 	callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
32880dbe28b3SPyun YongHyeon }
32890dbe28b3SPyun YongHyeon 
32900dbe28b3SPyun YongHyeon static void
32910dbe28b3SPyun YongHyeon msk_intr_phy(struct msk_if_softc *sc_if)
32920dbe28b3SPyun YongHyeon {
32930dbe28b3SPyun YongHyeon 	uint16_t status;
32940dbe28b3SPyun YongHyeon 
32950dbe28b3SPyun YongHyeon 	msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
3296431e606dSPyun YongHyeon 	status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT);
32970dbe28b3SPyun YongHyeon 	/* Handle FIFO Underrun/Overflow? */
32980dbe28b3SPyun YongHyeon 	if ((status & PHY_M_IS_FIFO_ERROR))
32990dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev,
33000dbe28b3SPyun YongHyeon 		    "PHY FIFO underrun/overflow.\n");
33010dbe28b3SPyun YongHyeon }
33020dbe28b3SPyun YongHyeon 
33030dbe28b3SPyun YongHyeon static void
33040dbe28b3SPyun YongHyeon msk_intr_gmac(struct msk_if_softc *sc_if)
33050dbe28b3SPyun YongHyeon {
33060dbe28b3SPyun YongHyeon 	struct msk_softc *sc;
33070dbe28b3SPyun YongHyeon 	uint8_t status;
33080dbe28b3SPyun YongHyeon 
33090dbe28b3SPyun YongHyeon 	sc = sc_if->msk_softc;
33100dbe28b3SPyun YongHyeon 	status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
33110dbe28b3SPyun YongHyeon 
33120dbe28b3SPyun YongHyeon 	/* GMAC Rx FIFO overrun. */
3313ff080216SPyun YongHyeon 	if ((status & GM_IS_RX_FF_OR) != 0)
33140dbe28b3SPyun YongHyeon 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
33150dbe28b3SPyun YongHyeon 		    GMF_CLI_RX_FO);
33160dbe28b3SPyun YongHyeon 	/* GMAC Tx FIFO underrun. */
33170dbe28b3SPyun YongHyeon 	if ((status & GM_IS_TX_FF_UR) != 0) {
33180dbe28b3SPyun YongHyeon 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
33190dbe28b3SPyun YongHyeon 		    GMF_CLI_TX_FU);
33200dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n");
33210dbe28b3SPyun YongHyeon 		/*
33220dbe28b3SPyun YongHyeon 		 * XXX
33230dbe28b3SPyun YongHyeon 		 * In case of Tx underrun, we may need to flush/reset
33240dbe28b3SPyun YongHyeon 		 * Tx MAC but that would also require resynchronization
3325b1ce21c6SRebecca Cran 		 * with status LEs. Reinitializing status LEs would
33260dbe28b3SPyun YongHyeon 		 * affect other port in dual MAC configuration so it
33270dbe28b3SPyun YongHyeon 		 * should be avoided as possible as we can.
33280dbe28b3SPyun YongHyeon 		 * Due to lack of documentation it's all vague guess but
33290dbe28b3SPyun YongHyeon 		 * it needs more investigation.
33300dbe28b3SPyun YongHyeon 		 */
33310dbe28b3SPyun YongHyeon 	}
33320dbe28b3SPyun YongHyeon }
33330dbe28b3SPyun YongHyeon 
33340dbe28b3SPyun YongHyeon static void
33350dbe28b3SPyun YongHyeon msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status)
33360dbe28b3SPyun YongHyeon {
33370dbe28b3SPyun YongHyeon 	struct msk_softc *sc;
33380dbe28b3SPyun YongHyeon 
33390dbe28b3SPyun YongHyeon 	sc = sc_if->msk_softc;
33400dbe28b3SPyun YongHyeon 	if ((status & Y2_IS_PAR_RD1) != 0) {
33410dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev,
33420dbe28b3SPyun YongHyeon 		    "RAM buffer read parity error\n");
33430dbe28b3SPyun YongHyeon 		/* Clear IRQ. */
33440dbe28b3SPyun YongHyeon 		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
33450dbe28b3SPyun YongHyeon 		    RI_CLR_RD_PERR);
33460dbe28b3SPyun YongHyeon 	}
33470dbe28b3SPyun YongHyeon 	if ((status & Y2_IS_PAR_WR1) != 0) {
33480dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev,
33490dbe28b3SPyun YongHyeon 		    "RAM buffer write parity error\n");
33500dbe28b3SPyun YongHyeon 		/* Clear IRQ. */
33510dbe28b3SPyun YongHyeon 		CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL),
33520dbe28b3SPyun YongHyeon 		    RI_CLR_WR_PERR);
33530dbe28b3SPyun YongHyeon 	}
33540dbe28b3SPyun YongHyeon 	if ((status & Y2_IS_PAR_MAC1) != 0) {
33550dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n");
33560dbe28b3SPyun YongHyeon 		/* Clear IRQ. */
33570dbe28b3SPyun YongHyeon 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
33580dbe28b3SPyun YongHyeon 		    GMF_CLI_TX_PE);
33590dbe28b3SPyun YongHyeon 	}
33600dbe28b3SPyun YongHyeon 	if ((status & Y2_IS_PAR_RX1) != 0) {
33610dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev, "Rx parity error\n");
33620dbe28b3SPyun YongHyeon 		/* Clear IRQ. */
33630dbe28b3SPyun YongHyeon 		CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR);
33640dbe28b3SPyun YongHyeon 	}
33650dbe28b3SPyun YongHyeon 	if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) {
33660dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev, "TCP segmentation error\n");
33670dbe28b3SPyun YongHyeon 		/* Clear IRQ. */
33680dbe28b3SPyun YongHyeon 		CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP);
33690dbe28b3SPyun YongHyeon 	}
33700dbe28b3SPyun YongHyeon }
33710dbe28b3SPyun YongHyeon 
33720dbe28b3SPyun YongHyeon static void
33730dbe28b3SPyun YongHyeon msk_intr_hwerr(struct msk_softc *sc)
33740dbe28b3SPyun YongHyeon {
33750dbe28b3SPyun YongHyeon 	uint32_t status;
33760dbe28b3SPyun YongHyeon 	uint32_t tlphead[4];
33770dbe28b3SPyun YongHyeon 
33780dbe28b3SPyun YongHyeon 	status = CSR_READ_4(sc, B0_HWE_ISRC);
33790dbe28b3SPyun YongHyeon 	/* Time Stamp timer overflow. */
33800dbe28b3SPyun YongHyeon 	if ((status & Y2_IS_TIST_OV) != 0)
33810dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
33820dbe28b3SPyun YongHyeon 	if ((status & Y2_IS_PCI_NEXP) != 0) {
33830dbe28b3SPyun YongHyeon 		/*
33840dbe28b3SPyun YongHyeon 		 * PCI Express Error occured which is not described in PEX
33850dbe28b3SPyun YongHyeon 		 * spec.
33860dbe28b3SPyun YongHyeon 		 * This error is also mapped either to Master Abort(
33870dbe28b3SPyun YongHyeon 		 * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and
33880dbe28b3SPyun YongHyeon 		 * can only be cleared there.
33890dbe28b3SPyun YongHyeon                  */
33900dbe28b3SPyun YongHyeon 		device_printf(sc->msk_dev,
33910dbe28b3SPyun YongHyeon 		    "PCI Express protocol violation error\n");
33920dbe28b3SPyun YongHyeon 	}
33930dbe28b3SPyun YongHyeon 
33940dbe28b3SPyun YongHyeon 	if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) {
33950dbe28b3SPyun YongHyeon 		uint16_t v16;
33960dbe28b3SPyun YongHyeon 
33970dbe28b3SPyun YongHyeon 		if ((status & Y2_IS_MST_ERR) != 0)
33980dbe28b3SPyun YongHyeon 			device_printf(sc->msk_dev,
33990dbe28b3SPyun YongHyeon 			    "unexpected IRQ Status error\n");
34000dbe28b3SPyun YongHyeon 		else
34010dbe28b3SPyun YongHyeon 			device_printf(sc->msk_dev,
34020dbe28b3SPyun YongHyeon 			    "unexpected IRQ Master error\n");
34030dbe28b3SPyun YongHyeon 		/* Reset all bits in the PCI status register. */
34040dbe28b3SPyun YongHyeon 		v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2);
34050dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
34060dbe28b3SPyun YongHyeon 		pci_write_config(sc->msk_dev, PCIR_STATUS, v16 |
34070dbe28b3SPyun YongHyeon 		    PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT |
3408d1a02e09SJohn Baldwin 		    PCIM_STATUS_RTABORT | PCIM_STATUS_MDPERR, 2);
34090dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
34100dbe28b3SPyun YongHyeon 	}
34110dbe28b3SPyun YongHyeon 
34120dbe28b3SPyun YongHyeon 	/* Check for PCI Express Uncorrectable Error. */
34130dbe28b3SPyun YongHyeon 	if ((status & Y2_IS_PCI_EXP) != 0) {
34140dbe28b3SPyun YongHyeon 		uint32_t v32;
34150dbe28b3SPyun YongHyeon 
34160dbe28b3SPyun YongHyeon 		/*
34170dbe28b3SPyun YongHyeon 		 * On PCI Express bus bridges are called root complexes (RC).
34180dbe28b3SPyun YongHyeon 		 * PCI Express errors are recognized by the root complex too,
34190dbe28b3SPyun YongHyeon 		 * which requests the system to handle the problem. After
34200dbe28b3SPyun YongHyeon 		 * error occurence it may be that no access to the adapter
34210dbe28b3SPyun YongHyeon 		 * may be performed any longer.
34220dbe28b3SPyun YongHyeon 		 */
34230dbe28b3SPyun YongHyeon 
34240dbe28b3SPyun YongHyeon 		v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT);
34250dbe28b3SPyun YongHyeon 		if ((v32 & PEX_UNSUP_REQ) != 0) {
34260dbe28b3SPyun YongHyeon 			/* Ignore unsupported request error. */
34270dbe28b3SPyun YongHyeon 			device_printf(sc->msk_dev,
34280dbe28b3SPyun YongHyeon 			    "Uncorrectable PCI Express error\n");
34290dbe28b3SPyun YongHyeon 		}
34300dbe28b3SPyun YongHyeon 		if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) {
34310dbe28b3SPyun YongHyeon 			int i;
34320dbe28b3SPyun YongHyeon 
34330dbe28b3SPyun YongHyeon 			/* Get TLP header form Log Registers. */
34340dbe28b3SPyun YongHyeon 			for (i = 0; i < 4; i++)
34350dbe28b3SPyun YongHyeon 				tlphead[i] = CSR_PCI_READ_4(sc,
34360dbe28b3SPyun YongHyeon 				    PEX_HEADER_LOG + i * 4);
34370dbe28b3SPyun YongHyeon 			/* Check for vendor defined broadcast message. */
34380dbe28b3SPyun YongHyeon 			if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) {
34390dbe28b3SPyun YongHyeon 				sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP;
34400dbe28b3SPyun YongHyeon 				CSR_WRITE_4(sc, B0_HWE_IMSK,
34410dbe28b3SPyun YongHyeon 				    sc->msk_intrhwemask);
34420dbe28b3SPyun YongHyeon 				CSR_READ_4(sc, B0_HWE_IMSK);
34430dbe28b3SPyun YongHyeon 			}
34440dbe28b3SPyun YongHyeon 		}
34450dbe28b3SPyun YongHyeon 		/* Clear the interrupt. */
34460dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON);
34470dbe28b3SPyun YongHyeon 		CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff);
34480dbe28b3SPyun YongHyeon 		CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
34490dbe28b3SPyun YongHyeon 	}
34500dbe28b3SPyun YongHyeon 
34510dbe28b3SPyun YongHyeon 	if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL)
34520dbe28b3SPyun YongHyeon 		msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status);
34530dbe28b3SPyun YongHyeon 	if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL)
34540dbe28b3SPyun YongHyeon 		msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8);
34550dbe28b3SPyun YongHyeon }
34560dbe28b3SPyun YongHyeon 
34570dbe28b3SPyun YongHyeon static __inline void
34580dbe28b3SPyun YongHyeon msk_rxput(struct msk_if_softc *sc_if)
34590dbe28b3SPyun YongHyeon {
34600dbe28b3SPyun YongHyeon 	struct msk_softc *sc;
34610dbe28b3SPyun YongHyeon 
34620dbe28b3SPyun YongHyeon 	sc = sc_if->msk_softc;
346385b340cbSPyun YongHyeon 	if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN))
34640dbe28b3SPyun YongHyeon 		bus_dmamap_sync(
34650dbe28b3SPyun YongHyeon 		    sc_if->msk_cdata.msk_jumbo_rx_ring_tag,
34660dbe28b3SPyun YongHyeon 		    sc_if->msk_cdata.msk_jumbo_rx_ring_map,
34670dbe28b3SPyun YongHyeon 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
34680dbe28b3SPyun YongHyeon 	else
34690dbe28b3SPyun YongHyeon 		bus_dmamap_sync(
34700dbe28b3SPyun YongHyeon 		    sc_if->msk_cdata.msk_rx_ring_tag,
34710dbe28b3SPyun YongHyeon 		    sc_if->msk_cdata.msk_rx_ring_map,
34720dbe28b3SPyun YongHyeon 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
34730dbe28b3SPyun YongHyeon 	CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq,
34740dbe28b3SPyun YongHyeon 	    PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod);
34750dbe28b3SPyun YongHyeon }
34760dbe28b3SPyun YongHyeon 
34770dbe28b3SPyun YongHyeon static int
34780dbe28b3SPyun YongHyeon msk_handle_events(struct msk_softc *sc)
34790dbe28b3SPyun YongHyeon {
34800dbe28b3SPyun YongHyeon 	struct msk_if_softc *sc_if;
34810dbe28b3SPyun YongHyeon 	int rxput[2];
34820dbe28b3SPyun YongHyeon 	struct msk_stat_desc *sd;
34830dbe28b3SPyun YongHyeon 	uint32_t control, status;
3484c876b43fSPyun YongHyeon 	int cons, len, port, rxprog;
34850dbe28b3SPyun YongHyeon 
348607fa0751SPyun YongHyeon 	if (sc->msk_stat_cons == CSR_READ_2(sc, STAT_PUT_IDX))
348707fa0751SPyun YongHyeon 		return (0);
348807fa0751SPyun YongHyeon 
34890dbe28b3SPyun YongHyeon 	/* Sync status LEs. */
34900dbe28b3SPyun YongHyeon 	bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
34910dbe28b3SPyun YongHyeon 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
34920dbe28b3SPyun YongHyeon 
34930dbe28b3SPyun YongHyeon 	rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0;
34940dbe28b3SPyun YongHyeon 	rxprog = 0;
3495c876b43fSPyun YongHyeon 	cons = sc->msk_stat_cons;
3496c876b43fSPyun YongHyeon 	for (;;) {
34970dbe28b3SPyun YongHyeon 		sd = &sc->msk_stat_ring[cons];
34980dbe28b3SPyun YongHyeon 		control = le32toh(sd->msk_control);
34990dbe28b3SPyun YongHyeon 		if ((control & HW_OWNER) == 0)
35000dbe28b3SPyun YongHyeon 			break;
35010dbe28b3SPyun YongHyeon 		control &= ~HW_OWNER;
35020dbe28b3SPyun YongHyeon 		sd->msk_control = htole32(control);
35030dbe28b3SPyun YongHyeon 		status = le32toh(sd->msk_status);
35040dbe28b3SPyun YongHyeon 		len = control & STLE_LEN_MASK;
35050dbe28b3SPyun YongHyeon 		port = (control >> 16) & 0x01;
35060dbe28b3SPyun YongHyeon 		sc_if = sc->msk_if[port];
35070dbe28b3SPyun YongHyeon 		if (sc_if == NULL) {
35080dbe28b3SPyun YongHyeon 			device_printf(sc->msk_dev, "invalid port opcode "
35090dbe28b3SPyun YongHyeon 			    "0x%08x\n", control & STLE_OP_MASK);
35100dbe28b3SPyun YongHyeon 			continue;
35110dbe28b3SPyun YongHyeon 		}
35120dbe28b3SPyun YongHyeon 
35130dbe28b3SPyun YongHyeon 		switch (control & STLE_OP_MASK) {
35140dbe28b3SPyun YongHyeon 		case OP_RXVLAN:
35150dbe28b3SPyun YongHyeon 			sc_if->msk_vtag = ntohs(len);
35160dbe28b3SPyun YongHyeon 			break;
35170dbe28b3SPyun YongHyeon 		case OP_RXCHKSVLAN:
35180dbe28b3SPyun YongHyeon 			sc_if->msk_vtag = ntohs(len);
3519388214e4SPyun YongHyeon 			/* FALLTHROUGH */
3520388214e4SPyun YongHyeon 		case OP_RXCHKS:
3521388214e4SPyun YongHyeon 			sc_if->msk_csum = status;
35220dbe28b3SPyun YongHyeon 			break;
35230dbe28b3SPyun YongHyeon 		case OP_RXSTAT:
352431fefd0dSPyun YongHyeon 			if (!(sc_if->msk_ifp->if_drv_flags & IFF_DRV_RUNNING))
352531fefd0dSPyun YongHyeon 				break;
352685b340cbSPyun YongHyeon 			if (sc_if->msk_framesize >
352785b340cbSPyun YongHyeon 			    (MCLBYTES - MSK_RX_BUF_ALIGN))
3528efb74172SPyun YongHyeon 				msk_jumbo_rxeof(sc_if, status, control, len);
35290dbe28b3SPyun YongHyeon 			else
3530efb74172SPyun YongHyeon 				msk_rxeof(sc_if, status, control, len);
35310dbe28b3SPyun YongHyeon 			rxprog++;
35320dbe28b3SPyun YongHyeon 			/*
35330dbe28b3SPyun YongHyeon 			 * Because there is no way to sync single Rx LE
35340dbe28b3SPyun YongHyeon 			 * put the DMA sync operation off until the end of
35350dbe28b3SPyun YongHyeon 			 * event processing.
35360dbe28b3SPyun YongHyeon 			 */
35370dbe28b3SPyun YongHyeon 			rxput[port]++;
35380dbe28b3SPyun YongHyeon 			/* Update prefetch unit if we've passed water mark. */
35390dbe28b3SPyun YongHyeon 			if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) {
35400dbe28b3SPyun YongHyeon 				msk_rxput(sc_if);
35410dbe28b3SPyun YongHyeon 				rxput[port] = 0;
35420dbe28b3SPyun YongHyeon 			}
35430dbe28b3SPyun YongHyeon 			break;
35440dbe28b3SPyun YongHyeon 		case OP_TXINDEXLE:
35450dbe28b3SPyun YongHyeon 			if (sc->msk_if[MSK_PORT_A] != NULL)
35460dbe28b3SPyun YongHyeon 				msk_txeof(sc->msk_if[MSK_PORT_A],
35470dbe28b3SPyun YongHyeon 				    status & STLE_TXA1_MSKL);
35480dbe28b3SPyun YongHyeon 			if (sc->msk_if[MSK_PORT_B] != NULL)
35490dbe28b3SPyun YongHyeon 				msk_txeof(sc->msk_if[MSK_PORT_B],
35500dbe28b3SPyun YongHyeon 				    ((status & STLE_TXA2_MSKL) >>
35510dbe28b3SPyun YongHyeon 				    STLE_TXA2_SHIFTL) |
35520dbe28b3SPyun YongHyeon 				    ((len & STLE_TXA2_MSKH) <<
35530dbe28b3SPyun YongHyeon 				    STLE_TXA2_SHIFTH));
35540dbe28b3SPyun YongHyeon 			break;
35550dbe28b3SPyun YongHyeon 		default:
35560dbe28b3SPyun YongHyeon 			device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n",
35570dbe28b3SPyun YongHyeon 			    control & STLE_OP_MASK);
35580dbe28b3SPyun YongHyeon 			break;
35590dbe28b3SPyun YongHyeon 		}
35600dbe28b3SPyun YongHyeon 		MSK_INC(cons, MSK_STAT_RING_CNT);
35610dbe28b3SPyun YongHyeon 		if (rxprog > sc->msk_process_limit)
35620dbe28b3SPyun YongHyeon 			break;
35630dbe28b3SPyun YongHyeon 	}
35640dbe28b3SPyun YongHyeon 
35650dbe28b3SPyun YongHyeon 	sc->msk_stat_cons = cons;
356617f6f326SPyun YongHyeon 	bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map,
356717f6f326SPyun YongHyeon 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
35680dbe28b3SPyun YongHyeon 
35690dbe28b3SPyun YongHyeon 	if (rxput[MSK_PORT_A] > 0)
35700dbe28b3SPyun YongHyeon 		msk_rxput(sc->msk_if[MSK_PORT_A]);
35710dbe28b3SPyun YongHyeon 	if (rxput[MSK_PORT_B] > 0)
35720dbe28b3SPyun YongHyeon 		msk_rxput(sc->msk_if[MSK_PORT_B]);
35730dbe28b3SPyun YongHyeon 
357407fa0751SPyun YongHyeon 	return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX));
35750dbe28b3SPyun YongHyeon }
35760dbe28b3SPyun YongHyeon 
357753dcfbd1SPyun YongHyeon static void
3578c876b43fSPyun YongHyeon msk_intr(void *xsc)
357953dcfbd1SPyun YongHyeon {
358053dcfbd1SPyun YongHyeon 	struct msk_softc *sc;
358153dcfbd1SPyun YongHyeon 	struct msk_if_softc *sc_if0, *sc_if1;
358253dcfbd1SPyun YongHyeon 	struct ifnet *ifp0, *ifp1;
358353dcfbd1SPyun YongHyeon 	uint32_t status;
3584c876b43fSPyun YongHyeon 	int domore;
358553dcfbd1SPyun YongHyeon 
358653dcfbd1SPyun YongHyeon 	sc = xsc;
358753dcfbd1SPyun YongHyeon 	MSK_LOCK(sc);
358853dcfbd1SPyun YongHyeon 
358953dcfbd1SPyun YongHyeon 	/* Reading B0_Y2_SP_ISRC2 masks further interrupts. */
359053dcfbd1SPyun YongHyeon 	status = CSR_READ_4(sc, B0_Y2_SP_ISRC2);
3591ab7df1e4SPyun YongHyeon 	if (status == 0 || status == 0xffffffff ||
3592ab7df1e4SPyun YongHyeon 	    (sc->msk_pflags & MSK_FLAG_SUSPEND) != 0 ||
359353dcfbd1SPyun YongHyeon 	    (status & sc->msk_intrmask) == 0) {
359453dcfbd1SPyun YongHyeon 		CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
35953d763c31SPyun YongHyeon 		MSK_UNLOCK(sc);
359653dcfbd1SPyun YongHyeon 		return;
359753dcfbd1SPyun YongHyeon 	}
359853dcfbd1SPyun YongHyeon 
359953dcfbd1SPyun YongHyeon 	sc_if0 = sc->msk_if[MSK_PORT_A];
360053dcfbd1SPyun YongHyeon 	sc_if1 = sc->msk_if[MSK_PORT_B];
360153dcfbd1SPyun YongHyeon 	ifp0 = ifp1 = NULL;
360253dcfbd1SPyun YongHyeon 	if (sc_if0 != NULL)
360353dcfbd1SPyun YongHyeon 		ifp0 = sc_if0->msk_ifp;
360453dcfbd1SPyun YongHyeon 	if (sc_if1 != NULL)
360553dcfbd1SPyun YongHyeon 		ifp1 = sc_if1->msk_ifp;
360653dcfbd1SPyun YongHyeon 
360753dcfbd1SPyun YongHyeon 	if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL)
360853dcfbd1SPyun YongHyeon 		msk_intr_phy(sc_if0);
360953dcfbd1SPyun YongHyeon 	if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL)
361053dcfbd1SPyun YongHyeon 		msk_intr_phy(sc_if1);
361153dcfbd1SPyun YongHyeon 	if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL)
361253dcfbd1SPyun YongHyeon 		msk_intr_gmac(sc_if0);
361353dcfbd1SPyun YongHyeon 	if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL)
361453dcfbd1SPyun YongHyeon 		msk_intr_gmac(sc_if1);
361553dcfbd1SPyun YongHyeon 	if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) {
361653dcfbd1SPyun YongHyeon 		device_printf(sc->msk_dev, "Rx descriptor error\n");
361753dcfbd1SPyun YongHyeon 		sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2);
361853dcfbd1SPyun YongHyeon 		CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
361953dcfbd1SPyun YongHyeon 		CSR_READ_4(sc, B0_IMSK);
362053dcfbd1SPyun YongHyeon 	}
362153dcfbd1SPyun YongHyeon         if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) {
362253dcfbd1SPyun YongHyeon 		device_printf(sc->msk_dev, "Tx descriptor error\n");
362353dcfbd1SPyun YongHyeon 		sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2);
362453dcfbd1SPyun YongHyeon 		CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
362553dcfbd1SPyun YongHyeon 		CSR_READ_4(sc, B0_IMSK);
362653dcfbd1SPyun YongHyeon 	}
362753dcfbd1SPyun YongHyeon 	if ((status & Y2_IS_HW_ERR) != 0)
362853dcfbd1SPyun YongHyeon 		msk_intr_hwerr(sc);
362953dcfbd1SPyun YongHyeon 
36300dbe28b3SPyun YongHyeon 	domore = msk_handle_events(sc);
3631c876b43fSPyun YongHyeon 	if ((status & Y2_IS_STAT_BMU) != 0 && domore == 0)
36320dbe28b3SPyun YongHyeon 		CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ);
36330dbe28b3SPyun YongHyeon 
36340dbe28b3SPyun YongHyeon 	/* Reenable interrupts. */
36350dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2);
3636c876b43fSPyun YongHyeon 
3637c876b43fSPyun YongHyeon 	if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
3638c876b43fSPyun YongHyeon 	    !IFQ_DRV_IS_EMPTY(&ifp0->if_snd))
3639c876b43fSPyun YongHyeon 		msk_start_locked(ifp0);
3640c876b43fSPyun YongHyeon 	if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 &&
3641c876b43fSPyun YongHyeon 	    !IFQ_DRV_IS_EMPTY(&ifp1->if_snd))
3642c876b43fSPyun YongHyeon 		msk_start_locked(ifp1);
3643c876b43fSPyun YongHyeon 
3644c876b43fSPyun YongHyeon 	MSK_UNLOCK(sc);
36450dbe28b3SPyun YongHyeon }
36460dbe28b3SPyun YongHyeon 
36470dbe28b3SPyun YongHyeon static void
3648daf29227SPyun YongHyeon msk_set_tx_stfwd(struct msk_if_softc *sc_if)
3649daf29227SPyun YongHyeon {
3650daf29227SPyun YongHyeon 	struct msk_softc *sc;
3651daf29227SPyun YongHyeon 	struct ifnet *ifp;
3652daf29227SPyun YongHyeon 
3653daf29227SPyun YongHyeon 	ifp = sc_if->msk_ifp;
3654daf29227SPyun YongHyeon 	sc = sc_if->msk_softc;
36557b4f47c1SPyun YongHyeon 	if ((sc->msk_hw_id == CHIP_ID_YUKON_EX &&
36567b4f47c1SPyun YongHyeon 	    sc->msk_hw_rev != CHIP_REV_YU_EX_A0) ||
36577b4f47c1SPyun YongHyeon 	    sc->msk_hw_id >= CHIP_ID_YUKON_SUPR) {
36587b4f47c1SPyun YongHyeon 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
36597b4f47c1SPyun YongHyeon 		    TX_STFW_ENA);
36607b4f47c1SPyun YongHyeon 	} else {
3661daf29227SPyun YongHyeon 		if (ifp->if_mtu > ETHERMTU) {
3662daf29227SPyun YongHyeon 			/* Set Tx GMAC FIFO Almost Empty Threshold. */
3663daf29227SPyun YongHyeon 			CSR_WRITE_4(sc,
3664daf29227SPyun YongHyeon 			    MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR),
3665daf29227SPyun YongHyeon 			    MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR);
3666daf29227SPyun YongHyeon 			/* Disable Store & Forward mode for Tx. */
36677b4f47c1SPyun YongHyeon 			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
36687b4f47c1SPyun YongHyeon 			    TX_STFW_DIS);
3669daf29227SPyun YongHyeon 		} else {
36707b4f47c1SPyun YongHyeon 			CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T),
36717b4f47c1SPyun YongHyeon 			    TX_STFW_ENA);
3672daf29227SPyun YongHyeon 		}
3673daf29227SPyun YongHyeon 	}
3674daf29227SPyun YongHyeon }
3675daf29227SPyun YongHyeon 
3676daf29227SPyun YongHyeon static void
36770dbe28b3SPyun YongHyeon msk_init(void *xsc)
36780dbe28b3SPyun YongHyeon {
36790dbe28b3SPyun YongHyeon 	struct msk_if_softc *sc_if = xsc;
36800dbe28b3SPyun YongHyeon 
36810dbe28b3SPyun YongHyeon 	MSK_IF_LOCK(sc_if);
36820dbe28b3SPyun YongHyeon 	msk_init_locked(sc_if);
36830dbe28b3SPyun YongHyeon 	MSK_IF_UNLOCK(sc_if);
36840dbe28b3SPyun YongHyeon }
36850dbe28b3SPyun YongHyeon 
36860dbe28b3SPyun YongHyeon static void
36870dbe28b3SPyun YongHyeon msk_init_locked(struct msk_if_softc *sc_if)
36880dbe28b3SPyun YongHyeon {
36890dbe28b3SPyun YongHyeon 	struct msk_softc *sc;
36900dbe28b3SPyun YongHyeon 	struct ifnet *ifp;
36910dbe28b3SPyun YongHyeon 	struct mii_data	 *mii;
3692cf5756a6SPyun YongHyeon 	uint8_t *eaddr;
36930dbe28b3SPyun YongHyeon 	uint16_t gmac;
369461708f4cSPyun YongHyeon 	uint32_t reg;
3695cf5756a6SPyun YongHyeon 	int error;
36960dbe28b3SPyun YongHyeon 
36970dbe28b3SPyun YongHyeon 	MSK_IF_LOCK_ASSERT(sc_if);
36980dbe28b3SPyun YongHyeon 
36990dbe28b3SPyun YongHyeon 	ifp = sc_if->msk_ifp;
37000dbe28b3SPyun YongHyeon 	sc = sc_if->msk_softc;
37010dbe28b3SPyun YongHyeon 	mii = device_get_softc(sc_if->msk_miibus);
37020dbe28b3SPyun YongHyeon 
370389e22666SPyun YongHyeon 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
370489e22666SPyun YongHyeon 		return;
370589e22666SPyun YongHyeon 
37060dbe28b3SPyun YongHyeon 	error = 0;
37070dbe28b3SPyun YongHyeon 	/* Cancel pending I/O and free all Rx/Tx buffers. */
37080dbe28b3SPyun YongHyeon 	msk_stop(sc_if);
37090dbe28b3SPyun YongHyeon 
371085b340cbSPyun YongHyeon 	if (ifp->if_mtu < ETHERMTU)
371185b340cbSPyun YongHyeon 		sc_if->msk_framesize = ETHERMTU;
371285b340cbSPyun YongHyeon 	else
371385b340cbSPyun YongHyeon 		sc_if->msk_framesize = ifp->if_mtu;
371485b340cbSPyun YongHyeon 	sc_if->msk_framesize += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
371585b340cbSPyun YongHyeon 	if (ifp->if_mtu > ETHERMTU &&
3716e2b16603SPyun YongHyeon 	    (sc_if->msk_flags & MSK_FLAG_JUMBO_NOCSUM) != 0) {
3717a109c74fSPyun YongHyeon 		ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO);
3718a109c74fSPyun YongHyeon 		ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM);
3719a109c74fSPyun YongHyeon 	}
37200dbe28b3SPyun YongHyeon 
3721e6e23ffeSPyun YongHyeon  	/* GMAC Control reset. */
3722e6e23ffeSPyun YongHyeon  	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_SET);
3723e6e23ffeSPyun YongHyeon  	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_RST_CLR);
3724e6e23ffeSPyun YongHyeon  	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_F_LOOPB_OFF);
3725daf29227SPyun YongHyeon 	if (sc->msk_hw_id == CHIP_ID_YUKON_EX)
3726daf29227SPyun YongHyeon 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL),
3727daf29227SPyun YongHyeon 		    GMC_BYP_MACSECRX_ON | GMC_BYP_MACSECTX_ON |
3728daf29227SPyun YongHyeon 		    GMC_BYP_RETR_ON);
3729e6e23ffeSPyun YongHyeon 
37300dbe28b3SPyun YongHyeon 	/*
3731e6e23ffeSPyun YongHyeon 	 * Initialize GMAC first such that speed/duplex/flow-control
3732e6e23ffeSPyun YongHyeon 	 * parameters are renegotiated when interface is brought up.
37330dbe28b3SPyun YongHyeon 	 */
3734e6e23ffeSPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, 0);
37350dbe28b3SPyun YongHyeon 
37360dbe28b3SPyun YongHyeon 	/* Dummy read the Interrupt Source Register. */
37370dbe28b3SPyun YongHyeon 	CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC));
37380dbe28b3SPyun YongHyeon 
37393a91ee71SPyun YongHyeon 	/* Clear MIB stats. */
37403a91ee71SPyun YongHyeon 	msk_stats_clear(sc_if);
37410dbe28b3SPyun YongHyeon 
37420dbe28b3SPyun YongHyeon 	/* Disable FCS. */
37430dbe28b3SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS);
37440dbe28b3SPyun YongHyeon 
37450dbe28b3SPyun YongHyeon 	/* Setup Transmit Control Register. */
37460dbe28b3SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
37470dbe28b3SPyun YongHyeon 
37480dbe28b3SPyun YongHyeon 	/* Setup Transmit Flow Control Register. */
37490dbe28b3SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff);
37500dbe28b3SPyun YongHyeon 
37510dbe28b3SPyun YongHyeon 	/* Setup Transmit Parameter Register. */
37520dbe28b3SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM,
37530dbe28b3SPyun YongHyeon 	    TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
37540dbe28b3SPyun YongHyeon 	    TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
37550dbe28b3SPyun YongHyeon 
37560dbe28b3SPyun YongHyeon 	gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) |
37570dbe28b3SPyun YongHyeon 	    GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
37580dbe28b3SPyun YongHyeon 
375985b340cbSPyun YongHyeon 	if (ifp->if_mtu > ETHERMTU)
37600dbe28b3SPyun YongHyeon 		gmac |= GM_SMOD_JUMBO_ENA;
37610dbe28b3SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac);
37620dbe28b3SPyun YongHyeon 
37630dbe28b3SPyun YongHyeon 	/* Set station address. */
3764cf5756a6SPyun YongHyeon 	eaddr = IF_LLADDR(ifp);
3765cf5756a6SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L,
3766cf5756a6SPyun YongHyeon 	    eaddr[0] | (eaddr[1] << 8));
3767cf5756a6SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1M,
3768cf5756a6SPyun YongHyeon 	    eaddr[2] | (eaddr[3] << 8));
3769cf5756a6SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1H,
3770cf5756a6SPyun YongHyeon 	    eaddr[4] | (eaddr[5] << 8));
3771cf5756a6SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L,
3772cf5756a6SPyun YongHyeon 	    eaddr[0] | (eaddr[1] << 8));
3773cf5756a6SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2M,
3774cf5756a6SPyun YongHyeon 	    eaddr[2] | (eaddr[3] << 8));
3775cf5756a6SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2H,
3776cf5756a6SPyun YongHyeon 	    eaddr[4] | (eaddr[5] << 8));
37770dbe28b3SPyun YongHyeon 
37780dbe28b3SPyun YongHyeon 	/* Disable interrupts for counter overflows. */
37790dbe28b3SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0);
37800dbe28b3SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0);
37810dbe28b3SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0);
37820dbe28b3SPyun YongHyeon 
37830dbe28b3SPyun YongHyeon 	/* Configure Rx MAC FIFO. */
37840dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
37850dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR);
378661708f4cSPyun YongHyeon 	reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
3787daf29227SPyun YongHyeon 	if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P ||
3788daf29227SPyun YongHyeon 	    sc->msk_hw_id == CHIP_ID_YUKON_EX)
378961708f4cSPyun YongHyeon 		reg |= GMF_RX_OVER_ON;
379061708f4cSPyun YongHyeon 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), reg);
37910dbe28b3SPyun YongHyeon 
37926d6588a1SPyun YongHyeon 	/* Set receive filter. */
37936d6588a1SPyun YongHyeon 	msk_rxfilter(sc_if);
37940dbe28b3SPyun YongHyeon 
3795cde64af3SPyun YongHyeon 	if (sc->msk_hw_id == CHIP_ID_YUKON_XL) {
3796cde64af3SPyun YongHyeon 		/* Clear flush mask - HW bug. */
3797cde64af3SPyun YongHyeon 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 0);
3798cde64af3SPyun YongHyeon 	} else {
37990dbe28b3SPyun YongHyeon 		/* Flush Rx MAC FIFO on any flow control or error. */
38000dbe28b3SPyun YongHyeon 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK),
38010dbe28b3SPyun YongHyeon 		    GMR_FS_ANY_ERR);
3802cde64af3SPyun YongHyeon 	}
38030dbe28b3SPyun YongHyeon 
3804d5d60164SPyun YongHyeon 	/*
3805d5d60164SPyun YongHyeon 	 * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word
3806d5d60164SPyun YongHyeon 	 * due to hardware hang on receipt of pause frames.
3807d5d60164SPyun YongHyeon 	 */
3808224003b7SPyun YongHyeon 	reg = RX_GMF_FL_THR_DEF + 1;
3809224003b7SPyun YongHyeon 	/* Another magic for Yukon FE+ - From Linux. */
3810224003b7SPyun YongHyeon 	if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
3811224003b7SPyun YongHyeon 	    sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0)
3812224003b7SPyun YongHyeon 		reg = 0x178;
3813224003b7SPyun YongHyeon 	CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), reg);
38140dbe28b3SPyun YongHyeon 
38150dbe28b3SPyun YongHyeon 	/* Configure Tx MAC FIFO. */
38160dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
38170dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR);
38180dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON);
38190dbe28b3SPyun YongHyeon 
38200dbe28b3SPyun YongHyeon 	/* Configure hardware VLAN tag insertion/stripping. */
38210dbe28b3SPyun YongHyeon 	msk_setvlan(sc_if, ifp);
38220dbe28b3SPyun YongHyeon 
382383c04c93SPyun YongHyeon 	if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0) {
3824b1ce21c6SRebecca Cran 		/* Set Rx Pause threshold. */
3825106b2e2fSPyun YongHyeon 		CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR),
38260dbe28b3SPyun YongHyeon 		    MSK_ECU_LLPP);
3827106b2e2fSPyun YongHyeon 		CSR_WRITE_2(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR),
38280dbe28b3SPyun YongHyeon 		    MSK_ECU_ULPP);
3829daf29227SPyun YongHyeon 		/* Configure store-and-forward for Tx. */
3830daf29227SPyun YongHyeon 		msk_set_tx_stfwd(sc_if);
38310dbe28b3SPyun YongHyeon 	}
38320dbe28b3SPyun YongHyeon 
3833224003b7SPyun YongHyeon  	if (sc->msk_hw_id == CHIP_ID_YUKON_FE_P &&
3834224003b7SPyun YongHyeon  	    sc->msk_hw_rev == CHIP_REV_YU_FE_P_A0) {
3835224003b7SPyun YongHyeon  		/* Disable dynamic watermark - from Linux. */
3836224003b7SPyun YongHyeon  		reg = CSR_READ_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA));
3837224003b7SPyun YongHyeon  		reg &= ~0x03;
3838224003b7SPyun YongHyeon  		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_EA), reg);
3839224003b7SPyun YongHyeon  	}
3840224003b7SPyun YongHyeon 
38410dbe28b3SPyun YongHyeon 	/*
38420dbe28b3SPyun YongHyeon 	 * Disable Force Sync bit and Alloc bit in Tx RAM interface
38430dbe28b3SPyun YongHyeon 	 * arbiter as we don't use Sync Tx queue.
38440dbe28b3SPyun YongHyeon 	 */
38450dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL),
38460dbe28b3SPyun YongHyeon 	    TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
38470dbe28b3SPyun YongHyeon 	/* Enable the RAM Interface Arbiter. */
38480dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB);
38490dbe28b3SPyun YongHyeon 
38500dbe28b3SPyun YongHyeon 	/* Setup RAM buffer. */
38510dbe28b3SPyun YongHyeon 	msk_set_rambuffer(sc_if);
38520dbe28b3SPyun YongHyeon 
38530dbe28b3SPyun YongHyeon 	/* Disable Tx sync Queue. */
38540dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET);
38550dbe28b3SPyun YongHyeon 
38560dbe28b3SPyun YongHyeon 	/* Setup Tx Queue Bus Memory Interface. */
38570dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET);
38580dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT);
38590dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON);
38600dbe28b3SPyun YongHyeon 	CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM);
3861ebb25bfaSPyun YongHyeon 	switch (sc->msk_hw_id) {
3862ebb25bfaSPyun YongHyeon 	case CHIP_ID_YUKON_EC_U:
3863ebb25bfaSPyun YongHyeon 		if (sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) {
38640dbe28b3SPyun YongHyeon 			/* Fix for Yukon-EC Ultra: set BMU FIFO level */
3865ebb25bfaSPyun YongHyeon 			CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL),
3866ebb25bfaSPyun YongHyeon 			    MSK_ECU_TXFF_LEV);
3867ebb25bfaSPyun YongHyeon 		}
3868ebb25bfaSPyun YongHyeon 		break;
3869ebb25bfaSPyun YongHyeon 	case CHIP_ID_YUKON_EX:
3870ebb25bfaSPyun YongHyeon 		/*
3871ebb25bfaSPyun YongHyeon 		 * Yukon Extreme seems to have silicon bug for
3872ebb25bfaSPyun YongHyeon 		 * automatic Tx checksum calculation capability.
3873ebb25bfaSPyun YongHyeon 		 */
3874ebb25bfaSPyun YongHyeon 		if (sc->msk_hw_rev == CHIP_REV_YU_EX_B0)
3875ebb25bfaSPyun YongHyeon 			CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_F),
3876ebb25bfaSPyun YongHyeon 			    F_TX_CHK_AUTO_OFF);
3877ebb25bfaSPyun YongHyeon 		break;
38780dbe28b3SPyun YongHyeon 	}
38790dbe28b3SPyun YongHyeon 
38800dbe28b3SPyun YongHyeon 	/* Setup Rx Queue Bus Memory Interface. */
38810dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET);
38820dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT);
38830dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON);
38840dbe28b3SPyun YongHyeon 	CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM);
38850dbe28b3SPyun YongHyeon         if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U &&
38860dbe28b3SPyun YongHyeon 	    sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) {
38870dbe28b3SPyun YongHyeon 		/* MAC Rx RAM Read is controlled by hardware. */
38880dbe28b3SPyun YongHyeon                 CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS);
38890dbe28b3SPyun YongHyeon 	}
38900dbe28b3SPyun YongHyeon 
38910dbe28b3SPyun YongHyeon 	msk_set_prefetch(sc, sc_if->msk_txq,
38920dbe28b3SPyun YongHyeon 	    sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1);
38930dbe28b3SPyun YongHyeon 	msk_init_tx_ring(sc_if);
38940dbe28b3SPyun YongHyeon 
38950dbe28b3SPyun YongHyeon 	/* Disable Rx checksum offload and RSS hash. */
3896388214e4SPyun YongHyeon 	reg = BMU_DIS_RX_RSS_HASH;
3897388214e4SPyun YongHyeon 	if ((sc_if->msk_flags & MSK_FLAG_DESCV2) == 0 &&
3898388214e4SPyun YongHyeon 	    (ifp->if_capenable & IFCAP_RXCSUM) != 0)
3899388214e4SPyun YongHyeon 		reg |= BMU_ENA_RX_CHKSUM;
3900388214e4SPyun YongHyeon 	else
3901388214e4SPyun YongHyeon 		reg |= BMU_DIS_RX_CHKSUM;
3902388214e4SPyun YongHyeon 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), reg);
390385b340cbSPyun YongHyeon 	if (sc_if->msk_framesize > (MCLBYTES - MSK_RX_BUF_ALIGN)) {
39040dbe28b3SPyun YongHyeon 		msk_set_prefetch(sc, sc_if->msk_rxq,
39050dbe28b3SPyun YongHyeon 		    sc_if->msk_rdata.msk_jumbo_rx_ring_paddr,
39060dbe28b3SPyun YongHyeon 		    MSK_JUMBO_RX_RING_CNT - 1);
39070dbe28b3SPyun YongHyeon 		error = msk_init_jumbo_rx_ring(sc_if);
39080dbe28b3SPyun YongHyeon 	 } else {
39090dbe28b3SPyun YongHyeon 		msk_set_prefetch(sc, sc_if->msk_rxq,
39100dbe28b3SPyun YongHyeon 		    sc_if->msk_rdata.msk_rx_ring_paddr,
39110dbe28b3SPyun YongHyeon 		    MSK_RX_RING_CNT - 1);
39120dbe28b3SPyun YongHyeon 		error = msk_init_rx_ring(sc_if);
39130dbe28b3SPyun YongHyeon 	}
39140dbe28b3SPyun YongHyeon 	if (error != 0) {
39150dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev,
39160dbe28b3SPyun YongHyeon 		    "initialization failed: no memory for Rx buffers\n");
39170dbe28b3SPyun YongHyeon 		msk_stop(sc_if);
39180dbe28b3SPyun YongHyeon 		return;
39190dbe28b3SPyun YongHyeon 	}
39207c8db6fdSPyun YongHyeon 	if (sc->msk_hw_id == CHIP_ID_YUKON_EX) {
39217c8db6fdSPyun YongHyeon 		/* Disable flushing of non-ASF packets. */
39227c8db6fdSPyun YongHyeon 		CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T),
39237c8db6fdSPyun YongHyeon 		    GMF_RX_MACSEC_FLUSH_OFF);
39247c8db6fdSPyun YongHyeon 	}
39250dbe28b3SPyun YongHyeon 
39260dbe28b3SPyun YongHyeon 	/* Configure interrupt handling. */
39270dbe28b3SPyun YongHyeon 	if (sc_if->msk_port == MSK_PORT_A) {
39280dbe28b3SPyun YongHyeon 		sc->msk_intrmask |= Y2_IS_PORT_A;
39290dbe28b3SPyun YongHyeon 		sc->msk_intrhwemask |= Y2_HWE_L1_MASK;
39300dbe28b3SPyun YongHyeon 	} else {
39310dbe28b3SPyun YongHyeon 		sc->msk_intrmask |= Y2_IS_PORT_B;
39320dbe28b3SPyun YongHyeon 		sc->msk_intrhwemask |= Y2_HWE_L2_MASK;
39330dbe28b3SPyun YongHyeon 	}
3934cf570c1fSPyun YongHyeon 	/* Configure IRQ moderation mask. */
3935cf570c1fSPyun YongHyeon 	CSR_WRITE_4(sc, B2_IRQM_MSK, sc->msk_intrmask);
3936cf570c1fSPyun YongHyeon 	if (sc->msk_int_holdoff > 0) {
3937cf570c1fSPyun YongHyeon 		/* Configure initial IRQ moderation timer value. */
3938cf570c1fSPyun YongHyeon 		CSR_WRITE_4(sc, B2_IRQM_INI,
3939cf570c1fSPyun YongHyeon 		    MSK_USECS(sc, sc->msk_int_holdoff));
3940cf570c1fSPyun YongHyeon 		CSR_WRITE_4(sc, B2_IRQM_VAL,
3941cf570c1fSPyun YongHyeon 		    MSK_USECS(sc, sc->msk_int_holdoff));
3942cf570c1fSPyun YongHyeon 		/* Start IRQ moderation. */
3943cf570c1fSPyun YongHyeon 		CSR_WRITE_1(sc, B2_IRQM_CTRL, TIM_START);
3944cf570c1fSPyun YongHyeon 	}
39450dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
39460dbe28b3SPyun YongHyeon 	CSR_READ_4(sc, B0_HWE_IMSK);
39470dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
39480dbe28b3SPyun YongHyeon 	CSR_READ_4(sc, B0_IMSK);
39490dbe28b3SPyun YongHyeon 
3950ab7df1e4SPyun YongHyeon 	sc_if->msk_flags &= ~MSK_FLAG_LINK;
39510dbe28b3SPyun YongHyeon 	mii_mediachg(mii);
39520dbe28b3SPyun YongHyeon 
39530dbe28b3SPyun YongHyeon 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
39540dbe28b3SPyun YongHyeon 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
39550dbe28b3SPyun YongHyeon 
39560dbe28b3SPyun YongHyeon 	callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if);
39570dbe28b3SPyun YongHyeon }
39580dbe28b3SPyun YongHyeon 
39590dbe28b3SPyun YongHyeon static void
39600dbe28b3SPyun YongHyeon msk_set_rambuffer(struct msk_if_softc *sc_if)
39610dbe28b3SPyun YongHyeon {
39620dbe28b3SPyun YongHyeon 	struct msk_softc *sc;
39630dbe28b3SPyun YongHyeon 	int ltpp, utpp;
39640dbe28b3SPyun YongHyeon 
39650dbe28b3SPyun YongHyeon 	sc = sc_if->msk_softc;
396683c04c93SPyun YongHyeon 	if ((sc_if->msk_flags & MSK_FLAG_RAMBUF) == 0)
396783c04c93SPyun YongHyeon 		return;
39680dbe28b3SPyun YongHyeon 
39690dbe28b3SPyun YongHyeon 	/* Setup Rx Queue. */
39700dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR);
39710dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START),
39720dbe28b3SPyun YongHyeon 	    sc->msk_rxqstart[sc_if->msk_port] / 8);
39730dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END),
39740dbe28b3SPyun YongHyeon 	    sc->msk_rxqend[sc_if->msk_port] / 8);
39750dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP),
39760dbe28b3SPyun YongHyeon 	    sc->msk_rxqstart[sc_if->msk_port] / 8);
39770dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP),
39780dbe28b3SPyun YongHyeon 	    sc->msk_rxqstart[sc_if->msk_port] / 8);
39790dbe28b3SPyun YongHyeon 
39800dbe28b3SPyun YongHyeon 	utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
39810dbe28b3SPyun YongHyeon 	    sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8;
39820dbe28b3SPyun YongHyeon 	ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 -
39830dbe28b3SPyun YongHyeon 	    sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8;
39840dbe28b3SPyun YongHyeon 	if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE)
39850dbe28b3SPyun YongHyeon 		ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8;
39860dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp);
39870dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp);
39880dbe28b3SPyun YongHyeon 	/* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */
39890dbe28b3SPyun YongHyeon 
39900dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD);
39910dbe28b3SPyun YongHyeon 	CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL));
39920dbe28b3SPyun YongHyeon 
39930dbe28b3SPyun YongHyeon 	/* Setup Tx Queue. */
39940dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR);
39950dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START),
39960dbe28b3SPyun YongHyeon 	    sc->msk_txqstart[sc_if->msk_port] / 8);
39970dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END),
39980dbe28b3SPyun YongHyeon 	    sc->msk_txqend[sc_if->msk_port] / 8);
39990dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP),
40000dbe28b3SPyun YongHyeon 	    sc->msk_txqstart[sc_if->msk_port] / 8);
40010dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP),
40020dbe28b3SPyun YongHyeon 	    sc->msk_txqstart[sc_if->msk_port] / 8);
40030dbe28b3SPyun YongHyeon 	/* Enable Store & Forward for Tx side. */
40040dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD);
40050dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD);
40060dbe28b3SPyun YongHyeon 	CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL));
40070dbe28b3SPyun YongHyeon }
40080dbe28b3SPyun YongHyeon 
40090dbe28b3SPyun YongHyeon static void
40100dbe28b3SPyun YongHyeon msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr,
40110dbe28b3SPyun YongHyeon     uint32_t count)
40120dbe28b3SPyun YongHyeon {
40130dbe28b3SPyun YongHyeon 
40140dbe28b3SPyun YongHyeon 	/* Reset the prefetch unit. */
40150dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
40160dbe28b3SPyun YongHyeon 	    PREF_UNIT_RST_SET);
40170dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
40180dbe28b3SPyun YongHyeon 	    PREF_UNIT_RST_CLR);
40190dbe28b3SPyun YongHyeon 	/* Set LE base address. */
40200dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG),
40210dbe28b3SPyun YongHyeon 	    MSK_ADDR_LO(addr));
40220dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG),
40230dbe28b3SPyun YongHyeon 	    MSK_ADDR_HI(addr));
40240dbe28b3SPyun YongHyeon 	/* Set the list last index. */
40250dbe28b3SPyun YongHyeon 	CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG),
40260dbe28b3SPyun YongHyeon 	    count);
40270dbe28b3SPyun YongHyeon 	/* Turn on prefetch unit. */
40280dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG),
40290dbe28b3SPyun YongHyeon 	    PREF_UNIT_OP_ON);
40300dbe28b3SPyun YongHyeon 	/* Dummy read to ensure write. */
40310dbe28b3SPyun YongHyeon 	CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG));
40320dbe28b3SPyun YongHyeon }
40330dbe28b3SPyun YongHyeon 
40340dbe28b3SPyun YongHyeon static void
40350dbe28b3SPyun YongHyeon msk_stop(struct msk_if_softc *sc_if)
40360dbe28b3SPyun YongHyeon {
40370dbe28b3SPyun YongHyeon 	struct msk_softc *sc;
40380dbe28b3SPyun YongHyeon 	struct msk_txdesc *txd;
40390dbe28b3SPyun YongHyeon 	struct msk_rxdesc *rxd;
40400dbe28b3SPyun YongHyeon 	struct msk_rxdesc *jrxd;
40410dbe28b3SPyun YongHyeon 	struct ifnet *ifp;
40420dbe28b3SPyun YongHyeon 	uint32_t val;
40430dbe28b3SPyun YongHyeon 	int i;
40440dbe28b3SPyun YongHyeon 
40450dbe28b3SPyun YongHyeon 	MSK_IF_LOCK_ASSERT(sc_if);
40460dbe28b3SPyun YongHyeon 	sc = sc_if->msk_softc;
40470dbe28b3SPyun YongHyeon 	ifp = sc_if->msk_ifp;
40480dbe28b3SPyun YongHyeon 
40490dbe28b3SPyun YongHyeon 	callout_stop(&sc_if->msk_tick_ch);
40502271eac7SPyun YongHyeon 	sc_if->msk_watchdog_timer = 0;
40510dbe28b3SPyun YongHyeon 
40520dbe28b3SPyun YongHyeon 	/* Disable interrupts. */
40530dbe28b3SPyun YongHyeon 	if (sc_if->msk_port == MSK_PORT_A) {
40540dbe28b3SPyun YongHyeon 		sc->msk_intrmask &= ~Y2_IS_PORT_A;
40550dbe28b3SPyun YongHyeon 		sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK;
40560dbe28b3SPyun YongHyeon 	} else {
40570dbe28b3SPyun YongHyeon 		sc->msk_intrmask &= ~Y2_IS_PORT_B;
40580dbe28b3SPyun YongHyeon 		sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK;
40590dbe28b3SPyun YongHyeon 	}
40600dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask);
40610dbe28b3SPyun YongHyeon 	CSR_READ_4(sc, B0_HWE_IMSK);
40620dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask);
40630dbe28b3SPyun YongHyeon 	CSR_READ_4(sc, B0_IMSK);
40640dbe28b3SPyun YongHyeon 
40650dbe28b3SPyun YongHyeon 	/* Disable Tx/Rx MAC. */
40660dbe28b3SPyun YongHyeon 	val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
40670dbe28b3SPyun YongHyeon 	val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
40680dbe28b3SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val);
40690dbe28b3SPyun YongHyeon 	/* Read again to ensure writing. */
40700dbe28b3SPyun YongHyeon 	GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL);
40713a91ee71SPyun YongHyeon 	/* Update stats and clear counters. */
40723a91ee71SPyun YongHyeon 	msk_stats_update(sc_if);
40730dbe28b3SPyun YongHyeon 
40740dbe28b3SPyun YongHyeon 	/* Stop Tx BMU. */
40750dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP);
40760dbe28b3SPyun YongHyeon 	val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
40770dbe28b3SPyun YongHyeon 	for (i = 0; i < MSK_TIMEOUT; i++) {
40780dbe28b3SPyun YongHyeon 		if ((val & (BMU_STOP | BMU_IDLE)) == 0) {
40790dbe28b3SPyun YongHyeon 			CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
40800dbe28b3SPyun YongHyeon 			    BMU_STOP);
4081e4816325SPyun YongHyeon 			val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR));
40820dbe28b3SPyun YongHyeon 		} else
40830dbe28b3SPyun YongHyeon 			break;
40840dbe28b3SPyun YongHyeon 		DELAY(1);
40850dbe28b3SPyun YongHyeon 	}
40860dbe28b3SPyun YongHyeon 	if (i == MSK_TIMEOUT)
40870dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n");
40880dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL),
40890dbe28b3SPyun YongHyeon 	    RB_RST_SET | RB_DIS_OP_MD);
40900dbe28b3SPyun YongHyeon 
40910dbe28b3SPyun YongHyeon 	/* Disable all GMAC interrupt. */
40920dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0);
40930dbe28b3SPyun YongHyeon 	/* Disable PHY interrupt. */
40940dbe28b3SPyun YongHyeon 	msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0);
40950dbe28b3SPyun YongHyeon 
40960dbe28b3SPyun YongHyeon 	/* Disable the RAM Interface Arbiter. */
40970dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB);
40980dbe28b3SPyun YongHyeon 
40990dbe28b3SPyun YongHyeon 	/* Reset the PCI FIFO of the async Tx queue */
41000dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR),
41010dbe28b3SPyun YongHyeon 	    BMU_RST_SET | BMU_FIFO_RST);
41020dbe28b3SPyun YongHyeon 
41030dbe28b3SPyun YongHyeon 	/* Reset the Tx prefetch units. */
41040dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG),
41050dbe28b3SPyun YongHyeon 	    PREF_UNIT_RST_SET);
41060dbe28b3SPyun YongHyeon 
41070dbe28b3SPyun YongHyeon 	/* Reset the RAM Buffer async Tx queue. */
41080dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET);
41090dbe28b3SPyun YongHyeon 
41100dbe28b3SPyun YongHyeon 	/* Reset Tx MAC FIFO. */
41110dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET);
41120dbe28b3SPyun YongHyeon 	/* Set Pause Off. */
41130dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF);
41140dbe28b3SPyun YongHyeon 
41150dbe28b3SPyun YongHyeon 	/*
41160dbe28b3SPyun YongHyeon 	 * The Rx Stop command will not work for Yukon-2 if the BMU does not
41170dbe28b3SPyun YongHyeon 	 * reach the end of packet and since we can't make sure that we have
41180dbe28b3SPyun YongHyeon 	 * incoming data, we must reset the BMU while it is not during a DMA
41190dbe28b3SPyun YongHyeon 	 * transfer. Since it is possible that the Rx path is still active,
41200dbe28b3SPyun YongHyeon 	 * the Rx RAM buffer will be stopped first, so any possible incoming
41210dbe28b3SPyun YongHyeon 	 * data will not trigger a DMA. After the RAM buffer is stopped, the
41220dbe28b3SPyun YongHyeon 	 * BMU is polled until any DMA in progress is ended and only then it
41230dbe28b3SPyun YongHyeon 	 * will be reset.
41240dbe28b3SPyun YongHyeon 	 */
41250dbe28b3SPyun YongHyeon 
41260dbe28b3SPyun YongHyeon 	/* Disable the RAM Buffer receive queue. */
41270dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD);
41280dbe28b3SPyun YongHyeon 	for (i = 0; i < MSK_TIMEOUT; i++) {
41290dbe28b3SPyun YongHyeon 		if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) ==
41300dbe28b3SPyun YongHyeon 		    CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL)))
41310dbe28b3SPyun YongHyeon 			break;
41320dbe28b3SPyun YongHyeon 		DELAY(1);
41330dbe28b3SPyun YongHyeon 	}
41340dbe28b3SPyun YongHyeon 	if (i == MSK_TIMEOUT)
41350dbe28b3SPyun YongHyeon 		device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n");
41360dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR),
41370dbe28b3SPyun YongHyeon 	    BMU_RST_SET | BMU_FIFO_RST);
41380dbe28b3SPyun YongHyeon 	/* Reset the Rx prefetch unit. */
41390dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG),
41400dbe28b3SPyun YongHyeon 	    PREF_UNIT_RST_SET);
41410dbe28b3SPyun YongHyeon 	/* Reset the RAM Buffer receive queue. */
41420dbe28b3SPyun YongHyeon 	CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET);
41430dbe28b3SPyun YongHyeon 	/* Reset Rx MAC FIFO. */
41440dbe28b3SPyun YongHyeon 	CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET);
41450dbe28b3SPyun YongHyeon 
41460dbe28b3SPyun YongHyeon 	/* Free Rx and Tx mbufs still in the queues. */
41470dbe28b3SPyun YongHyeon 	for (i = 0; i < MSK_RX_RING_CNT; i++) {
41480dbe28b3SPyun YongHyeon 		rxd = &sc_if->msk_cdata.msk_rxdesc[i];
41490dbe28b3SPyun YongHyeon 		if (rxd->rx_m != NULL) {
41500dbe28b3SPyun YongHyeon 			bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag,
41510dbe28b3SPyun YongHyeon 			    rxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
41520dbe28b3SPyun YongHyeon 			bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag,
41530dbe28b3SPyun YongHyeon 			    rxd->rx_dmamap);
41540dbe28b3SPyun YongHyeon 			m_freem(rxd->rx_m);
41550dbe28b3SPyun YongHyeon 			rxd->rx_m = NULL;
41560dbe28b3SPyun YongHyeon 		}
41570dbe28b3SPyun YongHyeon 	}
41580dbe28b3SPyun YongHyeon 	for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) {
41590dbe28b3SPyun YongHyeon 		jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i];
41600dbe28b3SPyun YongHyeon 		if (jrxd->rx_m != NULL) {
41610dbe28b3SPyun YongHyeon 			bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag,
41620dbe28b3SPyun YongHyeon 			    jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD);
41630dbe28b3SPyun YongHyeon 			bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag,
41640dbe28b3SPyun YongHyeon 			    jrxd->rx_dmamap);
41650dbe28b3SPyun YongHyeon 			m_freem(jrxd->rx_m);
41660dbe28b3SPyun YongHyeon 			jrxd->rx_m = NULL;
41670dbe28b3SPyun YongHyeon 		}
41680dbe28b3SPyun YongHyeon 	}
41690dbe28b3SPyun YongHyeon 	for (i = 0; i < MSK_TX_RING_CNT; i++) {
41700dbe28b3SPyun YongHyeon 		txd = &sc_if->msk_cdata.msk_txdesc[i];
41710dbe28b3SPyun YongHyeon 		if (txd->tx_m != NULL) {
41720dbe28b3SPyun YongHyeon 			bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag,
41730dbe28b3SPyun YongHyeon 			    txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
41740dbe28b3SPyun YongHyeon 			bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag,
41750dbe28b3SPyun YongHyeon 			    txd->tx_dmamap);
41760dbe28b3SPyun YongHyeon 			m_freem(txd->tx_m);
41770dbe28b3SPyun YongHyeon 			txd->tx_m = NULL;
41780dbe28b3SPyun YongHyeon 		}
41790dbe28b3SPyun YongHyeon 	}
41800dbe28b3SPyun YongHyeon 
41810dbe28b3SPyun YongHyeon 	/*
41820dbe28b3SPyun YongHyeon 	 * Mark the interface down.
41830dbe28b3SPyun YongHyeon 	 */
41840dbe28b3SPyun YongHyeon 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4185ab7df1e4SPyun YongHyeon 	sc_if->msk_flags &= ~MSK_FLAG_LINK;
41860dbe28b3SPyun YongHyeon }
41870dbe28b3SPyun YongHyeon 
41883a91ee71SPyun YongHyeon /*
41893a91ee71SPyun YongHyeon  * When GM_PAR_MIB_CLR bit of GM_PHY_ADDR is set, reading lower
41903a91ee71SPyun YongHyeon  * counter clears high 16 bits of the counter such that accessing
41913a91ee71SPyun YongHyeon  * lower 16 bits should be the last operation.
41923a91ee71SPyun YongHyeon  */
41933a91ee71SPyun YongHyeon #define	MSK_READ_MIB32(x, y)					\
41943a91ee71SPyun YongHyeon 	(((uint32_t)GMAC_READ_2(sc, x, (y) + 4)) << 16) +	\
41953a91ee71SPyun YongHyeon 	(uint32_t)GMAC_READ_2(sc, x, y)
41963a91ee71SPyun YongHyeon #define	MSK_READ_MIB64(x, y)					\
41973a91ee71SPyun YongHyeon 	(((uint64_t)MSK_READ_MIB32(x, (y) + 8)) << 32) +	\
41983a91ee71SPyun YongHyeon 	(uint64_t)MSK_READ_MIB32(x, y)
41993a91ee71SPyun YongHyeon 
42003a91ee71SPyun YongHyeon static void
42013a91ee71SPyun YongHyeon msk_stats_clear(struct msk_if_softc *sc_if)
42023a91ee71SPyun YongHyeon {
42033a91ee71SPyun YongHyeon 	struct msk_softc *sc;
42043a91ee71SPyun YongHyeon 	uint32_t reg;
42053a91ee71SPyun YongHyeon 	uint16_t gmac;
42063a91ee71SPyun YongHyeon 	int i;
42073a91ee71SPyun YongHyeon 
42083a91ee71SPyun YongHyeon 	MSK_IF_LOCK_ASSERT(sc_if);
42093a91ee71SPyun YongHyeon 
42103a91ee71SPyun YongHyeon 	sc = sc_if->msk_softc;
42113a91ee71SPyun YongHyeon 	/* Set MIB Clear Counter Mode. */
42123a91ee71SPyun YongHyeon 	gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
42133a91ee71SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
42143a91ee71SPyun YongHyeon 	/* Read all MIB Counters with Clear Mode set. */
421540d7192bSPyun YongHyeon 	for (i = GM_RXF_UC_OK; i <= GM_TXE_FIFO_UR; i += sizeof(uint32_t))
42163a91ee71SPyun YongHyeon 		reg = MSK_READ_MIB32(sc_if->msk_port, i);
42173a91ee71SPyun YongHyeon 	/* Clear MIB Clear Counter Mode. */
42183a91ee71SPyun YongHyeon 	gmac &= ~GM_PAR_MIB_CLR;
42193a91ee71SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
42203a91ee71SPyun YongHyeon }
42213a91ee71SPyun YongHyeon 
42223a91ee71SPyun YongHyeon static void
42233a91ee71SPyun YongHyeon msk_stats_update(struct msk_if_softc *sc_if)
42243a91ee71SPyun YongHyeon {
42253a91ee71SPyun YongHyeon 	struct msk_softc *sc;
42263a91ee71SPyun YongHyeon 	struct ifnet *ifp;
42273a91ee71SPyun YongHyeon 	struct msk_hw_stats *stats;
42283a91ee71SPyun YongHyeon 	uint16_t gmac;
42293a91ee71SPyun YongHyeon 	uint32_t reg;
42303a91ee71SPyun YongHyeon 
42313a91ee71SPyun YongHyeon 	MSK_IF_LOCK_ASSERT(sc_if);
42323a91ee71SPyun YongHyeon 
42333a91ee71SPyun YongHyeon 	ifp = sc_if->msk_ifp;
42343a91ee71SPyun YongHyeon 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
42353a91ee71SPyun YongHyeon 		return;
42363a91ee71SPyun YongHyeon 	sc = sc_if->msk_softc;
42373a91ee71SPyun YongHyeon 	stats = &sc_if->msk_stats;
42383a91ee71SPyun YongHyeon 	/* Set MIB Clear Counter Mode. */
42393a91ee71SPyun YongHyeon 	gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR);
42403a91ee71SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR);
42413a91ee71SPyun YongHyeon 
42423a91ee71SPyun YongHyeon 	/* Rx stats. */
42433a91ee71SPyun YongHyeon 	stats->rx_ucast_frames +=
42443a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_UC_OK);
42453a91ee71SPyun YongHyeon 	stats->rx_bcast_frames +=
42463a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_BC_OK);
42473a91ee71SPyun YongHyeon 	stats->rx_pause_frames +=
42483a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MPAUSE);
42493a91ee71SPyun YongHyeon 	stats->rx_mcast_frames +=
42503a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MC_OK);
42513a91ee71SPyun YongHyeon 	stats->rx_crc_errs +=
42523a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_FCS_ERR);
42533a91ee71SPyun YongHyeon 	reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE1);
42543a91ee71SPyun YongHyeon 	stats->rx_good_octets +=
42553a91ee71SPyun YongHyeon 	    MSK_READ_MIB64(sc_if->msk_port, GM_RXO_OK_LO);
42563a91ee71SPyun YongHyeon 	stats->rx_bad_octets +=
42573a91ee71SPyun YongHyeon 	    MSK_READ_MIB64(sc_if->msk_port, GM_RXO_ERR_LO);
42583a91ee71SPyun YongHyeon 	stats->rx_runts +=
42593a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SHT);
42603a91ee71SPyun YongHyeon 	stats->rx_runt_errs +=
42613a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FRAG);
42623a91ee71SPyun YongHyeon 	stats->rx_pkts_64 +=
42633a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_64B);
42643a91ee71SPyun YongHyeon 	stats->rx_pkts_65_127 +=
42653a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_127B);
42663a91ee71SPyun YongHyeon 	stats->rx_pkts_128_255 +=
42673a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_255B);
42683a91ee71SPyun YongHyeon 	stats->rx_pkts_256_511 +=
42693a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_511B);
42703a91ee71SPyun YongHyeon 	stats->rx_pkts_512_1023 +=
42713a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1023B);
42723a91ee71SPyun YongHyeon 	stats->rx_pkts_1024_1518 +=
42733a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_1518B);
42743a91ee71SPyun YongHyeon 	stats->rx_pkts_1519_max +=
42753a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_MAX_SZ);
42763a91ee71SPyun YongHyeon 	stats->rx_pkts_too_long +=
42773a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_LNG_ERR);
42783a91ee71SPyun YongHyeon 	stats->rx_pkts_jabbers +=
42793a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXF_JAB_PKT);
42803a91ee71SPyun YongHyeon 	reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE2);
42813a91ee71SPyun YongHyeon 	stats->rx_fifo_oflows +=
42823a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_RXE_FIFO_OV);
42833a91ee71SPyun YongHyeon 	reg = MSK_READ_MIB32(sc_if->msk_port, GM_RXF_SPARE3);
42843a91ee71SPyun YongHyeon 
42853a91ee71SPyun YongHyeon 	/* Tx stats. */
42863a91ee71SPyun YongHyeon 	stats->tx_ucast_frames +=
42873a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_UC_OK);
42883a91ee71SPyun YongHyeon 	stats->tx_bcast_frames +=
42893a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_BC_OK);
42903a91ee71SPyun YongHyeon 	stats->tx_pause_frames +=
42913a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MPAUSE);
42923a91ee71SPyun YongHyeon 	stats->tx_mcast_frames +=
42933a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MC_OK);
42943a91ee71SPyun YongHyeon 	stats->tx_octets +=
42953a91ee71SPyun YongHyeon 	    MSK_READ_MIB64(sc_if->msk_port, GM_TXO_OK_LO);
42963a91ee71SPyun YongHyeon 	stats->tx_pkts_64 +=
42973a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_64B);
42983a91ee71SPyun YongHyeon 	stats->tx_pkts_65_127 +=
42993a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_127B);
43003a91ee71SPyun YongHyeon 	stats->tx_pkts_128_255 +=
43013a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_255B);
43023a91ee71SPyun YongHyeon 	stats->tx_pkts_256_511 +=
43033a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_511B);
43043a91ee71SPyun YongHyeon 	stats->tx_pkts_512_1023 +=
43053a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1023B);
43063a91ee71SPyun YongHyeon 	stats->tx_pkts_1024_1518 +=
43073a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_1518B);
43083a91ee71SPyun YongHyeon 	stats->tx_pkts_1519_max +=
43093a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MAX_SZ);
43103a91ee71SPyun YongHyeon 	reg = MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SPARE1);
43113a91ee71SPyun YongHyeon 	stats->tx_colls +=
43123a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_COL);
43133a91ee71SPyun YongHyeon 	stats->tx_late_colls +=
43143a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_LAT_COL);
43153a91ee71SPyun YongHyeon 	stats->tx_excess_colls +=
43163a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_ABO_COL);
43173a91ee71SPyun YongHyeon 	stats->tx_multi_colls +=
43183a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_MUL_COL);
43193a91ee71SPyun YongHyeon 	stats->tx_single_colls +=
43203a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXF_SNG_COL);
43213a91ee71SPyun YongHyeon 	stats->tx_underflows +=
43223a91ee71SPyun YongHyeon 	    MSK_READ_MIB32(sc_if->msk_port, GM_TXE_FIFO_UR);
43233a91ee71SPyun YongHyeon 	/* Clear MIB Clear Counter Mode. */
43243a91ee71SPyun YongHyeon 	gmac &= ~GM_PAR_MIB_CLR;
43253a91ee71SPyun YongHyeon 	GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac);
43263a91ee71SPyun YongHyeon }
43273a91ee71SPyun YongHyeon 
43283a91ee71SPyun YongHyeon static int
43293a91ee71SPyun YongHyeon msk_sysctl_stat32(SYSCTL_HANDLER_ARGS)
43303a91ee71SPyun YongHyeon {
43313a91ee71SPyun YongHyeon 	struct msk_softc *sc;
43323a91ee71SPyun YongHyeon 	struct msk_if_softc *sc_if;
43333a91ee71SPyun YongHyeon 	uint32_t result, *stat;
43343a91ee71SPyun YongHyeon 	int off;
43353a91ee71SPyun YongHyeon 
43363a91ee71SPyun YongHyeon 	sc_if = (struct msk_if_softc *)arg1;
43373a91ee71SPyun YongHyeon 	sc = sc_if->msk_softc;
43383a91ee71SPyun YongHyeon 	off = arg2;
43393a91ee71SPyun YongHyeon 	stat = (uint32_t *)((uint8_t *)&sc_if->msk_stats + off);
43403a91ee71SPyun YongHyeon 
43413a91ee71SPyun YongHyeon 	MSK_IF_LOCK(sc_if);
43423a91ee71SPyun YongHyeon 	result = MSK_READ_MIB32(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2);
43433a91ee71SPyun YongHyeon 	result += *stat;
43443a91ee71SPyun YongHyeon 	MSK_IF_UNLOCK(sc_if);
43453a91ee71SPyun YongHyeon 
43463a91ee71SPyun YongHyeon 	return (sysctl_handle_int(oidp, &result, 0, req));
43473a91ee71SPyun YongHyeon }
43483a91ee71SPyun YongHyeon 
43493a91ee71SPyun YongHyeon static int
43503a91ee71SPyun YongHyeon msk_sysctl_stat64(SYSCTL_HANDLER_ARGS)
43513a91ee71SPyun YongHyeon {
43523a91ee71SPyun YongHyeon 	struct msk_softc *sc;
43533a91ee71SPyun YongHyeon 	struct msk_if_softc *sc_if;
43543a91ee71SPyun YongHyeon 	uint64_t result, *stat;
43553a91ee71SPyun YongHyeon 	int off;
43563a91ee71SPyun YongHyeon 
43573a91ee71SPyun YongHyeon 	sc_if = (struct msk_if_softc *)arg1;
43583a91ee71SPyun YongHyeon 	sc = sc_if->msk_softc;
43593a91ee71SPyun YongHyeon 	off = arg2;
43603a91ee71SPyun YongHyeon 	stat = (uint64_t *)((uint8_t *)&sc_if->msk_stats + off);
43613a91ee71SPyun YongHyeon 
43623a91ee71SPyun YongHyeon 	MSK_IF_LOCK(sc_if);
43633a91ee71SPyun YongHyeon 	result = MSK_READ_MIB64(sc_if->msk_port, GM_MIB_CNT_BASE + off * 2);
43643a91ee71SPyun YongHyeon 	result += *stat;
43653a91ee71SPyun YongHyeon 	MSK_IF_UNLOCK(sc_if);
43663a91ee71SPyun YongHyeon 
4367cbc134adSMatthew D Fleming 	return (sysctl_handle_64(oidp, &result, 0, req));
43683a91ee71SPyun YongHyeon }
43693a91ee71SPyun YongHyeon 
43703a91ee71SPyun YongHyeon #undef MSK_READ_MIB32
43713a91ee71SPyun YongHyeon #undef MSK_READ_MIB64
43723a91ee71SPyun YongHyeon 
43733a91ee71SPyun YongHyeon #define MSK_SYSCTL_STAT32(sc, c, o, p, n, d) 				\
43743a91ee71SPyun YongHyeon 	SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_UINT | CTLFLAG_RD, 	\
43753a91ee71SPyun YongHyeon 	    sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat32,	\
43763a91ee71SPyun YongHyeon 	    "IU", d)
43773a91ee71SPyun YongHyeon #define MSK_SYSCTL_STAT64(sc, c, o, p, n, d) 				\
4378cbc134adSMatthew D Fleming 	SYSCTL_ADD_PROC(c, p, OID_AUTO, o, CTLTYPE_U64 | CTLFLAG_RD, 	\
43793a91ee71SPyun YongHyeon 	    sc, offsetof(struct msk_hw_stats, n), msk_sysctl_stat64,	\
4380cbc134adSMatthew D Fleming 	    "QU", d)
43813a91ee71SPyun YongHyeon 
43823a91ee71SPyun YongHyeon static void
43833a91ee71SPyun YongHyeon msk_sysctl_node(struct msk_if_softc *sc_if)
43843a91ee71SPyun YongHyeon {
43853a91ee71SPyun YongHyeon 	struct sysctl_ctx_list *ctx;
43863a91ee71SPyun YongHyeon 	struct sysctl_oid_list *child, *schild;
43873a91ee71SPyun YongHyeon 	struct sysctl_oid *tree;
43883a91ee71SPyun YongHyeon 
43893a91ee71SPyun YongHyeon 	ctx = device_get_sysctl_ctx(sc_if->msk_if_dev);
43903a91ee71SPyun YongHyeon 	child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc_if->msk_if_dev));
43913a91ee71SPyun YongHyeon 
43923a91ee71SPyun YongHyeon 	tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
43933a91ee71SPyun YongHyeon 	    NULL, "MSK Statistics");
43943a91ee71SPyun YongHyeon 	schild = child = SYSCTL_CHILDREN(tree);
43953a91ee71SPyun YongHyeon 	tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "rx", CTLFLAG_RD,
43963a91ee71SPyun YongHyeon 	    NULL, "MSK RX Statistics");
43973a91ee71SPyun YongHyeon 	child = SYSCTL_CHILDREN(tree);
43983a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames",
43993a91ee71SPyun YongHyeon 	    child, rx_ucast_frames, "Good unicast frames");
44003a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames",
44013a91ee71SPyun YongHyeon 	    child, rx_bcast_frames, "Good broadcast frames");
44023a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames",
44033a91ee71SPyun YongHyeon 	    child, rx_pause_frames, "Pause frames");
44043a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames",
44053a91ee71SPyun YongHyeon 	    child, rx_mcast_frames, "Multicast frames");
44063a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "crc_errs",
44073a91ee71SPyun YongHyeon 	    child, rx_crc_errs, "CRC errors");
44083a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT64(sc_if, ctx, "good_octets",
44093a91ee71SPyun YongHyeon 	    child, rx_good_octets, "Good octets");
44103a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT64(sc_if, ctx, "bad_octets",
44113a91ee71SPyun YongHyeon 	    child, rx_bad_octets, "Bad octets");
44123a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64",
44133a91ee71SPyun YongHyeon 	    child, rx_pkts_64, "64 bytes frames");
44143a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127",
44153a91ee71SPyun YongHyeon 	    child, rx_pkts_65_127, "65 to 127 bytes frames");
44163a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255",
44173a91ee71SPyun YongHyeon 	    child, rx_pkts_128_255, "128 to 255 bytes frames");
44183a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511",
44193a91ee71SPyun YongHyeon 	    child, rx_pkts_256_511, "256 to 511 bytes frames");
44203a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023",
44213a91ee71SPyun YongHyeon 	    child, rx_pkts_512_1023, "512 to 1023 bytes frames");
44223a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518",
44233a91ee71SPyun YongHyeon 	    child, rx_pkts_1024_1518, "1024 to 1518 bytes frames");
44243a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max",
44253a91ee71SPyun YongHyeon 	    child, rx_pkts_1519_max, "1519 to max frames");
44263a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_too_long",
44273a91ee71SPyun YongHyeon 	    child, rx_pkts_too_long, "frames too long");
44283a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "jabbers",
44293a91ee71SPyun YongHyeon 	    child, rx_pkts_jabbers, "Jabber errors");
443079dd979aSPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "overflows",
44313a91ee71SPyun YongHyeon 	    child, rx_fifo_oflows, "FIFO overflows");
44323a91ee71SPyun YongHyeon 
44333a91ee71SPyun YongHyeon 	tree = SYSCTL_ADD_NODE(ctx, schild, OID_AUTO, "tx", CTLFLAG_RD,
44343a91ee71SPyun YongHyeon 	    NULL, "MSK TX Statistics");
44353a91ee71SPyun YongHyeon 	child = SYSCTL_CHILDREN(tree);
44363a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "ucast_frames",
44373a91ee71SPyun YongHyeon 	    child, tx_ucast_frames, "Unicast frames");
44383a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "bcast_frames",
44393a91ee71SPyun YongHyeon 	    child, tx_bcast_frames, "Broadcast frames");
44403a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "pause_frames",
44413a91ee71SPyun YongHyeon 	    child, tx_pause_frames, "Pause frames");
44423a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "mcast_frames",
44433a91ee71SPyun YongHyeon 	    child, tx_mcast_frames, "Multicast frames");
44443a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT64(sc_if, ctx, "octets",
44453a91ee71SPyun YongHyeon 	    child, tx_octets, "Octets");
44463a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_64",
44473a91ee71SPyun YongHyeon 	    child, tx_pkts_64, "64 bytes frames");
44483a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_65_127",
44493a91ee71SPyun YongHyeon 	    child, tx_pkts_65_127, "65 to 127 bytes frames");
44503a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_128_255",
44513a91ee71SPyun YongHyeon 	    child, tx_pkts_128_255, "128 to 255 bytes frames");
44523a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_256_511",
44533a91ee71SPyun YongHyeon 	    child, tx_pkts_256_511, "256 to 511 bytes frames");
44543a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_512_1023",
44553a91ee71SPyun YongHyeon 	    child, tx_pkts_512_1023, "512 to 1023 bytes frames");
44563a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1024_1518",
44573a91ee71SPyun YongHyeon 	    child, tx_pkts_1024_1518, "1024 to 1518 bytes frames");
44583a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "frames_1519_max",
44593a91ee71SPyun YongHyeon 	    child, tx_pkts_1519_max, "1519 to max frames");
44603a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "colls",
44613a91ee71SPyun YongHyeon 	    child, tx_colls, "Collisions");
44623a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "late_colls",
44633a91ee71SPyun YongHyeon 	    child, tx_late_colls, "Late collisions");
44643a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "excess_colls",
44653a91ee71SPyun YongHyeon 	    child, tx_excess_colls, "Excessive collisions");
44663a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "multi_colls",
44673a91ee71SPyun YongHyeon 	    child, tx_multi_colls, "Multiple collisions");
44683a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "single_colls",
44693a91ee71SPyun YongHyeon 	    child, tx_single_colls, "Single collisions");
44703a91ee71SPyun YongHyeon 	MSK_SYSCTL_STAT32(sc_if, ctx, "underflows",
44713a91ee71SPyun YongHyeon 	    child, tx_underflows, "FIFO underflows");
44723a91ee71SPyun YongHyeon }
44733a91ee71SPyun YongHyeon 
44743a91ee71SPyun YongHyeon #undef MSK_SYSCTL_STAT32
44753a91ee71SPyun YongHyeon #undef MSK_SYSCTL_STAT64
44763a91ee71SPyun YongHyeon 
44770dbe28b3SPyun YongHyeon static int
44780dbe28b3SPyun YongHyeon sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
44790dbe28b3SPyun YongHyeon {
44800dbe28b3SPyun YongHyeon 	int error, value;
44810dbe28b3SPyun YongHyeon 
44820dbe28b3SPyun YongHyeon 	if (!arg1)
44830dbe28b3SPyun YongHyeon 		return (EINVAL);
44840dbe28b3SPyun YongHyeon 	value = *(int *)arg1;
44850dbe28b3SPyun YongHyeon 	error = sysctl_handle_int(oidp, &value, 0, req);
44860dbe28b3SPyun YongHyeon 	if (error || !req->newptr)
44870dbe28b3SPyun YongHyeon 		return (error);
44880dbe28b3SPyun YongHyeon 	if (value < low || value > high)
44890dbe28b3SPyun YongHyeon 		return (EINVAL);
44900dbe28b3SPyun YongHyeon 	*(int *)arg1 = value;
44910dbe28b3SPyun YongHyeon 
44920dbe28b3SPyun YongHyeon 	return (0);
44930dbe28b3SPyun YongHyeon }
44940dbe28b3SPyun YongHyeon 
44950dbe28b3SPyun YongHyeon static int
44960dbe28b3SPyun YongHyeon sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS)
44970dbe28b3SPyun YongHyeon {
44980dbe28b3SPyun YongHyeon 
44990dbe28b3SPyun YongHyeon 	return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN,
45000dbe28b3SPyun YongHyeon 	    MSK_PROC_MAX));
45010dbe28b3SPyun YongHyeon }
4502