10dbe28b3SPyun YongHyeon /****************************************************************************** 20dbe28b3SPyun YongHyeon * 30dbe28b3SPyun YongHyeon * Name : sky2.c 40dbe28b3SPyun YongHyeon * Project: Gigabit Ethernet Driver for FreeBSD 5.x/6.x 50dbe28b3SPyun YongHyeon * Version: $Revision: 1.23 $ 60dbe28b3SPyun YongHyeon * Date : $Date: 2005/12/22 09:04:11 $ 70dbe28b3SPyun YongHyeon * Purpose: Main driver source file 80dbe28b3SPyun YongHyeon * 90dbe28b3SPyun YongHyeon *****************************************************************************/ 100dbe28b3SPyun YongHyeon 110dbe28b3SPyun YongHyeon /****************************************************************************** 120dbe28b3SPyun YongHyeon * 130dbe28b3SPyun YongHyeon * LICENSE: 140dbe28b3SPyun YongHyeon * Copyright (C) Marvell International Ltd. and/or its affiliates 150dbe28b3SPyun YongHyeon * 160dbe28b3SPyun YongHyeon * The computer program files contained in this folder ("Files") 170dbe28b3SPyun YongHyeon * are provided to you under the BSD-type license terms provided 180dbe28b3SPyun YongHyeon * below, and any use of such Files and any derivative works 190dbe28b3SPyun YongHyeon * thereof created by you shall be governed by the following terms 200dbe28b3SPyun YongHyeon * and conditions: 210dbe28b3SPyun YongHyeon * 220dbe28b3SPyun YongHyeon * - Redistributions of source code must retain the above copyright 230dbe28b3SPyun YongHyeon * notice, this list of conditions and the following disclaimer. 240dbe28b3SPyun YongHyeon * - Redistributions in binary form must reproduce the above 250dbe28b3SPyun YongHyeon * copyright notice, this list of conditions and the following 260dbe28b3SPyun YongHyeon * disclaimer in the documentation and/or other materials provided 270dbe28b3SPyun YongHyeon * with the distribution. 280dbe28b3SPyun YongHyeon * - Neither the name of Marvell nor the names of its contributors 290dbe28b3SPyun YongHyeon * may be used to endorse or promote products derived from this 300dbe28b3SPyun YongHyeon * software without specific prior written permission. 310dbe28b3SPyun YongHyeon * 320dbe28b3SPyun YongHyeon * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 330dbe28b3SPyun YongHyeon * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 340dbe28b3SPyun YongHyeon * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 350dbe28b3SPyun YongHyeon * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 360dbe28b3SPyun YongHyeon * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 370dbe28b3SPyun YongHyeon * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 380dbe28b3SPyun YongHyeon * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 390dbe28b3SPyun YongHyeon * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 400dbe28b3SPyun YongHyeon * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 410dbe28b3SPyun YongHyeon * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 420dbe28b3SPyun YongHyeon * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED 430dbe28b3SPyun YongHyeon * OF THE POSSIBILITY OF SUCH DAMAGE. 440dbe28b3SPyun YongHyeon * /LICENSE 450dbe28b3SPyun YongHyeon * 460dbe28b3SPyun YongHyeon *****************************************************************************/ 470dbe28b3SPyun YongHyeon 480dbe28b3SPyun YongHyeon /*- 490dbe28b3SPyun YongHyeon * Copyright (c) 1997, 1998, 1999, 2000 500dbe28b3SPyun YongHyeon * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 510dbe28b3SPyun YongHyeon * 520dbe28b3SPyun YongHyeon * Redistribution and use in source and binary forms, with or without 530dbe28b3SPyun YongHyeon * modification, are permitted provided that the following conditions 540dbe28b3SPyun YongHyeon * are met: 550dbe28b3SPyun YongHyeon * 1. Redistributions of source code must retain the above copyright 560dbe28b3SPyun YongHyeon * notice, this list of conditions and the following disclaimer. 570dbe28b3SPyun YongHyeon * 2. Redistributions in binary form must reproduce the above copyright 580dbe28b3SPyun YongHyeon * notice, this list of conditions and the following disclaimer in the 590dbe28b3SPyun YongHyeon * documentation and/or other materials provided with the distribution. 600dbe28b3SPyun YongHyeon * 3. All advertising materials mentioning features or use of this software 610dbe28b3SPyun YongHyeon * must display the following acknowledgement: 620dbe28b3SPyun YongHyeon * This product includes software developed by Bill Paul. 630dbe28b3SPyun YongHyeon * 4. Neither the name of the author nor the names of any co-contributors 640dbe28b3SPyun YongHyeon * may be used to endorse or promote products derived from this software 650dbe28b3SPyun YongHyeon * without specific prior written permission. 660dbe28b3SPyun YongHyeon * 670dbe28b3SPyun YongHyeon * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 680dbe28b3SPyun YongHyeon * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 690dbe28b3SPyun YongHyeon * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 700dbe28b3SPyun YongHyeon * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 710dbe28b3SPyun YongHyeon * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 720dbe28b3SPyun YongHyeon * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 730dbe28b3SPyun YongHyeon * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 740dbe28b3SPyun YongHyeon * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 750dbe28b3SPyun YongHyeon * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 760dbe28b3SPyun YongHyeon * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 770dbe28b3SPyun YongHyeon * THE POSSIBILITY OF SUCH DAMAGE. 780dbe28b3SPyun YongHyeon */ 790dbe28b3SPyun YongHyeon /*- 800dbe28b3SPyun YongHyeon * Copyright (c) 2003 Nathan L. Binkert <binkertn@umich.edu> 810dbe28b3SPyun YongHyeon * 820dbe28b3SPyun YongHyeon * Permission to use, copy, modify, and distribute this software for any 830dbe28b3SPyun YongHyeon * purpose with or without fee is hereby granted, provided that the above 840dbe28b3SPyun YongHyeon * copyright notice and this permission notice appear in all copies. 850dbe28b3SPyun YongHyeon * 860dbe28b3SPyun YongHyeon * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 870dbe28b3SPyun YongHyeon * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 880dbe28b3SPyun YongHyeon * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 890dbe28b3SPyun YongHyeon * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 900dbe28b3SPyun YongHyeon * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 910dbe28b3SPyun YongHyeon * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 920dbe28b3SPyun YongHyeon * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 930dbe28b3SPyun YongHyeon */ 940dbe28b3SPyun YongHyeon 950dbe28b3SPyun YongHyeon /* 960dbe28b3SPyun YongHyeon * Device driver for the Marvell Yukon II Ethernet controller. 970dbe28b3SPyun YongHyeon * Due to lack of documentation, this driver is based on the code from 980dbe28b3SPyun YongHyeon * sk(4) and Marvell's myk(4) driver for FreeBSD 5.x. 990dbe28b3SPyun YongHyeon */ 1000dbe28b3SPyun YongHyeon 1010dbe28b3SPyun YongHyeon #include <sys/cdefs.h> 1020dbe28b3SPyun YongHyeon __FBSDID("$FreeBSD$"); 1030dbe28b3SPyun YongHyeon 1040dbe28b3SPyun YongHyeon #include <sys/param.h> 1050dbe28b3SPyun YongHyeon #include <sys/systm.h> 1060dbe28b3SPyun YongHyeon #include <sys/bus.h> 1070dbe28b3SPyun YongHyeon #include <sys/endian.h> 1080dbe28b3SPyun YongHyeon #include <sys/mbuf.h> 1090dbe28b3SPyun YongHyeon #include <sys/malloc.h> 1100dbe28b3SPyun YongHyeon #include <sys/kernel.h> 1110dbe28b3SPyun YongHyeon #include <sys/module.h> 1120dbe28b3SPyun YongHyeon #include <sys/socket.h> 1130dbe28b3SPyun YongHyeon #include <sys/sockio.h> 1140dbe28b3SPyun YongHyeon #include <sys/queue.h> 1150dbe28b3SPyun YongHyeon #include <sys/sysctl.h> 1160dbe28b3SPyun YongHyeon #include <sys/taskqueue.h> 1170dbe28b3SPyun YongHyeon 1180dbe28b3SPyun YongHyeon #include <net/bpf.h> 1190dbe28b3SPyun YongHyeon #include <net/ethernet.h> 1200dbe28b3SPyun YongHyeon #include <net/if.h> 1210dbe28b3SPyun YongHyeon #include <net/if_arp.h> 1220dbe28b3SPyun YongHyeon #include <net/if_dl.h> 1230dbe28b3SPyun YongHyeon #include <net/if_media.h> 1240dbe28b3SPyun YongHyeon #include <net/if_types.h> 1250dbe28b3SPyun YongHyeon #include <net/if_vlan_var.h> 1260dbe28b3SPyun YongHyeon 1270dbe28b3SPyun YongHyeon #include <netinet/in.h> 1280dbe28b3SPyun YongHyeon #include <netinet/in_systm.h> 1290dbe28b3SPyun YongHyeon #include <netinet/ip.h> 1300dbe28b3SPyun YongHyeon #include <netinet/tcp.h> 1310dbe28b3SPyun YongHyeon #include <netinet/udp.h> 1320dbe28b3SPyun YongHyeon 1330dbe28b3SPyun YongHyeon #include <machine/bus.h> 134b5898b80SPyun YongHyeon #include <machine/in_cksum.h> 1350dbe28b3SPyun YongHyeon #include <machine/resource.h> 1360dbe28b3SPyun YongHyeon #include <sys/rman.h> 1370dbe28b3SPyun YongHyeon 1380dbe28b3SPyun YongHyeon #include <dev/mii/mii.h> 1390dbe28b3SPyun YongHyeon #include <dev/mii/miivar.h> 1400dbe28b3SPyun YongHyeon #include <dev/mii/brgphyreg.h> 1410dbe28b3SPyun YongHyeon 1420dbe28b3SPyun YongHyeon #include <dev/pci/pcireg.h> 1430dbe28b3SPyun YongHyeon #include <dev/pci/pcivar.h> 1440dbe28b3SPyun YongHyeon 1450dbe28b3SPyun YongHyeon #include <dev/msk/if_mskreg.h> 1460dbe28b3SPyun YongHyeon 1470dbe28b3SPyun YongHyeon MODULE_DEPEND(msk, pci, 1, 1, 1); 1480dbe28b3SPyun YongHyeon MODULE_DEPEND(msk, ether, 1, 1, 1); 1490dbe28b3SPyun YongHyeon MODULE_DEPEND(msk, miibus, 1, 1, 1); 1500dbe28b3SPyun YongHyeon 1510dbe28b3SPyun YongHyeon /* "device miibus" required. See GENERIC if you get errors here. */ 1520dbe28b3SPyun YongHyeon #include "miibus_if.h" 1530dbe28b3SPyun YongHyeon 1540dbe28b3SPyun YongHyeon /* Tunables. */ 1550dbe28b3SPyun YongHyeon static int msi_disable = 0; 1560dbe28b3SPyun YongHyeon TUNABLE_INT("hw.msk.msi_disable", &msi_disable); 15753dcfbd1SPyun YongHyeon static int legacy_intr = 0; 15853dcfbd1SPyun YongHyeon TUNABLE_INT("hw.msk.legacy_intr", &legacy_intr); 1590dbe28b3SPyun YongHyeon 1600dbe28b3SPyun YongHyeon #define MSK_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 1610dbe28b3SPyun YongHyeon 1620dbe28b3SPyun YongHyeon /* 1630dbe28b3SPyun YongHyeon * Devices supported by this driver. 1640dbe28b3SPyun YongHyeon */ 1650dbe28b3SPyun YongHyeon static struct msk_product { 1660dbe28b3SPyun YongHyeon uint16_t msk_vendorid; 1670dbe28b3SPyun YongHyeon uint16_t msk_deviceid; 1680dbe28b3SPyun YongHyeon const char *msk_name; 1690dbe28b3SPyun YongHyeon } msk_products[] = { 1700dbe28b3SPyun YongHyeon { VENDORID_SK, DEVICEID_SK_YUKON2, 1710dbe28b3SPyun YongHyeon "SK-9Sxx Gigabit Ethernet" }, 1720dbe28b3SPyun YongHyeon { VENDORID_SK, DEVICEID_SK_YUKON2_EXPR, 1730dbe28b3SPyun YongHyeon "SK-9Exx Gigabit Ethernet"}, 1740dbe28b3SPyun YongHyeon { VENDORID_MARVELL, DEVICEID_MRVL_8021CU, 1750dbe28b3SPyun YongHyeon "Marvell Yukon 88E8021CU Gigabit Ethernet" }, 1760dbe28b3SPyun YongHyeon { VENDORID_MARVELL, DEVICEID_MRVL_8021X, 1770dbe28b3SPyun YongHyeon "Marvell Yukon 88E8021 SX/LX Gigabit Ethernet" }, 1780dbe28b3SPyun YongHyeon { VENDORID_MARVELL, DEVICEID_MRVL_8022CU, 1790dbe28b3SPyun YongHyeon "Marvell Yukon 88E8022CU Gigabit Ethernet" }, 1800dbe28b3SPyun YongHyeon { VENDORID_MARVELL, DEVICEID_MRVL_8022X, 1810dbe28b3SPyun YongHyeon "Marvell Yukon 88E8022 SX/LX Gigabit Ethernet" }, 1820dbe28b3SPyun YongHyeon { VENDORID_MARVELL, DEVICEID_MRVL_8061CU, 1830dbe28b3SPyun YongHyeon "Marvell Yukon 88E8061CU Gigabit Ethernet" }, 1840dbe28b3SPyun YongHyeon { VENDORID_MARVELL, DEVICEID_MRVL_8061X, 1850dbe28b3SPyun YongHyeon "Marvell Yukon 88E8061 SX/LX Gigabit Ethernet" }, 1860dbe28b3SPyun YongHyeon { VENDORID_MARVELL, DEVICEID_MRVL_8062CU, 1870dbe28b3SPyun YongHyeon "Marvell Yukon 88E8062CU Gigabit Ethernet" }, 1880dbe28b3SPyun YongHyeon { VENDORID_MARVELL, DEVICEID_MRVL_8062X, 1890dbe28b3SPyun YongHyeon "Marvell Yukon 88E8062 SX/LX Gigabit Ethernet" }, 1900dbe28b3SPyun YongHyeon { VENDORID_MARVELL, DEVICEID_MRVL_8035, 1910dbe28b3SPyun YongHyeon "Marvell Yukon 88E8035 Gigabit Ethernet" }, 1920dbe28b3SPyun YongHyeon { VENDORID_MARVELL, DEVICEID_MRVL_8036, 1930dbe28b3SPyun YongHyeon "Marvell Yukon 88E8036 Gigabit Ethernet" }, 1940dbe28b3SPyun YongHyeon { VENDORID_MARVELL, DEVICEID_MRVL_8038, 1950dbe28b3SPyun YongHyeon "Marvell Yukon 88E8038 Gigabit Ethernet" }, 19628d34c0eSRemko Lodder { VENDORID_MARVELL, DEVICEID_MRVL_8039, 19728d34c0eSRemko Lodder "Marvell Yukon 88E8039 Gigabit Ethernet" }, 1980dbe28b3SPyun YongHyeon { VENDORID_MARVELL, DEVICEID_MRVL_4361, 1990dbe28b3SPyun YongHyeon "Marvell Yukon 88E8050 Gigabit Ethernet" }, 2000dbe28b3SPyun YongHyeon { VENDORID_MARVELL, DEVICEID_MRVL_4360, 2010dbe28b3SPyun YongHyeon "Marvell Yukon 88E8052 Gigabit Ethernet" }, 2020dbe28b3SPyun YongHyeon { VENDORID_MARVELL, DEVICEID_MRVL_4362, 2030dbe28b3SPyun YongHyeon "Marvell Yukon 88E8053 Gigabit Ethernet" }, 2040dbe28b3SPyun YongHyeon { VENDORID_MARVELL, DEVICEID_MRVL_4363, 2050dbe28b3SPyun YongHyeon "Marvell Yukon 88E8055 Gigabit Ethernet" }, 2060dbe28b3SPyun YongHyeon { VENDORID_MARVELL, DEVICEID_MRVL_4364, 2070dbe28b3SPyun YongHyeon "Marvell Yukon 88E8056 Gigabit Ethernet" }, 20875ef16dfSPyun YongHyeon { VENDORID_MARVELL, DEVICEID_MRVL_436A, 20975ef16dfSPyun YongHyeon "Marvell Yukon 88E8058 Gigabit Ethernet" }, 2100dbe28b3SPyun YongHyeon { VENDORID_DLINK, DEVICEID_DLINK_DGE550SX, 2110dbe28b3SPyun YongHyeon "D-Link 550SX Gigabit Ethernet" }, 2120dbe28b3SPyun YongHyeon { VENDORID_DLINK, DEVICEID_DLINK_DGE560T, 2130dbe28b3SPyun YongHyeon "D-Link 560T Gigabit Ethernet" } 2140dbe28b3SPyun YongHyeon }; 2150dbe28b3SPyun YongHyeon 2160dbe28b3SPyun YongHyeon static const char *model_name[] = { 2170dbe28b3SPyun YongHyeon "Yukon XL", 2180dbe28b3SPyun YongHyeon "Yukon EC Ultra", 2190dbe28b3SPyun YongHyeon "Yukon Unknown", 2200dbe28b3SPyun YongHyeon "Yukon EC", 2210dbe28b3SPyun YongHyeon "Yukon FE" 2220dbe28b3SPyun YongHyeon }; 2230dbe28b3SPyun YongHyeon 2240dbe28b3SPyun YongHyeon static int mskc_probe(device_t); 2250dbe28b3SPyun YongHyeon static int mskc_attach(device_t); 2260dbe28b3SPyun YongHyeon static int mskc_detach(device_t); 2276a087a87SPyun YongHyeon static int mskc_shutdown(device_t); 2280dbe28b3SPyun YongHyeon static int mskc_setup_rambuffer(struct msk_softc *); 2290dbe28b3SPyun YongHyeon static int mskc_suspend(device_t); 2300dbe28b3SPyun YongHyeon static int mskc_resume(device_t); 2310dbe28b3SPyun YongHyeon static void mskc_reset(struct msk_softc *); 2320dbe28b3SPyun YongHyeon 2330dbe28b3SPyun YongHyeon static int msk_probe(device_t); 2340dbe28b3SPyun YongHyeon static int msk_attach(device_t); 2350dbe28b3SPyun YongHyeon static int msk_detach(device_t); 2360dbe28b3SPyun YongHyeon 2370dbe28b3SPyun YongHyeon static void msk_tick(void *); 23853dcfbd1SPyun YongHyeon static void msk_legacy_intr(void *); 239ef544f63SPaolo Pisati static int msk_intr(void *); 2400dbe28b3SPyun YongHyeon static void msk_int_task(void *, int); 2410dbe28b3SPyun YongHyeon static void msk_intr_phy(struct msk_if_softc *); 2420dbe28b3SPyun YongHyeon static void msk_intr_gmac(struct msk_if_softc *); 2430dbe28b3SPyun YongHyeon static __inline void msk_rxput(struct msk_if_softc *); 2440dbe28b3SPyun YongHyeon static int msk_handle_events(struct msk_softc *); 2450dbe28b3SPyun YongHyeon static void msk_handle_hwerr(struct msk_if_softc *, uint32_t); 2460dbe28b3SPyun YongHyeon static void msk_intr_hwerr(struct msk_softc *); 2470dbe28b3SPyun YongHyeon static void msk_rxeof(struct msk_if_softc *, uint32_t, int); 2480dbe28b3SPyun YongHyeon static void msk_jumbo_rxeof(struct msk_if_softc *, uint32_t, int); 2490dbe28b3SPyun YongHyeon static void msk_txeof(struct msk_if_softc *, int); 2500dbe28b3SPyun YongHyeon static int msk_encap(struct msk_if_softc *, struct mbuf **); 2510dbe28b3SPyun YongHyeon static void msk_tx_task(void *, int); 2520dbe28b3SPyun YongHyeon static void msk_start(struct ifnet *); 2530dbe28b3SPyun YongHyeon static int msk_ioctl(struct ifnet *, u_long, caddr_t); 2540dbe28b3SPyun YongHyeon static void msk_set_prefetch(struct msk_softc *, int, bus_addr_t, uint32_t); 2550dbe28b3SPyun YongHyeon static void msk_set_rambuffer(struct msk_if_softc *); 2560dbe28b3SPyun YongHyeon static void msk_init(void *); 2570dbe28b3SPyun YongHyeon static void msk_init_locked(struct msk_if_softc *); 2580dbe28b3SPyun YongHyeon static void msk_stop(struct msk_if_softc *); 2592271eac7SPyun YongHyeon static void msk_watchdog(struct msk_if_softc *); 2600dbe28b3SPyun YongHyeon static int msk_mediachange(struct ifnet *); 2610dbe28b3SPyun YongHyeon static void msk_mediastatus(struct ifnet *, struct ifmediareq *); 2620dbe28b3SPyun YongHyeon static void msk_phy_power(struct msk_softc *, int); 2630dbe28b3SPyun YongHyeon static void msk_dmamap_cb(void *, bus_dma_segment_t *, int, int); 2640dbe28b3SPyun YongHyeon static int msk_status_dma_alloc(struct msk_softc *); 2650dbe28b3SPyun YongHyeon static void msk_status_dma_free(struct msk_softc *); 2660dbe28b3SPyun YongHyeon static int msk_txrx_dma_alloc(struct msk_if_softc *); 2670dbe28b3SPyun YongHyeon static void msk_txrx_dma_free(struct msk_if_softc *); 2680dbe28b3SPyun YongHyeon static void *msk_jalloc(struct msk_if_softc *); 2690dbe28b3SPyun YongHyeon static void msk_jfree(void *, void *); 2700dbe28b3SPyun YongHyeon static int msk_init_rx_ring(struct msk_if_softc *); 2710dbe28b3SPyun YongHyeon static int msk_init_jumbo_rx_ring(struct msk_if_softc *); 2720dbe28b3SPyun YongHyeon static void msk_init_tx_ring(struct msk_if_softc *); 2730dbe28b3SPyun YongHyeon static __inline void msk_discard_rxbuf(struct msk_if_softc *, int); 2740dbe28b3SPyun YongHyeon static __inline void msk_discard_jumbo_rxbuf(struct msk_if_softc *, int); 2750dbe28b3SPyun YongHyeon static int msk_newbuf(struct msk_if_softc *, int); 2760dbe28b3SPyun YongHyeon static int msk_jumbo_newbuf(struct msk_if_softc *, int); 2770dbe28b3SPyun YongHyeon 2780dbe28b3SPyun YongHyeon static int msk_phy_readreg(struct msk_if_softc *, int, int); 2790dbe28b3SPyun YongHyeon static int msk_phy_writereg(struct msk_if_softc *, int, int, int); 2800dbe28b3SPyun YongHyeon static int msk_miibus_readreg(device_t, int, int); 2810dbe28b3SPyun YongHyeon static int msk_miibus_writereg(device_t, int, int, int); 2820dbe28b3SPyun YongHyeon static void msk_miibus_statchg(device_t); 2830dbe28b3SPyun YongHyeon static void msk_link_task(void *, int); 2840dbe28b3SPyun YongHyeon 2850dbe28b3SPyun YongHyeon static void msk_setmulti(struct msk_if_softc *); 2860dbe28b3SPyun YongHyeon static void msk_setvlan(struct msk_if_softc *, struct ifnet *); 2870dbe28b3SPyun YongHyeon static void msk_setpromisc(struct msk_if_softc *); 2880dbe28b3SPyun YongHyeon 2890dbe28b3SPyun YongHyeon static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 2900dbe28b3SPyun YongHyeon static int sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS); 2910dbe28b3SPyun YongHyeon 2920dbe28b3SPyun YongHyeon static device_method_t mskc_methods[] = { 2930dbe28b3SPyun YongHyeon /* Device interface */ 2940dbe28b3SPyun YongHyeon DEVMETHOD(device_probe, mskc_probe), 2950dbe28b3SPyun YongHyeon DEVMETHOD(device_attach, mskc_attach), 2960dbe28b3SPyun YongHyeon DEVMETHOD(device_detach, mskc_detach), 2970dbe28b3SPyun YongHyeon DEVMETHOD(device_suspend, mskc_suspend), 2980dbe28b3SPyun YongHyeon DEVMETHOD(device_resume, mskc_resume), 2990dbe28b3SPyun YongHyeon DEVMETHOD(device_shutdown, mskc_shutdown), 3000dbe28b3SPyun YongHyeon 3010dbe28b3SPyun YongHyeon /* bus interface */ 3020dbe28b3SPyun YongHyeon DEVMETHOD(bus_print_child, bus_generic_print_child), 3030dbe28b3SPyun YongHyeon DEVMETHOD(bus_driver_added, bus_generic_driver_added), 3040dbe28b3SPyun YongHyeon 3050dbe28b3SPyun YongHyeon { NULL, NULL } 3060dbe28b3SPyun YongHyeon }; 3070dbe28b3SPyun YongHyeon 3080dbe28b3SPyun YongHyeon static driver_t mskc_driver = { 3090dbe28b3SPyun YongHyeon "mskc", 3100dbe28b3SPyun YongHyeon mskc_methods, 3110dbe28b3SPyun YongHyeon sizeof(struct msk_softc) 3120dbe28b3SPyun YongHyeon }; 3130dbe28b3SPyun YongHyeon 3140dbe28b3SPyun YongHyeon static devclass_t mskc_devclass; 3150dbe28b3SPyun YongHyeon 3160dbe28b3SPyun YongHyeon static device_method_t msk_methods[] = { 3170dbe28b3SPyun YongHyeon /* Device interface */ 3180dbe28b3SPyun YongHyeon DEVMETHOD(device_probe, msk_probe), 3190dbe28b3SPyun YongHyeon DEVMETHOD(device_attach, msk_attach), 3200dbe28b3SPyun YongHyeon DEVMETHOD(device_detach, msk_detach), 3210dbe28b3SPyun YongHyeon DEVMETHOD(device_shutdown, bus_generic_shutdown), 3220dbe28b3SPyun YongHyeon 3230dbe28b3SPyun YongHyeon /* bus interface */ 3240dbe28b3SPyun YongHyeon DEVMETHOD(bus_print_child, bus_generic_print_child), 3250dbe28b3SPyun YongHyeon DEVMETHOD(bus_driver_added, bus_generic_driver_added), 3260dbe28b3SPyun YongHyeon 3270dbe28b3SPyun YongHyeon /* MII interface */ 3280dbe28b3SPyun YongHyeon DEVMETHOD(miibus_readreg, msk_miibus_readreg), 3290dbe28b3SPyun YongHyeon DEVMETHOD(miibus_writereg, msk_miibus_writereg), 3300dbe28b3SPyun YongHyeon DEVMETHOD(miibus_statchg, msk_miibus_statchg), 3310dbe28b3SPyun YongHyeon 3320dbe28b3SPyun YongHyeon { NULL, NULL } 3330dbe28b3SPyun YongHyeon }; 3340dbe28b3SPyun YongHyeon 3350dbe28b3SPyun YongHyeon static driver_t msk_driver = { 3360dbe28b3SPyun YongHyeon "msk", 3370dbe28b3SPyun YongHyeon msk_methods, 3380dbe28b3SPyun YongHyeon sizeof(struct msk_if_softc) 3390dbe28b3SPyun YongHyeon }; 3400dbe28b3SPyun YongHyeon 3410dbe28b3SPyun YongHyeon static devclass_t msk_devclass; 3420dbe28b3SPyun YongHyeon 3430dbe28b3SPyun YongHyeon DRIVER_MODULE(mskc, pci, mskc_driver, mskc_devclass, 0, 0); 3440dbe28b3SPyun YongHyeon DRIVER_MODULE(msk, mskc, msk_driver, msk_devclass, 0, 0); 3450dbe28b3SPyun YongHyeon DRIVER_MODULE(miibus, msk, miibus_driver, miibus_devclass, 0, 0); 3460dbe28b3SPyun YongHyeon 3470dbe28b3SPyun YongHyeon static struct resource_spec msk_res_spec_io[] = { 3480dbe28b3SPyun YongHyeon { SYS_RES_IOPORT, PCIR_BAR(1), RF_ACTIVE }, 3490dbe28b3SPyun YongHyeon { -1, 0, 0 } 3500dbe28b3SPyun YongHyeon }; 3510dbe28b3SPyun YongHyeon 3520dbe28b3SPyun YongHyeon static struct resource_spec msk_res_spec_mem[] = { 3530dbe28b3SPyun YongHyeon { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 354298946a9SPyun YongHyeon { -1, 0, 0 } 355298946a9SPyun YongHyeon }; 356298946a9SPyun YongHyeon 357298946a9SPyun YongHyeon static struct resource_spec msk_irq_spec_legacy[] = { 3580dbe28b3SPyun YongHyeon { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 3590dbe28b3SPyun YongHyeon { -1, 0, 0 } 3600dbe28b3SPyun YongHyeon }; 3610dbe28b3SPyun YongHyeon 362298946a9SPyun YongHyeon static struct resource_spec msk_irq_spec_msi[] = { 363298946a9SPyun YongHyeon { SYS_RES_IRQ, 1, RF_ACTIVE }, 3648463d7a0SPyun YongHyeon { -1, 0, 0 } 3658463d7a0SPyun YongHyeon }; 3668463d7a0SPyun YongHyeon 3678463d7a0SPyun YongHyeon static struct resource_spec msk_irq_spec_msi2[] = { 3688463d7a0SPyun YongHyeon { SYS_RES_IRQ, 1, RF_ACTIVE }, 369298946a9SPyun YongHyeon { SYS_RES_IRQ, 2, RF_ACTIVE }, 370298946a9SPyun YongHyeon { -1, 0, 0 } 371298946a9SPyun YongHyeon }; 372298946a9SPyun YongHyeon 3730dbe28b3SPyun YongHyeon static int 3740dbe28b3SPyun YongHyeon msk_miibus_readreg(device_t dev, int phy, int reg) 3750dbe28b3SPyun YongHyeon { 3760dbe28b3SPyun YongHyeon struct msk_if_softc *sc_if; 3770dbe28b3SPyun YongHyeon 378431e606dSPyun YongHyeon if (phy != PHY_ADDR_MARV) 379431e606dSPyun YongHyeon return (0); 380431e606dSPyun YongHyeon 3810dbe28b3SPyun YongHyeon sc_if = device_get_softc(dev); 3820dbe28b3SPyun YongHyeon 3830dbe28b3SPyun YongHyeon return (msk_phy_readreg(sc_if, phy, reg)); 3840dbe28b3SPyun YongHyeon } 3850dbe28b3SPyun YongHyeon 3860dbe28b3SPyun YongHyeon static int 3870dbe28b3SPyun YongHyeon msk_phy_readreg(struct msk_if_softc *sc_if, int phy, int reg) 3880dbe28b3SPyun YongHyeon { 3890dbe28b3SPyun YongHyeon struct msk_softc *sc; 3900dbe28b3SPyun YongHyeon int i, val; 3910dbe28b3SPyun YongHyeon 3920dbe28b3SPyun YongHyeon sc = sc_if->msk_softc; 3930dbe28b3SPyun YongHyeon 3940dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 3950dbe28b3SPyun YongHyeon GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD); 3960dbe28b3SPyun YongHyeon 3970dbe28b3SPyun YongHyeon for (i = 0; i < MSK_TIMEOUT; i++) { 3980dbe28b3SPyun YongHyeon DELAY(1); 3990dbe28b3SPyun YongHyeon val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL); 4000dbe28b3SPyun YongHyeon if ((val & GM_SMI_CT_RD_VAL) != 0) { 4010dbe28b3SPyun YongHyeon val = GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_DATA); 4020dbe28b3SPyun YongHyeon break; 4030dbe28b3SPyun YongHyeon } 4040dbe28b3SPyun YongHyeon } 4050dbe28b3SPyun YongHyeon 4060dbe28b3SPyun YongHyeon if (i == MSK_TIMEOUT) { 4070dbe28b3SPyun YongHyeon if_printf(sc_if->msk_ifp, "phy failed to come ready\n"); 4080dbe28b3SPyun YongHyeon val = 0; 4090dbe28b3SPyun YongHyeon } 4100dbe28b3SPyun YongHyeon 4110dbe28b3SPyun YongHyeon return (val); 4120dbe28b3SPyun YongHyeon } 4130dbe28b3SPyun YongHyeon 4140dbe28b3SPyun YongHyeon static int 4150dbe28b3SPyun YongHyeon msk_miibus_writereg(device_t dev, int phy, int reg, int val) 4160dbe28b3SPyun YongHyeon { 4170dbe28b3SPyun YongHyeon struct msk_if_softc *sc_if; 4180dbe28b3SPyun YongHyeon 419431e606dSPyun YongHyeon if (phy != PHY_ADDR_MARV) 420431e606dSPyun YongHyeon return (0); 421431e606dSPyun YongHyeon 4220dbe28b3SPyun YongHyeon sc_if = device_get_softc(dev); 4230dbe28b3SPyun YongHyeon 4240dbe28b3SPyun YongHyeon return (msk_phy_writereg(sc_if, phy, reg, val)); 4250dbe28b3SPyun YongHyeon } 4260dbe28b3SPyun YongHyeon 4270dbe28b3SPyun YongHyeon static int 4280dbe28b3SPyun YongHyeon msk_phy_writereg(struct msk_if_softc *sc_if, int phy, int reg, int val) 4290dbe28b3SPyun YongHyeon { 4300dbe28b3SPyun YongHyeon struct msk_softc *sc; 4310dbe28b3SPyun YongHyeon int i; 4320dbe28b3SPyun YongHyeon 4330dbe28b3SPyun YongHyeon sc = sc_if->msk_softc; 4340dbe28b3SPyun YongHyeon 4350dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_DATA, val); 4360dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_SMI_CTRL, 4370dbe28b3SPyun YongHyeon GM_SMI_CT_PHY_AD(phy) | GM_SMI_CT_REG_AD(reg)); 4380dbe28b3SPyun YongHyeon for (i = 0; i < MSK_TIMEOUT; i++) { 4390dbe28b3SPyun YongHyeon DELAY(1); 4400dbe28b3SPyun YongHyeon if ((GMAC_READ_2(sc, sc_if->msk_port, GM_SMI_CTRL) & 4410dbe28b3SPyun YongHyeon GM_SMI_CT_BUSY) == 0) 4420dbe28b3SPyun YongHyeon break; 4430dbe28b3SPyun YongHyeon } 4440dbe28b3SPyun YongHyeon if (i == MSK_TIMEOUT) 4450dbe28b3SPyun YongHyeon if_printf(sc_if->msk_ifp, "phy write timeout\n"); 4460dbe28b3SPyun YongHyeon 4470dbe28b3SPyun YongHyeon return (0); 4480dbe28b3SPyun YongHyeon } 4490dbe28b3SPyun YongHyeon 4500dbe28b3SPyun YongHyeon static void 4510dbe28b3SPyun YongHyeon msk_miibus_statchg(device_t dev) 4520dbe28b3SPyun YongHyeon { 4530dbe28b3SPyun YongHyeon struct msk_if_softc *sc_if; 4540dbe28b3SPyun YongHyeon 4550dbe28b3SPyun YongHyeon sc_if = device_get_softc(dev); 4560dbe28b3SPyun YongHyeon taskqueue_enqueue(taskqueue_swi, &sc_if->msk_link_task); 4570dbe28b3SPyun YongHyeon } 4580dbe28b3SPyun YongHyeon 4590dbe28b3SPyun YongHyeon static void 4600dbe28b3SPyun YongHyeon msk_link_task(void *arg, int pending) 4610dbe28b3SPyun YongHyeon { 4620dbe28b3SPyun YongHyeon struct msk_softc *sc; 4630dbe28b3SPyun YongHyeon struct msk_if_softc *sc_if; 4640dbe28b3SPyun YongHyeon struct mii_data *mii; 4650dbe28b3SPyun YongHyeon struct ifnet *ifp; 466bf59599fSPyun YongHyeon uint32_t gmac; 4670dbe28b3SPyun YongHyeon 4680dbe28b3SPyun YongHyeon sc_if = (struct msk_if_softc *)arg; 4690dbe28b3SPyun YongHyeon sc = sc_if->msk_softc; 4700dbe28b3SPyun YongHyeon 4710dbe28b3SPyun YongHyeon MSK_IF_LOCK(sc_if); 4720dbe28b3SPyun YongHyeon 4730dbe28b3SPyun YongHyeon mii = device_get_softc(sc_if->msk_miibus); 4740dbe28b3SPyun YongHyeon ifp = sc_if->msk_ifp; 4750dbe28b3SPyun YongHyeon if (mii == NULL || ifp == NULL) { 4760dbe28b3SPyun YongHyeon MSK_IF_UNLOCK(sc_if); 4770dbe28b3SPyun YongHyeon return; 4780dbe28b3SPyun YongHyeon } 4790dbe28b3SPyun YongHyeon 4800dbe28b3SPyun YongHyeon if (mii->mii_media_status & IFM_ACTIVE) { 4810dbe28b3SPyun YongHyeon if (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) 4820dbe28b3SPyun YongHyeon sc_if->msk_link = 1; 4830dbe28b3SPyun YongHyeon } else 4840dbe28b3SPyun YongHyeon sc_if->msk_link = 0; 4850dbe28b3SPyun YongHyeon 4860dbe28b3SPyun YongHyeon if (sc_if->msk_link != 0) { 4870dbe28b3SPyun YongHyeon /* Enable Tx FIFO Underrun. */ 4880dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 4890dbe28b3SPyun YongHyeon GM_IS_TX_FF_UR | GM_IS_RX_FF_OR); 490bf59599fSPyun YongHyeon /* 491bf59599fSPyun YongHyeon * Because mii(4) notify msk(4) that it detected link status 492bf59599fSPyun YongHyeon * change, there is no need to enable automatic 493bf59599fSPyun YongHyeon * speed/flow-control/duplex updates. 494bf59599fSPyun YongHyeon */ 495bf59599fSPyun YongHyeon gmac = GM_GPCR_AU_ALL_DIS; 4960dbe28b3SPyun YongHyeon switch (IFM_SUBTYPE(mii->mii_media_active)) { 4970dbe28b3SPyun YongHyeon case IFM_1000_SX: 4980dbe28b3SPyun YongHyeon case IFM_1000_T: 4990dbe28b3SPyun YongHyeon gmac |= GM_GPCR_SPEED_1000; 5000dbe28b3SPyun YongHyeon break; 5010dbe28b3SPyun YongHyeon case IFM_100_TX: 5020dbe28b3SPyun YongHyeon gmac |= GM_GPCR_SPEED_100; 5030dbe28b3SPyun YongHyeon break; 5040dbe28b3SPyun YongHyeon case IFM_10_T: 5050dbe28b3SPyun YongHyeon break; 5060dbe28b3SPyun YongHyeon } 5070dbe28b3SPyun YongHyeon 5080dbe28b3SPyun YongHyeon if (((mii->mii_media_active & IFM_GMASK) & IFM_FDX) != 0) 5090dbe28b3SPyun YongHyeon gmac |= GM_GPCR_DUP_FULL; 510bf59599fSPyun YongHyeon /* Disable Rx flow control. */ 511bf59599fSPyun YongHyeon if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG0) == 0) 512bf59599fSPyun YongHyeon gmac |= GM_GPCR_FC_RX_DIS; 513bf59599fSPyun YongHyeon /* Disable Tx flow control. */ 514bf59599fSPyun YongHyeon if (((mii->mii_media_active & IFM_GMASK) & IFM_FLAG1) == 0) 515bf59599fSPyun YongHyeon gmac |= GM_GPCR_FC_TX_DIS; 5160dbe28b3SPyun YongHyeon gmac |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA; 5170dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 5180dbe28b3SPyun YongHyeon /* Read again to ensure writing. */ 5190dbe28b3SPyun YongHyeon GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 5200dbe28b3SPyun YongHyeon 5210dbe28b3SPyun YongHyeon gmac = GMC_PAUSE_ON; 5220dbe28b3SPyun YongHyeon if (((mii->mii_media_active & IFM_GMASK) & 5230dbe28b3SPyun YongHyeon (IFM_FLAG0 | IFM_FLAG1)) == 0) 5240dbe28b3SPyun YongHyeon gmac = GMC_PAUSE_OFF; 5250dbe28b3SPyun YongHyeon /* Diable pause for 10/100 Mbps in half-duplex mode. */ 5260dbe28b3SPyun YongHyeon if ((((mii->mii_media_active & IFM_GMASK) & IFM_FDX) == 0) && 5270dbe28b3SPyun YongHyeon (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX || 5280dbe28b3SPyun YongHyeon IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T)) 5290dbe28b3SPyun YongHyeon gmac = GMC_PAUSE_OFF; 5300dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), gmac); 5310dbe28b3SPyun YongHyeon 5320dbe28b3SPyun YongHyeon /* Enable PHY interrupt for FIFO underrun/overflow. */ 5330dbe28b3SPyun YongHyeon msk_phy_writereg(sc_if, PHY_ADDR_MARV, 5340dbe28b3SPyun YongHyeon PHY_MARV_INT_MASK, PHY_M_IS_FIFO_ERROR); 5350dbe28b3SPyun YongHyeon } else { 5360dbe28b3SPyun YongHyeon /* 5370dbe28b3SPyun YongHyeon * Link state changed to down. 5380dbe28b3SPyun YongHyeon * Disable PHY interrupts. 5390dbe28b3SPyun YongHyeon */ 540431e606dSPyun YongHyeon msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 5410dbe28b3SPyun YongHyeon /* Disable Rx/Tx MAC. */ 542bf59599fSPyun YongHyeon gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 5430dbe28b3SPyun YongHyeon gmac &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 5440dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 5450dbe28b3SPyun YongHyeon /* Read again to ensure writing. */ 5460dbe28b3SPyun YongHyeon GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 5470dbe28b3SPyun YongHyeon } 5480dbe28b3SPyun YongHyeon 5490dbe28b3SPyun YongHyeon MSK_IF_UNLOCK(sc_if); 5500dbe28b3SPyun YongHyeon } 5510dbe28b3SPyun YongHyeon 5520dbe28b3SPyun YongHyeon static void 5530dbe28b3SPyun YongHyeon msk_setmulti(struct msk_if_softc *sc_if) 5540dbe28b3SPyun YongHyeon { 5550dbe28b3SPyun YongHyeon struct msk_softc *sc; 5560dbe28b3SPyun YongHyeon struct ifnet *ifp; 5570dbe28b3SPyun YongHyeon struct ifmultiaddr *ifma; 5580dbe28b3SPyun YongHyeon uint32_t mchash[2]; 5590dbe28b3SPyun YongHyeon uint32_t crc; 5600dbe28b3SPyun YongHyeon uint16_t mode; 5610dbe28b3SPyun YongHyeon 5620dbe28b3SPyun YongHyeon sc = sc_if->msk_softc; 5630dbe28b3SPyun YongHyeon 5640dbe28b3SPyun YongHyeon MSK_IF_LOCK_ASSERT(sc_if); 5650dbe28b3SPyun YongHyeon 5660dbe28b3SPyun YongHyeon ifp = sc_if->msk_ifp; 5670dbe28b3SPyun YongHyeon 5680dbe28b3SPyun YongHyeon bzero(mchash, sizeof(mchash)); 5690dbe28b3SPyun YongHyeon mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 5700dbe28b3SPyun YongHyeon mode |= GM_RXCR_UCF_ENA; 5710dbe28b3SPyun YongHyeon if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 5720dbe28b3SPyun YongHyeon if ((ifp->if_flags & IFF_PROMISC) != 0) 5730dbe28b3SPyun YongHyeon mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 5740dbe28b3SPyun YongHyeon else if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 5750dbe28b3SPyun YongHyeon mchash[0] = 0xffff; 5760dbe28b3SPyun YongHyeon mchash[1] = 0xffff; 5770dbe28b3SPyun YongHyeon } 5780dbe28b3SPyun YongHyeon } else { 5790dbe28b3SPyun YongHyeon IF_ADDR_LOCK(ifp); 5800dbe28b3SPyun YongHyeon TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 5810dbe28b3SPyun YongHyeon if (ifma->ifma_addr->sa_family != AF_LINK) 5820dbe28b3SPyun YongHyeon continue; 5830dbe28b3SPyun YongHyeon crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 5840dbe28b3SPyun YongHyeon ifma->ifma_addr), ETHER_ADDR_LEN); 5850dbe28b3SPyun YongHyeon /* Just want the 6 least significant bits. */ 5860dbe28b3SPyun YongHyeon crc &= 0x3f; 5870dbe28b3SPyun YongHyeon /* Set the corresponding bit in the hash table. */ 5880dbe28b3SPyun YongHyeon mchash[crc >> 5] |= 1 << (crc & 0x1f); 5890dbe28b3SPyun YongHyeon } 5900dbe28b3SPyun YongHyeon IF_ADDR_UNLOCK(ifp); 5910dbe28b3SPyun YongHyeon mode |= GM_RXCR_MCF_ENA; 5920dbe28b3SPyun YongHyeon } 5930dbe28b3SPyun YongHyeon 5940dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H1, 5950dbe28b3SPyun YongHyeon mchash[0] & 0xffff); 5960dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H2, 5970dbe28b3SPyun YongHyeon (mchash[0] >> 16) & 0xffff); 5980dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H3, 5990dbe28b3SPyun YongHyeon mchash[1] & 0xffff); 6000dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_MC_ADDR_H4, 6010dbe28b3SPyun YongHyeon (mchash[1] >> 16) & 0xffff); 6020dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 6030dbe28b3SPyun YongHyeon } 6040dbe28b3SPyun YongHyeon 6050dbe28b3SPyun YongHyeon static void 6060dbe28b3SPyun YongHyeon msk_setvlan(struct msk_if_softc *sc_if, struct ifnet *ifp) 6070dbe28b3SPyun YongHyeon { 6080dbe28b3SPyun YongHyeon struct msk_softc *sc; 6090dbe28b3SPyun YongHyeon 6100dbe28b3SPyun YongHyeon sc = sc_if->msk_softc; 6110dbe28b3SPyun YongHyeon if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 6120dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 6130dbe28b3SPyun YongHyeon RX_VLAN_STRIP_ON); 6140dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 6150dbe28b3SPyun YongHyeon TX_VLAN_TAG_ON); 6160dbe28b3SPyun YongHyeon } else { 6170dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 6180dbe28b3SPyun YongHyeon RX_VLAN_STRIP_OFF); 6190dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 6200dbe28b3SPyun YongHyeon TX_VLAN_TAG_OFF); 6210dbe28b3SPyun YongHyeon } 6220dbe28b3SPyun YongHyeon } 6230dbe28b3SPyun YongHyeon 6240dbe28b3SPyun YongHyeon static void 6250dbe28b3SPyun YongHyeon msk_setpromisc(struct msk_if_softc *sc_if) 6260dbe28b3SPyun YongHyeon { 6270dbe28b3SPyun YongHyeon struct msk_softc *sc; 6280dbe28b3SPyun YongHyeon struct ifnet *ifp; 6290dbe28b3SPyun YongHyeon uint16_t mode; 6300dbe28b3SPyun YongHyeon 6310dbe28b3SPyun YongHyeon MSK_IF_LOCK_ASSERT(sc_if); 6320dbe28b3SPyun YongHyeon 6330dbe28b3SPyun YongHyeon sc = sc_if->msk_softc; 6340dbe28b3SPyun YongHyeon ifp = sc_if->msk_ifp; 6350dbe28b3SPyun YongHyeon 6360dbe28b3SPyun YongHyeon mode = GMAC_READ_2(sc, sc_if->msk_port, GM_RX_CTRL); 6370dbe28b3SPyun YongHyeon if (ifp->if_flags & IFF_PROMISC) 6380dbe28b3SPyun YongHyeon mode &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 6390dbe28b3SPyun YongHyeon else 6400dbe28b3SPyun YongHyeon mode |= (GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA); 6410dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, mode); 6420dbe28b3SPyun YongHyeon } 6430dbe28b3SPyun YongHyeon 6440dbe28b3SPyun YongHyeon static int 6450dbe28b3SPyun YongHyeon msk_init_rx_ring(struct msk_if_softc *sc_if) 6460dbe28b3SPyun YongHyeon { 6470dbe28b3SPyun YongHyeon struct msk_ring_data *rd; 6480dbe28b3SPyun YongHyeon struct msk_rxdesc *rxd; 6490dbe28b3SPyun YongHyeon int i, prod; 6500dbe28b3SPyun YongHyeon 6510dbe28b3SPyun YongHyeon MSK_IF_LOCK_ASSERT(sc_if); 6520dbe28b3SPyun YongHyeon 6530dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_cons = 0; 6540dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_prod = 0; 6550dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 6560dbe28b3SPyun YongHyeon 6570dbe28b3SPyun YongHyeon rd = &sc_if->msk_rdata; 6580dbe28b3SPyun YongHyeon bzero(rd->msk_rx_ring, sizeof(struct msk_rx_desc) * MSK_RX_RING_CNT); 6590dbe28b3SPyun YongHyeon prod = sc_if->msk_cdata.msk_rx_prod; 6600dbe28b3SPyun YongHyeon for (i = 0; i < MSK_RX_RING_CNT; i++) { 6610dbe28b3SPyun YongHyeon rxd = &sc_if->msk_cdata.msk_rxdesc[prod]; 6620dbe28b3SPyun YongHyeon rxd->rx_m = NULL; 6630dbe28b3SPyun YongHyeon rxd->rx_le = &rd->msk_rx_ring[prod]; 6640dbe28b3SPyun YongHyeon if (msk_newbuf(sc_if, prod) != 0) 6650dbe28b3SPyun YongHyeon return (ENOBUFS); 6660dbe28b3SPyun YongHyeon MSK_INC(prod, MSK_RX_RING_CNT); 6670dbe28b3SPyun YongHyeon } 6680dbe28b3SPyun YongHyeon 6690dbe28b3SPyun YongHyeon bus_dmamap_sync(sc_if->msk_cdata.msk_rx_ring_tag, 6700dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_ring_map, 6710dbe28b3SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 6720dbe28b3SPyun YongHyeon 6730dbe28b3SPyun YongHyeon /* Update prefetch unit. */ 6740dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_prod = MSK_RX_RING_CNT - 1; 6750dbe28b3SPyun YongHyeon CSR_WRITE_2(sc_if->msk_softc, 6760dbe28b3SPyun YongHyeon Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 6770dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_prod); 6780dbe28b3SPyun YongHyeon 6790dbe28b3SPyun YongHyeon return (0); 6800dbe28b3SPyun YongHyeon } 6810dbe28b3SPyun YongHyeon 6820dbe28b3SPyun YongHyeon static int 6830dbe28b3SPyun YongHyeon msk_init_jumbo_rx_ring(struct msk_if_softc *sc_if) 6840dbe28b3SPyun YongHyeon { 6850dbe28b3SPyun YongHyeon struct msk_ring_data *rd; 6860dbe28b3SPyun YongHyeon struct msk_rxdesc *rxd; 6870dbe28b3SPyun YongHyeon int i, prod; 6880dbe28b3SPyun YongHyeon 6890dbe28b3SPyun YongHyeon MSK_IF_LOCK_ASSERT(sc_if); 6900dbe28b3SPyun YongHyeon 6910dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_cons = 0; 6920dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_prod = 0; 6930dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_putwm = MSK_PUT_WM; 6940dbe28b3SPyun YongHyeon 6950dbe28b3SPyun YongHyeon rd = &sc_if->msk_rdata; 6960dbe28b3SPyun YongHyeon bzero(rd->msk_jumbo_rx_ring, 6970dbe28b3SPyun YongHyeon sizeof(struct msk_rx_desc) * MSK_JUMBO_RX_RING_CNT); 6980dbe28b3SPyun YongHyeon prod = sc_if->msk_cdata.msk_rx_prod; 6990dbe28b3SPyun YongHyeon for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 7000dbe28b3SPyun YongHyeon rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[prod]; 7010dbe28b3SPyun YongHyeon rxd->rx_m = NULL; 7020dbe28b3SPyun YongHyeon rxd->rx_le = &rd->msk_jumbo_rx_ring[prod]; 7030dbe28b3SPyun YongHyeon if (msk_jumbo_newbuf(sc_if, prod) != 0) 7040dbe28b3SPyun YongHyeon return (ENOBUFS); 7050dbe28b3SPyun YongHyeon MSK_INC(prod, MSK_JUMBO_RX_RING_CNT); 7060dbe28b3SPyun YongHyeon } 7070dbe28b3SPyun YongHyeon 7080dbe28b3SPyun YongHyeon bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 7090dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_jumbo_rx_ring_map, 7100dbe28b3SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 7110dbe28b3SPyun YongHyeon 7120dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_prod = MSK_JUMBO_RX_RING_CNT - 1; 7130dbe28b3SPyun YongHyeon CSR_WRITE_2(sc_if->msk_softc, 7140dbe28b3SPyun YongHyeon Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_PUT_IDX_REG), 7150dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_prod); 7160dbe28b3SPyun YongHyeon 7170dbe28b3SPyun YongHyeon return (0); 7180dbe28b3SPyun YongHyeon } 7190dbe28b3SPyun YongHyeon 7200dbe28b3SPyun YongHyeon static void 7210dbe28b3SPyun YongHyeon msk_init_tx_ring(struct msk_if_softc *sc_if) 7220dbe28b3SPyun YongHyeon { 7230dbe28b3SPyun YongHyeon struct msk_ring_data *rd; 7240dbe28b3SPyun YongHyeon struct msk_txdesc *txd; 7250dbe28b3SPyun YongHyeon int i; 7260dbe28b3SPyun YongHyeon 7270dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tso_mtu = 0; 7280dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_prod = 0; 7290dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_cons = 0; 7300dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_cnt = 0; 7310dbe28b3SPyun YongHyeon 7320dbe28b3SPyun YongHyeon rd = &sc_if->msk_rdata; 7330dbe28b3SPyun YongHyeon bzero(rd->msk_tx_ring, sizeof(struct msk_tx_desc) * MSK_TX_RING_CNT); 7340dbe28b3SPyun YongHyeon for (i = 0; i < MSK_TX_RING_CNT; i++) { 7350dbe28b3SPyun YongHyeon txd = &sc_if->msk_cdata.msk_txdesc[i]; 7360dbe28b3SPyun YongHyeon txd->tx_m = NULL; 7370dbe28b3SPyun YongHyeon txd->tx_le = &rd->msk_tx_ring[i]; 7380dbe28b3SPyun YongHyeon } 7390dbe28b3SPyun YongHyeon 7400dbe28b3SPyun YongHyeon bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 7410dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_ring_map, 7420dbe28b3SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 7430dbe28b3SPyun YongHyeon } 7440dbe28b3SPyun YongHyeon 7450dbe28b3SPyun YongHyeon static __inline void 7460dbe28b3SPyun YongHyeon msk_discard_rxbuf(struct msk_if_softc *sc_if, int idx) 7470dbe28b3SPyun YongHyeon { 7480dbe28b3SPyun YongHyeon struct msk_rx_desc *rx_le; 7490dbe28b3SPyun YongHyeon struct msk_rxdesc *rxd; 7500dbe28b3SPyun YongHyeon struct mbuf *m; 7510dbe28b3SPyun YongHyeon 7520dbe28b3SPyun YongHyeon rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 7530dbe28b3SPyun YongHyeon m = rxd->rx_m; 7540dbe28b3SPyun YongHyeon rx_le = rxd->rx_le; 7550dbe28b3SPyun YongHyeon rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 7560dbe28b3SPyun YongHyeon } 7570dbe28b3SPyun YongHyeon 7580dbe28b3SPyun YongHyeon static __inline void 7590dbe28b3SPyun YongHyeon msk_discard_jumbo_rxbuf(struct msk_if_softc *sc_if, int idx) 7600dbe28b3SPyun YongHyeon { 7610dbe28b3SPyun YongHyeon struct msk_rx_desc *rx_le; 7620dbe28b3SPyun YongHyeon struct msk_rxdesc *rxd; 7630dbe28b3SPyun YongHyeon struct mbuf *m; 7640dbe28b3SPyun YongHyeon 7650dbe28b3SPyun YongHyeon rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 7660dbe28b3SPyun YongHyeon m = rxd->rx_m; 7670dbe28b3SPyun YongHyeon rx_le = rxd->rx_le; 7680dbe28b3SPyun YongHyeon rx_le->msk_control = htole32(m->m_len | OP_PACKET | HW_OWNER); 7690dbe28b3SPyun YongHyeon } 7700dbe28b3SPyun YongHyeon 7710dbe28b3SPyun YongHyeon static int 7720dbe28b3SPyun YongHyeon msk_newbuf(struct msk_if_softc *sc_if, int idx) 7730dbe28b3SPyun YongHyeon { 7740dbe28b3SPyun YongHyeon struct msk_rx_desc *rx_le; 7750dbe28b3SPyun YongHyeon struct msk_rxdesc *rxd; 7760dbe28b3SPyun YongHyeon struct mbuf *m; 7770dbe28b3SPyun YongHyeon bus_dma_segment_t segs[1]; 7780dbe28b3SPyun YongHyeon bus_dmamap_t map; 7790dbe28b3SPyun YongHyeon int nsegs; 7800dbe28b3SPyun YongHyeon 7810dbe28b3SPyun YongHyeon m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 7820dbe28b3SPyun YongHyeon if (m == NULL) 7830dbe28b3SPyun YongHyeon return (ENOBUFS); 7840dbe28b3SPyun YongHyeon 7850dbe28b3SPyun YongHyeon m->m_len = m->m_pkthdr.len = MCLBYTES; 7860dbe28b3SPyun YongHyeon m_adj(m, ETHER_ALIGN); 7870dbe28b3SPyun YongHyeon 7880dbe28b3SPyun YongHyeon if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_rx_tag, 7890dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_sparemap, m, segs, &nsegs, 7900dbe28b3SPyun YongHyeon BUS_DMA_NOWAIT) != 0) { 7910dbe28b3SPyun YongHyeon m_freem(m); 7920dbe28b3SPyun YongHyeon return (ENOBUFS); 7930dbe28b3SPyun YongHyeon } 7940dbe28b3SPyun YongHyeon KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 7950dbe28b3SPyun YongHyeon 7960dbe28b3SPyun YongHyeon rxd = &sc_if->msk_cdata.msk_rxdesc[idx]; 7970dbe28b3SPyun YongHyeon if (rxd->rx_m != NULL) { 7980dbe28b3SPyun YongHyeon bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 7990dbe28b3SPyun YongHyeon BUS_DMASYNC_POSTREAD); 8000dbe28b3SPyun YongHyeon bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap); 8010dbe28b3SPyun YongHyeon } 8020dbe28b3SPyun YongHyeon map = rxd->rx_dmamap; 8030dbe28b3SPyun YongHyeon rxd->rx_dmamap = sc_if->msk_cdata.msk_rx_sparemap; 8040dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_sparemap = map; 8050dbe28b3SPyun YongHyeon bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, rxd->rx_dmamap, 8060dbe28b3SPyun YongHyeon BUS_DMASYNC_PREREAD); 8070dbe28b3SPyun YongHyeon rxd->rx_m = m; 8080dbe28b3SPyun YongHyeon rx_le = rxd->rx_le; 8090dbe28b3SPyun YongHyeon rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 8100dbe28b3SPyun YongHyeon rx_le->msk_control = 8110dbe28b3SPyun YongHyeon htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 8120dbe28b3SPyun YongHyeon 8130dbe28b3SPyun YongHyeon return (0); 8140dbe28b3SPyun YongHyeon } 8150dbe28b3SPyun YongHyeon 8160dbe28b3SPyun YongHyeon static int 8170dbe28b3SPyun YongHyeon msk_jumbo_newbuf(struct msk_if_softc *sc_if, int idx) 8180dbe28b3SPyun YongHyeon { 8190dbe28b3SPyun YongHyeon struct msk_rx_desc *rx_le; 8200dbe28b3SPyun YongHyeon struct msk_rxdesc *rxd; 8210dbe28b3SPyun YongHyeon struct mbuf *m; 8220dbe28b3SPyun YongHyeon bus_dma_segment_t segs[1]; 8230dbe28b3SPyun YongHyeon bus_dmamap_t map; 8240dbe28b3SPyun YongHyeon int nsegs; 8250dbe28b3SPyun YongHyeon void *buf; 8260dbe28b3SPyun YongHyeon 8270dbe28b3SPyun YongHyeon MGETHDR(m, M_DONTWAIT, MT_DATA); 8280dbe28b3SPyun YongHyeon if (m == NULL) 8290dbe28b3SPyun YongHyeon return (ENOBUFS); 8300dbe28b3SPyun YongHyeon buf = msk_jalloc(sc_if); 8310dbe28b3SPyun YongHyeon if (buf == NULL) { 8320dbe28b3SPyun YongHyeon m_freem(m); 8330dbe28b3SPyun YongHyeon return (ENOBUFS); 8340dbe28b3SPyun YongHyeon } 8350dbe28b3SPyun YongHyeon /* Attach the buffer to the mbuf. */ 836cf827063SPoul-Henning Kamp MEXTADD(m, buf, MSK_JLEN, msk_jfree, buf, 837cf827063SPoul-Henning Kamp (struct msk_if_softc *)sc_if, 0, EXT_NET_DRV); 8380dbe28b3SPyun YongHyeon if ((m->m_flags & M_EXT) == 0) { 8390dbe28b3SPyun YongHyeon m_freem(m); 8400dbe28b3SPyun YongHyeon return (ENOBUFS); 8410dbe28b3SPyun YongHyeon } 8420dbe28b3SPyun YongHyeon m->m_pkthdr.len = m->m_len = MSK_JLEN; 8430dbe28b3SPyun YongHyeon m_adj(m, ETHER_ALIGN); 8440dbe28b3SPyun YongHyeon 8450dbe28b3SPyun YongHyeon if (bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_jumbo_rx_tag, 8460dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_jumbo_rx_sparemap, m, segs, &nsegs, 8470dbe28b3SPyun YongHyeon BUS_DMA_NOWAIT) != 0) { 8480dbe28b3SPyun YongHyeon m_freem(m); 8490dbe28b3SPyun YongHyeon return (ENOBUFS); 8500dbe28b3SPyun YongHyeon } 8510dbe28b3SPyun YongHyeon KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 8520dbe28b3SPyun YongHyeon 8530dbe28b3SPyun YongHyeon rxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[idx]; 8540dbe28b3SPyun YongHyeon if (rxd->rx_m != NULL) { 8550dbe28b3SPyun YongHyeon bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 8560dbe28b3SPyun YongHyeon rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 8570dbe28b3SPyun YongHyeon bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 8580dbe28b3SPyun YongHyeon rxd->rx_dmamap); 8590dbe28b3SPyun YongHyeon } 8600dbe28b3SPyun YongHyeon map = rxd->rx_dmamap; 8610dbe28b3SPyun YongHyeon rxd->rx_dmamap = sc_if->msk_cdata.msk_jumbo_rx_sparemap; 8620dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_jumbo_rx_sparemap = map; 8630dbe28b3SPyun YongHyeon bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, rxd->rx_dmamap, 8640dbe28b3SPyun YongHyeon BUS_DMASYNC_PREREAD); 8650dbe28b3SPyun YongHyeon rxd->rx_m = m; 8660dbe28b3SPyun YongHyeon rx_le = rxd->rx_le; 8670dbe28b3SPyun YongHyeon rx_le->msk_addr = htole32(MSK_ADDR_LO(segs[0].ds_addr)); 8680dbe28b3SPyun YongHyeon rx_le->msk_control = 8690dbe28b3SPyun YongHyeon htole32(segs[0].ds_len | OP_PACKET | HW_OWNER); 8700dbe28b3SPyun YongHyeon 8710dbe28b3SPyun YongHyeon return (0); 8720dbe28b3SPyun YongHyeon } 8730dbe28b3SPyun YongHyeon 8740dbe28b3SPyun YongHyeon /* 8750dbe28b3SPyun YongHyeon * Set media options. 8760dbe28b3SPyun YongHyeon */ 8770dbe28b3SPyun YongHyeon static int 8780dbe28b3SPyun YongHyeon msk_mediachange(struct ifnet *ifp) 8790dbe28b3SPyun YongHyeon { 8800dbe28b3SPyun YongHyeon struct msk_if_softc *sc_if; 8810dbe28b3SPyun YongHyeon struct mii_data *mii; 8820dbe28b3SPyun YongHyeon 8830dbe28b3SPyun YongHyeon sc_if = ifp->if_softc; 8840dbe28b3SPyun YongHyeon 8850dbe28b3SPyun YongHyeon MSK_IF_LOCK(sc_if); 8860dbe28b3SPyun YongHyeon mii = device_get_softc(sc_if->msk_miibus); 8870dbe28b3SPyun YongHyeon mii_mediachg(mii); 8880dbe28b3SPyun YongHyeon MSK_IF_UNLOCK(sc_if); 8890dbe28b3SPyun YongHyeon 8900dbe28b3SPyun YongHyeon return (0); 8910dbe28b3SPyun YongHyeon } 8920dbe28b3SPyun YongHyeon 8930dbe28b3SPyun YongHyeon /* 8940dbe28b3SPyun YongHyeon * Report current media status. 8950dbe28b3SPyun YongHyeon */ 8960dbe28b3SPyun YongHyeon static void 8970dbe28b3SPyun YongHyeon msk_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 8980dbe28b3SPyun YongHyeon { 8990dbe28b3SPyun YongHyeon struct msk_if_softc *sc_if; 9000dbe28b3SPyun YongHyeon struct mii_data *mii; 9010dbe28b3SPyun YongHyeon 9020dbe28b3SPyun YongHyeon sc_if = ifp->if_softc; 9030dbe28b3SPyun YongHyeon MSK_IF_LOCK(sc_if); 9040dbe28b3SPyun YongHyeon mii = device_get_softc(sc_if->msk_miibus); 9050dbe28b3SPyun YongHyeon 9060dbe28b3SPyun YongHyeon mii_pollstat(mii); 9070dbe28b3SPyun YongHyeon MSK_IF_UNLOCK(sc_if); 9080dbe28b3SPyun YongHyeon ifmr->ifm_active = mii->mii_media_active; 9090dbe28b3SPyun YongHyeon ifmr->ifm_status = mii->mii_media_status; 9100dbe28b3SPyun YongHyeon } 9110dbe28b3SPyun YongHyeon 9120dbe28b3SPyun YongHyeon static int 9130dbe28b3SPyun YongHyeon msk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 9140dbe28b3SPyun YongHyeon { 9150dbe28b3SPyun YongHyeon struct msk_if_softc *sc_if; 9160dbe28b3SPyun YongHyeon struct ifreq *ifr; 9170dbe28b3SPyun YongHyeon struct mii_data *mii; 9180dbe28b3SPyun YongHyeon int error, mask; 9190dbe28b3SPyun YongHyeon 9200dbe28b3SPyun YongHyeon sc_if = ifp->if_softc; 9210dbe28b3SPyun YongHyeon ifr = (struct ifreq *)data; 9220dbe28b3SPyun YongHyeon error = 0; 9230dbe28b3SPyun YongHyeon 9240dbe28b3SPyun YongHyeon switch(command) { 9250dbe28b3SPyun YongHyeon case SIOCSIFMTU: 9260dbe28b3SPyun YongHyeon if (ifr->ifr_mtu > MSK_JUMBO_MTU || ifr->ifr_mtu < ETHERMIN) { 9270dbe28b3SPyun YongHyeon error = EINVAL; 9280dbe28b3SPyun YongHyeon break; 9290dbe28b3SPyun YongHyeon } 930a109c74fSPyun YongHyeon if (sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_FE && 9310dbe28b3SPyun YongHyeon ifr->ifr_mtu > MSK_MAX_FRAMELEN) { 9320dbe28b3SPyun YongHyeon error = EINVAL; 9330dbe28b3SPyun YongHyeon break; 9340dbe28b3SPyun YongHyeon } 9350dbe28b3SPyun YongHyeon MSK_IF_LOCK(sc_if); 9360dbe28b3SPyun YongHyeon ifp->if_mtu = ifr->ifr_mtu; 9370dbe28b3SPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 9380dbe28b3SPyun YongHyeon msk_init_locked(sc_if); 9390dbe28b3SPyun YongHyeon MSK_IF_UNLOCK(sc_if); 9400dbe28b3SPyun YongHyeon break; 9410dbe28b3SPyun YongHyeon case SIOCSIFFLAGS: 9420dbe28b3SPyun YongHyeon MSK_IF_LOCK(sc_if); 9430dbe28b3SPyun YongHyeon if ((ifp->if_flags & IFF_UP) != 0) { 9440dbe28b3SPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 9450dbe28b3SPyun YongHyeon if (((ifp->if_flags ^ sc_if->msk_if_flags) 9460dbe28b3SPyun YongHyeon & IFF_PROMISC) != 0) { 9470dbe28b3SPyun YongHyeon msk_setpromisc(sc_if); 9480dbe28b3SPyun YongHyeon msk_setmulti(sc_if); 9490dbe28b3SPyun YongHyeon } 9500dbe28b3SPyun YongHyeon } else { 9510dbe28b3SPyun YongHyeon if (sc_if->msk_detach == 0) 9520dbe28b3SPyun YongHyeon msk_init_locked(sc_if); 9530dbe28b3SPyun YongHyeon } 9540dbe28b3SPyun YongHyeon } else { 9550dbe28b3SPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 9560dbe28b3SPyun YongHyeon msk_stop(sc_if); 9570dbe28b3SPyun YongHyeon } 9580dbe28b3SPyun YongHyeon sc_if->msk_if_flags = ifp->if_flags; 9590dbe28b3SPyun YongHyeon MSK_IF_UNLOCK(sc_if); 9600dbe28b3SPyun YongHyeon break; 9610dbe28b3SPyun YongHyeon case SIOCADDMULTI: 9620dbe28b3SPyun YongHyeon case SIOCDELMULTI: 9630dbe28b3SPyun YongHyeon MSK_IF_LOCK(sc_if); 9640dbe28b3SPyun YongHyeon if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 9650dbe28b3SPyun YongHyeon msk_setmulti(sc_if); 9660dbe28b3SPyun YongHyeon MSK_IF_UNLOCK(sc_if); 9670dbe28b3SPyun YongHyeon break; 9680dbe28b3SPyun YongHyeon case SIOCGIFMEDIA: 9690dbe28b3SPyun YongHyeon case SIOCSIFMEDIA: 9700dbe28b3SPyun YongHyeon mii = device_get_softc(sc_if->msk_miibus); 9710dbe28b3SPyun YongHyeon error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 9720dbe28b3SPyun YongHyeon break; 9730dbe28b3SPyun YongHyeon case SIOCSIFCAP: 9740dbe28b3SPyun YongHyeon MSK_IF_LOCK(sc_if); 9750dbe28b3SPyun YongHyeon mask = ifr->ifr_reqcap ^ ifp->if_capenable; 9760dbe28b3SPyun YongHyeon if ((mask & IFCAP_TXCSUM) != 0) { 9770dbe28b3SPyun YongHyeon ifp->if_capenable ^= IFCAP_TXCSUM; 9780dbe28b3SPyun YongHyeon if ((IFCAP_TXCSUM & ifp->if_capenable) != 0 && 9790dbe28b3SPyun YongHyeon (IFCAP_TXCSUM & ifp->if_capabilities) != 0) 9800dbe28b3SPyun YongHyeon ifp->if_hwassist |= MSK_CSUM_FEATURES; 9810dbe28b3SPyun YongHyeon else 9820dbe28b3SPyun YongHyeon ifp->if_hwassist &= ~MSK_CSUM_FEATURES; 9830dbe28b3SPyun YongHyeon } 9840dbe28b3SPyun YongHyeon if ((mask & IFCAP_VLAN_HWTAGGING) != 0) { 9850dbe28b3SPyun YongHyeon ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 9860dbe28b3SPyun YongHyeon msk_setvlan(sc_if, ifp); 9870dbe28b3SPyun YongHyeon } 9880dbe28b3SPyun YongHyeon 9890dbe28b3SPyun YongHyeon if ((mask & IFCAP_TSO4) != 0) { 9900dbe28b3SPyun YongHyeon ifp->if_capenable ^= IFCAP_TSO4; 9910dbe28b3SPyun YongHyeon if ((IFCAP_TSO4 & ifp->if_capenable) != 0 && 9920dbe28b3SPyun YongHyeon (IFCAP_TSO4 & ifp->if_capabilities) != 0) 9930dbe28b3SPyun YongHyeon ifp->if_hwassist |= CSUM_TSO; 9940dbe28b3SPyun YongHyeon else 9950dbe28b3SPyun YongHyeon ifp->if_hwassist &= ~CSUM_TSO; 9960dbe28b3SPyun YongHyeon } 997a109c74fSPyun YongHyeon if (sc_if->msk_framesize > MSK_MAX_FRAMELEN && 998a109c74fSPyun YongHyeon sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 999a109c74fSPyun YongHyeon /* 1000a109c74fSPyun YongHyeon * In Yukon EC Ultra, TSO & checksum offload is not 1001a109c74fSPyun YongHyeon * supported for jumbo frame. 1002a109c74fSPyun YongHyeon */ 1003a109c74fSPyun YongHyeon ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 1004a109c74fSPyun YongHyeon ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 1005a109c74fSPyun YongHyeon } 1006a109c74fSPyun YongHyeon 10070dbe28b3SPyun YongHyeon VLAN_CAPABILITIES(ifp); 10080dbe28b3SPyun YongHyeon MSK_IF_UNLOCK(sc_if); 10090dbe28b3SPyun YongHyeon break; 10100dbe28b3SPyun YongHyeon default: 10110dbe28b3SPyun YongHyeon error = ether_ioctl(ifp, command, data); 10120dbe28b3SPyun YongHyeon break; 10130dbe28b3SPyun YongHyeon } 10140dbe28b3SPyun YongHyeon 10150dbe28b3SPyun YongHyeon return (error); 10160dbe28b3SPyun YongHyeon } 10170dbe28b3SPyun YongHyeon 10180dbe28b3SPyun YongHyeon static int 10190dbe28b3SPyun YongHyeon mskc_probe(device_t dev) 10200dbe28b3SPyun YongHyeon { 10210dbe28b3SPyun YongHyeon struct msk_product *mp; 10220dbe28b3SPyun YongHyeon uint16_t vendor, devid; 10230dbe28b3SPyun YongHyeon int i; 10240dbe28b3SPyun YongHyeon 10250dbe28b3SPyun YongHyeon vendor = pci_get_vendor(dev); 10260dbe28b3SPyun YongHyeon devid = pci_get_device(dev); 10270dbe28b3SPyun YongHyeon mp = msk_products; 10280dbe28b3SPyun YongHyeon for (i = 0; i < sizeof(msk_products)/sizeof(msk_products[0]); 10290dbe28b3SPyun YongHyeon i++, mp++) { 10300dbe28b3SPyun YongHyeon if (vendor == mp->msk_vendorid && devid == mp->msk_deviceid) { 10310dbe28b3SPyun YongHyeon device_set_desc(dev, mp->msk_name); 10320dbe28b3SPyun YongHyeon return (BUS_PROBE_DEFAULT); 10330dbe28b3SPyun YongHyeon } 10340dbe28b3SPyun YongHyeon } 10350dbe28b3SPyun YongHyeon 10360dbe28b3SPyun YongHyeon return (ENXIO); 10370dbe28b3SPyun YongHyeon } 10380dbe28b3SPyun YongHyeon 10390dbe28b3SPyun YongHyeon static int 10400dbe28b3SPyun YongHyeon mskc_setup_rambuffer(struct msk_softc *sc) 10410dbe28b3SPyun YongHyeon { 1042e4a5f4e0SPyun YongHyeon int next; 10430dbe28b3SPyun YongHyeon int i; 10440dbe28b3SPyun YongHyeon uint8_t val; 10450dbe28b3SPyun YongHyeon 10460dbe28b3SPyun YongHyeon /* Get adapter SRAM size. */ 10470dbe28b3SPyun YongHyeon val = CSR_READ_1(sc, B2_E_0); 10480dbe28b3SPyun YongHyeon sc->msk_ramsize = (val == 0) ? 128 : val * 4; 10490dbe28b3SPyun YongHyeon if (bootverbose) 10500dbe28b3SPyun YongHyeon device_printf(sc->msk_dev, 10510dbe28b3SPyun YongHyeon "RAM buffer size : %dKB\n", sc->msk_ramsize); 10520dbe28b3SPyun YongHyeon /* 1053e4a5f4e0SPyun YongHyeon * Give receiver 2/3 of memory and round down to the multiple 1054e4a5f4e0SPyun YongHyeon * of 1024. Tx/Rx RAM buffer size of Yukon II shoud be multiple 1055e4a5f4e0SPyun YongHyeon * of 1024. 10560dbe28b3SPyun YongHyeon */ 1057e4a5f4e0SPyun YongHyeon sc->msk_rxqsize = rounddown((sc->msk_ramsize * 1024 * 2) / 3, 1024); 1058e4a5f4e0SPyun YongHyeon sc->msk_txqsize = (sc->msk_ramsize * 1024) - sc->msk_rxqsize; 10590dbe28b3SPyun YongHyeon for (i = 0, next = 0; i < sc->msk_num_port; i++) { 10600dbe28b3SPyun YongHyeon sc->msk_rxqstart[i] = next; 1061e4a5f4e0SPyun YongHyeon sc->msk_rxqend[i] = next + sc->msk_rxqsize - 1; 10620dbe28b3SPyun YongHyeon next = sc->msk_rxqend[i] + 1; 10630dbe28b3SPyun YongHyeon sc->msk_txqstart[i] = next; 1064e4a5f4e0SPyun YongHyeon sc->msk_txqend[i] = next + sc->msk_txqsize - 1; 10650dbe28b3SPyun YongHyeon next = sc->msk_txqend[i] + 1; 10660dbe28b3SPyun YongHyeon if (bootverbose) { 10670dbe28b3SPyun YongHyeon device_printf(sc->msk_dev, 10680dbe28b3SPyun YongHyeon "Port %d : Rx Queue %dKB(0x%08x:0x%08x)\n", i, 1069e4a5f4e0SPyun YongHyeon sc->msk_rxqsize / 1024, sc->msk_rxqstart[i], 10700dbe28b3SPyun YongHyeon sc->msk_rxqend[i]); 10710dbe28b3SPyun YongHyeon device_printf(sc->msk_dev, 10720dbe28b3SPyun YongHyeon "Port %d : Tx Queue %dKB(0x%08x:0x%08x)\n", i, 1073e4a5f4e0SPyun YongHyeon sc->msk_txqsize / 1024, sc->msk_txqstart[i], 10740dbe28b3SPyun YongHyeon sc->msk_txqend[i]); 10750dbe28b3SPyun YongHyeon } 10760dbe28b3SPyun YongHyeon } 10770dbe28b3SPyun YongHyeon 10780dbe28b3SPyun YongHyeon return (0); 10790dbe28b3SPyun YongHyeon } 10800dbe28b3SPyun YongHyeon 10810dbe28b3SPyun YongHyeon static void 10820dbe28b3SPyun YongHyeon msk_phy_power(struct msk_softc *sc, int mode) 10830dbe28b3SPyun YongHyeon { 10840dbe28b3SPyun YongHyeon uint32_t val; 10850dbe28b3SPyun YongHyeon int i; 10860dbe28b3SPyun YongHyeon 10870dbe28b3SPyun YongHyeon switch (mode) { 10880dbe28b3SPyun YongHyeon case MSK_PHY_POWERUP: 10890dbe28b3SPyun YongHyeon /* Switch power to VCC (WA for VAUX problem). */ 10900dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, B0_POWER_CTRL, 10910dbe28b3SPyun YongHyeon PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON); 10920dbe28b3SPyun YongHyeon /* Disable Core Clock Division, set Clock Select to 0. */ 10930dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS); 10940dbe28b3SPyun YongHyeon 10950dbe28b3SPyun YongHyeon val = 0; 10960dbe28b3SPyun YongHyeon if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 10970dbe28b3SPyun YongHyeon sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 10980dbe28b3SPyun YongHyeon /* Enable bits are inverted. */ 10990dbe28b3SPyun YongHyeon val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 11000dbe28b3SPyun YongHyeon Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 11010dbe28b3SPyun YongHyeon Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 11020dbe28b3SPyun YongHyeon } 11030dbe28b3SPyun YongHyeon /* 11040dbe28b3SPyun YongHyeon * Enable PCI & Core Clock, enable clock gating for both Links. 11050dbe28b3SPyun YongHyeon */ 11060dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 11070dbe28b3SPyun YongHyeon 11080dbe28b3SPyun YongHyeon val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 11090dbe28b3SPyun YongHyeon val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); 11100dbe28b3SPyun YongHyeon if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 11110dbe28b3SPyun YongHyeon sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 11120dbe28b3SPyun YongHyeon /* Deassert Low Power for 1st PHY. */ 11130dbe28b3SPyun YongHyeon val |= PCI_Y2_PHY1_COMA; 11140dbe28b3SPyun YongHyeon if (sc->msk_num_port > 1) 11150dbe28b3SPyun YongHyeon val |= PCI_Y2_PHY2_COMA; 11160dbe28b3SPyun YongHyeon } else if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 11170dbe28b3SPyun YongHyeon uint32_t our; 11180dbe28b3SPyun YongHyeon 11190dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); 11200dbe28b3SPyun YongHyeon 11210dbe28b3SPyun YongHyeon /* Enable all clocks. */ 11220dbe28b3SPyun YongHyeon pci_write_config(sc->msk_dev, PCI_OUR_REG_3, 0, 4); 11230dbe28b3SPyun YongHyeon our = pci_read_config(sc->msk_dev, PCI_OUR_REG_4, 4); 11240dbe28b3SPyun YongHyeon our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN| 11250dbe28b3SPyun YongHyeon PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST); 11260dbe28b3SPyun YongHyeon /* Set all bits to 0 except bits 15..12. */ 11270dbe28b3SPyun YongHyeon pci_write_config(sc->msk_dev, PCI_OUR_REG_4, our, 4); 11280dbe28b3SPyun YongHyeon /* Set to default value. */ 11290dbe28b3SPyun YongHyeon pci_write_config(sc->msk_dev, PCI_OUR_REG_5, 0, 4); 11300dbe28b3SPyun YongHyeon } 11310dbe28b3SPyun YongHyeon /* Release PHY from PowerDown/COMA mode. */ 11320dbe28b3SPyun YongHyeon pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 11330dbe28b3SPyun YongHyeon for (i = 0; i < sc->msk_num_port; i++) { 11340dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 11350dbe28b3SPyun YongHyeon GMLC_RST_SET); 11360dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), 11370dbe28b3SPyun YongHyeon GMLC_RST_CLR); 11380dbe28b3SPyun YongHyeon } 11390dbe28b3SPyun YongHyeon break; 11400dbe28b3SPyun YongHyeon case MSK_PHY_POWERDOWN: 11410dbe28b3SPyun YongHyeon val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 11420dbe28b3SPyun YongHyeon val |= PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD; 11430dbe28b3SPyun YongHyeon if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 11440dbe28b3SPyun YongHyeon sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 11450dbe28b3SPyun YongHyeon val &= ~PCI_Y2_PHY1_COMA; 11460dbe28b3SPyun YongHyeon if (sc->msk_num_port > 1) 11470dbe28b3SPyun YongHyeon val &= ~PCI_Y2_PHY2_COMA; 11480dbe28b3SPyun YongHyeon } 11490dbe28b3SPyun YongHyeon pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 11500dbe28b3SPyun YongHyeon 11510dbe28b3SPyun YongHyeon val = Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS | 11520dbe28b3SPyun YongHyeon Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS | 11530dbe28b3SPyun YongHyeon Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS; 11540dbe28b3SPyun YongHyeon if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 11550dbe28b3SPyun YongHyeon sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { 11560dbe28b3SPyun YongHyeon /* Enable bits are inverted. */ 11570dbe28b3SPyun YongHyeon val = 0; 11580dbe28b3SPyun YongHyeon } 11590dbe28b3SPyun YongHyeon /* 11600dbe28b3SPyun YongHyeon * Disable PCI & Core Clock, disable clock gating for 11610dbe28b3SPyun YongHyeon * both Links. 11620dbe28b3SPyun YongHyeon */ 11630dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); 11640dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, B0_POWER_CTRL, 11650dbe28b3SPyun YongHyeon PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF); 11660dbe28b3SPyun YongHyeon break; 11670dbe28b3SPyun YongHyeon default: 11680dbe28b3SPyun YongHyeon break; 11690dbe28b3SPyun YongHyeon } 11700dbe28b3SPyun YongHyeon } 11710dbe28b3SPyun YongHyeon 11720dbe28b3SPyun YongHyeon static void 11730dbe28b3SPyun YongHyeon mskc_reset(struct msk_softc *sc) 11740dbe28b3SPyun YongHyeon { 11750dbe28b3SPyun YongHyeon bus_addr_t addr; 11760dbe28b3SPyun YongHyeon uint16_t status; 11770dbe28b3SPyun YongHyeon uint32_t val; 11780dbe28b3SPyun YongHyeon int i; 11790dbe28b3SPyun YongHyeon 11800dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 11810dbe28b3SPyun YongHyeon 11820dbe28b3SPyun YongHyeon /* Disable ASF. */ 11830dbe28b3SPyun YongHyeon if (sc->msk_hw_id < CHIP_ID_YUKON_XL) { 11840dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET); 11850dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, B0_CTST, Y2_ASF_DISABLE); 11860dbe28b3SPyun YongHyeon } 11870dbe28b3SPyun YongHyeon /* 11880dbe28b3SPyun YongHyeon * Since we disabled ASF, S/W reset is required for Power Management. 11890dbe28b3SPyun YongHyeon */ 11900dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 11910dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 11920dbe28b3SPyun YongHyeon 11930dbe28b3SPyun YongHyeon /* Clear all error bits in the PCI status register. */ 11940dbe28b3SPyun YongHyeon status = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 11950dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 11960dbe28b3SPyun YongHyeon 11970dbe28b3SPyun YongHyeon pci_write_config(sc->msk_dev, PCIR_STATUS, status | 11980dbe28b3SPyun YongHyeon PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 11990dbe28b3SPyun YongHyeon PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 12000dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, B0_CTST, CS_MRST_CLR); 12010dbe28b3SPyun YongHyeon 12020dbe28b3SPyun YongHyeon switch (sc->msk_bustype) { 12030dbe28b3SPyun YongHyeon case MSK_PEX_BUS: 12040dbe28b3SPyun YongHyeon /* Clear all PEX errors. */ 12050dbe28b3SPyun YongHyeon CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 12060dbe28b3SPyun YongHyeon val = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 12070dbe28b3SPyun YongHyeon if ((val & PEX_RX_OV) != 0) { 12080dbe28b3SPyun YongHyeon sc->msk_intrmask &= ~Y2_IS_HW_ERR; 12090dbe28b3SPyun YongHyeon sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 12100dbe28b3SPyun YongHyeon } 12110dbe28b3SPyun YongHyeon break; 12120dbe28b3SPyun YongHyeon case MSK_PCI_BUS: 12130dbe28b3SPyun YongHyeon case MSK_PCIX_BUS: 12140dbe28b3SPyun YongHyeon /* Set Cache Line Size to 2(8bytes) if configured to 0. */ 12150dbe28b3SPyun YongHyeon val = pci_read_config(sc->msk_dev, PCIR_CACHELNSZ, 1); 12160dbe28b3SPyun YongHyeon if (val == 0) 12170dbe28b3SPyun YongHyeon pci_write_config(sc->msk_dev, PCIR_CACHELNSZ, 2, 1); 12180dbe28b3SPyun YongHyeon if (sc->msk_bustype == MSK_PCIX_BUS) { 12190dbe28b3SPyun YongHyeon /* Set Cache Line Size opt. */ 12200dbe28b3SPyun YongHyeon val = pci_read_config(sc->msk_dev, PCI_OUR_REG_1, 4); 12210dbe28b3SPyun YongHyeon val |= PCI_CLS_OPT; 12220dbe28b3SPyun YongHyeon pci_write_config(sc->msk_dev, PCI_OUR_REG_1, val, 4); 12230dbe28b3SPyun YongHyeon } 12240dbe28b3SPyun YongHyeon break; 12250dbe28b3SPyun YongHyeon } 12260dbe28b3SPyun YongHyeon /* Set PHY power state. */ 12270dbe28b3SPyun YongHyeon msk_phy_power(sc, MSK_PHY_POWERUP); 12280dbe28b3SPyun YongHyeon 12290dbe28b3SPyun YongHyeon /* Reset GPHY/GMAC Control */ 12300dbe28b3SPyun YongHyeon for (i = 0; i < sc->msk_num_port; i++) { 12310dbe28b3SPyun YongHyeon /* GPHY Control reset. */ 12320dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_SET); 12330dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(i, GPHY_CTRL), GPC_RST_CLR); 12340dbe28b3SPyun YongHyeon /* GMAC Control reset. */ 12350dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_SET); 12360dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_RST_CLR); 12370dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(i, GMAC_CTRL), GMC_F_LOOPB_OFF); 12380dbe28b3SPyun YongHyeon } 12390dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 12400dbe28b3SPyun YongHyeon 12410dbe28b3SPyun YongHyeon /* LED On. */ 12420dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_ON); 12430dbe28b3SPyun YongHyeon 12440dbe28b3SPyun YongHyeon /* Clear TWSI IRQ. */ 12450dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, B2_I2C_IRQ, I2C_CLR_IRQ); 12460dbe28b3SPyun YongHyeon 12470dbe28b3SPyun YongHyeon /* Turn off hardware timer. */ 12480dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, B2_TI_CTRL, TIM_STOP); 12490dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, B2_TI_CTRL, TIM_CLR_IRQ); 12500dbe28b3SPyun YongHyeon 12510dbe28b3SPyun YongHyeon /* Turn off descriptor polling. */ 12520dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, B28_DPT_CTRL, DPT_STOP); 12530dbe28b3SPyun YongHyeon 12540dbe28b3SPyun YongHyeon /* Turn off time stamps. */ 12550dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_STOP); 12560dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 12570dbe28b3SPyun YongHyeon 12580dbe28b3SPyun YongHyeon /* Configure timeout values. */ 12590dbe28b3SPyun YongHyeon for (i = 0; i < sc->msk_num_port; i++) { 12600dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_SET); 12610dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, SELECT_RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR); 12620dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R1), 12630dbe28b3SPyun YongHyeon MSK_RI_TO_53); 12640dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA1), 12650dbe28b3SPyun YongHyeon MSK_RI_TO_53); 12660dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS1), 12670dbe28b3SPyun YongHyeon MSK_RI_TO_53); 12680dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R1), 12690dbe28b3SPyun YongHyeon MSK_RI_TO_53); 12700dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA1), 12710dbe28b3SPyun YongHyeon MSK_RI_TO_53); 12720dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS1), 12730dbe28b3SPyun YongHyeon MSK_RI_TO_53); 12740dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_R2), 12750dbe28b3SPyun YongHyeon MSK_RI_TO_53); 12760dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XA2), 12770dbe28b3SPyun YongHyeon MSK_RI_TO_53); 12780dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_WTO_XS2), 12790dbe28b3SPyun YongHyeon MSK_RI_TO_53); 12800dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_R2), 12810dbe28b3SPyun YongHyeon MSK_RI_TO_53); 12820dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XA2), 12830dbe28b3SPyun YongHyeon MSK_RI_TO_53); 12840dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, SELECT_RAM_BUFFER(i, B3_RI_RTO_XS2), 12850dbe28b3SPyun YongHyeon MSK_RI_TO_53); 12860dbe28b3SPyun YongHyeon } 12870dbe28b3SPyun YongHyeon 12880dbe28b3SPyun YongHyeon /* Disable all interrupts. */ 12890dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 12900dbe28b3SPyun YongHyeon CSR_READ_4(sc, B0_HWE_IMSK); 12910dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, B0_IMSK, 0); 12920dbe28b3SPyun YongHyeon CSR_READ_4(sc, B0_IMSK); 12930dbe28b3SPyun YongHyeon 12940dbe28b3SPyun YongHyeon /* 12950dbe28b3SPyun YongHyeon * On dual port PCI-X card, there is an problem where status 12960dbe28b3SPyun YongHyeon * can be received out of order due to split transactions. 12970dbe28b3SPyun YongHyeon */ 12980dbe28b3SPyun YongHyeon if (sc->msk_bustype == MSK_PCIX_BUS && sc->msk_num_port > 1) { 12990dbe28b3SPyun YongHyeon int pcix; 13000dbe28b3SPyun YongHyeon uint16_t pcix_cmd; 13010dbe28b3SPyun YongHyeon 13020dbe28b3SPyun YongHyeon if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, &pcix) == 0) { 13030dbe28b3SPyun YongHyeon pcix_cmd = pci_read_config(sc->msk_dev, pcix + 2, 2); 13040dbe28b3SPyun YongHyeon /* Clear Max Outstanding Split Transactions. */ 13050dbe28b3SPyun YongHyeon pcix_cmd &= ~0x70; 13060dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 13070dbe28b3SPyun YongHyeon pci_write_config(sc->msk_dev, pcix + 2, pcix_cmd, 2); 13080dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 13090dbe28b3SPyun YongHyeon } 13100dbe28b3SPyun YongHyeon } 13110dbe28b3SPyun YongHyeon if (sc->msk_bustype == MSK_PEX_BUS) { 13120dbe28b3SPyun YongHyeon uint16_t v, width; 13130dbe28b3SPyun YongHyeon 13140dbe28b3SPyun YongHyeon v = pci_read_config(sc->msk_dev, PEX_DEV_CTRL, 2); 13150dbe28b3SPyun YongHyeon /* Change Max. Read Request Size to 4096 bytes. */ 13160dbe28b3SPyun YongHyeon v &= ~PEX_DC_MAX_RRS_MSK; 13170dbe28b3SPyun YongHyeon v |= PEX_DC_MAX_RD_RQ_SIZE(5); 13180dbe28b3SPyun YongHyeon pci_write_config(sc->msk_dev, PEX_DEV_CTRL, v, 2); 13190dbe28b3SPyun YongHyeon width = pci_read_config(sc->msk_dev, PEX_LNK_STAT, 2); 13200dbe28b3SPyun YongHyeon width = (width & PEX_LS_LINK_WI_MSK) >> 4; 13210dbe28b3SPyun YongHyeon v = pci_read_config(sc->msk_dev, PEX_LNK_CAP, 2); 13220dbe28b3SPyun YongHyeon v = (v & PEX_LS_LINK_WI_MSK) >> 4; 13230dbe28b3SPyun YongHyeon if (v != width) 13240dbe28b3SPyun YongHyeon device_printf(sc->msk_dev, 13250dbe28b3SPyun YongHyeon "negotiated width of link(x%d) != " 13260dbe28b3SPyun YongHyeon "max. width of link(x%d)\n", width, v); 13270dbe28b3SPyun YongHyeon } 13280dbe28b3SPyun YongHyeon 13290dbe28b3SPyun YongHyeon /* Clear status list. */ 13300dbe28b3SPyun YongHyeon bzero(sc->msk_stat_ring, 13310dbe28b3SPyun YongHyeon sizeof(struct msk_stat_desc) * MSK_STAT_RING_CNT); 13320dbe28b3SPyun YongHyeon sc->msk_stat_cons = 0; 13330dbe28b3SPyun YongHyeon bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 13340dbe28b3SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 13350dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_SET); 13360dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_RST_CLR); 13370dbe28b3SPyun YongHyeon /* Set the status list base address. */ 13380dbe28b3SPyun YongHyeon addr = sc->msk_stat_ring_paddr; 13390dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, STAT_LIST_ADDR_LO, MSK_ADDR_LO(addr)); 13400dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, STAT_LIST_ADDR_HI, MSK_ADDR_HI(addr)); 13410dbe28b3SPyun YongHyeon /* Set the status list last index. */ 13420dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, STAT_LAST_IDX, MSK_STAT_RING_CNT - 1); 1343cfd540e7SPyun YongHyeon if (sc->msk_hw_id == CHIP_ID_YUKON_EC && 1344cfd540e7SPyun YongHyeon sc->msk_hw_rev == CHIP_REV_YU_EC_A1) { 13450dbe28b3SPyun YongHyeon /* WA for dev. #4.3 */ 13460dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, STAT_TX_IDX_TH, ST_TXTH_IDX_MASK); 13470dbe28b3SPyun YongHyeon /* WA for dev. #4.18 */ 13480dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, STAT_FIFO_WM, 0x21); 13490dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x07); 13500dbe28b3SPyun YongHyeon } else { 13510dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, STAT_TX_IDX_TH, 0x0a); 13520dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, STAT_FIFO_WM, 0x10); 1353cfd540e7SPyun YongHyeon if (sc->msk_hw_id == CHIP_ID_YUKON_XL && 1354cfd540e7SPyun YongHyeon sc->msk_hw_rev == CHIP_REV_YU_XL_A0) 1355cfd540e7SPyun YongHyeon CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x04); 1356cfd540e7SPyun YongHyeon else 1357cfd540e7SPyun YongHyeon CSR_WRITE_1(sc, STAT_FIFO_ISR_WM, 0x10); 13580dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, STAT_ISR_TIMER_INI, 0x0190); 13590dbe28b3SPyun YongHyeon } 13600dbe28b3SPyun YongHyeon /* 13610dbe28b3SPyun YongHyeon * Use default value for STAT_ISR_TIMER_INI, STAT_LEV_TIMER_INI. 13620dbe28b3SPyun YongHyeon */ 13630dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, STAT_TX_TIMER_INI, MSK_USECS(sc, 1000)); 13640dbe28b3SPyun YongHyeon 13650dbe28b3SPyun YongHyeon /* Enable status unit. */ 13660dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_OP_ON); 13670dbe28b3SPyun YongHyeon 13680dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, STAT_TX_TIMER_CTRL, TIM_START); 13690dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, STAT_LEV_TIMER_CTRL, TIM_START); 13700dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, STAT_ISR_TIMER_CTRL, TIM_START); 13710dbe28b3SPyun YongHyeon } 13720dbe28b3SPyun YongHyeon 13730dbe28b3SPyun YongHyeon static int 13740dbe28b3SPyun YongHyeon msk_probe(device_t dev) 13750dbe28b3SPyun YongHyeon { 13760dbe28b3SPyun YongHyeon struct msk_softc *sc; 13770dbe28b3SPyun YongHyeon char desc[100]; 13780dbe28b3SPyun YongHyeon 13790dbe28b3SPyun YongHyeon sc = device_get_softc(device_get_parent(dev)); 13800dbe28b3SPyun YongHyeon /* 13810dbe28b3SPyun YongHyeon * Not much to do here. We always know there will be 13820dbe28b3SPyun YongHyeon * at least one GMAC present, and if there are two, 13830dbe28b3SPyun YongHyeon * mskc_attach() will create a second device instance 13840dbe28b3SPyun YongHyeon * for us. 13850dbe28b3SPyun YongHyeon */ 13860dbe28b3SPyun YongHyeon snprintf(desc, sizeof(desc), 13870dbe28b3SPyun YongHyeon "Marvell Technology Group Ltd. %s Id 0x%02x Rev 0x%02x", 13880dbe28b3SPyun YongHyeon model_name[sc->msk_hw_id - CHIP_ID_YUKON_XL], sc->msk_hw_id, 13890dbe28b3SPyun YongHyeon sc->msk_hw_rev); 13900dbe28b3SPyun YongHyeon device_set_desc_copy(dev, desc); 13910dbe28b3SPyun YongHyeon 13920dbe28b3SPyun YongHyeon return (BUS_PROBE_DEFAULT); 13930dbe28b3SPyun YongHyeon } 13940dbe28b3SPyun YongHyeon 13950dbe28b3SPyun YongHyeon static int 13960dbe28b3SPyun YongHyeon msk_attach(device_t dev) 13970dbe28b3SPyun YongHyeon { 13980dbe28b3SPyun YongHyeon struct msk_softc *sc; 13990dbe28b3SPyun YongHyeon struct msk_if_softc *sc_if; 14000dbe28b3SPyun YongHyeon struct ifnet *ifp; 14010dbe28b3SPyun YongHyeon int i, port, error; 14020dbe28b3SPyun YongHyeon uint8_t eaddr[6]; 14030dbe28b3SPyun YongHyeon 14040dbe28b3SPyun YongHyeon if (dev == NULL) 14050dbe28b3SPyun YongHyeon return (EINVAL); 14060dbe28b3SPyun YongHyeon 14070dbe28b3SPyun YongHyeon error = 0; 14080dbe28b3SPyun YongHyeon sc_if = device_get_softc(dev); 14090dbe28b3SPyun YongHyeon sc = device_get_softc(device_get_parent(dev)); 14100dbe28b3SPyun YongHyeon port = *(int *)device_get_ivars(dev); 14110dbe28b3SPyun YongHyeon 14120dbe28b3SPyun YongHyeon sc_if->msk_if_dev = dev; 14130dbe28b3SPyun YongHyeon sc_if->msk_port = port; 14140dbe28b3SPyun YongHyeon sc_if->msk_softc = sc; 14150dbe28b3SPyun YongHyeon sc->msk_if[port] = sc_if; 14160dbe28b3SPyun YongHyeon /* Setup Tx/Rx queue register offsets. */ 14170dbe28b3SPyun YongHyeon if (port == MSK_PORT_A) { 14180dbe28b3SPyun YongHyeon sc_if->msk_txq = Q_XA1; 14190dbe28b3SPyun YongHyeon sc_if->msk_txsq = Q_XS1; 14200dbe28b3SPyun YongHyeon sc_if->msk_rxq = Q_R1; 14210dbe28b3SPyun YongHyeon } else { 14220dbe28b3SPyun YongHyeon sc_if->msk_txq = Q_XA2; 14230dbe28b3SPyun YongHyeon sc_if->msk_txsq = Q_XS2; 14240dbe28b3SPyun YongHyeon sc_if->msk_rxq = Q_R2; 14250dbe28b3SPyun YongHyeon } 14260dbe28b3SPyun YongHyeon 14270dbe28b3SPyun YongHyeon callout_init_mtx(&sc_if->msk_tick_ch, &sc_if->msk_softc->msk_mtx, 0); 14280dbe28b3SPyun YongHyeon TASK_INIT(&sc_if->msk_link_task, 0, msk_link_task, sc_if); 14290dbe28b3SPyun YongHyeon 14300dbe28b3SPyun YongHyeon if ((error = msk_txrx_dma_alloc(sc_if) != 0)) 14310dbe28b3SPyun YongHyeon goto fail; 14320dbe28b3SPyun YongHyeon 14330dbe28b3SPyun YongHyeon ifp = sc_if->msk_ifp = if_alloc(IFT_ETHER); 14340dbe28b3SPyun YongHyeon if (ifp == NULL) { 14350dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, "can not if_alloc()\n"); 14360dbe28b3SPyun YongHyeon error = ENOSPC; 14370dbe28b3SPyun YongHyeon goto fail; 14380dbe28b3SPyun YongHyeon } 14390dbe28b3SPyun YongHyeon ifp->if_softc = sc_if; 14400dbe28b3SPyun YongHyeon if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 14410dbe28b3SPyun YongHyeon ifp->if_mtu = ETHERMTU; 14420dbe28b3SPyun YongHyeon ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 14430dbe28b3SPyun YongHyeon /* 14440dbe28b3SPyun YongHyeon * IFCAP_RXCSUM capability is intentionally disabled as the hardware 14450dbe28b3SPyun YongHyeon * has serious bug in Rx checksum offload for all Yukon II family 14460dbe28b3SPyun YongHyeon * hardware. It seems there is a workaround to make it work somtimes. 14470dbe28b3SPyun YongHyeon * However, the workaround also have to check OP code sequences to 14480dbe28b3SPyun YongHyeon * verify whether the OP code is correct. Sometimes it should compute 14490dbe28b3SPyun YongHyeon * IP/TCP/UDP checksum in driver in order to verify correctness of 14500dbe28b3SPyun YongHyeon * checksum computed by hardware. If you have to compute checksum 14510dbe28b3SPyun YongHyeon * with software to verify the hardware's checksum why have hardware 14520dbe28b3SPyun YongHyeon * compute the checksum? I think there is no reason to spend time to 14530dbe28b3SPyun YongHyeon * make Rx checksum offload work on Yukon II hardware. 14540dbe28b3SPyun YongHyeon */ 1455a109c74fSPyun YongHyeon ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1456a109c74fSPyun YongHyeon ifp->if_hwassist = MSK_CSUM_FEATURES | CSUM_TSO; 14570dbe28b3SPyun YongHyeon ifp->if_capenable = ifp->if_capabilities; 14580dbe28b3SPyun YongHyeon ifp->if_ioctl = msk_ioctl; 14590dbe28b3SPyun YongHyeon ifp->if_start = msk_start; 14600dbe28b3SPyun YongHyeon ifp->if_timer = 0; 14610dbe28b3SPyun YongHyeon ifp->if_watchdog = NULL; 14620dbe28b3SPyun YongHyeon ifp->if_init = msk_init; 14630dbe28b3SPyun YongHyeon IFQ_SET_MAXLEN(&ifp->if_snd, MSK_TX_RING_CNT - 1); 14640dbe28b3SPyun YongHyeon ifp->if_snd.ifq_drv_maxlen = MSK_TX_RING_CNT - 1; 14650dbe28b3SPyun YongHyeon IFQ_SET_READY(&ifp->if_snd); 14660dbe28b3SPyun YongHyeon 14670dbe28b3SPyun YongHyeon TASK_INIT(&sc_if->msk_tx_task, 1, msk_tx_task, ifp); 14680dbe28b3SPyun YongHyeon 14690dbe28b3SPyun YongHyeon /* 14700dbe28b3SPyun YongHyeon * Get station address for this interface. Note that 14710dbe28b3SPyun YongHyeon * dual port cards actually come with three station 14720dbe28b3SPyun YongHyeon * addresses: one for each port, plus an extra. The 14730dbe28b3SPyun YongHyeon * extra one is used by the SysKonnect driver software 14740dbe28b3SPyun YongHyeon * as a 'virtual' station address for when both ports 14750dbe28b3SPyun YongHyeon * are operating in failover mode. Currently we don't 14760dbe28b3SPyun YongHyeon * use this extra address. 14770dbe28b3SPyun YongHyeon */ 14780dbe28b3SPyun YongHyeon MSK_IF_LOCK(sc_if); 14790dbe28b3SPyun YongHyeon for (i = 0; i < ETHER_ADDR_LEN; i++) 14800dbe28b3SPyun YongHyeon eaddr[i] = CSR_READ_1(sc, B2_MAC_1 + (port * 8) + i); 14810dbe28b3SPyun YongHyeon 14820dbe28b3SPyun YongHyeon /* 14830dbe28b3SPyun YongHyeon * Call MI attach routine. Can't hold locks when calling into ether_*. 14840dbe28b3SPyun YongHyeon */ 14850dbe28b3SPyun YongHyeon MSK_IF_UNLOCK(sc_if); 14860dbe28b3SPyun YongHyeon ether_ifattach(ifp, eaddr); 14870dbe28b3SPyun YongHyeon MSK_IF_LOCK(sc_if); 14880dbe28b3SPyun YongHyeon 14890dbe28b3SPyun YongHyeon /* VLAN capability setup */ 14900dbe28b3SPyun YongHyeon ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 149106ff0944SPyun YongHyeon /* 149206ff0944SPyun YongHyeon * Due to Tx checksum offload hardware bugs, msk(4) manually 149306ff0944SPyun YongHyeon * computes checksum for short frames. For VLAN tagged frames 149406ff0944SPyun YongHyeon * this workaround does not work so disable checksum offload 149506ff0944SPyun YongHyeon * for VLAN interface. 149606ff0944SPyun YongHyeon */ 14970dbe28b3SPyun YongHyeon ifp->if_capenable = ifp->if_capabilities; 14980dbe28b3SPyun YongHyeon 14990dbe28b3SPyun YongHyeon /* 15000dbe28b3SPyun YongHyeon * Tell the upper layer(s) we support long frames. 15010dbe28b3SPyun YongHyeon * Must appear after the call to ether_ifattach() because 15020dbe28b3SPyun YongHyeon * ether_ifattach() sets ifi_hdrlen to the default value. 15030dbe28b3SPyun YongHyeon */ 15040dbe28b3SPyun YongHyeon ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 15050dbe28b3SPyun YongHyeon 1506a109c74fSPyun YongHyeon sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN + 1507a109c74fSPyun YongHyeon ETHER_VLAN_ENCAP_LEN; 1508a109c74fSPyun YongHyeon 15090dbe28b3SPyun YongHyeon /* 15100dbe28b3SPyun YongHyeon * Do miibus setup. 15110dbe28b3SPyun YongHyeon */ 15120dbe28b3SPyun YongHyeon MSK_IF_UNLOCK(sc_if); 15130dbe28b3SPyun YongHyeon error = mii_phy_probe(dev, &sc_if->msk_miibus, msk_mediachange, 15140dbe28b3SPyun YongHyeon msk_mediastatus); 15150dbe28b3SPyun YongHyeon if (error != 0) { 15160dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, "no PHY found!\n"); 15170dbe28b3SPyun YongHyeon ether_ifdetach(ifp); 15180dbe28b3SPyun YongHyeon error = ENXIO; 15190dbe28b3SPyun YongHyeon goto fail; 15200dbe28b3SPyun YongHyeon } 15210dbe28b3SPyun YongHyeon 15220dbe28b3SPyun YongHyeon fail: 15230dbe28b3SPyun YongHyeon if (error != 0) { 15240dbe28b3SPyun YongHyeon /* Access should be ok even though lock has been dropped */ 15250dbe28b3SPyun YongHyeon sc->msk_if[port] = NULL; 15260dbe28b3SPyun YongHyeon msk_detach(dev); 15270dbe28b3SPyun YongHyeon } 15280dbe28b3SPyun YongHyeon 15290dbe28b3SPyun YongHyeon return (error); 15300dbe28b3SPyun YongHyeon } 15310dbe28b3SPyun YongHyeon 15320dbe28b3SPyun YongHyeon /* 15330dbe28b3SPyun YongHyeon * Attach the interface. Allocate softc structures, do ifmedia 15340dbe28b3SPyun YongHyeon * setup and ethernet/BPF attach. 15350dbe28b3SPyun YongHyeon */ 15360dbe28b3SPyun YongHyeon static int 15370dbe28b3SPyun YongHyeon mskc_attach(device_t dev) 15380dbe28b3SPyun YongHyeon { 15390dbe28b3SPyun YongHyeon struct msk_softc *sc; 15408463d7a0SPyun YongHyeon int error, msic, msir, *port, reg; 15410dbe28b3SPyun YongHyeon 15420dbe28b3SPyun YongHyeon sc = device_get_softc(dev); 15430dbe28b3SPyun YongHyeon sc->msk_dev = dev; 15440dbe28b3SPyun YongHyeon mtx_init(&sc->msk_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 15450dbe28b3SPyun YongHyeon MTX_DEF); 15460dbe28b3SPyun YongHyeon 15470dbe28b3SPyun YongHyeon /* 15480dbe28b3SPyun YongHyeon * Map control/status registers. 15490dbe28b3SPyun YongHyeon */ 15500dbe28b3SPyun YongHyeon pci_enable_busmaster(dev); 15510dbe28b3SPyun YongHyeon 1552298946a9SPyun YongHyeon /* Allocate I/O resource */ 15530dbe28b3SPyun YongHyeon #ifdef MSK_USEIOSPACE 15540dbe28b3SPyun YongHyeon sc->msk_res_spec = msk_res_spec_io; 15550dbe28b3SPyun YongHyeon #else 15560dbe28b3SPyun YongHyeon sc->msk_res_spec = msk_res_spec_mem; 15570dbe28b3SPyun YongHyeon #endif 1558a485f97aSPyun YongHyeon sc->msk_irq_spec = msk_irq_spec_legacy; 15590dbe28b3SPyun YongHyeon error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 15600dbe28b3SPyun YongHyeon if (error) { 15610dbe28b3SPyun YongHyeon if (sc->msk_res_spec == msk_res_spec_mem) 15620dbe28b3SPyun YongHyeon sc->msk_res_spec = msk_res_spec_io; 15630dbe28b3SPyun YongHyeon else 15640dbe28b3SPyun YongHyeon sc->msk_res_spec = msk_res_spec_mem; 15650dbe28b3SPyun YongHyeon error = bus_alloc_resources(dev, sc->msk_res_spec, sc->msk_res); 15660dbe28b3SPyun YongHyeon if (error) { 15670dbe28b3SPyun YongHyeon device_printf(dev, "couldn't allocate %s resources\n", 15680dbe28b3SPyun YongHyeon sc->msk_res_spec == msk_res_spec_mem ? "memory" : 15690dbe28b3SPyun YongHyeon "I/O"); 15700dbe28b3SPyun YongHyeon mtx_destroy(&sc->msk_mtx); 15710dbe28b3SPyun YongHyeon return (ENXIO); 15720dbe28b3SPyun YongHyeon } 15730dbe28b3SPyun YongHyeon } 15740dbe28b3SPyun YongHyeon 15750dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 15760dbe28b3SPyun YongHyeon sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); 15770dbe28b3SPyun YongHyeon sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; 15780dbe28b3SPyun YongHyeon /* Bail out if chip is not recognized. */ 15790dbe28b3SPyun YongHyeon if (sc->msk_hw_id < CHIP_ID_YUKON_XL || 15800dbe28b3SPyun YongHyeon sc->msk_hw_id > CHIP_ID_YUKON_FE) { 15810dbe28b3SPyun YongHyeon device_printf(dev, "unknown device: id=0x%02x, rev=0x%02x\n", 15820dbe28b3SPyun YongHyeon sc->msk_hw_id, sc->msk_hw_rev); 1583ad6d01d1SPyun YongHyeon mtx_destroy(&sc->msk_mtx); 1584ad6d01d1SPyun YongHyeon return (ENXIO); 15850dbe28b3SPyun YongHyeon } 15860dbe28b3SPyun YongHyeon 15870dbe28b3SPyun YongHyeon SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 15880dbe28b3SPyun YongHyeon SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 15890dbe28b3SPyun YongHyeon OID_AUTO, "process_limit", CTLTYPE_INT | CTLFLAG_RW, 15900dbe28b3SPyun YongHyeon &sc->msk_process_limit, 0, sysctl_hw_msk_proc_limit, "I", 15910dbe28b3SPyun YongHyeon "max number of Rx events to process"); 15920dbe28b3SPyun YongHyeon 15930dbe28b3SPyun YongHyeon sc->msk_process_limit = MSK_PROC_DEFAULT; 15940dbe28b3SPyun YongHyeon error = resource_int_value(device_get_name(dev), device_get_unit(dev), 15950dbe28b3SPyun YongHyeon "process_limit", &sc->msk_process_limit); 15960dbe28b3SPyun YongHyeon if (error == 0) { 15970dbe28b3SPyun YongHyeon if (sc->msk_process_limit < MSK_PROC_MIN || 15980dbe28b3SPyun YongHyeon sc->msk_process_limit > MSK_PROC_MAX) { 15990dbe28b3SPyun YongHyeon device_printf(dev, "process_limit value out of range; " 16000dbe28b3SPyun YongHyeon "using default: %d\n", MSK_PROC_DEFAULT); 16010dbe28b3SPyun YongHyeon sc->msk_process_limit = MSK_PROC_DEFAULT; 16020dbe28b3SPyun YongHyeon } 16030dbe28b3SPyun YongHyeon } 16040dbe28b3SPyun YongHyeon 16050dbe28b3SPyun YongHyeon /* Soft reset. */ 16060dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 16070dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); 16080dbe28b3SPyun YongHyeon sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); 16090dbe28b3SPyun YongHyeon if (sc->msk_pmd == 'L' || sc->msk_pmd == 'S') 16100dbe28b3SPyun YongHyeon sc->msk_coppertype = 0; 16110dbe28b3SPyun YongHyeon else 16120dbe28b3SPyun YongHyeon sc->msk_coppertype = 1; 16130dbe28b3SPyun YongHyeon /* Check number of MACs. */ 16140dbe28b3SPyun YongHyeon sc->msk_num_port = 1; 16150dbe28b3SPyun YongHyeon if ((CSR_READ_1(sc, B2_Y2_HW_RES) & CFG_DUAL_MAC_MSK) == 16160dbe28b3SPyun YongHyeon CFG_DUAL_MAC_MSK) { 16170dbe28b3SPyun YongHyeon if (!(CSR_READ_1(sc, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC)) 16180dbe28b3SPyun YongHyeon sc->msk_num_port++; 16190dbe28b3SPyun YongHyeon } 16200dbe28b3SPyun YongHyeon 16210dbe28b3SPyun YongHyeon /* Check bus type. */ 16220dbe28b3SPyun YongHyeon if (pci_find_extcap(sc->msk_dev, PCIY_EXPRESS, ®) == 0) 16230dbe28b3SPyun YongHyeon sc->msk_bustype = MSK_PEX_BUS; 16240dbe28b3SPyun YongHyeon else if (pci_find_extcap(sc->msk_dev, PCIY_PCIX, ®) == 0) 16250dbe28b3SPyun YongHyeon sc->msk_bustype = MSK_PCIX_BUS; 16260dbe28b3SPyun YongHyeon else 16270dbe28b3SPyun YongHyeon sc->msk_bustype = MSK_PCI_BUS; 16280dbe28b3SPyun YongHyeon 16290dbe28b3SPyun YongHyeon switch (sc->msk_hw_id) { 16300dbe28b3SPyun YongHyeon case CHIP_ID_YUKON_EC: 16310dbe28b3SPyun YongHyeon case CHIP_ID_YUKON_EC_U: 16320dbe28b3SPyun YongHyeon sc->msk_clock = 125; /* 125 Mhz */ 16330dbe28b3SPyun YongHyeon break; 16340dbe28b3SPyun YongHyeon case CHIP_ID_YUKON_FE: 16350dbe28b3SPyun YongHyeon sc->msk_clock = 100; /* 100 Mhz */ 16360dbe28b3SPyun YongHyeon break; 16370dbe28b3SPyun YongHyeon case CHIP_ID_YUKON_XL: 16380dbe28b3SPyun YongHyeon sc->msk_clock = 156; /* 156 Mhz */ 16390dbe28b3SPyun YongHyeon break; 16400dbe28b3SPyun YongHyeon default: 16410dbe28b3SPyun YongHyeon sc->msk_clock = 156; /* 156 Mhz */ 1642cfd540e7SPyun YongHyeon break; 16430dbe28b3SPyun YongHyeon } 16440dbe28b3SPyun YongHyeon 1645298946a9SPyun YongHyeon /* Allocate IRQ resources. */ 1646298946a9SPyun YongHyeon msic = pci_msi_count(dev); 1647298946a9SPyun YongHyeon if (bootverbose) 1648298946a9SPyun YongHyeon device_printf(dev, "MSI count : %d\n", msic); 1649298946a9SPyun YongHyeon /* 1650298946a9SPyun YongHyeon * The Yukon II reports it can handle two messages, one for each 1651298946a9SPyun YongHyeon * possible port. We go ahead and allocate two messages and only 1652298946a9SPyun YongHyeon * setup a handler for both if we have a dual port card. 1653298946a9SPyun YongHyeon * 1654298946a9SPyun YongHyeon * XXX: I haven't untangled the interrupt handler to handle dual 1655298946a9SPyun YongHyeon * port cards with separate MSI messages, so for now I disable MSI 1656298946a9SPyun YongHyeon * on dual port cards. 1657298946a9SPyun YongHyeon */ 165853dcfbd1SPyun YongHyeon if (legacy_intr != 0) 165953dcfbd1SPyun YongHyeon msi_disable = 1; 16608463d7a0SPyun YongHyeon if (msi_disable == 0) { 16618463d7a0SPyun YongHyeon switch (msic) { 16628463d7a0SPyun YongHyeon case 2: 16638463d7a0SPyun YongHyeon case 1: /* 88E8058 reports 1 MSI message */ 16648463d7a0SPyun YongHyeon msir = msic; 16658463d7a0SPyun YongHyeon if (sc->msk_num_port == 1 && 16668463d7a0SPyun YongHyeon pci_alloc_msi(dev, &msir) == 0) { 16678463d7a0SPyun YongHyeon if (msic == msir) { 1668298946a9SPyun YongHyeon sc->msk_msi = 1; 16698463d7a0SPyun YongHyeon sc->msk_irq_spec = msic == 2 ? 16708463d7a0SPyun YongHyeon msk_irq_spec_msi2 : 16718463d7a0SPyun YongHyeon msk_irq_spec_msi; 16726ec27c17SPyun YongHyeon } else 1673298946a9SPyun YongHyeon pci_release_msi(dev); 1674298946a9SPyun YongHyeon } 16758463d7a0SPyun YongHyeon break; 16768463d7a0SPyun YongHyeon default: 16778463d7a0SPyun YongHyeon device_printf(dev, 16788463d7a0SPyun YongHyeon "Unexpected number of MSI messages : %d\n", msic); 16798463d7a0SPyun YongHyeon break; 16808463d7a0SPyun YongHyeon } 16818463d7a0SPyun YongHyeon } 1682298946a9SPyun YongHyeon 1683298946a9SPyun YongHyeon error = bus_alloc_resources(dev, sc->msk_irq_spec, sc->msk_irq); 1684298946a9SPyun YongHyeon if (error) { 1685298946a9SPyun YongHyeon device_printf(dev, "couldn't allocate IRQ resources\n"); 1686298946a9SPyun YongHyeon goto fail; 1687298946a9SPyun YongHyeon } 1688298946a9SPyun YongHyeon 16890dbe28b3SPyun YongHyeon if ((error = msk_status_dma_alloc(sc)) != 0) 16900dbe28b3SPyun YongHyeon goto fail; 16910dbe28b3SPyun YongHyeon 16920dbe28b3SPyun YongHyeon /* Set base interrupt mask. */ 16930dbe28b3SPyun YongHyeon sc->msk_intrmask = Y2_IS_HW_ERR | Y2_IS_STAT_BMU; 16940dbe28b3SPyun YongHyeon sc->msk_intrhwemask = Y2_IS_TIST_OV | Y2_IS_MST_ERR | 16950dbe28b3SPyun YongHyeon Y2_IS_IRQ_STAT | Y2_IS_PCI_EXP | Y2_IS_PCI_NEXP; 16960dbe28b3SPyun YongHyeon 16970dbe28b3SPyun YongHyeon /* Reset the adapter. */ 16980dbe28b3SPyun YongHyeon mskc_reset(sc); 16990dbe28b3SPyun YongHyeon 17000dbe28b3SPyun YongHyeon if ((error = mskc_setup_rambuffer(sc)) != 0) 17010dbe28b3SPyun YongHyeon goto fail; 17020dbe28b3SPyun YongHyeon 17030dbe28b3SPyun YongHyeon sc->msk_devs[MSK_PORT_A] = device_add_child(dev, "msk", -1); 17040dbe28b3SPyun YongHyeon if (sc->msk_devs[MSK_PORT_A] == NULL) { 17050dbe28b3SPyun YongHyeon device_printf(dev, "failed to add child for PORT_A\n"); 17060dbe28b3SPyun YongHyeon error = ENXIO; 17070dbe28b3SPyun YongHyeon goto fail; 17080dbe28b3SPyun YongHyeon } 17090dbe28b3SPyun YongHyeon port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 17100dbe28b3SPyun YongHyeon if (port == NULL) { 17110dbe28b3SPyun YongHyeon device_printf(dev, "failed to allocate memory for " 17120dbe28b3SPyun YongHyeon "ivars of PORT_A\n"); 17130dbe28b3SPyun YongHyeon error = ENXIO; 17140dbe28b3SPyun YongHyeon goto fail; 17150dbe28b3SPyun YongHyeon } 17160dbe28b3SPyun YongHyeon *port = MSK_PORT_A; 17170dbe28b3SPyun YongHyeon device_set_ivars(sc->msk_devs[MSK_PORT_A], port); 17180dbe28b3SPyun YongHyeon 17190dbe28b3SPyun YongHyeon if (sc->msk_num_port > 1) { 17200dbe28b3SPyun YongHyeon sc->msk_devs[MSK_PORT_B] = device_add_child(dev, "msk", -1); 17210dbe28b3SPyun YongHyeon if (sc->msk_devs[MSK_PORT_B] == NULL) { 17220dbe28b3SPyun YongHyeon device_printf(dev, "failed to add child for PORT_B\n"); 17230dbe28b3SPyun YongHyeon error = ENXIO; 17240dbe28b3SPyun YongHyeon goto fail; 17250dbe28b3SPyun YongHyeon } 17260dbe28b3SPyun YongHyeon port = malloc(sizeof(int), M_DEVBUF, M_WAITOK); 17270dbe28b3SPyun YongHyeon if (port == NULL) { 17280dbe28b3SPyun YongHyeon device_printf(dev, "failed to allocate memory for " 17290dbe28b3SPyun YongHyeon "ivars of PORT_B\n"); 17300dbe28b3SPyun YongHyeon error = ENXIO; 17310dbe28b3SPyun YongHyeon goto fail; 17320dbe28b3SPyun YongHyeon } 17330dbe28b3SPyun YongHyeon *port = MSK_PORT_B; 17340dbe28b3SPyun YongHyeon device_set_ivars(sc->msk_devs[MSK_PORT_B], port); 17350dbe28b3SPyun YongHyeon } 17360dbe28b3SPyun YongHyeon 17370dbe28b3SPyun YongHyeon error = bus_generic_attach(dev); 17380dbe28b3SPyun YongHyeon if (error) { 17390dbe28b3SPyun YongHyeon device_printf(dev, "failed to attach port(s)\n"); 17400dbe28b3SPyun YongHyeon goto fail; 17410dbe28b3SPyun YongHyeon } 17420dbe28b3SPyun YongHyeon 174353dcfbd1SPyun YongHyeon /* Hook interrupt last to avoid having to lock softc. */ 174453dcfbd1SPyun YongHyeon if (legacy_intr) 174553dcfbd1SPyun YongHyeon error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 174653dcfbd1SPyun YongHyeon INTR_MPSAFE, NULL, msk_legacy_intr, sc, 174753dcfbd1SPyun YongHyeon &sc->msk_intrhand[0]); 174853dcfbd1SPyun YongHyeon else { 17490dbe28b3SPyun YongHyeon TASK_INIT(&sc->msk_int_task, 0, msk_int_task, sc); 17500dbe28b3SPyun YongHyeon sc->msk_tq = taskqueue_create_fast("msk_taskq", M_WAITOK, 17510dbe28b3SPyun YongHyeon taskqueue_thread_enqueue, &sc->msk_tq); 17520dbe28b3SPyun YongHyeon taskqueue_start_threads(&sc->msk_tq, 1, PI_NET, "%s taskq", 17530dbe28b3SPyun YongHyeon device_get_nameunit(sc->msk_dev)); 1754298946a9SPyun YongHyeon error = bus_setup_intr(dev, sc->msk_irq[0], INTR_TYPE_NET | 1755ef544f63SPaolo Pisati INTR_MPSAFE, msk_intr, NULL, sc, &sc->msk_intrhand[0]); 175653dcfbd1SPyun YongHyeon } 17570dbe28b3SPyun YongHyeon 17580dbe28b3SPyun YongHyeon if (error != 0) { 17590dbe28b3SPyun YongHyeon device_printf(dev, "couldn't set up interrupt handler\n"); 176053dcfbd1SPyun YongHyeon if (legacy_intr == 0) 17610dbe28b3SPyun YongHyeon taskqueue_free(sc->msk_tq); 17620dbe28b3SPyun YongHyeon sc->msk_tq = NULL; 17630dbe28b3SPyun YongHyeon goto fail; 17640dbe28b3SPyun YongHyeon } 17650dbe28b3SPyun YongHyeon fail: 17660dbe28b3SPyun YongHyeon if (error != 0) 17670dbe28b3SPyun YongHyeon mskc_detach(dev); 17680dbe28b3SPyun YongHyeon 17690dbe28b3SPyun YongHyeon return (error); 17700dbe28b3SPyun YongHyeon } 17710dbe28b3SPyun YongHyeon 17720dbe28b3SPyun YongHyeon /* 17730dbe28b3SPyun YongHyeon * Shutdown hardware and free up resources. This can be called any 17740dbe28b3SPyun YongHyeon * time after the mutex has been initialized. It is called in both 17750dbe28b3SPyun YongHyeon * the error case in attach and the normal detach case so it needs 17760dbe28b3SPyun YongHyeon * to be careful about only freeing resources that have actually been 17770dbe28b3SPyun YongHyeon * allocated. 17780dbe28b3SPyun YongHyeon */ 17790dbe28b3SPyun YongHyeon static int 17800dbe28b3SPyun YongHyeon msk_detach(device_t dev) 17810dbe28b3SPyun YongHyeon { 17820dbe28b3SPyun YongHyeon struct msk_softc *sc; 17830dbe28b3SPyun YongHyeon struct msk_if_softc *sc_if; 17840dbe28b3SPyun YongHyeon struct ifnet *ifp; 17850dbe28b3SPyun YongHyeon 17860dbe28b3SPyun YongHyeon sc_if = device_get_softc(dev); 17870dbe28b3SPyun YongHyeon KASSERT(mtx_initialized(&sc_if->msk_softc->msk_mtx), 17880dbe28b3SPyun YongHyeon ("msk mutex not initialized in msk_detach")); 17890dbe28b3SPyun YongHyeon MSK_IF_LOCK(sc_if); 17900dbe28b3SPyun YongHyeon 17910dbe28b3SPyun YongHyeon ifp = sc_if->msk_ifp; 17920dbe28b3SPyun YongHyeon if (device_is_attached(dev)) { 17930dbe28b3SPyun YongHyeon /* XXX */ 17940dbe28b3SPyun YongHyeon sc_if->msk_detach = 1; 17950dbe28b3SPyun YongHyeon msk_stop(sc_if); 17960dbe28b3SPyun YongHyeon /* Can't hold locks while calling detach. */ 17970dbe28b3SPyun YongHyeon MSK_IF_UNLOCK(sc_if); 17980dbe28b3SPyun YongHyeon callout_drain(&sc_if->msk_tick_ch); 17990dbe28b3SPyun YongHyeon taskqueue_drain(taskqueue_fast, &sc_if->msk_tx_task); 18000dbe28b3SPyun YongHyeon taskqueue_drain(taskqueue_swi, &sc_if->msk_link_task); 18010dbe28b3SPyun YongHyeon ether_ifdetach(ifp); 18020dbe28b3SPyun YongHyeon MSK_IF_LOCK(sc_if); 18030dbe28b3SPyun YongHyeon } 18040dbe28b3SPyun YongHyeon 18050dbe28b3SPyun YongHyeon /* 18060dbe28b3SPyun YongHyeon * We're generally called from mskc_detach() which is using 18070dbe28b3SPyun YongHyeon * device_delete_child() to get to here. It's already trashed 18080dbe28b3SPyun YongHyeon * miibus for us, so don't do it here or we'll panic. 18090dbe28b3SPyun YongHyeon * 18100dbe28b3SPyun YongHyeon * if (sc_if->msk_miibus != NULL) { 18110dbe28b3SPyun YongHyeon * device_delete_child(dev, sc_if->msk_miibus); 18120dbe28b3SPyun YongHyeon * sc_if->msk_miibus = NULL; 18130dbe28b3SPyun YongHyeon * } 18140dbe28b3SPyun YongHyeon */ 18150dbe28b3SPyun YongHyeon 18160dbe28b3SPyun YongHyeon msk_txrx_dma_free(sc_if); 18170dbe28b3SPyun YongHyeon bus_generic_detach(dev); 18180dbe28b3SPyun YongHyeon 18190dbe28b3SPyun YongHyeon if (ifp) 18200dbe28b3SPyun YongHyeon if_free(ifp); 18210dbe28b3SPyun YongHyeon sc = sc_if->msk_softc; 18220dbe28b3SPyun YongHyeon sc->msk_if[sc_if->msk_port] = NULL; 18230dbe28b3SPyun YongHyeon MSK_IF_UNLOCK(sc_if); 18240dbe28b3SPyun YongHyeon 18250dbe28b3SPyun YongHyeon return (0); 18260dbe28b3SPyun YongHyeon } 18270dbe28b3SPyun YongHyeon 18280dbe28b3SPyun YongHyeon static int 18290dbe28b3SPyun YongHyeon mskc_detach(device_t dev) 18300dbe28b3SPyun YongHyeon { 18310dbe28b3SPyun YongHyeon struct msk_softc *sc; 18320dbe28b3SPyun YongHyeon 18330dbe28b3SPyun YongHyeon sc = device_get_softc(dev); 18340dbe28b3SPyun YongHyeon KASSERT(mtx_initialized(&sc->msk_mtx), ("msk mutex not initialized")); 18350dbe28b3SPyun YongHyeon 18360dbe28b3SPyun YongHyeon if (device_is_alive(dev)) { 18370dbe28b3SPyun YongHyeon if (sc->msk_devs[MSK_PORT_A] != NULL) { 18380dbe28b3SPyun YongHyeon free(device_get_ivars(sc->msk_devs[MSK_PORT_A]), 18390dbe28b3SPyun YongHyeon M_DEVBUF); 18400dbe28b3SPyun YongHyeon device_delete_child(dev, sc->msk_devs[MSK_PORT_A]); 18410dbe28b3SPyun YongHyeon } 18420dbe28b3SPyun YongHyeon if (sc->msk_devs[MSK_PORT_B] != NULL) { 18430dbe28b3SPyun YongHyeon free(device_get_ivars(sc->msk_devs[MSK_PORT_B]), 18440dbe28b3SPyun YongHyeon M_DEVBUF); 18450dbe28b3SPyun YongHyeon device_delete_child(dev, sc->msk_devs[MSK_PORT_B]); 18460dbe28b3SPyun YongHyeon } 18470dbe28b3SPyun YongHyeon bus_generic_detach(dev); 18480dbe28b3SPyun YongHyeon } 18490dbe28b3SPyun YongHyeon 18500dbe28b3SPyun YongHyeon /* Disable all interrupts. */ 18510dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, B0_IMSK, 0); 18520dbe28b3SPyun YongHyeon CSR_READ_4(sc, B0_IMSK); 18530dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 18540dbe28b3SPyun YongHyeon CSR_READ_4(sc, B0_HWE_IMSK); 18550dbe28b3SPyun YongHyeon 18560dbe28b3SPyun YongHyeon /* LED Off. */ 18570dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, B0_CTST, Y2_LED_STAT_OFF); 18580dbe28b3SPyun YongHyeon 18590dbe28b3SPyun YongHyeon /* Put hardware reset. */ 18600dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 18610dbe28b3SPyun YongHyeon 18620dbe28b3SPyun YongHyeon msk_status_dma_free(sc); 18630dbe28b3SPyun YongHyeon 186453dcfbd1SPyun YongHyeon if (legacy_intr == 0 && sc->msk_tq != NULL) { 18650dbe28b3SPyun YongHyeon taskqueue_drain(sc->msk_tq, &sc->msk_int_task); 18660dbe28b3SPyun YongHyeon taskqueue_free(sc->msk_tq); 18670dbe28b3SPyun YongHyeon sc->msk_tq = NULL; 18680dbe28b3SPyun YongHyeon } 1869298946a9SPyun YongHyeon if (sc->msk_intrhand[0]) { 1870298946a9SPyun YongHyeon bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]); 1871298946a9SPyun YongHyeon sc->msk_intrhand[0] = NULL; 18720dbe28b3SPyun YongHyeon } 1873298946a9SPyun YongHyeon if (sc->msk_intrhand[1]) { 1874298946a9SPyun YongHyeon bus_teardown_intr(dev, sc->msk_irq[0], sc->msk_intrhand[0]); 1875298946a9SPyun YongHyeon sc->msk_intrhand[1] = NULL; 1876298946a9SPyun YongHyeon } 1877298946a9SPyun YongHyeon bus_release_resources(dev, sc->msk_irq_spec, sc->msk_irq); 18780dbe28b3SPyun YongHyeon if (sc->msk_msi) 18790dbe28b3SPyun YongHyeon pci_release_msi(dev); 18800dbe28b3SPyun YongHyeon bus_release_resources(dev, sc->msk_res_spec, sc->msk_res); 18810dbe28b3SPyun YongHyeon mtx_destroy(&sc->msk_mtx); 18820dbe28b3SPyun YongHyeon 18830dbe28b3SPyun YongHyeon return (0); 18840dbe28b3SPyun YongHyeon } 18850dbe28b3SPyun YongHyeon 18860dbe28b3SPyun YongHyeon struct msk_dmamap_arg { 18870dbe28b3SPyun YongHyeon bus_addr_t msk_busaddr; 18880dbe28b3SPyun YongHyeon }; 18890dbe28b3SPyun YongHyeon 18900dbe28b3SPyun YongHyeon static void 18910dbe28b3SPyun YongHyeon msk_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 18920dbe28b3SPyun YongHyeon { 18930dbe28b3SPyun YongHyeon struct msk_dmamap_arg *ctx; 18940dbe28b3SPyun YongHyeon 18950dbe28b3SPyun YongHyeon if (error != 0) 18960dbe28b3SPyun YongHyeon return; 18970dbe28b3SPyun YongHyeon ctx = arg; 18980dbe28b3SPyun YongHyeon ctx->msk_busaddr = segs[0].ds_addr; 18990dbe28b3SPyun YongHyeon } 19000dbe28b3SPyun YongHyeon 19010dbe28b3SPyun YongHyeon /* Create status DMA region. */ 19020dbe28b3SPyun YongHyeon static int 19030dbe28b3SPyun YongHyeon msk_status_dma_alloc(struct msk_softc *sc) 19040dbe28b3SPyun YongHyeon { 19050dbe28b3SPyun YongHyeon struct msk_dmamap_arg ctx; 19060dbe28b3SPyun YongHyeon int error; 19070dbe28b3SPyun YongHyeon 19080dbe28b3SPyun YongHyeon error = bus_dma_tag_create( 19090dbe28b3SPyun YongHyeon bus_get_dma_tag(sc->msk_dev), /* parent */ 19100dbe28b3SPyun YongHyeon MSK_STAT_ALIGN, 0, /* alignment, boundary */ 19110dbe28b3SPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 19120dbe28b3SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 19130dbe28b3SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 19140dbe28b3SPyun YongHyeon MSK_STAT_RING_SZ, /* maxsize */ 19150dbe28b3SPyun YongHyeon 1, /* nsegments */ 19160dbe28b3SPyun YongHyeon MSK_STAT_RING_SZ, /* maxsegsize */ 19170dbe28b3SPyun YongHyeon 0, /* flags */ 19180dbe28b3SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 19190dbe28b3SPyun YongHyeon &sc->msk_stat_tag); 19200dbe28b3SPyun YongHyeon if (error != 0) { 19210dbe28b3SPyun YongHyeon device_printf(sc->msk_dev, 19220dbe28b3SPyun YongHyeon "failed to create status DMA tag\n"); 19230dbe28b3SPyun YongHyeon return (error); 19240dbe28b3SPyun YongHyeon } 19250dbe28b3SPyun YongHyeon 19260dbe28b3SPyun YongHyeon /* Allocate DMA'able memory and load the DMA map for status ring. */ 19270dbe28b3SPyun YongHyeon error = bus_dmamem_alloc(sc->msk_stat_tag, 19280dbe28b3SPyun YongHyeon (void **)&sc->msk_stat_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT | 19290dbe28b3SPyun YongHyeon BUS_DMA_ZERO, &sc->msk_stat_map); 19300dbe28b3SPyun YongHyeon if (error != 0) { 19310dbe28b3SPyun YongHyeon device_printf(sc->msk_dev, 19320dbe28b3SPyun YongHyeon "failed to allocate DMA'able memory for status ring\n"); 19330dbe28b3SPyun YongHyeon return (error); 19340dbe28b3SPyun YongHyeon } 19350dbe28b3SPyun YongHyeon 19360dbe28b3SPyun YongHyeon ctx.msk_busaddr = 0; 19370dbe28b3SPyun YongHyeon error = bus_dmamap_load(sc->msk_stat_tag, 19380dbe28b3SPyun YongHyeon sc->msk_stat_map, sc->msk_stat_ring, MSK_STAT_RING_SZ, 19390dbe28b3SPyun YongHyeon msk_dmamap_cb, &ctx, 0); 19400dbe28b3SPyun YongHyeon if (error != 0) { 19410dbe28b3SPyun YongHyeon device_printf(sc->msk_dev, 19420dbe28b3SPyun YongHyeon "failed to load DMA'able memory for status ring\n"); 19430dbe28b3SPyun YongHyeon return (error); 19440dbe28b3SPyun YongHyeon } 19450dbe28b3SPyun YongHyeon sc->msk_stat_ring_paddr = ctx.msk_busaddr; 19460dbe28b3SPyun YongHyeon 19470dbe28b3SPyun YongHyeon return (0); 19480dbe28b3SPyun YongHyeon } 19490dbe28b3SPyun YongHyeon 19500dbe28b3SPyun YongHyeon static void 19510dbe28b3SPyun YongHyeon msk_status_dma_free(struct msk_softc *sc) 19520dbe28b3SPyun YongHyeon { 19530dbe28b3SPyun YongHyeon 19540dbe28b3SPyun YongHyeon /* Destroy status block. */ 19550dbe28b3SPyun YongHyeon if (sc->msk_stat_tag) { 19560dbe28b3SPyun YongHyeon if (sc->msk_stat_map) { 19570dbe28b3SPyun YongHyeon bus_dmamap_unload(sc->msk_stat_tag, sc->msk_stat_map); 19580dbe28b3SPyun YongHyeon if (sc->msk_stat_ring) { 19590dbe28b3SPyun YongHyeon bus_dmamem_free(sc->msk_stat_tag, 19600dbe28b3SPyun YongHyeon sc->msk_stat_ring, sc->msk_stat_map); 19610dbe28b3SPyun YongHyeon sc->msk_stat_ring = NULL; 19620dbe28b3SPyun YongHyeon } 19630dbe28b3SPyun YongHyeon sc->msk_stat_map = NULL; 19640dbe28b3SPyun YongHyeon } 19650dbe28b3SPyun YongHyeon bus_dma_tag_destroy(sc->msk_stat_tag); 19660dbe28b3SPyun YongHyeon sc->msk_stat_tag = NULL; 19670dbe28b3SPyun YongHyeon } 19680dbe28b3SPyun YongHyeon } 19690dbe28b3SPyun YongHyeon 19700dbe28b3SPyun YongHyeon static int 19710dbe28b3SPyun YongHyeon msk_txrx_dma_alloc(struct msk_if_softc *sc_if) 19720dbe28b3SPyun YongHyeon { 19730dbe28b3SPyun YongHyeon struct msk_dmamap_arg ctx; 19740dbe28b3SPyun YongHyeon struct msk_txdesc *txd; 19750dbe28b3SPyun YongHyeon struct msk_rxdesc *rxd; 19760dbe28b3SPyun YongHyeon struct msk_rxdesc *jrxd; 19770dbe28b3SPyun YongHyeon struct msk_jpool_entry *entry; 19780dbe28b3SPyun YongHyeon uint8_t *ptr; 19790dbe28b3SPyun YongHyeon int error, i; 19800dbe28b3SPyun YongHyeon 19810dbe28b3SPyun YongHyeon mtx_init(&sc_if->msk_jlist_mtx, "msk_jlist_mtx", NULL, MTX_DEF); 19820dbe28b3SPyun YongHyeon SLIST_INIT(&sc_if->msk_jfree_listhead); 19830dbe28b3SPyun YongHyeon SLIST_INIT(&sc_if->msk_jinuse_listhead); 19840dbe28b3SPyun YongHyeon 19850dbe28b3SPyun YongHyeon /* Create parent DMA tag. */ 19860dbe28b3SPyun YongHyeon /* 19870dbe28b3SPyun YongHyeon * XXX 19880dbe28b3SPyun YongHyeon * It seems that Yukon II supports full 64bits DMA operations. But 19890dbe28b3SPyun YongHyeon * it needs two descriptors(list elements) for 64bits DMA operations. 19900dbe28b3SPyun YongHyeon * Since we don't know what DMA address mappings(32bits or 64bits) 19910dbe28b3SPyun YongHyeon * would be used in advance for each mbufs, we limits its DMA space 19920dbe28b3SPyun YongHyeon * to be in range of 32bits address space. Otherwise, we should check 19930dbe28b3SPyun YongHyeon * what DMA address is used and chain another descriptor for the 19940dbe28b3SPyun YongHyeon * 64bits DMA operation. This also means descriptor ring size is 19950dbe28b3SPyun YongHyeon * variable. Limiting DMA address to be in 32bit address space greatly 19960dbe28b3SPyun YongHyeon * simplyfies descriptor handling and possibly would increase 19970dbe28b3SPyun YongHyeon * performance a bit due to efficient handling of descriptors. 19980dbe28b3SPyun YongHyeon * Apart from harassing checksum offloading mechanisms, it seems 19990dbe28b3SPyun YongHyeon * it's really bad idea to use a seperate descriptor for 64bit 20000dbe28b3SPyun YongHyeon * DMA operation to save small descriptor memory. Anyway, I've 20010dbe28b3SPyun YongHyeon * never seen these exotic scheme on ethernet interface hardware. 20020dbe28b3SPyun YongHyeon */ 20030dbe28b3SPyun YongHyeon error = bus_dma_tag_create( 20040dbe28b3SPyun YongHyeon bus_get_dma_tag(sc_if->msk_if_dev), /* parent */ 20050dbe28b3SPyun YongHyeon 1, 0, /* alignment, boundary */ 20060dbe28b3SPyun YongHyeon BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 20070dbe28b3SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 20080dbe28b3SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 20090dbe28b3SPyun YongHyeon BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 20100dbe28b3SPyun YongHyeon 0, /* nsegments */ 20110dbe28b3SPyun YongHyeon BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 20120dbe28b3SPyun YongHyeon 0, /* flags */ 20130dbe28b3SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 20140dbe28b3SPyun YongHyeon &sc_if->msk_cdata.msk_parent_tag); 20150dbe28b3SPyun YongHyeon if (error != 0) { 20160dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 20170dbe28b3SPyun YongHyeon "failed to create parent DMA tag\n"); 20180dbe28b3SPyun YongHyeon goto fail; 20190dbe28b3SPyun YongHyeon } 20200dbe28b3SPyun YongHyeon /* Create tag for Tx ring. */ 20210dbe28b3SPyun YongHyeon error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 20220dbe28b3SPyun YongHyeon MSK_RING_ALIGN, 0, /* alignment, boundary */ 20230dbe28b3SPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 20240dbe28b3SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 20250dbe28b3SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 20260dbe28b3SPyun YongHyeon MSK_TX_RING_SZ, /* maxsize */ 20270dbe28b3SPyun YongHyeon 1, /* nsegments */ 20280dbe28b3SPyun YongHyeon MSK_TX_RING_SZ, /* maxsegsize */ 20290dbe28b3SPyun YongHyeon 0, /* flags */ 20300dbe28b3SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 20310dbe28b3SPyun YongHyeon &sc_if->msk_cdata.msk_tx_ring_tag); 20320dbe28b3SPyun YongHyeon if (error != 0) { 20330dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 20340dbe28b3SPyun YongHyeon "failed to create Tx ring DMA tag\n"); 20350dbe28b3SPyun YongHyeon goto fail; 20360dbe28b3SPyun YongHyeon } 20370dbe28b3SPyun YongHyeon 20380dbe28b3SPyun YongHyeon /* Create tag for Rx ring. */ 20390dbe28b3SPyun YongHyeon error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 20400dbe28b3SPyun YongHyeon MSK_RING_ALIGN, 0, /* alignment, boundary */ 20410dbe28b3SPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 20420dbe28b3SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 20430dbe28b3SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 20440dbe28b3SPyun YongHyeon MSK_RX_RING_SZ, /* maxsize */ 20450dbe28b3SPyun YongHyeon 1, /* nsegments */ 20460dbe28b3SPyun YongHyeon MSK_RX_RING_SZ, /* maxsegsize */ 20470dbe28b3SPyun YongHyeon 0, /* flags */ 20480dbe28b3SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 20490dbe28b3SPyun YongHyeon &sc_if->msk_cdata.msk_rx_ring_tag); 20500dbe28b3SPyun YongHyeon if (error != 0) { 20510dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 20520dbe28b3SPyun YongHyeon "failed to create Rx ring DMA tag\n"); 20530dbe28b3SPyun YongHyeon goto fail; 20540dbe28b3SPyun YongHyeon } 20550dbe28b3SPyun YongHyeon 20560dbe28b3SPyun YongHyeon /* Create tag for jumbo Rx ring. */ 20570dbe28b3SPyun YongHyeon error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 20580dbe28b3SPyun YongHyeon MSK_RING_ALIGN, 0, /* alignment, boundary */ 20590dbe28b3SPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 20600dbe28b3SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 20610dbe28b3SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 20620dbe28b3SPyun YongHyeon MSK_JUMBO_RX_RING_SZ, /* maxsize */ 20630dbe28b3SPyun YongHyeon 1, /* nsegments */ 20640dbe28b3SPyun YongHyeon MSK_JUMBO_RX_RING_SZ, /* maxsegsize */ 20650dbe28b3SPyun YongHyeon 0, /* flags */ 20660dbe28b3SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 20670dbe28b3SPyun YongHyeon &sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 20680dbe28b3SPyun YongHyeon if (error != 0) { 20690dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 20700dbe28b3SPyun YongHyeon "failed to create jumbo Rx ring DMA tag\n"); 20710dbe28b3SPyun YongHyeon goto fail; 20720dbe28b3SPyun YongHyeon } 20730dbe28b3SPyun YongHyeon 20740dbe28b3SPyun YongHyeon /* Create tag for jumbo buffer blocks. */ 20750dbe28b3SPyun YongHyeon error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 20760dbe28b3SPyun YongHyeon PAGE_SIZE, 0, /* alignment, boundary */ 20770dbe28b3SPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 20780dbe28b3SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 20790dbe28b3SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 20800dbe28b3SPyun YongHyeon MSK_JMEM, /* maxsize */ 20810dbe28b3SPyun YongHyeon 1, /* nsegments */ 20820dbe28b3SPyun YongHyeon MSK_JMEM, /* maxsegsize */ 20830dbe28b3SPyun YongHyeon 0, /* flags */ 20840dbe28b3SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 20850dbe28b3SPyun YongHyeon &sc_if->msk_cdata.msk_jumbo_tag); 20860dbe28b3SPyun YongHyeon if (error != 0) { 20870dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 20880dbe28b3SPyun YongHyeon "failed to create jumbo Rx buffer block DMA tag\n"); 20890dbe28b3SPyun YongHyeon goto fail; 20900dbe28b3SPyun YongHyeon } 20910dbe28b3SPyun YongHyeon 20920dbe28b3SPyun YongHyeon /* Create tag for Tx buffers. */ 20930dbe28b3SPyun YongHyeon error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 20940dbe28b3SPyun YongHyeon 1, 0, /* alignment, boundary */ 20950dbe28b3SPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 20960dbe28b3SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 20970dbe28b3SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 20988b51df84SPyun YongHyeon MSK_TSO_MAXSIZE, /* maxsize */ 20990dbe28b3SPyun YongHyeon MSK_MAXTXSEGS, /* nsegments */ 21008b51df84SPyun YongHyeon MSK_TSO_MAXSGSIZE, /* maxsegsize */ 21010dbe28b3SPyun YongHyeon 0, /* flags */ 21020dbe28b3SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 21030dbe28b3SPyun YongHyeon &sc_if->msk_cdata.msk_tx_tag); 21040dbe28b3SPyun YongHyeon if (error != 0) { 21050dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 21060dbe28b3SPyun YongHyeon "failed to create Tx DMA tag\n"); 21070dbe28b3SPyun YongHyeon goto fail; 21080dbe28b3SPyun YongHyeon } 21090dbe28b3SPyun YongHyeon 21100dbe28b3SPyun YongHyeon /* Create tag for Rx buffers. */ 21110dbe28b3SPyun YongHyeon error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 21120dbe28b3SPyun YongHyeon 1, 0, /* alignment, boundary */ 21130dbe28b3SPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 21140dbe28b3SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 21150dbe28b3SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 21160dbe28b3SPyun YongHyeon MCLBYTES, /* maxsize */ 21170dbe28b3SPyun YongHyeon 1, /* nsegments */ 21180dbe28b3SPyun YongHyeon MCLBYTES, /* maxsegsize */ 21190dbe28b3SPyun YongHyeon 0, /* flags */ 21200dbe28b3SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 21210dbe28b3SPyun YongHyeon &sc_if->msk_cdata.msk_rx_tag); 21220dbe28b3SPyun YongHyeon if (error != 0) { 21230dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 21240dbe28b3SPyun YongHyeon "failed to create Rx DMA tag\n"); 21250dbe28b3SPyun YongHyeon goto fail; 21260dbe28b3SPyun YongHyeon } 21270dbe28b3SPyun YongHyeon 21280dbe28b3SPyun YongHyeon /* Create tag for jumbo Rx buffers. */ 21290dbe28b3SPyun YongHyeon error = bus_dma_tag_create(sc_if->msk_cdata.msk_parent_tag,/* parent */ 21300dbe28b3SPyun YongHyeon PAGE_SIZE, 0, /* alignment, boundary */ 21310dbe28b3SPyun YongHyeon BUS_SPACE_MAXADDR, /* lowaddr */ 21320dbe28b3SPyun YongHyeon BUS_SPACE_MAXADDR, /* highaddr */ 21330dbe28b3SPyun YongHyeon NULL, NULL, /* filter, filterarg */ 21340dbe28b3SPyun YongHyeon MCLBYTES * MSK_MAXRXSEGS, /* maxsize */ 21350dbe28b3SPyun YongHyeon MSK_MAXRXSEGS, /* nsegments */ 21360dbe28b3SPyun YongHyeon MSK_JLEN, /* maxsegsize */ 21370dbe28b3SPyun YongHyeon 0, /* flags */ 21380dbe28b3SPyun YongHyeon NULL, NULL, /* lockfunc, lockarg */ 21390dbe28b3SPyun YongHyeon &sc_if->msk_cdata.msk_jumbo_rx_tag); 21400dbe28b3SPyun YongHyeon if (error != 0) { 21410dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 21420dbe28b3SPyun YongHyeon "failed to create jumbo Rx DMA tag\n"); 21430dbe28b3SPyun YongHyeon goto fail; 21440dbe28b3SPyun YongHyeon } 21450dbe28b3SPyun YongHyeon 21460dbe28b3SPyun YongHyeon /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 21470dbe28b3SPyun YongHyeon error = bus_dmamem_alloc(sc_if->msk_cdata.msk_tx_ring_tag, 21480dbe28b3SPyun YongHyeon (void **)&sc_if->msk_rdata.msk_tx_ring, BUS_DMA_WAITOK | 21490dbe28b3SPyun YongHyeon BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_tx_ring_map); 21500dbe28b3SPyun YongHyeon if (error != 0) { 21510dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 21520dbe28b3SPyun YongHyeon "failed to allocate DMA'able memory for Tx ring\n"); 21530dbe28b3SPyun YongHyeon goto fail; 21540dbe28b3SPyun YongHyeon } 21550dbe28b3SPyun YongHyeon 21560dbe28b3SPyun YongHyeon ctx.msk_busaddr = 0; 21570dbe28b3SPyun YongHyeon error = bus_dmamap_load(sc_if->msk_cdata.msk_tx_ring_tag, 21580dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_ring_map, sc_if->msk_rdata.msk_tx_ring, 21590dbe28b3SPyun YongHyeon MSK_TX_RING_SZ, msk_dmamap_cb, &ctx, 0); 21600dbe28b3SPyun YongHyeon if (error != 0) { 21610dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 21620dbe28b3SPyun YongHyeon "failed to load DMA'able memory for Tx ring\n"); 21630dbe28b3SPyun YongHyeon goto fail; 21640dbe28b3SPyun YongHyeon } 21650dbe28b3SPyun YongHyeon sc_if->msk_rdata.msk_tx_ring_paddr = ctx.msk_busaddr; 21660dbe28b3SPyun YongHyeon 21670dbe28b3SPyun YongHyeon /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 21680dbe28b3SPyun YongHyeon error = bus_dmamem_alloc(sc_if->msk_cdata.msk_rx_ring_tag, 21690dbe28b3SPyun YongHyeon (void **)&sc_if->msk_rdata.msk_rx_ring, BUS_DMA_WAITOK | 21700dbe28b3SPyun YongHyeon BUS_DMA_COHERENT | BUS_DMA_ZERO, &sc_if->msk_cdata.msk_rx_ring_map); 21710dbe28b3SPyun YongHyeon if (error != 0) { 21720dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 21730dbe28b3SPyun YongHyeon "failed to allocate DMA'able memory for Rx ring\n"); 21740dbe28b3SPyun YongHyeon goto fail; 21750dbe28b3SPyun YongHyeon } 21760dbe28b3SPyun YongHyeon 21770dbe28b3SPyun YongHyeon ctx.msk_busaddr = 0; 21780dbe28b3SPyun YongHyeon error = bus_dmamap_load(sc_if->msk_cdata.msk_rx_ring_tag, 21790dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_ring_map, sc_if->msk_rdata.msk_rx_ring, 21800dbe28b3SPyun YongHyeon MSK_RX_RING_SZ, msk_dmamap_cb, &ctx, 0); 21810dbe28b3SPyun YongHyeon if (error != 0) { 21820dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 21830dbe28b3SPyun YongHyeon "failed to load DMA'able memory for Rx ring\n"); 21840dbe28b3SPyun YongHyeon goto fail; 21850dbe28b3SPyun YongHyeon } 21860dbe28b3SPyun YongHyeon sc_if->msk_rdata.msk_rx_ring_paddr = ctx.msk_busaddr; 21870dbe28b3SPyun YongHyeon 21880dbe28b3SPyun YongHyeon /* Allocate DMA'able memory and load the DMA map for jumbo Rx ring. */ 21890dbe28b3SPyun YongHyeon error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 21900dbe28b3SPyun YongHyeon (void **)&sc_if->msk_rdata.msk_jumbo_rx_ring, 21910dbe28b3SPyun YongHyeon BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 21920dbe28b3SPyun YongHyeon &sc_if->msk_cdata.msk_jumbo_rx_ring_map); 21930dbe28b3SPyun YongHyeon if (error != 0) { 21940dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 21950dbe28b3SPyun YongHyeon "failed to allocate DMA'able memory for jumbo Rx ring\n"); 21960dbe28b3SPyun YongHyeon goto fail; 21970dbe28b3SPyun YongHyeon } 21980dbe28b3SPyun YongHyeon 21990dbe28b3SPyun YongHyeon ctx.msk_busaddr = 0; 22000dbe28b3SPyun YongHyeon error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 22010dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_jumbo_rx_ring_map, 22020dbe28b3SPyun YongHyeon sc_if->msk_rdata.msk_jumbo_rx_ring, MSK_JUMBO_RX_RING_SZ, 22030dbe28b3SPyun YongHyeon msk_dmamap_cb, &ctx, 0); 22040dbe28b3SPyun YongHyeon if (error != 0) { 22050dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 22060dbe28b3SPyun YongHyeon "failed to load DMA'able memory for jumbo Rx ring\n"); 22070dbe28b3SPyun YongHyeon goto fail; 22080dbe28b3SPyun YongHyeon } 22090dbe28b3SPyun YongHyeon sc_if->msk_rdata.msk_jumbo_rx_ring_paddr = ctx.msk_busaddr; 22100dbe28b3SPyun YongHyeon 22110dbe28b3SPyun YongHyeon /* Create DMA maps for Tx buffers. */ 22120dbe28b3SPyun YongHyeon for (i = 0; i < MSK_TX_RING_CNT; i++) { 22130dbe28b3SPyun YongHyeon txd = &sc_if->msk_cdata.msk_txdesc[i]; 22140dbe28b3SPyun YongHyeon txd->tx_m = NULL; 22150dbe28b3SPyun YongHyeon txd->tx_dmamap = NULL; 22160dbe28b3SPyun YongHyeon error = bus_dmamap_create(sc_if->msk_cdata.msk_tx_tag, 0, 22170dbe28b3SPyun YongHyeon &txd->tx_dmamap); 22180dbe28b3SPyun YongHyeon if (error != 0) { 22190dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 22200dbe28b3SPyun YongHyeon "failed to create Tx dmamap\n"); 22210dbe28b3SPyun YongHyeon goto fail; 22220dbe28b3SPyun YongHyeon } 22230dbe28b3SPyun YongHyeon } 22240dbe28b3SPyun YongHyeon /* Create DMA maps for Rx buffers. */ 22250dbe28b3SPyun YongHyeon if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 22260dbe28b3SPyun YongHyeon &sc_if->msk_cdata.msk_rx_sparemap)) != 0) { 22270dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 22280dbe28b3SPyun YongHyeon "failed to create spare Rx dmamap\n"); 22290dbe28b3SPyun YongHyeon goto fail; 22300dbe28b3SPyun YongHyeon } 22310dbe28b3SPyun YongHyeon for (i = 0; i < MSK_RX_RING_CNT; i++) { 22320dbe28b3SPyun YongHyeon rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 22330dbe28b3SPyun YongHyeon rxd->rx_m = NULL; 22340dbe28b3SPyun YongHyeon rxd->rx_dmamap = NULL; 22350dbe28b3SPyun YongHyeon error = bus_dmamap_create(sc_if->msk_cdata.msk_rx_tag, 0, 22360dbe28b3SPyun YongHyeon &rxd->rx_dmamap); 22370dbe28b3SPyun YongHyeon if (error != 0) { 22380dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 22390dbe28b3SPyun YongHyeon "failed to create Rx dmamap\n"); 22400dbe28b3SPyun YongHyeon goto fail; 22410dbe28b3SPyun YongHyeon } 22420dbe28b3SPyun YongHyeon } 22430dbe28b3SPyun YongHyeon /* Create DMA maps for jumbo Rx buffers. */ 22440dbe28b3SPyun YongHyeon if ((error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 22450dbe28b3SPyun YongHyeon &sc_if->msk_cdata.msk_jumbo_rx_sparemap)) != 0) { 22460dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 22470dbe28b3SPyun YongHyeon "failed to create spare jumbo Rx dmamap\n"); 22480dbe28b3SPyun YongHyeon goto fail; 22490dbe28b3SPyun YongHyeon } 22500dbe28b3SPyun YongHyeon for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 22510dbe28b3SPyun YongHyeon jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 22520dbe28b3SPyun YongHyeon jrxd->rx_m = NULL; 22530dbe28b3SPyun YongHyeon jrxd->rx_dmamap = NULL; 22540dbe28b3SPyun YongHyeon error = bus_dmamap_create(sc_if->msk_cdata.msk_jumbo_rx_tag, 0, 22550dbe28b3SPyun YongHyeon &jrxd->rx_dmamap); 22560dbe28b3SPyun YongHyeon if (error != 0) { 22570dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 22580dbe28b3SPyun YongHyeon "failed to create jumbo Rx dmamap\n"); 22590dbe28b3SPyun YongHyeon goto fail; 22600dbe28b3SPyun YongHyeon } 22610dbe28b3SPyun YongHyeon } 22620dbe28b3SPyun YongHyeon 22630dbe28b3SPyun YongHyeon /* Allocate DMA'able memory and load the DMA map for jumbo buf. */ 22640dbe28b3SPyun YongHyeon error = bus_dmamem_alloc(sc_if->msk_cdata.msk_jumbo_tag, 22650dbe28b3SPyun YongHyeon (void **)&sc_if->msk_rdata.msk_jumbo_buf, 22660dbe28b3SPyun YongHyeon BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 22670dbe28b3SPyun YongHyeon &sc_if->msk_cdata.msk_jumbo_map); 22680dbe28b3SPyun YongHyeon if (error != 0) { 22690dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 22700dbe28b3SPyun YongHyeon "failed to allocate DMA'able memory for jumbo buf\n"); 22710dbe28b3SPyun YongHyeon goto fail; 22720dbe28b3SPyun YongHyeon } 22730dbe28b3SPyun YongHyeon 22740dbe28b3SPyun YongHyeon ctx.msk_busaddr = 0; 22750dbe28b3SPyun YongHyeon error = bus_dmamap_load(sc_if->msk_cdata.msk_jumbo_tag, 22760dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_jumbo_map, sc_if->msk_rdata.msk_jumbo_buf, 22770dbe28b3SPyun YongHyeon MSK_JMEM, msk_dmamap_cb, &ctx, 0); 22780dbe28b3SPyun YongHyeon if (error != 0) { 22790dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 22800dbe28b3SPyun YongHyeon "failed to load DMA'able memory for jumbobuf\n"); 22810dbe28b3SPyun YongHyeon goto fail; 22820dbe28b3SPyun YongHyeon } 22830dbe28b3SPyun YongHyeon sc_if->msk_rdata.msk_jumbo_buf_paddr = ctx.msk_busaddr; 22840dbe28b3SPyun YongHyeon 22850dbe28b3SPyun YongHyeon /* 22860dbe28b3SPyun YongHyeon * Now divide it up into 9K pieces and save the addresses 22870dbe28b3SPyun YongHyeon * in an array. 22880dbe28b3SPyun YongHyeon */ 22890dbe28b3SPyun YongHyeon ptr = sc_if->msk_rdata.msk_jumbo_buf; 22900dbe28b3SPyun YongHyeon for (i = 0; i < MSK_JSLOTS; i++) { 22910dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_jslots[i] = ptr; 22920dbe28b3SPyun YongHyeon ptr += MSK_JLEN; 22930dbe28b3SPyun YongHyeon entry = malloc(sizeof(struct msk_jpool_entry), 22940dbe28b3SPyun YongHyeon M_DEVBUF, M_WAITOK); 22950dbe28b3SPyun YongHyeon if (entry == NULL) { 22960dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 22970dbe28b3SPyun YongHyeon "no memory for jumbo buffers!\n"); 22980dbe28b3SPyun YongHyeon error = ENOMEM; 22990dbe28b3SPyun YongHyeon goto fail; 23000dbe28b3SPyun YongHyeon } 23010dbe28b3SPyun YongHyeon entry->slot = i; 23020dbe28b3SPyun YongHyeon SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, 23030dbe28b3SPyun YongHyeon jpool_entries); 23040dbe28b3SPyun YongHyeon } 23050dbe28b3SPyun YongHyeon 23060dbe28b3SPyun YongHyeon fail: 23070dbe28b3SPyun YongHyeon return (error); 23080dbe28b3SPyun YongHyeon } 23090dbe28b3SPyun YongHyeon 23100dbe28b3SPyun YongHyeon static void 23110dbe28b3SPyun YongHyeon msk_txrx_dma_free(struct msk_if_softc *sc_if) 23120dbe28b3SPyun YongHyeon { 23130dbe28b3SPyun YongHyeon struct msk_txdesc *txd; 23140dbe28b3SPyun YongHyeon struct msk_rxdesc *rxd; 23150dbe28b3SPyun YongHyeon struct msk_rxdesc *jrxd; 23160dbe28b3SPyun YongHyeon struct msk_jpool_entry *entry; 23170dbe28b3SPyun YongHyeon int i; 23180dbe28b3SPyun YongHyeon 23190dbe28b3SPyun YongHyeon MSK_JLIST_LOCK(sc_if); 23200dbe28b3SPyun YongHyeon while ((entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead))) { 23210dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 23220dbe28b3SPyun YongHyeon "asked to free buffer that is in use!\n"); 23230dbe28b3SPyun YongHyeon SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries); 23240dbe28b3SPyun YongHyeon SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, 23250dbe28b3SPyun YongHyeon jpool_entries); 23260dbe28b3SPyun YongHyeon } 23270dbe28b3SPyun YongHyeon 23280dbe28b3SPyun YongHyeon while (!SLIST_EMPTY(&sc_if->msk_jfree_listhead)) { 23290dbe28b3SPyun YongHyeon entry = SLIST_FIRST(&sc_if->msk_jfree_listhead); 23300dbe28b3SPyun YongHyeon SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries); 23310dbe28b3SPyun YongHyeon free(entry, M_DEVBUF); 23320dbe28b3SPyun YongHyeon } 23330dbe28b3SPyun YongHyeon MSK_JLIST_UNLOCK(sc_if); 23340dbe28b3SPyun YongHyeon 23350dbe28b3SPyun YongHyeon /* Destroy jumbo buffer block. */ 23360dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_jumbo_map) 23370dbe28b3SPyun YongHyeon bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_tag, 23380dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_jumbo_map); 23390dbe28b3SPyun YongHyeon 23400dbe28b3SPyun YongHyeon if (sc_if->msk_rdata.msk_jumbo_buf) { 23410dbe28b3SPyun YongHyeon bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_tag, 23420dbe28b3SPyun YongHyeon sc_if->msk_rdata.msk_jumbo_buf, 23430dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_jumbo_map); 23440dbe28b3SPyun YongHyeon sc_if->msk_rdata.msk_jumbo_buf = NULL; 23450dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_jumbo_map = NULL; 23460dbe28b3SPyun YongHyeon } 23470dbe28b3SPyun YongHyeon 23480dbe28b3SPyun YongHyeon /* Tx ring. */ 23490dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_tx_ring_tag) { 23500dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_tx_ring_map) 23510dbe28b3SPyun YongHyeon bus_dmamap_unload(sc_if->msk_cdata.msk_tx_ring_tag, 23520dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_ring_map); 23530dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_tx_ring_map && 23540dbe28b3SPyun YongHyeon sc_if->msk_rdata.msk_tx_ring) 23550dbe28b3SPyun YongHyeon bus_dmamem_free(sc_if->msk_cdata.msk_tx_ring_tag, 23560dbe28b3SPyun YongHyeon sc_if->msk_rdata.msk_tx_ring, 23570dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_ring_map); 23580dbe28b3SPyun YongHyeon sc_if->msk_rdata.msk_tx_ring = NULL; 23590dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_ring_map = NULL; 23600dbe28b3SPyun YongHyeon bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_ring_tag); 23610dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_ring_tag = NULL; 23620dbe28b3SPyun YongHyeon } 23630dbe28b3SPyun YongHyeon /* Rx ring. */ 23640dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_rx_ring_tag) { 23650dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_rx_ring_map) 23660dbe28b3SPyun YongHyeon bus_dmamap_unload(sc_if->msk_cdata.msk_rx_ring_tag, 23670dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_ring_map); 23680dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_rx_ring_map && 23690dbe28b3SPyun YongHyeon sc_if->msk_rdata.msk_rx_ring) 23700dbe28b3SPyun YongHyeon bus_dmamem_free(sc_if->msk_cdata.msk_rx_ring_tag, 23710dbe28b3SPyun YongHyeon sc_if->msk_rdata.msk_rx_ring, 23720dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_ring_map); 23730dbe28b3SPyun YongHyeon sc_if->msk_rdata.msk_rx_ring = NULL; 23740dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_ring_map = NULL; 23750dbe28b3SPyun YongHyeon bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_ring_tag); 23760dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_ring_tag = NULL; 23770dbe28b3SPyun YongHyeon } 23780dbe28b3SPyun YongHyeon /* Jumbo Rx ring. */ 23790dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_jumbo_rx_ring_tag) { 23800dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_jumbo_rx_ring_map) 23810dbe28b3SPyun YongHyeon bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 23820dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_jumbo_rx_ring_map); 23830dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_jumbo_rx_ring_map && 23840dbe28b3SPyun YongHyeon sc_if->msk_rdata.msk_jumbo_rx_ring) 23850dbe28b3SPyun YongHyeon bus_dmamem_free(sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 23860dbe28b3SPyun YongHyeon sc_if->msk_rdata.msk_jumbo_rx_ring, 23870dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_jumbo_rx_ring_map); 23880dbe28b3SPyun YongHyeon sc_if->msk_rdata.msk_jumbo_rx_ring = NULL; 23890dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_jumbo_rx_ring_map = NULL; 23900dbe28b3SPyun YongHyeon bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_ring_tag); 23910dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_jumbo_rx_ring_tag = NULL; 23920dbe28b3SPyun YongHyeon } 23930dbe28b3SPyun YongHyeon /* Tx buffers. */ 23940dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_tx_tag) { 23950dbe28b3SPyun YongHyeon for (i = 0; i < MSK_TX_RING_CNT; i++) { 23960dbe28b3SPyun YongHyeon txd = &sc_if->msk_cdata.msk_txdesc[i]; 23970dbe28b3SPyun YongHyeon if (txd->tx_dmamap) { 23980dbe28b3SPyun YongHyeon bus_dmamap_destroy(sc_if->msk_cdata.msk_tx_tag, 23990dbe28b3SPyun YongHyeon txd->tx_dmamap); 24000dbe28b3SPyun YongHyeon txd->tx_dmamap = NULL; 24010dbe28b3SPyun YongHyeon } 24020dbe28b3SPyun YongHyeon } 24030dbe28b3SPyun YongHyeon bus_dma_tag_destroy(sc_if->msk_cdata.msk_tx_tag); 24040dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_tag = NULL; 24050dbe28b3SPyun YongHyeon } 24060dbe28b3SPyun YongHyeon /* Rx buffers. */ 24070dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_rx_tag) { 24080dbe28b3SPyun YongHyeon for (i = 0; i < MSK_RX_RING_CNT; i++) { 24090dbe28b3SPyun YongHyeon rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 24100dbe28b3SPyun YongHyeon if (rxd->rx_dmamap) { 24110dbe28b3SPyun YongHyeon bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 24120dbe28b3SPyun YongHyeon rxd->rx_dmamap); 24130dbe28b3SPyun YongHyeon rxd->rx_dmamap = NULL; 24140dbe28b3SPyun YongHyeon } 24150dbe28b3SPyun YongHyeon } 24160dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_rx_sparemap) { 24170dbe28b3SPyun YongHyeon bus_dmamap_destroy(sc_if->msk_cdata.msk_rx_tag, 24180dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_sparemap); 24190dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_sparemap = 0; 24200dbe28b3SPyun YongHyeon } 24210dbe28b3SPyun YongHyeon bus_dma_tag_destroy(sc_if->msk_cdata.msk_rx_tag); 24220dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_tag = NULL; 24230dbe28b3SPyun YongHyeon } 24240dbe28b3SPyun YongHyeon /* Jumbo Rx buffers. */ 24250dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_jumbo_rx_tag) { 24260dbe28b3SPyun YongHyeon for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 24270dbe28b3SPyun YongHyeon jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 24280dbe28b3SPyun YongHyeon if (jrxd->rx_dmamap) { 24290dbe28b3SPyun YongHyeon bus_dmamap_destroy( 24300dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_jumbo_rx_tag, 24310dbe28b3SPyun YongHyeon jrxd->rx_dmamap); 24320dbe28b3SPyun YongHyeon jrxd->rx_dmamap = NULL; 24330dbe28b3SPyun YongHyeon } 24340dbe28b3SPyun YongHyeon } 24350dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_jumbo_rx_sparemap) { 24360dbe28b3SPyun YongHyeon bus_dmamap_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag, 24370dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_jumbo_rx_sparemap); 24380dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_jumbo_rx_sparemap = 0; 24390dbe28b3SPyun YongHyeon } 24400dbe28b3SPyun YongHyeon bus_dma_tag_destroy(sc_if->msk_cdata.msk_jumbo_rx_tag); 24410dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_jumbo_rx_tag = NULL; 24420dbe28b3SPyun YongHyeon } 24430dbe28b3SPyun YongHyeon 24440dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_parent_tag) { 24450dbe28b3SPyun YongHyeon bus_dma_tag_destroy(sc_if->msk_cdata.msk_parent_tag); 24460dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_parent_tag = NULL; 24470dbe28b3SPyun YongHyeon } 24480dbe28b3SPyun YongHyeon mtx_destroy(&sc_if->msk_jlist_mtx); 24490dbe28b3SPyun YongHyeon } 24500dbe28b3SPyun YongHyeon 24510dbe28b3SPyun YongHyeon /* 24520dbe28b3SPyun YongHyeon * Allocate a jumbo buffer. 24530dbe28b3SPyun YongHyeon */ 24540dbe28b3SPyun YongHyeon static void * 24550dbe28b3SPyun YongHyeon msk_jalloc(struct msk_if_softc *sc_if) 24560dbe28b3SPyun YongHyeon { 24570dbe28b3SPyun YongHyeon struct msk_jpool_entry *entry; 24580dbe28b3SPyun YongHyeon 24590dbe28b3SPyun YongHyeon MSK_JLIST_LOCK(sc_if); 24600dbe28b3SPyun YongHyeon 24610dbe28b3SPyun YongHyeon entry = SLIST_FIRST(&sc_if->msk_jfree_listhead); 24620dbe28b3SPyun YongHyeon 24630dbe28b3SPyun YongHyeon if (entry == NULL) { 24640dbe28b3SPyun YongHyeon MSK_JLIST_UNLOCK(sc_if); 24650dbe28b3SPyun YongHyeon return (NULL); 24660dbe28b3SPyun YongHyeon } 24670dbe28b3SPyun YongHyeon 24680dbe28b3SPyun YongHyeon SLIST_REMOVE_HEAD(&sc_if->msk_jfree_listhead, jpool_entries); 24690dbe28b3SPyun YongHyeon SLIST_INSERT_HEAD(&sc_if->msk_jinuse_listhead, entry, jpool_entries); 24700dbe28b3SPyun YongHyeon 24710dbe28b3SPyun YongHyeon MSK_JLIST_UNLOCK(sc_if); 24720dbe28b3SPyun YongHyeon 24730dbe28b3SPyun YongHyeon return (sc_if->msk_cdata.msk_jslots[entry->slot]); 24740dbe28b3SPyun YongHyeon } 24750dbe28b3SPyun YongHyeon 24760dbe28b3SPyun YongHyeon /* 24770dbe28b3SPyun YongHyeon * Release a jumbo buffer. 24780dbe28b3SPyun YongHyeon */ 24790dbe28b3SPyun YongHyeon static void 24800dbe28b3SPyun YongHyeon msk_jfree(void *buf, void *args) 24810dbe28b3SPyun YongHyeon { 24820dbe28b3SPyun YongHyeon struct msk_if_softc *sc_if; 24830dbe28b3SPyun YongHyeon struct msk_jpool_entry *entry; 24840dbe28b3SPyun YongHyeon int i; 24850dbe28b3SPyun YongHyeon 24860dbe28b3SPyun YongHyeon /* Extract the softc struct pointer. */ 24870dbe28b3SPyun YongHyeon sc_if = (struct msk_if_softc *)args; 24880dbe28b3SPyun YongHyeon KASSERT(sc_if != NULL, ("%s: can't find softc pointer!", __func__)); 24890dbe28b3SPyun YongHyeon 24900dbe28b3SPyun YongHyeon MSK_JLIST_LOCK(sc_if); 24910dbe28b3SPyun YongHyeon /* Calculate the slot this buffer belongs to. */ 24920dbe28b3SPyun YongHyeon i = ((vm_offset_t)buf 24930dbe28b3SPyun YongHyeon - (vm_offset_t)sc_if->msk_rdata.msk_jumbo_buf) / MSK_JLEN; 24940dbe28b3SPyun YongHyeon KASSERT(i >= 0 && i < MSK_JSLOTS, 24950dbe28b3SPyun YongHyeon ("%s: asked to free buffer that we don't manage!", __func__)); 24960dbe28b3SPyun YongHyeon 24970dbe28b3SPyun YongHyeon entry = SLIST_FIRST(&sc_if->msk_jinuse_listhead); 24980dbe28b3SPyun YongHyeon KASSERT(entry != NULL, ("%s: buffer not in use!", __func__)); 24990dbe28b3SPyun YongHyeon entry->slot = i; 25000dbe28b3SPyun YongHyeon SLIST_REMOVE_HEAD(&sc_if->msk_jinuse_listhead, jpool_entries); 25010dbe28b3SPyun YongHyeon SLIST_INSERT_HEAD(&sc_if->msk_jfree_listhead, entry, jpool_entries); 25020dbe28b3SPyun YongHyeon if (SLIST_EMPTY(&sc_if->msk_jinuse_listhead)) 25030dbe28b3SPyun YongHyeon wakeup(sc_if); 25040dbe28b3SPyun YongHyeon 25050dbe28b3SPyun YongHyeon MSK_JLIST_UNLOCK(sc_if); 25060dbe28b3SPyun YongHyeon } 25070dbe28b3SPyun YongHyeon 25080dbe28b3SPyun YongHyeon static int 25090dbe28b3SPyun YongHyeon msk_encap(struct msk_if_softc *sc_if, struct mbuf **m_head) 25100dbe28b3SPyun YongHyeon { 25110dbe28b3SPyun YongHyeon struct msk_txdesc *txd, *txd_last; 25120dbe28b3SPyun YongHyeon struct msk_tx_desc *tx_le; 25130dbe28b3SPyun YongHyeon struct mbuf *m; 25140dbe28b3SPyun YongHyeon bus_dmamap_t map; 25150dbe28b3SPyun YongHyeon bus_dma_segment_t txsegs[MSK_MAXTXSEGS]; 25160dbe28b3SPyun YongHyeon uint32_t control, prod, si; 25170dbe28b3SPyun YongHyeon uint16_t offset, tcp_offset, tso_mtu; 25180dbe28b3SPyun YongHyeon int error, i, nseg, tso; 25190dbe28b3SPyun YongHyeon 25200dbe28b3SPyun YongHyeon MSK_IF_LOCK_ASSERT(sc_if); 25210dbe28b3SPyun YongHyeon 25220dbe28b3SPyun YongHyeon tcp_offset = offset = 0; 25230dbe28b3SPyun YongHyeon m = *m_head; 25240dbe28b3SPyun YongHyeon if ((m->m_pkthdr.csum_flags & (MSK_CSUM_FEATURES | CSUM_TSO)) != 0) { 25250dbe28b3SPyun YongHyeon /* 25260dbe28b3SPyun YongHyeon * Since mbuf has no protocol specific structure information 25270dbe28b3SPyun YongHyeon * in it we have to inspect protocol information here to 25280dbe28b3SPyun YongHyeon * setup TSO and checksum offload. I don't know why Marvell 25290dbe28b3SPyun YongHyeon * made a such decision in chip design because other GigE 25300dbe28b3SPyun YongHyeon * hardwares normally takes care of all these chores in 25310dbe28b3SPyun YongHyeon * hardware. However, TSO performance of Yukon II is very 25320dbe28b3SPyun YongHyeon * good such that it's worth to implement it. 25330dbe28b3SPyun YongHyeon */ 25340dbe28b3SPyun YongHyeon struct ether_header *eh; 25350dbe28b3SPyun YongHyeon struct ip *ip; 25360dbe28b3SPyun YongHyeon struct tcphdr *tcp; 25370dbe28b3SPyun YongHyeon 25380dbe28b3SPyun YongHyeon /* TODO check for M_WRITABLE(m) */ 25390dbe28b3SPyun YongHyeon 25400dbe28b3SPyun YongHyeon offset = sizeof(struct ether_header); 25410dbe28b3SPyun YongHyeon m = m_pullup(m, offset); 25420dbe28b3SPyun YongHyeon if (m == NULL) { 25430dbe28b3SPyun YongHyeon *m_head = NULL; 25440dbe28b3SPyun YongHyeon return (ENOBUFS); 25450dbe28b3SPyun YongHyeon } 25460dbe28b3SPyun YongHyeon eh = mtod(m, struct ether_header *); 25470dbe28b3SPyun YongHyeon /* Check if hardware VLAN insertion is off. */ 25480dbe28b3SPyun YongHyeon if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 25490dbe28b3SPyun YongHyeon offset = sizeof(struct ether_vlan_header); 25500dbe28b3SPyun YongHyeon m = m_pullup(m, offset); 25510dbe28b3SPyun YongHyeon if (m == NULL) { 25520dbe28b3SPyun YongHyeon *m_head = NULL; 25530dbe28b3SPyun YongHyeon return (ENOBUFS); 25540dbe28b3SPyun YongHyeon } 2555b5898b80SPyun YongHyeon } 25560dbe28b3SPyun YongHyeon m = m_pullup(m, offset + sizeof(struct ip)); 25570dbe28b3SPyun YongHyeon if (m == NULL) { 25580dbe28b3SPyun YongHyeon *m_head = NULL; 25590dbe28b3SPyun YongHyeon return (ENOBUFS); 25600dbe28b3SPyun YongHyeon } 2561b5898b80SPyun YongHyeon ip = (struct ip *)(mtod(m, char *) + offset); 25620dbe28b3SPyun YongHyeon offset += (ip->ip_hl << 2); 25630dbe28b3SPyun YongHyeon tcp_offset = offset; 2564b5898b80SPyun YongHyeon /* 2565b5898b80SPyun YongHyeon * It seems that Yukon II has Tx checksum offload bug for 2566b5898b80SPyun YongHyeon * small TCP packets that's less than 60 bytes in size 2567b5898b80SPyun YongHyeon * (e.g. TCP window probe packet, pure ACK packet). 2568b5898b80SPyun YongHyeon * Common work around like padding with zeros to make the 2569b5898b80SPyun YongHyeon * frame minimum ethernet frame size didn't work at all. 2570b5898b80SPyun YongHyeon * Instead of disabling checksum offload completely we 2571b5898b80SPyun YongHyeon * resort to S/W checksum routine when we encounter short 2572b5898b80SPyun YongHyeon * TCP frames. 2573b5898b80SPyun YongHyeon * Short UDP packets appear to be handled correctly by 2574b5898b80SPyun YongHyeon * Yukon II. 2575b5898b80SPyun YongHyeon */ 2576b5898b80SPyun YongHyeon if (m->m_pkthdr.len < MSK_MIN_FRAMELEN && 2577b5898b80SPyun YongHyeon (m->m_pkthdr.csum_flags & CSUM_TCP) != 0) { 2578b5898b80SPyun YongHyeon uint16_t csum; 2579b5898b80SPyun YongHyeon 2580b5898b80SPyun YongHyeon csum = in_cksum_skip(m, ntohs(ip->ip_len) + offset - 2581b5898b80SPyun YongHyeon (ip->ip_hl << 2), offset); 2582b5898b80SPyun YongHyeon *(uint16_t *)(m->m_data + offset + 2583b5898b80SPyun YongHyeon m->m_pkthdr.csum_data) = csum; 2584b5898b80SPyun YongHyeon m->m_pkthdr.csum_flags &= ~CSUM_TCP; 2585b5898b80SPyun YongHyeon } 25860dbe28b3SPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 25870dbe28b3SPyun YongHyeon m = m_pullup(m, offset + sizeof(struct tcphdr)); 25880dbe28b3SPyun YongHyeon if (m == NULL) { 25890dbe28b3SPyun YongHyeon *m_head = NULL; 25900dbe28b3SPyun YongHyeon return (ENOBUFS); 25910dbe28b3SPyun YongHyeon } 25923326191fSPyun YongHyeon tcp = (struct tcphdr *)(mtod(m, char *) + offset); 25930dbe28b3SPyun YongHyeon offset += (tcp->th_off << 2); 25940dbe28b3SPyun YongHyeon } 25950dbe28b3SPyun YongHyeon *m_head = m; 25960dbe28b3SPyun YongHyeon } 25970dbe28b3SPyun YongHyeon 25980dbe28b3SPyun YongHyeon prod = sc_if->msk_cdata.msk_tx_prod; 25990dbe28b3SPyun YongHyeon txd = &sc_if->msk_cdata.msk_txdesc[prod]; 26000dbe28b3SPyun YongHyeon txd_last = txd; 26010dbe28b3SPyun YongHyeon map = txd->tx_dmamap; 26020dbe28b3SPyun YongHyeon error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, map, 26030dbe28b3SPyun YongHyeon *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 26040dbe28b3SPyun YongHyeon if (error == EFBIG) { 2605304a4c6fSJohn Baldwin m = m_collapse(*m_head, M_DONTWAIT, MSK_MAXTXSEGS); 26060dbe28b3SPyun YongHyeon if (m == NULL) { 26070dbe28b3SPyun YongHyeon m_freem(*m_head); 26080dbe28b3SPyun YongHyeon *m_head = NULL; 26090dbe28b3SPyun YongHyeon return (ENOBUFS); 26100dbe28b3SPyun YongHyeon } 26110dbe28b3SPyun YongHyeon *m_head = m; 26120dbe28b3SPyun YongHyeon error = bus_dmamap_load_mbuf_sg(sc_if->msk_cdata.msk_tx_tag, 26130dbe28b3SPyun YongHyeon map, *m_head, txsegs, &nseg, BUS_DMA_NOWAIT); 26140dbe28b3SPyun YongHyeon if (error != 0) { 26150dbe28b3SPyun YongHyeon m_freem(*m_head); 26160dbe28b3SPyun YongHyeon *m_head = NULL; 26170dbe28b3SPyun YongHyeon return (error); 26180dbe28b3SPyun YongHyeon } 26190dbe28b3SPyun YongHyeon } else if (error != 0) 26200dbe28b3SPyun YongHyeon return (error); 26210dbe28b3SPyun YongHyeon if (nseg == 0) { 26220dbe28b3SPyun YongHyeon m_freem(*m_head); 26230dbe28b3SPyun YongHyeon *m_head = NULL; 26240dbe28b3SPyun YongHyeon return (EIO); 26250dbe28b3SPyun YongHyeon } 26260dbe28b3SPyun YongHyeon 26270dbe28b3SPyun YongHyeon /* Check number of available descriptors. */ 26280dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_tx_cnt + nseg >= 26290dbe28b3SPyun YongHyeon (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT)) { 26300dbe28b3SPyun YongHyeon bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, map); 26310dbe28b3SPyun YongHyeon return (ENOBUFS); 26320dbe28b3SPyun YongHyeon } 26330dbe28b3SPyun YongHyeon 26340dbe28b3SPyun YongHyeon control = 0; 26350dbe28b3SPyun YongHyeon tso = 0; 26360dbe28b3SPyun YongHyeon tx_le = NULL; 26370dbe28b3SPyun YongHyeon 26380dbe28b3SPyun YongHyeon /* Check TSO support. */ 26390dbe28b3SPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 26400dbe28b3SPyun YongHyeon tso_mtu = offset + m->m_pkthdr.tso_segsz; 26410dbe28b3SPyun YongHyeon if (tso_mtu != sc_if->msk_cdata.msk_tso_mtu) { 26420dbe28b3SPyun YongHyeon tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 26430dbe28b3SPyun YongHyeon tx_le->msk_addr = htole32(tso_mtu); 26440dbe28b3SPyun YongHyeon tx_le->msk_control = htole32(OP_LRGLEN | HW_OWNER); 26450dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_cnt++; 26460dbe28b3SPyun YongHyeon MSK_INC(prod, MSK_TX_RING_CNT); 26470dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tso_mtu = tso_mtu; 26480dbe28b3SPyun YongHyeon } 26490dbe28b3SPyun YongHyeon tso++; 26500dbe28b3SPyun YongHyeon } 26510dbe28b3SPyun YongHyeon /* Check if we have a VLAN tag to insert. */ 26520dbe28b3SPyun YongHyeon if ((m->m_flags & M_VLANTAG) != 0) { 26530dbe28b3SPyun YongHyeon if (tso == 0) { 26540dbe28b3SPyun YongHyeon tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 26550dbe28b3SPyun YongHyeon tx_le->msk_addr = htole32(0); 26560dbe28b3SPyun YongHyeon tx_le->msk_control = htole32(OP_VLAN | HW_OWNER | 26570dbe28b3SPyun YongHyeon htons(m->m_pkthdr.ether_vtag)); 26580dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_cnt++; 26590dbe28b3SPyun YongHyeon MSK_INC(prod, MSK_TX_RING_CNT); 26600dbe28b3SPyun YongHyeon } else { 26610dbe28b3SPyun YongHyeon tx_le->msk_control |= htole32(OP_VLAN | 26620dbe28b3SPyun YongHyeon htons(m->m_pkthdr.ether_vtag)); 26630dbe28b3SPyun YongHyeon } 26640dbe28b3SPyun YongHyeon control |= INS_VLAN; 26650dbe28b3SPyun YongHyeon } 26660dbe28b3SPyun YongHyeon /* Check if we have to handle checksum offload. */ 26670dbe28b3SPyun YongHyeon if (tso == 0 && (m->m_pkthdr.csum_flags & MSK_CSUM_FEATURES) != 0) { 26680dbe28b3SPyun YongHyeon tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 26690dbe28b3SPyun YongHyeon tx_le->msk_addr = htole32(((tcp_offset + m->m_pkthdr.csum_data) 26700dbe28b3SPyun YongHyeon & 0xffff) | ((uint32_t)tcp_offset << 16)); 26710dbe28b3SPyun YongHyeon tx_le->msk_control = htole32(1 << 16 | (OP_TCPLISW | HW_OWNER)); 26720dbe28b3SPyun YongHyeon control = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM; 26730dbe28b3SPyun YongHyeon if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 26740dbe28b3SPyun YongHyeon control |= UDPTCP; 26750dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_cnt++; 26760dbe28b3SPyun YongHyeon MSK_INC(prod, MSK_TX_RING_CNT); 26770dbe28b3SPyun YongHyeon } 26780dbe28b3SPyun YongHyeon 26790dbe28b3SPyun YongHyeon si = prod; 26800dbe28b3SPyun YongHyeon tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 26810dbe28b3SPyun YongHyeon tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[0].ds_addr)); 26820dbe28b3SPyun YongHyeon if (tso == 0) 26830dbe28b3SPyun YongHyeon tx_le->msk_control = htole32(txsegs[0].ds_len | control | 26840dbe28b3SPyun YongHyeon OP_PACKET); 26850dbe28b3SPyun YongHyeon else 26860dbe28b3SPyun YongHyeon tx_le->msk_control = htole32(txsegs[0].ds_len | control | 26870dbe28b3SPyun YongHyeon OP_LARGESEND); 26880dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_cnt++; 26890dbe28b3SPyun YongHyeon MSK_INC(prod, MSK_TX_RING_CNT); 26900dbe28b3SPyun YongHyeon 26910dbe28b3SPyun YongHyeon for (i = 1; i < nseg; i++) { 26920dbe28b3SPyun YongHyeon tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 26930dbe28b3SPyun YongHyeon tx_le->msk_addr = htole32(MSK_ADDR_LO(txsegs[i].ds_addr)); 26940dbe28b3SPyun YongHyeon tx_le->msk_control = htole32(txsegs[i].ds_len | control | 26950dbe28b3SPyun YongHyeon OP_BUFFER | HW_OWNER); 26960dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_cnt++; 26970dbe28b3SPyun YongHyeon MSK_INC(prod, MSK_TX_RING_CNT); 26980dbe28b3SPyun YongHyeon } 26990dbe28b3SPyun YongHyeon /* Update producer index. */ 27000dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_prod = prod; 27010dbe28b3SPyun YongHyeon 27020dbe28b3SPyun YongHyeon /* Set EOP on the last desciptor. */ 27030dbe28b3SPyun YongHyeon prod = (prod + MSK_TX_RING_CNT - 1) % MSK_TX_RING_CNT; 27040dbe28b3SPyun YongHyeon tx_le = &sc_if->msk_rdata.msk_tx_ring[prod]; 27050dbe28b3SPyun YongHyeon tx_le->msk_control |= htole32(EOP); 27060dbe28b3SPyun YongHyeon 27070dbe28b3SPyun YongHyeon /* Turn the first descriptor ownership to hardware. */ 27080dbe28b3SPyun YongHyeon tx_le = &sc_if->msk_rdata.msk_tx_ring[si]; 27090dbe28b3SPyun YongHyeon tx_le->msk_control |= htole32(HW_OWNER); 27100dbe28b3SPyun YongHyeon 27110dbe28b3SPyun YongHyeon txd = &sc_if->msk_cdata.msk_txdesc[prod]; 27120dbe28b3SPyun YongHyeon map = txd_last->tx_dmamap; 27130dbe28b3SPyun YongHyeon txd_last->tx_dmamap = txd->tx_dmamap; 27140dbe28b3SPyun YongHyeon txd->tx_dmamap = map; 27150dbe28b3SPyun YongHyeon txd->tx_m = m; 27160dbe28b3SPyun YongHyeon 27170dbe28b3SPyun YongHyeon /* Sync descriptors. */ 27180dbe28b3SPyun YongHyeon bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, map, BUS_DMASYNC_PREWRITE); 27190dbe28b3SPyun YongHyeon bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 27200dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_ring_map, 27210dbe28b3SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 27220dbe28b3SPyun YongHyeon 27230dbe28b3SPyun YongHyeon return (0); 27240dbe28b3SPyun YongHyeon } 27250dbe28b3SPyun YongHyeon 27260dbe28b3SPyun YongHyeon static void 27270dbe28b3SPyun YongHyeon msk_tx_task(void *arg, int pending) 27280dbe28b3SPyun YongHyeon { 27290dbe28b3SPyun YongHyeon struct ifnet *ifp; 27300dbe28b3SPyun YongHyeon 27310dbe28b3SPyun YongHyeon ifp = arg; 27320dbe28b3SPyun YongHyeon msk_start(ifp); 27330dbe28b3SPyun YongHyeon } 27340dbe28b3SPyun YongHyeon 27350dbe28b3SPyun YongHyeon static void 27360dbe28b3SPyun YongHyeon msk_start(struct ifnet *ifp) 27370dbe28b3SPyun YongHyeon { 27380dbe28b3SPyun YongHyeon struct msk_if_softc *sc_if; 27390dbe28b3SPyun YongHyeon struct mbuf *m_head; 27400dbe28b3SPyun YongHyeon int enq; 27410dbe28b3SPyun YongHyeon 27420dbe28b3SPyun YongHyeon sc_if = ifp->if_softc; 27430dbe28b3SPyun YongHyeon 27440dbe28b3SPyun YongHyeon MSK_IF_LOCK(sc_if); 27450dbe28b3SPyun YongHyeon 27460dbe28b3SPyun YongHyeon if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 27470dbe28b3SPyun YongHyeon IFF_DRV_RUNNING || sc_if->msk_link == 0) { 27480dbe28b3SPyun YongHyeon MSK_IF_UNLOCK(sc_if); 27490dbe28b3SPyun YongHyeon return; 27500dbe28b3SPyun YongHyeon } 27510dbe28b3SPyun YongHyeon 27520dbe28b3SPyun YongHyeon for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 27530dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_cnt < 27540dbe28b3SPyun YongHyeon (MSK_TX_RING_CNT - MSK_RESERVED_TX_DESC_CNT); ) { 27550dbe28b3SPyun YongHyeon IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 27560dbe28b3SPyun YongHyeon if (m_head == NULL) 27570dbe28b3SPyun YongHyeon break; 27580dbe28b3SPyun YongHyeon /* 27590dbe28b3SPyun YongHyeon * Pack the data into the transmit ring. If we 27600dbe28b3SPyun YongHyeon * don't have room, set the OACTIVE flag and wait 27610dbe28b3SPyun YongHyeon * for the NIC to drain the ring. 27620dbe28b3SPyun YongHyeon */ 27630dbe28b3SPyun YongHyeon if (msk_encap(sc_if, &m_head) != 0) { 27640dbe28b3SPyun YongHyeon if (m_head == NULL) 27650dbe28b3SPyun YongHyeon break; 27660dbe28b3SPyun YongHyeon IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 27670dbe28b3SPyun YongHyeon ifp->if_drv_flags |= IFF_DRV_OACTIVE; 27680dbe28b3SPyun YongHyeon break; 27690dbe28b3SPyun YongHyeon } 27700dbe28b3SPyun YongHyeon 27710dbe28b3SPyun YongHyeon enq++; 27720dbe28b3SPyun YongHyeon /* 27730dbe28b3SPyun YongHyeon * If there's a BPF listener, bounce a copy of this frame 27740dbe28b3SPyun YongHyeon * to him. 27750dbe28b3SPyun YongHyeon */ 277659a0d28bSChristian S.J. Peron ETHER_BPF_MTAP(ifp, m_head); 27770dbe28b3SPyun YongHyeon } 27780dbe28b3SPyun YongHyeon 27790dbe28b3SPyun YongHyeon if (enq > 0) { 27800dbe28b3SPyun YongHyeon /* Transmit */ 27810dbe28b3SPyun YongHyeon CSR_WRITE_2(sc_if->msk_softc, 27820dbe28b3SPyun YongHyeon Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_PUT_IDX_REG), 27830dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_prod); 27840dbe28b3SPyun YongHyeon 27850dbe28b3SPyun YongHyeon /* Set a timeout in case the chip goes out to lunch. */ 27862271eac7SPyun YongHyeon sc_if->msk_watchdog_timer = MSK_TX_TIMEOUT; 27870dbe28b3SPyun YongHyeon } 27880dbe28b3SPyun YongHyeon 27890dbe28b3SPyun YongHyeon MSK_IF_UNLOCK(sc_if); 27900dbe28b3SPyun YongHyeon } 27910dbe28b3SPyun YongHyeon 27920dbe28b3SPyun YongHyeon static void 27932271eac7SPyun YongHyeon msk_watchdog(struct msk_if_softc *sc_if) 27940dbe28b3SPyun YongHyeon { 27950dbe28b3SPyun YongHyeon struct ifnet *ifp; 27960dbe28b3SPyun YongHyeon uint32_t ridx; 27970dbe28b3SPyun YongHyeon int idx; 27980dbe28b3SPyun YongHyeon 27990dbe28b3SPyun YongHyeon MSK_IF_LOCK_ASSERT(sc_if); 28000dbe28b3SPyun YongHyeon 28012271eac7SPyun YongHyeon if (sc_if->msk_watchdog_timer == 0 || --sc_if->msk_watchdog_timer) 28022271eac7SPyun YongHyeon return; 28030dbe28b3SPyun YongHyeon ifp = sc_if->msk_ifp; 28040dbe28b3SPyun YongHyeon if (sc_if->msk_link == 0) { 28050dbe28b3SPyun YongHyeon if (bootverbose) 28060dbe28b3SPyun YongHyeon if_printf(sc_if->msk_ifp, "watchdog timeout " 28070dbe28b3SPyun YongHyeon "(missed link)\n"); 28080dbe28b3SPyun YongHyeon ifp->if_oerrors++; 28090dbe28b3SPyun YongHyeon msk_init_locked(sc_if); 28100dbe28b3SPyun YongHyeon return; 28110dbe28b3SPyun YongHyeon } 28120dbe28b3SPyun YongHyeon 28130dbe28b3SPyun YongHyeon /* 28140dbe28b3SPyun YongHyeon * Reclaim first as there is a possibility of losing Tx completion 28150dbe28b3SPyun YongHyeon * interrupts. 28160dbe28b3SPyun YongHyeon */ 28170dbe28b3SPyun YongHyeon ridx = sc_if->msk_port == MSK_PORT_A ? STAT_TXA1_RIDX : STAT_TXA2_RIDX; 28180dbe28b3SPyun YongHyeon idx = CSR_READ_2(sc_if->msk_softc, ridx); 28190dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_tx_cons != idx) { 28200dbe28b3SPyun YongHyeon msk_txeof(sc_if, idx); 28210dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_tx_cnt == 0) { 28220dbe28b3SPyun YongHyeon if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 28230dbe28b3SPyun YongHyeon "-- recovering\n"); 28240dbe28b3SPyun YongHyeon if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 28250dbe28b3SPyun YongHyeon taskqueue_enqueue(taskqueue_fast, 28260dbe28b3SPyun YongHyeon &sc_if->msk_tx_task); 28270dbe28b3SPyun YongHyeon return; 28280dbe28b3SPyun YongHyeon } 28290dbe28b3SPyun YongHyeon } 28300dbe28b3SPyun YongHyeon 28310dbe28b3SPyun YongHyeon if_printf(ifp, "watchdog timeout\n"); 28320dbe28b3SPyun YongHyeon ifp->if_oerrors++; 28330dbe28b3SPyun YongHyeon msk_init_locked(sc_if); 28340dbe28b3SPyun YongHyeon if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 28350dbe28b3SPyun YongHyeon taskqueue_enqueue(taskqueue_fast, &sc_if->msk_tx_task); 28360dbe28b3SPyun YongHyeon } 28370dbe28b3SPyun YongHyeon 28386a087a87SPyun YongHyeon static int 28390dbe28b3SPyun YongHyeon mskc_shutdown(device_t dev) 28400dbe28b3SPyun YongHyeon { 28410dbe28b3SPyun YongHyeon struct msk_softc *sc; 28420dbe28b3SPyun YongHyeon int i; 28430dbe28b3SPyun YongHyeon 28440dbe28b3SPyun YongHyeon sc = device_get_softc(dev); 28450dbe28b3SPyun YongHyeon MSK_LOCK(sc); 28460dbe28b3SPyun YongHyeon for (i = 0; i < sc->msk_num_port; i++) { 28470dbe28b3SPyun YongHyeon if (sc->msk_if[i] != NULL) 28480dbe28b3SPyun YongHyeon msk_stop(sc->msk_if[i]); 28490dbe28b3SPyun YongHyeon } 28500dbe28b3SPyun YongHyeon 28510dbe28b3SPyun YongHyeon /* Disable all interrupts. */ 28520dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, B0_IMSK, 0); 28530dbe28b3SPyun YongHyeon CSR_READ_4(sc, B0_IMSK); 28540dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 28550dbe28b3SPyun YongHyeon CSR_READ_4(sc, B0_HWE_IMSK); 28560dbe28b3SPyun YongHyeon 28570dbe28b3SPyun YongHyeon /* Put hardware reset. */ 28580dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 28590dbe28b3SPyun YongHyeon 28600dbe28b3SPyun YongHyeon MSK_UNLOCK(sc); 28616a087a87SPyun YongHyeon return (0); 28620dbe28b3SPyun YongHyeon } 28630dbe28b3SPyun YongHyeon 28640dbe28b3SPyun YongHyeon static int 28650dbe28b3SPyun YongHyeon mskc_suspend(device_t dev) 28660dbe28b3SPyun YongHyeon { 28670dbe28b3SPyun YongHyeon struct msk_softc *sc; 28680dbe28b3SPyun YongHyeon int i; 28690dbe28b3SPyun YongHyeon 28700dbe28b3SPyun YongHyeon sc = device_get_softc(dev); 28710dbe28b3SPyun YongHyeon 28720dbe28b3SPyun YongHyeon MSK_LOCK(sc); 28730dbe28b3SPyun YongHyeon 28740dbe28b3SPyun YongHyeon for (i = 0; i < sc->msk_num_port; i++) { 28750dbe28b3SPyun YongHyeon if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 28760dbe28b3SPyun YongHyeon ((sc->msk_if[i]->msk_ifp->if_drv_flags & 28770dbe28b3SPyun YongHyeon IFF_DRV_RUNNING) != 0)) 28780dbe28b3SPyun YongHyeon msk_stop(sc->msk_if[i]); 28790dbe28b3SPyun YongHyeon } 28800dbe28b3SPyun YongHyeon 28810dbe28b3SPyun YongHyeon /* Disable all interrupts. */ 28820dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, B0_IMSK, 0); 28830dbe28b3SPyun YongHyeon CSR_READ_4(sc, B0_IMSK); 28840dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, B0_HWE_IMSK, 0); 28850dbe28b3SPyun YongHyeon CSR_READ_4(sc, B0_HWE_IMSK); 28860dbe28b3SPyun YongHyeon 28870dbe28b3SPyun YongHyeon msk_phy_power(sc, MSK_PHY_POWERDOWN); 28880dbe28b3SPyun YongHyeon 28890dbe28b3SPyun YongHyeon /* Put hardware reset. */ 28900dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); 28910dbe28b3SPyun YongHyeon sc->msk_suspended = 1; 28920dbe28b3SPyun YongHyeon 28930dbe28b3SPyun YongHyeon MSK_UNLOCK(sc); 28940dbe28b3SPyun YongHyeon 28950dbe28b3SPyun YongHyeon return (0); 28960dbe28b3SPyun YongHyeon } 28970dbe28b3SPyun YongHyeon 28980dbe28b3SPyun YongHyeon static int 28990dbe28b3SPyun YongHyeon mskc_resume(device_t dev) 29000dbe28b3SPyun YongHyeon { 29010dbe28b3SPyun YongHyeon struct msk_softc *sc; 29020dbe28b3SPyun YongHyeon int i; 29030dbe28b3SPyun YongHyeon 29040dbe28b3SPyun YongHyeon sc = device_get_softc(dev); 29050dbe28b3SPyun YongHyeon 29060dbe28b3SPyun YongHyeon MSK_LOCK(sc); 29070dbe28b3SPyun YongHyeon 29080dbe28b3SPyun YongHyeon mskc_reset(sc); 29090dbe28b3SPyun YongHyeon for (i = 0; i < sc->msk_num_port; i++) { 29100dbe28b3SPyun YongHyeon if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL && 29110dbe28b3SPyun YongHyeon ((sc->msk_if[i]->msk_ifp->if_flags & IFF_UP) != 0)) 29120dbe28b3SPyun YongHyeon msk_init_locked(sc->msk_if[i]); 29130dbe28b3SPyun YongHyeon } 29140dbe28b3SPyun YongHyeon sc->msk_suspended = 0; 29150dbe28b3SPyun YongHyeon 29160dbe28b3SPyun YongHyeon MSK_UNLOCK(sc); 29170dbe28b3SPyun YongHyeon 29180dbe28b3SPyun YongHyeon return (0); 29190dbe28b3SPyun YongHyeon } 29200dbe28b3SPyun YongHyeon 29210dbe28b3SPyun YongHyeon static void 29220dbe28b3SPyun YongHyeon msk_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len) 29230dbe28b3SPyun YongHyeon { 29240dbe28b3SPyun YongHyeon struct mbuf *m; 29250dbe28b3SPyun YongHyeon struct ifnet *ifp; 29260dbe28b3SPyun YongHyeon struct msk_rxdesc *rxd; 29270dbe28b3SPyun YongHyeon int cons, rxlen; 29280dbe28b3SPyun YongHyeon 29290dbe28b3SPyun YongHyeon ifp = sc_if->msk_ifp; 29300dbe28b3SPyun YongHyeon 29310dbe28b3SPyun YongHyeon MSK_IF_LOCK_ASSERT(sc_if); 29320dbe28b3SPyun YongHyeon 29330dbe28b3SPyun YongHyeon cons = sc_if->msk_cdata.msk_rx_cons; 29340dbe28b3SPyun YongHyeon do { 29350dbe28b3SPyun YongHyeon rxlen = status >> 16; 293671e88667SPyun YongHyeon if ((status & GMR_FS_VLAN) != 0 && 293771e88667SPyun YongHyeon (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 29380dbe28b3SPyun YongHyeon rxlen -= ETHER_VLAN_ENCAP_LEN; 29390dbe28b3SPyun YongHyeon if (len > sc_if->msk_framesize || 29400dbe28b3SPyun YongHyeon ((status & GMR_FS_ANY_ERR) != 0) || 29410dbe28b3SPyun YongHyeon ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 29420dbe28b3SPyun YongHyeon /* Don't count flow-control packet as errors. */ 29430dbe28b3SPyun YongHyeon if ((status & GMR_FS_GOOD_FC) == 0) 29440dbe28b3SPyun YongHyeon ifp->if_ierrors++; 29450dbe28b3SPyun YongHyeon msk_discard_rxbuf(sc_if, cons); 29460dbe28b3SPyun YongHyeon break; 29470dbe28b3SPyun YongHyeon } 29480dbe28b3SPyun YongHyeon rxd = &sc_if->msk_cdata.msk_rxdesc[cons]; 29490dbe28b3SPyun YongHyeon m = rxd->rx_m; 29500dbe28b3SPyun YongHyeon if (msk_newbuf(sc_if, cons) != 0) { 29510dbe28b3SPyun YongHyeon ifp->if_iqdrops++; 29520dbe28b3SPyun YongHyeon /* Reuse old buffer. */ 29530dbe28b3SPyun YongHyeon msk_discard_rxbuf(sc_if, cons); 29540dbe28b3SPyun YongHyeon break; 29550dbe28b3SPyun YongHyeon } 29560dbe28b3SPyun YongHyeon m->m_pkthdr.rcvif = ifp; 29570dbe28b3SPyun YongHyeon m->m_pkthdr.len = m->m_len = len; 29580dbe28b3SPyun YongHyeon ifp->if_ipackets++; 29590dbe28b3SPyun YongHyeon /* Check for VLAN tagged packets. */ 29600dbe28b3SPyun YongHyeon if ((status & GMR_FS_VLAN) != 0 && 29610dbe28b3SPyun YongHyeon (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 29620dbe28b3SPyun YongHyeon m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 29630dbe28b3SPyun YongHyeon m->m_flags |= M_VLANTAG; 29640dbe28b3SPyun YongHyeon } 29650dbe28b3SPyun YongHyeon MSK_IF_UNLOCK(sc_if); 29660dbe28b3SPyun YongHyeon (*ifp->if_input)(ifp, m); 29670dbe28b3SPyun YongHyeon MSK_IF_LOCK(sc_if); 29680dbe28b3SPyun YongHyeon } while (0); 29690dbe28b3SPyun YongHyeon 29700dbe28b3SPyun YongHyeon MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_RX_RING_CNT); 29710dbe28b3SPyun YongHyeon MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_RX_RING_CNT); 29720dbe28b3SPyun YongHyeon } 29730dbe28b3SPyun YongHyeon 29740dbe28b3SPyun YongHyeon static void 29750dbe28b3SPyun YongHyeon msk_jumbo_rxeof(struct msk_if_softc *sc_if, uint32_t status, int len) 29760dbe28b3SPyun YongHyeon { 29770dbe28b3SPyun YongHyeon struct mbuf *m; 29780dbe28b3SPyun YongHyeon struct ifnet *ifp; 29790dbe28b3SPyun YongHyeon struct msk_rxdesc *jrxd; 29800dbe28b3SPyun YongHyeon int cons, rxlen; 29810dbe28b3SPyun YongHyeon 29820dbe28b3SPyun YongHyeon ifp = sc_if->msk_ifp; 29830dbe28b3SPyun YongHyeon 29840dbe28b3SPyun YongHyeon MSK_IF_LOCK_ASSERT(sc_if); 29850dbe28b3SPyun YongHyeon 29860dbe28b3SPyun YongHyeon cons = sc_if->msk_cdata.msk_rx_cons; 29870dbe28b3SPyun YongHyeon do { 29880dbe28b3SPyun YongHyeon rxlen = status >> 16; 298971e88667SPyun YongHyeon if ((status & GMR_FS_VLAN) != 0 && 299071e88667SPyun YongHyeon (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 29910dbe28b3SPyun YongHyeon rxlen -= ETHER_VLAN_ENCAP_LEN; 29920dbe28b3SPyun YongHyeon if (len > sc_if->msk_framesize || 29930dbe28b3SPyun YongHyeon ((status & GMR_FS_ANY_ERR) != 0) || 29940dbe28b3SPyun YongHyeon ((status & GMR_FS_RX_OK) == 0) || (rxlen != len)) { 29950dbe28b3SPyun YongHyeon /* Don't count flow-control packet as errors. */ 29960dbe28b3SPyun YongHyeon if ((status & GMR_FS_GOOD_FC) == 0) 29970dbe28b3SPyun YongHyeon ifp->if_ierrors++; 29980dbe28b3SPyun YongHyeon msk_discard_jumbo_rxbuf(sc_if, cons); 29990dbe28b3SPyun YongHyeon break; 30000dbe28b3SPyun YongHyeon } 30010dbe28b3SPyun YongHyeon jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[cons]; 30020dbe28b3SPyun YongHyeon m = jrxd->rx_m; 30030dbe28b3SPyun YongHyeon if (msk_jumbo_newbuf(sc_if, cons) != 0) { 30040dbe28b3SPyun YongHyeon ifp->if_iqdrops++; 30050dbe28b3SPyun YongHyeon /* Reuse old buffer. */ 30060dbe28b3SPyun YongHyeon msk_discard_jumbo_rxbuf(sc_if, cons); 30070dbe28b3SPyun YongHyeon break; 30080dbe28b3SPyun YongHyeon } 30090dbe28b3SPyun YongHyeon m->m_pkthdr.rcvif = ifp; 30100dbe28b3SPyun YongHyeon m->m_pkthdr.len = m->m_len = len; 30110dbe28b3SPyun YongHyeon ifp->if_ipackets++; 30120dbe28b3SPyun YongHyeon /* Check for VLAN tagged packets. */ 30130dbe28b3SPyun YongHyeon if ((status & GMR_FS_VLAN) != 0 && 30140dbe28b3SPyun YongHyeon (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) { 30150dbe28b3SPyun YongHyeon m->m_pkthdr.ether_vtag = sc_if->msk_vtag; 30160dbe28b3SPyun YongHyeon m->m_flags |= M_VLANTAG; 30170dbe28b3SPyun YongHyeon } 30180dbe28b3SPyun YongHyeon MSK_IF_UNLOCK(sc_if); 30190dbe28b3SPyun YongHyeon (*ifp->if_input)(ifp, m); 30200dbe28b3SPyun YongHyeon MSK_IF_LOCK(sc_if); 30210dbe28b3SPyun YongHyeon } while (0); 30220dbe28b3SPyun YongHyeon 30230dbe28b3SPyun YongHyeon MSK_INC(sc_if->msk_cdata.msk_rx_cons, MSK_JUMBO_RX_RING_CNT); 30240dbe28b3SPyun YongHyeon MSK_INC(sc_if->msk_cdata.msk_rx_prod, MSK_JUMBO_RX_RING_CNT); 30250dbe28b3SPyun YongHyeon } 30260dbe28b3SPyun YongHyeon 30270dbe28b3SPyun YongHyeon static void 30280dbe28b3SPyun YongHyeon msk_txeof(struct msk_if_softc *sc_if, int idx) 30290dbe28b3SPyun YongHyeon { 30300dbe28b3SPyun YongHyeon struct msk_txdesc *txd; 30310dbe28b3SPyun YongHyeon struct msk_tx_desc *cur_tx; 30320dbe28b3SPyun YongHyeon struct ifnet *ifp; 30330dbe28b3SPyun YongHyeon uint32_t control; 30340dbe28b3SPyun YongHyeon int cons, prog; 30350dbe28b3SPyun YongHyeon 30360dbe28b3SPyun YongHyeon MSK_IF_LOCK_ASSERT(sc_if); 30370dbe28b3SPyun YongHyeon 30380dbe28b3SPyun YongHyeon ifp = sc_if->msk_ifp; 30390dbe28b3SPyun YongHyeon 30400dbe28b3SPyun YongHyeon bus_dmamap_sync(sc_if->msk_cdata.msk_tx_ring_tag, 30410dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_ring_map, 30420dbe28b3SPyun YongHyeon BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 30430dbe28b3SPyun YongHyeon /* 30440dbe28b3SPyun YongHyeon * Go through our tx ring and free mbufs for those 30450dbe28b3SPyun YongHyeon * frames that have been sent. 30460dbe28b3SPyun YongHyeon */ 30470dbe28b3SPyun YongHyeon cons = sc_if->msk_cdata.msk_tx_cons; 30480dbe28b3SPyun YongHyeon prog = 0; 30490dbe28b3SPyun YongHyeon for (; cons != idx; MSK_INC(cons, MSK_TX_RING_CNT)) { 30500dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_tx_cnt <= 0) 30510dbe28b3SPyun YongHyeon break; 30520dbe28b3SPyun YongHyeon prog++; 30530dbe28b3SPyun YongHyeon cur_tx = &sc_if->msk_rdata.msk_tx_ring[cons]; 30540dbe28b3SPyun YongHyeon control = le32toh(cur_tx->msk_control); 30550dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_cnt--; 30560dbe28b3SPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 30570dbe28b3SPyun YongHyeon if ((control & EOP) == 0) 30580dbe28b3SPyun YongHyeon continue; 30590dbe28b3SPyun YongHyeon txd = &sc_if->msk_cdata.msk_txdesc[cons]; 30600dbe28b3SPyun YongHyeon bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap, 30610dbe28b3SPyun YongHyeon BUS_DMASYNC_POSTWRITE); 30620dbe28b3SPyun YongHyeon bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, txd->tx_dmamap); 30630dbe28b3SPyun YongHyeon 30640dbe28b3SPyun YongHyeon ifp->if_opackets++; 30650dbe28b3SPyun YongHyeon KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!", 30660dbe28b3SPyun YongHyeon __func__)); 30670dbe28b3SPyun YongHyeon m_freem(txd->tx_m); 30680dbe28b3SPyun YongHyeon txd->tx_m = NULL; 30690dbe28b3SPyun YongHyeon } 30700dbe28b3SPyun YongHyeon 30710dbe28b3SPyun YongHyeon if (prog > 0) { 30720dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_tx_cons = cons; 30730dbe28b3SPyun YongHyeon if (sc_if->msk_cdata.msk_tx_cnt == 0) 30742271eac7SPyun YongHyeon sc_if->msk_watchdog_timer = 0; 30750dbe28b3SPyun YongHyeon /* No need to sync LEs as we didn't update LEs. */ 30760dbe28b3SPyun YongHyeon } 30770dbe28b3SPyun YongHyeon } 30780dbe28b3SPyun YongHyeon 30790dbe28b3SPyun YongHyeon static void 30800dbe28b3SPyun YongHyeon msk_tick(void *xsc_if) 30810dbe28b3SPyun YongHyeon { 30820dbe28b3SPyun YongHyeon struct msk_if_softc *sc_if; 30830dbe28b3SPyun YongHyeon struct mii_data *mii; 30840dbe28b3SPyun YongHyeon 30850dbe28b3SPyun YongHyeon sc_if = xsc_if; 30860dbe28b3SPyun YongHyeon 30870dbe28b3SPyun YongHyeon MSK_IF_LOCK_ASSERT(sc_if); 30880dbe28b3SPyun YongHyeon 30890dbe28b3SPyun YongHyeon mii = device_get_softc(sc_if->msk_miibus); 30900dbe28b3SPyun YongHyeon 30910dbe28b3SPyun YongHyeon mii_tick(mii); 30922271eac7SPyun YongHyeon msk_watchdog(sc_if); 30930dbe28b3SPyun YongHyeon callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 30940dbe28b3SPyun YongHyeon } 30950dbe28b3SPyun YongHyeon 30960dbe28b3SPyun YongHyeon static void 30970dbe28b3SPyun YongHyeon msk_intr_phy(struct msk_if_softc *sc_if) 30980dbe28b3SPyun YongHyeon { 30990dbe28b3SPyun YongHyeon uint16_t status; 31000dbe28b3SPyun YongHyeon 31010dbe28b3SPyun YongHyeon msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 3102431e606dSPyun YongHyeon status = msk_phy_readreg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_STAT); 31030dbe28b3SPyun YongHyeon /* Handle FIFO Underrun/Overflow? */ 31040dbe28b3SPyun YongHyeon if ((status & PHY_M_IS_FIFO_ERROR)) 31050dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 31060dbe28b3SPyun YongHyeon "PHY FIFO underrun/overflow.\n"); 31070dbe28b3SPyun YongHyeon } 31080dbe28b3SPyun YongHyeon 31090dbe28b3SPyun YongHyeon static void 31100dbe28b3SPyun YongHyeon msk_intr_gmac(struct msk_if_softc *sc_if) 31110dbe28b3SPyun YongHyeon { 31120dbe28b3SPyun YongHyeon struct msk_softc *sc; 31130dbe28b3SPyun YongHyeon uint8_t status; 31140dbe28b3SPyun YongHyeon 31150dbe28b3SPyun YongHyeon sc = sc_if->msk_softc; 31160dbe28b3SPyun YongHyeon status = CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 31170dbe28b3SPyun YongHyeon 31180dbe28b3SPyun YongHyeon /* GMAC Rx FIFO overrun. */ 31190dbe28b3SPyun YongHyeon if ((status & GM_IS_RX_FF_OR) != 0) { 31200dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 31210dbe28b3SPyun YongHyeon GMF_CLI_RX_FO); 31220dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, "Rx FIFO overrun!\n"); 31230dbe28b3SPyun YongHyeon } 31240dbe28b3SPyun YongHyeon /* GMAC Tx FIFO underrun. */ 31250dbe28b3SPyun YongHyeon if ((status & GM_IS_TX_FF_UR) != 0) { 31260dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 31270dbe28b3SPyun YongHyeon GMF_CLI_TX_FU); 31280dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, "Tx FIFO underrun!\n"); 31290dbe28b3SPyun YongHyeon /* 31300dbe28b3SPyun YongHyeon * XXX 31310dbe28b3SPyun YongHyeon * In case of Tx underrun, we may need to flush/reset 31320dbe28b3SPyun YongHyeon * Tx MAC but that would also require resynchronization 31330dbe28b3SPyun YongHyeon * with status LEs. Reintializing status LEs would 31340dbe28b3SPyun YongHyeon * affect other port in dual MAC configuration so it 31350dbe28b3SPyun YongHyeon * should be avoided as possible as we can. 31360dbe28b3SPyun YongHyeon * Due to lack of documentation it's all vague guess but 31370dbe28b3SPyun YongHyeon * it needs more investigation. 31380dbe28b3SPyun YongHyeon */ 31390dbe28b3SPyun YongHyeon } 31400dbe28b3SPyun YongHyeon } 31410dbe28b3SPyun YongHyeon 31420dbe28b3SPyun YongHyeon static void 31430dbe28b3SPyun YongHyeon msk_handle_hwerr(struct msk_if_softc *sc_if, uint32_t status) 31440dbe28b3SPyun YongHyeon { 31450dbe28b3SPyun YongHyeon struct msk_softc *sc; 31460dbe28b3SPyun YongHyeon 31470dbe28b3SPyun YongHyeon sc = sc_if->msk_softc; 31480dbe28b3SPyun YongHyeon if ((status & Y2_IS_PAR_RD1) != 0) { 31490dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 31500dbe28b3SPyun YongHyeon "RAM buffer read parity error\n"); 31510dbe28b3SPyun YongHyeon /* Clear IRQ. */ 31520dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 31530dbe28b3SPyun YongHyeon RI_CLR_RD_PERR); 31540dbe28b3SPyun YongHyeon } 31550dbe28b3SPyun YongHyeon if ((status & Y2_IS_PAR_WR1) != 0) { 31560dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 31570dbe28b3SPyun YongHyeon "RAM buffer write parity error\n"); 31580dbe28b3SPyun YongHyeon /* Clear IRQ. */ 31590dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, SELECT_RAM_BUFFER(sc_if->msk_port, B3_RI_CTRL), 31600dbe28b3SPyun YongHyeon RI_CLR_WR_PERR); 31610dbe28b3SPyun YongHyeon } 31620dbe28b3SPyun YongHyeon if ((status & Y2_IS_PAR_MAC1) != 0) { 31630dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, "Tx MAC parity error\n"); 31640dbe28b3SPyun YongHyeon /* Clear IRQ. */ 31650dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 31660dbe28b3SPyun YongHyeon GMF_CLI_TX_PE); 31670dbe28b3SPyun YongHyeon } 31680dbe28b3SPyun YongHyeon if ((status & Y2_IS_PAR_RX1) != 0) { 31690dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, "Rx parity error\n"); 31700dbe28b3SPyun YongHyeon /* Clear IRQ. */ 31710dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_IRQ_PAR); 31720dbe28b3SPyun YongHyeon } 31730dbe28b3SPyun YongHyeon if ((status & (Y2_IS_TCP_TXS1 | Y2_IS_TCP_TXA1)) != 0) { 31740dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, "TCP segmentation error\n"); 31750dbe28b3SPyun YongHyeon /* Clear IRQ. */ 31760dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_IRQ_TCP); 31770dbe28b3SPyun YongHyeon } 31780dbe28b3SPyun YongHyeon } 31790dbe28b3SPyun YongHyeon 31800dbe28b3SPyun YongHyeon static void 31810dbe28b3SPyun YongHyeon msk_intr_hwerr(struct msk_softc *sc) 31820dbe28b3SPyun YongHyeon { 31830dbe28b3SPyun YongHyeon uint32_t status; 31840dbe28b3SPyun YongHyeon uint32_t tlphead[4]; 31850dbe28b3SPyun YongHyeon 31860dbe28b3SPyun YongHyeon status = CSR_READ_4(sc, B0_HWE_ISRC); 31870dbe28b3SPyun YongHyeon /* Time Stamp timer overflow. */ 31880dbe28b3SPyun YongHyeon if ((status & Y2_IS_TIST_OV) != 0) 31890dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ); 31900dbe28b3SPyun YongHyeon if ((status & Y2_IS_PCI_NEXP) != 0) { 31910dbe28b3SPyun YongHyeon /* 31920dbe28b3SPyun YongHyeon * PCI Express Error occured which is not described in PEX 31930dbe28b3SPyun YongHyeon * spec. 31940dbe28b3SPyun YongHyeon * This error is also mapped either to Master Abort( 31950dbe28b3SPyun YongHyeon * Y2_IS_MST_ERR) or Target Abort (Y2_IS_IRQ_STAT) bit and 31960dbe28b3SPyun YongHyeon * can only be cleared there. 31970dbe28b3SPyun YongHyeon */ 31980dbe28b3SPyun YongHyeon device_printf(sc->msk_dev, 31990dbe28b3SPyun YongHyeon "PCI Express protocol violation error\n"); 32000dbe28b3SPyun YongHyeon } 32010dbe28b3SPyun YongHyeon 32020dbe28b3SPyun YongHyeon if ((status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) != 0) { 32030dbe28b3SPyun YongHyeon uint16_t v16; 32040dbe28b3SPyun YongHyeon 32050dbe28b3SPyun YongHyeon if ((status & Y2_IS_MST_ERR) != 0) 32060dbe28b3SPyun YongHyeon device_printf(sc->msk_dev, 32070dbe28b3SPyun YongHyeon "unexpected IRQ Status error\n"); 32080dbe28b3SPyun YongHyeon else 32090dbe28b3SPyun YongHyeon device_printf(sc->msk_dev, 32100dbe28b3SPyun YongHyeon "unexpected IRQ Master error\n"); 32110dbe28b3SPyun YongHyeon /* Reset all bits in the PCI status register. */ 32120dbe28b3SPyun YongHyeon v16 = pci_read_config(sc->msk_dev, PCIR_STATUS, 2); 32130dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 32140dbe28b3SPyun YongHyeon pci_write_config(sc->msk_dev, PCIR_STATUS, v16 | 32150dbe28b3SPyun YongHyeon PCIM_STATUS_PERR | PCIM_STATUS_SERR | PCIM_STATUS_RMABORT | 32160dbe28b3SPyun YongHyeon PCIM_STATUS_RTABORT | PCIM_STATUS_PERRREPORT, 2); 32170dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 32180dbe28b3SPyun YongHyeon } 32190dbe28b3SPyun YongHyeon 32200dbe28b3SPyun YongHyeon /* Check for PCI Express Uncorrectable Error. */ 32210dbe28b3SPyun YongHyeon if ((status & Y2_IS_PCI_EXP) != 0) { 32220dbe28b3SPyun YongHyeon uint32_t v32; 32230dbe28b3SPyun YongHyeon 32240dbe28b3SPyun YongHyeon /* 32250dbe28b3SPyun YongHyeon * On PCI Express bus bridges are called root complexes (RC). 32260dbe28b3SPyun YongHyeon * PCI Express errors are recognized by the root complex too, 32270dbe28b3SPyun YongHyeon * which requests the system to handle the problem. After 32280dbe28b3SPyun YongHyeon * error occurence it may be that no access to the adapter 32290dbe28b3SPyun YongHyeon * may be performed any longer. 32300dbe28b3SPyun YongHyeon */ 32310dbe28b3SPyun YongHyeon 32320dbe28b3SPyun YongHyeon v32 = CSR_PCI_READ_4(sc, PEX_UNC_ERR_STAT); 32330dbe28b3SPyun YongHyeon if ((v32 & PEX_UNSUP_REQ) != 0) { 32340dbe28b3SPyun YongHyeon /* Ignore unsupported request error. */ 32350dbe28b3SPyun YongHyeon device_printf(sc->msk_dev, 32360dbe28b3SPyun YongHyeon "Uncorrectable PCI Express error\n"); 32370dbe28b3SPyun YongHyeon } 32380dbe28b3SPyun YongHyeon if ((v32 & (PEX_FATAL_ERRORS | PEX_POIS_TLP)) != 0) { 32390dbe28b3SPyun YongHyeon int i; 32400dbe28b3SPyun YongHyeon 32410dbe28b3SPyun YongHyeon /* Get TLP header form Log Registers. */ 32420dbe28b3SPyun YongHyeon for (i = 0; i < 4; i++) 32430dbe28b3SPyun YongHyeon tlphead[i] = CSR_PCI_READ_4(sc, 32440dbe28b3SPyun YongHyeon PEX_HEADER_LOG + i * 4); 32450dbe28b3SPyun YongHyeon /* Check for vendor defined broadcast message. */ 32460dbe28b3SPyun YongHyeon if (!(tlphead[0] == 0x73004001 && tlphead[1] == 0x7f)) { 32470dbe28b3SPyun YongHyeon sc->msk_intrhwemask &= ~Y2_IS_PCI_EXP; 32480dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, B0_HWE_IMSK, 32490dbe28b3SPyun YongHyeon sc->msk_intrhwemask); 32500dbe28b3SPyun YongHyeon CSR_READ_4(sc, B0_HWE_IMSK); 32510dbe28b3SPyun YongHyeon } 32520dbe28b3SPyun YongHyeon } 32530dbe28b3SPyun YongHyeon /* Clear the interrupt. */ 32540dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_ON); 32550dbe28b3SPyun YongHyeon CSR_PCI_WRITE_4(sc, PEX_UNC_ERR_STAT, 0xffffffff); 32560dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, B2_TST_CTRL1, TST_CFG_WRITE_OFF); 32570dbe28b3SPyun YongHyeon } 32580dbe28b3SPyun YongHyeon 32590dbe28b3SPyun YongHyeon if ((status & Y2_HWE_L1_MASK) != 0 && sc->msk_if[MSK_PORT_A] != NULL) 32600dbe28b3SPyun YongHyeon msk_handle_hwerr(sc->msk_if[MSK_PORT_A], status); 32610dbe28b3SPyun YongHyeon if ((status & Y2_HWE_L2_MASK) != 0 && sc->msk_if[MSK_PORT_B] != NULL) 32620dbe28b3SPyun YongHyeon msk_handle_hwerr(sc->msk_if[MSK_PORT_B], status >> 8); 32630dbe28b3SPyun YongHyeon } 32640dbe28b3SPyun YongHyeon 32650dbe28b3SPyun YongHyeon static __inline void 32660dbe28b3SPyun YongHyeon msk_rxput(struct msk_if_softc *sc_if) 32670dbe28b3SPyun YongHyeon { 32680dbe28b3SPyun YongHyeon struct msk_softc *sc; 32690dbe28b3SPyun YongHyeon 32700dbe28b3SPyun YongHyeon sc = sc_if->msk_softc; 32710dbe28b3SPyun YongHyeon if (sc_if->msk_framesize >(MCLBYTES - ETHER_HDR_LEN)) 32720dbe28b3SPyun YongHyeon bus_dmamap_sync( 32730dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_jumbo_rx_ring_tag, 32740dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_jumbo_rx_ring_map, 32750dbe28b3SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 32760dbe28b3SPyun YongHyeon else 32770dbe28b3SPyun YongHyeon bus_dmamap_sync( 32780dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_ring_tag, 32790dbe28b3SPyun YongHyeon sc_if->msk_cdata.msk_rx_ring_map, 32800dbe28b3SPyun YongHyeon BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 32810dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, 32820dbe28b3SPyun YongHyeon PREF_UNIT_PUT_IDX_REG), sc_if->msk_cdata.msk_rx_prod); 32830dbe28b3SPyun YongHyeon } 32840dbe28b3SPyun YongHyeon 32850dbe28b3SPyun YongHyeon static int 32860dbe28b3SPyun YongHyeon msk_handle_events(struct msk_softc *sc) 32870dbe28b3SPyun YongHyeon { 32880dbe28b3SPyun YongHyeon struct msk_if_softc *sc_if; 32890dbe28b3SPyun YongHyeon int rxput[2]; 32900dbe28b3SPyun YongHyeon struct msk_stat_desc *sd; 32910dbe28b3SPyun YongHyeon uint32_t control, status; 32920dbe28b3SPyun YongHyeon int cons, idx, len, port, rxprog; 32930dbe28b3SPyun YongHyeon 32940dbe28b3SPyun YongHyeon idx = CSR_READ_2(sc, STAT_PUT_IDX); 32950dbe28b3SPyun YongHyeon if (idx == sc->msk_stat_cons) 32960dbe28b3SPyun YongHyeon return (0); 32970dbe28b3SPyun YongHyeon 32980dbe28b3SPyun YongHyeon /* Sync status LEs. */ 32990dbe28b3SPyun YongHyeon bus_dmamap_sync(sc->msk_stat_tag, sc->msk_stat_map, 33000dbe28b3SPyun YongHyeon BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 33010dbe28b3SPyun YongHyeon /* XXX Sync Rx LEs here. */ 33020dbe28b3SPyun YongHyeon 33030dbe28b3SPyun YongHyeon rxput[MSK_PORT_A] = rxput[MSK_PORT_B] = 0; 33040dbe28b3SPyun YongHyeon 33050dbe28b3SPyun YongHyeon rxprog = 0; 33060dbe28b3SPyun YongHyeon for (cons = sc->msk_stat_cons; cons != idx;) { 33070dbe28b3SPyun YongHyeon sd = &sc->msk_stat_ring[cons]; 33080dbe28b3SPyun YongHyeon control = le32toh(sd->msk_control); 33090dbe28b3SPyun YongHyeon if ((control & HW_OWNER) == 0) 33100dbe28b3SPyun YongHyeon break; 33110dbe28b3SPyun YongHyeon /* 33120dbe28b3SPyun YongHyeon * Marvell's FreeBSD driver updates status LE after clearing 33130dbe28b3SPyun YongHyeon * HW_OWNER. However we don't have a way to sync single LE 33140dbe28b3SPyun YongHyeon * with bus_dma(9) API. bus_dma(9) provides a way to sync 33150dbe28b3SPyun YongHyeon * an entire DMA map. So don't sync LE until we have a better 33160dbe28b3SPyun YongHyeon * way to sync LEs. 33170dbe28b3SPyun YongHyeon */ 33180dbe28b3SPyun YongHyeon control &= ~HW_OWNER; 33190dbe28b3SPyun YongHyeon sd->msk_control = htole32(control); 33200dbe28b3SPyun YongHyeon status = le32toh(sd->msk_status); 33210dbe28b3SPyun YongHyeon len = control & STLE_LEN_MASK; 33220dbe28b3SPyun YongHyeon port = (control >> 16) & 0x01; 33230dbe28b3SPyun YongHyeon sc_if = sc->msk_if[port]; 33240dbe28b3SPyun YongHyeon if (sc_if == NULL) { 33250dbe28b3SPyun YongHyeon device_printf(sc->msk_dev, "invalid port opcode " 33260dbe28b3SPyun YongHyeon "0x%08x\n", control & STLE_OP_MASK); 33270dbe28b3SPyun YongHyeon continue; 33280dbe28b3SPyun YongHyeon } 33290dbe28b3SPyun YongHyeon 33300dbe28b3SPyun YongHyeon switch (control & STLE_OP_MASK) { 33310dbe28b3SPyun YongHyeon case OP_RXVLAN: 33320dbe28b3SPyun YongHyeon sc_if->msk_vtag = ntohs(len); 33330dbe28b3SPyun YongHyeon break; 33340dbe28b3SPyun YongHyeon case OP_RXCHKSVLAN: 33350dbe28b3SPyun YongHyeon sc_if->msk_vtag = ntohs(len); 33360dbe28b3SPyun YongHyeon break; 33370dbe28b3SPyun YongHyeon case OP_RXSTAT: 33380dbe28b3SPyun YongHyeon if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) 33390dbe28b3SPyun YongHyeon msk_jumbo_rxeof(sc_if, status, len); 33400dbe28b3SPyun YongHyeon else 33410dbe28b3SPyun YongHyeon msk_rxeof(sc_if, status, len); 33420dbe28b3SPyun YongHyeon rxprog++; 33430dbe28b3SPyun YongHyeon /* 33440dbe28b3SPyun YongHyeon * Because there is no way to sync single Rx LE 33450dbe28b3SPyun YongHyeon * put the DMA sync operation off until the end of 33460dbe28b3SPyun YongHyeon * event processing. 33470dbe28b3SPyun YongHyeon */ 33480dbe28b3SPyun YongHyeon rxput[port]++; 33490dbe28b3SPyun YongHyeon /* Update prefetch unit if we've passed water mark. */ 33500dbe28b3SPyun YongHyeon if (rxput[port] >= sc_if->msk_cdata.msk_rx_putwm) { 33510dbe28b3SPyun YongHyeon msk_rxput(sc_if); 33520dbe28b3SPyun YongHyeon rxput[port] = 0; 33530dbe28b3SPyun YongHyeon } 33540dbe28b3SPyun YongHyeon break; 33550dbe28b3SPyun YongHyeon case OP_TXINDEXLE: 33560dbe28b3SPyun YongHyeon if (sc->msk_if[MSK_PORT_A] != NULL) 33570dbe28b3SPyun YongHyeon msk_txeof(sc->msk_if[MSK_PORT_A], 33580dbe28b3SPyun YongHyeon status & STLE_TXA1_MSKL); 33590dbe28b3SPyun YongHyeon if (sc->msk_if[MSK_PORT_B] != NULL) 33600dbe28b3SPyun YongHyeon msk_txeof(sc->msk_if[MSK_PORT_B], 33610dbe28b3SPyun YongHyeon ((status & STLE_TXA2_MSKL) >> 33620dbe28b3SPyun YongHyeon STLE_TXA2_SHIFTL) | 33630dbe28b3SPyun YongHyeon ((len & STLE_TXA2_MSKH) << 33640dbe28b3SPyun YongHyeon STLE_TXA2_SHIFTH)); 33650dbe28b3SPyun YongHyeon break; 33660dbe28b3SPyun YongHyeon default: 33670dbe28b3SPyun YongHyeon device_printf(sc->msk_dev, "unhandled opcode 0x%08x\n", 33680dbe28b3SPyun YongHyeon control & STLE_OP_MASK); 33690dbe28b3SPyun YongHyeon break; 33700dbe28b3SPyun YongHyeon } 33710dbe28b3SPyun YongHyeon MSK_INC(cons, MSK_STAT_RING_CNT); 33720dbe28b3SPyun YongHyeon if (rxprog > sc->msk_process_limit) 33730dbe28b3SPyun YongHyeon break; 33740dbe28b3SPyun YongHyeon } 33750dbe28b3SPyun YongHyeon 33760dbe28b3SPyun YongHyeon sc->msk_stat_cons = cons; 33770dbe28b3SPyun YongHyeon /* XXX We should sync status LEs here. See above notes. */ 33780dbe28b3SPyun YongHyeon 33790dbe28b3SPyun YongHyeon if (rxput[MSK_PORT_A] > 0) 33800dbe28b3SPyun YongHyeon msk_rxput(sc->msk_if[MSK_PORT_A]); 33810dbe28b3SPyun YongHyeon if (rxput[MSK_PORT_B] > 0) 33820dbe28b3SPyun YongHyeon msk_rxput(sc->msk_if[MSK_PORT_B]); 33830dbe28b3SPyun YongHyeon 33840dbe28b3SPyun YongHyeon return (sc->msk_stat_cons != CSR_READ_2(sc, STAT_PUT_IDX)); 33850dbe28b3SPyun YongHyeon } 33860dbe28b3SPyun YongHyeon 338753dcfbd1SPyun YongHyeon /* Legacy interrupt handler for shared interrupt. */ 338853dcfbd1SPyun YongHyeon static void 338953dcfbd1SPyun YongHyeon msk_legacy_intr(void *xsc) 339053dcfbd1SPyun YongHyeon { 339153dcfbd1SPyun YongHyeon struct msk_softc *sc; 339253dcfbd1SPyun YongHyeon struct msk_if_softc *sc_if0, *sc_if1; 339353dcfbd1SPyun YongHyeon struct ifnet *ifp0, *ifp1; 339453dcfbd1SPyun YongHyeon uint32_t status; 339553dcfbd1SPyun YongHyeon 339653dcfbd1SPyun YongHyeon sc = xsc; 339753dcfbd1SPyun YongHyeon MSK_LOCK(sc); 339853dcfbd1SPyun YongHyeon 339953dcfbd1SPyun YongHyeon /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 340053dcfbd1SPyun YongHyeon status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 340153dcfbd1SPyun YongHyeon if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 || 340253dcfbd1SPyun YongHyeon (status & sc->msk_intrmask) == 0) { 340353dcfbd1SPyun YongHyeon CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 340453dcfbd1SPyun YongHyeon return; 340553dcfbd1SPyun YongHyeon } 340653dcfbd1SPyun YongHyeon 340753dcfbd1SPyun YongHyeon sc_if0 = sc->msk_if[MSK_PORT_A]; 340853dcfbd1SPyun YongHyeon sc_if1 = sc->msk_if[MSK_PORT_B]; 340953dcfbd1SPyun YongHyeon ifp0 = ifp1 = NULL; 341053dcfbd1SPyun YongHyeon if (sc_if0 != NULL) 341153dcfbd1SPyun YongHyeon ifp0 = sc_if0->msk_ifp; 341253dcfbd1SPyun YongHyeon if (sc_if1 != NULL) 341353dcfbd1SPyun YongHyeon ifp1 = sc_if1->msk_ifp; 341453dcfbd1SPyun YongHyeon 341553dcfbd1SPyun YongHyeon if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 341653dcfbd1SPyun YongHyeon msk_intr_phy(sc_if0); 341753dcfbd1SPyun YongHyeon if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 341853dcfbd1SPyun YongHyeon msk_intr_phy(sc_if1); 341953dcfbd1SPyun YongHyeon if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 342053dcfbd1SPyun YongHyeon msk_intr_gmac(sc_if0); 342153dcfbd1SPyun YongHyeon if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 342253dcfbd1SPyun YongHyeon msk_intr_gmac(sc_if1); 342353dcfbd1SPyun YongHyeon if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 342453dcfbd1SPyun YongHyeon device_printf(sc->msk_dev, "Rx descriptor error\n"); 342553dcfbd1SPyun YongHyeon sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 342653dcfbd1SPyun YongHyeon CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 342753dcfbd1SPyun YongHyeon CSR_READ_4(sc, B0_IMSK); 342853dcfbd1SPyun YongHyeon } 342953dcfbd1SPyun YongHyeon if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 343053dcfbd1SPyun YongHyeon device_printf(sc->msk_dev, "Tx descriptor error\n"); 343153dcfbd1SPyun YongHyeon sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 343253dcfbd1SPyun YongHyeon CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 343353dcfbd1SPyun YongHyeon CSR_READ_4(sc, B0_IMSK); 343453dcfbd1SPyun YongHyeon } 343553dcfbd1SPyun YongHyeon if ((status & Y2_IS_HW_ERR) != 0) 343653dcfbd1SPyun YongHyeon msk_intr_hwerr(sc); 343753dcfbd1SPyun YongHyeon 343853dcfbd1SPyun YongHyeon while (msk_handle_events(sc) != 0) 343953dcfbd1SPyun YongHyeon ; 344053dcfbd1SPyun YongHyeon if ((status & Y2_IS_STAT_BMU) != 0) 344153dcfbd1SPyun YongHyeon CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 344253dcfbd1SPyun YongHyeon 344353dcfbd1SPyun YongHyeon /* Reenable interrupts. */ 344453dcfbd1SPyun YongHyeon CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 344553dcfbd1SPyun YongHyeon 344653dcfbd1SPyun YongHyeon if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 344753dcfbd1SPyun YongHyeon !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 344853dcfbd1SPyun YongHyeon taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task); 344953dcfbd1SPyun YongHyeon if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 345053dcfbd1SPyun YongHyeon !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 345153dcfbd1SPyun YongHyeon taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task); 345253dcfbd1SPyun YongHyeon 345353dcfbd1SPyun YongHyeon MSK_UNLOCK(sc); 345453dcfbd1SPyun YongHyeon } 345553dcfbd1SPyun YongHyeon 3456ef544f63SPaolo Pisati static int 34570dbe28b3SPyun YongHyeon msk_intr(void *xsc) 34580dbe28b3SPyun YongHyeon { 34590dbe28b3SPyun YongHyeon struct msk_softc *sc; 34600dbe28b3SPyun YongHyeon uint32_t status; 34610dbe28b3SPyun YongHyeon 34620dbe28b3SPyun YongHyeon sc = xsc; 34630dbe28b3SPyun YongHyeon status = CSR_READ_4(sc, B0_Y2_SP_ISRC2); 34640dbe28b3SPyun YongHyeon /* Reading B0_Y2_SP_ISRC2 masks further interrupts. */ 34650dbe28b3SPyun YongHyeon if (status == 0 || status == 0xffffffff) { 34660dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 3467ef544f63SPaolo Pisati return (FILTER_STRAY); 34680dbe28b3SPyun YongHyeon } 34690dbe28b3SPyun YongHyeon 34700dbe28b3SPyun YongHyeon taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task); 3471ef544f63SPaolo Pisati return (FILTER_HANDLED); 34720dbe28b3SPyun YongHyeon } 34730dbe28b3SPyun YongHyeon 34740dbe28b3SPyun YongHyeon static void 34750dbe28b3SPyun YongHyeon msk_int_task(void *arg, int pending) 34760dbe28b3SPyun YongHyeon { 34770dbe28b3SPyun YongHyeon struct msk_softc *sc; 34780dbe28b3SPyun YongHyeon struct msk_if_softc *sc_if0, *sc_if1; 34790dbe28b3SPyun YongHyeon struct ifnet *ifp0, *ifp1; 34800dbe28b3SPyun YongHyeon uint32_t status; 34810dbe28b3SPyun YongHyeon int domore; 34820dbe28b3SPyun YongHyeon 34830dbe28b3SPyun YongHyeon sc = arg; 34840dbe28b3SPyun YongHyeon MSK_LOCK(sc); 34850dbe28b3SPyun YongHyeon 34860dbe28b3SPyun YongHyeon /* Get interrupt source. */ 34870dbe28b3SPyun YongHyeon status = CSR_READ_4(sc, B0_ISRC); 34880dbe28b3SPyun YongHyeon if (status == 0 || status == 0xffffffff || sc->msk_suspended != 0 || 34890dbe28b3SPyun YongHyeon (status & sc->msk_intrmask) == 0) 34900dbe28b3SPyun YongHyeon goto done; 34910dbe28b3SPyun YongHyeon 34920dbe28b3SPyun YongHyeon sc_if0 = sc->msk_if[MSK_PORT_A]; 34930dbe28b3SPyun YongHyeon sc_if1 = sc->msk_if[MSK_PORT_B]; 34940dbe28b3SPyun YongHyeon ifp0 = ifp1 = NULL; 3495b55031fdSPyun YongHyeon if (sc_if0 != NULL) 34960dbe28b3SPyun YongHyeon ifp0 = sc_if0->msk_ifp; 3497b55031fdSPyun YongHyeon if (sc_if1 != NULL) 34980dbe28b3SPyun YongHyeon ifp1 = sc_if1->msk_ifp; 34990dbe28b3SPyun YongHyeon 35000dbe28b3SPyun YongHyeon if ((status & Y2_IS_IRQ_PHY1) != 0 && sc_if0 != NULL) 35010dbe28b3SPyun YongHyeon msk_intr_phy(sc_if0); 35020dbe28b3SPyun YongHyeon if ((status & Y2_IS_IRQ_PHY2) != 0 && sc_if1 != NULL) 35030dbe28b3SPyun YongHyeon msk_intr_phy(sc_if1); 35040dbe28b3SPyun YongHyeon if ((status & Y2_IS_IRQ_MAC1) != 0 && sc_if0 != NULL) 35050dbe28b3SPyun YongHyeon msk_intr_gmac(sc_if0); 35060dbe28b3SPyun YongHyeon if ((status & Y2_IS_IRQ_MAC2) != 0 && sc_if1 != NULL) 35070dbe28b3SPyun YongHyeon msk_intr_gmac(sc_if1); 35080dbe28b3SPyun YongHyeon if ((status & (Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2)) != 0) { 35090dbe28b3SPyun YongHyeon device_printf(sc->msk_dev, "Rx descriptor error\n"); 35100dbe28b3SPyun YongHyeon sc->msk_intrmask &= ~(Y2_IS_CHK_RX1 | Y2_IS_CHK_RX2); 35110dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 35120dbe28b3SPyun YongHyeon CSR_READ_4(sc, B0_IMSK); 35130dbe28b3SPyun YongHyeon } 35140dbe28b3SPyun YongHyeon if ((status & (Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2)) != 0) { 35150dbe28b3SPyun YongHyeon device_printf(sc->msk_dev, "Tx descriptor error\n"); 35160dbe28b3SPyun YongHyeon sc->msk_intrmask &= ~(Y2_IS_CHK_TXA1 | Y2_IS_CHK_TXA2); 35170dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 35180dbe28b3SPyun YongHyeon CSR_READ_4(sc, B0_IMSK); 35190dbe28b3SPyun YongHyeon } 35200dbe28b3SPyun YongHyeon if ((status & Y2_IS_HW_ERR) != 0) 35210dbe28b3SPyun YongHyeon msk_intr_hwerr(sc); 35220dbe28b3SPyun YongHyeon 35230dbe28b3SPyun YongHyeon domore = msk_handle_events(sc); 35240dbe28b3SPyun YongHyeon if ((status & Y2_IS_STAT_BMU) != 0) 35250dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, STAT_CTRL, SC_STAT_CLR_IRQ); 35260dbe28b3SPyun YongHyeon 3527b55031fdSPyun YongHyeon if (ifp0 != NULL && (ifp0->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3528b55031fdSPyun YongHyeon !IFQ_DRV_IS_EMPTY(&ifp0->if_snd)) 35290dbe28b3SPyun YongHyeon taskqueue_enqueue(taskqueue_fast, &sc_if0->msk_tx_task); 3530b55031fdSPyun YongHyeon if (ifp1 != NULL && (ifp1->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3531b55031fdSPyun YongHyeon !IFQ_DRV_IS_EMPTY(&ifp1->if_snd)) 35320dbe28b3SPyun YongHyeon taskqueue_enqueue(taskqueue_fast, &sc_if1->msk_tx_task); 35330dbe28b3SPyun YongHyeon 35340dbe28b3SPyun YongHyeon if (domore > 0) { 35350dbe28b3SPyun YongHyeon taskqueue_enqueue(sc->msk_tq, &sc->msk_int_task); 35360dbe28b3SPyun YongHyeon MSK_UNLOCK(sc); 35370dbe28b3SPyun YongHyeon return; 35380dbe28b3SPyun YongHyeon } 35390dbe28b3SPyun YongHyeon done: 35400dbe28b3SPyun YongHyeon MSK_UNLOCK(sc); 35410dbe28b3SPyun YongHyeon 35420dbe28b3SPyun YongHyeon /* Reenable interrupts. */ 35430dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, B0_Y2_SP_ICR, 2); 35440dbe28b3SPyun YongHyeon } 35450dbe28b3SPyun YongHyeon 35460dbe28b3SPyun YongHyeon static void 35470dbe28b3SPyun YongHyeon msk_init(void *xsc) 35480dbe28b3SPyun YongHyeon { 35490dbe28b3SPyun YongHyeon struct msk_if_softc *sc_if = xsc; 35500dbe28b3SPyun YongHyeon 35510dbe28b3SPyun YongHyeon MSK_IF_LOCK(sc_if); 35520dbe28b3SPyun YongHyeon msk_init_locked(sc_if); 35530dbe28b3SPyun YongHyeon MSK_IF_UNLOCK(sc_if); 35540dbe28b3SPyun YongHyeon } 35550dbe28b3SPyun YongHyeon 35560dbe28b3SPyun YongHyeon static void 35570dbe28b3SPyun YongHyeon msk_init_locked(struct msk_if_softc *sc_if) 35580dbe28b3SPyun YongHyeon { 35590dbe28b3SPyun YongHyeon struct msk_softc *sc; 35600dbe28b3SPyun YongHyeon struct ifnet *ifp; 35610dbe28b3SPyun YongHyeon struct mii_data *mii; 35620dbe28b3SPyun YongHyeon uint16_t eaddr[ETHER_ADDR_LEN / 2]; 35630dbe28b3SPyun YongHyeon uint16_t gmac; 35640dbe28b3SPyun YongHyeon int error, i; 35650dbe28b3SPyun YongHyeon 35660dbe28b3SPyun YongHyeon MSK_IF_LOCK_ASSERT(sc_if); 35670dbe28b3SPyun YongHyeon 35680dbe28b3SPyun YongHyeon ifp = sc_if->msk_ifp; 35690dbe28b3SPyun YongHyeon sc = sc_if->msk_softc; 35700dbe28b3SPyun YongHyeon mii = device_get_softc(sc_if->msk_miibus); 35710dbe28b3SPyun YongHyeon 35720dbe28b3SPyun YongHyeon error = 0; 35730dbe28b3SPyun YongHyeon /* Cancel pending I/O and free all Rx/Tx buffers. */ 35740dbe28b3SPyun YongHyeon msk_stop(sc_if); 35750dbe28b3SPyun YongHyeon 35760dbe28b3SPyun YongHyeon sc_if->msk_framesize = ifp->if_mtu + ETHER_HDR_LEN + 35770dbe28b3SPyun YongHyeon ETHER_VLAN_ENCAP_LEN; 3578a109c74fSPyun YongHyeon if (sc_if->msk_framesize > MSK_MAX_FRAMELEN && 3579a109c74fSPyun YongHyeon sc_if->msk_softc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 3580a109c74fSPyun YongHyeon /* 3581a109c74fSPyun YongHyeon * In Yukon EC Ultra, TSO & checksum offload is not 3582a109c74fSPyun YongHyeon * supported for jumbo frame. 3583a109c74fSPyun YongHyeon */ 3584a109c74fSPyun YongHyeon ifp->if_hwassist &= ~(MSK_CSUM_FEATURES | CSUM_TSO); 3585a109c74fSPyun YongHyeon ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TXCSUM); 3586a109c74fSPyun YongHyeon } 35870dbe28b3SPyun YongHyeon 35880dbe28b3SPyun YongHyeon /* 35890dbe28b3SPyun YongHyeon * Initialize GMAC first. 35900dbe28b3SPyun YongHyeon * Without this initialization, Rx MAC did not work as expected 35910dbe28b3SPyun YongHyeon * and Rx MAC garbled status LEs and it resulted in out-of-order 35920dbe28b3SPyun YongHyeon * or duplicated frame delivery which in turn showed very poor 35930dbe28b3SPyun YongHyeon * Rx performance.(I had to write a packet analysis code that 35940dbe28b3SPyun YongHyeon * could be embeded in driver to diagnose this issue.) 35950dbe28b3SPyun YongHyeon * I've spent almost 2 months to fix this issue. If I have had 35960dbe28b3SPyun YongHyeon * datasheet for Yukon II I wouldn't have encountered this. :-( 35970dbe28b3SPyun YongHyeon */ 35980dbe28b3SPyun YongHyeon gmac = GM_GPCR_SPEED_100 | GM_GPCR_SPEED_1000 | GM_GPCR_DUP_FULL; 35990dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, gmac); 36000dbe28b3SPyun YongHyeon 36010dbe28b3SPyun YongHyeon /* Dummy read the Interrupt Source Register. */ 36020dbe28b3SPyun YongHyeon CSR_READ_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_SRC)); 36030dbe28b3SPyun YongHyeon 36040dbe28b3SPyun YongHyeon /* Set MIB Clear Counter Mode. */ 36050dbe28b3SPyun YongHyeon gmac = GMAC_READ_2(sc, sc_if->msk_port, GM_PHY_ADDR); 36060dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac | GM_PAR_MIB_CLR); 36070dbe28b3SPyun YongHyeon /* Read all MIB Counters with Clear Mode set. */ 36080dbe28b3SPyun YongHyeon for (i = 0; i < GM_MIB_CNT_SIZE; i++) 36090dbe28b3SPyun YongHyeon GMAC_READ_2(sc, sc_if->msk_port, GM_MIB_CNT_BASE + 8 * i); 36100dbe28b3SPyun YongHyeon /* Clear MIB Clear Counter Mode. */ 36110dbe28b3SPyun YongHyeon gmac &= ~GM_PAR_MIB_CLR; 36120dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_PHY_ADDR, gmac); 36130dbe28b3SPyun YongHyeon 36140dbe28b3SPyun YongHyeon /* Disable FCS. */ 36150dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_CTRL, GM_RXCR_CRC_DIS); 36160dbe28b3SPyun YongHyeon 36170dbe28b3SPyun YongHyeon /* Setup Transmit Control Register. */ 36180dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF)); 36190dbe28b3SPyun YongHyeon 36200dbe28b3SPyun YongHyeon /* Setup Transmit Flow Control Register. */ 36210dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_FLOW_CTRL, 0xffff); 36220dbe28b3SPyun YongHyeon 36230dbe28b3SPyun YongHyeon /* Setup Transmit Parameter Register. */ 36240dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_PARAM, 36250dbe28b3SPyun YongHyeon TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) | TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) | 36260dbe28b3SPyun YongHyeon TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) | TX_BACK_OFF_LIM(TX_BOF_LIM_DEF)); 36270dbe28b3SPyun YongHyeon 36280dbe28b3SPyun YongHyeon gmac = DATA_BLIND_VAL(DATA_BLIND_DEF) | 36290dbe28b3SPyun YongHyeon GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF); 36300dbe28b3SPyun YongHyeon 36310dbe28b3SPyun YongHyeon if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) 36320dbe28b3SPyun YongHyeon gmac |= GM_SMOD_JUMBO_ENA; 36330dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_SERIAL_MODE, gmac); 36340dbe28b3SPyun YongHyeon 36350dbe28b3SPyun YongHyeon /* Set station address. */ 36360dbe28b3SPyun YongHyeon bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 36370dbe28b3SPyun YongHyeon for (i = 0; i < ETHER_ADDR_LEN /2; i++) 36380dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_1L + i * 4, 36390dbe28b3SPyun YongHyeon eaddr[i]); 36400dbe28b3SPyun YongHyeon for (i = 0; i < ETHER_ADDR_LEN /2; i++) 36410dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_SRC_ADDR_2L + i * 4, 36420dbe28b3SPyun YongHyeon eaddr[i]); 36430dbe28b3SPyun YongHyeon 36440dbe28b3SPyun YongHyeon /* Disable interrupts for counter overflows. */ 36450dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_TX_IRQ_MSK, 0); 36460dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_RX_IRQ_MSK, 0); 36470dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_TR_IRQ_MSK, 0); 36480dbe28b3SPyun YongHyeon 36490dbe28b3SPyun YongHyeon /* Configure Rx MAC FIFO. */ 36500dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 36510dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_CLR); 36520dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), 36530dbe28b3SPyun YongHyeon GMF_OPER_ON | GMF_RX_F_FL_ON); 36540dbe28b3SPyun YongHyeon 36550dbe28b3SPyun YongHyeon /* Set promiscuous mode. */ 36560dbe28b3SPyun YongHyeon msk_setpromisc(sc_if); 36570dbe28b3SPyun YongHyeon 36580dbe28b3SPyun YongHyeon /* Set multicast filter. */ 36590dbe28b3SPyun YongHyeon msk_setmulti(sc_if); 36600dbe28b3SPyun YongHyeon 36610dbe28b3SPyun YongHyeon /* Flush Rx MAC FIFO on any flow control or error. */ 36620dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_MSK), 36630dbe28b3SPyun YongHyeon GMR_FS_ANY_ERR); 36640dbe28b3SPyun YongHyeon 3665d5d60164SPyun YongHyeon /* 3666d5d60164SPyun YongHyeon * Set Rx FIFO flush threshold to 64 bytes + 1 FIFO word 3667d5d60164SPyun YongHyeon * due to hardware hang on receipt of pause frames. 3668d5d60164SPyun YongHyeon */ 36690dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_FL_THR), 3670d5d60164SPyun YongHyeon RX_GMF_FL_THR_DEF + 1); 36710dbe28b3SPyun YongHyeon 36720dbe28b3SPyun YongHyeon /* Configure Tx MAC FIFO. */ 36730dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 36740dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_CLR); 36750dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_OPER_ON); 36760dbe28b3SPyun YongHyeon 36770dbe28b3SPyun YongHyeon /* Configure hardware VLAN tag insertion/stripping. */ 36780dbe28b3SPyun YongHyeon msk_setvlan(sc_if, ifp); 36790dbe28b3SPyun YongHyeon 36800dbe28b3SPyun YongHyeon if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U) { 36810dbe28b3SPyun YongHyeon /* Set Rx Pause threshould. */ 36820dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_LP_THR), 36830dbe28b3SPyun YongHyeon MSK_ECU_LLPP); 36840dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, RX_GMF_UP_THR), 36850dbe28b3SPyun YongHyeon MSK_ECU_ULPP); 36860dbe28b3SPyun YongHyeon if (sc_if->msk_framesize > MSK_MAX_FRAMELEN) { 36870dbe28b3SPyun YongHyeon /* 36880dbe28b3SPyun YongHyeon * Set Tx GMAC FIFO Almost Empty Threshold. 36890dbe28b3SPyun YongHyeon */ 36900dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_AE_THR), 3691a109c74fSPyun YongHyeon MSK_ECU_JUMBO_WM << 16 | MSK_ECU_AE_THR); 36920dbe28b3SPyun YongHyeon /* Disable Store & Forward mode for Tx. */ 36930dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3694a109c74fSPyun YongHyeon TX_JUMBO_ENA | TX_STFW_DIS); 3695a109c74fSPyun YongHyeon } else { 3696a109c74fSPyun YongHyeon /* Enable Store & Forward mode for Tx. */ 3697a109c74fSPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), 3698a109c74fSPyun YongHyeon TX_JUMBO_DIS | TX_STFW_ENA); 36990dbe28b3SPyun YongHyeon } 37000dbe28b3SPyun YongHyeon } 37010dbe28b3SPyun YongHyeon 37020dbe28b3SPyun YongHyeon /* 37030dbe28b3SPyun YongHyeon * Disable Force Sync bit and Alloc bit in Tx RAM interface 37040dbe28b3SPyun YongHyeon * arbiter as we don't use Sync Tx queue. 37050dbe28b3SPyun YongHyeon */ 37060dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), 37070dbe28b3SPyun YongHyeon TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC); 37080dbe28b3SPyun YongHyeon /* Enable the RAM Interface Arbiter. */ 37090dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_ENA_ARB); 37100dbe28b3SPyun YongHyeon 37110dbe28b3SPyun YongHyeon /* Setup RAM buffer. */ 37120dbe28b3SPyun YongHyeon msk_set_rambuffer(sc_if); 37130dbe28b3SPyun YongHyeon 37140dbe28b3SPyun YongHyeon /* Disable Tx sync Queue. */ 37150dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txsq, RB_CTRL), RB_RST_SET); 37160dbe28b3SPyun YongHyeon 37170dbe28b3SPyun YongHyeon /* Setup Tx Queue Bus Memory Interface. */ 37180dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_CLR_RESET); 37190dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_OPER_INIT); 37200dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_FIFO_OP_ON); 37210dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_WM), MSK_BMU_TX_WM); 37220dbe28b3SPyun YongHyeon if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 37230dbe28b3SPyun YongHyeon sc->msk_hw_rev == CHIP_REV_YU_EC_U_A0) { 37240dbe28b3SPyun YongHyeon /* Fix for Yukon-EC Ultra: set BMU FIFO level */ 37250dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_txq, Q_AL), MSK_ECU_TXFF_LEV); 37260dbe28b3SPyun YongHyeon } 37270dbe28b3SPyun YongHyeon 37280dbe28b3SPyun YongHyeon /* Setup Rx Queue Bus Memory Interface. */ 37290dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_CLR_RESET); 37300dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_OPER_INIT); 37310dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), BMU_FIFO_OP_ON); 37320dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, Q_ADDR(sc_if->msk_rxq, Q_WM), MSK_BMU_RX_WM); 37330dbe28b3SPyun YongHyeon if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U && 37340dbe28b3SPyun YongHyeon sc->msk_hw_rev >= CHIP_REV_YU_EC_U_A1) { 37350dbe28b3SPyun YongHyeon /* MAC Rx RAM Read is controlled by hardware. */ 37360dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_F), F_M_RX_RAM_DIS); 37370dbe28b3SPyun YongHyeon } 37380dbe28b3SPyun YongHyeon 37390dbe28b3SPyun YongHyeon msk_set_prefetch(sc, sc_if->msk_txq, 37400dbe28b3SPyun YongHyeon sc_if->msk_rdata.msk_tx_ring_paddr, MSK_TX_RING_CNT - 1); 37410dbe28b3SPyun YongHyeon msk_init_tx_ring(sc_if); 37420dbe28b3SPyun YongHyeon 37430dbe28b3SPyun YongHyeon /* Disable Rx checksum offload and RSS hash. */ 37440dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 37450dbe28b3SPyun YongHyeon BMU_DIS_RX_CHKSUM | BMU_DIS_RX_RSS_HASH); 37460dbe28b3SPyun YongHyeon if (sc_if->msk_framesize > (MCLBYTES - ETHER_HDR_LEN)) { 37470dbe28b3SPyun YongHyeon msk_set_prefetch(sc, sc_if->msk_rxq, 37480dbe28b3SPyun YongHyeon sc_if->msk_rdata.msk_jumbo_rx_ring_paddr, 37490dbe28b3SPyun YongHyeon MSK_JUMBO_RX_RING_CNT - 1); 37500dbe28b3SPyun YongHyeon error = msk_init_jumbo_rx_ring(sc_if); 37510dbe28b3SPyun YongHyeon } else { 37520dbe28b3SPyun YongHyeon msk_set_prefetch(sc, sc_if->msk_rxq, 37530dbe28b3SPyun YongHyeon sc_if->msk_rdata.msk_rx_ring_paddr, 37540dbe28b3SPyun YongHyeon MSK_RX_RING_CNT - 1); 37550dbe28b3SPyun YongHyeon error = msk_init_rx_ring(sc_if); 37560dbe28b3SPyun YongHyeon } 37570dbe28b3SPyun YongHyeon if (error != 0) { 37580dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, 37590dbe28b3SPyun YongHyeon "initialization failed: no memory for Rx buffers\n"); 37600dbe28b3SPyun YongHyeon msk_stop(sc_if); 37610dbe28b3SPyun YongHyeon return; 37620dbe28b3SPyun YongHyeon } 37630dbe28b3SPyun YongHyeon 37640dbe28b3SPyun YongHyeon /* Configure interrupt handling. */ 37650dbe28b3SPyun YongHyeon if (sc_if->msk_port == MSK_PORT_A) { 37660dbe28b3SPyun YongHyeon sc->msk_intrmask |= Y2_IS_PORT_A; 37670dbe28b3SPyun YongHyeon sc->msk_intrhwemask |= Y2_HWE_L1_MASK; 37680dbe28b3SPyun YongHyeon } else { 37690dbe28b3SPyun YongHyeon sc->msk_intrmask |= Y2_IS_PORT_B; 37700dbe28b3SPyun YongHyeon sc->msk_intrhwemask |= Y2_HWE_L2_MASK; 37710dbe28b3SPyun YongHyeon } 37720dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 37730dbe28b3SPyun YongHyeon CSR_READ_4(sc, B0_HWE_IMSK); 37740dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 37750dbe28b3SPyun YongHyeon CSR_READ_4(sc, B0_IMSK); 37760dbe28b3SPyun YongHyeon 37770dbe28b3SPyun YongHyeon sc_if->msk_link = 0; 37780dbe28b3SPyun YongHyeon mii_mediachg(mii); 37790dbe28b3SPyun YongHyeon 37800dbe28b3SPyun YongHyeon ifp->if_drv_flags |= IFF_DRV_RUNNING; 37810dbe28b3SPyun YongHyeon ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 37820dbe28b3SPyun YongHyeon 37830dbe28b3SPyun YongHyeon callout_reset(&sc_if->msk_tick_ch, hz, msk_tick, sc_if); 37840dbe28b3SPyun YongHyeon } 37850dbe28b3SPyun YongHyeon 37860dbe28b3SPyun YongHyeon static void 37870dbe28b3SPyun YongHyeon msk_set_rambuffer(struct msk_if_softc *sc_if) 37880dbe28b3SPyun YongHyeon { 37890dbe28b3SPyun YongHyeon struct msk_softc *sc; 37900dbe28b3SPyun YongHyeon int ltpp, utpp; 37910dbe28b3SPyun YongHyeon 37920dbe28b3SPyun YongHyeon sc = sc_if->msk_softc; 37930dbe28b3SPyun YongHyeon 37940dbe28b3SPyun YongHyeon /* Setup Rx Queue. */ 37950dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_CLR); 37960dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_START), 37970dbe28b3SPyun YongHyeon sc->msk_rxqstart[sc_if->msk_port] / 8); 37980dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_END), 37990dbe28b3SPyun YongHyeon sc->msk_rxqend[sc_if->msk_port] / 8); 38000dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_WP), 38010dbe28b3SPyun YongHyeon sc->msk_rxqstart[sc_if->msk_port] / 8); 38020dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RP), 38030dbe28b3SPyun YongHyeon sc->msk_rxqstart[sc_if->msk_port] / 8); 38040dbe28b3SPyun YongHyeon 38050dbe28b3SPyun YongHyeon utpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 38060dbe28b3SPyun YongHyeon sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_ULPP) / 8; 38070dbe28b3SPyun YongHyeon ltpp = (sc->msk_rxqend[sc_if->msk_port] + 1 - 38080dbe28b3SPyun YongHyeon sc->msk_rxqstart[sc_if->msk_port] - MSK_RB_LLPP_B) / 8; 38090dbe28b3SPyun YongHyeon if (sc->msk_rxqsize < MSK_MIN_RXQ_SIZE) 38100dbe28b3SPyun YongHyeon ltpp += (MSK_RB_LLPP_B - MSK_RB_LLPP_S) / 8; 38110dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_UTPP), utpp); 38120dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_rxq, RB_RX_LTPP), ltpp); 38130dbe28b3SPyun YongHyeon /* Set Rx priority(RB_RX_UTHP/RB_RX_LTHP) thresholds? */ 38140dbe28b3SPyun YongHyeon 38150dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_ENA_OP_MD); 38160dbe28b3SPyun YongHyeon CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL)); 38170dbe28b3SPyun YongHyeon 38180dbe28b3SPyun YongHyeon /* Setup Tx Queue. */ 38190dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_CLR); 38200dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_START), 38210dbe28b3SPyun YongHyeon sc->msk_txqstart[sc_if->msk_port] / 8); 38220dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_END), 38230dbe28b3SPyun YongHyeon sc->msk_txqend[sc_if->msk_port] / 8); 38240dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_WP), 38250dbe28b3SPyun YongHyeon sc->msk_txqstart[sc_if->msk_port] / 8); 38260dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, RB_ADDR(sc_if->msk_txq, RB_RP), 38270dbe28b3SPyun YongHyeon sc->msk_txqstart[sc_if->msk_port] / 8); 38280dbe28b3SPyun YongHyeon /* Enable Store & Forward for Tx side. */ 38290dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_STFWD); 38300dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_ENA_OP_MD); 38310dbe28b3SPyun YongHyeon CSR_READ_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL)); 38320dbe28b3SPyun YongHyeon } 38330dbe28b3SPyun YongHyeon 38340dbe28b3SPyun YongHyeon static void 38350dbe28b3SPyun YongHyeon msk_set_prefetch(struct msk_softc *sc, int qaddr, bus_addr_t addr, 38360dbe28b3SPyun YongHyeon uint32_t count) 38370dbe28b3SPyun YongHyeon { 38380dbe28b3SPyun YongHyeon 38390dbe28b3SPyun YongHyeon /* Reset the prefetch unit. */ 38400dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 38410dbe28b3SPyun YongHyeon PREF_UNIT_RST_SET); 38420dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 38430dbe28b3SPyun YongHyeon PREF_UNIT_RST_CLR); 38440dbe28b3SPyun YongHyeon /* Set LE base address. */ 38450dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_LOW_REG), 38460dbe28b3SPyun YongHyeon MSK_ADDR_LO(addr)); 38470dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_ADDR_HI_REG), 38480dbe28b3SPyun YongHyeon MSK_ADDR_HI(addr)); 38490dbe28b3SPyun YongHyeon /* Set the list last index. */ 38500dbe28b3SPyun YongHyeon CSR_WRITE_2(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_LAST_IDX_REG), 38510dbe28b3SPyun YongHyeon count); 38520dbe28b3SPyun YongHyeon /* Turn on prefetch unit. */ 38530dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG), 38540dbe28b3SPyun YongHyeon PREF_UNIT_OP_ON); 38550dbe28b3SPyun YongHyeon /* Dummy read to ensure write. */ 38560dbe28b3SPyun YongHyeon CSR_READ_4(sc, Y2_PREF_Q_ADDR(qaddr, PREF_UNIT_CTRL_REG)); 38570dbe28b3SPyun YongHyeon } 38580dbe28b3SPyun YongHyeon 38590dbe28b3SPyun YongHyeon static void 38600dbe28b3SPyun YongHyeon msk_stop(struct msk_if_softc *sc_if) 38610dbe28b3SPyun YongHyeon { 38620dbe28b3SPyun YongHyeon struct msk_softc *sc; 38630dbe28b3SPyun YongHyeon struct msk_txdesc *txd; 38640dbe28b3SPyun YongHyeon struct msk_rxdesc *rxd; 38650dbe28b3SPyun YongHyeon struct msk_rxdesc *jrxd; 38660dbe28b3SPyun YongHyeon struct ifnet *ifp; 38670dbe28b3SPyun YongHyeon uint32_t val; 38680dbe28b3SPyun YongHyeon int i; 38690dbe28b3SPyun YongHyeon 38700dbe28b3SPyun YongHyeon MSK_IF_LOCK_ASSERT(sc_if); 38710dbe28b3SPyun YongHyeon sc = sc_if->msk_softc; 38720dbe28b3SPyun YongHyeon ifp = sc_if->msk_ifp; 38730dbe28b3SPyun YongHyeon 38740dbe28b3SPyun YongHyeon callout_stop(&sc_if->msk_tick_ch); 38752271eac7SPyun YongHyeon sc_if->msk_watchdog_timer = 0; 38760dbe28b3SPyun YongHyeon 38770dbe28b3SPyun YongHyeon /* Disable interrupts. */ 38780dbe28b3SPyun YongHyeon if (sc_if->msk_port == MSK_PORT_A) { 38790dbe28b3SPyun YongHyeon sc->msk_intrmask &= ~Y2_IS_PORT_A; 38800dbe28b3SPyun YongHyeon sc->msk_intrhwemask &= ~Y2_HWE_L1_MASK; 38810dbe28b3SPyun YongHyeon } else { 38820dbe28b3SPyun YongHyeon sc->msk_intrmask &= ~Y2_IS_PORT_B; 38830dbe28b3SPyun YongHyeon sc->msk_intrhwemask &= ~Y2_HWE_L2_MASK; 38840dbe28b3SPyun YongHyeon } 38850dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, B0_HWE_IMSK, sc->msk_intrhwemask); 38860dbe28b3SPyun YongHyeon CSR_READ_4(sc, B0_HWE_IMSK); 38870dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, B0_IMSK, sc->msk_intrmask); 38880dbe28b3SPyun YongHyeon CSR_READ_4(sc, B0_IMSK); 38890dbe28b3SPyun YongHyeon 38900dbe28b3SPyun YongHyeon /* Disable Tx/Rx MAC. */ 38910dbe28b3SPyun YongHyeon val = GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 38920dbe28b3SPyun YongHyeon val &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA); 38930dbe28b3SPyun YongHyeon GMAC_WRITE_2(sc, sc_if->msk_port, GM_GP_CTRL, val); 38940dbe28b3SPyun YongHyeon /* Read again to ensure writing. */ 38950dbe28b3SPyun YongHyeon GMAC_READ_2(sc, sc_if->msk_port, GM_GP_CTRL); 38960dbe28b3SPyun YongHyeon 38970dbe28b3SPyun YongHyeon /* Stop Tx BMU. */ 38980dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), BMU_STOP); 38990dbe28b3SPyun YongHyeon val = CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 39000dbe28b3SPyun YongHyeon for (i = 0; i < MSK_TIMEOUT; i++) { 39010dbe28b3SPyun YongHyeon if ((val & (BMU_STOP | BMU_IDLE)) == 0) { 39020dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 39030dbe28b3SPyun YongHyeon BMU_STOP); 39040dbe28b3SPyun YongHyeon CSR_READ_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR)); 39050dbe28b3SPyun YongHyeon } else 39060dbe28b3SPyun YongHyeon break; 39070dbe28b3SPyun YongHyeon DELAY(1); 39080dbe28b3SPyun YongHyeon } 39090dbe28b3SPyun YongHyeon if (i == MSK_TIMEOUT) 39100dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, "Tx BMU stop failed\n"); 39110dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), 39120dbe28b3SPyun YongHyeon RB_RST_SET | RB_DIS_OP_MD); 39130dbe28b3SPyun YongHyeon 39140dbe28b3SPyun YongHyeon /* Disable all GMAC interrupt. */ 39150dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, GMAC_IRQ_MSK), 0); 39160dbe28b3SPyun YongHyeon /* Disable PHY interrupt. */ 39170dbe28b3SPyun YongHyeon msk_phy_writereg(sc_if, PHY_ADDR_MARV, PHY_MARV_INT_MASK, 0); 39180dbe28b3SPyun YongHyeon 39190dbe28b3SPyun YongHyeon /* Disable the RAM Interface Arbiter. */ 39200dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, MR_ADDR(sc_if->msk_port, TXA_CTRL), TXA_DIS_ARB); 39210dbe28b3SPyun YongHyeon 39220dbe28b3SPyun YongHyeon /* Reset the PCI FIFO of the async Tx queue */ 39230dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_txq, Q_CSR), 39240dbe28b3SPyun YongHyeon BMU_RST_SET | BMU_FIFO_RST); 39250dbe28b3SPyun YongHyeon 39260dbe28b3SPyun YongHyeon /* Reset the Tx prefetch units. */ 39270dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_txq, PREF_UNIT_CTRL_REG), 39280dbe28b3SPyun YongHyeon PREF_UNIT_RST_SET); 39290dbe28b3SPyun YongHyeon 39300dbe28b3SPyun YongHyeon /* Reset the RAM Buffer async Tx queue. */ 39310dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_txq, RB_CTRL), RB_RST_SET); 39320dbe28b3SPyun YongHyeon 39330dbe28b3SPyun YongHyeon /* Reset Tx MAC FIFO. */ 39340dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, TX_GMF_CTRL_T), GMF_RST_SET); 39350dbe28b3SPyun YongHyeon /* Set Pause Off. */ 39360dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, GMAC_CTRL), GMC_PAUSE_OFF); 39370dbe28b3SPyun YongHyeon 39380dbe28b3SPyun YongHyeon /* 39390dbe28b3SPyun YongHyeon * The Rx Stop command will not work for Yukon-2 if the BMU does not 39400dbe28b3SPyun YongHyeon * reach the end of packet and since we can't make sure that we have 39410dbe28b3SPyun YongHyeon * incoming data, we must reset the BMU while it is not during a DMA 39420dbe28b3SPyun YongHyeon * transfer. Since it is possible that the Rx path is still active, 39430dbe28b3SPyun YongHyeon * the Rx RAM buffer will be stopped first, so any possible incoming 39440dbe28b3SPyun YongHyeon * data will not trigger a DMA. After the RAM buffer is stopped, the 39450dbe28b3SPyun YongHyeon * BMU is polled until any DMA in progress is ended and only then it 39460dbe28b3SPyun YongHyeon * will be reset. 39470dbe28b3SPyun YongHyeon */ 39480dbe28b3SPyun YongHyeon 39490dbe28b3SPyun YongHyeon /* Disable the RAM Buffer receive queue. */ 39500dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_DIS_OP_MD); 39510dbe28b3SPyun YongHyeon for (i = 0; i < MSK_TIMEOUT; i++) { 39520dbe28b3SPyun YongHyeon if (CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RSL)) == 39530dbe28b3SPyun YongHyeon CSR_READ_1(sc, RB_ADDR(sc_if->msk_rxq, Q_RL))) 39540dbe28b3SPyun YongHyeon break; 39550dbe28b3SPyun YongHyeon DELAY(1); 39560dbe28b3SPyun YongHyeon } 39570dbe28b3SPyun YongHyeon if (i == MSK_TIMEOUT) 39580dbe28b3SPyun YongHyeon device_printf(sc_if->msk_if_dev, "Rx BMU stop failed\n"); 39590dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Q_ADDR(sc_if->msk_rxq, Q_CSR), 39600dbe28b3SPyun YongHyeon BMU_RST_SET | BMU_FIFO_RST); 39610dbe28b3SPyun YongHyeon /* Reset the Rx prefetch unit. */ 39620dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, Y2_PREF_Q_ADDR(sc_if->msk_rxq, PREF_UNIT_CTRL_REG), 39630dbe28b3SPyun YongHyeon PREF_UNIT_RST_SET); 39640dbe28b3SPyun YongHyeon /* Reset the RAM Buffer receive queue. */ 39650dbe28b3SPyun YongHyeon CSR_WRITE_1(sc, RB_ADDR(sc_if->msk_rxq, RB_CTRL), RB_RST_SET); 39660dbe28b3SPyun YongHyeon /* Reset Rx MAC FIFO. */ 39670dbe28b3SPyun YongHyeon CSR_WRITE_4(sc, MR_ADDR(sc_if->msk_port, RX_GMF_CTRL_T), GMF_RST_SET); 39680dbe28b3SPyun YongHyeon 39690dbe28b3SPyun YongHyeon /* Free Rx and Tx mbufs still in the queues. */ 39700dbe28b3SPyun YongHyeon for (i = 0; i < MSK_RX_RING_CNT; i++) { 39710dbe28b3SPyun YongHyeon rxd = &sc_if->msk_cdata.msk_rxdesc[i]; 39720dbe28b3SPyun YongHyeon if (rxd->rx_m != NULL) { 39730dbe28b3SPyun YongHyeon bus_dmamap_sync(sc_if->msk_cdata.msk_rx_tag, 39740dbe28b3SPyun YongHyeon rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 39750dbe28b3SPyun YongHyeon bus_dmamap_unload(sc_if->msk_cdata.msk_rx_tag, 39760dbe28b3SPyun YongHyeon rxd->rx_dmamap); 39770dbe28b3SPyun YongHyeon m_freem(rxd->rx_m); 39780dbe28b3SPyun YongHyeon rxd->rx_m = NULL; 39790dbe28b3SPyun YongHyeon } 39800dbe28b3SPyun YongHyeon } 39810dbe28b3SPyun YongHyeon for (i = 0; i < MSK_JUMBO_RX_RING_CNT; i++) { 39820dbe28b3SPyun YongHyeon jrxd = &sc_if->msk_cdata.msk_jumbo_rxdesc[i]; 39830dbe28b3SPyun YongHyeon if (jrxd->rx_m != NULL) { 39840dbe28b3SPyun YongHyeon bus_dmamap_sync(sc_if->msk_cdata.msk_jumbo_rx_tag, 39850dbe28b3SPyun YongHyeon jrxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 39860dbe28b3SPyun YongHyeon bus_dmamap_unload(sc_if->msk_cdata.msk_jumbo_rx_tag, 39870dbe28b3SPyun YongHyeon jrxd->rx_dmamap); 39880dbe28b3SPyun YongHyeon m_freem(jrxd->rx_m); 39890dbe28b3SPyun YongHyeon jrxd->rx_m = NULL; 39900dbe28b3SPyun YongHyeon } 39910dbe28b3SPyun YongHyeon } 39920dbe28b3SPyun YongHyeon for (i = 0; i < MSK_TX_RING_CNT; i++) { 39930dbe28b3SPyun YongHyeon txd = &sc_if->msk_cdata.msk_txdesc[i]; 39940dbe28b3SPyun YongHyeon if (txd->tx_m != NULL) { 39950dbe28b3SPyun YongHyeon bus_dmamap_sync(sc_if->msk_cdata.msk_tx_tag, 39960dbe28b3SPyun YongHyeon txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 39970dbe28b3SPyun YongHyeon bus_dmamap_unload(sc_if->msk_cdata.msk_tx_tag, 39980dbe28b3SPyun YongHyeon txd->tx_dmamap); 39990dbe28b3SPyun YongHyeon m_freem(txd->tx_m); 40000dbe28b3SPyun YongHyeon txd->tx_m = NULL; 40010dbe28b3SPyun YongHyeon } 40020dbe28b3SPyun YongHyeon } 40030dbe28b3SPyun YongHyeon 40040dbe28b3SPyun YongHyeon /* 40050dbe28b3SPyun YongHyeon * Mark the interface down. 40060dbe28b3SPyun YongHyeon */ 40070dbe28b3SPyun YongHyeon ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 40080dbe28b3SPyun YongHyeon sc_if->msk_link = 0; 40090dbe28b3SPyun YongHyeon } 40100dbe28b3SPyun YongHyeon 40110dbe28b3SPyun YongHyeon static int 40120dbe28b3SPyun YongHyeon sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 40130dbe28b3SPyun YongHyeon { 40140dbe28b3SPyun YongHyeon int error, value; 40150dbe28b3SPyun YongHyeon 40160dbe28b3SPyun YongHyeon if (!arg1) 40170dbe28b3SPyun YongHyeon return (EINVAL); 40180dbe28b3SPyun YongHyeon value = *(int *)arg1; 40190dbe28b3SPyun YongHyeon error = sysctl_handle_int(oidp, &value, 0, req); 40200dbe28b3SPyun YongHyeon if (error || !req->newptr) 40210dbe28b3SPyun YongHyeon return (error); 40220dbe28b3SPyun YongHyeon if (value < low || value > high) 40230dbe28b3SPyun YongHyeon return (EINVAL); 40240dbe28b3SPyun YongHyeon *(int *)arg1 = value; 40250dbe28b3SPyun YongHyeon 40260dbe28b3SPyun YongHyeon return (0); 40270dbe28b3SPyun YongHyeon } 40280dbe28b3SPyun YongHyeon 40290dbe28b3SPyun YongHyeon static int 40300dbe28b3SPyun YongHyeon sysctl_hw_msk_proc_limit(SYSCTL_HANDLER_ARGS) 40310dbe28b3SPyun YongHyeon { 40320dbe28b3SPyun YongHyeon 40330dbe28b3SPyun YongHyeon return (sysctl_int_range(oidp, arg1, arg2, req, MSK_PROC_MIN, 40340dbe28b3SPyun YongHyeon MSK_PROC_MAX)); 40350dbe28b3SPyun YongHyeon } 4036