1 /* 2 * Copyright (c) 2015, AVAGO Tech. All rights reserved. Author: Marian Choy 3 * Copyright (c) 2014, LSI Corp. All rights reserved. Author: Marian Choy 4 * Support: freebsdraid@avagotech.com 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 2. Redistributions 12 * in binary form must reproduce the above copyright notice, this list of 13 * conditions and the following disclaimer in the documentation and/or other 14 * materials provided with the distribution. 3. Neither the name of the 15 * <ORGANIZATION> nor the names of its contributors may be used to endorse or 16 * promote products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * The views and conclusions contained in the software and documentation are 32 * those of the authors and should not be interpreted as representing 33 * official policies,either expressed or implied, of the FreeBSD Project. 34 * 35 * Send feedback to: <megaraidfbsd@avagotech.com> Mail to: AVAGO TECHNOLOGIES, 1621 36 * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD 37 * 38 */ 39 40 #include <sys/cdefs.h> 41 __FBSDID("$FreeBSD$"); 42 43 #include <dev/mrsas/mrsas.h> 44 45 #include <cam/cam.h> 46 #include <cam/cam_ccb.h> 47 #include <cam/cam_sim.h> 48 #include <cam/cam_xpt_sim.h> 49 #include <cam/cam_debug.h> 50 #include <cam/cam_periph.h> 51 #include <cam/cam_xpt_periph.h> 52 53 /* 54 * Function prototypes 55 */ 56 u_int8_t MR_ValidateMapInfo(struct mrsas_softc *sc); 57 u_int8_t 58 mrsas_get_best_arm_pd(struct mrsas_softc *sc, 59 PLD_LOAD_BALANCE_INFO lbInfo, struct IO_REQUEST_INFO *io_info); 60 u_int8_t 61 MR_BuildRaidContext(struct mrsas_softc *sc, 62 struct IO_REQUEST_INFO *io_info, 63 RAID_CONTEXT * pRAID_Context, MR_DRV_RAID_MAP_ALL * map); 64 u_int8_t 65 MR_GetPhyParams(struct mrsas_softc *sc, u_int32_t ld, 66 u_int64_t stripRow, u_int16_t stripRef, struct IO_REQUEST_INFO *io_info, 67 RAID_CONTEXT * pRAID_Context, 68 MR_DRV_RAID_MAP_ALL * map); 69 u_int8_t MR_TargetIdToLdGet(u_int32_t ldTgtId, MR_DRV_RAID_MAP_ALL *map); 70 u_int32_t MR_LdBlockSizeGet(u_int32_t ldTgtId, MR_DRV_RAID_MAP_ALL * map); 71 u_int16_t MR_GetLDTgtId(u_int32_t ld, MR_DRV_RAID_MAP_ALL * map); 72 u_int16_t 73 mrsas_get_updated_dev_handle(struct mrsas_softc *sc, 74 PLD_LOAD_BALANCE_INFO lbInfo, struct IO_REQUEST_INFO *io_info); 75 u_int32_t mega_mod64(u_int64_t dividend, u_int32_t divisor); 76 u_int32_t 77 MR_GetSpanBlock(u_int32_t ld, u_int64_t row, u_int64_t *span_blk, 78 MR_DRV_RAID_MAP_ALL * map, int *div_error); 79 u_int64_t mega_div64_32(u_int64_t dividend, u_int32_t divisor); 80 void 81 mrsas_update_load_balance_params(struct mrsas_softc *sc, 82 MR_DRV_RAID_MAP_ALL * map, PLD_LOAD_BALANCE_INFO lbInfo); 83 void 84 mrsas_set_pd_lba(MRSAS_RAID_SCSI_IO_REQUEST * io_request, 85 u_int8_t cdb_len, struct IO_REQUEST_INFO *io_info, union ccb *ccb, 86 MR_DRV_RAID_MAP_ALL * local_map_ptr, u_int32_t ref_tag, 87 u_int32_t ld_block_size); 88 static u_int16_t 89 MR_LdSpanArrayGet(u_int32_t ld, u_int32_t span, 90 MR_DRV_RAID_MAP_ALL * map); 91 static u_int16_t MR_PdDevHandleGet(u_int32_t pd, MR_DRV_RAID_MAP_ALL * map); 92 static u_int16_t 93 MR_ArPdGet(u_int32_t ar, u_int32_t arm, 94 MR_DRV_RAID_MAP_ALL * map); 95 static MR_LD_SPAN * 96 MR_LdSpanPtrGet(u_int32_t ld, u_int32_t span, 97 MR_DRV_RAID_MAP_ALL * map); 98 static u_int8_t 99 MR_LdDataArmGet(u_int32_t ld, u_int32_t armIdx, 100 MR_DRV_RAID_MAP_ALL * map); 101 static MR_SPAN_BLOCK_INFO * 102 MR_LdSpanInfoGet(u_int32_t ld, 103 MR_DRV_RAID_MAP_ALL * map); 104 MR_LD_RAID *MR_LdRaidGet(u_int32_t ld, MR_DRV_RAID_MAP_ALL * map); 105 static int MR_PopulateDrvRaidMap(struct mrsas_softc *sc); 106 107 /* 108 * Spanset related function prototypes Added for PRL11 configuration (Uneven 109 * span support) 110 */ 111 void mr_update_span_set(MR_DRV_RAID_MAP_ALL * map, PLD_SPAN_INFO ldSpanInfo); 112 static u_int8_t 113 mr_spanset_get_phy_params(struct mrsas_softc *sc, u_int32_t ld, 114 u_int64_t stripRow, u_int16_t stripRef, struct IO_REQUEST_INFO *io_info, 115 RAID_CONTEXT * pRAID_Context, MR_DRV_RAID_MAP_ALL * map); 116 static u_int64_t 117 get_row_from_strip(struct mrsas_softc *sc, u_int32_t ld, 118 u_int64_t strip, MR_DRV_RAID_MAP_ALL * map); 119 static u_int32_t 120 mr_spanset_get_span_block(struct mrsas_softc *sc, 121 u_int32_t ld, u_int64_t row, u_int64_t *span_blk, 122 MR_DRV_RAID_MAP_ALL * map, int *div_error); 123 static u_int8_t 124 get_arm(struct mrsas_softc *sc, u_int32_t ld, u_int8_t span, 125 u_int64_t stripe, MR_DRV_RAID_MAP_ALL * map); 126 127 /* 128 * Spanset related defines Added for PRL11 configuration(Uneven span support) 129 */ 130 #define SPAN_ROW_SIZE(map, ld, index_) MR_LdSpanPtrGet(ld, index_, map)->spanRowSize 131 #define SPAN_ROW_DATA_SIZE(map_, ld, index_) \ 132 MR_LdSpanPtrGet(ld, index_, map)->spanRowDataSize 133 #define SPAN_INVALID 0xff 134 #define SPAN_DEBUG 0 135 136 /* 137 * Related Defines 138 */ 139 140 typedef u_int64_t REGION_KEY; 141 typedef u_int32_t REGION_LEN; 142 143 #define MR_LD_STATE_OPTIMAL 3 144 #define FALSE 0 145 #define TRUE 1 146 147 #define LB_PENDING_CMDS_DEFAULT 4 148 149 /* 150 * Related Macros 151 */ 152 153 #define ABS_DIFF(a,b) ( ((a) > (b)) ? ((a) - (b)) : ((b) - (a)) ) 154 155 #define swap32(x) \ 156 ((unsigned int)( \ 157 (((unsigned int)(x) & (unsigned int)0x000000ffUL) << 24) | \ 158 (((unsigned int)(x) & (unsigned int)0x0000ff00UL) << 8) | \ 159 (((unsigned int)(x) & (unsigned int)0x00ff0000UL) >> 8) | \ 160 (((unsigned int)(x) & (unsigned int)0xff000000UL) >> 24) )) 161 162 /* 163 * In-line functions for mod and divide of 64-bit dividend and 32-bit 164 * divisor. Assumes a check for a divisor of zero is not possible. 165 * 166 * @param dividend: Dividend 167 * @param divisor: Divisor 168 * @return remainder 169 */ 170 171 #define mega_mod64(dividend, divisor) ({ \ 172 int remainder; \ 173 remainder = ((u_int64_t) (dividend)) % (u_int32_t) (divisor); \ 174 remainder;}) 175 176 #define mega_div64_32(dividend, divisor) ({ \ 177 int quotient; \ 178 quotient = ((u_int64_t) (dividend)) / (u_int32_t) (divisor); \ 179 quotient;}) 180 181 /* 182 * Various RAID map access functions. These functions access the various 183 * parts of the RAID map and returns the appropriate parameters. 184 */ 185 186 MR_LD_RAID * 187 MR_LdRaidGet(u_int32_t ld, MR_DRV_RAID_MAP_ALL * map) 188 { 189 return (&map->raidMap.ldSpanMap[ld].ldRaid); 190 } 191 192 u_int16_t 193 MR_GetLDTgtId(u_int32_t ld, MR_DRV_RAID_MAP_ALL * map) 194 { 195 return (map->raidMap.ldSpanMap[ld].ldRaid.targetId); 196 } 197 198 static u_int16_t 199 MR_LdSpanArrayGet(u_int32_t ld, u_int32_t span, MR_DRV_RAID_MAP_ALL * map) 200 { 201 return map->raidMap.ldSpanMap[ld].spanBlock[span].span.arrayRef; 202 } 203 204 static u_int8_t 205 MR_LdDataArmGet(u_int32_t ld, u_int32_t armIdx, MR_DRV_RAID_MAP_ALL * map) 206 { 207 return map->raidMap.ldSpanMap[ld].dataArmMap[armIdx]; 208 } 209 210 static u_int16_t 211 MR_PdDevHandleGet(u_int32_t pd, MR_DRV_RAID_MAP_ALL * map) 212 { 213 return map->raidMap.devHndlInfo[pd].curDevHdl; 214 } 215 216 static u_int8_t MR_PdInterfaceTypeGet(u_int32_t pd, MR_DRV_RAID_MAP_ALL *map) 217 { 218 return map->raidMap.devHndlInfo[pd].interfaceType; 219 } 220 221 static u_int16_t 222 MR_ArPdGet(u_int32_t ar, u_int32_t arm, MR_DRV_RAID_MAP_ALL * map) 223 { 224 return map->raidMap.arMapInfo[ar].pd[arm]; 225 } 226 227 static MR_LD_SPAN * 228 MR_LdSpanPtrGet(u_int32_t ld, u_int32_t span, MR_DRV_RAID_MAP_ALL * map) 229 { 230 return &map->raidMap.ldSpanMap[ld].spanBlock[span].span; 231 } 232 233 static MR_SPAN_BLOCK_INFO * 234 MR_LdSpanInfoGet(u_int32_t ld, MR_DRV_RAID_MAP_ALL * map) 235 { 236 return &map->raidMap.ldSpanMap[ld].spanBlock[0]; 237 } 238 239 u_int8_t 240 MR_TargetIdToLdGet(u_int32_t ldTgtId, MR_DRV_RAID_MAP_ALL * map) 241 { 242 return map->raidMap.ldTgtIdToLd[ldTgtId]; 243 } 244 245 u_int32_t 246 MR_LdBlockSizeGet(u_int32_t ldTgtId, MR_DRV_RAID_MAP_ALL * map) 247 { 248 MR_LD_RAID *raid; 249 u_int32_t ld, ldBlockSize = MRSAS_SCSIBLOCKSIZE; 250 251 ld = MR_TargetIdToLdGet(ldTgtId, map); 252 253 /* 254 * Check if logical drive was removed. 255 */ 256 if (ld >= MAX_LOGICAL_DRIVES) 257 return ldBlockSize; 258 259 raid = MR_LdRaidGet(ld, map); 260 ldBlockSize = raid->logicalBlockLength; 261 if (!ldBlockSize) 262 ldBlockSize = MRSAS_SCSIBLOCKSIZE; 263 264 return ldBlockSize; 265 } 266 267 /* 268 * This function will Populate Driver Map using Dynamic firmware raid map 269 */ 270 static int 271 MR_PopulateDrvRaidMapVentura(struct mrsas_softc *sc) 272 { 273 unsigned int i, j; 274 u_int16_t ld_count; 275 276 MR_FW_RAID_MAP_DYNAMIC *fw_map_dyn; 277 MR_RAID_MAP_DESC_TABLE *desc_table; 278 MR_DRV_RAID_MAP_ALL *drv_map = sc->ld_drv_map[(sc->map_id & 1)]; 279 MR_DRV_RAID_MAP *pDrvRaidMap = &drv_map->raidMap; 280 void *raid_map_data = NULL; 281 282 fw_map_dyn = (MR_FW_RAID_MAP_DYNAMIC *) sc->raidmap_mem[(sc->map_id & 1)]; 283 284 if (fw_map_dyn == NULL) { 285 device_printf(sc->mrsas_dev, 286 "from %s %d map0 %p map1 %p map size %d \n", __func__, __LINE__, 287 sc->raidmap_mem[0], sc->raidmap_mem[1], sc->maxRaidMapSize); 288 return 1; 289 } 290 #if VD_EXT_DEBUG 291 device_printf(sc->mrsas_dev, 292 " raidMapSize 0x%x, descTableOffset 0x%x, " 293 " descTableSize 0x%x, descTableNumElements 0x%x \n", 294 fw_map_dyn->raidMapSize, fw_map_dyn->descTableOffset, 295 fw_map_dyn->descTableSize, fw_map_dyn->descTableNumElements); 296 #endif 297 desc_table = (MR_RAID_MAP_DESC_TABLE *) ((char *)fw_map_dyn + 298 fw_map_dyn->descTableOffset); 299 if (desc_table != fw_map_dyn->raidMapDescTable) { 300 device_printf(sc->mrsas_dev, 301 "offsets of desc table are not matching returning " 302 " FW raid map has been changed: desc %p original %p\n", 303 desc_table, fw_map_dyn->raidMapDescTable); 304 } 305 memset(drv_map, 0, sc->drv_map_sz); 306 ld_count = fw_map_dyn->ldCount; 307 pDrvRaidMap->ldCount = ld_count; 308 pDrvRaidMap->fpPdIoTimeoutSec = fw_map_dyn->fpPdIoTimeoutSec; 309 pDrvRaidMap->totalSize = sizeof(MR_DRV_RAID_MAP_ALL); 310 /* point to actual data starting point */ 311 raid_map_data = (char *)fw_map_dyn + 312 fw_map_dyn->descTableOffset + fw_map_dyn->descTableSize; 313 314 for (i = 0; i < fw_map_dyn->descTableNumElements; ++i) { 315 if (!desc_table) { 316 device_printf(sc->mrsas_dev, 317 "desc table is null, coming out %p \n", desc_table); 318 return 1; 319 } 320 #if VD_EXT_DEBUG 321 device_printf(sc->mrsas_dev, "raid_map_data %p \n", raid_map_data); 322 device_printf(sc->mrsas_dev, 323 "desc table %p \n", desc_table); 324 device_printf(sc->mrsas_dev, 325 "raidmap type %d, raidmapOffset 0x%x, " 326 " raid map number of elements 0%x, raidmapsize 0x%x\n", 327 desc_table->raidMapDescType, desc_table->raidMapDescOffset, 328 desc_table->raidMapDescElements, desc_table->raidMapDescBufferSize); 329 #endif 330 switch (desc_table->raidMapDescType) { 331 case RAID_MAP_DESC_TYPE_DEVHDL_INFO: 332 fw_map_dyn->RaidMapDescPtrs.ptrStruct.devHndlInfo = (MR_DEV_HANDLE_INFO *) 333 ((char *)raid_map_data + desc_table->raidMapDescOffset); 334 #if VD_EXT_DEBUG 335 device_printf(sc->mrsas_dev, 336 "devHndlInfo address %p\n", fw_map_dyn->RaidMapDescPtrs.ptrStruct.devHndlInfo); 337 #endif 338 memcpy(pDrvRaidMap->devHndlInfo, fw_map_dyn->RaidMapDescPtrs.ptrStruct.devHndlInfo, 339 sizeof(MR_DEV_HANDLE_INFO) * desc_table->raidMapDescElements); 340 break; 341 case RAID_MAP_DESC_TYPE_TGTID_INFO: 342 fw_map_dyn->RaidMapDescPtrs.ptrStruct.ldTgtIdToLd = (u_int16_t *) 343 ((char *)raid_map_data + desc_table->raidMapDescOffset); 344 #if VD_EXT_DEBUG 345 device_printf(sc->mrsas_dev, 346 "ldTgtIdToLd address %p\n", fw_map_dyn->RaidMapDescPtrs.ptrStruct.ldTgtIdToLd); 347 #endif 348 for (j = 0; j < desc_table->raidMapDescElements; j++) { 349 pDrvRaidMap->ldTgtIdToLd[j] = fw_map_dyn->RaidMapDescPtrs.ptrStruct.ldTgtIdToLd[j]; 350 #if VD_EXT_DEBUG 351 device_printf(sc->mrsas_dev, 352 " %d drv ldTgtIdToLd %d\n", j, pDrvRaidMap->ldTgtIdToLd[j]); 353 #endif 354 } 355 break; 356 case RAID_MAP_DESC_TYPE_ARRAY_INFO: 357 fw_map_dyn->RaidMapDescPtrs.ptrStruct.arMapInfo = (MR_ARRAY_INFO *) ((char *)raid_map_data + 358 desc_table->raidMapDescOffset); 359 #if VD_EXT_DEBUG 360 device_printf(sc->mrsas_dev, 361 "arMapInfo address %p\n", fw_map_dyn->RaidMapDescPtrs.ptrStruct.arMapInfo); 362 #endif 363 memcpy(pDrvRaidMap->arMapInfo, fw_map_dyn->RaidMapDescPtrs.ptrStruct.arMapInfo, 364 sizeof(MR_ARRAY_INFO) * desc_table->raidMapDescElements); 365 break; 366 case RAID_MAP_DESC_TYPE_SPAN_INFO: 367 fw_map_dyn->RaidMapDescPtrs.ptrStruct.ldSpanMap = (MR_LD_SPAN_MAP *) ((char *)raid_map_data + 368 desc_table->raidMapDescOffset); 369 memcpy(pDrvRaidMap->ldSpanMap, fw_map_dyn->RaidMapDescPtrs.ptrStruct.ldSpanMap, 370 sizeof(MR_LD_SPAN_MAP) * desc_table->raidMapDescElements); 371 #if VD_EXT_DEBUG 372 device_printf(sc->mrsas_dev, 373 "ldSpanMap address %p\n", fw_map_dyn->RaidMapDescPtrs.ptrStruct.ldSpanMap); 374 device_printf(sc->mrsas_dev, 375 "MR_LD_SPAN_MAP size 0x%lx\n", sizeof(MR_LD_SPAN_MAP)); 376 for (j = 0; j < ld_count; j++) { 377 printf("mrsas(%d) : fw_map_dyn->ldSpanMap[%d].ldRaid.targetId 0x%x " 378 "fw_map_dyn->ldSpanMap[%d].ldRaid.seqNum 0x%x size 0x%x\n", 379 j, j, fw_map_dyn->RaidMapDescPtrs.ptrStruct.ldSpanMap[j].ldRaid.targetId, j, 380 fw_map_dyn->RaidMapDescPtrs.ptrStruct.ldSpanMap[j].ldRaid.seqNum, 381 (u_int32_t)fw_map_dyn->RaidMapDescPtrs.ptrStruct.ldSpanMap[j].ldRaid.rowSize); 382 printf("mrsas(%d) : pDrvRaidMap->ldSpanMap[%d].ldRaid.targetId 0x%x " 383 "pDrvRaidMap->ldSpanMap[%d].ldRaid.seqNum 0x%x size 0x%x\n", 384 j, j, pDrvRaidMap->ldSpanMap[j].ldRaid.targetId, j, 385 pDrvRaidMap->ldSpanMap[j].ldRaid.seqNum, 386 (u_int32_t)pDrvRaidMap->ldSpanMap[j].ldRaid.rowSize); 387 printf("mrsas : drv raid map all %p raid map %p LD RAID MAP %p/%p\n", 388 drv_map, pDrvRaidMap, &fw_map_dyn->RaidMapDescPtrs.ptrStruct.ldSpanMap[j].ldRaid, 389 &pDrvRaidMap->ldSpanMap[j].ldRaid); 390 } 391 #endif 392 break; 393 default: 394 device_printf(sc->mrsas_dev, 395 "wrong number of desctableElements %d\n", 396 fw_map_dyn->descTableNumElements); 397 } 398 ++desc_table; 399 } 400 return 0; 401 } 402 403 /* 404 * This function will Populate Driver Map using firmware raid map 405 */ 406 static int 407 MR_PopulateDrvRaidMap(struct mrsas_softc *sc) 408 { 409 MR_FW_RAID_MAP_ALL *fw_map_old = NULL; 410 MR_FW_RAID_MAP_EXT *fw_map_ext; 411 MR_FW_RAID_MAP *pFwRaidMap = NULL; 412 unsigned int i; 413 u_int16_t ld_count; 414 415 MR_DRV_RAID_MAP_ALL *drv_map = sc->ld_drv_map[(sc->map_id & 1)]; 416 MR_DRV_RAID_MAP *pDrvRaidMap = &drv_map->raidMap; 417 418 if (sc->maxRaidMapSize) { 419 return MR_PopulateDrvRaidMapVentura(sc); 420 } else if (sc->max256vdSupport) { 421 fw_map_ext = (MR_FW_RAID_MAP_EXT *) sc->raidmap_mem[(sc->map_id & 1)]; 422 ld_count = (u_int16_t)(fw_map_ext->ldCount); 423 if (ld_count > MAX_LOGICAL_DRIVES_EXT) { 424 device_printf(sc->mrsas_dev, 425 "mrsas: LD count exposed in RAID map in not valid\n"); 426 return 1; 427 } 428 #if VD_EXT_DEBUG 429 for (i = 0; i < ld_count; i++) { 430 printf("mrsas : Index 0x%x Target Id 0x%x Seq Num 0x%x Size 0/%lx\n", 431 i, fw_map_ext->ldSpanMap[i].ldRaid.targetId, 432 fw_map_ext->ldSpanMap[i].ldRaid.seqNum, 433 fw_map_ext->ldSpanMap[i].ldRaid.size); 434 } 435 #endif 436 memset(drv_map, 0, sc->drv_map_sz); 437 pDrvRaidMap->ldCount = ld_count; 438 pDrvRaidMap->fpPdIoTimeoutSec = fw_map_ext->fpPdIoTimeoutSec; 439 for (i = 0; i < (MAX_LOGICAL_DRIVES_EXT); i++) { 440 pDrvRaidMap->ldTgtIdToLd[i] = (u_int16_t)fw_map_ext->ldTgtIdToLd[i]; 441 } 442 memcpy(pDrvRaidMap->ldSpanMap, fw_map_ext->ldSpanMap, sizeof(MR_LD_SPAN_MAP) * ld_count); 443 #if VD_EXT_DEBUG 444 for (i = 0; i < ld_count; i++) { 445 printf("mrsas(%d) : fw_map_ext->ldSpanMap[%d].ldRaid.targetId 0x%x " 446 "fw_map_ext->ldSpanMap[%d].ldRaid.seqNum 0x%x size 0x%x\n", 447 i, i, fw_map_ext->ldSpanMap[i].ldRaid.targetId, i, 448 fw_map_ext->ldSpanMap[i].ldRaid.seqNum, 449 (u_int32_t)fw_map_ext->ldSpanMap[i].ldRaid.rowSize); 450 printf("mrsas(%d) : pDrvRaidMap->ldSpanMap[%d].ldRaid.targetId 0x%x" 451 "pDrvRaidMap->ldSpanMap[%d].ldRaid.seqNum 0x%x size 0x%x\n", i, i, 452 pDrvRaidMap->ldSpanMap[i].ldRaid.targetId, i, 453 pDrvRaidMap->ldSpanMap[i].ldRaid.seqNum, 454 (u_int32_t)pDrvRaidMap->ldSpanMap[i].ldRaid.rowSize); 455 printf("mrsas : drv raid map all %p raid map %p LD RAID MAP %p/%p\n", 456 drv_map, pDrvRaidMap, &fw_map_ext->ldSpanMap[i].ldRaid, 457 &pDrvRaidMap->ldSpanMap[i].ldRaid); 458 } 459 #endif 460 memcpy(pDrvRaidMap->arMapInfo, fw_map_ext->arMapInfo, 461 sizeof(MR_ARRAY_INFO) * MAX_API_ARRAYS_EXT); 462 memcpy(pDrvRaidMap->devHndlInfo, fw_map_ext->devHndlInfo, 463 sizeof(MR_DEV_HANDLE_INFO) * MAX_RAIDMAP_PHYSICAL_DEVICES); 464 465 pDrvRaidMap->totalSize = sizeof(MR_FW_RAID_MAP_EXT); 466 } else { 467 fw_map_old = (MR_FW_RAID_MAP_ALL *) sc->raidmap_mem[(sc->map_id & 1)]; 468 pFwRaidMap = &fw_map_old->raidMap; 469 470 #if VD_EXT_DEBUG 471 for (i = 0; i < pFwRaidMap->ldCount; i++) { 472 device_printf(sc->mrsas_dev, 473 "Index 0x%x Target Id 0x%x Seq Num 0x%x Size 0/%lx\n", i, 474 fw_map_old->raidMap.ldSpanMap[i].ldRaid.targetId, 475 fw_map_old->raidMap.ldSpanMap[i].ldRaid.seqNum, 476 fw_map_old->raidMap.ldSpanMap[i].ldRaid.size); 477 } 478 #endif 479 480 memset(drv_map, 0, sc->drv_map_sz); 481 pDrvRaidMap->totalSize = pFwRaidMap->totalSize; 482 pDrvRaidMap->ldCount = pFwRaidMap->ldCount; 483 pDrvRaidMap->fpPdIoTimeoutSec = 484 pFwRaidMap->fpPdIoTimeoutSec; 485 486 for (i = 0; i < MAX_RAIDMAP_LOGICAL_DRIVES + MAX_RAIDMAP_VIEWS; i++) { 487 pDrvRaidMap->ldTgtIdToLd[i] = 488 (u_int8_t)pFwRaidMap->ldTgtIdToLd[i]; 489 } 490 491 for (i = 0; i < pDrvRaidMap->ldCount; i++) { 492 pDrvRaidMap->ldSpanMap[i] = 493 pFwRaidMap->ldSpanMap[i]; 494 495 #if VD_EXT_DEBUG 496 device_printf(sc->mrsas_dev, "pFwRaidMap->ldSpanMap[%d].ldRaid.targetId 0x%x " 497 "pFwRaidMap->ldSpanMap[%d].ldRaid.seqNum 0x%x size 0x%x\n", 498 i, i, pFwRaidMap->ldSpanMap[i].ldRaid.targetId, 499 pFwRaidMap->ldSpanMap[i].ldRaid.seqNum, 500 (u_int32_t)pFwRaidMap->ldSpanMap[i].ldRaid.rowSize); 501 device_printf(sc->mrsas_dev, "pDrvRaidMap->ldSpanMap[%d].ldRaid.targetId 0x%x" 502 "pDrvRaidMap->ldSpanMap[%d].ldRaid.seqNum 0x%x size 0x%x\n", i, i, 503 pDrvRaidMap->ldSpanMap[i].ldRaid.targetId, 504 pDrvRaidMap->ldSpanMap[i].ldRaid.seqNum, 505 (u_int32_t)pDrvRaidMap->ldSpanMap[i].ldRaid.rowSize); 506 device_printf(sc->mrsas_dev, "drv raid map all %p raid map %p LD RAID MAP %p/%p\n", 507 drv_map, pDrvRaidMap, 508 &pFwRaidMap->ldSpanMap[i].ldRaid, &pDrvRaidMap->ldSpanMap[i].ldRaid); 509 #endif 510 } 511 512 memcpy(pDrvRaidMap->arMapInfo, pFwRaidMap->arMapInfo, 513 sizeof(MR_ARRAY_INFO) * MAX_RAIDMAP_ARRAYS); 514 memcpy(pDrvRaidMap->devHndlInfo, pFwRaidMap->devHndlInfo, 515 sizeof(MR_DEV_HANDLE_INFO) * 516 MAX_RAIDMAP_PHYSICAL_DEVICES); 517 } 518 return 0; 519 } 520 521 /* 522 * MR_ValidateMapInfo: Validate RAID map 523 * input: Adapter instance soft state 524 * 525 * This function checks and validates the loaded RAID map. It returns 0 if 526 * successful, and 1 otherwise. 527 */ 528 u_int8_t 529 MR_ValidateMapInfo(struct mrsas_softc *sc) 530 { 531 if (!sc) { 532 return 1; 533 } 534 if (MR_PopulateDrvRaidMap(sc)) 535 return 0; 536 537 MR_DRV_RAID_MAP_ALL *drv_map = sc->ld_drv_map[(sc->map_id & 1)]; 538 MR_DRV_RAID_MAP *pDrvRaidMap = &drv_map->raidMap; 539 540 u_int32_t expected_map_size; 541 542 drv_map = sc->ld_drv_map[(sc->map_id & 1)]; 543 pDrvRaidMap = &drv_map->raidMap; 544 PLD_SPAN_INFO ldSpanInfo = (PLD_SPAN_INFO) & sc->log_to_span; 545 546 if (sc->maxRaidMapSize) 547 expected_map_size = sizeof(MR_DRV_RAID_MAP_ALL); 548 else if (sc->max256vdSupport) 549 expected_map_size = sizeof(MR_FW_RAID_MAP_EXT); 550 else 551 expected_map_size = 552 (sizeof(MR_FW_RAID_MAP) - sizeof(MR_LD_SPAN_MAP)) + 553 (sizeof(MR_LD_SPAN_MAP) * pDrvRaidMap->ldCount); 554 555 if (pDrvRaidMap->totalSize != expected_map_size) { 556 device_printf(sc->mrsas_dev, "map size %x not matching ld count\n", expected_map_size); 557 device_printf(sc->mrsas_dev, "span map= %x\n", (unsigned int)sizeof(MR_LD_SPAN_MAP)); 558 device_printf(sc->mrsas_dev, "pDrvRaidMap->totalSize=%x\n", pDrvRaidMap->totalSize); 559 return 1; 560 } 561 if (sc->UnevenSpanSupport) { 562 mr_update_span_set(drv_map, ldSpanInfo); 563 } 564 mrsas_update_load_balance_params(sc, drv_map, sc->load_balance_info); 565 566 return 0; 567 } 568 569 /* 570 * 571 * Function to print info about span set created in driver from FW raid map 572 * 573 * Inputs: map 574 * ldSpanInfo: ld map span info per HBA instance 575 * 576 * 577 */ 578 #if SPAN_DEBUG 579 static int 580 getSpanInfo(MR_DRV_RAID_MAP_ALL * map, PLD_SPAN_INFO ldSpanInfo) 581 { 582 583 u_int8_t span; 584 u_int32_t element; 585 MR_LD_RAID *raid; 586 LD_SPAN_SET *span_set; 587 MR_QUAD_ELEMENT *quad; 588 int ldCount; 589 u_int16_t ld; 590 591 for (ldCount = 0; ldCount < MAX_LOGICAL_DRIVES; ldCount++) { 592 ld = MR_TargetIdToLdGet(ldCount, map); 593 if (ld >= MAX_LOGICAL_DRIVES) { 594 continue; 595 } 596 raid = MR_LdRaidGet(ld, map); 597 printf("LD %x: span_depth=%x\n", ld, raid->spanDepth); 598 for (span = 0; span < raid->spanDepth; span++) 599 printf("Span=%x, number of quads=%x\n", span, 600 map->raidMap.ldSpanMap[ld].spanBlock[span]. 601 block_span_info.noElements); 602 for (element = 0; element < MAX_QUAD_DEPTH; element++) { 603 span_set = &(ldSpanInfo[ld].span_set[element]); 604 if (span_set->span_row_data_width == 0) 605 break; 606 607 printf("Span Set %x: width=%x, diff=%x\n", element, 608 (unsigned int)span_set->span_row_data_width, 609 (unsigned int)span_set->diff); 610 printf("logical LBA start=0x%08lx, end=0x%08lx\n", 611 (long unsigned int)span_set->log_start_lba, 612 (long unsigned int)span_set->log_end_lba); 613 printf("span row start=0x%08lx, end=0x%08lx\n", 614 (long unsigned int)span_set->span_row_start, 615 (long unsigned int)span_set->span_row_end); 616 printf("data row start=0x%08lx, end=0x%08lx\n", 617 (long unsigned int)span_set->data_row_start, 618 (long unsigned int)span_set->data_row_end); 619 printf("data strip start=0x%08lx, end=0x%08lx\n", 620 (long unsigned int)span_set->data_strip_start, 621 (long unsigned int)span_set->data_strip_end); 622 623 for (span = 0; span < raid->spanDepth; span++) { 624 if (map->raidMap.ldSpanMap[ld].spanBlock[span]. 625 block_span_info.noElements >= element + 1) { 626 quad = &map->raidMap.ldSpanMap[ld]. 627 spanBlock[span].block_span_info. 628 quad[element]; 629 printf("Span=%x, Quad=%x, diff=%x\n", span, 630 element, quad->diff); 631 printf("offset_in_span=0x%08lx\n", 632 (long unsigned int)quad->offsetInSpan); 633 printf("logical start=0x%08lx, end=0x%08lx\n", 634 (long unsigned int)quad->logStart, 635 (long unsigned int)quad->logEnd); 636 } 637 } 638 } 639 } 640 return 0; 641 } 642 643 #endif 644 /* 645 * 646 * This routine calculates the Span block for given row using spanset. 647 * 648 * Inputs : HBA instance 649 * ld: Logical drive number 650 * row: Row number 651 * map: LD map 652 * 653 * Outputs : span - Span number block 654 * - Absolute Block number in the physical disk 655 * div_error - Devide error code. 656 */ 657 658 u_int32_t 659 mr_spanset_get_span_block(struct mrsas_softc *sc, u_int32_t ld, u_int64_t row, 660 u_int64_t *span_blk, MR_DRV_RAID_MAP_ALL * map, int *div_error) 661 { 662 MR_LD_RAID *raid = MR_LdRaidGet(ld, map); 663 LD_SPAN_SET *span_set; 664 MR_QUAD_ELEMENT *quad; 665 u_int32_t span, info; 666 PLD_SPAN_INFO ldSpanInfo = sc->log_to_span; 667 668 for (info = 0; info < MAX_QUAD_DEPTH; info++) { 669 span_set = &(ldSpanInfo[ld].span_set[info]); 670 671 if (span_set->span_row_data_width == 0) 672 break; 673 if (row > span_set->data_row_end) 674 continue; 675 676 for (span = 0; span < raid->spanDepth; span++) 677 if (map->raidMap.ldSpanMap[ld].spanBlock[span]. 678 block_span_info.noElements >= info + 1) { 679 quad = &map->raidMap.ldSpanMap[ld]. 680 spanBlock[span]. 681 block_span_info.quad[info]; 682 if (quad->diff == 0) { 683 *div_error = 1; 684 return span; 685 } 686 if (quad->logStart <= row && 687 row <= quad->logEnd && 688 (mega_mod64(row - quad->logStart, 689 quad->diff)) == 0) { 690 if (span_blk != NULL) { 691 u_int64_t blk; 692 693 blk = mega_div64_32 694 ((row - quad->logStart), 695 quad->diff); 696 blk = (blk + quad->offsetInSpan) 697 << raid->stripeShift; 698 *span_blk = blk; 699 } 700 return span; 701 } 702 } 703 } 704 return SPAN_INVALID; 705 } 706 707 /* 708 * 709 * This routine calculates the row for given strip using spanset. 710 * 711 * Inputs : HBA instance 712 * ld: Logical drive number 713 * Strip: Strip 714 * map: LD map 715 * 716 * Outputs : row - row associated with strip 717 */ 718 719 static u_int64_t 720 get_row_from_strip(struct mrsas_softc *sc, 721 u_int32_t ld, u_int64_t strip, MR_DRV_RAID_MAP_ALL * map) 722 { 723 MR_LD_RAID *raid = MR_LdRaidGet(ld, map); 724 LD_SPAN_SET *span_set; 725 PLD_SPAN_INFO ldSpanInfo = sc->log_to_span; 726 u_int32_t info, strip_offset, span, span_offset; 727 u_int64_t span_set_Strip, span_set_Row; 728 729 for (info = 0; info < MAX_QUAD_DEPTH; info++) { 730 span_set = &(ldSpanInfo[ld].span_set[info]); 731 732 if (span_set->span_row_data_width == 0) 733 break; 734 if (strip > span_set->data_strip_end) 735 continue; 736 737 span_set_Strip = strip - span_set->data_strip_start; 738 strip_offset = mega_mod64(span_set_Strip, 739 span_set->span_row_data_width); 740 span_set_Row = mega_div64_32(span_set_Strip, 741 span_set->span_row_data_width) * span_set->diff; 742 for (span = 0, span_offset = 0; span < raid->spanDepth; span++) 743 if (map->raidMap.ldSpanMap[ld].spanBlock[span]. 744 block_span_info.noElements >= info + 1) { 745 if (strip_offset >= 746 span_set->strip_offset[span]) 747 span_offset++; 748 else 749 break; 750 } 751 mrsas_dprint(sc, MRSAS_PRL11, "AVAGO Debug : Strip 0x%llx, span_set_Strip 0x%llx, span_set_Row 0x%llx " 752 "data width 0x%llx span offset 0x%llx\n", (unsigned long long)strip, 753 (unsigned long long)span_set_Strip, 754 (unsigned long long)span_set_Row, 755 (unsigned long long)span_set->span_row_data_width, (unsigned long long)span_offset); 756 mrsas_dprint(sc, MRSAS_PRL11, "AVAGO Debug : For strip 0x%llx row is 0x%llx\n", (unsigned long long)strip, 757 (unsigned long long)span_set->data_row_start + 758 (unsigned long long)span_set_Row + (span_offset - 1)); 759 return (span_set->data_row_start + span_set_Row + (span_offset - 1)); 760 } 761 return -1LLU; 762 } 763 764 /* 765 * 766 * This routine calculates the Start Strip for given row using spanset. 767 * 768 * Inputs: HBA instance 769 * ld: Logical drive number 770 * row: Row number 771 * map: LD map 772 * 773 * Outputs : Strip - Start strip associated with row 774 */ 775 776 static u_int64_t 777 get_strip_from_row(struct mrsas_softc *sc, 778 u_int32_t ld, u_int64_t row, MR_DRV_RAID_MAP_ALL * map) 779 { 780 MR_LD_RAID *raid = MR_LdRaidGet(ld, map); 781 LD_SPAN_SET *span_set; 782 MR_QUAD_ELEMENT *quad; 783 PLD_SPAN_INFO ldSpanInfo = sc->log_to_span; 784 u_int32_t span, info; 785 u_int64_t strip; 786 787 for (info = 0; info < MAX_QUAD_DEPTH; info++) { 788 span_set = &(ldSpanInfo[ld].span_set[info]); 789 790 if (span_set->span_row_data_width == 0) 791 break; 792 if (row > span_set->data_row_end) 793 continue; 794 795 for (span = 0; span < raid->spanDepth; span++) 796 if (map->raidMap.ldSpanMap[ld].spanBlock[span]. 797 block_span_info.noElements >= info + 1) { 798 quad = &map->raidMap.ldSpanMap[ld]. 799 spanBlock[span].block_span_info.quad[info]; 800 if (quad->logStart <= row && 801 row <= quad->logEnd && 802 mega_mod64((row - quad->logStart), 803 quad->diff) == 0) { 804 strip = mega_div64_32 805 (((row - span_set->data_row_start) 806 - quad->logStart), 807 quad->diff); 808 strip *= span_set->span_row_data_width; 809 strip += span_set->data_strip_start; 810 strip += span_set->strip_offset[span]; 811 return strip; 812 } 813 } 814 } 815 mrsas_dprint(sc, MRSAS_PRL11, "AVAGO Debug - get_strip_from_row: returns invalid " 816 "strip for ld=%x, row=%lx\n", ld, (long unsigned int)row); 817 return -1; 818 } 819 820 /* 821 * ***************************************************************************** 822 * 823 * 824 * This routine calculates the Physical Arm for given strip using spanset. 825 * 826 * Inputs : HBA instance 827 * Logical drive number 828 * Strip 829 * LD map 830 * 831 * Outputs : Phys Arm - Phys Arm associated with strip 832 */ 833 834 static u_int32_t 835 get_arm_from_strip(struct mrsas_softc *sc, 836 u_int32_t ld, u_int64_t strip, MR_DRV_RAID_MAP_ALL * map) 837 { 838 MR_LD_RAID *raid = MR_LdRaidGet(ld, map); 839 LD_SPAN_SET *span_set; 840 PLD_SPAN_INFO ldSpanInfo = sc->log_to_span; 841 u_int32_t info, strip_offset, span, span_offset; 842 843 for (info = 0; info < MAX_QUAD_DEPTH; info++) { 844 span_set = &(ldSpanInfo[ld].span_set[info]); 845 846 if (span_set->span_row_data_width == 0) 847 break; 848 if (strip > span_set->data_strip_end) 849 continue; 850 851 strip_offset = (u_int32_t)mega_mod64 852 ((strip - span_set->data_strip_start), 853 span_set->span_row_data_width); 854 855 for (span = 0, span_offset = 0; span < raid->spanDepth; span++) 856 if (map->raidMap.ldSpanMap[ld].spanBlock[span]. 857 block_span_info.noElements >= info + 1) { 858 if (strip_offset >= span_set->strip_offset[span]) 859 span_offset = span_set->strip_offset[span]; 860 else 861 break; 862 } 863 mrsas_dprint(sc, MRSAS_PRL11, "AVAGO PRL11: get_arm_from_strip: " 864 "for ld=0x%x strip=0x%lx arm is 0x%x\n", ld, 865 (long unsigned int)strip, (strip_offset - span_offset)); 866 return (strip_offset - span_offset); 867 } 868 869 mrsas_dprint(sc, MRSAS_PRL11, "AVAGO Debug: - get_arm_from_strip: returns invalid arm" 870 " for ld=%x strip=%lx\n", ld, (long unsigned int)strip); 871 872 return -1; 873 } 874 875 /* This Function will return Phys arm */ 876 u_int8_t 877 get_arm(struct mrsas_softc *sc, u_int32_t ld, u_int8_t span, u_int64_t stripe, 878 MR_DRV_RAID_MAP_ALL * map) 879 { 880 MR_LD_RAID *raid = MR_LdRaidGet(ld, map); 881 882 /* Need to check correct default value */ 883 u_int32_t arm = 0; 884 885 switch (raid->level) { 886 case 0: 887 case 5: 888 case 6: 889 arm = mega_mod64(stripe, SPAN_ROW_SIZE(map, ld, span)); 890 break; 891 case 1: 892 /* start with logical arm */ 893 arm = get_arm_from_strip(sc, ld, stripe, map); 894 arm *= 2; 895 break; 896 } 897 898 return arm; 899 } 900 901 /* 902 * 903 * This routine calculates the arm, span and block for the specified stripe and 904 * reference in stripe using spanset 905 * 906 * Inputs : 907 * sc - HBA instance 908 * ld - Logical drive number 909 * stripRow: Stripe number 910 * stripRef: Reference in stripe 911 * 912 * Outputs : span - Span number block - Absolute Block 913 * number in the physical disk 914 */ 915 static u_int8_t 916 mr_spanset_get_phy_params(struct mrsas_softc *sc, u_int32_t ld, u_int64_t stripRow, 917 u_int16_t stripRef, struct IO_REQUEST_INFO *io_info, 918 RAID_CONTEXT * pRAID_Context, MR_DRV_RAID_MAP_ALL * map) 919 { 920 MR_LD_RAID *raid = MR_LdRaidGet(ld, map); 921 u_int32_t pd, arRef, r1_alt_pd; 922 u_int8_t physArm, span; 923 u_int64_t row; 924 u_int8_t retval = TRUE; 925 u_int64_t *pdBlock = &io_info->pdBlock; 926 u_int16_t *pDevHandle = &io_info->devHandle; 927 u_int8_t *pPdInterface = &io_info->pdInterface; 928 929 u_int32_t logArm, rowMod, armQ, arm; 930 931 /* Get row and span from io_info for Uneven Span IO. */ 932 row = io_info->start_row; 933 span = io_info->start_span; 934 935 if (raid->level == 6) { 936 logArm = get_arm_from_strip(sc, ld, stripRow, map); 937 rowMod = mega_mod64(row, SPAN_ROW_SIZE(map, ld, span)); 938 armQ = SPAN_ROW_SIZE(map, ld, span) - 1 - rowMod; 939 arm = armQ + 1 + logArm; 940 if (arm >= SPAN_ROW_SIZE(map, ld, span)) 941 arm -= SPAN_ROW_SIZE(map, ld, span); 942 physArm = (u_int8_t)arm; 943 } else 944 /* Calculate the arm */ 945 physArm = get_arm(sc, ld, span, stripRow, map); 946 947 arRef = MR_LdSpanArrayGet(ld, span, map); 948 pd = MR_ArPdGet(arRef, physArm, map); 949 950 if (pd != MR_PD_INVALID) { 951 *pDevHandle = MR_PdDevHandleGet(pd, map); 952 *pPdInterface = MR_PdInterfaceTypeGet(pd, map); 953 /* get second pd also for raid 1/10 fast path writes */ 954 if ((raid->level == 1) && !io_info->isRead) { 955 r1_alt_pd = MR_ArPdGet(arRef, physArm + 1, map); 956 if (r1_alt_pd != MR_PD_INVALID) 957 io_info->r1_alt_dev_handle = MR_PdDevHandleGet(r1_alt_pd, map); 958 } 959 } else { 960 *pDevHandle = MR_DEVHANDLE_INVALID; 961 if ((raid->level >= 5) && ((sc->device_id == MRSAS_TBOLT) || 962 (sc->mrsas_gen3_ctrl && 963 raid->regTypeReqOnRead != REGION_TYPE_UNUSED))) 964 pRAID_Context->regLockFlags = REGION_TYPE_EXCLUSIVE; 965 else if (raid->level == 1) { 966 pd = MR_ArPdGet(arRef, physArm + 1, map); 967 if (pd != MR_PD_INVALID) { 968 *pDevHandle = MR_PdDevHandleGet(pd, map); 969 *pPdInterface = MR_PdInterfaceTypeGet(pd, map); 970 } 971 } 972 } 973 974 *pdBlock += stripRef + MR_LdSpanPtrGet(ld, span, map)->startBlk; 975 if (sc->is_ventura || sc->is_aero) { 976 ((RAID_CONTEXT_G35 *) pRAID_Context)->spanArm = 977 (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm; 978 io_info->span_arm = (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm; 979 } else { 980 pRAID_Context->spanArm = (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm; 981 io_info->span_arm = pRAID_Context->spanArm; 982 } 983 return retval; 984 } 985 986 /* 987 * MR_BuildRaidContext: Set up Fast path RAID context 988 * 989 * This function will initiate command processing. The start/end row and strip 990 * information is calculated then the lock is acquired. This function will 991 * return 0 if region lock was acquired OR return num strips. 992 */ 993 u_int8_t 994 MR_BuildRaidContext(struct mrsas_softc *sc, struct IO_REQUEST_INFO *io_info, 995 RAID_CONTEXT * pRAID_Context, MR_DRV_RAID_MAP_ALL * map) 996 { 997 MR_LD_RAID *raid; 998 u_int32_t ld, stripSize, stripe_mask; 999 u_int64_t endLba, endStrip, endRow, start_row, start_strip; 1000 REGION_KEY regStart; 1001 REGION_LEN regSize; 1002 u_int8_t num_strips, numRows; 1003 u_int16_t ref_in_start_stripe, ref_in_end_stripe; 1004 u_int64_t ldStartBlock; 1005 u_int32_t numBlocks, ldTgtId; 1006 u_int8_t isRead, stripIdx; 1007 u_int8_t retval = 0; 1008 u_int8_t startlba_span = SPAN_INVALID; 1009 u_int64_t *pdBlock = &io_info->pdBlock; 1010 int error_code = 0; 1011 1012 ldStartBlock = io_info->ldStartBlock; 1013 numBlocks = io_info->numBlocks; 1014 ldTgtId = io_info->ldTgtId; 1015 isRead = io_info->isRead; 1016 1017 io_info->IoforUnevenSpan = 0; 1018 io_info->start_span = SPAN_INVALID; 1019 1020 ld = MR_TargetIdToLdGet(ldTgtId, map); 1021 raid = MR_LdRaidGet(ld, map); 1022 1023 /* check read ahead bit */ 1024 io_info->raCapable = raid->capability.raCapable; 1025 1026 if (raid->rowDataSize == 0) { 1027 if (MR_LdSpanPtrGet(ld, 0, map)->spanRowDataSize == 0) 1028 return FALSE; 1029 else if (sc->UnevenSpanSupport) { 1030 io_info->IoforUnevenSpan = 1; 1031 } else { 1032 mrsas_dprint(sc, MRSAS_PRL11, "AVAGO Debug: raid->rowDataSize is 0, but has SPAN[0] rowDataSize = 0x%0x," 1033 " but there is _NO_ UnevenSpanSupport\n", 1034 MR_LdSpanPtrGet(ld, 0, map)->spanRowDataSize); 1035 return FALSE; 1036 } 1037 } 1038 stripSize = 1 << raid->stripeShift; 1039 stripe_mask = stripSize - 1; 1040 /* 1041 * calculate starting row and stripe, and number of strips and rows 1042 */ 1043 start_strip = ldStartBlock >> raid->stripeShift; 1044 ref_in_start_stripe = (u_int16_t)(ldStartBlock & stripe_mask); 1045 endLba = ldStartBlock + numBlocks - 1; 1046 ref_in_end_stripe = (u_int16_t)(endLba & stripe_mask); 1047 endStrip = endLba >> raid->stripeShift; 1048 num_strips = (u_int8_t)(endStrip - start_strip + 1); /* End strip */ 1049 if (io_info->IoforUnevenSpan) { 1050 start_row = get_row_from_strip(sc, ld, start_strip, map); 1051 endRow = get_row_from_strip(sc, ld, endStrip, map); 1052 if (raid->spanDepth == 1) { 1053 startlba_span = 0; 1054 *pdBlock = start_row << raid->stripeShift; 1055 } else { 1056 startlba_span = (u_int8_t)mr_spanset_get_span_block(sc, ld, start_row, 1057 pdBlock, map, &error_code); 1058 if (error_code == 1) { 1059 mrsas_dprint(sc, MRSAS_PRL11, "AVAGO Debug: return from %s %d. Send IO w/o region lock.\n", 1060 __func__, __LINE__); 1061 return FALSE; 1062 } 1063 } 1064 if (startlba_span == SPAN_INVALID) { 1065 mrsas_dprint(sc, MRSAS_PRL11, "AVAGO Debug: return from %s %d for row 0x%llx," 1066 "start strip %llx endSrip %llx\n", __func__, 1067 __LINE__, (unsigned long long)start_row, 1068 (unsigned long long)start_strip, 1069 (unsigned long long)endStrip); 1070 return FALSE; 1071 } 1072 io_info->start_span = startlba_span; 1073 io_info->start_row = start_row; 1074 mrsas_dprint(sc, MRSAS_PRL11, "AVAGO Debug: Check Span number from %s %d for row 0x%llx, " 1075 " start strip 0x%llx endSrip 0x%llx span 0x%x\n", 1076 __func__, __LINE__, (unsigned long long)start_row, 1077 (unsigned long long)start_strip, 1078 (unsigned long long)endStrip, startlba_span); 1079 mrsas_dprint(sc, MRSAS_PRL11, "AVAGO Debug : 1. start_row 0x%llx endRow 0x%llx Start span 0x%x\n", 1080 (unsigned long long)start_row, (unsigned long long)endRow, startlba_span); 1081 } else { 1082 start_row = mega_div64_32(start_strip, raid->rowDataSize); 1083 endRow = mega_div64_32(endStrip, raid->rowDataSize); 1084 } 1085 1086 numRows = (u_int8_t)(endRow - start_row + 1); /* get the row count */ 1087 1088 /* 1089 * Calculate region info. (Assume region at start of first row, and 1090 * assume this IO needs the full row - will adjust if not true.) 1091 */ 1092 regStart = start_row << raid->stripeShift; 1093 regSize = stripSize; 1094 1095 /* Check if we can send this I/O via FastPath */ 1096 if (raid->capability.fpCapable) { 1097 if (isRead) 1098 io_info->fpOkForIo = (raid->capability.fpReadCapable && 1099 ((num_strips == 1) || 1100 raid->capability.fpReadAcrossStripe)); 1101 else 1102 io_info->fpOkForIo = (raid->capability.fpWriteCapable && 1103 ((num_strips == 1) || 1104 raid->capability.fpWriteAcrossStripe)); 1105 } else 1106 io_info->fpOkForIo = FALSE; 1107 1108 if (numRows == 1) { 1109 if (num_strips == 1) { 1110 regStart += ref_in_start_stripe; 1111 regSize = numBlocks; 1112 } 1113 } else if (io_info->IoforUnevenSpan == 0) { 1114 /* 1115 * For Even span region lock optimization. If the start strip 1116 * is the last in the start row 1117 */ 1118 if (start_strip == (start_row + 1) * raid->rowDataSize - 1) { 1119 regStart += ref_in_start_stripe; 1120 /* 1121 * initialize count to sectors from startRef to end 1122 * of strip 1123 */ 1124 regSize = stripSize - ref_in_start_stripe; 1125 } 1126 /* add complete rows in the middle of the transfer */ 1127 if (numRows > 2) 1128 regSize += (numRows - 2) << raid->stripeShift; 1129 1130 /* if IO ends within first strip of last row */ 1131 if (endStrip == endRow * raid->rowDataSize) 1132 regSize += ref_in_end_stripe + 1; 1133 else 1134 regSize += stripSize; 1135 } else { 1136 if (start_strip == (get_strip_from_row(sc, ld, start_row, map) + 1137 SPAN_ROW_DATA_SIZE(map, ld, startlba_span) - 1)) { 1138 regStart += ref_in_start_stripe; 1139 /* 1140 * initialize count to sectors from startRef to end 1141 * of strip 1142 */ 1143 regSize = stripSize - ref_in_start_stripe; 1144 } 1145 /* add complete rows in the middle of the transfer */ 1146 if (numRows > 2) 1147 regSize += (numRows - 2) << raid->stripeShift; 1148 1149 /* if IO ends within first strip of last row */ 1150 if (endStrip == get_strip_from_row(sc, ld, endRow, map)) 1151 regSize += ref_in_end_stripe + 1; 1152 else 1153 regSize += stripSize; 1154 } 1155 pRAID_Context->timeoutValue = map->raidMap.fpPdIoTimeoutSec; 1156 if (sc->mrsas_gen3_ctrl) 1157 pRAID_Context->regLockFlags = (isRead) ? raid->regTypeReqOnRead : raid->regTypeReqOnWrite; 1158 else if (sc->device_id == MRSAS_TBOLT) 1159 pRAID_Context->regLockFlags = (isRead) ? REGION_TYPE_SHARED_READ : raid->regTypeReqOnWrite; 1160 pRAID_Context->VirtualDiskTgtId = raid->targetId; 1161 pRAID_Context->regLockRowLBA = regStart; 1162 pRAID_Context->regLockLength = regSize; 1163 pRAID_Context->configSeqNum = raid->seqNum; 1164 1165 /* 1166 * Get Phy Params only if FP capable, or else leave it to MR firmware 1167 * to do the calculation. 1168 */ 1169 if (io_info->fpOkForIo) { 1170 retval = io_info->IoforUnevenSpan ? 1171 mr_spanset_get_phy_params(sc, ld, start_strip, 1172 ref_in_start_stripe, io_info, pRAID_Context, map) : 1173 MR_GetPhyParams(sc, ld, start_strip, 1174 ref_in_start_stripe, io_info, pRAID_Context, map); 1175 /* If IO on an invalid Pd, then FP is not possible */ 1176 if (io_info->devHandle == MR_DEVHANDLE_INVALID) 1177 io_info->fpOkForIo = FALSE; 1178 /* 1179 * if FP possible, set the SLUD bit in regLockFlags for 1180 * ventura 1181 */ 1182 else if ((sc->is_ventura || sc->is_aero) && !isRead && 1183 (raid->writeMode == MR_RL_WRITE_BACK_MODE) && (raid->level <= 1) && 1184 raid->capability.fpCacheBypassCapable) { 1185 ((RAID_CONTEXT_G35 *) pRAID_Context)->routingFlags.bits.sld = 1; 1186 } 1187 1188 return retval; 1189 } else if (isRead) { 1190 for (stripIdx = 0; stripIdx < num_strips; stripIdx++) { 1191 retval = io_info->IoforUnevenSpan ? 1192 mr_spanset_get_phy_params(sc, ld, start_strip + stripIdx, 1193 ref_in_start_stripe, io_info, pRAID_Context, map) : 1194 MR_GetPhyParams(sc, ld, start_strip + stripIdx, 1195 ref_in_start_stripe, io_info, pRAID_Context, map); 1196 if (!retval) 1197 return TRUE; 1198 } 1199 } 1200 #if SPAN_DEBUG 1201 /* Just for testing what arm we get for strip. */ 1202 get_arm_from_strip(sc, ld, start_strip, map); 1203 #endif 1204 return TRUE; 1205 } 1206 1207 /* 1208 * 1209 * This routine pepare spanset info from Valid Raid map and store it into local 1210 * copy of ldSpanInfo per instance data structure. 1211 * 1212 * Inputs : LD map 1213 * ldSpanInfo per HBA instance 1214 * 1215 */ 1216 void 1217 mr_update_span_set(MR_DRV_RAID_MAP_ALL * map, PLD_SPAN_INFO ldSpanInfo) 1218 { 1219 u_int8_t span, count; 1220 u_int32_t element, span_row_width; 1221 u_int64_t span_row; 1222 MR_LD_RAID *raid; 1223 LD_SPAN_SET *span_set, *span_set_prev; 1224 MR_QUAD_ELEMENT *quad; 1225 int ldCount; 1226 u_int16_t ld; 1227 1228 for (ldCount = 0; ldCount < MAX_LOGICAL_DRIVES; ldCount++) { 1229 ld = MR_TargetIdToLdGet(ldCount, map); 1230 if (ld >= MAX_LOGICAL_DRIVES) 1231 continue; 1232 raid = MR_LdRaidGet(ld, map); 1233 for (element = 0; element < MAX_QUAD_DEPTH; element++) { 1234 for (span = 0; span < raid->spanDepth; span++) { 1235 if (map->raidMap.ldSpanMap[ld].spanBlock[span]. 1236 block_span_info.noElements < element + 1) 1237 continue; 1238 /* TO-DO */ 1239 span_set = &(ldSpanInfo[ld].span_set[element]); 1240 quad = &map->raidMap.ldSpanMap[ld]. 1241 spanBlock[span].block_span_info.quad[element]; 1242 1243 span_set->diff = quad->diff; 1244 1245 for (count = 0, span_row_width = 0; 1246 count < raid->spanDepth; count++) { 1247 if (map->raidMap.ldSpanMap[ld].spanBlock[count]. 1248 block_span_info.noElements >= element + 1) { 1249 span_set->strip_offset[count] = span_row_width; 1250 span_row_width += 1251 MR_LdSpanPtrGet(ld, count, map)->spanRowDataSize; 1252 #if SPAN_DEBUG 1253 printf("AVAGO Debug span %x rowDataSize %x\n", count, 1254 MR_LdSpanPtrGet(ld, count, map)->spanRowDataSize); 1255 #endif 1256 } 1257 } 1258 1259 span_set->span_row_data_width = span_row_width; 1260 span_row = mega_div64_32(((quad->logEnd - 1261 quad->logStart) + quad->diff), quad->diff); 1262 1263 if (element == 0) { 1264 span_set->log_start_lba = 0; 1265 span_set->log_end_lba = 1266 ((span_row << raid->stripeShift) * span_row_width) - 1; 1267 1268 span_set->span_row_start = 0; 1269 span_set->span_row_end = span_row - 1; 1270 1271 span_set->data_strip_start = 0; 1272 span_set->data_strip_end = (span_row * span_row_width) - 1; 1273 1274 span_set->data_row_start = 0; 1275 span_set->data_row_end = (span_row * quad->diff) - 1; 1276 } else { 1277 span_set_prev = &(ldSpanInfo[ld].span_set[element - 1]); 1278 span_set->log_start_lba = span_set_prev->log_end_lba + 1; 1279 span_set->log_end_lba = span_set->log_start_lba + 1280 ((span_row << raid->stripeShift) * span_row_width) - 1; 1281 1282 span_set->span_row_start = span_set_prev->span_row_end + 1; 1283 span_set->span_row_end = 1284 span_set->span_row_start + span_row - 1; 1285 1286 span_set->data_strip_start = 1287 span_set_prev->data_strip_end + 1; 1288 span_set->data_strip_end = span_set->data_strip_start + 1289 (span_row * span_row_width) - 1; 1290 1291 span_set->data_row_start = span_set_prev->data_row_end + 1; 1292 span_set->data_row_end = span_set->data_row_start + 1293 (span_row * quad->diff) - 1; 1294 } 1295 break; 1296 } 1297 if (span == raid->spanDepth) 1298 break; /* no quads remain */ 1299 } 1300 } 1301 #if SPAN_DEBUG 1302 getSpanInfo(map, ldSpanInfo); /* to get span set info */ 1303 #endif 1304 } 1305 1306 /* 1307 * mrsas_update_load_balance_params: Update load balance parmas 1308 * Inputs: 1309 * sc - driver softc instance 1310 * drv_map - driver RAID map 1311 * lbInfo - Load balance info 1312 * 1313 * This function updates the load balance parameters for the LD config of a two 1314 * drive optimal RAID-1. 1315 */ 1316 void 1317 mrsas_update_load_balance_params(struct mrsas_softc *sc, 1318 MR_DRV_RAID_MAP_ALL * drv_map, PLD_LOAD_BALANCE_INFO lbInfo) 1319 { 1320 int ldCount; 1321 u_int16_t ld; 1322 MR_LD_RAID *raid; 1323 1324 if (sc->lb_pending_cmds > 128 || sc->lb_pending_cmds < 1) 1325 sc->lb_pending_cmds = LB_PENDING_CMDS_DEFAULT; 1326 1327 for (ldCount = 0; ldCount < MAX_LOGICAL_DRIVES_EXT; ldCount++) { 1328 ld = MR_TargetIdToLdGet(ldCount, drv_map); 1329 if (ld >= MAX_LOGICAL_DRIVES_EXT) { 1330 lbInfo[ldCount].loadBalanceFlag = 0; 1331 continue; 1332 } 1333 raid = MR_LdRaidGet(ld, drv_map); 1334 if ((raid->level != 1) || 1335 (raid->ldState != MR_LD_STATE_OPTIMAL)) { 1336 lbInfo[ldCount].loadBalanceFlag = 0; 1337 continue; 1338 } 1339 lbInfo[ldCount].loadBalanceFlag = 1; 1340 } 1341 } 1342 1343 /* 1344 * mrsas_set_pd_lba: Sets PD LBA 1345 * input: io_request pointer 1346 * CDB length 1347 * io_info pointer 1348 * Pointer to CCB 1349 * Local RAID map pointer 1350 * Start block of IO Block Size 1351 * 1352 * Used to set the PD logical block address in CDB for FP IOs. 1353 */ 1354 void 1355 mrsas_set_pd_lba(MRSAS_RAID_SCSI_IO_REQUEST * io_request, u_int8_t cdb_len, 1356 struct IO_REQUEST_INFO *io_info, union ccb *ccb, 1357 MR_DRV_RAID_MAP_ALL * local_map_ptr, u_int32_t ref_tag, 1358 u_int32_t ld_block_size) 1359 { 1360 MR_LD_RAID *raid; 1361 u_int32_t ld; 1362 u_int64_t start_blk = io_info->pdBlock; 1363 u_int8_t *cdb = io_request->CDB.CDB32; 1364 u_int32_t num_blocks = io_info->numBlocks; 1365 u_int8_t opcode = 0, flagvals = 0, groupnum = 0, control = 0; 1366 struct ccb_hdr *ccb_h = &(ccb->ccb_h); 1367 1368 /* Check if T10 PI (DIF) is enabled for this LD */ 1369 ld = MR_TargetIdToLdGet(io_info->ldTgtId, local_map_ptr); 1370 raid = MR_LdRaidGet(ld, local_map_ptr); 1371 if (raid->capability.ldPiMode == MR_PROT_INFO_TYPE_CONTROLLER) { 1372 memset(cdb, 0, sizeof(io_request->CDB.CDB32)); 1373 cdb[0] = MRSAS_SCSI_VARIABLE_LENGTH_CMD; 1374 cdb[7] = MRSAS_SCSI_ADDL_CDB_LEN; 1375 1376 if (ccb_h->flags == CAM_DIR_OUT) 1377 cdb[9] = MRSAS_SCSI_SERVICE_ACTION_READ32; 1378 else 1379 cdb[9] = MRSAS_SCSI_SERVICE_ACTION_WRITE32; 1380 cdb[10] = MRSAS_RD_WR_PROTECT_CHECK_ALL; 1381 1382 /* LBA */ 1383 cdb[12] = (u_int8_t)((start_blk >> 56) & 0xff); 1384 cdb[13] = (u_int8_t)((start_blk >> 48) & 0xff); 1385 cdb[14] = (u_int8_t)((start_blk >> 40) & 0xff); 1386 cdb[15] = (u_int8_t)((start_blk >> 32) & 0xff); 1387 cdb[16] = (u_int8_t)((start_blk >> 24) & 0xff); 1388 cdb[17] = (u_int8_t)((start_blk >> 16) & 0xff); 1389 cdb[18] = (u_int8_t)((start_blk >> 8) & 0xff); 1390 cdb[19] = (u_int8_t)(start_blk & 0xff); 1391 1392 /* Logical block reference tag */ 1393 io_request->CDB.EEDP32.PrimaryReferenceTag = swap32(ref_tag); 1394 io_request->CDB.EEDP32.PrimaryApplicationTagMask = 0xffff; 1395 io_request->IoFlags = 32; /* Specify 32-byte cdb */ 1396 1397 /* Transfer length */ 1398 cdb[28] = (u_int8_t)((num_blocks >> 24) & 0xff); 1399 cdb[29] = (u_int8_t)((num_blocks >> 16) & 0xff); 1400 cdb[30] = (u_int8_t)((num_blocks >> 8) & 0xff); 1401 cdb[31] = (u_int8_t)(num_blocks & 0xff); 1402 1403 /* set SCSI IO EEDP Flags */ 1404 if (ccb_h->flags == CAM_DIR_OUT) { 1405 io_request->EEDPFlags = 1406 MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG | 1407 MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG | 1408 MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP | 1409 MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG | 1410 MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD; 1411 } else { 1412 io_request->EEDPFlags = 1413 MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG | 1414 MPI2_SCSIIO_EEDPFLAGS_INSERT_OP; 1415 } 1416 io_request->Control |= (0x4 << 26); 1417 io_request->EEDPBlockSize = ld_block_size; 1418 } else { 1419 /* Some drives don't support 16/12 byte CDB's, convert to 10 */ 1420 if (((cdb_len == 12) || (cdb_len == 16)) && 1421 (start_blk <= 0xffffffff)) { 1422 if (cdb_len == 16) { 1423 opcode = cdb[0] == READ_16 ? READ_10 : WRITE_10; 1424 flagvals = cdb[1]; 1425 groupnum = cdb[14]; 1426 control = cdb[15]; 1427 } else { 1428 opcode = cdb[0] == READ_12 ? READ_10 : WRITE_10; 1429 flagvals = cdb[1]; 1430 groupnum = cdb[10]; 1431 control = cdb[11]; 1432 } 1433 1434 memset(cdb, 0, sizeof(io_request->CDB.CDB32)); 1435 1436 cdb[0] = opcode; 1437 cdb[1] = flagvals; 1438 cdb[6] = groupnum; 1439 cdb[9] = control; 1440 1441 /* Transfer length */ 1442 cdb[8] = (u_int8_t)(num_blocks & 0xff); 1443 cdb[7] = (u_int8_t)((num_blocks >> 8) & 0xff); 1444 1445 io_request->IoFlags = 10; /* Specify 10-byte cdb */ 1446 cdb_len = 10; 1447 } else if ((cdb_len < 16) && (start_blk > 0xffffffff)) { 1448 /* Convert to 16 byte CDB for large LBA's */ 1449 switch (cdb_len) { 1450 case 6: 1451 opcode = cdb[0] == READ_6 ? READ_16 : WRITE_16; 1452 control = cdb[5]; 1453 break; 1454 case 10: 1455 opcode = cdb[0] == READ_10 ? READ_16 : WRITE_16; 1456 flagvals = cdb[1]; 1457 groupnum = cdb[6]; 1458 control = cdb[9]; 1459 break; 1460 case 12: 1461 opcode = cdb[0] == READ_12 ? READ_16 : WRITE_16; 1462 flagvals = cdb[1]; 1463 groupnum = cdb[10]; 1464 control = cdb[11]; 1465 break; 1466 } 1467 1468 memset(cdb, 0, sizeof(io_request->CDB.CDB32)); 1469 1470 cdb[0] = opcode; 1471 cdb[1] = flagvals; 1472 cdb[14] = groupnum; 1473 cdb[15] = control; 1474 1475 /* Transfer length */ 1476 cdb[13] = (u_int8_t)(num_blocks & 0xff); 1477 cdb[12] = (u_int8_t)((num_blocks >> 8) & 0xff); 1478 cdb[11] = (u_int8_t)((num_blocks >> 16) & 0xff); 1479 cdb[10] = (u_int8_t)((num_blocks >> 24) & 0xff); 1480 1481 io_request->IoFlags = 16; /* Specify 16-byte cdb */ 1482 cdb_len = 16; 1483 } else if ((cdb_len == 6) && (start_blk > 0x1fffff)) { 1484 /* convert to 10 byte CDB */ 1485 opcode = cdb[0] == READ_6 ? READ_10 : WRITE_10; 1486 control = cdb[5]; 1487 1488 memset(cdb, 0, sizeof(io_request->CDB.CDB32)); 1489 cdb[0] = opcode; 1490 cdb[9] = control; 1491 1492 /* Set transfer length */ 1493 cdb[8] = (u_int8_t)(num_blocks & 0xff); 1494 cdb[7] = (u_int8_t)((num_blocks >> 8) & 0xff); 1495 1496 /* Specify 10-byte cdb */ 1497 cdb_len = 10; 1498 } 1499 /* Fall through normal case, just load LBA here */ 1500 u_int8_t val = cdb[1] & 0xE0; 1501 1502 switch (cdb_len) { 1503 case 6: 1504 cdb[3] = (u_int8_t)(start_blk & 0xff); 1505 cdb[2] = (u_int8_t)((start_blk >> 8) & 0xff); 1506 cdb[1] = val | ((u_int8_t)(start_blk >> 16) & 0x1f); 1507 break; 1508 case 10: 1509 cdb[5] = (u_int8_t)(start_blk & 0xff); 1510 cdb[4] = (u_int8_t)((start_blk >> 8) & 0xff); 1511 cdb[3] = (u_int8_t)((start_blk >> 16) & 0xff); 1512 cdb[2] = (u_int8_t)((start_blk >> 24) & 0xff); 1513 break; 1514 case 16: 1515 cdb[9] = (u_int8_t)(start_blk & 0xff); 1516 cdb[8] = (u_int8_t)((start_blk >> 8) & 0xff); 1517 cdb[7] = (u_int8_t)((start_blk >> 16) & 0xff); 1518 cdb[6] = (u_int8_t)((start_blk >> 24) & 0xff); 1519 cdb[5] = (u_int8_t)((start_blk >> 32) & 0xff); 1520 cdb[4] = (u_int8_t)((start_blk >> 40) & 0xff); 1521 cdb[3] = (u_int8_t)((start_blk >> 48) & 0xff); 1522 cdb[2] = (u_int8_t)((start_blk >> 56) & 0xff); 1523 break; 1524 } 1525 } 1526 } 1527 1528 /* 1529 * mrsas_get_best_arm_pd: Determine the best spindle arm 1530 * Inputs: 1531 * sc - HBA instance 1532 * lbInfo - Load balance info 1533 * io_info - IO request info 1534 * 1535 * This function determines and returns the best arm by looking at the 1536 * parameters of the last PD access. 1537 */ 1538 u_int8_t 1539 mrsas_get_best_arm_pd(struct mrsas_softc *sc, 1540 PLD_LOAD_BALANCE_INFO lbInfo, struct IO_REQUEST_INFO *io_info) 1541 { 1542 MR_LD_RAID *raid; 1543 MR_DRV_RAID_MAP_ALL *drv_map; 1544 u_int16_t pd1_devHandle; 1545 u_int16_t pend0, pend1, ld; 1546 u_int64_t diff0, diff1; 1547 u_int8_t bestArm, pd0, pd1, span, arm; 1548 u_int32_t arRef, span_row_size; 1549 1550 u_int64_t block = io_info->ldStartBlock; 1551 u_int32_t count = io_info->numBlocks; 1552 1553 span = ((io_info->span_arm & RAID_CTX_SPANARM_SPAN_MASK) 1554 >> RAID_CTX_SPANARM_SPAN_SHIFT); 1555 arm = (io_info->span_arm & RAID_CTX_SPANARM_ARM_MASK); 1556 1557 drv_map = sc->ld_drv_map[(sc->map_id & 1)]; 1558 ld = MR_TargetIdToLdGet(io_info->ldTgtId, drv_map); 1559 raid = MR_LdRaidGet(ld, drv_map); 1560 span_row_size = sc->UnevenSpanSupport ? 1561 SPAN_ROW_SIZE(drv_map, ld, span) : raid->rowSize; 1562 1563 arRef = MR_LdSpanArrayGet(ld, span, drv_map); 1564 pd0 = MR_ArPdGet(arRef, arm, drv_map); 1565 pd1 = MR_ArPdGet(arRef, (arm + 1) >= span_row_size ? 1566 (arm + 1 - span_row_size) : arm + 1, drv_map); 1567 1568 /* Get PD1 Dev Handle */ 1569 pd1_devHandle = MR_PdDevHandleGet(pd1, drv_map); 1570 if (pd1_devHandle == MR_DEVHANDLE_INVALID) { 1571 bestArm = arm; 1572 } else { 1573 /* get the pending cmds for the data and mirror arms */ 1574 pend0 = mrsas_atomic_read(&lbInfo->scsi_pending_cmds[pd0]); 1575 pend1 = mrsas_atomic_read(&lbInfo->scsi_pending_cmds[pd1]); 1576 1577 /* Determine the disk whose head is nearer to the req. block */ 1578 diff0 = ABS_DIFF(block, lbInfo->last_accessed_block[pd0]); 1579 diff1 = ABS_DIFF(block, lbInfo->last_accessed_block[pd1]); 1580 bestArm = (diff0 <= diff1 ? arm : arm ^ 1); 1581 1582 if ((bestArm == arm && pend0 > pend1 + sc->lb_pending_cmds) || 1583 (bestArm != arm && pend1 > pend0 + sc->lb_pending_cmds)) 1584 bestArm ^= 1; 1585 1586 /* Update the last accessed block on the correct pd */ 1587 io_info->span_arm = (span << RAID_CTX_SPANARM_SPAN_SHIFT) | bestArm; 1588 io_info->pd_after_lb = (bestArm == arm) ? pd0 : pd1; 1589 } 1590 1591 lbInfo->last_accessed_block[bestArm == arm ? pd0 : pd1] = block + count - 1; 1592 #if SPAN_DEBUG 1593 if (arm != bestArm) 1594 printf("AVAGO Debug R1 Load balance occur - span 0x%x arm 0x%x bestArm 0x%x " 1595 "io_info->span_arm 0x%x\n", 1596 span, arm, bestArm, io_info->span_arm); 1597 #endif 1598 1599 return io_info->pd_after_lb; 1600 } 1601 1602 /* 1603 * mrsas_get_updated_dev_handle: Get the update dev handle 1604 * Inputs: 1605 * sc - Adapter instance soft state 1606 * lbInfo - Load balance info 1607 * io_info - io_info pointer 1608 * 1609 * This function determines and returns the updated dev handle. 1610 */ 1611 u_int16_t 1612 mrsas_get_updated_dev_handle(struct mrsas_softc *sc, 1613 PLD_LOAD_BALANCE_INFO lbInfo, struct IO_REQUEST_INFO *io_info) 1614 { 1615 u_int8_t arm_pd; 1616 u_int16_t devHandle; 1617 MR_DRV_RAID_MAP_ALL *drv_map; 1618 1619 drv_map = sc->ld_drv_map[(sc->map_id & 1)]; 1620 1621 /* get best new arm */ 1622 arm_pd = mrsas_get_best_arm_pd(sc, lbInfo, io_info); 1623 devHandle = MR_PdDevHandleGet(arm_pd, drv_map); 1624 io_info->pdInterface = MR_PdInterfaceTypeGet(arm_pd, drv_map); 1625 mrsas_atomic_inc(&lbInfo->scsi_pending_cmds[arm_pd]); 1626 1627 return devHandle; 1628 } 1629 1630 /* 1631 * MR_GetPhyParams: Calculates arm, span, and block 1632 * Inputs: Adapter soft state 1633 * Logical drive number (LD) 1634 * Stripe number(stripRow) 1635 * Reference in stripe (stripRef) 1636 * 1637 * Outputs: Absolute Block number in the physical disk 1638 * 1639 * This routine calculates the arm, span and block for the specified stripe and 1640 * reference in stripe. 1641 */ 1642 u_int8_t 1643 MR_GetPhyParams(struct mrsas_softc *sc, u_int32_t ld, 1644 u_int64_t stripRow, 1645 u_int16_t stripRef, struct IO_REQUEST_INFO *io_info, 1646 RAID_CONTEXT * pRAID_Context, MR_DRV_RAID_MAP_ALL * map) 1647 { 1648 MR_LD_RAID *raid = MR_LdRaidGet(ld, map); 1649 u_int32_t pd, arRef, r1_alt_pd; 1650 u_int8_t physArm, span; 1651 u_int64_t row; 1652 u_int8_t retval = TRUE; 1653 int error_code = 0; 1654 u_int64_t *pdBlock = &io_info->pdBlock; 1655 u_int16_t *pDevHandle = &io_info->devHandle; 1656 u_int8_t *pPdInterface = &io_info->pdInterface; 1657 u_int32_t rowMod, armQ, arm, logArm; 1658 1659 row = mega_div64_32(stripRow, raid->rowDataSize); 1660 1661 if (raid->level == 6) { 1662 /* logical arm within row */ 1663 logArm = mega_mod64(stripRow, raid->rowDataSize); 1664 if (raid->rowSize == 0) 1665 return FALSE; 1666 rowMod = mega_mod64(row, raid->rowSize); /* get logical row mod */ 1667 armQ = raid->rowSize - 1 - rowMod; /* index of Q drive */ 1668 arm = armQ + 1 + logArm;/* data always logically follows Q */ 1669 if (arm >= raid->rowSize) /* handle wrap condition */ 1670 arm -= raid->rowSize; 1671 physArm = (u_int8_t)arm; 1672 } else { 1673 if (raid->modFactor == 0) 1674 return FALSE; 1675 physArm = MR_LdDataArmGet(ld, mega_mod64(stripRow, raid->modFactor), map); 1676 } 1677 1678 if (raid->spanDepth == 1) { 1679 span = 0; 1680 *pdBlock = row << raid->stripeShift; 1681 } else { 1682 span = (u_int8_t)MR_GetSpanBlock(ld, row, pdBlock, map, &error_code); 1683 if (error_code == 1) 1684 return FALSE; 1685 } 1686 1687 /* Get the array on which this span is present */ 1688 arRef = MR_LdSpanArrayGet(ld, span, map); 1689 1690 pd = MR_ArPdGet(arRef, physArm, map); /* Get the Pd. */ 1691 1692 if (pd != MR_PD_INVALID) { 1693 /* Get dev handle from Pd */ 1694 *pDevHandle = MR_PdDevHandleGet(pd, map); 1695 *pPdInterface = MR_PdInterfaceTypeGet(pd, map); 1696 /* get second pd also for raid 1/10 fast path writes */ 1697 if ((raid->level == 1) && !io_info->isRead) { 1698 r1_alt_pd = MR_ArPdGet(arRef, physArm + 1, map); 1699 if (r1_alt_pd != MR_PD_INVALID) 1700 io_info->r1_alt_dev_handle = MR_PdDevHandleGet(r1_alt_pd, map); 1701 } 1702 } else { 1703 *pDevHandle = MR_DEVHANDLE_INVALID; /* set dev handle as invalid. */ 1704 if ((raid->level >= 5) && ((sc->device_id == MRSAS_TBOLT) || 1705 (sc->mrsas_gen3_ctrl && 1706 raid->regTypeReqOnRead != REGION_TYPE_UNUSED))) 1707 pRAID_Context->regLockFlags = REGION_TYPE_EXCLUSIVE; 1708 else if (raid->level == 1) { 1709 /* Get Alternate Pd. */ 1710 pd = MR_ArPdGet(arRef, physArm + 1, map); 1711 if (pd != MR_PD_INVALID) { 1712 /* Get dev handle from Pd. */ 1713 *pDevHandle = MR_PdDevHandleGet(pd, map); 1714 *pPdInterface = MR_PdInterfaceTypeGet(pd, map); 1715 } 1716 } 1717 } 1718 1719 *pdBlock += stripRef + MR_LdSpanPtrGet(ld, span, map)->startBlk; 1720 if (sc->is_ventura || sc->is_aero) { 1721 ((RAID_CONTEXT_G35 *) pRAID_Context)->spanArm = 1722 (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm; 1723 io_info->span_arm = (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm; 1724 } else { 1725 pRAID_Context->spanArm = (span << RAID_CTX_SPANARM_SPAN_SHIFT) | physArm; 1726 io_info->span_arm = pRAID_Context->spanArm; 1727 } 1728 return retval; 1729 } 1730 1731 /* 1732 * MR_GetSpanBlock: Calculates span block 1733 * Inputs: LD 1734 * row PD 1735 * span block 1736 * RAID map pointer 1737 * 1738 * Outputs: Span number Error code 1739 * 1740 * This routine calculates the span from the span block info. 1741 */ 1742 u_int32_t 1743 MR_GetSpanBlock(u_int32_t ld, u_int64_t row, u_int64_t *span_blk, 1744 MR_DRV_RAID_MAP_ALL * map, int *div_error) 1745 { 1746 MR_SPAN_BLOCK_INFO *pSpanBlock = MR_LdSpanInfoGet(ld, map); 1747 MR_QUAD_ELEMENT *quad; 1748 MR_LD_RAID *raid = MR_LdRaidGet(ld, map); 1749 u_int32_t span, j; 1750 u_int64_t blk, debugBlk; 1751 1752 for (span = 0; span < raid->spanDepth; span++, pSpanBlock++) { 1753 for (j = 0; j < pSpanBlock->block_span_info.noElements; j++) { 1754 quad = &pSpanBlock->block_span_info.quad[j]; 1755 if (quad->diff == 0) { 1756 *div_error = 1; 1757 return span; 1758 } 1759 if (quad->logStart <= row && row <= quad->logEnd && 1760 (mega_mod64(row - quad->logStart, quad->diff)) == 0) { 1761 if (span_blk != NULL) { 1762 blk = mega_div64_32((row - quad->logStart), quad->diff); 1763 debugBlk = blk; 1764 blk = (blk + quad->offsetInSpan) << raid->stripeShift; 1765 *span_blk = blk; 1766 } 1767 return span; 1768 } 1769 } 1770 } 1771 return span; 1772 } 1773