1 /* 2 * Copyright (c) 2014, LSI Corp. All rights reserved. Authors: Marian Choy 3 * Support: freebsdraid@lsi.com 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 2. Redistributions 11 * in binary form must reproduce the above copyright notice, this list of 12 * conditions and the following disclaimer in the documentation and/or other 13 * materials provided with the distribution. 3. Neither the name of the 14 * <ORGANIZATION> nor the names of its contributors may be used to endorse or 15 * promote products derived from this software without specific prior written 16 * permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 * 30 * The views and conclusions contained in the software and documentation are 31 * those of the authors and should not be interpreted as representing 32 * official policies,either expressed or implied, of the FreeBSD Project. 33 * 34 * Send feedback to: <megaraidfbsd@lsi.com> Mail to: LSI Corporation, 1621 35 * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD 36 * 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #ifndef MRSAS_H 43 #define MRSAS_H 44 45 #include <sys/param.h> /* defines used in kernel.h */ 46 #include <sys/module.h> 47 #include <sys/systm.h> 48 #include <sys/proc.h> 49 #include <sys/errno.h> 50 #include <sys/kernel.h> /* types used in module initialization */ 51 #include <sys/conf.h> /* cdevsw struct */ 52 #include <sys/uio.h> /* uio struct */ 53 #include <sys/malloc.h> 54 #include <sys/bus.h> /* structs, prototypes for pci bus 55 * stuff */ 56 #include <sys/rman.h> 57 #include <sys/types.h> 58 #include <sys/lock.h> 59 #include <sys/sema.h> 60 #include <sys/sysctl.h> 61 #include <sys/stat.h> 62 #include <sys/taskqueue.h> 63 #include <sys/poll.h> 64 #include <sys/selinfo.h> 65 66 #include <machine/bus.h> 67 #include <machine/resource.h> 68 #include <machine/atomic.h> 69 70 #include <dev/pci/pcivar.h> /* For pci_get macros! */ 71 #include <dev/pci/pcireg.h> 72 73 74 #define IOCTL_SEMA_DESCRIPTION "mrsas semaphore for MFI pool" 75 76 /* 77 * Device IDs and PCI 78 */ 79 #define MRSAS_TBOLT 0x005b 80 #define MRSAS_INVADER 0x005d 81 #define MRSAS_FURY 0x005f 82 #define MRSAS_PCI_BAR0 0x10 83 #define MRSAS_PCI_BAR1 0x14 84 #define MRSAS_PCI_BAR2 0x1C 85 86 /* 87 * Firmware State Defines 88 */ 89 #define MRSAS_FWSTATE_MAXCMD_MASK 0x0000FFFF 90 #define MRSAS_FWSTATE_SGE_MASK 0x00FF0000 91 #define MRSAS_FW_STATE_CHNG_INTERRUPT 1 92 93 /* 94 * Message Frame Defines 95 */ 96 #define MRSAS_SENSE_LEN 96 97 #define MRSAS_FUSION_MAX_RESET_TRIES 3 98 99 /* 100 * Miscellaneous Defines 101 */ 102 #define BYTE_ALIGNMENT 1 103 #define MRSAS_MAX_NAME_LENGTH 32 104 #define MRSAS_VERSION "06.705.10.02-fbsd" 105 #define MRSAS_ULONG_MAX 0xFFFFFFFFFFFFFFFF 106 #define MRSAS_DEFAULT_TIMEOUT 0x14 /* Temporarily set */ 107 #define DONE 0 108 #define MRSAS_PAGE_SIZE 4096 109 #define MRSAS_RESET_NOTICE_INTERVAL 5 110 #define MRSAS_IO_TIMEOUT 180000 /* 180 second timeout */ 111 #define MRSAS_LDIO_QUEUE_DEPTH 70 /* 70 percent as default */ 112 #define THRESHOLD_REPLY_COUNT 50 113 #define MAX_MSIX_COUNT 128 114 115 /* 116 * Boolean types 117 */ 118 #if (__FreeBSD_version < 901000) 119 typedef enum _boolean { 120 false, true 121 } boolean; 122 123 #endif 124 enum err { 125 SUCCESS, FAIL 126 }; 127 128 MALLOC_DECLARE(M_MRSAS); 129 SYSCTL_DECL(_hw_mrsas); 130 131 #define MRSAS_INFO (1 << 0) 132 #define MRSAS_TRACE (1 << 1) 133 #define MRSAS_FAULT (1 << 2) 134 #define MRSAS_OCR (1 << 3) 135 #define MRSAS_TOUT MRSAS_OCR 136 #define MRSAS_AEN (1 << 4) 137 #define MRSAS_PRL11 (1 << 5) 138 139 #define mrsas_dprint(sc, level, msg, args...) \ 140 do { \ 141 if (sc->mrsas_debug & level) \ 142 device_printf(sc->mrsas_dev, msg, ##args); \ 143 } while (0) 144 145 146 /**************************************************************************** 147 * Raid Context structure which describes MegaRAID specific IO Paramenters 148 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 149 ****************************************************************************/ 150 151 typedef struct _RAID_CONTEXT { 152 u_int8_t Type:4; 153 u_int8_t nseg:4; 154 u_int8_t resvd0; 155 u_int16_t timeoutValue; 156 u_int8_t regLockFlags; 157 u_int8_t resvd1; 158 u_int16_t VirtualDiskTgtId; 159 u_int64_t regLockRowLBA; 160 u_int32_t regLockLength; 161 u_int16_t nextLMId; 162 u_int8_t exStatus; 163 u_int8_t status; 164 u_int8_t RAIDFlags; 165 u_int8_t numSGE; 166 u_int16_t configSeqNum; 167 u_int8_t spanArm; 168 u_int8_t resvd2[3]; 169 } RAID_CONTEXT; 170 171 172 /************************************************************************* 173 * MPI2 Defines 174 ************************************************************************/ 175 176 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 177 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 178 #define MPI2_VERSION_MAJOR (0x02) 179 #define MPI2_VERSION_MINOR (0x00) 180 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 181 #define MPI2_VERSION_MAJOR_SHIFT (8) 182 #define MPI2_VERSION_MINOR_MASK (0x00FF) 183 #define MPI2_VERSION_MINOR_SHIFT (0) 184 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 185 MPI2_VERSION_MINOR) 186 #define MPI2_HEADER_VERSION_UNIT (0x10) 187 #define MPI2_HEADER_VERSION_DEV (0x00) 188 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 189 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 190 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 191 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 192 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 193 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 194 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) 195 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) 196 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) 197 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) 198 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) 199 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) 200 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 201 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 202 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 203 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 204 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 205 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 206 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 207 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 208 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 209 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 210 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 211 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 212 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 213 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 214 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 215 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 216 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 217 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 218 219 #ifndef MPI2_POINTER 220 #define MPI2_POINTER * 221 #endif 222 223 224 /*************************************** 225 * MPI2 Structures 226 ***************************************/ 227 228 typedef struct _MPI25_IEEE_SGE_CHAIN64 { 229 u_int64_t Address; 230 u_int32_t Length; 231 u_int16_t Reserved1; 232 u_int8_t NextChainOffset; 233 u_int8_t Flags; 234 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, 235 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t; 236 237 typedef struct _MPI2_SGE_SIMPLE_UNION { 238 u_int32_t FlagsLength; 239 union { 240 u_int32_t Address32; 241 u_int64_t Address64; 242 } u; 243 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 244 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 245 246 typedef struct { 247 u_int8_t CDB[20]; /* 0x00 */ 248 u_int32_t PrimaryReferenceTag; /* 0x14 */ 249 u_int16_t PrimaryApplicationTag;/* 0x18 */ 250 u_int16_t PrimaryApplicationTagMask; /* 0x1A */ 251 u_int32_t TransferLength; /* 0x1C */ 252 } MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32, 253 Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t; 254 255 typedef struct _MPI2_SGE_CHAIN_UNION { 256 u_int16_t Length; 257 u_int8_t NextChainOffset; 258 u_int8_t Flags; 259 union { 260 u_int32_t Address32; 261 u_int64_t Address64; 262 } u; 263 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 264 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 265 266 typedef struct _MPI2_IEEE_SGE_SIMPLE32 { 267 u_int32_t Address; 268 u_int32_t FlagsLength; 269 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 270 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 271 typedef struct _MPI2_IEEE_SGE_SIMPLE64 { 272 u_int64_t Address; 273 u_int32_t Length; 274 u_int16_t Reserved1; 275 u_int8_t Reserved2; 276 u_int8_t Flags; 277 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 278 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 279 280 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 281 MPI2_IEEE_SGE_SIMPLE32 Simple32; 282 MPI2_IEEE_SGE_SIMPLE64 Simple64; 283 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 284 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 285 286 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 287 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 288 289 typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 290 MPI2_IEEE_SGE_CHAIN32 Chain32; 291 MPI2_IEEE_SGE_CHAIN64 Chain64; 292 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 293 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 294 295 typedef union _MPI2_SGE_IO_UNION { 296 MPI2_SGE_SIMPLE_UNION MpiSimple; 297 MPI2_SGE_CHAIN_UNION MpiChain; 298 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 299 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 300 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 301 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 302 303 typedef union { 304 u_int8_t CDB32[32]; 305 MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 306 MPI2_SGE_SIMPLE_UNION SGE; 307 } MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION, 308 Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t; 309 310 /* 311 * RAID SCSI IO Request Message Total SGE count will be one less than 312 * _MPI2_SCSI_IO_REQUEST 313 */ 314 typedef struct _MPI2_RAID_SCSI_IO_REQUEST { 315 u_int16_t DevHandle; /* 0x00 */ 316 u_int8_t ChainOffset; /* 0x02 */ 317 u_int8_t Function; /* 0x03 */ 318 u_int16_t Reserved1; /* 0x04 */ 319 u_int8_t Reserved2; /* 0x06 */ 320 u_int8_t MsgFlags; /* 0x07 */ 321 u_int8_t VP_ID; /* 0x08 */ 322 u_int8_t VF_ID; /* 0x09 */ 323 u_int16_t Reserved3; /* 0x0A */ 324 u_int32_t SenseBufferLowAddress;/* 0x0C */ 325 u_int16_t SGLFlags; /* 0x10 */ 326 u_int8_t SenseBufferLength; /* 0x12 */ 327 u_int8_t Reserved4; /* 0x13 */ 328 u_int8_t SGLOffset0; /* 0x14 */ 329 u_int8_t SGLOffset1; /* 0x15 */ 330 u_int8_t SGLOffset2; /* 0x16 */ 331 u_int8_t SGLOffset3; /* 0x17 */ 332 u_int32_t SkipCount; /* 0x18 */ 333 u_int32_t DataLength; /* 0x1C */ 334 u_int32_t BidirectionalDataLength; /* 0x20 */ 335 u_int16_t IoFlags; /* 0x24 */ 336 u_int16_t EEDPFlags; /* 0x26 */ 337 u_int32_t EEDPBlockSize; /* 0x28 */ 338 u_int32_t SecondaryReferenceTag;/* 0x2C */ 339 u_int16_t SecondaryApplicationTag; /* 0x30 */ 340 u_int16_t ApplicationTagTranslationMask; /* 0x32 */ 341 u_int8_t LUN[8]; /* 0x34 */ 342 u_int32_t Control; /* 0x3C */ 343 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 344 RAID_CONTEXT RaidContext; /* 0x60 */ 345 MPI2_SGE_IO_UNION SGL; /* 0x80 */ 346 } MRSAS_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MRSAS_RAID_SCSI_IO_REQUEST, 347 MRSASRaidSCSIIORequest_t, MPI2_POINTER pMRSASRaidSCSIIORequest_t; 348 349 /* 350 * MPT RAID MFA IO Descriptor. 351 */ 352 typedef struct _MRSAS_RAID_MFA_IO_DESCRIPTOR { 353 u_int32_t RequestFlags:8; 354 u_int32_t MessageAddress1:24; /* bits 31:8 */ 355 u_int32_t MessageAddress2; /* bits 61:32 */ 356 } MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR, *PMRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR; 357 358 /* Default Request Descriptor */ 359 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR { 360 u_int8_t RequestFlags; /* 0x00 */ 361 u_int8_t MSIxIndex; /* 0x01 */ 362 u_int16_t SMID; /* 0x02 */ 363 u_int16_t LMID; /* 0x04 */ 364 u_int16_t DescriptorTypeDependent; /* 0x06 */ 365 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 366 367 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 368 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 369 370 /* High Priority Request Descriptor */ 371 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { 372 u_int8_t RequestFlags; /* 0x00 */ 373 u_int8_t MSIxIndex; /* 0x01 */ 374 u_int16_t SMID; /* 0x02 */ 375 u_int16_t LMID; /* 0x04 */ 376 u_int16_t Reserved1; /* 0x06 */ 377 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 378 379 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 380 Mpi2HighPriorityRequestDescriptor_t, MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 381 382 /* SCSI IO Request Descriptor */ 383 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR { 384 u_int8_t RequestFlags; /* 0x00 */ 385 u_int8_t MSIxIndex; /* 0x01 */ 386 u_int16_t SMID; /* 0x02 */ 387 u_int16_t LMID; /* 0x04 */ 388 u_int16_t DevHandle; /* 0x06 */ 389 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 390 391 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 392 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 393 394 /* SCSI Target Request Descriptor */ 395 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { 396 u_int8_t RequestFlags; /* 0x00 */ 397 u_int8_t MSIxIndex; /* 0x01 */ 398 u_int16_t SMID; /* 0x02 */ 399 u_int16_t LMID; /* 0x04 */ 400 u_int16_t IoIndex; /* 0x06 */ 401 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 402 403 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 404 Mpi2SCSITargetRequestDescriptor_t, MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 405 406 /* RAID Accelerator Request Descriptor */ 407 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 408 u_int8_t RequestFlags; /* 0x00 */ 409 u_int8_t MSIxIndex; /* 0x01 */ 410 u_int16_t SMID; /* 0x02 */ 411 u_int16_t LMID; /* 0x04 */ 412 u_int16_t Reserved; /* 0x06 */ 413 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 414 415 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 416 Mpi2RAIDAcceleratorRequestDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 417 418 /* union of Request Descriptors */ 419 typedef union _MRSAS_REQUEST_DESCRIPTOR_UNION { 420 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 421 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 422 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 423 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 424 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 425 MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo; 426 union { 427 struct { 428 u_int32_t low; 429 u_int32_t high; 430 } u; 431 u_int64_t Words; 432 } addr; 433 } MRSAS_REQUEST_DESCRIPTOR_UNION; 434 435 /* Default Reply Descriptor */ 436 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR { 437 u_int8_t ReplyFlags; /* 0x00 */ 438 u_int8_t MSIxIndex; /* 0x01 */ 439 u_int16_t DescriptorTypeDependent1; /* 0x02 */ 440 u_int32_t DescriptorTypeDependent2; /* 0x04 */ 441 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 442 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 443 444 /* Address Reply Descriptor */ 445 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR { 446 u_int8_t ReplyFlags; /* 0x00 */ 447 u_int8_t MSIxIndex; /* 0x01 */ 448 u_int16_t SMID; /* 0x02 */ 449 u_int32_t ReplyFrameAddress; /* 0x04 */ 450 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 451 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 452 453 /* SCSI IO Success Reply Descriptor */ 454 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { 455 u_int8_t ReplyFlags; /* 0x00 */ 456 u_int8_t MSIxIndex; /* 0x01 */ 457 u_int16_t SMID; /* 0x02 */ 458 u_int16_t TaskTag; /* 0x04 */ 459 u_int16_t Reserved1; /* 0x06 */ 460 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 461 462 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 463 Mpi2SCSIIOSuccessReplyDescriptor_t, MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 464 465 /* TargetAssist Success Reply Descriptor */ 466 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { 467 u_int8_t ReplyFlags; /* 0x00 */ 468 u_int8_t MSIxIndex; /* 0x01 */ 469 u_int16_t SMID; /* 0x02 */ 470 u_int8_t SequenceNumber; /* 0x04 */ 471 u_int8_t Reserved1; /* 0x05 */ 472 u_int16_t IoIndex; /* 0x06 */ 473 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 474 475 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 476 Mpi2TargetAssistSuccessReplyDescriptor_t, MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 477 478 /* Target Command Buffer Reply Descriptor */ 479 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { 480 u_int8_t ReplyFlags; /* 0x00 */ 481 u_int8_t MSIxIndex; /* 0x01 */ 482 u_int8_t VP_ID; /* 0x02 */ 483 u_int8_t Flags; /* 0x03 */ 484 u_int16_t InitiatorDevHandle; /* 0x04 */ 485 u_int16_t IoIndex; /* 0x06 */ 486 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 487 488 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 489 Mpi2TargetCommandBufferReplyDescriptor_t, MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 490 491 /* RAID Accelerator Success Reply Descriptor */ 492 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 493 u_int8_t ReplyFlags; /* 0x00 */ 494 u_int8_t MSIxIndex; /* 0x01 */ 495 u_int16_t SMID; /* 0x02 */ 496 u_int32_t Reserved; /* 0x04 */ 497 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 498 499 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 500 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 501 502 /* union of Reply Descriptors */ 503 typedef union _MPI2_REPLY_DESCRIPTORS_UNION { 504 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 505 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 506 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 507 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 508 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 509 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 510 u_int64_t Words; 511 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 512 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 513 514 typedef union { 515 volatile unsigned int val; 516 unsigned int val_rdonly; 517 } mrsas_atomic_t; 518 519 #define mrsas_atomic_read(v) atomic_load_acq_int(&(v)->val) 520 #define mrsas_atomic_set(v,i) atomic_store_rel_int(&(v)->val, i) 521 #define mrsas_atomic_dec(v) atomic_fetchadd_int(&(v)->val, -1) 522 #define mrsas_atomic_inc(v) atomic_fetchadd_int(&(v)->val, 1) 523 524 /* IOCInit Request message */ 525 typedef struct _MPI2_IOC_INIT_REQUEST { 526 u_int8_t WhoInit; /* 0x00 */ 527 u_int8_t Reserved1; /* 0x01 */ 528 u_int8_t ChainOffset; /* 0x02 */ 529 u_int8_t Function; /* 0x03 */ 530 u_int16_t Reserved2; /* 0x04 */ 531 u_int8_t Reserved3; /* 0x06 */ 532 u_int8_t MsgFlags; /* 0x07 */ 533 u_int8_t VP_ID; /* 0x08 */ 534 u_int8_t VF_ID; /* 0x09 */ 535 u_int16_t Reserved4; /* 0x0A */ 536 u_int16_t MsgVersion; /* 0x0C */ 537 u_int16_t HeaderVersion; /* 0x0E */ 538 u_int32_t Reserved5; /* 0x10 */ 539 u_int16_t Reserved6; /* 0x14 */ 540 u_int8_t Reserved7; /* 0x16 */ 541 u_int8_t HostMSIxVectors; /* 0x17 */ 542 u_int16_t Reserved8; /* 0x18 */ 543 u_int16_t SystemRequestFrameSize; /* 0x1A */ 544 u_int16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 545 u_int16_t ReplyFreeQueueDepth; /* 0x1E */ 546 u_int32_t SenseBufferAddressHigh; /* 0x20 */ 547 u_int32_t SystemReplyAddressHigh; /* 0x24 */ 548 u_int64_t SystemRequestFrameBaseAddress; /* 0x28 */ 549 u_int64_t ReplyDescriptorPostQueueAddress; /* 0x30 */ 550 u_int64_t ReplyFreeQueueAddress;/* 0x38 */ 551 u_int64_t TimeStamp; /* 0x40 */ 552 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 553 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 554 555 /* 556 * MR private defines 557 */ 558 #define MR_PD_INVALID 0xFFFF 559 #define MAX_SPAN_DEPTH 8 560 #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH 561 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 562 #define MAX_ROW_SIZE 32 563 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 564 #define MAX_LOGICAL_DRIVES 64 565 #define MAX_LOGICAL_DRIVES_EXT 256 566 567 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 568 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 569 570 #define MAX_ARRAYS 128 571 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 572 573 #define MAX_ARRAYS_EXT 256 574 #define MAX_API_ARRAYS_EXT MAX_ARRAYS_EXT 575 576 #define MAX_PHYSICAL_DEVICES 256 577 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 578 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 579 580 581 #define MRSAS_MAX_PD_CHANNELS 1 582 #define MRSAS_MAX_LD_CHANNELS 1 583 #define MRSAS_MAX_DEV_PER_CHANNEL 256 584 #define MRSAS_DEFAULT_INIT_ID -1 585 #define MRSAS_MAX_LUN 8 586 #define MRSAS_DEFAULT_CMD_PER_LUN 256 587 #define MRSAS_MAX_PD (MRSAS_MAX_PD_CHANNELS * \ 588 MRSAS_MAX_DEV_PER_CHANNEL) 589 #define MRSAS_MAX_LD_IDS (MRSAS_MAX_LD_CHANNELS * \ 590 MRSAS_MAX_DEV_PER_CHANNEL) 591 592 593 #define VD_EXT_DEBUG 0 594 595 596 /******************************************************************* 597 * RAID map related structures 598 ********************************************************************/ 599 #pragma pack(1) 600 typedef struct _MR_DEV_HANDLE_INFO { 601 u_int16_t curDevHdl; 602 u_int8_t validHandles; 603 u_int8_t reserved; 604 u_int16_t devHandle[2]; 605 } MR_DEV_HANDLE_INFO; 606 607 #pragma pack() 608 609 typedef struct _MR_ARRAY_INFO { 610 u_int16_t pd[MAX_RAIDMAP_ROW_SIZE]; 611 } MR_ARRAY_INFO; 612 613 typedef struct _MR_QUAD_ELEMENT { 614 u_int64_t logStart; 615 u_int64_t logEnd; 616 u_int64_t offsetInSpan; 617 u_int32_t diff; 618 u_int32_t reserved1; 619 } MR_QUAD_ELEMENT; 620 621 typedef struct _MR_SPAN_INFO { 622 u_int32_t noElements; 623 u_int32_t reserved1; 624 MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; 625 } MR_SPAN_INFO; 626 627 typedef struct _MR_LD_SPAN_ { 628 u_int64_t startBlk; 629 u_int64_t numBlks; 630 u_int16_t arrayRef; 631 u_int8_t spanRowSize; 632 u_int8_t spanRowDataSize; 633 u_int8_t reserved[4]; 634 } MR_LD_SPAN; 635 636 typedef struct _MR_SPAN_BLOCK_INFO { 637 u_int64_t num_rows; 638 MR_LD_SPAN span; 639 MR_SPAN_INFO block_span_info; 640 } MR_SPAN_BLOCK_INFO; 641 642 typedef struct _MR_LD_RAID { 643 struct { 644 u_int32_t fpCapable:1; 645 u_int32_t reserved5:3; 646 u_int32_t ldPiMode:4; 647 u_int32_t pdPiMode:4; 648 u_int32_t encryptionType:8; 649 u_int32_t fpWriteCapable:1; 650 u_int32_t fpReadCapable:1; 651 u_int32_t fpWriteAcrossStripe:1; 652 u_int32_t fpReadAcrossStripe:1; 653 u_int32_t fpNonRWCapable:1; 654 u_int32_t reserved4:7; 655 } capability; 656 u_int32_t reserved6; 657 u_int64_t size; 658 659 u_int8_t spanDepth; 660 u_int8_t level; 661 u_int8_t stripeShift; 662 u_int8_t rowSize; 663 664 u_int8_t rowDataSize; 665 u_int8_t writeMode; 666 u_int8_t PRL; 667 u_int8_t SRL; 668 669 u_int16_t targetId; 670 u_int8_t ldState; 671 u_int8_t regTypeReqOnWrite; 672 u_int8_t modFactor; 673 u_int8_t regTypeReqOnRead; 674 u_int16_t seqNum; 675 676 struct { 677 u_int32_t ldSyncRequired:1; 678 u_int32_t regTypeReqOnReadLsValid:1; 679 u_int32_t reserved:30; 680 } flags; 681 682 u_int8_t LUN[8]; 683 u_int8_t fpIoTimeoutForLd; 684 u_int8_t reserved2[3]; 685 u_int32_t logicalBlockLength; 686 struct { 687 u_int32_t LdPiExp:4; 688 u_int32_t LdLogicalBlockExp:4; 689 u_int32_t reserved1:24; 690 } exponent; 691 u_int8_t reserved3[0x80 - 0x38]; 692 } MR_LD_RAID; 693 694 typedef struct _MR_LD_SPAN_MAP { 695 MR_LD_RAID ldRaid; 696 u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE]; 697 MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; 698 } MR_LD_SPAN_MAP; 699 700 typedef struct _MR_FW_RAID_MAP { 701 u_int32_t totalSize; 702 union { 703 struct { 704 u_int32_t maxLd; 705 u_int32_t maxSpanDepth; 706 u_int32_t maxRowSize; 707 u_int32_t maxPdCount; 708 u_int32_t maxArrays; 709 } validationInfo; 710 u_int32_t version[5]; 711 u_int32_t reserved1[5]; 712 } raid_desc; 713 u_int32_t ldCount; 714 u_int32_t Reserved1; 715 716 /* 717 * This doesn't correspond to FW Ld Tgt Id to LD, but will purge. For 718 * example: if tgt Id is 4 and FW LD is 2, and there is only one LD, 719 * FW will populate the array like this. [0xFF, 0xFF, 0xFF, 0xFF, 720 * 0x0,.....]. This is to help reduce the entire strcture size if 721 * there are few LDs or driver is looking info for 1 LD only. 722 */ 723 u_int8_t ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES + MAX_RAIDMAP_VIEWS]; 724 u_int8_t fpPdIoTimeoutSec; 725 u_int8_t reserved2[7]; 726 MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; 727 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 728 MR_LD_SPAN_MAP ldSpanMap[1]; 729 } MR_FW_RAID_MAP; 730 731 732 typedef struct _MR_FW_RAID_MAP_EXT { 733 /* Not used in new map */ 734 u_int32_t reserved; 735 736 union { 737 struct { 738 u_int32_t maxLd; 739 u_int32_t maxSpanDepth; 740 u_int32_t maxRowSize; 741 u_int32_t maxPdCount; 742 u_int32_t maxArrays; 743 } validationInfo; 744 u_int32_t version[5]; 745 u_int32_t reserved1[5]; 746 } fw_raid_desc; 747 748 u_int8_t fpPdIoTimeoutSec; 749 u_int8_t reserved2[7]; 750 751 u_int16_t ldCount; 752 u_int16_t arCount; 753 u_int16_t spanCount; 754 u_int16_t reserve3; 755 756 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 757 u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; 758 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; 759 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT]; 760 } MR_FW_RAID_MAP_EXT; 761 762 763 typedef struct _MR_DRV_RAID_MAP { 764 /* 765 * Total size of this structure, including this field. This feild 766 * will be manupulated by driver for ext raid map, else pick the 767 * value from firmware raid map. 768 */ 769 u_int32_t totalSize; 770 771 union { 772 struct { 773 u_int32_t maxLd; 774 u_int32_t maxSpanDepth; 775 u_int32_t maxRowSize; 776 u_int32_t maxPdCount; 777 u_int32_t maxArrays; 778 } validationInfo; 779 u_int32_t version[5]; 780 u_int32_t reserved1[5]; 781 } drv_raid_desc; 782 783 /* timeout value used by driver in FP IOs */ 784 u_int8_t fpPdIoTimeoutSec; 785 u_int8_t reserved2[7]; 786 787 u_int16_t ldCount; 788 u_int16_t arCount; 789 u_int16_t spanCount; 790 u_int16_t reserve3; 791 792 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 793 u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; 794 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; 795 MR_LD_SPAN_MAP ldSpanMap[1]; 796 797 } MR_DRV_RAID_MAP; 798 799 /* 800 * Driver raid map size is same as raid map ext MR_DRV_RAID_MAP_ALL is 801 * created to sync with old raid. And it is mainly for code re-use purpose. 802 */ 803 804 #pragma pack(1) 805 typedef struct _MR_DRV_RAID_MAP_ALL { 806 807 MR_DRV_RAID_MAP raidMap; 808 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT - 1]; 809 } MR_DRV_RAID_MAP_ALL; 810 811 #pragma pack() 812 813 typedef struct _LD_LOAD_BALANCE_INFO { 814 u_int8_t loadBalanceFlag; 815 u_int8_t reserved1; 816 u_int16_t raid1DevHandle[2]; 817 mrsas_atomic_t scsi_pending_cmds[2]; 818 u_int64_t last_accessed_block[2]; 819 } LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO; 820 821 /* SPAN_SET is info caclulated from span info from Raid map per ld */ 822 typedef struct _LD_SPAN_SET { 823 u_int64_t log_start_lba; 824 u_int64_t log_end_lba; 825 u_int64_t span_row_start; 826 u_int64_t span_row_end; 827 u_int64_t data_strip_start; 828 u_int64_t data_strip_end; 829 u_int64_t data_row_start; 830 u_int64_t data_row_end; 831 u_int8_t strip_offset[MAX_SPAN_DEPTH]; 832 u_int32_t span_row_data_width; 833 u_int32_t diff; 834 u_int32_t reserved[2]; 835 } LD_SPAN_SET, *PLD_SPAN_SET; 836 837 typedef struct LOG_BLOCK_SPAN_INFO { 838 LD_SPAN_SET span_set[MAX_SPAN_DEPTH]; 839 } LD_SPAN_INFO, *PLD_SPAN_INFO; 840 841 #pragma pack(1) 842 typedef struct _MR_FW_RAID_MAP_ALL { 843 MR_FW_RAID_MAP raidMap; 844 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1]; 845 } MR_FW_RAID_MAP_ALL; 846 847 #pragma pack() 848 849 struct IO_REQUEST_INFO { 850 u_int64_t ldStartBlock; 851 u_int32_t numBlocks; 852 u_int16_t ldTgtId; 853 u_int8_t isRead; 854 u_int16_t devHandle; 855 u_int64_t pdBlock; 856 u_int8_t fpOkForIo; 857 u_int8_t IoforUnevenSpan; 858 u_int8_t start_span; 859 u_int8_t reserved; 860 u_int64_t start_row; 861 }; 862 863 typedef struct _MR_LD_TARGET_SYNC { 864 u_int8_t targetId; 865 u_int8_t reserved; 866 u_int16_t seqNum; 867 } MR_LD_TARGET_SYNC; 868 869 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03) 870 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 871 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 872 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 873 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 874 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 875 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40) 876 877 union desc_value { 878 u_int64_t word; 879 struct { 880 u_int32_t low; 881 u_int32_t high; 882 } u; 883 }; 884 885 /******************************************************************* 886 * Temporary command 887 ********************************************************************/ 888 struct mrsas_tmp_dcmd { 889 bus_dma_tag_t tmp_dcmd_tag; 890 bus_dmamap_t tmp_dcmd_dmamap; 891 void *tmp_dcmd_mem; 892 bus_addr_t tmp_dcmd_phys_addr; 893 }; 894 895 /******************************************************************* 896 * Register set, included legacy controllers 1068 and 1078, 897 * structure extended for 1078 registers 898 *******************************************************************/ 899 #pragma pack(1) 900 typedef struct _mrsas_register_set { 901 u_int32_t doorbell; /* 0000h */ 902 u_int32_t fusion_seq_offset; /* 0004h */ 903 u_int32_t fusion_host_diag; /* 0008h */ 904 u_int32_t reserved_01; /* 000Ch */ 905 906 u_int32_t inbound_msg_0; /* 0010h */ 907 u_int32_t inbound_msg_1; /* 0014h */ 908 u_int32_t outbound_msg_0; /* 0018h */ 909 u_int32_t outbound_msg_1; /* 001Ch */ 910 911 u_int32_t inbound_doorbell; /* 0020h */ 912 u_int32_t inbound_intr_status; /* 0024h */ 913 u_int32_t inbound_intr_mask; /* 0028h */ 914 915 u_int32_t outbound_doorbell; /* 002Ch */ 916 u_int32_t outbound_intr_status; /* 0030h */ 917 u_int32_t outbound_intr_mask; /* 0034h */ 918 919 u_int32_t reserved_1[2]; /* 0038h */ 920 921 u_int32_t inbound_queue_port; /* 0040h */ 922 u_int32_t outbound_queue_port; /* 0044h */ 923 924 u_int32_t reserved_2[9]; /* 0048h */ 925 u_int32_t reply_post_host_index;/* 006Ch */ 926 u_int32_t reserved_2_2[12]; /* 0070h */ 927 928 u_int32_t outbound_doorbell_clear; /* 00A0h */ 929 930 u_int32_t reserved_3[3]; /* 00A4h */ 931 932 u_int32_t outbound_scratch_pad; /* 00B0h */ 933 u_int32_t outbound_scratch_pad_2; /* 00B4h */ 934 935 u_int32_t reserved_4[2]; /* 00B8h */ 936 937 u_int32_t inbound_low_queue_port; /* 00C0h */ 938 939 u_int32_t inbound_high_queue_port; /* 00C4h */ 940 941 u_int32_t reserved_5; /* 00C8h */ 942 u_int32_t res_6[11]; /* CCh */ 943 u_int32_t host_diag; 944 u_int32_t seq_offset; 945 u_int32_t index_registers[807]; /* 00CCh */ 946 } mrsas_reg_set; 947 948 #pragma pack() 949 950 /******************************************************************* 951 * Firmware Interface Defines 952 ******************************************************************* 953 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker 954 * for protocol between the software and firmware. Commands are 955 * issued using "message frames". 956 ******************************************************************/ 957 /* 958 * FW posts its state in upper 4 bits of outbound_msg_0 register 959 */ 960 #define MFI_STATE_MASK 0xF0000000 961 #define MFI_STATE_UNDEFINED 0x00000000 962 #define MFI_STATE_BB_INIT 0x10000000 963 #define MFI_STATE_FW_INIT 0x40000000 964 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 965 #define MFI_STATE_FW_INIT_2 0x70000000 966 #define MFI_STATE_DEVICE_SCAN 0x80000000 967 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 968 #define MFI_STATE_FLUSH_CACHE 0xA0000000 969 #define MFI_STATE_READY 0xB0000000 970 #define MFI_STATE_OPERATIONAL 0xC0000000 971 #define MFI_STATE_FAULT 0xF0000000 972 #define MFI_RESET_REQUIRED 0x00000001 973 #define MFI_RESET_ADAPTER 0x00000002 974 #define MEGAMFI_FRAME_SIZE 64 975 #define MRSAS_MFI_FRAME_SIZE 1024 976 #define MRSAS_MFI_SENSE_SIZE 128 977 978 /* 979 * During FW init, clear pending cmds & reset state using inbound_msg_0 980 * 981 * ABORT : Abort all pending cmds READY : Move from OPERATIONAL to 982 * READY state; discard queue info MFIMODE : Discard (possible) low MFA 983 * posted in 64-bit mode (??) CLR_HANDSHAKE: FW is waiting for HANDSHAKE from 984 * BIOS or Driver HOTPLUG : Resume from Hotplug MFI_STOP_ADP : Send 985 * signal to FW to stop processing 986 */ 987 988 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) 989 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) 990 #define DIAG_WRITE_ENABLE (0x00000080) 991 #define DIAG_RESET_ADAPTER (0x00000004) 992 993 #define MFI_ADP_RESET 0x00000040 994 #define MFI_INIT_ABORT 0x00000001 995 #define MFI_INIT_READY 0x00000002 996 #define MFI_INIT_MFIMODE 0x00000004 997 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 998 #define MFI_INIT_HOTPLUG 0x00000010 999 #define MFI_STOP_ADP 0x00000020 1000 #define MFI_RESET_FLAGS MFI_INIT_READY| \ 1001 MFI_INIT_MFIMODE| \ 1002 MFI_INIT_ABORT 1003 1004 /* 1005 * MFI frame flags 1006 */ 1007 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 1008 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 1009 #define MFI_FRAME_SGL32 0x0000 1010 #define MFI_FRAME_SGL64 0x0002 1011 #define MFI_FRAME_SENSE32 0x0000 1012 #define MFI_FRAME_SENSE64 0x0004 1013 #define MFI_FRAME_DIR_NONE 0x0000 1014 #define MFI_FRAME_DIR_WRITE 0x0008 1015 #define MFI_FRAME_DIR_READ 0x0010 1016 #define MFI_FRAME_DIR_BOTH 0x0018 1017 #define MFI_FRAME_IEEE 0x0020 1018 1019 /* 1020 * Definition for cmd_status 1021 */ 1022 #define MFI_CMD_STATUS_POLL_MODE 0xFF 1023 1024 /* 1025 * MFI command opcodes 1026 */ 1027 #define MFI_CMD_INIT 0x00 1028 #define MFI_CMD_LD_READ 0x01 1029 #define MFI_CMD_LD_WRITE 0x02 1030 #define MFI_CMD_LD_SCSI_IO 0x03 1031 #define MFI_CMD_PD_SCSI_IO 0x04 1032 #define MFI_CMD_DCMD 0x05 1033 #define MFI_CMD_ABORT 0x06 1034 #define MFI_CMD_SMP 0x07 1035 #define MFI_CMD_STP 0x08 1036 #define MFI_CMD_INVALID 0xff 1037 1038 #define MR_DCMD_CTRL_GET_INFO 0x01010000 1039 #define MR_DCMD_LD_GET_LIST 0x03010000 1040 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 1041 #define MR_FLUSH_CTRL_CACHE 0x01 1042 #define MR_FLUSH_DISK_CACHE 0x02 1043 1044 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 1045 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 1046 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 1047 1048 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 1049 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 1050 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 1051 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 1052 1053 #define MR_DCMD_CLUSTER 0x08000000 1054 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 1055 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 1056 #define MR_DCMD_PD_LIST_QUERY 0x02010100 1057 1058 #define MR_DCMD_CTRL_MISC_CPX 0x0100e200 1059 #define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET 0x0100e201 1060 #define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA 0x0100e202 1061 #define MR_DCMD_CTRL_MISC_CPX_UNREGISTER 0x0100e203 1062 #define MAX_MR_ROW_SIZE 32 1063 #define MR_CPX_DIR_WRITE 1 1064 #define MR_CPX_DIR_READ 0 1065 #define MR_CPX_VERSION 1 1066 1067 #define MR_DCMD_CTRL_IO_METRICS_GET 0x01170200 1068 1069 #define MR_EVT_CFG_CLEARED 0x0004 1070 1071 #define MR_EVT_LD_STATE_CHANGE 0x0051 1072 #define MR_EVT_PD_INSERTED 0x005b 1073 #define MR_EVT_PD_REMOVED 0x0070 1074 #define MR_EVT_LD_CREATED 0x008a 1075 #define MR_EVT_LD_DELETED 0x008b 1076 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1077 #define MR_EVT_LD_OFFLINE 0x00fc 1078 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1079 #define MR_EVT_CTRL_PERF_COLLECTION 0x017e 1080 1081 /* 1082 * MFI command completion codes 1083 */ 1084 enum MFI_STAT { 1085 MFI_STAT_OK = 0x00, 1086 MFI_STAT_INVALID_CMD = 0x01, 1087 MFI_STAT_INVALID_DCMD = 0x02, 1088 MFI_STAT_INVALID_PARAMETER = 0x03, 1089 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 1090 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 1091 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 1092 MFI_STAT_APP_IN_USE = 0x07, 1093 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 1094 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 1095 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 1096 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 1097 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 1098 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 1099 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 1100 MFI_STAT_FLASH_BUSY = 0x0f, 1101 MFI_STAT_FLASH_ERROR = 0x10, 1102 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 1103 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 1104 MFI_STAT_FLASH_NOT_OPEN = 0x13, 1105 MFI_STAT_FLASH_NOT_STARTED = 0x14, 1106 MFI_STAT_FLUSH_FAILED = 0x15, 1107 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 1108 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 1109 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 1110 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 1111 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 1112 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 1113 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 1114 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 1115 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 1116 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 1117 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 1118 MFI_STAT_MFC_HW_ERROR = 0x21, 1119 MFI_STAT_NO_HW_PRESENT = 0x22, 1120 MFI_STAT_NOT_FOUND = 0x23, 1121 MFI_STAT_NOT_IN_ENCL = 0x24, 1122 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 1123 MFI_STAT_PD_TYPE_WRONG = 0x26, 1124 MFI_STAT_PR_DISABLED = 0x27, 1125 MFI_STAT_ROW_INDEX_INVALID = 0x28, 1126 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 1127 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 1128 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 1129 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 1130 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 1131 MFI_STAT_SCSI_IO_FAILED = 0x2e, 1132 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 1133 MFI_STAT_SHUTDOWN_FAILED = 0x30, 1134 MFI_STAT_TIME_NOT_SET = 0x31, 1135 MFI_STAT_WRONG_STATE = 0x32, 1136 MFI_STAT_LD_OFFLINE = 0x33, 1137 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 1138 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 1139 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 1140 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 1141 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 1142 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 1143 1144 MFI_STAT_INVALID_STATUS = 0xFF 1145 }; 1146 1147 /* 1148 * Number of mailbox bytes in DCMD message frame 1149 */ 1150 #define MFI_MBOX_SIZE 12 1151 1152 enum MR_EVT_CLASS { 1153 1154 MR_EVT_CLASS_DEBUG = -2, 1155 MR_EVT_CLASS_PROGRESS = -1, 1156 MR_EVT_CLASS_INFO = 0, 1157 MR_EVT_CLASS_WARNING = 1, 1158 MR_EVT_CLASS_CRITICAL = 2, 1159 MR_EVT_CLASS_FATAL = 3, 1160 MR_EVT_CLASS_DEAD = 4, 1161 1162 }; 1163 1164 enum MR_EVT_LOCALE { 1165 1166 MR_EVT_LOCALE_LD = 0x0001, 1167 MR_EVT_LOCALE_PD = 0x0002, 1168 MR_EVT_LOCALE_ENCL = 0x0004, 1169 MR_EVT_LOCALE_BBU = 0x0008, 1170 MR_EVT_LOCALE_SAS = 0x0010, 1171 MR_EVT_LOCALE_CTRL = 0x0020, 1172 MR_EVT_LOCALE_CONFIG = 0x0040, 1173 MR_EVT_LOCALE_CLUSTER = 0x0080, 1174 MR_EVT_LOCALE_ALL = 0xffff, 1175 1176 }; 1177 1178 enum MR_EVT_ARGS { 1179 1180 MR_EVT_ARGS_NONE, 1181 MR_EVT_ARGS_CDB_SENSE, 1182 MR_EVT_ARGS_LD, 1183 MR_EVT_ARGS_LD_COUNT, 1184 MR_EVT_ARGS_LD_LBA, 1185 MR_EVT_ARGS_LD_OWNER, 1186 MR_EVT_ARGS_LD_LBA_PD_LBA, 1187 MR_EVT_ARGS_LD_PROG, 1188 MR_EVT_ARGS_LD_STATE, 1189 MR_EVT_ARGS_LD_STRIP, 1190 MR_EVT_ARGS_PD, 1191 MR_EVT_ARGS_PD_ERR, 1192 MR_EVT_ARGS_PD_LBA, 1193 MR_EVT_ARGS_PD_LBA_LD, 1194 MR_EVT_ARGS_PD_PROG, 1195 MR_EVT_ARGS_PD_STATE, 1196 MR_EVT_ARGS_PCI, 1197 MR_EVT_ARGS_RATE, 1198 MR_EVT_ARGS_STR, 1199 MR_EVT_ARGS_TIME, 1200 MR_EVT_ARGS_ECC, 1201 MR_EVT_ARGS_LD_PROP, 1202 MR_EVT_ARGS_PD_SPARE, 1203 MR_EVT_ARGS_PD_INDEX, 1204 MR_EVT_ARGS_DIAG_PASS, 1205 MR_EVT_ARGS_DIAG_FAIL, 1206 MR_EVT_ARGS_PD_LBA_LBA, 1207 MR_EVT_ARGS_PORT_PHY, 1208 MR_EVT_ARGS_PD_MISSING, 1209 MR_EVT_ARGS_PD_ADDRESS, 1210 MR_EVT_ARGS_BITMAP, 1211 MR_EVT_ARGS_CONNECTOR, 1212 MR_EVT_ARGS_PD_PD, 1213 MR_EVT_ARGS_PD_FRU, 1214 MR_EVT_ARGS_PD_PATHINFO, 1215 MR_EVT_ARGS_PD_POWER_STATE, 1216 MR_EVT_ARGS_GENERIC, 1217 }; 1218 1219 1220 /* 1221 * Thunderbolt (and later) Defines 1222 */ 1223 #define MRSAS_MAX_SZ_CHAIN_FRAME 1024 1224 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) 1225 #define MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 1226 #define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 1227 #define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 1228 #define MRSAS_LOAD_BALANCE_FLAG 0x1 1229 #define MRSAS_DCMD_MBOX_PEND_FLAG 0x1 1230 #define HOST_DIAG_WRITE_ENABLE 0x80 1231 #define HOST_DIAG_RESET_ADAPTER 0x4 1232 #define MRSAS_TBOLT_MAX_RESET_TRIES 3 1233 #define MRSAS_MAX_MFI_CMDS 32 1234 1235 /* 1236 * Invader Defines 1237 */ 1238 #define MPI2_TYPE_CUDA 0x2 1239 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000 1240 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00 1241 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10 1242 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80 1243 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8 1244 1245 /* 1246 * T10 PI defines 1247 */ 1248 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8 1249 #define MRSAS_SCSI_VARIABLE_LENGTH_CMD 0x7f 1250 #define MRSAS_SCSI_SERVICE_ACTION_READ32 0x9 1251 #define MRSAS_SCSI_SERVICE_ACTION_WRITE32 0xB 1252 #define MRSAS_SCSI_ADDL_CDB_LEN 0x18 1253 #define MRSAS_RD_WR_PROTECT_CHECK_ALL 0x20 1254 #define MRSAS_RD_WR_PROTECT_CHECK_NONE 0x60 1255 #define MRSAS_SCSIBLOCKSIZE 512 1256 1257 /* 1258 * Raid context flags 1259 */ 1260 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 1261 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 1262 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE { 1263 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, 1264 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1, 1265 } MR_RAID_FLAGS_IO_SUB_TYPE; 1266 1267 /* 1268 * Request descriptor types 1269 */ 1270 #define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7 1271 #define MRSAS_REQ_DESCRIPT_FLAGS_MFA 0x1 1272 #define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2 1273 #define MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1 1274 #define MRSAS_FP_CMD_LEN 16 1275 #define MRSAS_FUSION_IN_RESET 0 1276 1277 #define RAID_CTX_SPANARM_ARM_SHIFT (0) 1278 #define RAID_CTX_SPANARM_ARM_MASK (0x1f) 1279 #define RAID_CTX_SPANARM_SPAN_SHIFT (5) 1280 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0) 1281 1282 /* 1283 * Define region lock types 1284 */ 1285 typedef enum _REGION_TYPE { 1286 REGION_TYPE_UNUSED = 0, 1287 REGION_TYPE_SHARED_READ = 1, 1288 REGION_TYPE_SHARED_WRITE = 2, 1289 REGION_TYPE_EXCLUSIVE = 3, 1290 } REGION_TYPE; 1291 1292 1293 /* 1294 * SCSI-CAM Related Defines 1295 */ 1296 #define MRSAS_SCSI_MAX_LUNS 0 1297 #define MRSAS_SCSI_INITIATOR_ID 255 1298 #define MRSAS_SCSI_MAX_CMDS 8 1299 #define MRSAS_SCSI_MAX_CDB_LEN 16 1300 #define MRSAS_SCSI_SENSE_BUFFERSIZE 96 1301 #define MRSAS_MAX_SGL 70 1302 #define MRSAS_MAX_IO_SIZE (256 * 1024) 1303 #define MRSAS_INTERNAL_CMDS 32 1304 1305 /* Request types */ 1306 #define MRSAS_REQ_TYPE_INTERNAL_CMD 0x0 1307 #define MRSAS_REQ_TYPE_AEN_FETCH 0x1 1308 #define MRSAS_REQ_TYPE_PASSTHRU 0x2 1309 #define MRSAS_REQ_TYPE_GETSET_PARAM 0x3 1310 #define MRSAS_REQ_TYPE_SCSI_IO 0x4 1311 1312 /* Request states */ 1313 #define MRSAS_REQ_STATE_FREE 0 1314 #define MRSAS_REQ_STATE_BUSY 1 1315 #define MRSAS_REQ_STATE_TRAN 2 1316 #define MRSAS_REQ_STATE_COMPLETE 3 1317 1318 enum mrsas_req_flags { 1319 MRSAS_DIR_UNKNOWN = 0x1, 1320 MRSAS_DIR_IN = 0x2, 1321 MRSAS_DIR_OUT = 0x4, 1322 MRSAS_DIR_NONE = 0x8, 1323 }; 1324 1325 /* 1326 * Adapter Reset States 1327 */ 1328 enum { 1329 MRSAS_HBA_OPERATIONAL = 0, 1330 MRSAS_ADPRESET_SM_INFAULT = 1, 1331 MRSAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 1332 MRSAS_ADPRESET_SM_OPERATIONAL = 3, 1333 MRSAS_HW_CRITICAL_ERROR = 4, 1334 MRSAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 1335 }; 1336 1337 /* 1338 * MPT Command Structure 1339 */ 1340 struct mrsas_mpt_cmd { 1341 MRSAS_RAID_SCSI_IO_REQUEST *io_request; 1342 bus_addr_t io_request_phys_addr; 1343 MPI2_SGE_IO_UNION *chain_frame; 1344 bus_addr_t chain_frame_phys_addr; 1345 u_int32_t sge_count; 1346 u_int8_t *sense; 1347 bus_addr_t sense_phys_addr; 1348 u_int8_t retry_for_fw_reset; 1349 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc; 1350 u_int32_t sync_cmd_idx; 1351 u_int32_t index; 1352 u_int8_t flags; 1353 u_int8_t load_balance; 1354 bus_size_t length; 1355 u_int32_t error_code; 1356 bus_dmamap_t data_dmamap; 1357 void *data; 1358 union ccb *ccb_ptr; 1359 struct callout cm_callout; 1360 struct mrsas_softc *sc; 1361 TAILQ_ENTRY(mrsas_mpt_cmd) next; 1362 }; 1363 1364 /* 1365 * MFI Command Structure 1366 */ 1367 struct mrsas_mfi_cmd { 1368 union mrsas_frame *frame; 1369 bus_dmamap_t frame_dmamap; 1370 void *frame_mem; 1371 bus_addr_t frame_phys_addr; 1372 u_int8_t *sense; 1373 bus_dmamap_t sense_dmamap; 1374 void *sense_mem; 1375 bus_addr_t sense_phys_addr; 1376 u_int32_t index; 1377 u_int8_t sync_cmd; 1378 u_int8_t cmd_status; 1379 u_int8_t abort_aen; 1380 u_int8_t retry_for_fw_reset; 1381 struct mrsas_softc *sc; 1382 union ccb *ccb_ptr; 1383 union { 1384 struct { 1385 u_int16_t smid; 1386 u_int16_t resvd; 1387 } context; 1388 u_int32_t frame_count; 1389 } cmd_id; 1390 TAILQ_ENTRY(mrsas_mfi_cmd) next; 1391 }; 1392 1393 1394 /* 1395 * define constants for device list query options 1396 */ 1397 enum MR_PD_QUERY_TYPE { 1398 MR_PD_QUERY_TYPE_ALL = 0, 1399 MR_PD_QUERY_TYPE_STATE = 1, 1400 MR_PD_QUERY_TYPE_POWER_STATE = 2, 1401 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 1402 MR_PD_QUERY_TYPE_SPEED = 4, 1403 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 1404 }; 1405 1406 #define MR_EVT_CFG_CLEARED 0x0004 1407 #define MR_EVT_LD_STATE_CHANGE 0x0051 1408 #define MR_EVT_PD_INSERTED 0x005b 1409 #define MR_EVT_PD_REMOVED 0x0070 1410 #define MR_EVT_LD_CREATED 0x008a 1411 #define MR_EVT_LD_DELETED 0x008b 1412 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1413 #define MR_EVT_LD_OFFLINE 0x00fc 1414 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1415 1416 enum MR_PD_STATE { 1417 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1418 MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 1419 MR_PD_STATE_HOT_SPARE = 0x02, 1420 MR_PD_STATE_OFFLINE = 0x10, 1421 MR_PD_STATE_FAILED = 0x11, 1422 MR_PD_STATE_REBUILD = 0x14, 1423 MR_PD_STATE_ONLINE = 0x18, 1424 MR_PD_STATE_COPYBACK = 0x20, 1425 MR_PD_STATE_SYSTEM = 0x40, 1426 }; 1427 1428 /* 1429 * defines the physical drive address structure 1430 */ 1431 #pragma pack(1) 1432 struct MR_PD_ADDRESS { 1433 u_int16_t deviceId; 1434 u_int16_t enclDeviceId; 1435 1436 union { 1437 struct { 1438 u_int8_t enclIndex; 1439 u_int8_t slotNumber; 1440 } mrPdAddress; 1441 struct { 1442 u_int8_t enclPosition; 1443 u_int8_t enclConnectorIndex; 1444 } mrEnclAddress; 1445 } u1; 1446 u_int8_t scsiDevType; 1447 union { 1448 u_int8_t connectedPortBitmap; 1449 u_int8_t connectedPortNumbers; 1450 } u2; 1451 u_int64_t sasAddr[2]; 1452 }; 1453 1454 #pragma pack() 1455 1456 /* 1457 * defines the physical drive list structure 1458 */ 1459 #pragma pack(1) 1460 struct MR_PD_LIST { 1461 u_int32_t size; 1462 u_int32_t count; 1463 struct MR_PD_ADDRESS addr[1]; 1464 }; 1465 1466 #pragma pack() 1467 1468 #pragma pack(1) 1469 struct mrsas_pd_list { 1470 u_int16_t tid; 1471 u_int8_t driveType; 1472 u_int8_t driveState; 1473 }; 1474 1475 #pragma pack() 1476 1477 /* 1478 * defines the logical drive reference structure 1479 */ 1480 typedef union _MR_LD_REF { 1481 struct { 1482 u_int8_t targetId; 1483 u_int8_t reserved; 1484 u_int16_t seqNum; 1485 } ld_context; 1486 u_int32_t ref; 1487 } MR_LD_REF; 1488 1489 1490 /* 1491 * defines the logical drive list structure 1492 */ 1493 #pragma pack(1) 1494 struct MR_LD_LIST { 1495 u_int32_t ldCount; 1496 u_int32_t reserved; 1497 struct { 1498 MR_LD_REF ref; 1499 u_int8_t state; 1500 u_int8_t reserved[3]; 1501 u_int64_t size; 1502 } ldList[MAX_LOGICAL_DRIVES_EXT]; 1503 }; 1504 1505 #pragma pack() 1506 1507 /* 1508 * SAS controller properties 1509 */ 1510 #pragma pack(1) 1511 struct mrsas_ctrl_prop { 1512 u_int16_t seq_num; 1513 u_int16_t pred_fail_poll_interval; 1514 u_int16_t intr_throttle_count; 1515 u_int16_t intr_throttle_timeouts; 1516 u_int8_t rebuild_rate; 1517 u_int8_t patrol_read_rate; 1518 u_int8_t bgi_rate; 1519 u_int8_t cc_rate; 1520 u_int8_t recon_rate; 1521 u_int8_t cache_flush_interval; 1522 u_int8_t spinup_drv_count; 1523 u_int8_t spinup_delay; 1524 u_int8_t cluster_enable; 1525 u_int8_t coercion_mode; 1526 u_int8_t alarm_enable; 1527 u_int8_t disable_auto_rebuild; 1528 u_int8_t disable_battery_warn; 1529 u_int8_t ecc_bucket_size; 1530 u_int16_t ecc_bucket_leak_rate; 1531 u_int8_t restore_hotspare_on_insertion; 1532 u_int8_t expose_encl_devices; 1533 u_int8_t maintainPdFailHistory; 1534 u_int8_t disallowHostRequestReordering; 1535 u_int8_t abortCCOnError; 1536 u_int8_t loadBalanceMode; 1537 u_int8_t disableAutoDetectBackplane; 1538 u_int8_t snapVDSpace; 1539 /* 1540 * Add properties that can be controlled by a bit in the following 1541 * structure. 1542 */ 1543 struct { 1544 u_int32_t copyBackDisabled:1; 1545 u_int32_t SMARTerEnabled:1; 1546 u_int32_t prCorrectUnconfiguredAreas:1; 1547 u_int32_t useFdeOnly:1; 1548 u_int32_t disableNCQ:1; 1549 u_int32_t SSDSMARTerEnabled:1; 1550 u_int32_t SSDPatrolReadEnabled:1; 1551 u_int32_t enableSpinDownUnconfigured:1; 1552 u_int32_t autoEnhancedImport:1; 1553 u_int32_t enableSecretKeyControl:1; 1554 u_int32_t disableOnlineCtrlReset:1; 1555 u_int32_t allowBootWithPinnedCache:1; 1556 u_int32_t disableSpinDownHS:1; 1557 u_int32_t enableJBOD:1; 1558 u_int32_t disableCacheBypass:1; 1559 u_int32_t useDiskActivityForLocate:1; 1560 u_int32_t enablePI:1; 1561 u_int32_t preventPIImport:1; 1562 u_int32_t useGlobalSparesForEmergency:1; 1563 u_int32_t useUnconfGoodForEmergency:1; 1564 u_int32_t useEmergencySparesforSMARTer:1; 1565 u_int32_t forceSGPIOForQuadOnly:1; 1566 u_int32_t enableConfigAutoBalance:1; 1567 u_int32_t enableVirtualCache:1; 1568 u_int32_t enableAutoLockRecovery:1; 1569 u_int32_t disableImmediateIO:1; 1570 u_int32_t disableT10RebuildAssist:1; 1571 u_int32_t ignore64ldRestriction:1; 1572 u_int32_t enableSwZone:1; 1573 u_int32_t limitMaxRateSATA3G:1; 1574 u_int32_t reserved:2; 1575 } OnOffProperties; 1576 u_int8_t autoSnapVDSpace; 1577 u_int8_t viewSpace; 1578 u_int16_t spinDownTime; 1579 u_int8_t reserved[24]; 1580 1581 }; 1582 1583 #pragma pack() 1584 1585 1586 /* 1587 * SAS controller information 1588 */ 1589 struct mrsas_ctrl_info { 1590 /* 1591 * PCI device information 1592 */ 1593 struct { 1594 u_int16_t vendor_id; 1595 u_int16_t device_id; 1596 u_int16_t sub_vendor_id; 1597 u_int16_t sub_device_id; 1598 u_int8_t reserved[24]; 1599 } __packed pci; 1600 /* 1601 * Host interface information 1602 */ 1603 struct { 1604 u_int8_t PCIX:1; 1605 u_int8_t PCIE:1; 1606 u_int8_t iSCSI:1; 1607 u_int8_t SAS_3G:1; 1608 u_int8_t reserved_0:4; 1609 u_int8_t reserved_1[6]; 1610 u_int8_t port_count; 1611 u_int64_t port_addr[8]; 1612 } __packed host_interface; 1613 /* 1614 * Device (backend) interface information 1615 */ 1616 struct { 1617 u_int8_t SPI:1; 1618 u_int8_t SAS_3G:1; 1619 u_int8_t SATA_1_5G:1; 1620 u_int8_t SATA_3G:1; 1621 u_int8_t reserved_0:4; 1622 u_int8_t reserved_1[6]; 1623 u_int8_t port_count; 1624 u_int64_t port_addr[8]; 1625 } __packed device_interface; 1626 1627 u_int32_t image_check_word; 1628 u_int32_t image_component_count; 1629 1630 struct { 1631 char name[8]; 1632 char version[32]; 1633 char build_date[16]; 1634 char built_time[16]; 1635 } __packed image_component[8]; 1636 1637 u_int32_t pending_image_component_count; 1638 1639 struct { 1640 char name[8]; 1641 char version[32]; 1642 char build_date[16]; 1643 char build_time[16]; 1644 } __packed pending_image_component[8]; 1645 1646 u_int8_t max_arms; 1647 u_int8_t max_spans; 1648 u_int8_t max_arrays; 1649 u_int8_t max_lds; 1650 char product_name[80]; 1651 char serial_no[32]; 1652 1653 /* 1654 * Other physical/controller/operation information. Indicates the 1655 * presence of the hardware 1656 */ 1657 struct { 1658 u_int32_t bbu:1; 1659 u_int32_t alarm:1; 1660 u_int32_t nvram:1; 1661 u_int32_t uart:1; 1662 u_int32_t reserved:28; 1663 } __packed hw_present; 1664 1665 u_int32_t current_fw_time; 1666 1667 /* 1668 * Maximum data transfer sizes 1669 */ 1670 u_int16_t max_concurrent_cmds; 1671 u_int16_t max_sge_count; 1672 u_int32_t max_request_size; 1673 1674 /* 1675 * Logical and physical device counts 1676 */ 1677 u_int16_t ld_present_count; 1678 u_int16_t ld_degraded_count; 1679 u_int16_t ld_offline_count; 1680 1681 u_int16_t pd_present_count; 1682 u_int16_t pd_disk_present_count; 1683 u_int16_t pd_disk_pred_failure_count; 1684 u_int16_t pd_disk_failed_count; 1685 1686 /* 1687 * Memory size information 1688 */ 1689 u_int16_t nvram_size; 1690 u_int16_t memory_size; 1691 u_int16_t flash_size; 1692 1693 /* 1694 * Error counters 1695 */ 1696 u_int16_t mem_correctable_error_count; 1697 u_int16_t mem_uncorrectable_error_count; 1698 1699 /* 1700 * Cluster information 1701 */ 1702 u_int8_t cluster_permitted; 1703 u_int8_t cluster_active; 1704 1705 /* 1706 * Additional max data transfer sizes 1707 */ 1708 u_int16_t max_strips_per_io; 1709 1710 /* 1711 * Controller capabilities structures 1712 */ 1713 struct { 1714 u_int32_t raid_level_0:1; 1715 u_int32_t raid_level_1:1; 1716 u_int32_t raid_level_5:1; 1717 u_int32_t raid_level_1E:1; 1718 u_int32_t raid_level_6:1; 1719 u_int32_t reserved:27; 1720 } __packed raid_levels; 1721 1722 struct { 1723 u_int32_t rbld_rate:1; 1724 u_int32_t cc_rate:1; 1725 u_int32_t bgi_rate:1; 1726 u_int32_t recon_rate:1; 1727 u_int32_t patrol_rate:1; 1728 u_int32_t alarm_control:1; 1729 u_int32_t cluster_supported:1; 1730 u_int32_t bbu:1; 1731 u_int32_t spanning_allowed:1; 1732 u_int32_t dedicated_hotspares:1; 1733 u_int32_t revertible_hotspares:1; 1734 u_int32_t foreign_config_import:1; 1735 u_int32_t self_diagnostic:1; 1736 u_int32_t mixed_redundancy_arr:1; 1737 u_int32_t global_hot_spares:1; 1738 u_int32_t reserved:17; 1739 } __packed adapter_operations; 1740 1741 struct { 1742 u_int32_t read_policy:1; 1743 u_int32_t write_policy:1; 1744 u_int32_t io_policy:1; 1745 u_int32_t access_policy:1; 1746 u_int32_t disk_cache_policy:1; 1747 u_int32_t reserved:27; 1748 } __packed ld_operations; 1749 1750 struct { 1751 u_int8_t min; 1752 u_int8_t max; 1753 u_int8_t reserved[2]; 1754 } __packed stripe_sz_ops; 1755 1756 struct { 1757 u_int32_t force_online:1; 1758 u_int32_t force_offline:1; 1759 u_int32_t force_rebuild:1; 1760 u_int32_t reserved:29; 1761 } __packed pd_operations; 1762 1763 struct { 1764 u_int32_t ctrl_supports_sas:1; 1765 u_int32_t ctrl_supports_sata:1; 1766 u_int32_t allow_mix_in_encl:1; 1767 u_int32_t allow_mix_in_ld:1; 1768 u_int32_t allow_sata_in_cluster:1; 1769 u_int32_t reserved:27; 1770 } __packed pd_mix_support; 1771 1772 /* 1773 * Define ECC single-bit-error bucket information 1774 */ 1775 u_int8_t ecc_bucket_count; 1776 u_int8_t reserved_2[11]; 1777 1778 /* 1779 * Include the controller properties (changeable items) 1780 */ 1781 struct mrsas_ctrl_prop properties; 1782 1783 /* 1784 * Define FW pkg version (set in envt v'bles on OEM basis) 1785 */ 1786 char package_version[0x60]; 1787 1788 u_int64_t deviceInterfacePortAddr2[8]; 1789 u_int8_t reserved3[128]; 1790 1791 struct { 1792 u_int16_t minPdRaidLevel_0:4; 1793 u_int16_t maxPdRaidLevel_0:12; 1794 1795 u_int16_t minPdRaidLevel_1:4; 1796 u_int16_t maxPdRaidLevel_1:12; 1797 1798 u_int16_t minPdRaidLevel_5:4; 1799 u_int16_t maxPdRaidLevel_5:12; 1800 1801 u_int16_t minPdRaidLevel_1E:4; 1802 u_int16_t maxPdRaidLevel_1E:12; 1803 1804 u_int16_t minPdRaidLevel_6:4; 1805 u_int16_t maxPdRaidLevel_6:12; 1806 1807 u_int16_t minPdRaidLevel_10:4; 1808 u_int16_t maxPdRaidLevel_10:12; 1809 1810 u_int16_t minPdRaidLevel_50:4; 1811 u_int16_t maxPdRaidLevel_50:12; 1812 1813 u_int16_t minPdRaidLevel_60:4; 1814 u_int16_t maxPdRaidLevel_60:12; 1815 1816 u_int16_t minPdRaidLevel_1E_RLQ0:4; 1817 u_int16_t maxPdRaidLevel_1E_RLQ0:12; 1818 1819 u_int16_t minPdRaidLevel_1E0_RLQ0:4; 1820 u_int16_t maxPdRaidLevel_1E0_RLQ0:12; 1821 1822 u_int16_t reserved[6]; 1823 } pdsForRaidLevels; 1824 1825 u_int16_t maxPds; /* 0x780 */ 1826 u_int16_t maxDedHSPs; /* 0x782 */ 1827 u_int16_t maxGlobalHSPs; /* 0x784 */ 1828 u_int16_t ddfSize; /* 0x786 */ 1829 u_int8_t maxLdsPerArray; /* 0x788 */ 1830 u_int8_t partitionsInDDF; /* 0x789 */ 1831 u_int8_t lockKeyBinding; /* 0x78a */ 1832 u_int8_t maxPITsPerLd; /* 0x78b */ 1833 u_int8_t maxViewsPerLd; /* 0x78c */ 1834 u_int8_t maxTargetId; /* 0x78d */ 1835 u_int16_t maxBvlVdSize; /* 0x78e */ 1836 1837 u_int16_t maxConfigurableSSCSize; /* 0x790 */ 1838 u_int16_t currentSSCsize; /* 0x792 */ 1839 1840 char expanderFwVersion[12]; /* 0x794 */ 1841 1842 u_int16_t PFKTrialTimeRemaining;/* 0x7A0 */ 1843 1844 u_int16_t cacheMemorySize; /* 0x7A2 */ 1845 1846 struct { /* 0x7A4 */ 1847 u_int32_t supportPIcontroller:1; 1848 u_int32_t supportLdPIType1:1; 1849 u_int32_t supportLdPIType2:1; 1850 u_int32_t supportLdPIType3:1; 1851 u_int32_t supportLdBBMInfo:1; 1852 u_int32_t supportShieldState:1; 1853 u_int32_t blockSSDWriteCacheChange:1; 1854 u_int32_t supportSuspendResumeBGops:1; 1855 u_int32_t supportEmergencySpares:1; 1856 u_int32_t supportSetLinkSpeed:1; 1857 u_int32_t supportBootTimePFKChange:1; 1858 u_int32_t supportJBOD:1; 1859 u_int32_t disableOnlinePFKChange:1; 1860 u_int32_t supportPerfTuning:1; 1861 u_int32_t supportSSDPatrolRead:1; 1862 u_int32_t realTimeScheduler:1; 1863 1864 u_int32_t supportResetNow:1; 1865 u_int32_t supportEmulatedDrives:1; 1866 u_int32_t headlessMode:1; 1867 u_int32_t dedicatedHotSparesLimited:1; 1868 1869 1870 u_int32_t supportUnevenSpans:1; 1871 u_int32_t reserved:11; 1872 } adapterOperations2; 1873 1874 u_int8_t driverVersion[32]; /* 0x7A8 */ 1875 u_int8_t maxDAPdCountSpinup60; /* 0x7C8 */ 1876 u_int8_t temperatureROC; /* 0x7C9 */ 1877 u_int8_t temperatureCtrl; /* 0x7CA */ 1878 u_int8_t reserved4; /* 0x7CB */ 1879 u_int16_t maxConfigurablePds; /* 0x7CC */ 1880 1881 1882 u_int8_t reserved5[2]; /* 0x7CD reserved */ 1883 1884 struct { 1885 u_int32_t peerIsPresent:1; 1886 u_int32_t peerIsIncompatible:1; 1887 1888 u_int32_t hwIncompatible:1; 1889 u_int32_t fwVersionMismatch:1; 1890 u_int32_t ctrlPropIncompatible:1; 1891 u_int32_t premiumFeatureMismatch:1; 1892 u_int32_t reserved:26; 1893 } cluster; 1894 1895 char clusterId[16]; /* 0x7D4 */ 1896 1897 char reserved6[4]; /* 0x7E4 RESERVED FOR IOV */ 1898 1899 struct { /* 0x7E8 */ 1900 u_int32_t resrved:5; 1901 u_int32_t supportMaxExtLDs:1; 1902 u_int32_t reserved1:26; 1903 } adapterOperations3; 1904 1905 u_int8_t pad[0x800 - 0x7EC]; /* 0x7EC */ 1906 } __packed; 1907 1908 /* 1909 * When SCSI mid-layer calls driver's reset routine, driver waits for 1910 * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 1911 * that the driver cannot _actually_ abort or reset pending commands. While 1912 * it is waiting for the commands to complete, it prints a diagnostic message 1913 * every MRSAS_RESET_NOTICE_INTERVAL seconds 1914 */ 1915 #define MRSAS_RESET_WAIT_TIME 180 1916 #define MRSAS_INTERNAL_CMD_WAIT_TIME 180 1917 #define MRSAS_IOC_INIT_WAIT_TIME 60 1918 #define MRSAS_RESET_NOTICE_INTERVAL 5 1919 #define MRSAS_IOCTL_CMD 0 1920 #define MRSAS_DEFAULT_CMD_TIMEOUT 90 1921 #define MRSAS_THROTTLE_QUEUE_DEPTH 16 1922 1923 /* 1924 * MSI-x regsiters offset defines 1925 */ 1926 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) 1927 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 1928 #define MR_MAX_REPLY_QUEUES_OFFSET (0x0000001F) 1929 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET (0x003FC000) 1930 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14 1931 #define MR_MAX_MSIX_REG_ARRAY 16 1932 1933 /* 1934 * FW reports the maximum of number of commands that it can accept (maximum 1935 * commands that can be outstanding) at any time. The driver must report a 1936 * lower number to the mid layer because it can issue a few internal commands 1937 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 1938 * is shown below 1939 */ 1940 #define MRSAS_INT_CMDS 32 1941 #define MRSAS_SKINNY_INT_CMDS 5 1942 #define MRSAS_MAX_MSIX_QUEUES 128 1943 1944 /* 1945 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit SGLs 1946 * based on the size of bus_addr_t 1947 */ 1948 #define IS_DMA64 (sizeof(bus_addr_t) == 8) 1949 1950 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 1951 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 1952 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 1953 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 1954 1955 #define MFI_OB_INTR_STATUS_MASK 0x00000002 1956 #define MFI_POLL_TIMEOUT_SECS 60 1957 1958 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 1959 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 1960 #define MFI_GEN2_ENABLE_INTERRUPT_MASK 0x00000001 1961 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 1962 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 1963 #define MFI_1068_PCSR_OFFSET 0x84 1964 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 1965 #define MFI_1068_FW_READY 0xDDDD0000 1966 1967 typedef union _MFI_CAPABILITIES { 1968 struct { 1969 u_int32_t support_fp_remote_lun:1; 1970 u_int32_t support_additional_msix:1; 1971 u_int32_t support_fastpath_wb:1; 1972 u_int32_t support_max_255lds:1; 1973 u_int32_t reserved:28; 1974 } mfi_capabilities; 1975 u_int32_t reg; 1976 } MFI_CAPABILITIES; 1977 1978 #pragma pack(1) 1979 struct mrsas_sge32 { 1980 u_int32_t phys_addr; 1981 u_int32_t length; 1982 }; 1983 1984 #pragma pack() 1985 1986 #pragma pack(1) 1987 struct mrsas_sge64 { 1988 u_int64_t phys_addr; 1989 u_int32_t length; 1990 }; 1991 1992 #pragma pack() 1993 1994 #pragma pack() 1995 union mrsas_sgl { 1996 struct mrsas_sge32 sge32[1]; 1997 struct mrsas_sge64 sge64[1]; 1998 }; 1999 2000 #pragma pack() 2001 2002 #pragma pack(1) 2003 struct mrsas_header { 2004 u_int8_t cmd; /* 00e */ 2005 u_int8_t sense_len; /* 01h */ 2006 u_int8_t cmd_status; /* 02h */ 2007 u_int8_t scsi_status; /* 03h */ 2008 2009 u_int8_t target_id; /* 04h */ 2010 u_int8_t lun; /* 05h */ 2011 u_int8_t cdb_len; /* 06h */ 2012 u_int8_t sge_count; /* 07h */ 2013 2014 u_int32_t context; /* 08h */ 2015 u_int32_t pad_0; /* 0Ch */ 2016 2017 u_int16_t flags; /* 10h */ 2018 u_int16_t timeout; /* 12h */ 2019 u_int32_t data_xferlen; /* 14h */ 2020 }; 2021 2022 #pragma pack() 2023 2024 #pragma pack(1) 2025 struct mrsas_init_frame { 2026 u_int8_t cmd; /* 00h */ 2027 u_int8_t reserved_0; /* 01h */ 2028 u_int8_t cmd_status; /* 02h */ 2029 2030 u_int8_t reserved_1; /* 03h */ 2031 MFI_CAPABILITIES driver_operations; /* 04h */ 2032 u_int32_t context; /* 08h */ 2033 u_int32_t pad_0; /* 0Ch */ 2034 2035 u_int16_t flags; /* 10h */ 2036 u_int16_t reserved_3; /* 12h */ 2037 u_int32_t data_xfer_len; /* 14h */ 2038 2039 u_int32_t queue_info_new_phys_addr_lo; /* 18h */ 2040 u_int32_t queue_info_new_phys_addr_hi; /* 1Ch */ 2041 u_int32_t queue_info_old_phys_addr_lo; /* 20h */ 2042 u_int32_t queue_info_old_phys_addr_hi; /* 24h */ 2043 u_int32_t driver_ver_lo; /* 28h */ 2044 u_int32_t driver_ver_hi; /* 2Ch */ 2045 u_int32_t reserved_4[4]; /* 30h */ 2046 }; 2047 2048 #pragma pack() 2049 2050 #pragma pack(1) 2051 struct mrsas_io_frame { 2052 u_int8_t cmd; /* 00h */ 2053 u_int8_t sense_len; /* 01h */ 2054 u_int8_t cmd_status; /* 02h */ 2055 u_int8_t scsi_status; /* 03h */ 2056 2057 u_int8_t target_id; /* 04h */ 2058 u_int8_t access_byte; /* 05h */ 2059 u_int8_t reserved_0; /* 06h */ 2060 u_int8_t sge_count; /* 07h */ 2061 2062 u_int32_t context; /* 08h */ 2063 u_int32_t pad_0; /* 0Ch */ 2064 2065 u_int16_t flags; /* 10h */ 2066 u_int16_t timeout; /* 12h */ 2067 u_int32_t lba_count; /* 14h */ 2068 2069 u_int32_t sense_buf_phys_addr_lo; /* 18h */ 2070 u_int32_t sense_buf_phys_addr_hi; /* 1Ch */ 2071 2072 u_int32_t start_lba_lo; /* 20h */ 2073 u_int32_t start_lba_hi; /* 24h */ 2074 2075 union mrsas_sgl sgl; /* 28h */ 2076 }; 2077 2078 #pragma pack() 2079 2080 #pragma pack(1) 2081 struct mrsas_pthru_frame { 2082 u_int8_t cmd; /* 00h */ 2083 u_int8_t sense_len; /* 01h */ 2084 u_int8_t cmd_status; /* 02h */ 2085 u_int8_t scsi_status; /* 03h */ 2086 2087 u_int8_t target_id; /* 04h */ 2088 u_int8_t lun; /* 05h */ 2089 u_int8_t cdb_len; /* 06h */ 2090 u_int8_t sge_count; /* 07h */ 2091 2092 u_int32_t context; /* 08h */ 2093 u_int32_t pad_0; /* 0Ch */ 2094 2095 u_int16_t flags; /* 10h */ 2096 u_int16_t timeout; /* 12h */ 2097 u_int32_t data_xfer_len; /* 14h */ 2098 2099 u_int32_t sense_buf_phys_addr_lo; /* 18h */ 2100 u_int32_t sense_buf_phys_addr_hi; /* 1Ch */ 2101 2102 u_int8_t cdb[16]; /* 20h */ 2103 union mrsas_sgl sgl; /* 30h */ 2104 }; 2105 2106 #pragma pack() 2107 2108 #pragma pack(1) 2109 struct mrsas_dcmd_frame { 2110 u_int8_t cmd; /* 00h */ 2111 u_int8_t reserved_0; /* 01h */ 2112 u_int8_t cmd_status; /* 02h */ 2113 u_int8_t reserved_1[4]; /* 03h */ 2114 u_int8_t sge_count; /* 07h */ 2115 2116 u_int32_t context; /* 08h */ 2117 u_int32_t pad_0; /* 0Ch */ 2118 2119 u_int16_t flags; /* 10h */ 2120 u_int16_t timeout; /* 12h */ 2121 2122 u_int32_t data_xfer_len; /* 14h */ 2123 u_int32_t opcode; /* 18h */ 2124 2125 union { /* 1Ch */ 2126 u_int8_t b[12]; 2127 u_int16_t s[6]; 2128 u_int32_t w[3]; 2129 } mbox; 2130 2131 union mrsas_sgl sgl; /* 28h */ 2132 }; 2133 2134 #pragma pack() 2135 2136 #pragma pack(1) 2137 struct mrsas_abort_frame { 2138 u_int8_t cmd; /* 00h */ 2139 u_int8_t reserved_0; /* 01h */ 2140 u_int8_t cmd_status; /* 02h */ 2141 2142 u_int8_t reserved_1; /* 03h */ 2143 MFI_CAPABILITIES driver_operations; /* 04h */ 2144 u_int32_t context; /* 08h */ 2145 u_int32_t pad_0; /* 0Ch */ 2146 2147 u_int16_t flags; /* 10h */ 2148 u_int16_t reserved_3; /* 12h */ 2149 u_int32_t reserved_4; /* 14h */ 2150 2151 u_int32_t abort_context; /* 18h */ 2152 u_int32_t pad_1; /* 1Ch */ 2153 2154 u_int32_t abort_mfi_phys_addr_lo; /* 20h */ 2155 u_int32_t abort_mfi_phys_addr_hi; /* 24h */ 2156 2157 u_int32_t reserved_5[6]; /* 28h */ 2158 }; 2159 2160 #pragma pack() 2161 2162 #pragma pack(1) 2163 struct mrsas_smp_frame { 2164 u_int8_t cmd; /* 00h */ 2165 u_int8_t reserved_1; /* 01h */ 2166 u_int8_t cmd_status; /* 02h */ 2167 u_int8_t connection_status; /* 03h */ 2168 2169 u_int8_t reserved_2[3]; /* 04h */ 2170 u_int8_t sge_count; /* 07h */ 2171 2172 u_int32_t context; /* 08h */ 2173 u_int32_t pad_0; /* 0Ch */ 2174 2175 u_int16_t flags; /* 10h */ 2176 u_int16_t timeout; /* 12h */ 2177 2178 u_int32_t data_xfer_len; /* 14h */ 2179 u_int64_t sas_addr; /* 18h */ 2180 2181 union { 2182 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: req */ 2183 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: req */ 2184 } sgl; 2185 }; 2186 2187 #pragma pack() 2188 2189 2190 #pragma pack(1) 2191 struct mrsas_stp_frame { 2192 u_int8_t cmd; /* 00h */ 2193 u_int8_t reserved_1; /* 01h */ 2194 u_int8_t cmd_status; /* 02h */ 2195 u_int8_t reserved_2; /* 03h */ 2196 2197 u_int8_t target_id; /* 04h */ 2198 u_int8_t reserved_3[2]; /* 05h */ 2199 u_int8_t sge_count; /* 07h */ 2200 2201 u_int32_t context; /* 08h */ 2202 u_int32_t pad_0; /* 0Ch */ 2203 2204 u_int16_t flags; /* 10h */ 2205 u_int16_t timeout; /* 12h */ 2206 2207 u_int32_t data_xfer_len; /* 14h */ 2208 2209 u_int16_t fis[10]; /* 18h */ 2210 u_int32_t stp_flags; 2211 2212 union { 2213 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: data */ 2214 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: data */ 2215 } sgl; 2216 }; 2217 2218 #pragma pack() 2219 2220 union mrsas_frame { 2221 struct mrsas_header hdr; 2222 struct mrsas_init_frame init; 2223 struct mrsas_io_frame io; 2224 struct mrsas_pthru_frame pthru; 2225 struct mrsas_dcmd_frame dcmd; 2226 struct mrsas_abort_frame abort; 2227 struct mrsas_smp_frame smp; 2228 struct mrsas_stp_frame stp; 2229 u_int8_t raw_bytes[64]; 2230 }; 2231 2232 #pragma pack(1) 2233 union mrsas_evt_class_locale { 2234 2235 struct { 2236 u_int16_t locale; 2237 u_int8_t reserved; 2238 int8_t class; 2239 } __packed members; 2240 2241 u_int32_t word; 2242 2243 } __packed; 2244 2245 #pragma pack() 2246 2247 2248 #pragma pack(1) 2249 struct mrsas_evt_log_info { 2250 u_int32_t newest_seq_num; 2251 u_int32_t oldest_seq_num; 2252 u_int32_t clear_seq_num; 2253 u_int32_t shutdown_seq_num; 2254 u_int32_t boot_seq_num; 2255 2256 } __packed; 2257 2258 #pragma pack() 2259 2260 struct mrsas_progress { 2261 2262 u_int16_t progress; 2263 u_int16_t elapsed_seconds; 2264 2265 } __packed; 2266 2267 struct mrsas_evtarg_ld { 2268 2269 u_int16_t target_id; 2270 u_int8_t ld_index; 2271 u_int8_t reserved; 2272 2273 } __packed; 2274 2275 struct mrsas_evtarg_pd { 2276 u_int16_t device_id; 2277 u_int8_t encl_index; 2278 u_int8_t slot_number; 2279 2280 } __packed; 2281 2282 struct mrsas_evt_detail { 2283 2284 u_int32_t seq_num; 2285 u_int32_t time_stamp; 2286 u_int32_t code; 2287 union mrsas_evt_class_locale cl; 2288 u_int8_t arg_type; 2289 u_int8_t reserved1[15]; 2290 2291 union { 2292 struct { 2293 struct mrsas_evtarg_pd pd; 2294 u_int8_t cdb_length; 2295 u_int8_t sense_length; 2296 u_int8_t reserved[2]; 2297 u_int8_t cdb[16]; 2298 u_int8_t sense[64]; 2299 } __packed cdbSense; 2300 2301 struct mrsas_evtarg_ld ld; 2302 2303 struct { 2304 struct mrsas_evtarg_ld ld; 2305 u_int64_t count; 2306 } __packed ld_count; 2307 2308 struct { 2309 u_int64_t lba; 2310 struct mrsas_evtarg_ld ld; 2311 } __packed ld_lba; 2312 2313 struct { 2314 struct mrsas_evtarg_ld ld; 2315 u_int32_t prevOwner; 2316 u_int32_t newOwner; 2317 } __packed ld_owner; 2318 2319 struct { 2320 u_int64_t ld_lba; 2321 u_int64_t pd_lba; 2322 struct mrsas_evtarg_ld ld; 2323 struct mrsas_evtarg_pd pd; 2324 } __packed ld_lba_pd_lba; 2325 2326 struct { 2327 struct mrsas_evtarg_ld ld; 2328 struct mrsas_progress prog; 2329 } __packed ld_prog; 2330 2331 struct { 2332 struct mrsas_evtarg_ld ld; 2333 u_int32_t prev_state; 2334 u_int32_t new_state; 2335 } __packed ld_state; 2336 2337 struct { 2338 u_int64_t strip; 2339 struct mrsas_evtarg_ld ld; 2340 } __packed ld_strip; 2341 2342 struct mrsas_evtarg_pd pd; 2343 2344 struct { 2345 struct mrsas_evtarg_pd pd; 2346 u_int32_t err; 2347 } __packed pd_err; 2348 2349 struct { 2350 u_int64_t lba; 2351 struct mrsas_evtarg_pd pd; 2352 } __packed pd_lba; 2353 2354 struct { 2355 u_int64_t lba; 2356 struct mrsas_evtarg_pd pd; 2357 struct mrsas_evtarg_ld ld; 2358 } __packed pd_lba_ld; 2359 2360 struct { 2361 struct mrsas_evtarg_pd pd; 2362 struct mrsas_progress prog; 2363 } __packed pd_prog; 2364 2365 struct { 2366 struct mrsas_evtarg_pd pd; 2367 u_int32_t prevState; 2368 u_int32_t newState; 2369 } __packed pd_state; 2370 2371 struct { 2372 u_int16_t vendorId; 2373 u_int16_t deviceId; 2374 u_int16_t subVendorId; 2375 u_int16_t subDeviceId; 2376 } __packed pci; 2377 2378 u_int32_t rate; 2379 char str[96]; 2380 2381 struct { 2382 u_int32_t rtc; 2383 u_int32_t elapsedSeconds; 2384 } __packed time; 2385 2386 struct { 2387 u_int32_t ecar; 2388 u_int32_t elog; 2389 char str[64]; 2390 } __packed ecc; 2391 2392 u_int8_t b[96]; 2393 u_int16_t s[48]; 2394 u_int32_t w[24]; 2395 u_int64_t d[12]; 2396 } args; 2397 2398 char description[128]; 2399 2400 } __packed; 2401 2402 struct mrsas_irq_context { 2403 struct mrsas_softc *sc; 2404 uint32_t MSIxIndex; 2405 }; 2406 2407 /* Controller management info added to support Linux Emulator */ 2408 #define MAX_MGMT_ADAPTERS 1024 2409 2410 struct mrsas_mgmt_info { 2411 u_int16_t count; 2412 struct mrsas_softc *sc_ptr[MAX_MGMT_ADAPTERS]; 2413 int max_index; 2414 }; 2415 2416 /******************************************************************* 2417 * per-instance data 2418 ********************************************************************/ 2419 struct mrsas_softc { 2420 device_t mrsas_dev; 2421 struct cdev *mrsas_cdev; 2422 uint16_t device_id; 2423 struct resource *reg_res; 2424 int reg_res_id; 2425 bus_space_tag_t bus_tag; 2426 bus_space_handle_t bus_handle; 2427 bus_dma_tag_t mrsas_parent_tag; 2428 bus_dma_tag_t verbuf_tag; 2429 bus_dmamap_t verbuf_dmamap; 2430 void *verbuf_mem; 2431 bus_addr_t verbuf_phys_addr; 2432 bus_dma_tag_t sense_tag; 2433 bus_dmamap_t sense_dmamap; 2434 void *sense_mem; 2435 bus_addr_t sense_phys_addr; 2436 bus_dma_tag_t io_request_tag; 2437 bus_dmamap_t io_request_dmamap; 2438 void *io_request_mem; 2439 bus_addr_t io_request_phys_addr; 2440 bus_dma_tag_t chain_frame_tag; 2441 bus_dmamap_t chain_frame_dmamap; 2442 void *chain_frame_mem; 2443 bus_addr_t chain_frame_phys_addr; 2444 bus_dma_tag_t reply_desc_tag; 2445 bus_dmamap_t reply_desc_dmamap; 2446 void *reply_desc_mem; 2447 bus_addr_t reply_desc_phys_addr; 2448 bus_dma_tag_t ioc_init_tag; 2449 bus_dmamap_t ioc_init_dmamap; 2450 void *ioc_init_mem; 2451 bus_addr_t ioc_init_phys_mem; 2452 bus_dma_tag_t data_tag; 2453 struct cam_sim *sim_0; 2454 struct cam_sim *sim_1; 2455 struct cam_path *path_0; 2456 struct cam_path *path_1; 2457 struct mtx sim_lock; 2458 struct mtx pci_lock; 2459 struct mtx io_lock; 2460 struct mtx ioctl_lock; 2461 struct mtx mpt_cmd_pool_lock; 2462 struct mtx mfi_cmd_pool_lock; 2463 struct mtx raidmap_lock; 2464 struct mtx aen_lock; 2465 struct selinfo mrsas_select; 2466 uint32_t mrsas_aen_triggered; 2467 uint32_t mrsas_poll_waiting; 2468 2469 struct sema ioctl_count_sema; 2470 uint32_t max_fw_cmds; 2471 uint32_t max_num_sge; 2472 struct resource *mrsas_irq[MAX_MSIX_COUNT]; 2473 void *intr_handle[MAX_MSIX_COUNT]; 2474 int irq_id[MAX_MSIX_COUNT]; 2475 struct mrsas_irq_context irq_context[MAX_MSIX_COUNT]; 2476 int msix_vectors; 2477 int msix_enable; 2478 uint32_t msix_reg_offset[16]; 2479 struct mrsas_mpt_cmd **mpt_cmd_list; 2480 struct mrsas_mfi_cmd **mfi_cmd_list; 2481 TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head; 2482 TAILQ_HEAD(, mrsas_mfi_cmd) mrsas_mfi_cmd_list_head; 2483 bus_addr_t req_frames_desc_phys; 2484 u_int8_t *req_frames_desc; 2485 u_int8_t *req_desc; 2486 bus_addr_t io_request_frames_phys; 2487 u_int8_t *io_request_frames; 2488 bus_addr_t reply_frames_desc_phys; 2489 u_int16_t last_reply_idx[MAX_MSIX_COUNT]; 2490 u_int32_t reply_q_depth; 2491 u_int32_t request_alloc_sz; 2492 u_int32_t reply_alloc_sz; 2493 u_int32_t io_frames_alloc_sz; 2494 u_int32_t chain_frames_alloc_sz; 2495 u_int16_t max_sge_in_main_msg; 2496 u_int16_t max_sge_in_chain; 2497 u_int8_t chain_offset_io_request; 2498 u_int8_t chain_offset_mfi_pthru; 2499 u_int32_t map_sz; 2500 u_int64_t map_id; 2501 struct mrsas_mfi_cmd *map_update_cmd; 2502 struct mrsas_mfi_cmd *aen_cmd; 2503 u_int8_t fast_path_io; 2504 void *chan; 2505 void *ocr_chan; 2506 u_int8_t adprecovery; 2507 u_int8_t remove_in_progress; 2508 u_int8_t ocr_thread_active; 2509 u_int8_t do_timedout_reset; 2510 u_int32_t reset_in_progress; 2511 u_int32_t reset_count; 2512 bus_dma_tag_t raidmap_tag[2]; 2513 bus_dmamap_t raidmap_dmamap[2]; 2514 void *raidmap_mem[2]; 2515 bus_addr_t raidmap_phys_addr[2]; 2516 bus_dma_tag_t mficmd_frame_tag; 2517 bus_dma_tag_t mficmd_sense_tag; 2518 bus_dma_tag_t evt_detail_tag; 2519 bus_dmamap_t evt_detail_dmamap; 2520 struct mrsas_evt_detail *evt_detail_mem; 2521 bus_addr_t evt_detail_phys_addr; 2522 bus_dma_tag_t ctlr_info_tag; 2523 bus_dmamap_t ctlr_info_dmamap; 2524 void *ctlr_info_mem; 2525 bus_addr_t ctlr_info_phys_addr; 2526 u_int32_t max_sectors_per_req; 2527 u_int32_t disableOnlineCtrlReset; 2528 mrsas_atomic_t fw_outstanding; 2529 u_int32_t mrsas_debug; 2530 u_int32_t mrsas_io_timeout; 2531 u_int32_t mrsas_fw_fault_check_delay; 2532 u_int32_t io_cmds_highwater; 2533 u_int8_t UnevenSpanSupport; 2534 struct sysctl_ctx_list sysctl_ctx; 2535 struct sysctl_oid *sysctl_tree; 2536 struct proc *ocr_thread; 2537 u_int32_t last_seq_num; 2538 bus_dma_tag_t el_info_tag; 2539 bus_dmamap_t el_info_dmamap; 2540 void *el_info_mem; 2541 bus_addr_t el_info_phys_addr; 2542 struct mrsas_pd_list pd_list[MRSAS_MAX_PD]; 2543 struct mrsas_pd_list local_pd_list[MRSAS_MAX_PD]; 2544 u_int8_t ld_ids[MRSAS_MAX_LD_IDS]; 2545 struct taskqueue *ev_tq; 2546 struct task ev_task; 2547 u_int32_t CurLdCount; 2548 u_int64_t reset_flags; 2549 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT]; 2550 LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT]; 2551 2552 u_int8_t max256vdSupport; 2553 u_int16_t fw_supported_vd_count; 2554 u_int16_t fw_supported_pd_count; 2555 2556 u_int16_t drv_supported_vd_count; 2557 u_int16_t drv_supported_pd_count; 2558 2559 u_int32_t max_map_sz; 2560 u_int32_t current_map_sz; 2561 u_int32_t old_map_sz; 2562 u_int32_t new_map_sz; 2563 u_int32_t drv_map_sz; 2564 2565 /* Non dma-able memory. Driver local copy. */ 2566 MR_DRV_RAID_MAP_ALL *ld_drv_map[2]; 2567 }; 2568 2569 /* Compatibility shims for different OS versions */ 2570 #if __FreeBSD_version >= 800001 2571 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 2572 kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 2573 #define mrsas_kproc_exit(arg) kproc_exit(arg) 2574 #else 2575 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 2576 kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 2577 #define mrsas_kproc_exit(arg) kthread_exit(arg) 2578 #endif 2579 2580 static __inline void 2581 mrsas_clear_bit(int b, volatile void *p) 2582 { 2583 atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 2584 } 2585 2586 static __inline void 2587 mrsas_set_bit(int b, volatile void *p) 2588 { 2589 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 2590 } 2591 2592 static __inline int 2593 mrsas_test_bit(int b, volatile void *p) 2594 { 2595 return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f)); 2596 } 2597 2598 #endif /* MRSAS_H */ 2599