1 /* 2 * Copyright (c) 2015, AVAGO Tech. All rights reserved. Authors: Marian Choy 3 * Copyright (c) 2014, LSI Corp. All rights reserved. Authors: Marian Choy 4 * Support: freebsdraid@avagotech.com 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 2. Redistributions 12 * in binary form must reproduce the above copyright notice, this list of 13 * conditions and the following disclaimer in the documentation and/or other 14 * materials provided with the distribution. 3. Neither the name of the 15 * <ORGANIZATION> nor the names of its contributors may be used to endorse or 16 * promote products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * The views and conclusions contained in the software and documentation are 32 * those of the authors and should not be interpreted as representing 33 * official policies,either expressed or implied, of the FreeBSD Project. 34 * 35 * Send feedback to: <megaraidfbsd@avagotech.com> Mail to: AVAGO TECHNOLOGIES, 1621 36 * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD 37 * 38 */ 39 40 #include <sys/cdefs.h> 41 __FBSDID("$FreeBSD$"); 42 43 #ifndef MRSAS_H 44 #define MRSAS_H 45 46 #include <sys/param.h> /* defines used in kernel.h */ 47 #include <sys/module.h> 48 #include <sys/systm.h> 49 #include <sys/proc.h> 50 #include <sys/errno.h> 51 #include <sys/kernel.h> /* types used in module initialization */ 52 #include <sys/conf.h> /* cdevsw struct */ 53 #include <sys/uio.h> /* uio struct */ 54 #include <sys/malloc.h> 55 #include <sys/bus.h> /* structs, prototypes for pci bus 56 * stuff */ 57 #include <sys/rman.h> 58 #include <sys/types.h> 59 #include <sys/lock.h> 60 #include <sys/mutex.h> 61 #include <sys/sema.h> 62 #include <sys/sysctl.h> 63 #include <sys/stat.h> 64 #include <sys/taskqueue.h> 65 #include <sys/poll.h> 66 #include <sys/selinfo.h> 67 68 #include <machine/bus.h> 69 #include <machine/resource.h> 70 #include <machine/atomic.h> 71 72 #include <dev/pci/pcivar.h> /* For pci_get macros! */ 73 #include <dev/pci/pcireg.h> 74 75 #define IOCTL_SEMA_DESCRIPTION "mrsas semaphore for MFI pool" 76 77 /* 78 * Device IDs and PCI 79 */ 80 #define MRSAS_TBOLT 0x005b 81 #define MRSAS_INVADER 0x005d 82 #define MRSAS_FURY 0x005f 83 #define MRSAS_INTRUDER 0x00ce 84 #define MRSAS_INTRUDER_24 0x00cf 85 #define MRSAS_CUTLASS_52 0x0052 86 #define MRSAS_CUTLASS_53 0x0053 87 /* Gen3.5 Conroller */ 88 #define MRSAS_VENTURA 0x0014 89 #define MRSAS_CRUSADER 0x0015 90 #define MRSAS_HARPOON 0x0016 91 #define MRSAS_TOMCAT 0x0017 92 #define MRSAS_VENTURA_4PORT 0x001B 93 #define MRSAS_CRUSADER_4PORT 0x001C 94 #define MRSAS_AERO_10E0 0x10E0 95 #define MRSAS_AERO_10E1 0x10E1 96 #define MRSAS_AERO_10E2 0x10E2 97 #define MRSAS_AERO_10E3 0x10E3 98 #define MRSAS_AERO_10E4 0x10E4 99 #define MRSAS_AERO_10E5 0x10E5 100 #define MRSAS_AERO_10E6 0x10E6 101 #define MRSAS_AERO_10E7 0x10E7 102 103 /* 104 * Firmware State Defines 105 */ 106 #define MRSAS_FWSTATE_MAXCMD_MASK 0x0000FFFF 107 #define MRSAS_FWSTATE_SGE_MASK 0x00FF0000 108 #define MRSAS_FW_STATE_CHNG_INTERRUPT 1 109 110 /* 111 * Message Frame Defines 112 */ 113 #define MRSAS_SENSE_LEN 96 114 #define MRSAS_FUSION_MAX_RESET_TRIES 3 115 116 /* 117 * Miscellaneous Defines 118 */ 119 #define BYTE_ALIGNMENT 1 120 #define MRSAS_MAX_NAME_LENGTH 32 121 #define MRSAS_VERSION "07.709.04.00-fbsd" 122 #define MRSAS_ULONG_MAX 0xFFFFFFFFFFFFFFFF 123 #define MRSAS_DEFAULT_TIMEOUT 0x14 /* Temporarily set */ 124 #define DONE 0 125 #define MRSAS_PAGE_SIZE 4096 126 #define MRSAS_RESET_NOTICE_INTERVAL 5 127 #define MRSAS_IO_TIMEOUT 180000 /* 180 second timeout */ 128 #define MRSAS_LDIO_QUEUE_DEPTH 70 /* 70 percent as default */ 129 #define THRESHOLD_REPLY_COUNT 50 130 #define MAX_MSIX_COUNT 128 131 132 #define MAX_STREAMS_TRACKED 8 133 #define MR_STREAM_BITMAP 0x76543210 134 #define BITS_PER_INDEX_STREAM 4 /* number of bits per index in U32 TrackStream */ 135 #define STREAM_MASK ((1 << BITS_PER_INDEX_STREAM) - 1) 136 #define ZERO_LAST_STREAM 0x0fffffff 137 138 /* 139 * Boolean types 140 */ 141 #if (__FreeBSD_version < 901000) 142 typedef enum _boolean { 143 false, true 144 } boolean; 145 146 #endif 147 enum err { 148 SUCCESS, FAIL 149 }; 150 151 MALLOC_DECLARE(M_MRSAS); 152 SYSCTL_DECL(_hw_mrsas); 153 154 #define MRSAS_INFO (1 << 0) 155 #define MRSAS_TRACE (1 << 1) 156 #define MRSAS_FAULT (1 << 2) 157 #define MRSAS_OCR (1 << 3) 158 #define MRSAS_TOUT MRSAS_OCR 159 #define MRSAS_AEN (1 << 4) 160 #define MRSAS_PRL11 (1 << 5) 161 162 #define mrsas_dprint(sc, level, msg, args...) \ 163 do { \ 164 if (sc->mrsas_debug & level) \ 165 device_printf(sc->mrsas_dev, msg, ##args); \ 166 } while (0) 167 168 #define le32_to_cpus(x) do { *((u_int32_t *)(x)) = le32toh((*(u_int32_t *)x)); } while (0) 169 #define le16_to_cpus(x) do { *((u_int16_t *)(x)) = le16toh((*(u_int16_t *)x)); } while (0) 170 171 /**************************************************************************** 172 * Raid Context structure which describes MegaRAID specific IO Paramenters 173 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 174 ****************************************************************************/ 175 176 typedef struct _RAID_CONTEXT { 177 #if _BYTE_ORDER == _LITTLE_ENDIAN 178 u_int8_t Type:4; 179 u_int8_t nseg:4; 180 #else 181 u_int8_t nseg:4; 182 u_int8_t Type:4; 183 #endif 184 u_int8_t resvd0; 185 u_int16_t timeoutValue; 186 u_int8_t regLockFlags; 187 u_int8_t resvd1; 188 u_int16_t VirtualDiskTgtId; 189 u_int64_t regLockRowLBA; 190 u_int32_t regLockLength; 191 u_int16_t nextLMId; 192 u_int8_t exStatus; 193 u_int8_t status; 194 u_int8_t RAIDFlags; 195 u_int8_t numSGE; 196 u_int16_t configSeqNum; 197 u_int8_t spanArm; 198 u_int8_t priority; /* 0x1D MR_PRIORITY_RANGE */ 199 u_int8_t numSGEExt; /* 0x1E 1M IO support */ 200 u_int8_t resvd2; /* 0x1F */ 201 } RAID_CONTEXT; 202 203 /* 204 * Raid Context structure which describes ventura MegaRAID specific IO Paramenters 205 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 206 */ 207 typedef struct _RAID_CONTEXT_G35 { 208 #if _BYTE_ORDER == _LITTLE_ENDIAN 209 u_int16_t Type:4; 210 u_int16_t nseg:4; 211 u_int16_t resvd0:8; 212 #else 213 u_int16_t resvd0:8; 214 u_int16_t nseg:4; 215 u_int16_t Type:4; 216 #endif 217 u_int16_t timeoutValue; 218 union { 219 struct { 220 #if _BYTE_ORDER == _LITTLE_ENDIAN 221 u_int16_t reserved:1; 222 u_int16_t sld:1; 223 u_int16_t c2f:1; 224 u_int16_t fwn:1; 225 u_int16_t sqn:1; 226 u_int16_t sbs:1; 227 u_int16_t rw:1; 228 u_int16_t log:1; 229 u_int16_t cpuSel:4; 230 u_int16_t setDivert:4; 231 #else 232 u_int16_t setDivert:4; 233 u_int16_t cpuSel:4; 234 u_int16_t log:1; 235 u_int16_t rw:1; 236 u_int16_t sbs:1; 237 u_int16_t sqn:1; 238 u_int16_t fwn:1; 239 u_int16_t c2f:1; 240 u_int16_t sld:1; 241 u_int16_t reserved:1; 242 #endif 243 } bits; 244 u_int16_t s; 245 } routingFlags; 246 u_int16_t VirtualDiskTgtId; 247 u_int64_t regLockRowLBA; 248 u_int32_t regLockLength; 249 union { 250 u_int16_t nextLMId; 251 u_int16_t peerSMID; 252 } smid; 253 u_int8_t exStatus; 254 u_int8_t status; 255 u_int8_t RAIDFlags; 256 u_int8_t spanArm; 257 u_int16_t configSeqNum; 258 #if _BYTE_ORDER == _LITTLE_ENDIAN 259 u_int16_t numSGE:12; 260 u_int16_t reserved:3; 261 u_int16_t streamDetected:1; 262 #else 263 u_int16_t streamDetected:1; 264 u_int16_t reserved:3; 265 u_int16_t numSGE:12; 266 #endif 267 u_int8_t resvd2[2]; 268 } RAID_CONTEXT_G35; 269 270 typedef union _RAID_CONTEXT_UNION { 271 RAID_CONTEXT raid_context; 272 RAID_CONTEXT_G35 raid_context_g35; 273 } RAID_CONTEXT_UNION, *PRAID_CONTEXT_UNION; 274 275 /************************************************************************* 276 * MPI2 Defines 277 ************************************************************************/ 278 279 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 280 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 281 #define MPI2_VERSION_MAJOR (0x02) 282 #define MPI2_VERSION_MINOR (0x00) 283 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 284 #define MPI2_VERSION_MAJOR_SHIFT (8) 285 #define MPI2_VERSION_MINOR_MASK (0x00FF) 286 #define MPI2_VERSION_MINOR_SHIFT (0) 287 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 288 MPI2_VERSION_MINOR) 289 #define MPI2_HEADER_VERSION_UNIT (0x10) 290 #define MPI2_HEADER_VERSION_DEV (0x00) 291 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 292 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 293 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 294 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 295 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 296 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 297 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) 298 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) 299 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) 300 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) 301 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) 302 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) 303 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 304 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) 305 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x03) 306 #define MPI2_REQ_DESCRIPT_FLAGS_FP_IO (0x06) 307 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 308 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 309 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 310 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 311 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 312 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 313 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 314 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 315 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 316 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 317 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 318 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 319 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 320 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 321 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 322 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 323 324 #ifndef MPI2_POINTER 325 #define MPI2_POINTER * 326 #endif 327 328 /*************************************** 329 * MPI2 Structures 330 ***************************************/ 331 332 typedef struct _MPI25_IEEE_SGE_CHAIN64 { 333 u_int64_t Address; 334 u_int32_t Length; 335 u_int16_t Reserved1; 336 u_int8_t NextChainOffset; 337 u_int8_t Flags; 338 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, 339 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t; 340 341 typedef struct _MPI2_SGE_SIMPLE_UNION { 342 u_int32_t FlagsLength; 343 union { 344 u_int32_t Address32; 345 u_int64_t Address64; 346 } u; 347 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 348 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 349 350 typedef struct { 351 u_int8_t CDB[20]; /* 0x00 */ 352 u_int32_t PrimaryReferenceTag; /* 0x14 */ 353 u_int16_t PrimaryApplicationTag;/* 0x18 */ 354 u_int16_t PrimaryApplicationTagMask; /* 0x1A */ 355 u_int32_t TransferLength; /* 0x1C */ 356 } MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32, 357 Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t; 358 359 typedef struct _MPI2_SGE_CHAIN_UNION { 360 u_int16_t Length; 361 u_int8_t NextChainOffset; 362 u_int8_t Flags; 363 union { 364 u_int32_t Address32; 365 u_int64_t Address64; 366 } u; 367 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 368 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 369 370 typedef struct _MPI2_IEEE_SGE_SIMPLE32 { 371 u_int32_t Address; 372 u_int32_t FlagsLength; 373 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 374 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 375 typedef struct _MPI2_IEEE_SGE_SIMPLE64 { 376 u_int64_t Address; 377 u_int32_t Length; 378 u_int16_t Reserved1; 379 u_int8_t Reserved2; 380 u_int8_t Flags; 381 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 382 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 383 384 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 385 MPI2_IEEE_SGE_SIMPLE32 Simple32; 386 MPI2_IEEE_SGE_SIMPLE64 Simple64; 387 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 388 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 389 390 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 391 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 392 393 typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 394 MPI2_IEEE_SGE_CHAIN32 Chain32; 395 MPI2_IEEE_SGE_CHAIN64 Chain64; 396 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 397 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 398 399 typedef union _MPI2_SGE_IO_UNION { 400 MPI2_SGE_SIMPLE_UNION MpiSimple; 401 MPI2_SGE_CHAIN_UNION MpiChain; 402 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 403 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 404 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 405 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 406 407 typedef union { 408 u_int8_t CDB32[32]; 409 MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 410 MPI2_SGE_SIMPLE_UNION SGE; 411 } MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION, 412 Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t; 413 414 /**************************************************************************** 415 * * SCSI Task Management messages 416 * ****************************************************************************/ 417 418 /*SCSI Task Management Request Message */ 419 typedef struct _MPI2_SCSI_TASK_MANAGE_REQUEST { 420 u_int16_t DevHandle; /*0x00 */ 421 u_int8_t ChainOffset; /*0x02 */ 422 u_int8_t Function; /*0x03 */ 423 u_int8_t Reserved1; /*0x04 */ 424 u_int8_t TaskType; /*0x05 */ 425 u_int8_t Reserved2; /*0x06 */ 426 u_int8_t MsgFlags; /*0x07 */ 427 u_int8_t VP_ID; /*0x08 */ 428 u_int8_t VF_ID; /*0x09 */ 429 u_int16_t Reserved3; /*0x0A */ 430 u_int8_t LUN[8]; /*0x0C */ 431 u_int32_t Reserved4[7]; /*0x14 */ 432 u_int16_t TaskMID; /*0x30 */ 433 u_int16_t Reserved5; /*0x32 */ 434 } MPI2_SCSI_TASK_MANAGE_REQUEST; 435 436 /*SCSI Task Management Reply Message */ 437 typedef struct _MPI2_SCSI_TASK_MANAGE_REPLY { 438 u_int16_t DevHandle; /*0x00 */ 439 u_int8_t MsgLength; /*0x02 */ 440 u_int8_t Function; /*0x03 */ 441 u_int8_t ResponseCode; /*0x04 */ 442 u_int8_t TaskType; /*0x05 */ 443 u_int8_t Reserved1; /*0x06 */ 444 u_int8_t MsgFlags; /*0x07 */ 445 u_int8_t VP_ID; /*0x08 */ 446 u_int8_t VF_ID; /*0x09 */ 447 u_int16_t Reserved2; /*0x0A */ 448 u_int16_t Reserved3; /*0x0C */ 449 u_int16_t IOCStatus; /*0x0E */ 450 u_int32_t IOCLogInfo; /*0x10 */ 451 u_int32_t TerminationCount; /*0x14 */ 452 u_int32_t ResponseInfo; /*0x18 */ 453 } MPI2_SCSI_TASK_MANAGE_REPLY; 454 455 typedef struct _MR_TM_REQUEST { 456 char request[128]; 457 } MR_TM_REQUEST; 458 459 typedef struct _MR_TM_REPLY { 460 char reply[128]; 461 } MR_TM_REPLY; 462 463 /* SCSI Task Management Request Message */ 464 typedef struct _MR_TASK_MANAGE_REQUEST { 465 /*To be type casted to struct MPI2_SCSI_TASK_MANAGE_REQUEST */ 466 MR_TM_REQUEST TmRequest; 467 union { 468 struct { 469 #if _BYTE_ORDER == _LITTLE_ENDIAN 470 u_int32_t isTMForLD:1; 471 u_int32_t isTMForPD:1; 472 u_int32_t reserved1:30; 473 #else 474 u_int32_t reserved1:30; 475 u_int32_t isTMForPD:1; 476 u_int32_t isTMForLD:1; 477 #endif 478 u_int32_t reserved2; 479 } tmReqFlags; 480 MR_TM_REPLY TMReply; 481 } uTmReqReply; 482 } MR_TASK_MANAGE_REQUEST; 483 484 /* TaskType values */ 485 #define MPI2_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01) 486 #define MPI2_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02) 487 #define MPI2_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03) 488 #define MPI2_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05) 489 #define MPI2_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06) 490 #define MPI2_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07) 491 #define MPI2_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08) 492 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_TASK_SET (0x09) 493 #define MPI2_SCSITASKMGMT_TASKTYPE_QRY_ASYNC_EVENT (0x0A) 494 495 /* ResponseCode values */ 496 #define MPI2_SCSITASKMGMT_RSP_TM_COMPLETE (0x00) 497 #define MPI2_SCSITASKMGMT_RSP_INVALID_FRAME (0x02) 498 #define MPI2_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04) 499 #define MPI2_SCSITASKMGMT_RSP_TM_FAILED (0x05) 500 #define MPI2_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08) 501 #define MPI2_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09) 502 #define MPI2_SCSITASKMGMT_RSP_TM_OVERLAPPED_TAG (0x0A) 503 #define MPI2_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80) 504 505 /* 506 * RAID SCSI IO Request Message Total SGE count will be one less than 507 * _MPI2_SCSI_IO_REQUEST 508 */ 509 typedef struct _MPI2_RAID_SCSI_IO_REQUEST { 510 u_int16_t DevHandle; /* 0x00 */ 511 u_int8_t ChainOffset; /* 0x02 */ 512 u_int8_t Function; /* 0x03 */ 513 u_int16_t Reserved1; /* 0x04 */ 514 u_int8_t Reserved2; /* 0x06 */ 515 u_int8_t MsgFlags; /* 0x07 */ 516 u_int8_t VP_ID; /* 0x08 */ 517 u_int8_t VF_ID; /* 0x09 */ 518 u_int16_t Reserved3; /* 0x0A */ 519 u_int32_t SenseBufferLowAddress;/* 0x0C */ 520 u_int16_t SGLFlags; /* 0x10 */ 521 u_int8_t SenseBufferLength; /* 0x12 */ 522 u_int8_t Reserved4; /* 0x13 */ 523 u_int8_t SGLOffset0; /* 0x14 */ 524 u_int8_t SGLOffset1; /* 0x15 */ 525 u_int8_t SGLOffset2; /* 0x16 */ 526 u_int8_t SGLOffset3; /* 0x17 */ 527 u_int32_t SkipCount; /* 0x18 */ 528 u_int32_t DataLength; /* 0x1C */ 529 u_int32_t BidirectionalDataLength; /* 0x20 */ 530 u_int16_t IoFlags; /* 0x24 */ 531 u_int16_t EEDPFlags; /* 0x26 */ 532 u_int32_t EEDPBlockSize; /* 0x28 */ 533 u_int32_t SecondaryReferenceTag;/* 0x2C */ 534 u_int16_t SecondaryApplicationTag; /* 0x30 */ 535 u_int16_t ApplicationTagTranslationMask; /* 0x32 */ 536 u_int8_t LUN[8]; /* 0x34 */ 537 u_int32_t Control; /* 0x3C */ 538 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 539 RAID_CONTEXT_UNION RaidContext; /* 0x60 */ 540 MPI2_SGE_IO_UNION SGL; /* 0x80 */ 541 } MRSAS_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MRSAS_RAID_SCSI_IO_REQUEST, 542 MRSASRaidSCSIIORequest_t, MPI2_POINTER pMRSASRaidSCSIIORequest_t; 543 544 /* 545 * MPT RAID MFA IO Descriptor. 546 */ 547 typedef struct _MRSAS_RAID_MFA_IO_DESCRIPTOR { 548 u_int32_t RequestFlags:8; 549 u_int32_t MessageAddress1:24; /* bits 31:8 */ 550 u_int32_t MessageAddress2; /* bits 61:32 */ 551 } MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR, *PMRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR; 552 553 /* Default Request Descriptor */ 554 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR { 555 u_int8_t RequestFlags; /* 0x00 */ 556 u_int8_t MSIxIndex; /* 0x01 */ 557 u_int16_t SMID; /* 0x02 */ 558 u_int16_t LMID; /* 0x04 */ 559 u_int16_t DescriptorTypeDependent; /* 0x06 */ 560 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 561 562 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 563 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 564 565 /* High Priority Request Descriptor */ 566 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { 567 u_int8_t RequestFlags; /* 0x00 */ 568 u_int8_t MSIxIndex; /* 0x01 */ 569 u_int16_t SMID; /* 0x02 */ 570 u_int16_t LMID; /* 0x04 */ 571 u_int16_t Reserved1; /* 0x06 */ 572 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 573 574 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 575 Mpi2HighPriorityRequestDescriptor_t, MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 576 577 /* SCSI IO Request Descriptor */ 578 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR { 579 u_int8_t RequestFlags; /* 0x00 */ 580 u_int8_t MSIxIndex; /* 0x01 */ 581 u_int16_t SMID; /* 0x02 */ 582 u_int16_t LMID; /* 0x04 */ 583 u_int16_t DevHandle; /* 0x06 */ 584 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 585 586 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 587 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 588 589 /* SCSI Target Request Descriptor */ 590 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { 591 u_int8_t RequestFlags; /* 0x00 */ 592 u_int8_t MSIxIndex; /* 0x01 */ 593 u_int16_t SMID; /* 0x02 */ 594 u_int16_t LMID; /* 0x04 */ 595 u_int16_t IoIndex; /* 0x06 */ 596 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 597 598 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 599 Mpi2SCSITargetRequestDescriptor_t, MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 600 601 /* RAID Accelerator Request Descriptor */ 602 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 603 u_int8_t RequestFlags; /* 0x00 */ 604 u_int8_t MSIxIndex; /* 0x01 */ 605 u_int16_t SMID; /* 0x02 */ 606 u_int16_t LMID; /* 0x04 */ 607 u_int16_t Reserved; /* 0x06 */ 608 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 609 610 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 611 Mpi2RAIDAcceleratorRequestDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 612 613 /* union of Request Descriptors */ 614 typedef union _MRSAS_REQUEST_DESCRIPTOR_UNION { 615 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 616 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 617 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 618 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 619 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 620 MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo; 621 union { 622 struct { 623 u_int32_t low; 624 u_int32_t high; 625 } u; 626 u_int64_t Words; 627 } addr; 628 } MRSAS_REQUEST_DESCRIPTOR_UNION; 629 630 /* Default Reply Descriptor */ 631 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR { 632 u_int8_t ReplyFlags; /* 0x00 */ 633 u_int8_t MSIxIndex; /* 0x01 */ 634 u_int16_t DescriptorTypeDependent1; /* 0x02 */ 635 u_int32_t DescriptorTypeDependent2; /* 0x04 */ 636 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 637 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 638 639 /* Address Reply Descriptor */ 640 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR { 641 u_int8_t ReplyFlags; /* 0x00 */ 642 u_int8_t MSIxIndex; /* 0x01 */ 643 u_int16_t SMID; /* 0x02 */ 644 u_int32_t ReplyFrameAddress; /* 0x04 */ 645 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 646 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 647 648 /* SCSI IO Success Reply Descriptor */ 649 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { 650 u_int8_t ReplyFlags; /* 0x00 */ 651 u_int8_t MSIxIndex; /* 0x01 */ 652 u_int16_t SMID; /* 0x02 */ 653 u_int16_t TaskTag; /* 0x04 */ 654 u_int16_t Reserved1; /* 0x06 */ 655 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 656 657 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 658 Mpi2SCSIIOSuccessReplyDescriptor_t, MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 659 660 /* TargetAssist Success Reply Descriptor */ 661 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { 662 u_int8_t ReplyFlags; /* 0x00 */ 663 u_int8_t MSIxIndex; /* 0x01 */ 664 u_int16_t SMID; /* 0x02 */ 665 u_int8_t SequenceNumber; /* 0x04 */ 666 u_int8_t Reserved1; /* 0x05 */ 667 u_int16_t IoIndex; /* 0x06 */ 668 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 669 670 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 671 Mpi2TargetAssistSuccessReplyDescriptor_t, MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 672 673 /* Target Command Buffer Reply Descriptor */ 674 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { 675 u_int8_t ReplyFlags; /* 0x00 */ 676 u_int8_t MSIxIndex; /* 0x01 */ 677 u_int8_t VP_ID; /* 0x02 */ 678 u_int8_t Flags; /* 0x03 */ 679 u_int16_t InitiatorDevHandle; /* 0x04 */ 680 u_int16_t IoIndex; /* 0x06 */ 681 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 682 683 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 684 Mpi2TargetCommandBufferReplyDescriptor_t, MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 685 686 /* RAID Accelerator Success Reply Descriptor */ 687 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 688 u_int8_t ReplyFlags; /* 0x00 */ 689 u_int8_t MSIxIndex; /* 0x01 */ 690 u_int16_t SMID; /* 0x02 */ 691 u_int32_t Reserved; /* 0x04 */ 692 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 693 694 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 695 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 696 697 /* union of Reply Descriptors */ 698 typedef union _MPI2_REPLY_DESCRIPTORS_UNION { 699 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 700 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 701 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 702 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 703 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 704 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 705 u_int64_t Words; 706 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 707 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 708 709 typedef union { 710 volatile unsigned int val; 711 unsigned int val_rdonly; 712 } mrsas_atomic_t; 713 714 #define mrsas_atomic_read(v) atomic_load_acq_int(&(v)->val) 715 #define mrsas_atomic_set(v,i) atomic_store_rel_int(&(v)->val, i) 716 #define mrsas_atomic_dec(v) atomic_subtract_int(&(v)->val, 1) 717 #define mrsas_atomic_inc(v) atomic_add_int(&(v)->val, 1) 718 719 static inline int 720 mrsas_atomic_inc_return(mrsas_atomic_t *v) 721 { 722 return 1 + atomic_fetchadd_int(&(v)->val, 1); 723 } 724 725 /* IOCInit Request message */ 726 typedef struct _MPI2_IOC_INIT_REQUEST { 727 u_int8_t WhoInit; /* 0x00 */ 728 u_int8_t Reserved1; /* 0x01 */ 729 u_int8_t ChainOffset; /* 0x02 */ 730 u_int8_t Function; /* 0x03 */ 731 u_int16_t Reserved2; /* 0x04 */ 732 u_int8_t Reserved3; /* 0x06 */ 733 u_int8_t MsgFlags; /* 0x07 */ 734 u_int8_t VP_ID; /* 0x08 */ 735 u_int8_t VF_ID; /* 0x09 */ 736 u_int16_t Reserved4; /* 0x0A */ 737 u_int16_t MsgVersion; /* 0x0C */ 738 u_int16_t HeaderVersion; /* 0x0E */ 739 u_int32_t Reserved5; /* 0x10 */ 740 u_int16_t Reserved6; /* 0x14 */ 741 u_int8_t HostPageSize; /* 0x16 */ 742 u_int8_t HostMSIxVectors; /* 0x17 */ 743 u_int16_t Reserved8; /* 0x18 */ 744 u_int16_t SystemRequestFrameSize; /* 0x1A */ 745 u_int16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 746 u_int16_t ReplyFreeQueueDepth; /* 0x1E */ 747 u_int32_t SenseBufferAddressHigh; /* 0x20 */ 748 u_int32_t SystemReplyAddressHigh; /* 0x24 */ 749 u_int64_t SystemRequestFrameBaseAddress; /* 0x28 */ 750 u_int64_t ReplyDescriptorPostQueueAddress; /* 0x30 */ 751 u_int64_t ReplyFreeQueueAddress;/* 0x38 */ 752 u_int64_t TimeStamp; /* 0x40 */ 753 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 754 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 755 756 /* 757 * MR private defines 758 */ 759 #define MR_PD_INVALID 0xFFFF 760 #define MR_DEVHANDLE_INVALID 0xFFFF 761 #define MAX_SPAN_DEPTH 8 762 #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH 763 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 764 #define MAX_ROW_SIZE 32 765 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 766 #define MAX_LOGICAL_DRIVES 64 767 #define MAX_LOGICAL_DRIVES_EXT 256 768 #define MAX_LOGICAL_DRIVES_DYN 512 769 770 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 771 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 772 773 #define MAX_ARRAYS 128 774 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 775 776 #define MAX_ARRAYS_EXT 256 777 #define MAX_API_ARRAYS_EXT MAX_ARRAYS_EXT 778 #define MAX_API_ARRAYS_DYN 512 779 780 #define MAX_PHYSICAL_DEVICES 256 781 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 782 #define MAX_RAIDMAP_PHYSICAL_DEVICES_DYN 512 783 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 784 #define MR_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102 785 #define MR_DCMD_PD_MFI_TASK_MGMT 0x0200e100 786 787 #define MR_DCMD_PD_GET_INFO 0x02020000 788 #define MRSAS_MAX_PD_CHANNELS 1 789 #define MRSAS_MAX_LD_CHANNELS 1 790 #define MRSAS_MAX_DEV_PER_CHANNEL 256 791 #define MRSAS_DEFAULT_INIT_ID -1 792 #define MRSAS_MAX_LUN 8 793 #define MRSAS_DEFAULT_CMD_PER_LUN 256 794 #define MRSAS_MAX_PD (MRSAS_MAX_PD_CHANNELS * \ 795 MRSAS_MAX_DEV_PER_CHANNEL) 796 #define MRSAS_MAX_LD_IDS (MRSAS_MAX_LD_CHANNELS * \ 797 MRSAS_MAX_DEV_PER_CHANNEL) 798 799 #define VD_EXT_DEBUG 0 800 #define TM_DEBUG 1 801 802 /******************************************************************* 803 * RAID map related structures 804 ********************************************************************/ 805 #pragma pack(1) 806 typedef struct _MR_DEV_HANDLE_INFO { 807 u_int16_t curDevHdl; 808 u_int8_t validHandles; 809 u_int8_t interfaceType; 810 u_int16_t devHandle[2]; 811 } MR_DEV_HANDLE_INFO; 812 813 #pragma pack() 814 815 typedef struct _MR_ARRAY_INFO { 816 u_int16_t pd[MAX_RAIDMAP_ROW_SIZE]; 817 } MR_ARRAY_INFO; 818 819 typedef struct _MR_QUAD_ELEMENT { 820 u_int64_t logStart; 821 u_int64_t logEnd; 822 u_int64_t offsetInSpan; 823 u_int32_t diff; 824 u_int32_t reserved1; 825 } MR_QUAD_ELEMENT; 826 827 typedef struct _MR_SPAN_INFO { 828 u_int32_t noElements; 829 u_int32_t reserved1; 830 MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; 831 } MR_SPAN_INFO; 832 833 typedef struct _MR_LD_SPAN_ { 834 u_int64_t startBlk; 835 u_int64_t numBlks; 836 u_int16_t arrayRef; 837 u_int8_t spanRowSize; 838 u_int8_t spanRowDataSize; 839 u_int8_t reserved[4]; 840 } MR_LD_SPAN; 841 842 typedef struct _MR_SPAN_BLOCK_INFO { 843 u_int64_t num_rows; 844 MR_LD_SPAN span; 845 MR_SPAN_INFO block_span_info; 846 } MR_SPAN_BLOCK_INFO; 847 848 typedef struct _MR_LD_RAID { 849 struct { 850 #if _BYTE_ORDER == _LITTLE_ENDIAN 851 u_int32_t fpCapable:1; 852 u_int32_t raCapable:1; 853 u_int32_t reserved5:2; 854 u_int32_t ldPiMode:4; 855 u_int32_t pdPiMode:4; 856 u_int32_t encryptionType:8; 857 u_int32_t fpWriteCapable:1; 858 u_int32_t fpReadCapable:1; 859 u_int32_t fpWriteAcrossStripe:1; 860 u_int32_t fpReadAcrossStripe:1; 861 u_int32_t fpNonRWCapable:1; 862 u_int32_t tmCapable:1; 863 u_int32_t fpCacheBypassCapable:1; 864 u_int32_t reserved4:5; 865 #else 866 u_int32_t reserved4:5; 867 u_int32_t fpCacheBypassCapable:1; 868 u_int32_t tmCapable:1; 869 u_int32_t fpNonRWCapable:1; 870 u_int32_t fpReadAcrossStripe:1; 871 u_int32_t fpWriteAcrossStripe:1; 872 u_int32_t fpReadCapable:1; 873 u_int32_t fpWriteCapable:1; 874 u_int32_t encryptionType:8; 875 u_int32_t pdPiMode:4; 876 u_int32_t ldPiMode:4; 877 u_int32_t reserved5:2; 878 u_int32_t raCapable:1; 879 u_int32_t fpCapable:1; 880 #endif 881 } capability; 882 u_int32_t reserved6; 883 u_int64_t size; 884 885 u_int8_t spanDepth; 886 u_int8_t level; 887 u_int8_t stripeShift; 888 u_int8_t rowSize; 889 890 u_int8_t rowDataSize; 891 u_int8_t writeMode; 892 u_int8_t PRL; 893 u_int8_t SRL; 894 895 u_int16_t targetId; 896 u_int8_t ldState; 897 u_int8_t regTypeReqOnWrite; 898 u_int8_t modFactor; 899 u_int8_t regTypeReqOnRead; 900 u_int16_t seqNum; 901 902 struct { 903 #if _BYTE_ORDER == _LITTLE_ENDIAN 904 u_int32_t reserved:30; 905 u_int32_t regTypeReqOnReadLsValid:1; 906 u_int32_t ldSyncRequired:1; 907 #else 908 u_int32_t ldSyncRequired:1; 909 u_int32_t regTypeReqOnReadLsValid:1; 910 u_int32_t reserved:30; 911 #endif 912 } flags; 913 914 u_int8_t LUN[8]; 915 u_int8_t fpIoTimeoutForLd; 916 u_int8_t reserved2[3]; 917 u_int32_t logicalBlockLength; 918 struct { 919 #if _BYTE_ORDER == _LITTLE_ENDIAN 920 u_int32_t reserved1:24; 921 u_int32_t LdLogicalBlockExp:4; 922 u_int32_t LdPiExp:4; 923 #else 924 u_int32_t LdPiExp:4; 925 u_int32_t LdLogicalBlockExp:4; 926 u_int32_t reserved1:24; 927 #endif 928 } exponent; 929 u_int8_t reserved3[0x80 - 0x38]; 930 } MR_LD_RAID; 931 932 typedef struct _MR_LD_SPAN_MAP { 933 MR_LD_RAID ldRaid; 934 u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE]; 935 MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; 936 } MR_LD_SPAN_MAP; 937 938 typedef struct _MR_FW_RAID_MAP { 939 u_int32_t totalSize; 940 union { 941 struct { 942 u_int32_t maxLd; 943 u_int32_t maxSpanDepth; 944 u_int32_t maxRowSize; 945 u_int32_t maxPdCount; 946 u_int32_t maxArrays; 947 } validationInfo; 948 u_int32_t version[5]; 949 u_int32_t reserved1[5]; 950 } raid_desc; 951 u_int32_t ldCount; 952 u_int32_t Reserved1; 953 954 /* 955 * This doesn't correspond to FW Ld Tgt Id to LD, but will purge. For 956 * example: if tgt Id is 4 and FW LD is 2, and there is only one LD, 957 * FW will populate the array like this. [0xFF, 0xFF, 0xFF, 0xFF, 958 * 0x0,.....]. This is to help reduce the entire strcture size if 959 * there are few LDs or driver is looking info for 1 LD only. 960 */ 961 u_int8_t ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES + MAX_RAIDMAP_VIEWS]; 962 u_int8_t fpPdIoTimeoutSec; 963 u_int8_t reserved2[7]; 964 MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; 965 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 966 MR_LD_SPAN_MAP ldSpanMap[1]; 967 } MR_FW_RAID_MAP; 968 969 typedef struct _MR_FW_RAID_MAP_EXT { 970 /* Not used in new map */ 971 u_int32_t reserved; 972 973 union { 974 struct { 975 u_int32_t maxLd; 976 u_int32_t maxSpanDepth; 977 u_int32_t maxRowSize; 978 u_int32_t maxPdCount; 979 u_int32_t maxArrays; 980 } validationInfo; 981 u_int32_t version[5]; 982 u_int32_t reserved1[5]; 983 } fw_raid_desc; 984 985 u_int8_t fpPdIoTimeoutSec; 986 u_int8_t reserved2[7]; 987 988 u_int16_t ldCount; 989 u_int16_t arCount; 990 u_int16_t spanCount; 991 u_int16_t reserve3; 992 993 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 994 u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; 995 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; 996 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT]; 997 } MR_FW_RAID_MAP_EXT; 998 999 typedef struct _MR_DRV_RAID_MAP { 1000 /* 1001 * Total size of this structure, including this field. This feild 1002 * will be manupulated by driver for ext raid map, else pick the 1003 * value from firmware raid map. 1004 */ 1005 u_int32_t totalSize; 1006 1007 union { 1008 struct { 1009 u_int32_t maxLd; 1010 u_int32_t maxSpanDepth; 1011 u_int32_t maxRowSize; 1012 u_int32_t maxPdCount; 1013 u_int32_t maxArrays; 1014 } validationInfo; 1015 u_int32_t version[5]; 1016 u_int32_t reserved1[5]; 1017 } drv_raid_desc; 1018 1019 /* timeout value used by driver in FP IOs */ 1020 u_int8_t fpPdIoTimeoutSec; 1021 u_int8_t reserved2[7]; 1022 1023 u_int16_t ldCount; 1024 u_int16_t arCount; 1025 u_int16_t spanCount; 1026 u_int16_t reserve3; 1027 1028 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES_DYN]; 1029 u_int16_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_DYN]; 1030 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_DYN]; 1031 MR_LD_SPAN_MAP ldSpanMap[1]; 1032 1033 } MR_DRV_RAID_MAP; 1034 1035 /* 1036 * Driver raid map size is same as raid map ext MR_DRV_RAID_MAP_ALL is 1037 * created to sync with old raid. And it is mainly for code re-use purpose. 1038 */ 1039 1040 #pragma pack(1) 1041 typedef struct _MR_DRV_RAID_MAP_ALL { 1042 MR_DRV_RAID_MAP raidMap; 1043 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_DYN - 1]; 1044 } MR_DRV_RAID_MAP_ALL; 1045 1046 #pragma pack() 1047 1048 typedef struct _LD_LOAD_BALANCE_INFO { 1049 u_int8_t loadBalanceFlag; 1050 u_int8_t reserved1; 1051 mrsas_atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES]; 1052 u_int64_t last_accessed_block[MAX_PHYSICAL_DEVICES]; 1053 } LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO; 1054 1055 /* SPAN_SET is info caclulated from span info from Raid map per ld */ 1056 typedef struct _LD_SPAN_SET { 1057 u_int64_t log_start_lba; 1058 u_int64_t log_end_lba; 1059 u_int64_t span_row_start; 1060 u_int64_t span_row_end; 1061 u_int64_t data_strip_start; 1062 u_int64_t data_strip_end; 1063 u_int64_t data_row_start; 1064 u_int64_t data_row_end; 1065 u_int8_t strip_offset[MAX_SPAN_DEPTH]; 1066 u_int32_t span_row_data_width; 1067 u_int32_t diff; 1068 u_int32_t reserved[2]; 1069 } LD_SPAN_SET, *PLD_SPAN_SET; 1070 1071 typedef struct LOG_BLOCK_SPAN_INFO { 1072 LD_SPAN_SET span_set[MAX_SPAN_DEPTH]; 1073 } LD_SPAN_INFO, *PLD_SPAN_INFO; 1074 1075 #pragma pack(1) 1076 typedef struct _MR_FW_RAID_MAP_ALL { 1077 MR_FW_RAID_MAP raidMap; 1078 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1]; 1079 } MR_FW_RAID_MAP_ALL; 1080 1081 #pragma pack() 1082 1083 struct IO_REQUEST_INFO { 1084 u_int64_t ldStartBlock; 1085 u_int32_t numBlocks; 1086 u_int16_t ldTgtId; 1087 u_int8_t isRead; 1088 u_int16_t devHandle; 1089 u_int8_t pdInterface; 1090 u_int64_t pdBlock; 1091 u_int8_t fpOkForIo; 1092 u_int8_t IoforUnevenSpan; 1093 u_int8_t start_span; 1094 u_int8_t reserved; 1095 u_int64_t start_row; 1096 /* span[7:5], arm[4:0] */ 1097 u_int8_t span_arm; 1098 u_int8_t pd_after_lb; 1099 boolean_t raCapable; 1100 u_int16_t r1_alt_dev_handle; 1101 }; 1102 1103 /* 1104 * define MR_PD_CFG_SEQ structure for system PDs 1105 */ 1106 struct MR_PD_CFG_SEQ { 1107 u_int16_t seqNum; 1108 u_int16_t devHandle; 1109 struct { 1110 #if _BYTE_ORDER == _LITTLE_ENDIAN 1111 u_int8_t tmCapable:1; 1112 u_int8_t reserved:7; 1113 #else 1114 u_int8_t reserved:7; 1115 u_int8_t tmCapable:1; 1116 #endif 1117 } capability; 1118 u_int8_t reserved; 1119 u_int16_t pdTargetId; 1120 } __packed; 1121 1122 struct MR_PD_CFG_SEQ_NUM_SYNC { 1123 u_int32_t size; 1124 u_int32_t count; 1125 struct MR_PD_CFG_SEQ seq[1]; 1126 } __packed; 1127 1128 typedef struct _STREAM_DETECT { 1129 u_int64_t nextSeqLBA; 1130 struct megasas_cmd_fusion *first_cmd_fusion; 1131 struct megasas_cmd_fusion *last_cmd_fusion; 1132 u_int32_t countCmdsInStream; 1133 u_int16_t numSGEsInGroup; 1134 u_int8_t isRead; 1135 u_int8_t groupDepth; 1136 boolean_t groupFlush; 1137 u_int8_t reserved[7]; 1138 } STREAM_DETECT, *PTR_STREAM_DETECT; 1139 1140 typedef struct _LD_STREAM_DETECT { 1141 boolean_t writeBack; 1142 boolean_t FPWriteEnabled; 1143 boolean_t membersSSDs; 1144 boolean_t fpCacheBypassCapable; 1145 u_int32_t mruBitMap; 1146 volatile long iosToFware; 1147 volatile long writeBytesOutstanding; 1148 STREAM_DETECT streamTrack[MAX_STREAMS_TRACKED]; 1149 } LD_STREAM_DETECT, *PTR_LD_STREAM_DETECT; 1150 1151 typedef struct _MR_LD_TARGET_SYNC { 1152 u_int8_t targetId; 1153 u_int8_t reserved; 1154 u_int16_t seqNum; 1155 } MR_LD_TARGET_SYNC; 1156 1157 /* 1158 * RAID Map descriptor Types. 1159 * Each element should uniquely idetify one data structure in the RAID map 1160 */ 1161 typedef enum _MR_RAID_MAP_DESC_TYPE { 1162 RAID_MAP_DESC_TYPE_DEVHDL_INFO = 0, /* MR_DEV_HANDLE_INFO data */ 1163 RAID_MAP_DESC_TYPE_TGTID_INFO = 1, /* target to Ld num Index map */ 1164 RAID_MAP_DESC_TYPE_ARRAY_INFO = 2, /* MR_ARRAY_INFO data */ 1165 RAID_MAP_DESC_TYPE_SPAN_INFO = 3, /* MR_LD_SPAN_MAP data */ 1166 RAID_MAP_DESC_TYPE_COUNT, 1167 } MR_RAID_MAP_DESC_TYPE; 1168 1169 /* 1170 * This table defines the offset, size and num elements of each descriptor 1171 * type in the RAID Map buffer 1172 */ 1173 typedef struct _MR_RAID_MAP_DESC_TABLE { 1174 /* Raid map descriptor type */ 1175 u_int32_t raidMapDescType; 1176 /* Offset into the RAID map buffer where descriptor data is saved */ 1177 u_int32_t raidMapDescOffset; 1178 /* total size of the descriptor buffer */ 1179 u_int32_t raidMapDescBufferSize; 1180 /* Number of elements contained in the descriptor buffer */ 1181 u_int32_t raidMapDescElements; 1182 } MR_RAID_MAP_DESC_TABLE; 1183 1184 /* 1185 * Dynamic Raid Map Structure. 1186 */ 1187 typedef struct _MR_FW_RAID_MAP_DYNAMIC { 1188 u_int32_t raidMapSize; 1189 u_int32_t descTableOffset; 1190 u_int32_t descTableSize; 1191 u_int32_t descTableNumElements; 1192 u_int64_t PCIThresholdBandwidth; 1193 u_int32_t reserved2[3]; 1194 1195 u_int8_t fpPdIoTimeoutSec; 1196 u_int8_t reserved3[3]; 1197 u_int32_t rmwFPSeqNum; 1198 u_int16_t ldCount; 1199 u_int16_t arCount; 1200 u_int16_t spanCount; 1201 u_int16_t reserved4[3]; 1202 1203 /* 1204 * The below structure of pointers is only to be used by the driver. 1205 * This is added in the API to reduce the amount of code changes needed in 1206 * the driver to support dynamic RAID map. 1207 * Firmware should not update these pointers while preparing the raid map 1208 */ 1209 union { 1210 struct { 1211 MR_DEV_HANDLE_INFO *devHndlInfo; 1212 u_int16_t *ldTgtIdToLd; 1213 MR_ARRAY_INFO *arMapInfo; 1214 MR_LD_SPAN_MAP *ldSpanMap; 1215 } ptrStruct; 1216 u_int64_t ptrStructureSize[RAID_MAP_DESC_TYPE_COUNT]; 1217 } RaidMapDescPtrs; 1218 1219 /* 1220 * RAID Map descriptor table defines the layout of data in the RAID Map. 1221 * The size of the descriptor table itself could change. 1222 */ 1223 1224 /* Variable Size descriptor Table. */ 1225 MR_RAID_MAP_DESC_TABLE raidMapDescTable[RAID_MAP_DESC_TYPE_COUNT]; 1226 /* Variable Size buffer containing all data */ 1227 u_int32_t raidMapDescData[1]; 1228 1229 } MR_FW_RAID_MAP_DYNAMIC; 1230 1231 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1232 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1233 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1234 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1235 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1236 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1237 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1238 1239 /* Few NVME flags defines*/ 1240 #define MPI2_SGE_FLAGS_SHIFT (0x02) 1241 #define IEEE_SGE_FLAGS_FORMAT_MASK (0xC0) 1242 #define IEEE_SGE_FLAGS_FORMAT_IEEE (0x00) 1243 #define IEEE_SGE_FLAGS_FORMAT_PQI (0x01) 1244 #define IEEE_SGE_FLAGS_FORMAT_NVME (0x02) 1245 #define IEEE_SGE_FLAGS_FORMAT_AHCI (0x03) 1246 1247 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C) 1248 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00) 1249 #define MPI26_IEEE_SGE_FLAGS_NSF_PQI (0x04) 1250 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08) 1251 #define MPI26_IEEE_SGE_FLAGS_NSF_AHCI_PRDT (0x0C) 1252 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10) 1253 1254 union desc_value { 1255 u_int64_t word; 1256 struct { 1257 u_int32_t low; 1258 u_int32_t high; 1259 } u; 1260 }; 1261 1262 /******************************************************************* 1263 * Temporary command 1264 ********************************************************************/ 1265 struct mrsas_tmp_dcmd { 1266 bus_dma_tag_t tmp_dcmd_tag; 1267 bus_dmamap_t tmp_dcmd_dmamap; 1268 void *tmp_dcmd_mem; 1269 bus_addr_t tmp_dcmd_phys_addr; 1270 }; 1271 1272 #define MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT 16 1273 #define MR_MAX_RAID_MAP_SIZE_MASK 0x1FF 1274 #define MR_MIN_MAP_SIZE 0x10000 1275 1276 /******************************************************************* 1277 * Register set, included legacy controllers 1068 and 1078, 1278 * structure extended for 1078 registers 1279 *******************************************************************/ 1280 #pragma pack(1) 1281 typedef struct _mrsas_register_set { 1282 u_int32_t doorbell; /* 0000h */ 1283 u_int32_t fusion_seq_offset; /* 0004h */ 1284 u_int32_t fusion_host_diag; /* 0008h */ 1285 u_int32_t reserved_01; /* 000Ch */ 1286 1287 u_int32_t inbound_msg_0; /* 0010h */ 1288 u_int32_t inbound_msg_1; /* 0014h */ 1289 u_int32_t outbound_msg_0; /* 0018h */ 1290 u_int32_t outbound_msg_1; /* 001Ch */ 1291 1292 u_int32_t inbound_doorbell; /* 0020h */ 1293 u_int32_t inbound_intr_status; /* 0024h */ 1294 u_int32_t inbound_intr_mask; /* 0028h */ 1295 1296 u_int32_t outbound_doorbell; /* 002Ch */ 1297 u_int32_t outbound_intr_status; /* 0030h */ 1298 u_int32_t outbound_intr_mask; /* 0034h */ 1299 1300 u_int32_t reserved_1[2]; /* 0038h */ 1301 1302 u_int32_t inbound_queue_port; /* 0040h */ 1303 u_int32_t outbound_queue_port; /* 0044h */ 1304 1305 u_int32_t reserved_2[9]; /* 0048h */ 1306 u_int32_t reply_post_host_index;/* 006Ch */ 1307 u_int32_t reserved_2_2[12]; /* 0070h */ 1308 1309 u_int32_t outbound_doorbell_clear; /* 00A0h */ 1310 1311 u_int32_t reserved_3[3]; /* 00A4h */ 1312 1313 u_int32_t outbound_scratch_pad; /* 00B0h */ 1314 u_int32_t outbound_scratch_pad_2; /* 00B4h */ 1315 u_int32_t outbound_scratch_pad_3; /* 00B8h */ 1316 u_int32_t outbound_scratch_pad_4; /* 00BCh */ 1317 1318 u_int32_t inbound_low_queue_port; /* 00C0h */ 1319 1320 u_int32_t inbound_high_queue_port; /* 00C4h */ 1321 1322 u_int32_t inbound_single_queue_port; /* 00C8h */ 1323 u_int32_t res_6[11]; /* CCh */ 1324 u_int32_t host_diag; 1325 u_int32_t seq_offset; 1326 u_int32_t index_registers[807]; /* 00CCh */ 1327 } mrsas_reg_set; 1328 1329 #pragma pack() 1330 1331 /******************************************************************* 1332 * Firmware Interface Defines 1333 ******************************************************************* 1334 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker 1335 * for protocol between the software and firmware. Commands are 1336 * issued using "message frames". 1337 ******************************************************************/ 1338 /* 1339 * FW posts its state in upper 4 bits of outbound_msg_0 register 1340 */ 1341 #define MFI_STATE_MASK 0xF0000000 1342 #define MFI_STATE_UNDEFINED 0x00000000 1343 #define MFI_STATE_BB_INIT 0x10000000 1344 #define MFI_STATE_FW_INIT 0x40000000 1345 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 1346 #define MFI_STATE_FW_INIT_2 0x70000000 1347 #define MFI_STATE_DEVICE_SCAN 0x80000000 1348 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 1349 #define MFI_STATE_FLUSH_CACHE 0xA0000000 1350 #define MFI_STATE_READY 0xB0000000 1351 #define MFI_STATE_OPERATIONAL 0xC0000000 1352 #define MFI_STATE_FAULT 0xF0000000 1353 #define MFI_RESET_REQUIRED 0x00000001 1354 #define MFI_RESET_ADAPTER 0x00000002 1355 #define MEGAMFI_FRAME_SIZE 64 1356 #define MRSAS_MFI_FRAME_SIZE 1024 1357 #define MRSAS_MFI_SENSE_SIZE 128 1358 1359 /* 1360 * During FW init, clear pending cmds & reset state using inbound_msg_0 1361 * 1362 * ABORT : Abort all pending cmds READY : Move from OPERATIONAL to 1363 * READY state; discard queue info MFIMODE : Discard (possible) low MFA 1364 * posted in 64-bit mode (??) CLR_HANDSHAKE: FW is waiting for HANDSHAKE from 1365 * BIOS or Driver HOTPLUG : Resume from Hotplug MFI_STOP_ADP : Send 1366 * signal to FW to stop processing 1367 */ 1368 1369 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) 1370 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) 1371 #define DIAG_WRITE_ENABLE (0x00000080) 1372 #define DIAG_RESET_ADAPTER (0x00000004) 1373 1374 #define MFI_ADP_RESET 0x00000040 1375 #define MFI_INIT_ABORT 0x00000001 1376 #define MFI_INIT_READY 0x00000002 1377 #define MFI_INIT_MFIMODE 0x00000004 1378 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 1379 #define MFI_INIT_HOTPLUG 0x00000010 1380 #define MFI_STOP_ADP 0x00000020 1381 #define MFI_RESET_FLAGS MFI_INIT_READY| \ 1382 MFI_INIT_MFIMODE| \ 1383 MFI_INIT_ABORT 1384 1385 /* 1386 * MFI frame flags 1387 */ 1388 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 1389 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 1390 #define MFI_FRAME_SGL32 0x0000 1391 #define MFI_FRAME_SGL64 0x0002 1392 #define MFI_FRAME_SENSE32 0x0000 1393 #define MFI_FRAME_SENSE64 0x0004 1394 #define MFI_FRAME_DIR_NONE 0x0000 1395 #define MFI_FRAME_DIR_WRITE 0x0008 1396 #define MFI_FRAME_DIR_READ 0x0010 1397 #define MFI_FRAME_DIR_BOTH 0x0018 1398 #define MFI_FRAME_IEEE 0x0020 1399 1400 /* 1401 * Definition for cmd_status 1402 */ 1403 #define MFI_CMD_STATUS_POLL_MODE 0xFF 1404 1405 /* 1406 * MFI command opcodes 1407 */ 1408 #define MFI_CMD_INIT 0x00 1409 #define MFI_CMD_LD_READ 0x01 1410 #define MFI_CMD_LD_WRITE 0x02 1411 #define MFI_CMD_LD_SCSI_IO 0x03 1412 #define MFI_CMD_PD_SCSI_IO 0x04 1413 #define MFI_CMD_DCMD 0x05 1414 #define MFI_CMD_ABORT 0x06 1415 #define MFI_CMD_SMP 0x07 1416 #define MFI_CMD_STP 0x08 1417 #define MFI_CMD_INVALID 0xff 1418 1419 #define MR_DCMD_CTRL_GET_INFO 0x01010000 1420 #define MR_DCMD_LD_GET_LIST 0x03010000 1421 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 1422 #define MR_FLUSH_CTRL_CACHE 0x01 1423 #define MR_FLUSH_DISK_CACHE 0x02 1424 1425 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 1426 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 1427 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 1428 1429 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 1430 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 1431 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 1432 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 1433 1434 #define MR_DCMD_CLUSTER 0x08000000 1435 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 1436 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 1437 #define MR_DCMD_PD_LIST_QUERY 0x02010100 1438 1439 #define MR_DCMD_CTRL_MISC_CPX 0x0100e200 1440 #define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET 0x0100e201 1441 #define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA 0x0100e202 1442 #define MR_DCMD_CTRL_MISC_CPX_UNREGISTER 0x0100e203 1443 #define MAX_MR_ROW_SIZE 32 1444 #define MR_CPX_DIR_WRITE 1 1445 #define MR_CPX_DIR_READ 0 1446 #define MR_CPX_VERSION 1 1447 1448 #define MR_DCMD_CTRL_IO_METRICS_GET 0x01170200 1449 1450 #define MR_EVT_CFG_CLEARED 0x0004 1451 1452 #define MR_EVT_LD_STATE_CHANGE 0x0051 1453 #define MR_EVT_PD_INSERTED 0x005b 1454 #define MR_EVT_PD_REMOVED 0x0070 1455 #define MR_EVT_LD_CREATED 0x008a 1456 #define MR_EVT_LD_DELETED 0x008b 1457 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1458 #define MR_EVT_LD_OFFLINE 0x00fc 1459 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1460 #define MR_EVT_CTRL_PERF_COLLECTION 0x017e 1461 1462 /* 1463 * MFI command completion codes 1464 */ 1465 enum MFI_STAT { 1466 MFI_STAT_OK = 0x00, 1467 MFI_STAT_INVALID_CMD = 0x01, 1468 MFI_STAT_INVALID_DCMD = 0x02, 1469 MFI_STAT_INVALID_PARAMETER = 0x03, 1470 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 1471 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 1472 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 1473 MFI_STAT_APP_IN_USE = 0x07, 1474 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 1475 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 1476 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 1477 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 1478 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 1479 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 1480 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 1481 MFI_STAT_FLASH_BUSY = 0x0f, 1482 MFI_STAT_FLASH_ERROR = 0x10, 1483 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 1484 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 1485 MFI_STAT_FLASH_NOT_OPEN = 0x13, 1486 MFI_STAT_FLASH_NOT_STARTED = 0x14, 1487 MFI_STAT_FLUSH_FAILED = 0x15, 1488 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 1489 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 1490 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 1491 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 1492 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 1493 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 1494 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 1495 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 1496 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 1497 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 1498 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 1499 MFI_STAT_MFC_HW_ERROR = 0x21, 1500 MFI_STAT_NO_HW_PRESENT = 0x22, 1501 MFI_STAT_NOT_FOUND = 0x23, 1502 MFI_STAT_NOT_IN_ENCL = 0x24, 1503 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 1504 MFI_STAT_PD_TYPE_WRONG = 0x26, 1505 MFI_STAT_PR_DISABLED = 0x27, 1506 MFI_STAT_ROW_INDEX_INVALID = 0x28, 1507 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 1508 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 1509 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 1510 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 1511 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 1512 MFI_STAT_SCSI_IO_FAILED = 0x2e, 1513 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 1514 MFI_STAT_SHUTDOWN_FAILED = 0x30, 1515 MFI_STAT_TIME_NOT_SET = 0x31, 1516 MFI_STAT_WRONG_STATE = 0x32, 1517 MFI_STAT_LD_OFFLINE = 0x33, 1518 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 1519 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 1520 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 1521 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 1522 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 1523 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 1524 1525 MFI_STAT_INVALID_STATUS = 0xFF 1526 }; 1527 1528 /* 1529 * Number of mailbox bytes in DCMD message frame 1530 */ 1531 #define MFI_MBOX_SIZE 12 1532 1533 enum MR_EVT_CLASS { 1534 MR_EVT_CLASS_DEBUG = -2, 1535 MR_EVT_CLASS_PROGRESS = -1, 1536 MR_EVT_CLASS_INFO = 0, 1537 MR_EVT_CLASS_WARNING = 1, 1538 MR_EVT_CLASS_CRITICAL = 2, 1539 MR_EVT_CLASS_FATAL = 3, 1540 MR_EVT_CLASS_DEAD = 4, 1541 1542 }; 1543 1544 enum MR_EVT_LOCALE { 1545 MR_EVT_LOCALE_LD = 0x0001, 1546 MR_EVT_LOCALE_PD = 0x0002, 1547 MR_EVT_LOCALE_ENCL = 0x0004, 1548 MR_EVT_LOCALE_BBU = 0x0008, 1549 MR_EVT_LOCALE_SAS = 0x0010, 1550 MR_EVT_LOCALE_CTRL = 0x0020, 1551 MR_EVT_LOCALE_CONFIG = 0x0040, 1552 MR_EVT_LOCALE_CLUSTER = 0x0080, 1553 MR_EVT_LOCALE_ALL = 0xffff, 1554 1555 }; 1556 1557 enum MR_EVT_ARGS { 1558 MR_EVT_ARGS_NONE, 1559 MR_EVT_ARGS_CDB_SENSE, 1560 MR_EVT_ARGS_LD, 1561 MR_EVT_ARGS_LD_COUNT, 1562 MR_EVT_ARGS_LD_LBA, 1563 MR_EVT_ARGS_LD_OWNER, 1564 MR_EVT_ARGS_LD_LBA_PD_LBA, 1565 MR_EVT_ARGS_LD_PROG, 1566 MR_EVT_ARGS_LD_STATE, 1567 MR_EVT_ARGS_LD_STRIP, 1568 MR_EVT_ARGS_PD, 1569 MR_EVT_ARGS_PD_ERR, 1570 MR_EVT_ARGS_PD_LBA, 1571 MR_EVT_ARGS_PD_LBA_LD, 1572 MR_EVT_ARGS_PD_PROG, 1573 MR_EVT_ARGS_PD_STATE, 1574 MR_EVT_ARGS_PCI, 1575 MR_EVT_ARGS_RATE, 1576 MR_EVT_ARGS_STR, 1577 MR_EVT_ARGS_TIME, 1578 MR_EVT_ARGS_ECC, 1579 MR_EVT_ARGS_LD_PROP, 1580 MR_EVT_ARGS_PD_SPARE, 1581 MR_EVT_ARGS_PD_INDEX, 1582 MR_EVT_ARGS_DIAG_PASS, 1583 MR_EVT_ARGS_DIAG_FAIL, 1584 MR_EVT_ARGS_PD_LBA_LBA, 1585 MR_EVT_ARGS_PORT_PHY, 1586 MR_EVT_ARGS_PD_MISSING, 1587 MR_EVT_ARGS_PD_ADDRESS, 1588 MR_EVT_ARGS_BITMAP, 1589 MR_EVT_ARGS_CONNECTOR, 1590 MR_EVT_ARGS_PD_PD, 1591 MR_EVT_ARGS_PD_FRU, 1592 MR_EVT_ARGS_PD_PATHINFO, 1593 MR_EVT_ARGS_PD_POWER_STATE, 1594 MR_EVT_ARGS_GENERIC, 1595 }; 1596 1597 /* 1598 * Thunderbolt (and later) Defines 1599 */ 1600 #define MEGASAS_CHAIN_FRAME_SZ_MIN 1024 1601 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) 1602 #define MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 1603 #define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 1604 #define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 1605 #define MRSAS_LOAD_BALANCE_FLAG 0x1 1606 #define MRSAS_DCMD_MBOX_PEND_FLAG 0x1 1607 #define HOST_DIAG_WRITE_ENABLE 0x80 1608 #define HOST_DIAG_RESET_ADAPTER 0x4 1609 #define MRSAS_TBOLT_MAX_RESET_TRIES 3 1610 #define MRSAS_MAX_MFI_CMDS 16 1611 #define MRSAS_MAX_IOCTL_CMDS 3 1612 1613 /* 1614 * Invader Defines 1615 */ 1616 #define MPI2_TYPE_CUDA 0x2 1617 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000 1618 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00 1619 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10 1620 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80 1621 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8 1622 #define MR_RL_WRITE_THROUGH_MODE 0x00 1623 #define MR_RL_WRITE_BACK_MODE 0x01 1624 1625 /* 1626 * T10 PI defines 1627 */ 1628 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8 1629 #define MRSAS_SCSI_VARIABLE_LENGTH_CMD 0x7f 1630 #define MRSAS_SCSI_SERVICE_ACTION_READ32 0x9 1631 #define MRSAS_SCSI_SERVICE_ACTION_WRITE32 0xB 1632 #define MRSAS_SCSI_ADDL_CDB_LEN 0x18 1633 #define MRSAS_RD_WR_PROTECT_CHECK_ALL 0x20 1634 #define MRSAS_RD_WR_PROTECT_CHECK_NONE 0x60 1635 #define MRSAS_SCSIBLOCKSIZE 512 1636 1637 /* 1638 * Raid context flags 1639 */ 1640 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 1641 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 1642 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE { 1643 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, 1644 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1, 1645 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_DATA = 2, 1646 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_P = 3, 1647 MR_RAID_FLAGS_IO_SUB_TYPE_RMW_Q = 4, 1648 MR_RAID_FLAGS_IO_SUB_TYPE_CACHE_BYPASS = 6, 1649 MR_RAID_FLAGS_IO_SUB_TYPE_LDIO_BW_LIMIT = 7 1650 } MR_RAID_FLAGS_IO_SUB_TYPE; 1651 /* 1652 * Request descriptor types 1653 */ 1654 #define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7 1655 #define MRSAS_REQ_DESCRIPT_FLAGS_MFA 0x1 1656 #define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2 1657 #define MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1 1658 #define MRSAS_FP_CMD_LEN 16 1659 #define MRSAS_FUSION_IN_RESET 0 1660 1661 #define RAID_CTX_SPANARM_ARM_SHIFT (0) 1662 #define RAID_CTX_SPANARM_ARM_MASK (0x1f) 1663 #define RAID_CTX_SPANARM_SPAN_SHIFT (5) 1664 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0) 1665 1666 /* 1667 * Define region lock types 1668 */ 1669 typedef enum _REGION_TYPE { 1670 REGION_TYPE_UNUSED = 0, 1671 REGION_TYPE_SHARED_READ = 1, 1672 REGION_TYPE_SHARED_WRITE = 2, 1673 REGION_TYPE_EXCLUSIVE = 3, 1674 } REGION_TYPE; 1675 1676 /* 1677 * SCSI-CAM Related Defines 1678 */ 1679 #define MRSAS_SCSI_MAX_LUNS 0 1680 #define MRSAS_SCSI_INITIATOR_ID 255 1681 #define MRSAS_SCSI_MAX_CMDS 8 1682 #define MRSAS_SCSI_MAX_CDB_LEN 16 1683 #define MRSAS_SCSI_SENSE_BUFFERSIZE 96 1684 #define MRSAS_INTERNAL_CMDS 32 1685 #define MRSAS_FUSION_INT_CMDS 8 1686 1687 #define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK 0x400000 1688 #define MEGASAS_MAX_CHAIN_SIZE_MASK 0x3E0 1689 #define MEGASAS_256K_IO 128 1690 #define MEGASAS_1MB_IO (MEGASAS_256K_IO * 4) 1691 1692 /* Request types */ 1693 #define MRSAS_REQ_TYPE_INTERNAL_CMD 0x0 1694 #define MRSAS_REQ_TYPE_AEN_FETCH 0x1 1695 #define MRSAS_REQ_TYPE_PASSTHRU 0x2 1696 #define MRSAS_REQ_TYPE_GETSET_PARAM 0x3 1697 #define MRSAS_REQ_TYPE_SCSI_IO 0x4 1698 1699 /* Request states */ 1700 #define MRSAS_REQ_STATE_FREE 0 1701 #define MRSAS_REQ_STATE_BUSY 1 1702 #define MRSAS_REQ_STATE_TRAN 2 1703 #define MRSAS_REQ_STATE_COMPLETE 3 1704 1705 typedef enum _MR_SCSI_CMD_TYPE { 1706 READ_WRITE_LDIO = 0, 1707 NON_READ_WRITE_LDIO = 1, 1708 READ_WRITE_SYSPDIO = 2, 1709 NON_READ_WRITE_SYSPDIO = 3, 1710 } MR_SCSI_CMD_TYPE; 1711 1712 enum mrsas_req_flags { 1713 MRSAS_DIR_UNKNOWN = 0x1, 1714 MRSAS_DIR_IN = 0x2, 1715 MRSAS_DIR_OUT = 0x4, 1716 MRSAS_DIR_NONE = 0x8, 1717 }; 1718 1719 /* 1720 * Adapter Reset States 1721 */ 1722 enum { 1723 MRSAS_HBA_OPERATIONAL = 0, 1724 MRSAS_ADPRESET_SM_INFAULT = 1, 1725 MRSAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 1726 MRSAS_ADPRESET_SM_OPERATIONAL = 3, 1727 MRSAS_HW_CRITICAL_ERROR = 4, 1728 MRSAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 1729 }; 1730 1731 /* 1732 * MPT Command Structure 1733 */ 1734 struct mrsas_mpt_cmd { 1735 MRSAS_RAID_SCSI_IO_REQUEST *io_request; 1736 bus_addr_t io_request_phys_addr; 1737 MPI2_SGE_IO_UNION *chain_frame; 1738 bus_addr_t chain_frame_phys_addr; 1739 u_int32_t sge_count; 1740 u_int8_t *sense; 1741 bus_addr_t sense_phys_addr; 1742 u_int8_t retry_for_fw_reset; 1743 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc; 1744 u_int32_t sync_cmd_idx; 1745 u_int32_t index; 1746 u_int8_t flags; 1747 u_int8_t pd_r1_lb; 1748 u_int8_t load_balance; 1749 bus_size_t length; 1750 u_int32_t error_code; 1751 bus_dmamap_t data_dmamap; 1752 void *data; 1753 union ccb *ccb_ptr; 1754 struct callout cm_callout; 1755 struct mrsas_softc *sc; 1756 boolean_t tmCapable; 1757 u_int16_t r1_alt_dev_handle; 1758 boolean_t cmd_completed; 1759 struct mrsas_mpt_cmd *peer_cmd; 1760 bool callout_owner; 1761 TAILQ_ENTRY(mrsas_mpt_cmd) next; 1762 u_int8_t pdInterface; 1763 }; 1764 1765 /* 1766 * MFI Command Structure 1767 */ 1768 struct mrsas_mfi_cmd { 1769 union mrsas_frame *frame; 1770 bus_dmamap_t frame_dmamap; 1771 void *frame_mem; 1772 bus_addr_t frame_phys_addr; 1773 u_int8_t *sense; 1774 bus_dmamap_t sense_dmamap; 1775 void *sense_mem; 1776 bus_addr_t sense_phys_addr; 1777 u_int32_t index; 1778 u_int8_t sync_cmd; 1779 u_int8_t cmd_status; 1780 u_int8_t abort_aen; 1781 u_int8_t retry_for_fw_reset; 1782 struct mrsas_softc *sc; 1783 union ccb *ccb_ptr; 1784 union { 1785 struct { 1786 u_int16_t smid; 1787 u_int16_t resvd; 1788 } context; 1789 u_int32_t frame_count; 1790 } cmd_id; 1791 TAILQ_ENTRY(mrsas_mfi_cmd) next; 1792 }; 1793 1794 /* 1795 * define constants for device list query options 1796 */ 1797 enum MR_PD_QUERY_TYPE { 1798 MR_PD_QUERY_TYPE_ALL = 0, 1799 MR_PD_QUERY_TYPE_STATE = 1, 1800 MR_PD_QUERY_TYPE_POWER_STATE = 2, 1801 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 1802 MR_PD_QUERY_TYPE_SPEED = 4, 1803 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 1804 }; 1805 1806 #define MR_EVT_CFG_CLEARED 0x0004 1807 #define MR_EVT_LD_STATE_CHANGE 0x0051 1808 #define MR_EVT_PD_INSERTED 0x005b 1809 #define MR_EVT_PD_REMOVED 0x0070 1810 #define MR_EVT_LD_CREATED 0x008a 1811 #define MR_EVT_LD_DELETED 0x008b 1812 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1813 #define MR_EVT_LD_OFFLINE 0x00fc 1814 #define MR_EVT_CTRL_PROP_CHANGED 0x012f 1815 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1816 1817 enum MR_PD_STATE { 1818 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1819 MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 1820 MR_PD_STATE_HOT_SPARE = 0x02, 1821 MR_PD_STATE_OFFLINE = 0x10, 1822 MR_PD_STATE_FAILED = 0x11, 1823 MR_PD_STATE_REBUILD = 0x14, 1824 MR_PD_STATE_ONLINE = 0x18, 1825 MR_PD_STATE_COPYBACK = 0x20, 1826 MR_PD_STATE_SYSTEM = 0x40, 1827 }; 1828 1829 /* 1830 * defines the physical drive address structure 1831 */ 1832 #pragma pack(1) 1833 struct MR_PD_ADDRESS { 1834 u_int16_t deviceId; 1835 u_int16_t enclDeviceId; 1836 1837 union { 1838 struct { 1839 u_int8_t enclIndex; 1840 u_int8_t slotNumber; 1841 } mrPdAddress; 1842 struct { 1843 u_int8_t enclPosition; 1844 u_int8_t enclConnectorIndex; 1845 } mrEnclAddress; 1846 } u1; 1847 u_int8_t scsiDevType; 1848 union { 1849 u_int8_t connectedPortBitmap; 1850 u_int8_t connectedPortNumbers; 1851 } u2; 1852 u_int64_t sasAddr[2]; 1853 }; 1854 1855 #pragma pack() 1856 1857 /* 1858 * defines the physical drive list structure 1859 */ 1860 #pragma pack(1) 1861 struct MR_PD_LIST { 1862 u_int32_t size; 1863 u_int32_t count; 1864 struct MR_PD_ADDRESS addr[1]; 1865 }; 1866 1867 #pragma pack() 1868 1869 #pragma pack(1) 1870 struct mrsas_pd_list { 1871 u_int16_t tid; 1872 u_int8_t driveType; 1873 u_int8_t driveState; 1874 }; 1875 1876 #pragma pack() 1877 1878 /* 1879 * defines the logical drive reference structure 1880 */ 1881 typedef union _MR_LD_REF { 1882 struct { 1883 u_int8_t targetId; 1884 u_int8_t reserved; 1885 u_int16_t seqNum; 1886 } ld_context; 1887 u_int32_t ref; 1888 } MR_LD_REF; 1889 1890 /* 1891 * defines the logical drive list structure 1892 */ 1893 #pragma pack(1) 1894 struct MR_LD_LIST { 1895 u_int32_t ldCount; 1896 u_int32_t reserved; 1897 struct { 1898 MR_LD_REF ref; 1899 u_int8_t state; 1900 u_int8_t reserved[3]; 1901 u_int64_t size; 1902 } ldList[MAX_LOGICAL_DRIVES_EXT]; 1903 }; 1904 1905 #pragma pack() 1906 1907 /* 1908 * SAS controller properties 1909 */ 1910 #pragma pack(1) 1911 struct mrsas_ctrl_prop { 1912 u_int16_t seq_num; 1913 u_int16_t pred_fail_poll_interval; 1914 u_int16_t intr_throttle_count; 1915 u_int16_t intr_throttle_timeouts; 1916 u_int8_t rebuild_rate; 1917 u_int8_t patrol_read_rate; 1918 u_int8_t bgi_rate; 1919 u_int8_t cc_rate; 1920 u_int8_t recon_rate; 1921 u_int8_t cache_flush_interval; 1922 u_int8_t spinup_drv_count; 1923 u_int8_t spinup_delay; 1924 u_int8_t cluster_enable; 1925 u_int8_t coercion_mode; 1926 u_int8_t alarm_enable; 1927 u_int8_t disable_auto_rebuild; 1928 u_int8_t disable_battery_warn; 1929 u_int8_t ecc_bucket_size; 1930 u_int16_t ecc_bucket_leak_rate; 1931 u_int8_t restore_hotspare_on_insertion; 1932 u_int8_t expose_encl_devices; 1933 u_int8_t maintainPdFailHistory; 1934 u_int8_t disallowHostRequestReordering; 1935 u_int8_t abortCCOnError; 1936 u_int8_t loadBalanceMode; 1937 u_int8_t disableAutoDetectBackplane; 1938 u_int8_t snapVDSpace; 1939 /* 1940 * Add properties that can be controlled by a bit in the following 1941 * structure. 1942 */ 1943 struct { 1944 #if _BYTE_ORDER == _LITTLE_ENDIAN 1945 u_int32_t copyBackDisabled:1; 1946 u_int32_t SMARTerEnabled:1; 1947 u_int32_t prCorrectUnconfiguredAreas:1; 1948 u_int32_t useFdeOnly:1; 1949 u_int32_t disableNCQ:1; 1950 u_int32_t SSDSMARTerEnabled:1; 1951 u_int32_t SSDPatrolReadEnabled:1; 1952 u_int32_t enableSpinDownUnconfigured:1; 1953 u_int32_t autoEnhancedImport:1; 1954 u_int32_t enableSecretKeyControl:1; 1955 u_int32_t disableOnlineCtrlReset:1; 1956 u_int32_t allowBootWithPinnedCache:1; 1957 u_int32_t disableSpinDownHS:1; 1958 u_int32_t enableJBOD:1; 1959 u_int32_t disableCacheBypass:1; 1960 u_int32_t useDiskActivityForLocate:1; 1961 u_int32_t enablePI:1; 1962 u_int32_t preventPIImport:1; 1963 u_int32_t useGlobalSparesForEmergency:1; 1964 u_int32_t useUnconfGoodForEmergency:1; 1965 u_int32_t useEmergencySparesforSMARTer:1; 1966 u_int32_t forceSGPIOForQuadOnly:1; 1967 u_int32_t enableConfigAutoBalance:1; 1968 u_int32_t enableVirtualCache:1; 1969 u_int32_t enableAutoLockRecovery:1; 1970 u_int32_t disableImmediateIO:1; 1971 u_int32_t disableT10RebuildAssist:1; 1972 u_int32_t ignore64ldRestriction:1; 1973 u_int32_t enableSwZone:1; 1974 u_int32_t limitMaxRateSATA3G:1; 1975 u_int32_t reserved:2; 1976 #else 1977 u_int32_t reserved:2; 1978 u_int32_t limitMaxRateSATA3G:1; 1979 u_int32_t enableSwZone:1; 1980 u_int32_t ignore64ldRestriction:1; 1981 u_int32_t disableT10RebuildAssist:1; 1982 u_int32_t disableImmediateIO:1; 1983 u_int32_t enableAutoLockRecovery:1; 1984 u_int32_t enableVirtualCache:1; 1985 u_int32_t enableConfigAutoBalance:1; 1986 u_int32_t forceSGPIOForQuadOnly:1; 1987 u_int32_t useEmergencySparesforSMARTer:1; 1988 u_int32_t useUnconfGoodForEmergency:1; 1989 u_int32_t useGlobalSparesForEmergency:1; 1990 u_int32_t preventPIImport:1; 1991 u_int32_t enablePI:1; 1992 u_int32_t useDiskActivityForLocate:1; 1993 u_int32_t disableCacheBypass:1; 1994 u_int32_t enableJBOD:1; 1995 u_int32_t disableSpinDownHS:1; 1996 u_int32_t allowBootWithPinnedCache:1; 1997 u_int32_t disableOnlineCtrlReset:1; 1998 u_int32_t enableSecretKeyControl:1; 1999 u_int32_t autoEnhancedImport:1; 2000 u_int32_t enableSpinDownUnconfigured:1; 2001 u_int32_t SSDPatrolReadEnabled:1; 2002 u_int32_t SSDSMARTerEnabled:1; 2003 u_int32_t disableNCQ:1; 2004 u_int32_t useFdeOnly:1; 2005 u_int32_t prCorrectUnconfiguredAreas:1; 2006 u_int32_t SMARTerEnabled:1; 2007 u_int32_t copyBackDisabled:1; 2008 #endif 2009 } OnOffProperties; 2010 u_int8_t autoSnapVDSpace; 2011 u_int8_t viewSpace; 2012 u_int16_t spinDownTime; 2013 u_int8_t reserved[24]; 2014 2015 }; 2016 2017 #pragma pack() 2018 2019 /* 2020 * SAS controller information 2021 */ 2022 struct mrsas_ctrl_info { 2023 /* 2024 * PCI device information 2025 */ 2026 struct { 2027 u_int16_t vendor_id; 2028 u_int16_t device_id; 2029 u_int16_t sub_vendor_id; 2030 u_int16_t sub_device_id; 2031 u_int8_t reserved[24]; 2032 } __packed pci; 2033 /* 2034 * Host interface information 2035 */ 2036 struct { 2037 u_int8_t PCIX:1; 2038 u_int8_t PCIE:1; 2039 u_int8_t iSCSI:1; 2040 u_int8_t SAS_3G:1; 2041 u_int8_t reserved_0:4; 2042 u_int8_t reserved_1[6]; 2043 u_int8_t port_count; 2044 u_int64_t port_addr[8]; 2045 } __packed host_interface; 2046 /* 2047 * Device (backend) interface information 2048 */ 2049 struct { 2050 u_int8_t SPI:1; 2051 u_int8_t SAS_3G:1; 2052 u_int8_t SATA_1_5G:1; 2053 u_int8_t SATA_3G:1; 2054 u_int8_t reserved_0:4; 2055 u_int8_t reserved_1[6]; 2056 u_int8_t port_count; 2057 u_int64_t port_addr[8]; 2058 } __packed device_interface; 2059 2060 u_int32_t image_check_word; 2061 u_int32_t image_component_count; 2062 2063 struct { 2064 char name[8]; 2065 char version[32]; 2066 char build_date[16]; 2067 char built_time[16]; 2068 } __packed image_component[8]; 2069 2070 u_int32_t pending_image_component_count; 2071 2072 struct { 2073 char name[8]; 2074 char version[32]; 2075 char build_date[16]; 2076 char build_time[16]; 2077 } __packed pending_image_component[8]; 2078 2079 u_int8_t max_arms; 2080 u_int8_t max_spans; 2081 u_int8_t max_arrays; 2082 u_int8_t max_lds; 2083 char product_name[80]; 2084 char serial_no[32]; 2085 2086 /* 2087 * Other physical/controller/operation information. Indicates the 2088 * presence of the hardware 2089 */ 2090 struct { 2091 u_int32_t bbu:1; 2092 u_int32_t alarm:1; 2093 u_int32_t nvram:1; 2094 u_int32_t uart:1; 2095 u_int32_t reserved:28; 2096 } __packed hw_present; 2097 2098 u_int32_t current_fw_time; 2099 2100 /* 2101 * Maximum data transfer sizes 2102 */ 2103 u_int16_t max_concurrent_cmds; 2104 u_int16_t max_sge_count; 2105 u_int32_t max_request_size; 2106 2107 /* 2108 * Logical and physical device counts 2109 */ 2110 u_int16_t ld_present_count; 2111 u_int16_t ld_degraded_count; 2112 u_int16_t ld_offline_count; 2113 2114 u_int16_t pd_present_count; 2115 u_int16_t pd_disk_present_count; 2116 u_int16_t pd_disk_pred_failure_count; 2117 u_int16_t pd_disk_failed_count; 2118 2119 /* 2120 * Memory size information 2121 */ 2122 u_int16_t nvram_size; 2123 u_int16_t memory_size; 2124 u_int16_t flash_size; 2125 2126 /* 2127 * Error counters 2128 */ 2129 u_int16_t mem_correctable_error_count; 2130 u_int16_t mem_uncorrectable_error_count; 2131 2132 /* 2133 * Cluster information 2134 */ 2135 u_int8_t cluster_permitted; 2136 u_int8_t cluster_active; 2137 2138 /* 2139 * Additional max data transfer sizes 2140 */ 2141 u_int16_t max_strips_per_io; 2142 2143 /* 2144 * Controller capabilities structures 2145 */ 2146 struct { 2147 u_int32_t raid_level_0:1; 2148 u_int32_t raid_level_1:1; 2149 u_int32_t raid_level_5:1; 2150 u_int32_t raid_level_1E:1; 2151 u_int32_t raid_level_6:1; 2152 u_int32_t reserved:27; 2153 } __packed raid_levels; 2154 2155 struct { 2156 u_int32_t rbld_rate:1; 2157 u_int32_t cc_rate:1; 2158 u_int32_t bgi_rate:1; 2159 u_int32_t recon_rate:1; 2160 u_int32_t patrol_rate:1; 2161 u_int32_t alarm_control:1; 2162 u_int32_t cluster_supported:1; 2163 u_int32_t bbu:1; 2164 u_int32_t spanning_allowed:1; 2165 u_int32_t dedicated_hotspares:1; 2166 u_int32_t revertible_hotspares:1; 2167 u_int32_t foreign_config_import:1; 2168 u_int32_t self_diagnostic:1; 2169 u_int32_t mixed_redundancy_arr:1; 2170 u_int32_t global_hot_spares:1; 2171 u_int32_t reserved:17; 2172 } __packed adapter_operations; 2173 2174 struct { 2175 u_int32_t read_policy:1; 2176 u_int32_t write_policy:1; 2177 u_int32_t io_policy:1; 2178 u_int32_t access_policy:1; 2179 u_int32_t disk_cache_policy:1; 2180 u_int32_t reserved:27; 2181 } __packed ld_operations; 2182 2183 struct { 2184 u_int8_t min; 2185 u_int8_t max; 2186 u_int8_t reserved[2]; 2187 } __packed stripe_sz_ops; 2188 2189 struct { 2190 u_int32_t force_online:1; 2191 u_int32_t force_offline:1; 2192 u_int32_t force_rebuild:1; 2193 u_int32_t reserved:29; 2194 } __packed pd_operations; 2195 2196 struct { 2197 u_int32_t ctrl_supports_sas:1; 2198 u_int32_t ctrl_supports_sata:1; 2199 u_int32_t allow_mix_in_encl:1; 2200 u_int32_t allow_mix_in_ld:1; 2201 u_int32_t allow_sata_in_cluster:1; 2202 u_int32_t reserved:27; 2203 } __packed pd_mix_support; 2204 2205 /* 2206 * Define ECC single-bit-error bucket information 2207 */ 2208 u_int8_t ecc_bucket_count; 2209 u_int8_t reserved_2[11]; 2210 2211 /* 2212 * Include the controller properties (changeable items) 2213 */ 2214 struct mrsas_ctrl_prop properties; 2215 2216 /* 2217 * Define FW pkg version (set in envt v'bles on OEM basis) 2218 */ 2219 char package_version[0x60]; 2220 2221 u_int64_t deviceInterfacePortAddr2[8]; 2222 u_int8_t reserved3[128]; 2223 2224 struct { 2225 u_int16_t minPdRaidLevel_0:4; 2226 u_int16_t maxPdRaidLevel_0:12; 2227 2228 u_int16_t minPdRaidLevel_1:4; 2229 u_int16_t maxPdRaidLevel_1:12; 2230 2231 u_int16_t minPdRaidLevel_5:4; 2232 u_int16_t maxPdRaidLevel_5:12; 2233 2234 u_int16_t minPdRaidLevel_1E:4; 2235 u_int16_t maxPdRaidLevel_1E:12; 2236 2237 u_int16_t minPdRaidLevel_6:4; 2238 u_int16_t maxPdRaidLevel_6:12; 2239 2240 u_int16_t minPdRaidLevel_10:4; 2241 u_int16_t maxPdRaidLevel_10:12; 2242 2243 u_int16_t minPdRaidLevel_50:4; 2244 u_int16_t maxPdRaidLevel_50:12; 2245 2246 u_int16_t minPdRaidLevel_60:4; 2247 u_int16_t maxPdRaidLevel_60:12; 2248 2249 u_int16_t minPdRaidLevel_1E_RLQ0:4; 2250 u_int16_t maxPdRaidLevel_1E_RLQ0:12; 2251 2252 u_int16_t minPdRaidLevel_1E0_RLQ0:4; 2253 u_int16_t maxPdRaidLevel_1E0_RLQ0:12; 2254 2255 u_int16_t reserved[6]; 2256 } pdsForRaidLevels; 2257 2258 u_int16_t maxPds; /* 0x780 */ 2259 u_int16_t maxDedHSPs; /* 0x782 */ 2260 u_int16_t maxGlobalHSPs; /* 0x784 */ 2261 u_int16_t ddfSize; /* 0x786 */ 2262 u_int8_t maxLdsPerArray; /* 0x788 */ 2263 u_int8_t partitionsInDDF; /* 0x789 */ 2264 u_int8_t lockKeyBinding; /* 0x78a */ 2265 u_int8_t maxPITsPerLd; /* 0x78b */ 2266 u_int8_t maxViewsPerLd; /* 0x78c */ 2267 u_int8_t maxTargetId; /* 0x78d */ 2268 u_int16_t maxBvlVdSize; /* 0x78e */ 2269 2270 u_int16_t maxConfigurableSSCSize; /* 0x790 */ 2271 u_int16_t currentSSCsize; /* 0x792 */ 2272 2273 char expanderFwVersion[12]; /* 0x794 */ 2274 2275 u_int16_t PFKTrialTimeRemaining;/* 0x7A0 */ 2276 2277 u_int16_t cacheMemorySize; /* 0x7A2 */ 2278 2279 struct { /* 0x7A4 */ 2280 #if _BYTE_ORDER == _LITTLE_ENDIAN 2281 u_int32_t supportPIcontroller:1; 2282 u_int32_t supportLdPIType1:1; 2283 u_int32_t supportLdPIType2:1; 2284 u_int32_t supportLdPIType3:1; 2285 u_int32_t supportLdBBMInfo:1; 2286 u_int32_t supportShieldState:1; 2287 u_int32_t blockSSDWriteCacheChange:1; 2288 u_int32_t supportSuspendResumeBGops:1; 2289 u_int32_t supportEmergencySpares:1; 2290 u_int32_t supportSetLinkSpeed:1; 2291 u_int32_t supportBootTimePFKChange:1; 2292 u_int32_t supportJBOD:1; 2293 u_int32_t disableOnlinePFKChange:1; 2294 u_int32_t supportPerfTuning:1; 2295 u_int32_t supportSSDPatrolRead:1; 2296 u_int32_t realTimeScheduler:1; 2297 2298 u_int32_t supportResetNow:1; 2299 u_int32_t supportEmulatedDrives:1; 2300 u_int32_t headlessMode:1; 2301 u_int32_t dedicatedHotSparesLimited:1; 2302 2303 u_int32_t supportUnevenSpans:1; 2304 u_int32_t reserved:11; 2305 #else 2306 u_int32_t reserved:11; 2307 u_int32_t supportUnevenSpans:1; 2308 u_int32_t dedicatedHotSparesLimited:1; 2309 u_int32_t headlessMode:1; 2310 u_int32_t supportEmulatedDrives:1; 2311 u_int32_t supportResetNow:1; 2312 u_int32_t realTimeScheduler:1; 2313 u_int32_t supportSSDPatrolRead:1; 2314 u_int32_t supportPerfTuning:1; 2315 u_int32_t disableOnlinePFKChange:1; 2316 u_int32_t supportJBOD:1; 2317 u_int32_t supportBootTimePFKChange:1; 2318 u_int32_t supportSetLinkSpeed:1; 2319 u_int32_t supportEmergencySpares:1; 2320 u_int32_t supportSuspendResumeBGops:1; 2321 u_int32_t blockSSDWriteCacheChange:1; 2322 u_int32_t supportShieldState:1; 2323 u_int32_t supportLdBBMInfo:1; 2324 u_int32_t supportLdPIType3:1; 2325 u_int32_t supportLdPIType2:1; 2326 u_int32_t supportLdPIType1:1; 2327 u_int32_t supportPIcontroller:1; 2328 #endif 2329 } adapterOperations2; 2330 2331 u_int8_t driverVersion[32]; /* 0x7A8 */ 2332 u_int8_t maxDAPdCountSpinup60; /* 0x7C8 */ 2333 u_int8_t temperatureROC; /* 0x7C9 */ 2334 u_int8_t temperatureCtrl; /* 0x7CA */ 2335 u_int8_t reserved4; /* 0x7CB */ 2336 u_int16_t maxConfigurablePds; /* 0x7CC */ 2337 2338 u_int8_t reserved5[2]; /* 0x7CD reserved */ 2339 2340 struct { 2341 #if _BYTE_ORDER == _LITTLE_ENDIAN 2342 u_int32_t peerIsPresent:1; 2343 u_int32_t peerIsIncompatible:1; 2344 2345 u_int32_t hwIncompatible:1; 2346 u_int32_t fwVersionMismatch:1; 2347 u_int32_t ctrlPropIncompatible:1; 2348 u_int32_t premiumFeatureMismatch:1; 2349 u_int32_t reserved:26; 2350 #else 2351 u_int32_t reserved:26; 2352 u_int32_t premiumFeatureMismatch:1; 2353 u_int32_t ctrlPropIncompatible:1; 2354 u_int32_t fwVersionMismatch:1; 2355 u_int32_t hwIncompatible:1; 2356 u_int32_t peerIsIncompatible:1; 2357 u_int32_t peerIsPresent:1; 2358 #endif 2359 } cluster; 2360 2361 char clusterId[16]; /* 0x7D4 */ 2362 2363 char reserved6[4]; /* 0x7E4 RESERVED FOR IOV */ 2364 2365 struct { /* 0x7E8 */ 2366 #if _BYTE_ORDER == _LITTLE_ENDIAN 2367 u_int32_t supportPersonalityChange:2; 2368 u_int32_t supportThermalPollInterval:1; 2369 u_int32_t supportDisableImmediateIO:1; 2370 u_int32_t supportT10RebuildAssist:1; 2371 u_int32_t supportMaxExtLDs:1; 2372 u_int32_t supportCrashDump:1; 2373 u_int32_t supportSwZone:1; 2374 u_int32_t supportDebugQueue:1; 2375 u_int32_t supportNVCacheErase:1; 2376 u_int32_t supportForceTo512e:1; 2377 u_int32_t supportHOQRebuild:1; 2378 u_int32_t supportAllowedOpsforDrvRemoval:1; 2379 u_int32_t supportDrvActivityLEDSetting:1; 2380 u_int32_t supportNVDRAM:1; 2381 u_int32_t supportForceFlash:1; 2382 u_int32_t supportDisableSESMonitoring:1; 2383 u_int32_t supportCacheBypassModes:1; 2384 u_int32_t supportSecurityonJBOD:1; 2385 u_int32_t discardCacheDuringLDDelete:1; 2386 u_int32_t supportTTYLogCompression:1; 2387 u_int32_t supportCPLDUpdate:1; 2388 u_int32_t supportDiskCacheSettingForSysPDs:1; 2389 u_int32_t supportExtendedSSCSize:1; 2390 u_int32_t useSeqNumJbodFP:1; 2391 u_int32_t reserved:7; 2392 #else 2393 u_int32_t reserved:7; 2394 u_int32_t useSeqNumJbodFP:1; 2395 u_int32_t supportExtendedSSCSize:1; 2396 u_int32_t supportDiskCacheSettingForSysPDs:1; 2397 u_int32_t supportCPLDUpdate:1; 2398 u_int32_t supportTTYLogCompression:1; 2399 u_int32_t discardCacheDuringLDDelete:1; 2400 u_int32_t supportSecurityonJBOD:1; 2401 u_int32_t supportCacheBypassModes:1; 2402 u_int32_t supportDisableSESMonitoring:1; 2403 u_int32_t supportForceFlash:1; 2404 u_int32_t supportNVDRAM:1; 2405 u_int32_t supportDrvActivityLEDSetting:1; 2406 u_int32_t supportAllowedOpsforDrvRemoval:1; 2407 u_int32_t supportHOQRebuild:1; 2408 u_int32_t supportForceTo512e:1; 2409 u_int32_t supportNVCacheErase:1; 2410 u_int32_t supportDebugQueue:1; 2411 u_int32_t supportSwZone:1; 2412 u_int32_t supportCrashDump:1; 2413 u_int32_t supportMaxExtLDs:1; 2414 u_int32_t supportT10RebuildAssist:1; 2415 u_int32_t supportDisableImmediateIO:1; 2416 u_int32_t supportThermalPollInterval:1; 2417 u_int32_t supportPersonalityChange:2; 2418 #endif 2419 } adapterOperations3; 2420 2421 u_int8_t pad_cpld[16]; 2422 2423 struct { 2424 #if _BYTE_ORDER == _LITTLE_ENDIAN 2425 u_int16_t ctrlInfoExtSupported:1; 2426 u_int16_t supportIbuttonLess:1; 2427 u_int16_t supportedEncAlgo:1; 2428 u_int16_t supportEncryptedMfc:1; 2429 u_int16_t imageUploadSupported:1; 2430 u_int16_t supportSESCtrlInMultipathCfg:1; 2431 u_int16_t supportPdMapTargetId:1; 2432 u_int16_t FWSwapsBBUVPDInfo:1; 2433 u_int16_t reserved:8; 2434 #else 2435 u_int16_t reserved:8; 2436 u_int16_t FWSwapsBBUVPDInfo:1; 2437 u_int16_t supportPdMapTargetId:1; 2438 u_int16_t supportSESCtrlInMultipathCfg:1; 2439 u_int16_t imageUploadSupported:1; 2440 u_int16_t supportEncryptedMfc:1; 2441 u_int16_t supportedEncAlgo:1; 2442 u_int16_t supportIbuttonLess:1; 2443 u_int16_t ctrlInfoExtSupported:1; 2444 #endif 2445 } adapterOperations4; 2446 2447 u_int8_t pad[0x800 - 0x7FE]; /* 0x7FE */ 2448 } __packed; 2449 2450 /* 2451 * When SCSI mid-layer calls driver's reset routine, driver waits for 2452 * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 2453 * that the driver cannot _actually_ abort or reset pending commands. While 2454 * it is waiting for the commands to complete, it prints a diagnostic message 2455 * every MRSAS_RESET_NOTICE_INTERVAL seconds 2456 */ 2457 #define MRSAS_RESET_WAIT_TIME 180 2458 #define MRSAS_INTERNAL_CMD_WAIT_TIME 180 2459 #define MRSAS_RESET_NOTICE_INTERVAL 5 2460 #define MRSAS_IOCTL_CMD 0 2461 #define MRSAS_DEFAULT_CMD_TIMEOUT 90 2462 #define MRSAS_THROTTLE_QUEUE_DEPTH 16 2463 2464 /* 2465 * MSI-x regsiters offset defines 2466 */ 2467 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) 2468 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 2469 #define MR_MAX_REPLY_QUEUES_OFFSET (0x0000001F) 2470 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET (0x003FC000) 2471 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14 2472 #define MR_MAX_MSIX_REG_ARRAY 16 2473 2474 /* 2475 * SYNC CACHE offset define 2476 */ 2477 #define MR_CAN_HANDLE_SYNC_CACHE_OFFSET 0X01000000 2478 2479 #define MR_ATOMIC_DESCRIPTOR_SUPPORT_OFFSET (1 << 24) 2480 2481 /* 2482 * FW reports the maximum of number of commands that it can accept (maximum 2483 * commands that can be outstanding) at any time. The driver must report a 2484 * lower number to the mid layer because it can issue a few internal commands 2485 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 2486 * is shown below 2487 */ 2488 #define MRSAS_INT_CMDS 32 2489 #define MRSAS_SKINNY_INT_CMDS 5 2490 #define MRSAS_MAX_MSIX_QUEUES 128 2491 2492 /* 2493 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit SGLs 2494 * based on the size of bus_addr_t 2495 */ 2496 #define IS_DMA64 (sizeof(bus_addr_t) == 8) 2497 2498 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 2499 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 2500 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 2501 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 2502 2503 #define MFI_OB_INTR_STATUS_MASK 0x00000002 2504 #define MFI_POLL_TIMEOUT_SECS 60 2505 2506 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 2507 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 2508 #define MFI_GEN2_ENABLE_INTERRUPT_MASK 0x00000001 2509 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 2510 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 2511 #define MFI_1068_PCSR_OFFSET 0x84 2512 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 2513 #define MFI_1068_FW_READY 0xDDDD0000 2514 2515 typedef union _MFI_CAPABILITIES { 2516 struct { 2517 #if _BYTE_ORDER == _LITTLE_ENDIAN 2518 u_int32_t support_fp_remote_lun:1; 2519 u_int32_t support_additional_msix:1; 2520 u_int32_t support_fastpath_wb:1; 2521 u_int32_t support_max_255lds:1; 2522 u_int32_t support_ndrive_r1_lb:1; 2523 u_int32_t support_core_affinity:1; 2524 u_int32_t security_protocol_cmds_fw:1; 2525 u_int32_t support_ext_queue_depth:1; 2526 u_int32_t support_ext_io_size:1; 2527 u_int32_t reserved:23; 2528 #else 2529 u_int32_t reserved:23; 2530 u_int32_t support_ext_io_size:1; 2531 u_int32_t support_ext_queue_depth:1; 2532 u_int32_t security_protocol_cmds_fw:1; 2533 u_int32_t support_core_affinity:1; 2534 u_int32_t support_ndrive_r1_lb:1; 2535 u_int32_t support_max_255lds:1; 2536 u_int32_t support_fastpath_wb:1; 2537 u_int32_t support_additional_msix:1; 2538 u_int32_t support_fp_remote_lun:1; 2539 #endif 2540 } mfi_capabilities; 2541 u_int32_t reg; 2542 } MFI_CAPABILITIES; 2543 2544 #pragma pack(1) 2545 struct mrsas_sge32 { 2546 u_int32_t phys_addr; 2547 u_int32_t length; 2548 }; 2549 2550 #pragma pack() 2551 2552 #pragma pack(1) 2553 struct mrsas_sge64 { 2554 u_int64_t phys_addr; 2555 u_int32_t length; 2556 }; 2557 2558 #pragma pack() 2559 2560 #pragma pack() 2561 union mrsas_sgl { 2562 struct mrsas_sge32 sge32[1]; 2563 struct mrsas_sge64 sge64[1]; 2564 }; 2565 2566 #pragma pack() 2567 2568 #pragma pack(1) 2569 struct mrsas_header { 2570 u_int8_t cmd; /* 00e */ 2571 u_int8_t sense_len; /* 01h */ 2572 u_int8_t cmd_status; /* 02h */ 2573 u_int8_t scsi_status; /* 03h */ 2574 2575 u_int8_t target_id; /* 04h */ 2576 u_int8_t lun; /* 05h */ 2577 u_int8_t cdb_len; /* 06h */ 2578 u_int8_t sge_count; /* 07h */ 2579 2580 u_int32_t context; /* 08h */ 2581 u_int32_t pad_0; /* 0Ch */ 2582 2583 u_int16_t flags; /* 10h */ 2584 u_int16_t timeout; /* 12h */ 2585 u_int32_t data_xferlen; /* 14h */ 2586 }; 2587 2588 #pragma pack() 2589 2590 #pragma pack(1) 2591 struct mrsas_init_frame { 2592 u_int8_t cmd; /* 00h */ 2593 u_int8_t reserved_0; /* 01h */ 2594 u_int8_t cmd_status; /* 02h */ 2595 2596 u_int8_t reserved_1; /* 03h */ 2597 MFI_CAPABILITIES driver_operations; /* 04h */ 2598 u_int32_t context; /* 08h */ 2599 u_int32_t pad_0; /* 0Ch */ 2600 2601 u_int16_t flags; /* 10h */ 2602 u_int16_t reserved_3; /* 12h */ 2603 u_int32_t data_xfer_len; /* 14h */ 2604 2605 u_int32_t queue_info_new_phys_addr_lo; /* 18h */ 2606 u_int32_t queue_info_new_phys_addr_hi; /* 1Ch */ 2607 u_int32_t queue_info_old_phys_addr_lo; /* 20h */ 2608 u_int32_t queue_info_old_phys_addr_hi; /* 24h */ 2609 u_int32_t driver_ver_lo; /* 28h */ 2610 u_int32_t driver_ver_hi; /* 2Ch */ 2611 u_int32_t reserved_4[4]; /* 30h */ 2612 }; 2613 2614 #pragma pack() 2615 2616 #pragma pack(1) 2617 struct mrsas_io_frame { 2618 u_int8_t cmd; /* 00h */ 2619 u_int8_t sense_len; /* 01h */ 2620 u_int8_t cmd_status; /* 02h */ 2621 u_int8_t scsi_status; /* 03h */ 2622 2623 u_int8_t target_id; /* 04h */ 2624 u_int8_t access_byte; /* 05h */ 2625 u_int8_t reserved_0; /* 06h */ 2626 u_int8_t sge_count; /* 07h */ 2627 2628 u_int32_t context; /* 08h */ 2629 u_int32_t pad_0; /* 0Ch */ 2630 2631 u_int16_t flags; /* 10h */ 2632 u_int16_t timeout; /* 12h */ 2633 u_int32_t lba_count; /* 14h */ 2634 2635 u_int32_t sense_buf_phys_addr_lo; /* 18h */ 2636 u_int32_t sense_buf_phys_addr_hi; /* 1Ch */ 2637 2638 u_int32_t start_lba_lo; /* 20h */ 2639 u_int32_t start_lba_hi; /* 24h */ 2640 2641 union mrsas_sgl sgl; /* 28h */ 2642 }; 2643 2644 #pragma pack() 2645 2646 #pragma pack(1) 2647 struct mrsas_pthru_frame { 2648 u_int8_t cmd; /* 00h */ 2649 u_int8_t sense_len; /* 01h */ 2650 u_int8_t cmd_status; /* 02h */ 2651 u_int8_t scsi_status; /* 03h */ 2652 2653 u_int8_t target_id; /* 04h */ 2654 u_int8_t lun; /* 05h */ 2655 u_int8_t cdb_len; /* 06h */ 2656 u_int8_t sge_count; /* 07h */ 2657 2658 u_int32_t context; /* 08h */ 2659 u_int32_t pad_0; /* 0Ch */ 2660 2661 u_int16_t flags; /* 10h */ 2662 u_int16_t timeout; /* 12h */ 2663 u_int32_t data_xfer_len; /* 14h */ 2664 2665 u_int32_t sense_buf_phys_addr_lo; /* 18h */ 2666 u_int32_t sense_buf_phys_addr_hi; /* 1Ch */ 2667 2668 u_int8_t cdb[16]; /* 20h */ 2669 union mrsas_sgl sgl; /* 30h */ 2670 }; 2671 2672 #pragma pack() 2673 2674 #pragma pack(1) 2675 struct mrsas_dcmd_frame { 2676 u_int8_t cmd; /* 00h */ 2677 u_int8_t reserved_0; /* 01h */ 2678 u_int8_t cmd_status; /* 02h */ 2679 u_int8_t reserved_1[4]; /* 03h */ 2680 u_int8_t sge_count; /* 07h */ 2681 2682 u_int32_t context; /* 08h */ 2683 u_int32_t pad_0; /* 0Ch */ 2684 2685 u_int16_t flags; /* 10h */ 2686 u_int16_t timeout; /* 12h */ 2687 2688 u_int32_t data_xfer_len; /* 14h */ 2689 u_int32_t opcode; /* 18h */ 2690 2691 union { /* 1Ch */ 2692 u_int8_t b[12]; 2693 u_int16_t s[6]; 2694 u_int32_t w[3]; 2695 } mbox; 2696 2697 union mrsas_sgl sgl; /* 28h */ 2698 }; 2699 2700 #pragma pack() 2701 2702 #pragma pack(1) 2703 struct mrsas_abort_frame { 2704 u_int8_t cmd; /* 00h */ 2705 u_int8_t reserved_0; /* 01h */ 2706 u_int8_t cmd_status; /* 02h */ 2707 2708 u_int8_t reserved_1; /* 03h */ 2709 MFI_CAPABILITIES driver_operations; /* 04h */ 2710 u_int32_t context; /* 08h */ 2711 u_int32_t pad_0; /* 0Ch */ 2712 2713 u_int16_t flags; /* 10h */ 2714 u_int16_t reserved_3; /* 12h */ 2715 u_int32_t reserved_4; /* 14h */ 2716 2717 u_int32_t abort_context; /* 18h */ 2718 u_int32_t pad_1; /* 1Ch */ 2719 2720 u_int32_t abort_mfi_phys_addr_lo; /* 20h */ 2721 u_int32_t abort_mfi_phys_addr_hi; /* 24h */ 2722 2723 u_int32_t reserved_5[6]; /* 28h */ 2724 }; 2725 2726 #pragma pack() 2727 2728 #pragma pack(1) 2729 struct mrsas_smp_frame { 2730 u_int8_t cmd; /* 00h */ 2731 u_int8_t reserved_1; /* 01h */ 2732 u_int8_t cmd_status; /* 02h */ 2733 u_int8_t connection_status; /* 03h */ 2734 2735 u_int8_t reserved_2[3]; /* 04h */ 2736 u_int8_t sge_count; /* 07h */ 2737 2738 u_int32_t context; /* 08h */ 2739 u_int32_t pad_0; /* 0Ch */ 2740 2741 u_int16_t flags; /* 10h */ 2742 u_int16_t timeout; /* 12h */ 2743 2744 u_int32_t data_xfer_len; /* 14h */ 2745 u_int64_t sas_addr; /* 18h */ 2746 2747 union { 2748 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: req */ 2749 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: req */ 2750 } sgl; 2751 }; 2752 2753 #pragma pack() 2754 2755 #pragma pack(1) 2756 struct mrsas_stp_frame { 2757 u_int8_t cmd; /* 00h */ 2758 u_int8_t reserved_1; /* 01h */ 2759 u_int8_t cmd_status; /* 02h */ 2760 u_int8_t reserved_2; /* 03h */ 2761 2762 u_int8_t target_id; /* 04h */ 2763 u_int8_t reserved_3[2]; /* 05h */ 2764 u_int8_t sge_count; /* 07h */ 2765 2766 u_int32_t context; /* 08h */ 2767 u_int32_t pad_0; /* 0Ch */ 2768 2769 u_int16_t flags; /* 10h */ 2770 u_int16_t timeout; /* 12h */ 2771 2772 u_int32_t data_xfer_len; /* 14h */ 2773 2774 u_int16_t fis[10]; /* 18h */ 2775 u_int32_t stp_flags; 2776 2777 union { 2778 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: data */ 2779 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: data */ 2780 } sgl; 2781 }; 2782 2783 #pragma pack() 2784 2785 union mrsas_frame { 2786 struct mrsas_header hdr; 2787 struct mrsas_init_frame init; 2788 struct mrsas_io_frame io; 2789 struct mrsas_pthru_frame pthru; 2790 struct mrsas_dcmd_frame dcmd; 2791 struct mrsas_abort_frame abort; 2792 struct mrsas_smp_frame smp; 2793 struct mrsas_stp_frame stp; 2794 u_int8_t raw_bytes[64]; 2795 }; 2796 2797 #pragma pack(1) 2798 union mrsas_evt_class_locale { 2799 struct { 2800 #if _BYTE_ORDER == _LITTLE_ENDIAN 2801 u_int16_t locale; 2802 u_int8_t reserved; 2803 int8_t class; 2804 #else 2805 int8_t class; 2806 u_int8_t reserved; 2807 u_int16_t locale; 2808 #endif 2809 } __packed members; 2810 2811 u_int32_t word; 2812 2813 } __packed; 2814 2815 #pragma pack() 2816 2817 #pragma pack(1) 2818 struct mrsas_evt_log_info { 2819 u_int32_t newest_seq_num; 2820 u_int32_t oldest_seq_num; 2821 u_int32_t clear_seq_num; 2822 u_int32_t shutdown_seq_num; 2823 u_int32_t boot_seq_num; 2824 2825 } __packed; 2826 2827 #pragma pack() 2828 2829 struct mrsas_progress { 2830 u_int16_t progress; 2831 u_int16_t elapsed_seconds; 2832 2833 } __packed; 2834 2835 struct mrsas_evtarg_ld { 2836 u_int16_t target_id; 2837 u_int8_t ld_index; 2838 u_int8_t reserved; 2839 2840 } __packed; 2841 2842 struct mrsas_evtarg_pd { 2843 u_int16_t device_id; 2844 u_int8_t encl_index; 2845 u_int8_t slot_number; 2846 2847 } __packed; 2848 2849 struct mrsas_evt_detail { 2850 u_int32_t seq_num; 2851 u_int32_t time_stamp; 2852 u_int32_t code; 2853 union mrsas_evt_class_locale cl; 2854 u_int8_t arg_type; 2855 u_int8_t reserved1[15]; 2856 2857 union { 2858 struct { 2859 struct mrsas_evtarg_pd pd; 2860 u_int8_t cdb_length; 2861 u_int8_t sense_length; 2862 u_int8_t reserved[2]; 2863 u_int8_t cdb[16]; 2864 u_int8_t sense[64]; 2865 } __packed cdbSense; 2866 2867 struct mrsas_evtarg_ld ld; 2868 2869 struct { 2870 struct mrsas_evtarg_ld ld; 2871 u_int64_t count; 2872 } __packed ld_count; 2873 2874 struct { 2875 u_int64_t lba; 2876 struct mrsas_evtarg_ld ld; 2877 } __packed ld_lba; 2878 2879 struct { 2880 struct mrsas_evtarg_ld ld; 2881 u_int32_t prevOwner; 2882 u_int32_t newOwner; 2883 } __packed ld_owner; 2884 2885 struct { 2886 u_int64_t ld_lba; 2887 u_int64_t pd_lba; 2888 struct mrsas_evtarg_ld ld; 2889 struct mrsas_evtarg_pd pd; 2890 } __packed ld_lba_pd_lba; 2891 2892 struct { 2893 struct mrsas_evtarg_ld ld; 2894 struct mrsas_progress prog; 2895 } __packed ld_prog; 2896 2897 struct { 2898 struct mrsas_evtarg_ld ld; 2899 u_int32_t prev_state; 2900 u_int32_t new_state; 2901 } __packed ld_state; 2902 2903 struct { 2904 u_int64_t strip; 2905 struct mrsas_evtarg_ld ld; 2906 } __packed ld_strip; 2907 2908 struct mrsas_evtarg_pd pd; 2909 2910 struct { 2911 struct mrsas_evtarg_pd pd; 2912 u_int32_t err; 2913 } __packed pd_err; 2914 2915 struct { 2916 u_int64_t lba; 2917 struct mrsas_evtarg_pd pd; 2918 } __packed pd_lba; 2919 2920 struct { 2921 u_int64_t lba; 2922 struct mrsas_evtarg_pd pd; 2923 struct mrsas_evtarg_ld ld; 2924 } __packed pd_lba_ld; 2925 2926 struct { 2927 struct mrsas_evtarg_pd pd; 2928 struct mrsas_progress prog; 2929 } __packed pd_prog; 2930 2931 struct { 2932 struct mrsas_evtarg_pd pd; 2933 u_int32_t prevState; 2934 u_int32_t newState; 2935 } __packed pd_state; 2936 2937 struct { 2938 u_int16_t vendorId; 2939 u_int16_t deviceId; 2940 u_int16_t subVendorId; 2941 u_int16_t subDeviceId; 2942 } __packed pci; 2943 2944 u_int32_t rate; 2945 char str[96]; 2946 2947 struct { 2948 u_int32_t rtc; 2949 u_int32_t elapsedSeconds; 2950 } __packed time; 2951 2952 struct { 2953 u_int32_t ecar; 2954 u_int32_t elog; 2955 char str[64]; 2956 } __packed ecc; 2957 2958 u_int8_t b[96]; 2959 u_int16_t s[48]; 2960 u_int32_t w[24]; 2961 u_int64_t d[12]; 2962 } args; 2963 2964 char description[128]; 2965 2966 } __packed; 2967 2968 struct mrsas_irq_context { 2969 struct mrsas_softc *sc; 2970 uint32_t MSIxIndex; 2971 }; 2972 2973 enum MEGASAS_OCR_REASON { 2974 FW_FAULT_OCR = 0, 2975 MFI_DCMD_TIMEOUT_OCR = 1, 2976 }; 2977 2978 /* Controller management info added to support Linux Emulator */ 2979 #define MAX_MGMT_ADAPTERS 1024 2980 2981 struct mrsas_mgmt_info { 2982 u_int16_t count; 2983 struct mrsas_softc *sc_ptr[MAX_MGMT_ADAPTERS]; 2984 int max_index; 2985 }; 2986 2987 #define PCI_TYPE0_ADDRESSES 6 2988 #define PCI_TYPE1_ADDRESSES 2 2989 #define PCI_TYPE2_ADDRESSES 5 2990 2991 typedef struct _MRSAS_DRV_PCI_COMMON_HEADER { 2992 u_int16_t vendorID; 2993 //(ro) 2994 u_int16_t deviceID; 2995 //(ro) 2996 u_int16_t command; 2997 //Device control 2998 u_int16_t status; 2999 u_int8_t revisionID; 3000 //(ro) 3001 u_int8_t progIf; 3002 //(ro) 3003 u_int8_t subClass; 3004 //(ro) 3005 u_int8_t baseClass; 3006 //(ro) 3007 u_int8_t cacheLineSize; 3008 //(ro +) 3009 u_int8_t latencyTimer; 3010 //(ro +) 3011 u_int8_t headerType; 3012 //(ro) 3013 u_int8_t bist; 3014 //Built in self test 3015 3016 union { 3017 struct _MRSAS_DRV_PCI_HEADER_TYPE_0 { 3018 u_int32_t baseAddresses[PCI_TYPE0_ADDRESSES]; 3019 u_int32_t cis; 3020 u_int16_t subVendorID; 3021 u_int16_t subSystemID; 3022 u_int32_t romBaseAddress; 3023 u_int8_t capabilitiesPtr; 3024 u_int8_t reserved1[3]; 3025 u_int32_t reserved2; 3026 u_int8_t interruptLine; 3027 u_int8_t interruptPin; 3028 //(ro) 3029 u_int8_t minimumGrant; 3030 //(ro) 3031 u_int8_t maximumLatency; 3032 //(ro) 3033 } type0; 3034 3035 /* 3036 * PCI to PCI Bridge 3037 */ 3038 3039 struct _MRSAS_DRV_PCI_HEADER_TYPE_1 { 3040 u_int32_t baseAddresses[PCI_TYPE1_ADDRESSES]; 3041 u_int8_t primaryBus; 3042 u_int8_t secondaryBus; 3043 u_int8_t subordinateBus; 3044 u_int8_t secondaryLatency; 3045 u_int8_t ioBase; 3046 u_int8_t ioLimit; 3047 u_int16_t secondaryStatus; 3048 u_int16_t memoryBase; 3049 u_int16_t memoryLimit; 3050 u_int16_t prefetchBase; 3051 u_int16_t prefetchLimit; 3052 u_int32_t prefetchBaseUpper32; 3053 u_int32_t prefetchLimitUpper32; 3054 u_int16_t ioBaseUpper16; 3055 u_int16_t ioLimitUpper16; 3056 u_int8_t capabilitiesPtr; 3057 u_int8_t reserved1[3]; 3058 u_int32_t romBaseAddress; 3059 u_int8_t interruptLine; 3060 u_int8_t interruptPin; 3061 u_int16_t bridgeControl; 3062 } type1; 3063 3064 /* 3065 * PCI to CARDBUS Bridge 3066 */ 3067 3068 struct _MRSAS_DRV_PCI_HEADER_TYPE_2 { 3069 u_int32_t socketRegistersBaseAddress; 3070 u_int8_t capabilitiesPtr; 3071 u_int8_t reserved; 3072 u_int16_t secondaryStatus; 3073 u_int8_t primaryBus; 3074 u_int8_t secondaryBus; 3075 u_int8_t subordinateBus; 3076 u_int8_t secondaryLatency; 3077 struct { 3078 u_int32_t base; 3079 u_int32_t limit; 3080 } range [PCI_TYPE2_ADDRESSES - 1]; 3081 u_int8_t interruptLine; 3082 u_int8_t interruptPin; 3083 u_int16_t bridgeControl; 3084 } type2; 3085 } u; 3086 3087 } MRSAS_DRV_PCI_COMMON_HEADER, *PMRSAS_DRV_PCI_COMMON_HEADER; 3088 3089 #define MRSAS_DRV_PCI_COMMON_HEADER_SIZE sizeof(MRSAS_DRV_PCI_COMMON_HEADER) //64 bytes 3090 3091 typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY { 3092 union { 3093 struct { 3094 #if _BYTE_ORDER == _LITTLE_ENDIAN 3095 u_int32_t linkSpeed:4; 3096 u_int32_t linkWidth:6; 3097 u_int32_t aspmSupport:2; 3098 u_int32_t losExitLatency:3; 3099 u_int32_t l1ExitLatency:3; 3100 u_int32_t rsvdp:6; 3101 u_int32_t portNumber:8; 3102 #else 3103 u_int32_t portNumber:8; 3104 u_int32_t rsvdp:6; 3105 u_int32_t l1ExitLatency:3; 3106 u_int32_t losExitLatency:3; 3107 u_int32_t aspmSupport:2; 3108 u_int32_t linkWidth:6; 3109 u_int32_t linkSpeed:4; 3110 #endif 3111 } bits; 3112 3113 u_int32_t asUlong; 3114 } u; 3115 } MRSAS_DRV_PCI_LINK_CAPABILITY, *PMRSAS_DRV_PCI_LINK_CAPABILITY; 3116 3117 #define MRSAS_DRV_PCI_LINK_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_CAPABILITY) 3118 3119 typedef struct _MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY { 3120 union { 3121 struct { 3122 #if _BYTE_ORDER == _LITTLE_ENDIAN 3123 u_int16_t linkSpeed:4; 3124 u_int16_t negotiatedLinkWidth:6; 3125 u_int16_t linkTrainingError:1; 3126 u_int16_t linkTraning:1; 3127 u_int16_t slotClockConfig:1; 3128 u_int16_t rsvdZ:3; 3129 #else 3130 u_int16_t rsvdZ:3; 3131 u_int16_t slotClockConfig:1; 3132 u_int16_t linkTraning:1; 3133 u_int16_t linkTrainingError:1; 3134 u_int16_t negotiatedLinkWidth:6; 3135 u_int16_t linkSpeed:4; 3136 #endif 3137 } bits; 3138 3139 u_int16_t asUshort; 3140 } u; 3141 u_int16_t reserved; 3142 } MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY, *PMRSAS_DRV_PCI_LINK_STATUS_CAPABILITY; 3143 3144 #define MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY) 3145 3146 typedef struct _MRSAS_DRV_PCI_CAPABILITIES { 3147 MRSAS_DRV_PCI_LINK_CAPABILITY linkCapability; 3148 MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY linkStatusCapability; 3149 } MRSAS_DRV_PCI_CAPABILITIES, *PMRSAS_DRV_PCI_CAPABILITIES; 3150 3151 #define MRSAS_DRV_PCI_CAPABILITIES_SIZE sizeof(MRSAS_DRV_PCI_CAPABILITIES) 3152 3153 /* PCI information */ 3154 typedef struct _MRSAS_DRV_PCI_INFORMATION { 3155 u_int32_t busNumber; 3156 u_int8_t deviceNumber; 3157 u_int8_t functionNumber; 3158 u_int8_t interruptVector; 3159 u_int8_t reserved1; 3160 MRSAS_DRV_PCI_COMMON_HEADER pciHeaderInfo; 3161 MRSAS_DRV_PCI_CAPABILITIES capability; 3162 u_int32_t domainID; 3163 u_int8_t reserved2[28]; 3164 } MRSAS_DRV_PCI_INFORMATION, *PMRSAS_DRV_PCI_INFORMATION; 3165 3166 typedef enum _MR_PD_TYPE { 3167 UNKNOWN_DRIVE = 0, 3168 PARALLEL_SCSI = 1, 3169 SAS_PD = 2, 3170 SATA_PD = 3, 3171 FC_PD = 4, 3172 NVME_PD = 5, 3173 } MR_PD_TYPE; 3174 3175 typedef union _MR_PD_REF { 3176 struct { 3177 u_int16_t deviceId; 3178 u_int16_t seqNum; 3179 } mrPdRef; 3180 u_int32_t ref; 3181 } MR_PD_REF; 3182 3183 /* 3184 * define the DDF Type bit structure 3185 */ 3186 union MR_PD_DDF_TYPE { 3187 struct { 3188 union { 3189 struct { 3190 #if _BYTE_ORDER == _LITTLE_ENDIAN 3191 u_int16_t forcedPDGUID:1; 3192 u_int16_t inVD:1; 3193 u_int16_t isGlobalSpare:1; 3194 u_int16_t isSpare:1; 3195 u_int16_t isForeign:1; 3196 u_int16_t reserved:7; 3197 u_int16_t intf:4; 3198 #else 3199 u_int16_t intf:4; 3200 u_int16_t reserved:7; 3201 u_int16_t isForeign:1; 3202 u_int16_t isSpare:1; 3203 u_int16_t isGlobalSpare:1; 3204 u_int16_t inVD:1; 3205 u_int16_t forcedPDGUID:1; 3206 #endif 3207 } pdType; 3208 u_int16_t type; 3209 }; 3210 u_int16_t reserved; 3211 } ddf; 3212 struct { 3213 u_int32_t reserved; 3214 } nonDisk; 3215 u_int32_t type; 3216 } __packed; 3217 3218 /* 3219 * defines the progress structure 3220 */ 3221 union MR_PROGRESS { 3222 struct { 3223 u_int16_t progress; 3224 union { 3225 u_int16_t elapsedSecs; 3226 u_int16_t elapsedSecsForLastPercent; 3227 }; 3228 } mrProgress; 3229 u_int32_t w; 3230 } __packed; 3231 3232 /* 3233 * defines the physical drive progress structure 3234 */ 3235 struct MR_PD_PROGRESS { 3236 struct { 3237 #if _BYTE_ORDER == _LITTLE_ENDIAN 3238 u_int32_t rbld:1; 3239 u_int32_t patrol:1; 3240 u_int32_t clear:1; 3241 u_int32_t copyBack:1; 3242 u_int32_t erase:1; 3243 u_int32_t locate:1; 3244 u_int32_t reserved:26; 3245 #else 3246 u_int32_t reserved:26; 3247 u_int32_t locate:1; 3248 u_int32_t erase:1; 3249 u_int32_t copyBack:1; 3250 u_int32_t clear:1; 3251 u_int32_t patrol:1; 3252 u_int32_t rbld:1; 3253 #endif 3254 } active; 3255 union MR_PROGRESS rbld; 3256 union MR_PROGRESS patrol; 3257 union { 3258 union MR_PROGRESS clear; 3259 union MR_PROGRESS erase; 3260 }; 3261 3262 struct { 3263 #if _BYTE_ORDER == _LITTLE_ENDIAN 3264 u_int32_t rbld:1; 3265 u_int32_t patrol:1; 3266 u_int32_t clear:1; 3267 u_int32_t copyBack:1; 3268 u_int32_t erase:1; 3269 u_int32_t reserved:27; 3270 #else 3271 u_int32_t reserved:27; 3272 u_int32_t erase:1; 3273 u_int32_t copyBack:1; 3274 u_int32_t clear:1; 3275 u_int32_t patrol:1; 3276 u_int32_t rbld:1; 3277 #endif 3278 } pause; 3279 3280 union MR_PROGRESS reserved[3]; 3281 } __packed; 3282 3283 struct mrsas_pd_info { 3284 MR_PD_REF ref; 3285 u_int8_t inquiryData[96]; 3286 u_int8_t vpdPage83[64]; 3287 3288 u_int8_t notSupported; 3289 u_int8_t scsiDevType; 3290 3291 union { 3292 u_int8_t connectedPortBitmap; 3293 u_int8_t connectedPortNumbers; 3294 }; 3295 3296 u_int8_t deviceSpeed; 3297 u_int32_t mediaErrCount; 3298 u_int32_t otherErrCount; 3299 u_int32_t predFailCount; 3300 u_int32_t lastPredFailEventSeqNum; 3301 3302 u_int16_t fwState; 3303 u_int8_t disabledForRemoval; 3304 u_int8_t linkSpeed; 3305 union MR_PD_DDF_TYPE state; 3306 3307 struct { 3308 u_int8_t count; 3309 #if _BYTE_ORDER == _LITTLE_ENDIAN 3310 u_int8_t isPathBroken:4; 3311 u_int8_t reserved3:3; 3312 u_int8_t widePortCapable:1; 3313 #else 3314 u_int8_t widePortCapable:1; 3315 u_int8_t reserved3:3; 3316 u_int8_t isPathBroken:4; 3317 #endif 3318 u_int8_t connectorIndex[2]; 3319 u_int8_t reserved[4]; 3320 u_int64_t sasAddr[2]; 3321 u_int8_t reserved2[16]; 3322 } pathInfo; 3323 3324 u_int64_t rawSize; 3325 u_int64_t nonCoercedSize; 3326 u_int64_t coercedSize; 3327 u_int16_t enclDeviceId; 3328 u_int8_t enclIndex; 3329 3330 union { 3331 u_int8_t slotNumber; 3332 u_int8_t enclConnectorIndex; 3333 }; 3334 3335 struct MR_PD_PROGRESS progInfo; 3336 u_int8_t badBlockTableFull; 3337 u_int8_t unusableInCurrentConfig; 3338 u_int8_t vpdPage83Ext[64]; 3339 u_int8_t powerState; 3340 u_int8_t enclPosition; 3341 u_int32_t allowedOps; 3342 u_int16_t copyBackPartnerId; 3343 u_int16_t enclPartnerDeviceId; 3344 struct { 3345 #if _BYTE_ORDER == _LITTLE_ENDIAN 3346 u_int16_t fdeCapable:1; 3347 u_int16_t fdeEnabled:1; 3348 u_int16_t secured:1; 3349 u_int16_t locked:1; 3350 u_int16_t foreign:1; 3351 u_int16_t needsEKM:1; 3352 u_int16_t reserved:10; 3353 #else 3354 u_int16_t reserved:10; 3355 u_int16_t needsEKM:1; 3356 u_int16_t foreign:1; 3357 u_int16_t locked:1; 3358 u_int16_t secured:1; 3359 u_int16_t fdeEnabled:1; 3360 u_int16_t fdeCapable:1; 3361 #endif 3362 } security; 3363 u_int8_t mediaType; 3364 u_int8_t notCertified; 3365 u_int8_t bridgeVendor[8]; 3366 u_int8_t bridgeProductIdentification[16]; 3367 u_int8_t bridgeProductRevisionLevel[4]; 3368 u_int8_t satBridgeExists; 3369 3370 u_int8_t interfaceType; 3371 u_int8_t temperature; 3372 u_int8_t emulatedBlockSize; 3373 u_int16_t userDataBlockSize; 3374 u_int16_t reserved2; 3375 3376 struct { 3377 #if _BYTE_ORDER == _LITTLE_ENDIAN 3378 u_int32_t piType:3; 3379 u_int32_t piFormatted:1; 3380 u_int32_t piEligible:1; 3381 u_int32_t NCQ:1; 3382 u_int32_t WCE:1; 3383 u_int32_t commissionedSpare:1; 3384 u_int32_t emergencySpare:1; 3385 u_int32_t ineligibleForSSCD:1; 3386 u_int32_t ineligibleForLd:1; 3387 u_int32_t useSSEraseType:1; 3388 u_int32_t wceUnchanged:1; 3389 u_int32_t supportScsiUnmap:1; 3390 u_int32_t reserved:18; 3391 #else 3392 u_int32_t reserved:18; 3393 u_int32_t supportScsiUnmap:1; 3394 u_int32_t wceUnchanged:1; 3395 u_int32_t useSSEraseType:1; 3396 u_int32_t ineligibleForLd:1; 3397 u_int32_t ineligibleForSSCD:1; 3398 u_int32_t emergencySpare:1; 3399 u_int32_t commissionedSpare:1; 3400 u_int32_t WCE:1; 3401 u_int32_t NCQ:1; 3402 u_int32_t piEligible:1; 3403 u_int32_t piFormatted:1; 3404 u_int32_t piType:3; 3405 #endif 3406 } properties; 3407 3408 u_int64_t shieldDiagCompletionTime; 3409 u_int8_t shieldCounter; 3410 3411 u_int8_t linkSpeedOther; 3412 u_int8_t reserved4[2]; 3413 3414 struct { 3415 #if _BYTE_ORDER == _LITTLE_ENDIAN 3416 u_int32_t bbmErrCountSupported:1; 3417 u_int32_t bbmErrCount:31; 3418 #else 3419 u_int32_t bbmErrCount:31; 3420 u_int32_t bbmErrCountSupported:1; 3421 #endif 3422 } bbmErr; 3423 3424 u_int8_t reserved1[512-428]; 3425 } __packed; 3426 3427 struct mrsas_target { 3428 u_int16_t target_id; 3429 u_int32_t queue_depth; 3430 u_int8_t interface_type; 3431 u_int32_t max_io_size_kb; 3432 } __packed; 3433 3434 #define MR_NVME_PAGE_SIZE_MASK 0x000000FF 3435 #define MR_DEFAULT_NVME_PAGE_SIZE 4096 3436 #define MR_DEFAULT_NVME_PAGE_SHIFT 12 3437 3438 /******************************************************************* 3439 * per-instance data 3440 ********************************************************************/ 3441 struct mrsas_softc { 3442 device_t mrsas_dev; 3443 struct cdev *mrsas_cdev; 3444 struct intr_config_hook mrsas_ich; 3445 struct cdev *mrsas_linux_emulator_cdev; 3446 uint16_t device_id; 3447 struct resource *reg_res; 3448 int reg_res_id; 3449 bus_space_tag_t bus_tag; 3450 bus_space_handle_t bus_handle; 3451 bus_dma_tag_t mrsas_parent_tag; 3452 bus_dma_tag_t verbuf_tag; 3453 bus_dmamap_t verbuf_dmamap; 3454 void *verbuf_mem; 3455 bus_addr_t verbuf_phys_addr; 3456 bus_dma_tag_t sense_tag; 3457 bus_dmamap_t sense_dmamap; 3458 void *sense_mem; 3459 bus_addr_t sense_phys_addr; 3460 bus_dma_tag_t io_request_tag; 3461 bus_dmamap_t io_request_dmamap; 3462 void *io_request_mem; 3463 bus_addr_t io_request_phys_addr; 3464 bus_dma_tag_t chain_frame_tag; 3465 bus_dmamap_t chain_frame_dmamap; 3466 void *chain_frame_mem; 3467 bus_addr_t chain_frame_phys_addr; 3468 bus_dma_tag_t reply_desc_tag; 3469 bus_dmamap_t reply_desc_dmamap; 3470 void *reply_desc_mem; 3471 bus_addr_t reply_desc_phys_addr; 3472 bus_dma_tag_t ioc_init_tag; 3473 bus_dmamap_t ioc_init_dmamap; 3474 void *ioc_init_mem; 3475 bus_addr_t ioc_init_phys_mem; 3476 bus_dma_tag_t data_tag; 3477 struct cam_sim *sim_0; 3478 struct cam_sim *sim_1; 3479 struct cam_path *path_0; 3480 struct cam_path *path_1; 3481 struct mtx sim_lock; 3482 struct mtx pci_lock; 3483 struct mtx io_lock; 3484 struct mtx ioctl_lock; 3485 struct mtx mpt_cmd_pool_lock; 3486 struct mtx mfi_cmd_pool_lock; 3487 struct mtx raidmap_lock; 3488 struct mtx aen_lock; 3489 struct mtx stream_lock; 3490 struct selinfo mrsas_select; 3491 uint32_t mrsas_aen_triggered; 3492 uint32_t mrsas_poll_waiting; 3493 3494 struct sema ioctl_count_sema; 3495 uint32_t max_fw_cmds; 3496 uint16_t max_scsi_cmds; 3497 uint32_t max_num_sge; 3498 struct resource *mrsas_irq[MAX_MSIX_COUNT]; 3499 void *intr_handle[MAX_MSIX_COUNT]; 3500 int irq_id[MAX_MSIX_COUNT]; 3501 struct mrsas_irq_context irq_context[MAX_MSIX_COUNT]; 3502 int msix_vectors; 3503 int msix_enable; 3504 uint32_t msix_reg_offset[16]; 3505 uint8_t mask_interrupts; 3506 uint16_t max_chain_frame_sz; 3507 struct mrsas_mpt_cmd **mpt_cmd_list; 3508 struct mrsas_mfi_cmd **mfi_cmd_list; 3509 TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head; 3510 TAILQ_HEAD(, mrsas_mfi_cmd) mrsas_mfi_cmd_list_head; 3511 bus_addr_t req_frames_desc_phys; 3512 u_int8_t *req_frames_desc; 3513 u_int8_t *req_desc; 3514 bus_addr_t io_request_frames_phys; 3515 u_int8_t *io_request_frames; 3516 bus_addr_t reply_frames_desc_phys; 3517 u_int16_t last_reply_idx[MAX_MSIX_COUNT]; 3518 u_int32_t reply_q_depth; 3519 u_int32_t request_alloc_sz; 3520 u_int32_t reply_alloc_sz; 3521 u_int32_t io_frames_alloc_sz; 3522 u_int32_t chain_frames_alloc_sz; 3523 u_int16_t max_sge_in_main_msg; 3524 u_int16_t max_sge_in_chain; 3525 u_int8_t chain_offset_io_request; 3526 u_int8_t chain_offset_mfi_pthru; 3527 u_int32_t map_sz; 3528 u_int64_t map_id; 3529 u_int64_t pd_seq_map_id; 3530 struct mrsas_mfi_cmd *map_update_cmd; 3531 struct mrsas_mfi_cmd *jbod_seq_cmd; 3532 struct mrsas_mfi_cmd *aen_cmd; 3533 u_int8_t fast_path_io; 3534 void *chan; 3535 void *ocr_chan; 3536 u_int8_t adprecovery; 3537 u_int8_t remove_in_progress; 3538 u_int8_t ocr_thread_active; 3539 u_int8_t do_timedout_reset; 3540 u_int32_t reset_in_progress; 3541 u_int32_t reset_count; 3542 u_int32_t block_sync_cache; 3543 u_int32_t drv_stream_detection; 3544 u_int8_t fw_sync_cache_support; 3545 mrsas_atomic_t target_reset_outstanding; 3546 #define MRSAS_MAX_TM_TARGETS (MRSAS_MAX_PD + MRSAS_MAX_LD_IDS) 3547 struct mrsas_mpt_cmd *target_reset_pool[MRSAS_MAX_TM_TARGETS]; 3548 3549 bus_dma_tag_t jbodmap_tag[2]; 3550 bus_dmamap_t jbodmap_dmamap[2]; 3551 void *jbodmap_mem[2]; 3552 bus_addr_t jbodmap_phys_addr[2]; 3553 3554 bus_dma_tag_t raidmap_tag[2]; 3555 bus_dmamap_t raidmap_dmamap[2]; 3556 void *raidmap_mem[2]; 3557 bus_addr_t raidmap_phys_addr[2]; 3558 bus_dma_tag_t mficmd_frame_tag; 3559 bus_dma_tag_t mficmd_sense_tag; 3560 bus_addr_t evt_detail_phys_addr; 3561 bus_dma_tag_t evt_detail_tag; 3562 bus_dmamap_t evt_detail_dmamap; 3563 struct mrsas_evt_detail *evt_detail_mem; 3564 bus_addr_t pd_info_phys_addr; 3565 bus_dma_tag_t pd_info_tag; 3566 bus_dmamap_t pd_info_dmamap; 3567 struct mrsas_pd_info *pd_info_mem; 3568 struct mrsas_ctrl_info *ctrl_info; 3569 bus_dma_tag_t ctlr_info_tag; 3570 bus_dmamap_t ctlr_info_dmamap; 3571 void *ctlr_info_mem; 3572 bus_addr_t ctlr_info_phys_addr; 3573 u_int32_t max_sectors_per_req; 3574 u_int32_t disableOnlineCtrlReset; 3575 mrsas_atomic_t fw_outstanding; 3576 mrsas_atomic_t prp_count; 3577 mrsas_atomic_t sge_holes; 3578 3579 u_int32_t mrsas_debug; 3580 u_int32_t mrsas_io_timeout; 3581 u_int32_t mrsas_fw_fault_check_delay; 3582 u_int32_t io_cmds_highwater; 3583 u_int8_t UnevenSpanSupport; 3584 struct sysctl_ctx_list sysctl_ctx; 3585 struct sysctl_oid *sysctl_tree; 3586 struct proc *ocr_thread; 3587 u_int32_t last_seq_num; 3588 bus_dma_tag_t el_info_tag; 3589 bus_dmamap_t el_info_dmamap; 3590 void *el_info_mem; 3591 bus_addr_t el_info_phys_addr; 3592 struct mrsas_pd_list pd_list[MRSAS_MAX_PD]; 3593 struct mrsas_pd_list local_pd_list[MRSAS_MAX_PD]; 3594 struct mrsas_target target_list[MRSAS_MAX_TM_TARGETS]; 3595 u_int8_t ld_ids[MRSAS_MAX_LD_IDS]; 3596 struct taskqueue *ev_tq; 3597 struct task ev_task; 3598 u_int32_t CurLdCount; 3599 u_int64_t reset_flags; 3600 int lb_pending_cmds; 3601 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT]; 3602 LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT]; 3603 3604 u_int8_t mrsas_gen3_ctrl; 3605 u_int8_t secure_jbod_support; 3606 u_int8_t use_seqnum_jbod_fp; 3607 /* FW suport for more than 256 PD/JBOD */ 3608 u_int32_t support_morethan256jbod; 3609 u_int8_t max256vdSupport; 3610 u_int16_t fw_supported_vd_count; 3611 u_int16_t fw_supported_pd_count; 3612 3613 u_int16_t drv_supported_vd_count; 3614 u_int16_t drv_supported_pd_count; 3615 3616 u_int32_t max_map_sz; 3617 u_int32_t current_map_sz; 3618 u_int32_t old_map_sz; 3619 u_int32_t new_map_sz; 3620 u_int32_t drv_map_sz; 3621 3622 u_int32_t nvme_page_size; 3623 boolean_t is_ventura; 3624 boolean_t is_aero; 3625 boolean_t msix_combined; 3626 boolean_t atomic_desc_support; 3627 u_int16_t maxRaidMapSize; 3628 3629 /* Non dma-able memory. Driver local copy. */ 3630 MR_DRV_RAID_MAP_ALL *ld_drv_map[2]; 3631 PTR_LD_STREAM_DETECT *streamDetectByLD; 3632 }; 3633 3634 /* Compatibility shims for different OS versions */ 3635 #if __FreeBSD_version >= 800001 3636 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 3637 kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 3638 #define mrsas_kproc_exit(arg) kproc_exit(arg) 3639 #else 3640 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 3641 kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 3642 #define mrsas_kproc_exit(arg) kthread_exit(arg) 3643 #endif 3644 3645 static __inline void 3646 mrsas_clear_bit(int b, volatile void *p) 3647 { 3648 atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 3649 } 3650 3651 static __inline void 3652 mrsas_set_bit(int b, volatile void *p) 3653 { 3654 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 3655 } 3656 3657 static __inline int 3658 mrsas_test_bit(int b, volatile void *p) 3659 { 3660 return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f)); 3661 } 3662 3663 #endif /* MRSAS_H */ 3664