1 /* 2 * Copyright (c) 2015, AVAGO Tech. All rights reserved. Authors: Marian Choy 3 * Copyright (c) 2014, LSI Corp. All rights reserved. Authors: Marian Choy 4 * Support: freebsdraid@avagotech.com 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 2. Redistributions 12 * in binary form must reproduce the above copyright notice, this list of 13 * conditions and the following disclaimer in the documentation and/or other 14 * materials provided with the distribution. 3. Neither the name of the 15 * <ORGANIZATION> nor the names of its contributors may be used to endorse or 16 * promote products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * The views and conclusions contained in the software and documentation are 32 * those of the authors and should not be interpreted as representing 33 * official policies,either expressed or implied, of the FreeBSD Project. 34 * 35 * Send feedback to: <megaraidfbsd@avagotech.com> Mail to: AVAGO TECHNOLOGIES, 1621 36 * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD 37 * 38 */ 39 40 #include <sys/cdefs.h> 41 __FBSDID("$FreeBSD$"); 42 43 #ifndef MRSAS_H 44 #define MRSAS_H 45 46 #include <sys/param.h> /* defines used in kernel.h */ 47 #include <sys/module.h> 48 #include <sys/systm.h> 49 #include <sys/proc.h> 50 #include <sys/errno.h> 51 #include <sys/kernel.h> /* types used in module initialization */ 52 #include <sys/conf.h> /* cdevsw struct */ 53 #include <sys/uio.h> /* uio struct */ 54 #include <sys/malloc.h> 55 #include <sys/bus.h> /* structs, prototypes for pci bus 56 * stuff */ 57 #include <sys/rman.h> 58 #include <sys/types.h> 59 #include <sys/lock.h> 60 #include <sys/sema.h> 61 #include <sys/sysctl.h> 62 #include <sys/stat.h> 63 #include <sys/taskqueue.h> 64 #include <sys/poll.h> 65 #include <sys/selinfo.h> 66 67 #include <machine/bus.h> 68 #include <machine/resource.h> 69 #include <machine/atomic.h> 70 71 #include <dev/pci/pcivar.h> /* For pci_get macros! */ 72 #include <dev/pci/pcireg.h> 73 74 75 #define IOCTL_SEMA_DESCRIPTION "mrsas semaphore for MFI pool" 76 77 /* 78 * Device IDs and PCI 79 */ 80 #define MRSAS_TBOLT 0x005b 81 #define MRSAS_INVADER 0x005d 82 #define MRSAS_FURY 0x005f 83 #define MRSAS_INTRUDER 0x00ce 84 #define MRSAS_INTRUDER_24 0x00cf 85 #define MRSAS_PCI_BAR0 0x10 86 #define MRSAS_PCI_BAR1 0x14 87 #define MRSAS_PCI_BAR2 0x1C 88 89 /* 90 * Firmware State Defines 91 */ 92 #define MRSAS_FWSTATE_MAXCMD_MASK 0x0000FFFF 93 #define MRSAS_FWSTATE_SGE_MASK 0x00FF0000 94 #define MRSAS_FW_STATE_CHNG_INTERRUPT 1 95 96 /* 97 * Message Frame Defines 98 */ 99 #define MRSAS_SENSE_LEN 96 100 #define MRSAS_FUSION_MAX_RESET_TRIES 3 101 102 /* 103 * Miscellaneous Defines 104 */ 105 #define BYTE_ALIGNMENT 1 106 #define MRSAS_MAX_NAME_LENGTH 32 107 #define MRSAS_VERSION "06.709.07.00-fbsd" 108 #define MRSAS_ULONG_MAX 0xFFFFFFFFFFFFFFFF 109 #define MRSAS_DEFAULT_TIMEOUT 0x14 /* Temporarily set */ 110 #define DONE 0 111 #define MRSAS_PAGE_SIZE 4096 112 #define MRSAS_RESET_NOTICE_INTERVAL 5 113 #define MRSAS_IO_TIMEOUT 180000 /* 180 second timeout */ 114 #define MRSAS_LDIO_QUEUE_DEPTH 70 /* 70 percent as default */ 115 #define THRESHOLD_REPLY_COUNT 50 116 #define MAX_MSIX_COUNT 128 117 118 /* 119 * Boolean types 120 */ 121 #if (__FreeBSD_version < 901000) 122 typedef enum _boolean { 123 false, true 124 } boolean; 125 126 #endif 127 enum err { 128 SUCCESS, FAIL 129 }; 130 131 MALLOC_DECLARE(M_MRSAS); 132 SYSCTL_DECL(_hw_mrsas); 133 134 #define MRSAS_INFO (1 << 0) 135 #define MRSAS_TRACE (1 << 1) 136 #define MRSAS_FAULT (1 << 2) 137 #define MRSAS_OCR (1 << 3) 138 #define MRSAS_TOUT MRSAS_OCR 139 #define MRSAS_AEN (1 << 4) 140 #define MRSAS_PRL11 (1 << 5) 141 142 #define mrsas_dprint(sc, level, msg, args...) \ 143 do { \ 144 if (sc->mrsas_debug & level) \ 145 device_printf(sc->mrsas_dev, msg, ##args); \ 146 } while (0) 147 148 149 /**************************************************************************** 150 * Raid Context structure which describes MegaRAID specific IO Paramenters 151 * This resides at offset 0x60 where the SGL normally starts in MPT IO Frames 152 ****************************************************************************/ 153 154 typedef struct _RAID_CONTEXT { 155 u_int8_t Type:4; 156 u_int8_t nseg:4; 157 u_int8_t resvd0; 158 u_int16_t timeoutValue; 159 u_int8_t regLockFlags; 160 u_int8_t resvd1; 161 u_int16_t VirtualDiskTgtId; 162 u_int64_t regLockRowLBA; 163 u_int32_t regLockLength; 164 u_int16_t nextLMId; 165 u_int8_t exStatus; 166 u_int8_t status; 167 u_int8_t RAIDFlags; 168 u_int8_t numSGE; 169 u_int16_t configSeqNum; 170 u_int8_t spanArm; 171 u_int8_t priority; /* 0x1D MR_PRIORITY_RANGE */ 172 u_int8_t numSGEExt; /* 0x1E 1M IO support */ 173 u_int8_t resvd2; /* 0x1F */ 174 } RAID_CONTEXT; 175 176 177 /************************************************************************* 178 * MPI2 Defines 179 ************************************************************************/ 180 181 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 182 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 183 #define MPI2_VERSION_MAJOR (0x02) 184 #define MPI2_VERSION_MINOR (0x00) 185 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 186 #define MPI2_VERSION_MAJOR_SHIFT (8) 187 #define MPI2_VERSION_MINOR_MASK (0x00FF) 188 #define MPI2_VERSION_MINOR_SHIFT (0) 189 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 190 MPI2_VERSION_MINOR) 191 #define MPI2_HEADER_VERSION_UNIT (0x10) 192 #define MPI2_HEADER_VERSION_DEV (0x00) 193 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 194 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 195 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 196 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 197 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 198 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 199 #define MPI2_SCSIIO_EEDPFLAGS_INC_PRI_REFTAG (0x8000) 200 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REFTAG (0x0400) 201 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_REMOVE_OP (0x0003) 202 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_APPTAG (0x0200) 203 #define MPI2_SCSIIO_EEDPFLAGS_CHECK_GUARD (0x0100) 204 #define MPI2_SCSIIO_EEDPFLAGS_INSERT_OP (0x0004) 205 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 206 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 207 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 208 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 209 #define MPI2_SCSIIO_CONTROL_WRITE (0x01000000) 210 #define MPI2_SCSIIO_CONTROL_READ (0x02000000) 211 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 212 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 213 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 214 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 215 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 216 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 217 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 218 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 219 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 220 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 221 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 222 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 223 224 #ifndef MPI2_POINTER 225 #define MPI2_POINTER * 226 #endif 227 228 229 /*************************************** 230 * MPI2 Structures 231 ***************************************/ 232 233 typedef struct _MPI25_IEEE_SGE_CHAIN64 { 234 u_int64_t Address; 235 u_int32_t Length; 236 u_int16_t Reserved1; 237 u_int8_t NextChainOffset; 238 u_int8_t Flags; 239 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, 240 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t; 241 242 typedef struct _MPI2_SGE_SIMPLE_UNION { 243 u_int32_t FlagsLength; 244 union { 245 u_int32_t Address32; 246 u_int64_t Address64; 247 } u; 248 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 249 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 250 251 typedef struct { 252 u_int8_t CDB[20]; /* 0x00 */ 253 u_int32_t PrimaryReferenceTag; /* 0x14 */ 254 u_int16_t PrimaryApplicationTag;/* 0x18 */ 255 u_int16_t PrimaryApplicationTagMask; /* 0x1A */ 256 u_int32_t TransferLength; /* 0x1C */ 257 } MPI2_SCSI_IO_CDB_EEDP32, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_EEDP32, 258 Mpi2ScsiIoCdbEedp32_t, MPI2_POINTER pMpi2ScsiIoCdbEedp32_t; 259 260 typedef struct _MPI2_SGE_CHAIN_UNION { 261 u_int16_t Length; 262 u_int8_t NextChainOffset; 263 u_int8_t Flags; 264 union { 265 u_int32_t Address32; 266 u_int64_t Address64; 267 } u; 268 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 269 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 270 271 typedef struct _MPI2_IEEE_SGE_SIMPLE32 { 272 u_int32_t Address; 273 u_int32_t FlagsLength; 274 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 275 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 276 typedef struct _MPI2_IEEE_SGE_SIMPLE64 { 277 u_int64_t Address; 278 u_int32_t Length; 279 u_int16_t Reserved1; 280 u_int8_t Reserved2; 281 u_int8_t Flags; 282 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 283 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 284 285 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION { 286 MPI2_IEEE_SGE_SIMPLE32 Simple32; 287 MPI2_IEEE_SGE_SIMPLE64 Simple64; 288 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 289 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 290 291 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 292 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 293 294 typedef union _MPI2_IEEE_SGE_CHAIN_UNION { 295 MPI2_IEEE_SGE_CHAIN32 Chain32; 296 MPI2_IEEE_SGE_CHAIN64 Chain64; 297 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 298 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 299 300 typedef union _MPI2_SGE_IO_UNION { 301 MPI2_SGE_SIMPLE_UNION MpiSimple; 302 MPI2_SGE_CHAIN_UNION MpiChain; 303 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 304 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 305 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 306 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 307 308 typedef union { 309 u_int8_t CDB32[32]; 310 MPI2_SCSI_IO_CDB_EEDP32 EEDP32; 311 MPI2_SGE_SIMPLE_UNION SGE; 312 } MPI2_SCSI_IO_CDB_UNION, MPI2_POINTER PTR_MPI2_SCSI_IO_CDB_UNION, 313 Mpi2ScsiIoCdb_t, MPI2_POINTER pMpi2ScsiIoCdb_t; 314 315 /* 316 * RAID SCSI IO Request Message Total SGE count will be one less than 317 * _MPI2_SCSI_IO_REQUEST 318 */ 319 typedef struct _MPI2_RAID_SCSI_IO_REQUEST { 320 u_int16_t DevHandle; /* 0x00 */ 321 u_int8_t ChainOffset; /* 0x02 */ 322 u_int8_t Function; /* 0x03 */ 323 u_int16_t Reserved1; /* 0x04 */ 324 u_int8_t Reserved2; /* 0x06 */ 325 u_int8_t MsgFlags; /* 0x07 */ 326 u_int8_t VP_ID; /* 0x08 */ 327 u_int8_t VF_ID; /* 0x09 */ 328 u_int16_t Reserved3; /* 0x0A */ 329 u_int32_t SenseBufferLowAddress;/* 0x0C */ 330 u_int16_t SGLFlags; /* 0x10 */ 331 u_int8_t SenseBufferLength; /* 0x12 */ 332 u_int8_t Reserved4; /* 0x13 */ 333 u_int8_t SGLOffset0; /* 0x14 */ 334 u_int8_t SGLOffset1; /* 0x15 */ 335 u_int8_t SGLOffset2; /* 0x16 */ 336 u_int8_t SGLOffset3; /* 0x17 */ 337 u_int32_t SkipCount; /* 0x18 */ 338 u_int32_t DataLength; /* 0x1C */ 339 u_int32_t BidirectionalDataLength; /* 0x20 */ 340 u_int16_t IoFlags; /* 0x24 */ 341 u_int16_t EEDPFlags; /* 0x26 */ 342 u_int32_t EEDPBlockSize; /* 0x28 */ 343 u_int32_t SecondaryReferenceTag;/* 0x2C */ 344 u_int16_t SecondaryApplicationTag; /* 0x30 */ 345 u_int16_t ApplicationTagTranslationMask; /* 0x32 */ 346 u_int8_t LUN[8]; /* 0x34 */ 347 u_int32_t Control; /* 0x3C */ 348 MPI2_SCSI_IO_CDB_UNION CDB; /* 0x40 */ 349 RAID_CONTEXT RaidContext; /* 0x60 */ 350 MPI2_SGE_IO_UNION SGL; /* 0x80 */ 351 } MRSAS_RAID_SCSI_IO_REQUEST, MPI2_POINTER PTR_MRSAS_RAID_SCSI_IO_REQUEST, 352 MRSASRaidSCSIIORequest_t, MPI2_POINTER pMRSASRaidSCSIIORequest_t; 353 354 /* 355 * MPT RAID MFA IO Descriptor. 356 */ 357 typedef struct _MRSAS_RAID_MFA_IO_DESCRIPTOR { 358 u_int32_t RequestFlags:8; 359 u_int32_t MessageAddress1:24; /* bits 31:8 */ 360 u_int32_t MessageAddress2; /* bits 61:32 */ 361 } MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR, *PMRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR; 362 363 /* Default Request Descriptor */ 364 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR { 365 u_int8_t RequestFlags; /* 0x00 */ 366 u_int8_t MSIxIndex; /* 0x01 */ 367 u_int16_t SMID; /* 0x02 */ 368 u_int16_t LMID; /* 0x04 */ 369 u_int16_t DescriptorTypeDependent; /* 0x06 */ 370 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 371 372 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 373 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 374 375 /* High Priority Request Descriptor */ 376 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR { 377 u_int8_t RequestFlags; /* 0x00 */ 378 u_int8_t MSIxIndex; /* 0x01 */ 379 u_int16_t SMID; /* 0x02 */ 380 u_int16_t LMID; /* 0x04 */ 381 u_int16_t Reserved1; /* 0x06 */ 382 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 383 384 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 385 Mpi2HighPriorityRequestDescriptor_t, MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 386 387 /* SCSI IO Request Descriptor */ 388 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR { 389 u_int8_t RequestFlags; /* 0x00 */ 390 u_int8_t MSIxIndex; /* 0x01 */ 391 u_int16_t SMID; /* 0x02 */ 392 u_int16_t LMID; /* 0x04 */ 393 u_int16_t DevHandle; /* 0x06 */ 394 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 395 396 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 397 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 398 399 /* SCSI Target Request Descriptor */ 400 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR { 401 u_int8_t RequestFlags; /* 0x00 */ 402 u_int8_t MSIxIndex; /* 0x01 */ 403 u_int16_t SMID; /* 0x02 */ 404 u_int16_t LMID; /* 0x04 */ 405 u_int16_t IoIndex; /* 0x06 */ 406 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 407 408 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 409 Mpi2SCSITargetRequestDescriptor_t, MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 410 411 /* RAID Accelerator Request Descriptor */ 412 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR { 413 u_int8_t RequestFlags; /* 0x00 */ 414 u_int8_t MSIxIndex; /* 0x01 */ 415 u_int16_t SMID; /* 0x02 */ 416 u_int16_t LMID; /* 0x04 */ 417 u_int16_t Reserved; /* 0x06 */ 418 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 419 420 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 421 Mpi2RAIDAcceleratorRequestDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 422 423 /* union of Request Descriptors */ 424 typedef union _MRSAS_REQUEST_DESCRIPTOR_UNION { 425 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 426 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 427 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 428 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 429 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 430 MRSAS_RAID_MFA_IO_REQUEST_DESCRIPTOR MFAIo; 431 union { 432 struct { 433 u_int32_t low; 434 u_int32_t high; 435 } u; 436 u_int64_t Words; 437 } addr; 438 } MRSAS_REQUEST_DESCRIPTOR_UNION; 439 440 /* Default Reply Descriptor */ 441 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR { 442 u_int8_t ReplyFlags; /* 0x00 */ 443 u_int8_t MSIxIndex; /* 0x01 */ 444 u_int16_t DescriptorTypeDependent1; /* 0x02 */ 445 u_int32_t DescriptorTypeDependent2; /* 0x04 */ 446 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 447 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 448 449 /* Address Reply Descriptor */ 450 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR { 451 u_int8_t ReplyFlags; /* 0x00 */ 452 u_int8_t MSIxIndex; /* 0x01 */ 453 u_int16_t SMID; /* 0x02 */ 454 u_int32_t ReplyFrameAddress; /* 0x04 */ 455 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 456 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 457 458 /* SCSI IO Success Reply Descriptor */ 459 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR { 460 u_int8_t ReplyFlags; /* 0x00 */ 461 u_int8_t MSIxIndex; /* 0x01 */ 462 u_int16_t SMID; /* 0x02 */ 463 u_int16_t TaskTag; /* 0x04 */ 464 u_int16_t Reserved1; /* 0x06 */ 465 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 466 467 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 468 Mpi2SCSIIOSuccessReplyDescriptor_t, MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 469 470 /* TargetAssist Success Reply Descriptor */ 471 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR { 472 u_int8_t ReplyFlags; /* 0x00 */ 473 u_int8_t MSIxIndex; /* 0x01 */ 474 u_int16_t SMID; /* 0x02 */ 475 u_int8_t SequenceNumber; /* 0x04 */ 476 u_int8_t Reserved1; /* 0x05 */ 477 u_int16_t IoIndex; /* 0x06 */ 478 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 479 480 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 481 Mpi2TargetAssistSuccessReplyDescriptor_t, MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 482 483 /* Target Command Buffer Reply Descriptor */ 484 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR { 485 u_int8_t ReplyFlags; /* 0x00 */ 486 u_int8_t MSIxIndex; /* 0x01 */ 487 u_int8_t VP_ID; /* 0x02 */ 488 u_int8_t Flags; /* 0x03 */ 489 u_int16_t InitiatorDevHandle; /* 0x04 */ 490 u_int16_t IoIndex; /* 0x06 */ 491 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 492 493 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 494 Mpi2TargetCommandBufferReplyDescriptor_t, MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 495 496 /* RAID Accelerator Success Reply Descriptor */ 497 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR { 498 u_int8_t ReplyFlags; /* 0x00 */ 499 u_int8_t MSIxIndex; /* 0x01 */ 500 u_int16_t SMID; /* 0x02 */ 501 u_int32_t Reserved; /* 0x04 */ 502 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 503 504 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 505 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 506 507 /* union of Reply Descriptors */ 508 typedef union _MPI2_REPLY_DESCRIPTORS_UNION { 509 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 510 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 511 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 512 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 513 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 514 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 515 u_int64_t Words; 516 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 517 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 518 519 typedef union { 520 volatile unsigned int val; 521 unsigned int val_rdonly; 522 } mrsas_atomic_t; 523 524 #define mrsas_atomic_read(v) atomic_load_acq_int(&(v)->val) 525 #define mrsas_atomic_set(v,i) atomic_store_rel_int(&(v)->val, i) 526 #define mrsas_atomic_dec(v) atomic_fetchadd_int(&(v)->val, -1) 527 #define mrsas_atomic_inc(v) atomic_fetchadd_int(&(v)->val, 1) 528 529 /* IOCInit Request message */ 530 typedef struct _MPI2_IOC_INIT_REQUEST { 531 u_int8_t WhoInit; /* 0x00 */ 532 u_int8_t Reserved1; /* 0x01 */ 533 u_int8_t ChainOffset; /* 0x02 */ 534 u_int8_t Function; /* 0x03 */ 535 u_int16_t Reserved2; /* 0x04 */ 536 u_int8_t Reserved3; /* 0x06 */ 537 u_int8_t MsgFlags; /* 0x07 */ 538 u_int8_t VP_ID; /* 0x08 */ 539 u_int8_t VF_ID; /* 0x09 */ 540 u_int16_t Reserved4; /* 0x0A */ 541 u_int16_t MsgVersion; /* 0x0C */ 542 u_int16_t HeaderVersion; /* 0x0E */ 543 u_int32_t Reserved5; /* 0x10 */ 544 u_int16_t Reserved6; /* 0x14 */ 545 u_int8_t Reserved7; /* 0x16 */ 546 u_int8_t HostMSIxVectors; /* 0x17 */ 547 u_int16_t Reserved8; /* 0x18 */ 548 u_int16_t SystemRequestFrameSize; /* 0x1A */ 549 u_int16_t ReplyDescriptorPostQueueDepth; /* 0x1C */ 550 u_int16_t ReplyFreeQueueDepth; /* 0x1E */ 551 u_int32_t SenseBufferAddressHigh; /* 0x20 */ 552 u_int32_t SystemReplyAddressHigh; /* 0x24 */ 553 u_int64_t SystemRequestFrameBaseAddress; /* 0x28 */ 554 u_int64_t ReplyDescriptorPostQueueAddress; /* 0x30 */ 555 u_int64_t ReplyFreeQueueAddress;/* 0x38 */ 556 u_int64_t TimeStamp; /* 0x40 */ 557 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 558 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 559 560 /* 561 * MR private defines 562 */ 563 #define MR_PD_INVALID 0xFFFF 564 #define MAX_SPAN_DEPTH 8 565 #define MAX_QUAD_DEPTH MAX_SPAN_DEPTH 566 #define MAX_RAIDMAP_SPAN_DEPTH (MAX_SPAN_DEPTH) 567 #define MAX_ROW_SIZE 32 568 #define MAX_RAIDMAP_ROW_SIZE (MAX_ROW_SIZE) 569 #define MAX_LOGICAL_DRIVES 64 570 #define MAX_LOGICAL_DRIVES_EXT 256 571 572 #define MAX_RAIDMAP_LOGICAL_DRIVES (MAX_LOGICAL_DRIVES) 573 #define MAX_RAIDMAP_VIEWS (MAX_LOGICAL_DRIVES) 574 575 #define MAX_ARRAYS 128 576 #define MAX_RAIDMAP_ARRAYS (MAX_ARRAYS) 577 578 #define MAX_ARRAYS_EXT 256 579 #define MAX_API_ARRAYS_EXT MAX_ARRAYS_EXT 580 581 #define MAX_PHYSICAL_DEVICES 256 582 #define MAX_RAIDMAP_PHYSICAL_DEVICES (MAX_PHYSICAL_DEVICES) 583 #define MR_DCMD_LD_MAP_GET_INFO 0x0300e101 584 #define MR_DCMD_SYSTEM_PD_MAP_GET_INFO 0x0200e102 585 586 587 #define MRSAS_MAX_PD_CHANNELS 1 588 #define MRSAS_MAX_LD_CHANNELS 1 589 #define MRSAS_MAX_DEV_PER_CHANNEL 256 590 #define MRSAS_DEFAULT_INIT_ID -1 591 #define MRSAS_MAX_LUN 8 592 #define MRSAS_DEFAULT_CMD_PER_LUN 256 593 #define MRSAS_MAX_PD (MRSAS_MAX_PD_CHANNELS * \ 594 MRSAS_MAX_DEV_PER_CHANNEL) 595 #define MRSAS_MAX_LD_IDS (MRSAS_MAX_LD_CHANNELS * \ 596 MRSAS_MAX_DEV_PER_CHANNEL) 597 598 599 #define VD_EXT_DEBUG 0 600 601 602 /******************************************************************* 603 * RAID map related structures 604 ********************************************************************/ 605 #pragma pack(1) 606 typedef struct _MR_DEV_HANDLE_INFO { 607 u_int16_t curDevHdl; 608 u_int8_t validHandles; 609 u_int8_t reserved; 610 u_int16_t devHandle[2]; 611 } MR_DEV_HANDLE_INFO; 612 613 #pragma pack() 614 615 typedef struct _MR_ARRAY_INFO { 616 u_int16_t pd[MAX_RAIDMAP_ROW_SIZE]; 617 } MR_ARRAY_INFO; 618 619 typedef struct _MR_QUAD_ELEMENT { 620 u_int64_t logStart; 621 u_int64_t logEnd; 622 u_int64_t offsetInSpan; 623 u_int32_t diff; 624 u_int32_t reserved1; 625 } MR_QUAD_ELEMENT; 626 627 typedef struct _MR_SPAN_INFO { 628 u_int32_t noElements; 629 u_int32_t reserved1; 630 MR_QUAD_ELEMENT quad[MAX_RAIDMAP_SPAN_DEPTH]; 631 } MR_SPAN_INFO; 632 633 typedef struct _MR_LD_SPAN_ { 634 u_int64_t startBlk; 635 u_int64_t numBlks; 636 u_int16_t arrayRef; 637 u_int8_t spanRowSize; 638 u_int8_t spanRowDataSize; 639 u_int8_t reserved[4]; 640 } MR_LD_SPAN; 641 642 typedef struct _MR_SPAN_BLOCK_INFO { 643 u_int64_t num_rows; 644 MR_LD_SPAN span; 645 MR_SPAN_INFO block_span_info; 646 } MR_SPAN_BLOCK_INFO; 647 648 typedef struct _MR_LD_RAID { 649 struct { 650 u_int32_t fpCapable:1; 651 u_int32_t reserved5:3; 652 u_int32_t ldPiMode:4; 653 u_int32_t pdPiMode:4; 654 u_int32_t encryptionType:8; 655 u_int32_t fpWriteCapable:1; 656 u_int32_t fpReadCapable:1; 657 u_int32_t fpWriteAcrossStripe:1; 658 u_int32_t fpReadAcrossStripe:1; 659 u_int32_t fpNonRWCapable:1; 660 u_int32_t reserved4:7; 661 } capability; 662 u_int32_t reserved6; 663 u_int64_t size; 664 665 u_int8_t spanDepth; 666 u_int8_t level; 667 u_int8_t stripeShift; 668 u_int8_t rowSize; 669 670 u_int8_t rowDataSize; 671 u_int8_t writeMode; 672 u_int8_t PRL; 673 u_int8_t SRL; 674 675 u_int16_t targetId; 676 u_int8_t ldState; 677 u_int8_t regTypeReqOnWrite; 678 u_int8_t modFactor; 679 u_int8_t regTypeReqOnRead; 680 u_int16_t seqNum; 681 682 struct { 683 u_int32_t ldSyncRequired:1; 684 u_int32_t regTypeReqOnReadLsValid:1; 685 u_int32_t reserved:30; 686 } flags; 687 688 u_int8_t LUN[8]; 689 u_int8_t fpIoTimeoutForLd; 690 u_int8_t reserved2[3]; 691 u_int32_t logicalBlockLength; 692 struct { 693 u_int32_t LdPiExp:4; 694 u_int32_t LdLogicalBlockExp:4; 695 u_int32_t reserved1:24; 696 } exponent; 697 u_int8_t reserved3[0x80 - 0x38]; 698 } MR_LD_RAID; 699 700 typedef struct _MR_LD_SPAN_MAP { 701 MR_LD_RAID ldRaid; 702 u_int8_t dataArmMap[MAX_RAIDMAP_ROW_SIZE]; 703 MR_SPAN_BLOCK_INFO spanBlock[MAX_RAIDMAP_SPAN_DEPTH]; 704 } MR_LD_SPAN_MAP; 705 706 typedef struct _MR_FW_RAID_MAP { 707 u_int32_t totalSize; 708 union { 709 struct { 710 u_int32_t maxLd; 711 u_int32_t maxSpanDepth; 712 u_int32_t maxRowSize; 713 u_int32_t maxPdCount; 714 u_int32_t maxArrays; 715 } validationInfo; 716 u_int32_t version[5]; 717 u_int32_t reserved1[5]; 718 } raid_desc; 719 u_int32_t ldCount; 720 u_int32_t Reserved1; 721 722 /* 723 * This doesn't correspond to FW Ld Tgt Id to LD, but will purge. For 724 * example: if tgt Id is 4 and FW LD is 2, and there is only one LD, 725 * FW will populate the array like this. [0xFF, 0xFF, 0xFF, 0xFF, 726 * 0x0,.....]. This is to help reduce the entire strcture size if 727 * there are few LDs or driver is looking info for 1 LD only. 728 */ 729 u_int8_t ldTgtIdToLd[MAX_RAIDMAP_LOGICAL_DRIVES + MAX_RAIDMAP_VIEWS]; 730 u_int8_t fpPdIoTimeoutSec; 731 u_int8_t reserved2[7]; 732 MR_ARRAY_INFO arMapInfo[MAX_RAIDMAP_ARRAYS]; 733 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 734 MR_LD_SPAN_MAP ldSpanMap[1]; 735 } MR_FW_RAID_MAP; 736 737 738 typedef struct _MR_FW_RAID_MAP_EXT { 739 /* Not used in new map */ 740 u_int32_t reserved; 741 742 union { 743 struct { 744 u_int32_t maxLd; 745 u_int32_t maxSpanDepth; 746 u_int32_t maxRowSize; 747 u_int32_t maxPdCount; 748 u_int32_t maxArrays; 749 } validationInfo; 750 u_int32_t version[5]; 751 u_int32_t reserved1[5]; 752 } fw_raid_desc; 753 754 u_int8_t fpPdIoTimeoutSec; 755 u_int8_t reserved2[7]; 756 757 u_int16_t ldCount; 758 u_int16_t arCount; 759 u_int16_t spanCount; 760 u_int16_t reserve3; 761 762 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 763 u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; 764 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; 765 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT]; 766 } MR_FW_RAID_MAP_EXT; 767 768 769 typedef struct _MR_DRV_RAID_MAP { 770 /* 771 * Total size of this structure, including this field. This feild 772 * will be manupulated by driver for ext raid map, else pick the 773 * value from firmware raid map. 774 */ 775 u_int32_t totalSize; 776 777 union { 778 struct { 779 u_int32_t maxLd; 780 u_int32_t maxSpanDepth; 781 u_int32_t maxRowSize; 782 u_int32_t maxPdCount; 783 u_int32_t maxArrays; 784 } validationInfo; 785 u_int32_t version[5]; 786 u_int32_t reserved1[5]; 787 } drv_raid_desc; 788 789 /* timeout value used by driver in FP IOs */ 790 u_int8_t fpPdIoTimeoutSec; 791 u_int8_t reserved2[7]; 792 793 u_int16_t ldCount; 794 u_int16_t arCount; 795 u_int16_t spanCount; 796 u_int16_t reserve3; 797 798 MR_DEV_HANDLE_INFO devHndlInfo[MAX_RAIDMAP_PHYSICAL_DEVICES]; 799 u_int8_t ldTgtIdToLd[MAX_LOGICAL_DRIVES_EXT]; 800 MR_ARRAY_INFO arMapInfo[MAX_API_ARRAYS_EXT]; 801 MR_LD_SPAN_MAP ldSpanMap[1]; 802 803 } MR_DRV_RAID_MAP; 804 805 /* 806 * Driver raid map size is same as raid map ext MR_DRV_RAID_MAP_ALL is 807 * created to sync with old raid. And it is mainly for code re-use purpose. 808 */ 809 810 #pragma pack(1) 811 typedef struct _MR_DRV_RAID_MAP_ALL { 812 813 MR_DRV_RAID_MAP raidMap; 814 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES_EXT - 1]; 815 } MR_DRV_RAID_MAP_ALL; 816 817 #pragma pack() 818 819 typedef struct _LD_LOAD_BALANCE_INFO { 820 u_int8_t loadBalanceFlag; 821 u_int8_t reserved1; 822 mrsas_atomic_t scsi_pending_cmds[MAX_PHYSICAL_DEVICES]; 823 u_int64_t last_accessed_block[MAX_PHYSICAL_DEVICES]; 824 } LD_LOAD_BALANCE_INFO, *PLD_LOAD_BALANCE_INFO; 825 826 /* SPAN_SET is info caclulated from span info from Raid map per ld */ 827 typedef struct _LD_SPAN_SET { 828 u_int64_t log_start_lba; 829 u_int64_t log_end_lba; 830 u_int64_t span_row_start; 831 u_int64_t span_row_end; 832 u_int64_t data_strip_start; 833 u_int64_t data_strip_end; 834 u_int64_t data_row_start; 835 u_int64_t data_row_end; 836 u_int8_t strip_offset[MAX_SPAN_DEPTH]; 837 u_int32_t span_row_data_width; 838 u_int32_t diff; 839 u_int32_t reserved[2]; 840 } LD_SPAN_SET, *PLD_SPAN_SET; 841 842 typedef struct LOG_BLOCK_SPAN_INFO { 843 LD_SPAN_SET span_set[MAX_SPAN_DEPTH]; 844 } LD_SPAN_INFO, *PLD_SPAN_INFO; 845 846 #pragma pack(1) 847 typedef struct _MR_FW_RAID_MAP_ALL { 848 MR_FW_RAID_MAP raidMap; 849 MR_LD_SPAN_MAP ldSpanMap[MAX_LOGICAL_DRIVES - 1]; 850 } MR_FW_RAID_MAP_ALL; 851 852 #pragma pack() 853 854 struct IO_REQUEST_INFO { 855 u_int64_t ldStartBlock; 856 u_int32_t numBlocks; 857 u_int16_t ldTgtId; 858 u_int8_t isRead; 859 u_int16_t devHandle; 860 u_int64_t pdBlock; 861 u_int8_t fpOkForIo; 862 u_int8_t IoforUnevenSpan; 863 u_int8_t start_span; 864 u_int8_t reserved; 865 u_int64_t start_row; 866 /* span[7:5], arm[4:0] */ 867 u_int8_t span_arm; 868 u_int8_t pd_after_lb; 869 }; 870 871 /* 872 * define MR_PD_CFG_SEQ structure for system PDs 873 */ 874 struct MR_PD_CFG_SEQ { 875 u_int16_t seqNum; 876 u_int16_t devHandle; 877 u_int8_t reserved[4]; 878 } __packed; 879 880 struct MR_PD_CFG_SEQ_NUM_SYNC { 881 u_int32_t size; 882 u_int32_t count; 883 struct MR_PD_CFG_SEQ seq[1]; 884 } __packed; 885 886 887 typedef struct _MR_LD_TARGET_SYNC { 888 u_int8_t targetId; 889 u_int8_t reserved; 890 u_int16_t seqNum; 891 } MR_LD_TARGET_SYNC; 892 893 #define IEEE_SGE_FLAGS_ADDR_MASK (0x03) 894 #define IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 895 #define IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 896 #define IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 897 #define IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 898 #define IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 899 #define IEEE_SGE_FLAGS_END_OF_LIST (0x40) 900 901 union desc_value { 902 u_int64_t word; 903 struct { 904 u_int32_t low; 905 u_int32_t high; 906 } u; 907 }; 908 909 /******************************************************************* 910 * Temporary command 911 ********************************************************************/ 912 struct mrsas_tmp_dcmd { 913 bus_dma_tag_t tmp_dcmd_tag; 914 bus_dmamap_t tmp_dcmd_dmamap; 915 void *tmp_dcmd_mem; 916 bus_addr_t tmp_dcmd_phys_addr; 917 }; 918 919 /******************************************************************* 920 * Register set, included legacy controllers 1068 and 1078, 921 * structure extended for 1078 registers 922 *******************************************************************/ 923 #pragma pack(1) 924 typedef struct _mrsas_register_set { 925 u_int32_t doorbell; /* 0000h */ 926 u_int32_t fusion_seq_offset; /* 0004h */ 927 u_int32_t fusion_host_diag; /* 0008h */ 928 u_int32_t reserved_01; /* 000Ch */ 929 930 u_int32_t inbound_msg_0; /* 0010h */ 931 u_int32_t inbound_msg_1; /* 0014h */ 932 u_int32_t outbound_msg_0; /* 0018h */ 933 u_int32_t outbound_msg_1; /* 001Ch */ 934 935 u_int32_t inbound_doorbell; /* 0020h */ 936 u_int32_t inbound_intr_status; /* 0024h */ 937 u_int32_t inbound_intr_mask; /* 0028h */ 938 939 u_int32_t outbound_doorbell; /* 002Ch */ 940 u_int32_t outbound_intr_status; /* 0030h */ 941 u_int32_t outbound_intr_mask; /* 0034h */ 942 943 u_int32_t reserved_1[2]; /* 0038h */ 944 945 u_int32_t inbound_queue_port; /* 0040h */ 946 u_int32_t outbound_queue_port; /* 0044h */ 947 948 u_int32_t reserved_2[9]; /* 0048h */ 949 u_int32_t reply_post_host_index;/* 006Ch */ 950 u_int32_t reserved_2_2[12]; /* 0070h */ 951 952 u_int32_t outbound_doorbell_clear; /* 00A0h */ 953 954 u_int32_t reserved_3[3]; /* 00A4h */ 955 956 u_int32_t outbound_scratch_pad; /* 00B0h */ 957 u_int32_t outbound_scratch_pad_2; /* 00B4h */ 958 959 u_int32_t reserved_4[2]; /* 00B8h */ 960 961 u_int32_t inbound_low_queue_port; /* 00C0h */ 962 963 u_int32_t inbound_high_queue_port; /* 00C4h */ 964 965 u_int32_t reserved_5; /* 00C8h */ 966 u_int32_t res_6[11]; /* CCh */ 967 u_int32_t host_diag; 968 u_int32_t seq_offset; 969 u_int32_t index_registers[807]; /* 00CCh */ 970 } mrsas_reg_set; 971 972 #pragma pack() 973 974 /******************************************************************* 975 * Firmware Interface Defines 976 ******************************************************************* 977 * MFI stands for MegaRAID SAS FW Interface. This is just a moniker 978 * for protocol between the software and firmware. Commands are 979 * issued using "message frames". 980 ******************************************************************/ 981 /* 982 * FW posts its state in upper 4 bits of outbound_msg_0 register 983 */ 984 #define MFI_STATE_MASK 0xF0000000 985 #define MFI_STATE_UNDEFINED 0x00000000 986 #define MFI_STATE_BB_INIT 0x10000000 987 #define MFI_STATE_FW_INIT 0x40000000 988 #define MFI_STATE_WAIT_HANDSHAKE 0x60000000 989 #define MFI_STATE_FW_INIT_2 0x70000000 990 #define MFI_STATE_DEVICE_SCAN 0x80000000 991 #define MFI_STATE_BOOT_MESSAGE_PENDING 0x90000000 992 #define MFI_STATE_FLUSH_CACHE 0xA0000000 993 #define MFI_STATE_READY 0xB0000000 994 #define MFI_STATE_OPERATIONAL 0xC0000000 995 #define MFI_STATE_FAULT 0xF0000000 996 #define MFI_RESET_REQUIRED 0x00000001 997 #define MFI_RESET_ADAPTER 0x00000002 998 #define MEGAMFI_FRAME_SIZE 64 999 #define MRSAS_MFI_FRAME_SIZE 1024 1000 #define MRSAS_MFI_SENSE_SIZE 128 1001 1002 /* 1003 * During FW init, clear pending cmds & reset state using inbound_msg_0 1004 * 1005 * ABORT : Abort all pending cmds READY : Move from OPERATIONAL to 1006 * READY state; discard queue info MFIMODE : Discard (possible) low MFA 1007 * posted in 64-bit mode (??) CLR_HANDSHAKE: FW is waiting for HANDSHAKE from 1008 * BIOS or Driver HOTPLUG : Resume from Hotplug MFI_STOP_ADP : Send 1009 * signal to FW to stop processing 1010 */ 1011 1012 #define WRITE_SEQUENCE_OFFSET (0x0000000FC) 1013 #define HOST_DIAGNOSTIC_OFFSET (0x000000F8) 1014 #define DIAG_WRITE_ENABLE (0x00000080) 1015 #define DIAG_RESET_ADAPTER (0x00000004) 1016 1017 #define MFI_ADP_RESET 0x00000040 1018 #define MFI_INIT_ABORT 0x00000001 1019 #define MFI_INIT_READY 0x00000002 1020 #define MFI_INIT_MFIMODE 0x00000004 1021 #define MFI_INIT_CLEAR_HANDSHAKE 0x00000008 1022 #define MFI_INIT_HOTPLUG 0x00000010 1023 #define MFI_STOP_ADP 0x00000020 1024 #define MFI_RESET_FLAGS MFI_INIT_READY| \ 1025 MFI_INIT_MFIMODE| \ 1026 MFI_INIT_ABORT 1027 1028 /* 1029 * MFI frame flags 1030 */ 1031 #define MFI_FRAME_POST_IN_REPLY_QUEUE 0x0000 1032 #define MFI_FRAME_DONT_POST_IN_REPLY_QUEUE 0x0001 1033 #define MFI_FRAME_SGL32 0x0000 1034 #define MFI_FRAME_SGL64 0x0002 1035 #define MFI_FRAME_SENSE32 0x0000 1036 #define MFI_FRAME_SENSE64 0x0004 1037 #define MFI_FRAME_DIR_NONE 0x0000 1038 #define MFI_FRAME_DIR_WRITE 0x0008 1039 #define MFI_FRAME_DIR_READ 0x0010 1040 #define MFI_FRAME_DIR_BOTH 0x0018 1041 #define MFI_FRAME_IEEE 0x0020 1042 1043 /* 1044 * Definition for cmd_status 1045 */ 1046 #define MFI_CMD_STATUS_POLL_MODE 0xFF 1047 1048 /* 1049 * MFI command opcodes 1050 */ 1051 #define MFI_CMD_INIT 0x00 1052 #define MFI_CMD_LD_READ 0x01 1053 #define MFI_CMD_LD_WRITE 0x02 1054 #define MFI_CMD_LD_SCSI_IO 0x03 1055 #define MFI_CMD_PD_SCSI_IO 0x04 1056 #define MFI_CMD_DCMD 0x05 1057 #define MFI_CMD_ABORT 0x06 1058 #define MFI_CMD_SMP 0x07 1059 #define MFI_CMD_STP 0x08 1060 #define MFI_CMD_INVALID 0xff 1061 1062 #define MR_DCMD_CTRL_GET_INFO 0x01010000 1063 #define MR_DCMD_LD_GET_LIST 0x03010000 1064 #define MR_DCMD_CTRL_CACHE_FLUSH 0x01101000 1065 #define MR_FLUSH_CTRL_CACHE 0x01 1066 #define MR_FLUSH_DISK_CACHE 0x02 1067 1068 #define MR_DCMD_CTRL_SHUTDOWN 0x01050000 1069 #define MR_DCMD_HIBERNATE_SHUTDOWN 0x01060000 1070 #define MR_ENABLE_DRIVE_SPINDOWN 0x01 1071 1072 #define MR_DCMD_CTRL_EVENT_GET_INFO 0x01040100 1073 #define MR_DCMD_CTRL_EVENT_GET 0x01040300 1074 #define MR_DCMD_CTRL_EVENT_WAIT 0x01040500 1075 #define MR_DCMD_LD_GET_PROPERTIES 0x03030000 1076 1077 #define MR_DCMD_CLUSTER 0x08000000 1078 #define MR_DCMD_CLUSTER_RESET_ALL 0x08010100 1079 #define MR_DCMD_CLUSTER_RESET_LD 0x08010200 1080 #define MR_DCMD_PD_LIST_QUERY 0x02010100 1081 1082 #define MR_DCMD_CTRL_MISC_CPX 0x0100e200 1083 #define MR_DCMD_CTRL_MISC_CPX_INIT_DATA_GET 0x0100e201 1084 #define MR_DCMD_CTRL_MISC_CPX_QUEUE_DATA 0x0100e202 1085 #define MR_DCMD_CTRL_MISC_CPX_UNREGISTER 0x0100e203 1086 #define MAX_MR_ROW_SIZE 32 1087 #define MR_CPX_DIR_WRITE 1 1088 #define MR_CPX_DIR_READ 0 1089 #define MR_CPX_VERSION 1 1090 1091 #define MR_DCMD_CTRL_IO_METRICS_GET 0x01170200 1092 1093 #define MR_EVT_CFG_CLEARED 0x0004 1094 1095 #define MR_EVT_LD_STATE_CHANGE 0x0051 1096 #define MR_EVT_PD_INSERTED 0x005b 1097 #define MR_EVT_PD_REMOVED 0x0070 1098 #define MR_EVT_LD_CREATED 0x008a 1099 #define MR_EVT_LD_DELETED 0x008b 1100 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1101 #define MR_EVT_LD_OFFLINE 0x00fc 1102 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1103 #define MR_EVT_CTRL_PERF_COLLECTION 0x017e 1104 1105 /* 1106 * MFI command completion codes 1107 */ 1108 enum MFI_STAT { 1109 MFI_STAT_OK = 0x00, 1110 MFI_STAT_INVALID_CMD = 0x01, 1111 MFI_STAT_INVALID_DCMD = 0x02, 1112 MFI_STAT_INVALID_PARAMETER = 0x03, 1113 MFI_STAT_INVALID_SEQUENCE_NUMBER = 0x04, 1114 MFI_STAT_ABORT_NOT_POSSIBLE = 0x05, 1115 MFI_STAT_APP_HOST_CODE_NOT_FOUND = 0x06, 1116 MFI_STAT_APP_IN_USE = 0x07, 1117 MFI_STAT_APP_NOT_INITIALIZED = 0x08, 1118 MFI_STAT_ARRAY_INDEX_INVALID = 0x09, 1119 MFI_STAT_ARRAY_ROW_NOT_EMPTY = 0x0a, 1120 MFI_STAT_CONFIG_RESOURCE_CONFLICT = 0x0b, 1121 MFI_STAT_DEVICE_NOT_FOUND = 0x0c, 1122 MFI_STAT_DRIVE_TOO_SMALL = 0x0d, 1123 MFI_STAT_FLASH_ALLOC_FAIL = 0x0e, 1124 MFI_STAT_FLASH_BUSY = 0x0f, 1125 MFI_STAT_FLASH_ERROR = 0x10, 1126 MFI_STAT_FLASH_IMAGE_BAD = 0x11, 1127 MFI_STAT_FLASH_IMAGE_INCOMPLETE = 0x12, 1128 MFI_STAT_FLASH_NOT_OPEN = 0x13, 1129 MFI_STAT_FLASH_NOT_STARTED = 0x14, 1130 MFI_STAT_FLUSH_FAILED = 0x15, 1131 MFI_STAT_HOST_CODE_NOT_FOUNT = 0x16, 1132 MFI_STAT_LD_CC_IN_PROGRESS = 0x17, 1133 MFI_STAT_LD_INIT_IN_PROGRESS = 0x18, 1134 MFI_STAT_LD_LBA_OUT_OF_RANGE = 0x19, 1135 MFI_STAT_LD_MAX_CONFIGURED = 0x1a, 1136 MFI_STAT_LD_NOT_OPTIMAL = 0x1b, 1137 MFI_STAT_LD_RBLD_IN_PROGRESS = 0x1c, 1138 MFI_STAT_LD_RECON_IN_PROGRESS = 0x1d, 1139 MFI_STAT_LD_WRONG_RAID_LEVEL = 0x1e, 1140 MFI_STAT_MAX_SPARES_EXCEEDED = 0x1f, 1141 MFI_STAT_MEMORY_NOT_AVAILABLE = 0x20, 1142 MFI_STAT_MFC_HW_ERROR = 0x21, 1143 MFI_STAT_NO_HW_PRESENT = 0x22, 1144 MFI_STAT_NOT_FOUND = 0x23, 1145 MFI_STAT_NOT_IN_ENCL = 0x24, 1146 MFI_STAT_PD_CLEAR_IN_PROGRESS = 0x25, 1147 MFI_STAT_PD_TYPE_WRONG = 0x26, 1148 MFI_STAT_PR_DISABLED = 0x27, 1149 MFI_STAT_ROW_INDEX_INVALID = 0x28, 1150 MFI_STAT_SAS_CONFIG_INVALID_ACTION = 0x29, 1151 MFI_STAT_SAS_CONFIG_INVALID_DATA = 0x2a, 1152 MFI_STAT_SAS_CONFIG_INVALID_PAGE = 0x2b, 1153 MFI_STAT_SAS_CONFIG_INVALID_TYPE = 0x2c, 1154 MFI_STAT_SCSI_DONE_WITH_ERROR = 0x2d, 1155 MFI_STAT_SCSI_IO_FAILED = 0x2e, 1156 MFI_STAT_SCSI_RESERVATION_CONFLICT = 0x2f, 1157 MFI_STAT_SHUTDOWN_FAILED = 0x30, 1158 MFI_STAT_TIME_NOT_SET = 0x31, 1159 MFI_STAT_WRONG_STATE = 0x32, 1160 MFI_STAT_LD_OFFLINE = 0x33, 1161 MFI_STAT_PEER_NOTIFICATION_REJECTED = 0x34, 1162 MFI_STAT_PEER_NOTIFICATION_FAILED = 0x35, 1163 MFI_STAT_RESERVATION_IN_PROGRESS = 0x36, 1164 MFI_STAT_I2C_ERRORS_DETECTED = 0x37, 1165 MFI_STAT_PCI_ERRORS_DETECTED = 0x38, 1166 MFI_STAT_CONFIG_SEQ_MISMATCH = 0x67, 1167 1168 MFI_STAT_INVALID_STATUS = 0xFF 1169 }; 1170 1171 /* 1172 * Number of mailbox bytes in DCMD message frame 1173 */ 1174 #define MFI_MBOX_SIZE 12 1175 1176 enum MR_EVT_CLASS { 1177 1178 MR_EVT_CLASS_DEBUG = -2, 1179 MR_EVT_CLASS_PROGRESS = -1, 1180 MR_EVT_CLASS_INFO = 0, 1181 MR_EVT_CLASS_WARNING = 1, 1182 MR_EVT_CLASS_CRITICAL = 2, 1183 MR_EVT_CLASS_FATAL = 3, 1184 MR_EVT_CLASS_DEAD = 4, 1185 1186 }; 1187 1188 enum MR_EVT_LOCALE { 1189 1190 MR_EVT_LOCALE_LD = 0x0001, 1191 MR_EVT_LOCALE_PD = 0x0002, 1192 MR_EVT_LOCALE_ENCL = 0x0004, 1193 MR_EVT_LOCALE_BBU = 0x0008, 1194 MR_EVT_LOCALE_SAS = 0x0010, 1195 MR_EVT_LOCALE_CTRL = 0x0020, 1196 MR_EVT_LOCALE_CONFIG = 0x0040, 1197 MR_EVT_LOCALE_CLUSTER = 0x0080, 1198 MR_EVT_LOCALE_ALL = 0xffff, 1199 1200 }; 1201 1202 enum MR_EVT_ARGS { 1203 1204 MR_EVT_ARGS_NONE, 1205 MR_EVT_ARGS_CDB_SENSE, 1206 MR_EVT_ARGS_LD, 1207 MR_EVT_ARGS_LD_COUNT, 1208 MR_EVT_ARGS_LD_LBA, 1209 MR_EVT_ARGS_LD_OWNER, 1210 MR_EVT_ARGS_LD_LBA_PD_LBA, 1211 MR_EVT_ARGS_LD_PROG, 1212 MR_EVT_ARGS_LD_STATE, 1213 MR_EVT_ARGS_LD_STRIP, 1214 MR_EVT_ARGS_PD, 1215 MR_EVT_ARGS_PD_ERR, 1216 MR_EVT_ARGS_PD_LBA, 1217 MR_EVT_ARGS_PD_LBA_LD, 1218 MR_EVT_ARGS_PD_PROG, 1219 MR_EVT_ARGS_PD_STATE, 1220 MR_EVT_ARGS_PCI, 1221 MR_EVT_ARGS_RATE, 1222 MR_EVT_ARGS_STR, 1223 MR_EVT_ARGS_TIME, 1224 MR_EVT_ARGS_ECC, 1225 MR_EVT_ARGS_LD_PROP, 1226 MR_EVT_ARGS_PD_SPARE, 1227 MR_EVT_ARGS_PD_INDEX, 1228 MR_EVT_ARGS_DIAG_PASS, 1229 MR_EVT_ARGS_DIAG_FAIL, 1230 MR_EVT_ARGS_PD_LBA_LBA, 1231 MR_EVT_ARGS_PORT_PHY, 1232 MR_EVT_ARGS_PD_MISSING, 1233 MR_EVT_ARGS_PD_ADDRESS, 1234 MR_EVT_ARGS_BITMAP, 1235 MR_EVT_ARGS_CONNECTOR, 1236 MR_EVT_ARGS_PD_PD, 1237 MR_EVT_ARGS_PD_FRU, 1238 MR_EVT_ARGS_PD_PATHINFO, 1239 MR_EVT_ARGS_PD_POWER_STATE, 1240 MR_EVT_ARGS_GENERIC, 1241 }; 1242 1243 1244 /* 1245 * Thunderbolt (and later) Defines 1246 */ 1247 #define MEGASAS_CHAIN_FRAME_SZ_MIN 1024 1248 #define MFI_FUSION_ENABLE_INTERRUPT_MASK (0x00000009) 1249 #define MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE 256 1250 #define MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST 0xF0 1251 #define MRSAS_MPI2_FUNCTION_LD_IO_REQUEST 0xF1 1252 #define MRSAS_LOAD_BALANCE_FLAG 0x1 1253 #define MRSAS_DCMD_MBOX_PEND_FLAG 0x1 1254 #define HOST_DIAG_WRITE_ENABLE 0x80 1255 #define HOST_DIAG_RESET_ADAPTER 0x4 1256 #define MRSAS_TBOLT_MAX_RESET_TRIES 3 1257 #define MRSAS_MAX_MFI_CMDS 32 1258 1259 /* 1260 * Invader Defines 1261 */ 1262 #define MPI2_TYPE_CUDA 0x2 1263 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH 0x4000 1264 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU0 0x00 1265 #define MR_RL_FLAGS_GRANT_DESTINATION_CPU1 0x10 1266 #define MR_RL_FLAGS_GRANT_DESTINATION_CUDA 0x80 1267 #define MR_RL_FLAGS_SEQ_NUM_ENABLE 0x8 1268 1269 /* 1270 * T10 PI defines 1271 */ 1272 #define MR_PROT_INFO_TYPE_CONTROLLER 0x8 1273 #define MRSAS_SCSI_VARIABLE_LENGTH_CMD 0x7f 1274 #define MRSAS_SCSI_SERVICE_ACTION_READ32 0x9 1275 #define MRSAS_SCSI_SERVICE_ACTION_WRITE32 0xB 1276 #define MRSAS_SCSI_ADDL_CDB_LEN 0x18 1277 #define MRSAS_RD_WR_PROTECT_CHECK_ALL 0x20 1278 #define MRSAS_RD_WR_PROTECT_CHECK_NONE 0x60 1279 #define MRSAS_SCSIBLOCKSIZE 512 1280 1281 /* 1282 * Raid context flags 1283 */ 1284 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4 1285 #define MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30 1286 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE { 1287 MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0, 1288 MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1, 1289 } MR_RAID_FLAGS_IO_SUB_TYPE; 1290 1291 /* 1292 * Request descriptor types 1293 */ 1294 #define MRSAS_REQ_DESCRIPT_FLAGS_LD_IO 0x7 1295 #define MRSAS_REQ_DESCRIPT_FLAGS_MFA 0x1 1296 #define MRSAS_REQ_DESCRIPT_FLAGS_NO_LOCK 0x2 1297 #define MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT 1 1298 #define MRSAS_FP_CMD_LEN 16 1299 #define MRSAS_FUSION_IN_RESET 0 1300 1301 #define RAID_CTX_SPANARM_ARM_SHIFT (0) 1302 #define RAID_CTX_SPANARM_ARM_MASK (0x1f) 1303 #define RAID_CTX_SPANARM_SPAN_SHIFT (5) 1304 #define RAID_CTX_SPANARM_SPAN_MASK (0xE0) 1305 1306 /* 1307 * Define region lock types 1308 */ 1309 typedef enum _REGION_TYPE { 1310 REGION_TYPE_UNUSED = 0, 1311 REGION_TYPE_SHARED_READ = 1, 1312 REGION_TYPE_SHARED_WRITE = 2, 1313 REGION_TYPE_EXCLUSIVE = 3, 1314 } REGION_TYPE; 1315 1316 1317 /* 1318 * SCSI-CAM Related Defines 1319 */ 1320 #define MRSAS_SCSI_MAX_LUNS 0 1321 #define MRSAS_SCSI_INITIATOR_ID 255 1322 #define MRSAS_SCSI_MAX_CMDS 8 1323 #define MRSAS_SCSI_MAX_CDB_LEN 16 1324 #define MRSAS_SCSI_SENSE_BUFFERSIZE 96 1325 #define MRSAS_INTERNAL_CMDS 32 1326 1327 #define MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK 0x400000 1328 #define MEGASAS_MAX_CHAIN_SIZE_MASK 0x3E0 1329 #define MEGASAS_256K_IO 128 1330 #define MEGASAS_1MB_IO (MEGASAS_256K_IO * 4) 1331 1332 /* Request types */ 1333 #define MRSAS_REQ_TYPE_INTERNAL_CMD 0x0 1334 #define MRSAS_REQ_TYPE_AEN_FETCH 0x1 1335 #define MRSAS_REQ_TYPE_PASSTHRU 0x2 1336 #define MRSAS_REQ_TYPE_GETSET_PARAM 0x3 1337 #define MRSAS_REQ_TYPE_SCSI_IO 0x4 1338 1339 /* Request states */ 1340 #define MRSAS_REQ_STATE_FREE 0 1341 #define MRSAS_REQ_STATE_BUSY 1 1342 #define MRSAS_REQ_STATE_TRAN 2 1343 #define MRSAS_REQ_STATE_COMPLETE 3 1344 1345 typedef enum _MR_SCSI_CMD_TYPE { 1346 READ_WRITE_LDIO = 0, 1347 NON_READ_WRITE_LDIO = 1, 1348 READ_WRITE_SYSPDIO = 2, 1349 NON_READ_WRITE_SYSPDIO = 3, 1350 } MR_SCSI_CMD_TYPE; 1351 1352 enum mrsas_req_flags { 1353 MRSAS_DIR_UNKNOWN = 0x1, 1354 MRSAS_DIR_IN = 0x2, 1355 MRSAS_DIR_OUT = 0x4, 1356 MRSAS_DIR_NONE = 0x8, 1357 }; 1358 1359 /* 1360 * Adapter Reset States 1361 */ 1362 enum { 1363 MRSAS_HBA_OPERATIONAL = 0, 1364 MRSAS_ADPRESET_SM_INFAULT = 1, 1365 MRSAS_ADPRESET_SM_FW_RESET_SUCCESS = 2, 1366 MRSAS_ADPRESET_SM_OPERATIONAL = 3, 1367 MRSAS_HW_CRITICAL_ERROR = 4, 1368 MRSAS_ADPRESET_INPROG_SIGN = 0xDEADDEAD, 1369 }; 1370 1371 /* 1372 * MPT Command Structure 1373 */ 1374 struct mrsas_mpt_cmd { 1375 MRSAS_RAID_SCSI_IO_REQUEST *io_request; 1376 bus_addr_t io_request_phys_addr; 1377 MPI2_SGE_IO_UNION *chain_frame; 1378 bus_addr_t chain_frame_phys_addr; 1379 u_int32_t sge_count; 1380 u_int8_t *sense; 1381 bus_addr_t sense_phys_addr; 1382 u_int8_t retry_for_fw_reset; 1383 MRSAS_REQUEST_DESCRIPTOR_UNION *request_desc; 1384 u_int32_t sync_cmd_idx; 1385 u_int32_t index; 1386 u_int8_t flags; 1387 u_int8_t pd_r1_lb; 1388 u_int8_t load_balance; 1389 bus_size_t length; 1390 u_int32_t error_code; 1391 bus_dmamap_t data_dmamap; 1392 void *data; 1393 union ccb *ccb_ptr; 1394 struct callout cm_callout; 1395 struct mrsas_softc *sc; 1396 TAILQ_ENTRY(mrsas_mpt_cmd) next; 1397 }; 1398 1399 /* 1400 * MFI Command Structure 1401 */ 1402 struct mrsas_mfi_cmd { 1403 union mrsas_frame *frame; 1404 bus_dmamap_t frame_dmamap; 1405 void *frame_mem; 1406 bus_addr_t frame_phys_addr; 1407 u_int8_t *sense; 1408 bus_dmamap_t sense_dmamap; 1409 void *sense_mem; 1410 bus_addr_t sense_phys_addr; 1411 u_int32_t index; 1412 u_int8_t sync_cmd; 1413 u_int8_t cmd_status; 1414 u_int8_t abort_aen; 1415 u_int8_t retry_for_fw_reset; 1416 struct mrsas_softc *sc; 1417 union ccb *ccb_ptr; 1418 union { 1419 struct { 1420 u_int16_t smid; 1421 u_int16_t resvd; 1422 } context; 1423 u_int32_t frame_count; 1424 } cmd_id; 1425 TAILQ_ENTRY(mrsas_mfi_cmd) next; 1426 }; 1427 1428 1429 /* 1430 * define constants for device list query options 1431 */ 1432 enum MR_PD_QUERY_TYPE { 1433 MR_PD_QUERY_TYPE_ALL = 0, 1434 MR_PD_QUERY_TYPE_STATE = 1, 1435 MR_PD_QUERY_TYPE_POWER_STATE = 2, 1436 MR_PD_QUERY_TYPE_MEDIA_TYPE = 3, 1437 MR_PD_QUERY_TYPE_SPEED = 4, 1438 MR_PD_QUERY_TYPE_EXPOSED_TO_HOST = 5, 1439 }; 1440 1441 #define MR_EVT_CFG_CLEARED 0x0004 1442 #define MR_EVT_LD_STATE_CHANGE 0x0051 1443 #define MR_EVT_PD_INSERTED 0x005b 1444 #define MR_EVT_PD_REMOVED 0x0070 1445 #define MR_EVT_LD_CREATED 0x008a 1446 #define MR_EVT_LD_DELETED 0x008b 1447 #define MR_EVT_FOREIGN_CFG_IMPORTED 0x00db 1448 #define MR_EVT_LD_OFFLINE 0x00fc 1449 #define MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED 0x0152 1450 1451 enum MR_PD_STATE { 1452 MR_PD_STATE_UNCONFIGURED_GOOD = 0x00, 1453 MR_PD_STATE_UNCONFIGURED_BAD = 0x01, 1454 MR_PD_STATE_HOT_SPARE = 0x02, 1455 MR_PD_STATE_OFFLINE = 0x10, 1456 MR_PD_STATE_FAILED = 0x11, 1457 MR_PD_STATE_REBUILD = 0x14, 1458 MR_PD_STATE_ONLINE = 0x18, 1459 MR_PD_STATE_COPYBACK = 0x20, 1460 MR_PD_STATE_SYSTEM = 0x40, 1461 }; 1462 1463 /* 1464 * defines the physical drive address structure 1465 */ 1466 #pragma pack(1) 1467 struct MR_PD_ADDRESS { 1468 u_int16_t deviceId; 1469 u_int16_t enclDeviceId; 1470 1471 union { 1472 struct { 1473 u_int8_t enclIndex; 1474 u_int8_t slotNumber; 1475 } mrPdAddress; 1476 struct { 1477 u_int8_t enclPosition; 1478 u_int8_t enclConnectorIndex; 1479 } mrEnclAddress; 1480 } u1; 1481 u_int8_t scsiDevType; 1482 union { 1483 u_int8_t connectedPortBitmap; 1484 u_int8_t connectedPortNumbers; 1485 } u2; 1486 u_int64_t sasAddr[2]; 1487 }; 1488 1489 #pragma pack() 1490 1491 /* 1492 * defines the physical drive list structure 1493 */ 1494 #pragma pack(1) 1495 struct MR_PD_LIST { 1496 u_int32_t size; 1497 u_int32_t count; 1498 struct MR_PD_ADDRESS addr[1]; 1499 }; 1500 1501 #pragma pack() 1502 1503 #pragma pack(1) 1504 struct mrsas_pd_list { 1505 u_int16_t tid; 1506 u_int8_t driveType; 1507 u_int8_t driveState; 1508 }; 1509 1510 #pragma pack() 1511 1512 /* 1513 * defines the logical drive reference structure 1514 */ 1515 typedef union _MR_LD_REF { 1516 struct { 1517 u_int8_t targetId; 1518 u_int8_t reserved; 1519 u_int16_t seqNum; 1520 } ld_context; 1521 u_int32_t ref; 1522 } MR_LD_REF; 1523 1524 1525 /* 1526 * defines the logical drive list structure 1527 */ 1528 #pragma pack(1) 1529 struct MR_LD_LIST { 1530 u_int32_t ldCount; 1531 u_int32_t reserved; 1532 struct { 1533 MR_LD_REF ref; 1534 u_int8_t state; 1535 u_int8_t reserved[3]; 1536 u_int64_t size; 1537 } ldList[MAX_LOGICAL_DRIVES_EXT]; 1538 }; 1539 1540 #pragma pack() 1541 1542 /* 1543 * SAS controller properties 1544 */ 1545 #pragma pack(1) 1546 struct mrsas_ctrl_prop { 1547 u_int16_t seq_num; 1548 u_int16_t pred_fail_poll_interval; 1549 u_int16_t intr_throttle_count; 1550 u_int16_t intr_throttle_timeouts; 1551 u_int8_t rebuild_rate; 1552 u_int8_t patrol_read_rate; 1553 u_int8_t bgi_rate; 1554 u_int8_t cc_rate; 1555 u_int8_t recon_rate; 1556 u_int8_t cache_flush_interval; 1557 u_int8_t spinup_drv_count; 1558 u_int8_t spinup_delay; 1559 u_int8_t cluster_enable; 1560 u_int8_t coercion_mode; 1561 u_int8_t alarm_enable; 1562 u_int8_t disable_auto_rebuild; 1563 u_int8_t disable_battery_warn; 1564 u_int8_t ecc_bucket_size; 1565 u_int16_t ecc_bucket_leak_rate; 1566 u_int8_t restore_hotspare_on_insertion; 1567 u_int8_t expose_encl_devices; 1568 u_int8_t maintainPdFailHistory; 1569 u_int8_t disallowHostRequestReordering; 1570 u_int8_t abortCCOnError; 1571 u_int8_t loadBalanceMode; 1572 u_int8_t disableAutoDetectBackplane; 1573 u_int8_t snapVDSpace; 1574 /* 1575 * Add properties that can be controlled by a bit in the following 1576 * structure. 1577 */ 1578 struct { 1579 u_int32_t copyBackDisabled:1; 1580 u_int32_t SMARTerEnabled:1; 1581 u_int32_t prCorrectUnconfiguredAreas:1; 1582 u_int32_t useFdeOnly:1; 1583 u_int32_t disableNCQ:1; 1584 u_int32_t SSDSMARTerEnabled:1; 1585 u_int32_t SSDPatrolReadEnabled:1; 1586 u_int32_t enableSpinDownUnconfigured:1; 1587 u_int32_t autoEnhancedImport:1; 1588 u_int32_t enableSecretKeyControl:1; 1589 u_int32_t disableOnlineCtrlReset:1; 1590 u_int32_t allowBootWithPinnedCache:1; 1591 u_int32_t disableSpinDownHS:1; 1592 u_int32_t enableJBOD:1; 1593 u_int32_t disableCacheBypass:1; 1594 u_int32_t useDiskActivityForLocate:1; 1595 u_int32_t enablePI:1; 1596 u_int32_t preventPIImport:1; 1597 u_int32_t useGlobalSparesForEmergency:1; 1598 u_int32_t useUnconfGoodForEmergency:1; 1599 u_int32_t useEmergencySparesforSMARTer:1; 1600 u_int32_t forceSGPIOForQuadOnly:1; 1601 u_int32_t enableConfigAutoBalance:1; 1602 u_int32_t enableVirtualCache:1; 1603 u_int32_t enableAutoLockRecovery:1; 1604 u_int32_t disableImmediateIO:1; 1605 u_int32_t disableT10RebuildAssist:1; 1606 u_int32_t ignore64ldRestriction:1; 1607 u_int32_t enableSwZone:1; 1608 u_int32_t limitMaxRateSATA3G:1; 1609 u_int32_t reserved:2; 1610 } OnOffProperties; 1611 u_int8_t autoSnapVDSpace; 1612 u_int8_t viewSpace; 1613 u_int16_t spinDownTime; 1614 u_int8_t reserved[24]; 1615 1616 }; 1617 1618 #pragma pack() 1619 1620 1621 /* 1622 * SAS controller information 1623 */ 1624 struct mrsas_ctrl_info { 1625 /* 1626 * PCI device information 1627 */ 1628 struct { 1629 u_int16_t vendor_id; 1630 u_int16_t device_id; 1631 u_int16_t sub_vendor_id; 1632 u_int16_t sub_device_id; 1633 u_int8_t reserved[24]; 1634 } __packed pci; 1635 /* 1636 * Host interface information 1637 */ 1638 struct { 1639 u_int8_t PCIX:1; 1640 u_int8_t PCIE:1; 1641 u_int8_t iSCSI:1; 1642 u_int8_t SAS_3G:1; 1643 u_int8_t reserved_0:4; 1644 u_int8_t reserved_1[6]; 1645 u_int8_t port_count; 1646 u_int64_t port_addr[8]; 1647 } __packed host_interface; 1648 /* 1649 * Device (backend) interface information 1650 */ 1651 struct { 1652 u_int8_t SPI:1; 1653 u_int8_t SAS_3G:1; 1654 u_int8_t SATA_1_5G:1; 1655 u_int8_t SATA_3G:1; 1656 u_int8_t reserved_0:4; 1657 u_int8_t reserved_1[6]; 1658 u_int8_t port_count; 1659 u_int64_t port_addr[8]; 1660 } __packed device_interface; 1661 1662 u_int32_t image_check_word; 1663 u_int32_t image_component_count; 1664 1665 struct { 1666 char name[8]; 1667 char version[32]; 1668 char build_date[16]; 1669 char built_time[16]; 1670 } __packed image_component[8]; 1671 1672 u_int32_t pending_image_component_count; 1673 1674 struct { 1675 char name[8]; 1676 char version[32]; 1677 char build_date[16]; 1678 char build_time[16]; 1679 } __packed pending_image_component[8]; 1680 1681 u_int8_t max_arms; 1682 u_int8_t max_spans; 1683 u_int8_t max_arrays; 1684 u_int8_t max_lds; 1685 char product_name[80]; 1686 char serial_no[32]; 1687 1688 /* 1689 * Other physical/controller/operation information. Indicates the 1690 * presence of the hardware 1691 */ 1692 struct { 1693 u_int32_t bbu:1; 1694 u_int32_t alarm:1; 1695 u_int32_t nvram:1; 1696 u_int32_t uart:1; 1697 u_int32_t reserved:28; 1698 } __packed hw_present; 1699 1700 u_int32_t current_fw_time; 1701 1702 /* 1703 * Maximum data transfer sizes 1704 */ 1705 u_int16_t max_concurrent_cmds; 1706 u_int16_t max_sge_count; 1707 u_int32_t max_request_size; 1708 1709 /* 1710 * Logical and physical device counts 1711 */ 1712 u_int16_t ld_present_count; 1713 u_int16_t ld_degraded_count; 1714 u_int16_t ld_offline_count; 1715 1716 u_int16_t pd_present_count; 1717 u_int16_t pd_disk_present_count; 1718 u_int16_t pd_disk_pred_failure_count; 1719 u_int16_t pd_disk_failed_count; 1720 1721 /* 1722 * Memory size information 1723 */ 1724 u_int16_t nvram_size; 1725 u_int16_t memory_size; 1726 u_int16_t flash_size; 1727 1728 /* 1729 * Error counters 1730 */ 1731 u_int16_t mem_correctable_error_count; 1732 u_int16_t mem_uncorrectable_error_count; 1733 1734 /* 1735 * Cluster information 1736 */ 1737 u_int8_t cluster_permitted; 1738 u_int8_t cluster_active; 1739 1740 /* 1741 * Additional max data transfer sizes 1742 */ 1743 u_int16_t max_strips_per_io; 1744 1745 /* 1746 * Controller capabilities structures 1747 */ 1748 struct { 1749 u_int32_t raid_level_0:1; 1750 u_int32_t raid_level_1:1; 1751 u_int32_t raid_level_5:1; 1752 u_int32_t raid_level_1E:1; 1753 u_int32_t raid_level_6:1; 1754 u_int32_t reserved:27; 1755 } __packed raid_levels; 1756 1757 struct { 1758 u_int32_t rbld_rate:1; 1759 u_int32_t cc_rate:1; 1760 u_int32_t bgi_rate:1; 1761 u_int32_t recon_rate:1; 1762 u_int32_t patrol_rate:1; 1763 u_int32_t alarm_control:1; 1764 u_int32_t cluster_supported:1; 1765 u_int32_t bbu:1; 1766 u_int32_t spanning_allowed:1; 1767 u_int32_t dedicated_hotspares:1; 1768 u_int32_t revertible_hotspares:1; 1769 u_int32_t foreign_config_import:1; 1770 u_int32_t self_diagnostic:1; 1771 u_int32_t mixed_redundancy_arr:1; 1772 u_int32_t global_hot_spares:1; 1773 u_int32_t reserved:17; 1774 } __packed adapter_operations; 1775 1776 struct { 1777 u_int32_t read_policy:1; 1778 u_int32_t write_policy:1; 1779 u_int32_t io_policy:1; 1780 u_int32_t access_policy:1; 1781 u_int32_t disk_cache_policy:1; 1782 u_int32_t reserved:27; 1783 } __packed ld_operations; 1784 1785 struct { 1786 u_int8_t min; 1787 u_int8_t max; 1788 u_int8_t reserved[2]; 1789 } __packed stripe_sz_ops; 1790 1791 struct { 1792 u_int32_t force_online:1; 1793 u_int32_t force_offline:1; 1794 u_int32_t force_rebuild:1; 1795 u_int32_t reserved:29; 1796 } __packed pd_operations; 1797 1798 struct { 1799 u_int32_t ctrl_supports_sas:1; 1800 u_int32_t ctrl_supports_sata:1; 1801 u_int32_t allow_mix_in_encl:1; 1802 u_int32_t allow_mix_in_ld:1; 1803 u_int32_t allow_sata_in_cluster:1; 1804 u_int32_t reserved:27; 1805 } __packed pd_mix_support; 1806 1807 /* 1808 * Define ECC single-bit-error bucket information 1809 */ 1810 u_int8_t ecc_bucket_count; 1811 u_int8_t reserved_2[11]; 1812 1813 /* 1814 * Include the controller properties (changeable items) 1815 */ 1816 struct mrsas_ctrl_prop properties; 1817 1818 /* 1819 * Define FW pkg version (set in envt v'bles on OEM basis) 1820 */ 1821 char package_version[0x60]; 1822 1823 u_int64_t deviceInterfacePortAddr2[8]; 1824 u_int8_t reserved3[128]; 1825 1826 struct { 1827 u_int16_t minPdRaidLevel_0:4; 1828 u_int16_t maxPdRaidLevel_0:12; 1829 1830 u_int16_t minPdRaidLevel_1:4; 1831 u_int16_t maxPdRaidLevel_1:12; 1832 1833 u_int16_t minPdRaidLevel_5:4; 1834 u_int16_t maxPdRaidLevel_5:12; 1835 1836 u_int16_t minPdRaidLevel_1E:4; 1837 u_int16_t maxPdRaidLevel_1E:12; 1838 1839 u_int16_t minPdRaidLevel_6:4; 1840 u_int16_t maxPdRaidLevel_6:12; 1841 1842 u_int16_t minPdRaidLevel_10:4; 1843 u_int16_t maxPdRaidLevel_10:12; 1844 1845 u_int16_t minPdRaidLevel_50:4; 1846 u_int16_t maxPdRaidLevel_50:12; 1847 1848 u_int16_t minPdRaidLevel_60:4; 1849 u_int16_t maxPdRaidLevel_60:12; 1850 1851 u_int16_t minPdRaidLevel_1E_RLQ0:4; 1852 u_int16_t maxPdRaidLevel_1E_RLQ0:12; 1853 1854 u_int16_t minPdRaidLevel_1E0_RLQ0:4; 1855 u_int16_t maxPdRaidLevel_1E0_RLQ0:12; 1856 1857 u_int16_t reserved[6]; 1858 } pdsForRaidLevels; 1859 1860 u_int16_t maxPds; /* 0x780 */ 1861 u_int16_t maxDedHSPs; /* 0x782 */ 1862 u_int16_t maxGlobalHSPs; /* 0x784 */ 1863 u_int16_t ddfSize; /* 0x786 */ 1864 u_int8_t maxLdsPerArray; /* 0x788 */ 1865 u_int8_t partitionsInDDF; /* 0x789 */ 1866 u_int8_t lockKeyBinding; /* 0x78a */ 1867 u_int8_t maxPITsPerLd; /* 0x78b */ 1868 u_int8_t maxViewsPerLd; /* 0x78c */ 1869 u_int8_t maxTargetId; /* 0x78d */ 1870 u_int16_t maxBvlVdSize; /* 0x78e */ 1871 1872 u_int16_t maxConfigurableSSCSize; /* 0x790 */ 1873 u_int16_t currentSSCsize; /* 0x792 */ 1874 1875 char expanderFwVersion[12]; /* 0x794 */ 1876 1877 u_int16_t PFKTrialTimeRemaining;/* 0x7A0 */ 1878 1879 u_int16_t cacheMemorySize; /* 0x7A2 */ 1880 1881 struct { /* 0x7A4 */ 1882 u_int32_t supportPIcontroller:1; 1883 u_int32_t supportLdPIType1:1; 1884 u_int32_t supportLdPIType2:1; 1885 u_int32_t supportLdPIType3:1; 1886 u_int32_t supportLdBBMInfo:1; 1887 u_int32_t supportShieldState:1; 1888 u_int32_t blockSSDWriteCacheChange:1; 1889 u_int32_t supportSuspendResumeBGops:1; 1890 u_int32_t supportEmergencySpares:1; 1891 u_int32_t supportSetLinkSpeed:1; 1892 u_int32_t supportBootTimePFKChange:1; 1893 u_int32_t supportJBOD:1; 1894 u_int32_t disableOnlinePFKChange:1; 1895 u_int32_t supportPerfTuning:1; 1896 u_int32_t supportSSDPatrolRead:1; 1897 u_int32_t realTimeScheduler:1; 1898 1899 u_int32_t supportResetNow:1; 1900 u_int32_t supportEmulatedDrives:1; 1901 u_int32_t headlessMode:1; 1902 u_int32_t dedicatedHotSparesLimited:1; 1903 1904 1905 u_int32_t supportUnevenSpans:1; 1906 u_int32_t reserved:11; 1907 } adapterOperations2; 1908 1909 u_int8_t driverVersion[32]; /* 0x7A8 */ 1910 u_int8_t maxDAPdCountSpinup60; /* 0x7C8 */ 1911 u_int8_t temperatureROC; /* 0x7C9 */ 1912 u_int8_t temperatureCtrl; /* 0x7CA */ 1913 u_int8_t reserved4; /* 0x7CB */ 1914 u_int16_t maxConfigurablePds; /* 0x7CC */ 1915 1916 1917 u_int8_t reserved5[2]; /* 0x7CD reserved */ 1918 1919 struct { 1920 u_int32_t peerIsPresent:1; 1921 u_int32_t peerIsIncompatible:1; 1922 1923 u_int32_t hwIncompatible:1; 1924 u_int32_t fwVersionMismatch:1; 1925 u_int32_t ctrlPropIncompatible:1; 1926 u_int32_t premiumFeatureMismatch:1; 1927 u_int32_t reserved:26; 1928 } cluster; 1929 1930 char clusterId[16]; /* 0x7D4 */ 1931 1932 char reserved6[4]; /* 0x7E4 RESERVED FOR IOV */ 1933 1934 struct { /* 0x7E8 */ 1935 u_int32_t supportPersonalityChange:2; 1936 u_int32_t supportThermalPollInterval:1; 1937 u_int32_t supportDisableImmediateIO:1; 1938 u_int32_t supportT10RebuildAssist:1; 1939 u_int32_t supportMaxExtLDs:1; 1940 u_int32_t supportCrashDump:1; 1941 u_int32_t supportSwZone:1; 1942 u_int32_t supportDebugQueue:1; 1943 u_int32_t supportNVCacheErase:1; 1944 u_int32_t supportForceTo512e:1; 1945 u_int32_t supportHOQRebuild:1; 1946 u_int32_t supportAllowedOpsforDrvRemoval:1; 1947 u_int32_t supportDrvActivityLEDSetting:1; 1948 u_int32_t supportNVDRAM:1; 1949 u_int32_t supportForceFlash:1; 1950 u_int32_t supportDisableSESMonitoring:1; 1951 u_int32_t supportCacheBypassModes:1; 1952 u_int32_t supportSecurityonJBOD:1; 1953 u_int32_t discardCacheDuringLDDelete:1; 1954 u_int32_t supportTTYLogCompression:1; 1955 u_int32_t supportCPLDUpdate:1; 1956 u_int32_t supportDiskCacheSettingForSysPDs:1; 1957 u_int32_t supportExtendedSSCSize:1; 1958 u_int32_t useSeqNumJbodFP:1; 1959 u_int32_t reserved:7; 1960 } adapterOperations3; 1961 1962 u_int8_t pad[0x800 - 0x7EC]; /* 0x7EC */ 1963 } __packed; 1964 1965 /* 1966 * When SCSI mid-layer calls driver's reset routine, driver waits for 1967 * MRSAS_RESET_WAIT_TIME seconds for all outstanding IO to complete. Note 1968 * that the driver cannot _actually_ abort or reset pending commands. While 1969 * it is waiting for the commands to complete, it prints a diagnostic message 1970 * every MRSAS_RESET_NOTICE_INTERVAL seconds 1971 */ 1972 #define MRSAS_RESET_WAIT_TIME 180 1973 #define MRSAS_INTERNAL_CMD_WAIT_TIME 180 1974 #define MRSAS_IOC_INIT_WAIT_TIME 60 1975 #define MRSAS_RESET_NOTICE_INTERVAL 5 1976 #define MRSAS_IOCTL_CMD 0 1977 #define MRSAS_DEFAULT_CMD_TIMEOUT 90 1978 #define MRSAS_THROTTLE_QUEUE_DEPTH 16 1979 1980 /* 1981 * MSI-x regsiters offset defines 1982 */ 1983 #define MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) 1984 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 1985 #define MR_MAX_REPLY_QUEUES_OFFSET (0x0000001F) 1986 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET (0x003FC000) 1987 #define MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT 14 1988 #define MR_MAX_MSIX_REG_ARRAY 16 1989 1990 /* 1991 * FW reports the maximum of number of commands that it can accept (maximum 1992 * commands that can be outstanding) at any time. The driver must report a 1993 * lower number to the mid layer because it can issue a few internal commands 1994 * itself (E.g, AEN, abort cmd, IOCTLs etc). The number of commands it needs 1995 * is shown below 1996 */ 1997 #define MRSAS_INT_CMDS 32 1998 #define MRSAS_SKINNY_INT_CMDS 5 1999 #define MRSAS_MAX_MSIX_QUEUES 128 2000 2001 /* 2002 * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit SGLs 2003 * based on the size of bus_addr_t 2004 */ 2005 #define IS_DMA64 (sizeof(bus_addr_t) == 8) 2006 2007 #define MFI_XSCALE_OMR0_CHANGE_INTERRUPT 0x00000001 2008 #define MFI_INTR_FLAG_REPLY_MESSAGE 0x00000001 2009 #define MFI_INTR_FLAG_FIRMWARE_STATE_CHANGE 0x00000002 2010 #define MFI_G2_OUTBOUND_DOORBELL_CHANGE_INTERRUPT 0x00000004 2011 2012 #define MFI_OB_INTR_STATUS_MASK 0x00000002 2013 #define MFI_POLL_TIMEOUT_SECS 60 2014 2015 #define MFI_REPLY_1078_MESSAGE_INTERRUPT 0x80000000 2016 #define MFI_REPLY_GEN2_MESSAGE_INTERRUPT 0x00000001 2017 #define MFI_GEN2_ENABLE_INTERRUPT_MASK 0x00000001 2018 #define MFI_REPLY_SKINNY_MESSAGE_INTERRUPT 0x40000000 2019 #define MFI_SKINNY_ENABLE_INTERRUPT_MASK (0x00000001) 2020 #define MFI_1068_PCSR_OFFSET 0x84 2021 #define MFI_1068_FW_HANDSHAKE_OFFSET 0x64 2022 #define MFI_1068_FW_READY 0xDDDD0000 2023 2024 typedef union _MFI_CAPABILITIES { 2025 struct { 2026 u_int32_t support_fp_remote_lun:1; 2027 u_int32_t support_additional_msix:1; 2028 u_int32_t support_fastpath_wb:1; 2029 u_int32_t support_max_255lds:1; 2030 u_int32_t support_ndrive_r1_lb:1; 2031 u_int32_t support_core_affinity:1; 2032 u_int32_t security_protocol_cmds_fw:1; 2033 u_int32_t support_ext_queue_depth:1; 2034 u_int32_t support_ext_io_size:1; 2035 u_int32_t reserved:23; 2036 } mfi_capabilities; 2037 u_int32_t reg; 2038 } MFI_CAPABILITIES; 2039 2040 #pragma pack(1) 2041 struct mrsas_sge32 { 2042 u_int32_t phys_addr; 2043 u_int32_t length; 2044 }; 2045 2046 #pragma pack() 2047 2048 #pragma pack(1) 2049 struct mrsas_sge64 { 2050 u_int64_t phys_addr; 2051 u_int32_t length; 2052 }; 2053 2054 #pragma pack() 2055 2056 #pragma pack() 2057 union mrsas_sgl { 2058 struct mrsas_sge32 sge32[1]; 2059 struct mrsas_sge64 sge64[1]; 2060 }; 2061 2062 #pragma pack() 2063 2064 #pragma pack(1) 2065 struct mrsas_header { 2066 u_int8_t cmd; /* 00e */ 2067 u_int8_t sense_len; /* 01h */ 2068 u_int8_t cmd_status; /* 02h */ 2069 u_int8_t scsi_status; /* 03h */ 2070 2071 u_int8_t target_id; /* 04h */ 2072 u_int8_t lun; /* 05h */ 2073 u_int8_t cdb_len; /* 06h */ 2074 u_int8_t sge_count; /* 07h */ 2075 2076 u_int32_t context; /* 08h */ 2077 u_int32_t pad_0; /* 0Ch */ 2078 2079 u_int16_t flags; /* 10h */ 2080 u_int16_t timeout; /* 12h */ 2081 u_int32_t data_xferlen; /* 14h */ 2082 }; 2083 2084 #pragma pack() 2085 2086 #pragma pack(1) 2087 struct mrsas_init_frame { 2088 u_int8_t cmd; /* 00h */ 2089 u_int8_t reserved_0; /* 01h */ 2090 u_int8_t cmd_status; /* 02h */ 2091 2092 u_int8_t reserved_1; /* 03h */ 2093 MFI_CAPABILITIES driver_operations; /* 04h */ 2094 u_int32_t context; /* 08h */ 2095 u_int32_t pad_0; /* 0Ch */ 2096 2097 u_int16_t flags; /* 10h */ 2098 u_int16_t reserved_3; /* 12h */ 2099 u_int32_t data_xfer_len; /* 14h */ 2100 2101 u_int32_t queue_info_new_phys_addr_lo; /* 18h */ 2102 u_int32_t queue_info_new_phys_addr_hi; /* 1Ch */ 2103 u_int32_t queue_info_old_phys_addr_lo; /* 20h */ 2104 u_int32_t queue_info_old_phys_addr_hi; /* 24h */ 2105 u_int32_t driver_ver_lo; /* 28h */ 2106 u_int32_t driver_ver_hi; /* 2Ch */ 2107 u_int32_t reserved_4[4]; /* 30h */ 2108 }; 2109 2110 #pragma pack() 2111 2112 #pragma pack(1) 2113 struct mrsas_io_frame { 2114 u_int8_t cmd; /* 00h */ 2115 u_int8_t sense_len; /* 01h */ 2116 u_int8_t cmd_status; /* 02h */ 2117 u_int8_t scsi_status; /* 03h */ 2118 2119 u_int8_t target_id; /* 04h */ 2120 u_int8_t access_byte; /* 05h */ 2121 u_int8_t reserved_0; /* 06h */ 2122 u_int8_t sge_count; /* 07h */ 2123 2124 u_int32_t context; /* 08h */ 2125 u_int32_t pad_0; /* 0Ch */ 2126 2127 u_int16_t flags; /* 10h */ 2128 u_int16_t timeout; /* 12h */ 2129 u_int32_t lba_count; /* 14h */ 2130 2131 u_int32_t sense_buf_phys_addr_lo; /* 18h */ 2132 u_int32_t sense_buf_phys_addr_hi; /* 1Ch */ 2133 2134 u_int32_t start_lba_lo; /* 20h */ 2135 u_int32_t start_lba_hi; /* 24h */ 2136 2137 union mrsas_sgl sgl; /* 28h */ 2138 }; 2139 2140 #pragma pack() 2141 2142 #pragma pack(1) 2143 struct mrsas_pthru_frame { 2144 u_int8_t cmd; /* 00h */ 2145 u_int8_t sense_len; /* 01h */ 2146 u_int8_t cmd_status; /* 02h */ 2147 u_int8_t scsi_status; /* 03h */ 2148 2149 u_int8_t target_id; /* 04h */ 2150 u_int8_t lun; /* 05h */ 2151 u_int8_t cdb_len; /* 06h */ 2152 u_int8_t sge_count; /* 07h */ 2153 2154 u_int32_t context; /* 08h */ 2155 u_int32_t pad_0; /* 0Ch */ 2156 2157 u_int16_t flags; /* 10h */ 2158 u_int16_t timeout; /* 12h */ 2159 u_int32_t data_xfer_len; /* 14h */ 2160 2161 u_int32_t sense_buf_phys_addr_lo; /* 18h */ 2162 u_int32_t sense_buf_phys_addr_hi; /* 1Ch */ 2163 2164 u_int8_t cdb[16]; /* 20h */ 2165 union mrsas_sgl sgl; /* 30h */ 2166 }; 2167 2168 #pragma pack() 2169 2170 #pragma pack(1) 2171 struct mrsas_dcmd_frame { 2172 u_int8_t cmd; /* 00h */ 2173 u_int8_t reserved_0; /* 01h */ 2174 u_int8_t cmd_status; /* 02h */ 2175 u_int8_t reserved_1[4]; /* 03h */ 2176 u_int8_t sge_count; /* 07h */ 2177 2178 u_int32_t context; /* 08h */ 2179 u_int32_t pad_0; /* 0Ch */ 2180 2181 u_int16_t flags; /* 10h */ 2182 u_int16_t timeout; /* 12h */ 2183 2184 u_int32_t data_xfer_len; /* 14h */ 2185 u_int32_t opcode; /* 18h */ 2186 2187 union { /* 1Ch */ 2188 u_int8_t b[12]; 2189 u_int16_t s[6]; 2190 u_int32_t w[3]; 2191 } mbox; 2192 2193 union mrsas_sgl sgl; /* 28h */ 2194 }; 2195 2196 #pragma pack() 2197 2198 #pragma pack(1) 2199 struct mrsas_abort_frame { 2200 u_int8_t cmd; /* 00h */ 2201 u_int8_t reserved_0; /* 01h */ 2202 u_int8_t cmd_status; /* 02h */ 2203 2204 u_int8_t reserved_1; /* 03h */ 2205 MFI_CAPABILITIES driver_operations; /* 04h */ 2206 u_int32_t context; /* 08h */ 2207 u_int32_t pad_0; /* 0Ch */ 2208 2209 u_int16_t flags; /* 10h */ 2210 u_int16_t reserved_3; /* 12h */ 2211 u_int32_t reserved_4; /* 14h */ 2212 2213 u_int32_t abort_context; /* 18h */ 2214 u_int32_t pad_1; /* 1Ch */ 2215 2216 u_int32_t abort_mfi_phys_addr_lo; /* 20h */ 2217 u_int32_t abort_mfi_phys_addr_hi; /* 24h */ 2218 2219 u_int32_t reserved_5[6]; /* 28h */ 2220 }; 2221 2222 #pragma pack() 2223 2224 #pragma pack(1) 2225 struct mrsas_smp_frame { 2226 u_int8_t cmd; /* 00h */ 2227 u_int8_t reserved_1; /* 01h */ 2228 u_int8_t cmd_status; /* 02h */ 2229 u_int8_t connection_status; /* 03h */ 2230 2231 u_int8_t reserved_2[3]; /* 04h */ 2232 u_int8_t sge_count; /* 07h */ 2233 2234 u_int32_t context; /* 08h */ 2235 u_int32_t pad_0; /* 0Ch */ 2236 2237 u_int16_t flags; /* 10h */ 2238 u_int16_t timeout; /* 12h */ 2239 2240 u_int32_t data_xfer_len; /* 14h */ 2241 u_int64_t sas_addr; /* 18h */ 2242 2243 union { 2244 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: req */ 2245 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: req */ 2246 } sgl; 2247 }; 2248 2249 #pragma pack() 2250 2251 2252 #pragma pack(1) 2253 struct mrsas_stp_frame { 2254 u_int8_t cmd; /* 00h */ 2255 u_int8_t reserved_1; /* 01h */ 2256 u_int8_t cmd_status; /* 02h */ 2257 u_int8_t reserved_2; /* 03h */ 2258 2259 u_int8_t target_id; /* 04h */ 2260 u_int8_t reserved_3[2]; /* 05h */ 2261 u_int8_t sge_count; /* 07h */ 2262 2263 u_int32_t context; /* 08h */ 2264 u_int32_t pad_0; /* 0Ch */ 2265 2266 u_int16_t flags; /* 10h */ 2267 u_int16_t timeout; /* 12h */ 2268 2269 u_int32_t data_xfer_len; /* 14h */ 2270 2271 u_int16_t fis[10]; /* 18h */ 2272 u_int32_t stp_flags; 2273 2274 union { 2275 struct mrsas_sge32 sge32[2]; /* [0]: resp [1]: data */ 2276 struct mrsas_sge64 sge64[2]; /* [0]: resp [1]: data */ 2277 } sgl; 2278 }; 2279 2280 #pragma pack() 2281 2282 union mrsas_frame { 2283 struct mrsas_header hdr; 2284 struct mrsas_init_frame init; 2285 struct mrsas_io_frame io; 2286 struct mrsas_pthru_frame pthru; 2287 struct mrsas_dcmd_frame dcmd; 2288 struct mrsas_abort_frame abort; 2289 struct mrsas_smp_frame smp; 2290 struct mrsas_stp_frame stp; 2291 u_int8_t raw_bytes[64]; 2292 }; 2293 2294 #pragma pack(1) 2295 union mrsas_evt_class_locale { 2296 2297 struct { 2298 u_int16_t locale; 2299 u_int8_t reserved; 2300 int8_t class; 2301 } __packed members; 2302 2303 u_int32_t word; 2304 2305 } __packed; 2306 2307 #pragma pack() 2308 2309 2310 #pragma pack(1) 2311 struct mrsas_evt_log_info { 2312 u_int32_t newest_seq_num; 2313 u_int32_t oldest_seq_num; 2314 u_int32_t clear_seq_num; 2315 u_int32_t shutdown_seq_num; 2316 u_int32_t boot_seq_num; 2317 2318 } __packed; 2319 2320 #pragma pack() 2321 2322 struct mrsas_progress { 2323 2324 u_int16_t progress; 2325 u_int16_t elapsed_seconds; 2326 2327 } __packed; 2328 2329 struct mrsas_evtarg_ld { 2330 2331 u_int16_t target_id; 2332 u_int8_t ld_index; 2333 u_int8_t reserved; 2334 2335 } __packed; 2336 2337 struct mrsas_evtarg_pd { 2338 u_int16_t device_id; 2339 u_int8_t encl_index; 2340 u_int8_t slot_number; 2341 2342 } __packed; 2343 2344 struct mrsas_evt_detail { 2345 2346 u_int32_t seq_num; 2347 u_int32_t time_stamp; 2348 u_int32_t code; 2349 union mrsas_evt_class_locale cl; 2350 u_int8_t arg_type; 2351 u_int8_t reserved1[15]; 2352 2353 union { 2354 struct { 2355 struct mrsas_evtarg_pd pd; 2356 u_int8_t cdb_length; 2357 u_int8_t sense_length; 2358 u_int8_t reserved[2]; 2359 u_int8_t cdb[16]; 2360 u_int8_t sense[64]; 2361 } __packed cdbSense; 2362 2363 struct mrsas_evtarg_ld ld; 2364 2365 struct { 2366 struct mrsas_evtarg_ld ld; 2367 u_int64_t count; 2368 } __packed ld_count; 2369 2370 struct { 2371 u_int64_t lba; 2372 struct mrsas_evtarg_ld ld; 2373 } __packed ld_lba; 2374 2375 struct { 2376 struct mrsas_evtarg_ld ld; 2377 u_int32_t prevOwner; 2378 u_int32_t newOwner; 2379 } __packed ld_owner; 2380 2381 struct { 2382 u_int64_t ld_lba; 2383 u_int64_t pd_lba; 2384 struct mrsas_evtarg_ld ld; 2385 struct mrsas_evtarg_pd pd; 2386 } __packed ld_lba_pd_lba; 2387 2388 struct { 2389 struct mrsas_evtarg_ld ld; 2390 struct mrsas_progress prog; 2391 } __packed ld_prog; 2392 2393 struct { 2394 struct mrsas_evtarg_ld ld; 2395 u_int32_t prev_state; 2396 u_int32_t new_state; 2397 } __packed ld_state; 2398 2399 struct { 2400 u_int64_t strip; 2401 struct mrsas_evtarg_ld ld; 2402 } __packed ld_strip; 2403 2404 struct mrsas_evtarg_pd pd; 2405 2406 struct { 2407 struct mrsas_evtarg_pd pd; 2408 u_int32_t err; 2409 } __packed pd_err; 2410 2411 struct { 2412 u_int64_t lba; 2413 struct mrsas_evtarg_pd pd; 2414 } __packed pd_lba; 2415 2416 struct { 2417 u_int64_t lba; 2418 struct mrsas_evtarg_pd pd; 2419 struct mrsas_evtarg_ld ld; 2420 } __packed pd_lba_ld; 2421 2422 struct { 2423 struct mrsas_evtarg_pd pd; 2424 struct mrsas_progress prog; 2425 } __packed pd_prog; 2426 2427 struct { 2428 struct mrsas_evtarg_pd pd; 2429 u_int32_t prevState; 2430 u_int32_t newState; 2431 } __packed pd_state; 2432 2433 struct { 2434 u_int16_t vendorId; 2435 u_int16_t deviceId; 2436 u_int16_t subVendorId; 2437 u_int16_t subDeviceId; 2438 } __packed pci; 2439 2440 u_int32_t rate; 2441 char str[96]; 2442 2443 struct { 2444 u_int32_t rtc; 2445 u_int32_t elapsedSeconds; 2446 } __packed time; 2447 2448 struct { 2449 u_int32_t ecar; 2450 u_int32_t elog; 2451 char str[64]; 2452 } __packed ecc; 2453 2454 u_int8_t b[96]; 2455 u_int16_t s[48]; 2456 u_int32_t w[24]; 2457 u_int64_t d[12]; 2458 } args; 2459 2460 char description[128]; 2461 2462 } __packed; 2463 2464 struct mrsas_irq_context { 2465 struct mrsas_softc *sc; 2466 uint32_t MSIxIndex; 2467 }; 2468 2469 enum MEGASAS_OCR_REASON { 2470 FW_FAULT_OCR = 0, 2471 SCSIIO_TIMEOUT_OCR = 1, 2472 MFI_DCMD_TIMEOUT_OCR = 2, 2473 }; 2474 2475 /* Controller management info added to support Linux Emulator */ 2476 #define MAX_MGMT_ADAPTERS 1024 2477 2478 struct mrsas_mgmt_info { 2479 u_int16_t count; 2480 struct mrsas_softc *sc_ptr[MAX_MGMT_ADAPTERS]; 2481 int max_index; 2482 }; 2483 2484 #define PCI_TYPE0_ADDRESSES 6 2485 #define PCI_TYPE1_ADDRESSES 2 2486 #define PCI_TYPE2_ADDRESSES 5 2487 2488 typedef struct _MRSAS_DRV_PCI_COMMON_HEADER { 2489 u_int16_t vendorID; 2490 //(ro) 2491 u_int16_t deviceID; 2492 //(ro) 2493 u_int16_t command; 2494 //Device control 2495 u_int16_t status; 2496 u_int8_t revisionID; 2497 //(ro) 2498 u_int8_t progIf; 2499 //(ro) 2500 u_int8_t subClass; 2501 //(ro) 2502 u_int8_t baseClass; 2503 //(ro) 2504 u_int8_t cacheLineSize; 2505 //(ro +) 2506 u_int8_t latencyTimer; 2507 //(ro +) 2508 u_int8_t headerType; 2509 //(ro) 2510 u_int8_t bist; 2511 //Built in self test 2512 2513 union { 2514 struct _MRSAS_DRV_PCI_HEADER_TYPE_0 { 2515 u_int32_t baseAddresses[PCI_TYPE0_ADDRESSES]; 2516 u_int32_t cis; 2517 u_int16_t subVendorID; 2518 u_int16_t subSystemID; 2519 u_int32_t romBaseAddress; 2520 u_int8_t capabilitiesPtr; 2521 u_int8_t reserved1[3]; 2522 u_int32_t reserved2; 2523 u_int8_t interruptLine; 2524 u_int8_t interruptPin; 2525 //(ro) 2526 u_int8_t minimumGrant; 2527 //(ro) 2528 u_int8_t maximumLatency; 2529 //(ro) 2530 } type0; 2531 2532 /* 2533 * PCI to PCI Bridge 2534 */ 2535 2536 struct _MRSAS_DRV_PCI_HEADER_TYPE_1 { 2537 u_int32_t baseAddresses[PCI_TYPE1_ADDRESSES]; 2538 u_int8_t primaryBus; 2539 u_int8_t secondaryBus; 2540 u_int8_t subordinateBus; 2541 u_int8_t secondaryLatency; 2542 u_int8_t ioBase; 2543 u_int8_t ioLimit; 2544 u_int16_t secondaryStatus; 2545 u_int16_t memoryBase; 2546 u_int16_t memoryLimit; 2547 u_int16_t prefetchBase; 2548 u_int16_t prefetchLimit; 2549 u_int32_t prefetchBaseUpper32; 2550 u_int32_t prefetchLimitUpper32; 2551 u_int16_t ioBaseUpper16; 2552 u_int16_t ioLimitUpper16; 2553 u_int8_t capabilitiesPtr; 2554 u_int8_t reserved1[3]; 2555 u_int32_t romBaseAddress; 2556 u_int8_t interruptLine; 2557 u_int8_t interruptPin; 2558 u_int16_t bridgeControl; 2559 } type1; 2560 2561 /* 2562 * PCI to CARDBUS Bridge 2563 */ 2564 2565 struct _MRSAS_DRV_PCI_HEADER_TYPE_2 { 2566 u_int32_t socketRegistersBaseAddress; 2567 u_int8_t capabilitiesPtr; 2568 u_int8_t reserved; 2569 u_int16_t secondaryStatus; 2570 u_int8_t primaryBus; 2571 u_int8_t secondaryBus; 2572 u_int8_t subordinateBus; 2573 u_int8_t secondaryLatency; 2574 struct { 2575 u_int32_t base; 2576 u_int32_t limit; 2577 } range [PCI_TYPE2_ADDRESSES - 1]; 2578 u_int8_t interruptLine; 2579 u_int8_t interruptPin; 2580 u_int16_t bridgeControl; 2581 } type2; 2582 } u; 2583 2584 } MRSAS_DRV_PCI_COMMON_HEADER, *PMRSAS_DRV_PCI_COMMON_HEADER; 2585 2586 #define MRSAS_DRV_PCI_COMMON_HEADER_SIZE sizeof(MRSAS_DRV_PCI_COMMON_HEADER) //64 bytes 2587 2588 typedef struct _MRSAS_DRV_PCI_LINK_CAPABILITY { 2589 union { 2590 struct { 2591 u_int32_t linkSpeed:4; 2592 u_int32_t linkWidth:6; 2593 u_int32_t aspmSupport:2; 2594 u_int32_t losExitLatency:3; 2595 u_int32_t l1ExitLatency:3; 2596 u_int32_t rsvdp:6; 2597 u_int32_t portNumber:8; 2598 } bits; 2599 2600 u_int32_t asUlong; 2601 } u; 2602 } MRSAS_DRV_PCI_LINK_CAPABILITY, *PMRSAS_DRV_PCI_LINK_CAPABILITY; 2603 2604 #define MRSAS_DRV_PCI_LINK_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_CAPABILITY) 2605 2606 typedef struct _MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY { 2607 union { 2608 struct { 2609 u_int16_t linkSpeed:4; 2610 u_int16_t negotiatedLinkWidth:6; 2611 u_int16_t linkTrainingError:1; 2612 u_int16_t linkTraning:1; 2613 u_int16_t slotClockConfig:1; 2614 u_int16_t rsvdZ:3; 2615 } bits; 2616 2617 u_int16_t asUshort; 2618 } u; 2619 u_int16_t reserved; 2620 } MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY, *PMRSAS_DRV_PCI_LINK_STATUS_CAPABILITY; 2621 2622 #define MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY_SIZE sizeof(MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY) 2623 2624 2625 typedef struct _MRSAS_DRV_PCI_CAPABILITIES { 2626 MRSAS_DRV_PCI_LINK_CAPABILITY linkCapability; 2627 MRSAS_DRV_PCI_LINK_STATUS_CAPABILITY linkStatusCapability; 2628 } MRSAS_DRV_PCI_CAPABILITIES, *PMRSAS_DRV_PCI_CAPABILITIES; 2629 2630 #define MRSAS_DRV_PCI_CAPABILITIES_SIZE sizeof(MRSAS_DRV_PCI_CAPABILITIES) 2631 2632 /* PCI information */ 2633 typedef struct _MRSAS_DRV_PCI_INFORMATION { 2634 u_int32_t busNumber; 2635 u_int8_t deviceNumber; 2636 u_int8_t functionNumber; 2637 u_int8_t interruptVector; 2638 u_int8_t reserved1; 2639 MRSAS_DRV_PCI_COMMON_HEADER pciHeaderInfo; 2640 MRSAS_DRV_PCI_CAPABILITIES capability; 2641 u_int32_t domainID; 2642 u_int8_t reserved2[28]; 2643 } MRSAS_DRV_PCI_INFORMATION, *PMRSAS_DRV_PCI_INFORMATION; 2644 2645 /******************************************************************* 2646 * per-instance data 2647 ********************************************************************/ 2648 struct mrsas_softc { 2649 device_t mrsas_dev; 2650 struct cdev *mrsas_cdev; 2651 struct intr_config_hook mrsas_ich; 2652 struct cdev *mrsas_linux_emulator_cdev; 2653 uint16_t device_id; 2654 struct resource *reg_res; 2655 int reg_res_id; 2656 bus_space_tag_t bus_tag; 2657 bus_space_handle_t bus_handle; 2658 bus_dma_tag_t mrsas_parent_tag; 2659 bus_dma_tag_t verbuf_tag; 2660 bus_dmamap_t verbuf_dmamap; 2661 void *verbuf_mem; 2662 bus_addr_t verbuf_phys_addr; 2663 bus_dma_tag_t sense_tag; 2664 bus_dmamap_t sense_dmamap; 2665 void *sense_mem; 2666 bus_addr_t sense_phys_addr; 2667 bus_dma_tag_t io_request_tag; 2668 bus_dmamap_t io_request_dmamap; 2669 void *io_request_mem; 2670 bus_addr_t io_request_phys_addr; 2671 bus_dma_tag_t chain_frame_tag; 2672 bus_dmamap_t chain_frame_dmamap; 2673 void *chain_frame_mem; 2674 bus_addr_t chain_frame_phys_addr; 2675 bus_dma_tag_t reply_desc_tag; 2676 bus_dmamap_t reply_desc_dmamap; 2677 void *reply_desc_mem; 2678 bus_addr_t reply_desc_phys_addr; 2679 bus_dma_tag_t ioc_init_tag; 2680 bus_dmamap_t ioc_init_dmamap; 2681 void *ioc_init_mem; 2682 bus_addr_t ioc_init_phys_mem; 2683 bus_dma_tag_t data_tag; 2684 struct cam_sim *sim_0; 2685 struct cam_sim *sim_1; 2686 struct cam_path *path_0; 2687 struct cam_path *path_1; 2688 struct mtx sim_lock; 2689 struct mtx pci_lock; 2690 struct mtx io_lock; 2691 struct mtx ioctl_lock; 2692 struct mtx mpt_cmd_pool_lock; 2693 struct mtx mfi_cmd_pool_lock; 2694 struct mtx raidmap_lock; 2695 struct mtx aen_lock; 2696 struct selinfo mrsas_select; 2697 uint32_t mrsas_aen_triggered; 2698 uint32_t mrsas_poll_waiting; 2699 2700 struct sema ioctl_count_sema; 2701 uint32_t max_fw_cmds; 2702 uint32_t max_num_sge; 2703 struct resource *mrsas_irq[MAX_MSIX_COUNT]; 2704 void *intr_handle[MAX_MSIX_COUNT]; 2705 int irq_id[MAX_MSIX_COUNT]; 2706 struct mrsas_irq_context irq_context[MAX_MSIX_COUNT]; 2707 int msix_vectors; 2708 int msix_enable; 2709 uint32_t msix_reg_offset[16]; 2710 uint8_t mask_interrupts; 2711 uint16_t max_chain_frame_sz; 2712 struct mrsas_mpt_cmd **mpt_cmd_list; 2713 struct mrsas_mfi_cmd **mfi_cmd_list; 2714 TAILQ_HEAD(, mrsas_mpt_cmd) mrsas_mpt_cmd_list_head; 2715 TAILQ_HEAD(, mrsas_mfi_cmd) mrsas_mfi_cmd_list_head; 2716 bus_addr_t req_frames_desc_phys; 2717 u_int8_t *req_frames_desc; 2718 u_int8_t *req_desc; 2719 bus_addr_t io_request_frames_phys; 2720 u_int8_t *io_request_frames; 2721 bus_addr_t reply_frames_desc_phys; 2722 u_int16_t last_reply_idx[MAX_MSIX_COUNT]; 2723 u_int32_t reply_q_depth; 2724 u_int32_t request_alloc_sz; 2725 u_int32_t reply_alloc_sz; 2726 u_int32_t io_frames_alloc_sz; 2727 u_int32_t chain_frames_alloc_sz; 2728 u_int16_t max_sge_in_main_msg; 2729 u_int16_t max_sge_in_chain; 2730 u_int8_t chain_offset_io_request; 2731 u_int8_t chain_offset_mfi_pthru; 2732 u_int32_t map_sz; 2733 u_int64_t map_id; 2734 u_int64_t pd_seq_map_id; 2735 struct mrsas_mfi_cmd *map_update_cmd; 2736 struct mrsas_mfi_cmd *jbod_seq_cmd; 2737 struct mrsas_mfi_cmd *aen_cmd; 2738 u_int8_t fast_path_io; 2739 void *chan; 2740 void *ocr_chan; 2741 u_int8_t adprecovery; 2742 u_int8_t remove_in_progress; 2743 u_int8_t ocr_thread_active; 2744 u_int8_t do_timedout_reset; 2745 u_int32_t reset_in_progress; 2746 u_int32_t reset_count; 2747 2748 bus_dma_tag_t jbodmap_tag[2]; 2749 bus_dmamap_t jbodmap_dmamap[2]; 2750 void *jbodmap_mem[2]; 2751 bus_addr_t jbodmap_phys_addr[2]; 2752 2753 bus_dma_tag_t raidmap_tag[2]; 2754 bus_dmamap_t raidmap_dmamap[2]; 2755 void *raidmap_mem[2]; 2756 bus_addr_t raidmap_phys_addr[2]; 2757 bus_dma_tag_t mficmd_frame_tag; 2758 bus_dma_tag_t mficmd_sense_tag; 2759 bus_dma_tag_t evt_detail_tag; 2760 bus_dmamap_t evt_detail_dmamap; 2761 struct mrsas_evt_detail *evt_detail_mem; 2762 bus_addr_t evt_detail_phys_addr; 2763 struct mrsas_ctrl_info *ctrl_info; 2764 bus_dma_tag_t ctlr_info_tag; 2765 bus_dmamap_t ctlr_info_dmamap; 2766 void *ctlr_info_mem; 2767 bus_addr_t ctlr_info_phys_addr; 2768 u_int32_t max_sectors_per_req; 2769 u_int32_t disableOnlineCtrlReset; 2770 mrsas_atomic_t fw_outstanding; 2771 u_int32_t mrsas_debug; 2772 u_int32_t mrsas_io_timeout; 2773 u_int32_t mrsas_fw_fault_check_delay; 2774 u_int32_t io_cmds_highwater; 2775 u_int8_t UnevenSpanSupport; 2776 struct sysctl_ctx_list sysctl_ctx; 2777 struct sysctl_oid *sysctl_tree; 2778 struct proc *ocr_thread; 2779 u_int32_t last_seq_num; 2780 bus_dma_tag_t el_info_tag; 2781 bus_dmamap_t el_info_dmamap; 2782 void *el_info_mem; 2783 bus_addr_t el_info_phys_addr; 2784 struct mrsas_pd_list pd_list[MRSAS_MAX_PD]; 2785 struct mrsas_pd_list local_pd_list[MRSAS_MAX_PD]; 2786 u_int8_t ld_ids[MRSAS_MAX_LD_IDS]; 2787 struct taskqueue *ev_tq; 2788 struct task ev_task; 2789 u_int32_t CurLdCount; 2790 u_int64_t reset_flags; 2791 int lb_pending_cmds; 2792 LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES_EXT]; 2793 LD_SPAN_INFO log_to_span[MAX_LOGICAL_DRIVES_EXT]; 2794 2795 u_int8_t secure_jbod_support; 2796 u_int8_t use_seqnum_jbod_fp; 2797 u_int8_t max256vdSupport; 2798 u_int16_t fw_supported_vd_count; 2799 u_int16_t fw_supported_pd_count; 2800 2801 u_int16_t drv_supported_vd_count; 2802 u_int16_t drv_supported_pd_count; 2803 2804 u_int32_t max_map_sz; 2805 u_int32_t current_map_sz; 2806 u_int32_t old_map_sz; 2807 u_int32_t new_map_sz; 2808 u_int32_t drv_map_sz; 2809 2810 /* Non dma-able memory. Driver local copy. */ 2811 MR_DRV_RAID_MAP_ALL *ld_drv_map[2]; 2812 }; 2813 2814 /* Compatibility shims for different OS versions */ 2815 #if __FreeBSD_version >= 800001 2816 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 2817 kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 2818 #define mrsas_kproc_exit(arg) kproc_exit(arg) 2819 #else 2820 #define mrsas_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 2821 kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 2822 #define mrsas_kproc_exit(arg) kthread_exit(arg) 2823 #endif 2824 2825 static __inline void 2826 mrsas_clear_bit(int b, volatile void *p) 2827 { 2828 atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 2829 } 2830 2831 static __inline void 2832 mrsas_set_bit(int b, volatile void *p) 2833 { 2834 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 2835 } 2836 2837 static __inline int 2838 mrsas_test_bit(int b, volatile void *p) 2839 { 2840 return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f)); 2841 } 2842 2843 #endif /* MRSAS_H */ 2844