1 /* 2 * Copyright (c) 2014, LSI Corp. All rights reserved. Author: Marian Choy 3 * Support: freebsdraid@lsi.com 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: 8 * 9 * 1. Redistributions of source code must retain the above copyright notice, 10 * this list of conditions and the following disclaimer. 2. Redistributions 11 * in binary form must reproduce the above copyright notice, this list of 12 * conditions and the following disclaimer in the documentation and/or other 13 * materials provided with the distribution. 3. Neither the name of the 14 * <ORGANIZATION> nor the names of its contributors may be used to endorse or 15 * promote products derived from this software without specific prior written 16 * permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 * 30 * The views and conclusions contained in the software and documentation are 31 * those of the authors and should not be interpreted as representing 32 * official policies,either expressed or implied, of the FreeBSD Project. 33 * 34 * Send feedback to: <megaraidfbsd@lsi.com> Mail to: LSI Corporation, 1621 35 * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD 36 * 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #include <dev/mrsas/mrsas.h> 43 #include <dev/mrsas/mrsas_ioctl.h> 44 45 #include <cam/cam.h> 46 #include <cam/cam_ccb.h> 47 48 #include <sys/sysctl.h> 49 #include <sys/types.h> 50 #include <sys/kthread.h> 51 #include <sys/taskqueue.h> 52 #include <sys/smp.h> 53 54 55 /* 56 * Function prototypes 57 */ 58 static d_open_t mrsas_open; 59 static d_close_t mrsas_close; 60 static d_read_t mrsas_read; 61 static d_write_t mrsas_write; 62 static d_ioctl_t mrsas_ioctl; 63 static d_poll_t mrsas_poll; 64 65 static struct mrsas_mgmt_info mrsas_mgmt_info; 66 static struct mrsas_ident *mrsas_find_ident(device_t); 67 static int mrsas_setup_msix(struct mrsas_softc *sc); 68 static int mrsas_allocate_msix(struct mrsas_softc *sc); 69 static void mrsas_shutdown_ctlr(struct mrsas_softc *sc, u_int32_t opcode); 70 static void mrsas_flush_cache(struct mrsas_softc *sc); 71 static void mrsas_reset_reply_desc(struct mrsas_softc *sc); 72 static void mrsas_ocr_thread(void *arg); 73 static int mrsas_get_map_info(struct mrsas_softc *sc); 74 static int mrsas_get_ld_map_info(struct mrsas_softc *sc); 75 static int mrsas_sync_map_info(struct mrsas_softc *sc); 76 static int mrsas_get_pd_list(struct mrsas_softc *sc); 77 static int mrsas_get_ld_list(struct mrsas_softc *sc); 78 static int mrsas_setup_irq(struct mrsas_softc *sc); 79 static int mrsas_alloc_mem(struct mrsas_softc *sc); 80 static int mrsas_init_fw(struct mrsas_softc *sc); 81 static int mrsas_setup_raidmap(struct mrsas_softc *sc); 82 static int mrsas_complete_cmd(struct mrsas_softc *sc, u_int32_t MSIxIndex); 83 static int mrsas_clear_intr(struct mrsas_softc *sc); 84 static int 85 mrsas_get_ctrl_info(struct mrsas_softc *sc, 86 struct mrsas_ctrl_info *ctrl_info); 87 static int 88 mrsas_issue_blocked_abort_cmd(struct mrsas_softc *sc, 89 struct mrsas_mfi_cmd *cmd_to_abort); 90 u_int32_t mrsas_read_reg(struct mrsas_softc *sc, int offset); 91 u_int8_t 92 mrsas_build_mptmfi_passthru(struct mrsas_softc *sc, 93 struct mrsas_mfi_cmd *mfi_cmd); 94 int mrsas_transition_to_ready(struct mrsas_softc *sc, int ocr); 95 int mrsas_init_adapter(struct mrsas_softc *sc); 96 int mrsas_alloc_mpt_cmds(struct mrsas_softc *sc); 97 int mrsas_alloc_ioc_cmd(struct mrsas_softc *sc); 98 int mrsas_alloc_ctlr_info_cmd(struct mrsas_softc *sc); 99 int mrsas_ioc_init(struct mrsas_softc *sc); 100 int mrsas_bus_scan(struct mrsas_softc *sc); 101 int mrsas_issue_dcmd(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd); 102 int mrsas_issue_polled(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd); 103 int mrsas_reset_ctrl(struct mrsas_softc *sc); 104 int mrsas_wait_for_outstanding(struct mrsas_softc *sc); 105 int 106 mrsas_issue_blocked_cmd(struct mrsas_softc *sc, 107 struct mrsas_mfi_cmd *cmd); 108 int 109 mrsas_alloc_tmp_dcmd(struct mrsas_softc *sc, struct mrsas_tmp_dcmd *tcmd, 110 int size); 111 void mrsas_release_mfi_cmd(struct mrsas_mfi_cmd *cmd); 112 void mrsas_wakeup(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd); 113 void mrsas_complete_aen(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd); 114 void mrsas_complete_abort(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd); 115 void mrsas_disable_intr(struct mrsas_softc *sc); 116 void mrsas_enable_intr(struct mrsas_softc *sc); 117 void mrsas_free_ioc_cmd(struct mrsas_softc *sc); 118 void mrsas_free_mem(struct mrsas_softc *sc); 119 void mrsas_free_tmp_dcmd(struct mrsas_tmp_dcmd *tmp); 120 void mrsas_isr(void *arg); 121 void mrsas_teardown_intr(struct mrsas_softc *sc); 122 void mrsas_addr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 123 void mrsas_kill_hba(struct mrsas_softc *sc); 124 void mrsas_aen_handler(struct mrsas_softc *sc); 125 void 126 mrsas_write_reg(struct mrsas_softc *sc, int offset, 127 u_int32_t value); 128 void 129 mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo, 130 u_int32_t req_desc_hi); 131 void mrsas_free_ctlr_info_cmd(struct mrsas_softc *sc); 132 void 133 mrsas_complete_mptmfi_passthru(struct mrsas_softc *sc, 134 struct mrsas_mfi_cmd *cmd, u_int8_t status); 135 void 136 mrsas_map_mpt_cmd_status(struct mrsas_mpt_cmd *cmd, u_int8_t status, 137 u_int8_t extStatus); 138 struct mrsas_mfi_cmd *mrsas_get_mfi_cmd(struct mrsas_softc *sc); 139 140 MRSAS_REQUEST_DESCRIPTOR_UNION *mrsas_build_mpt_cmd 141 (struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd); 142 143 extern int mrsas_cam_attach(struct mrsas_softc *sc); 144 extern void mrsas_cam_detach(struct mrsas_softc *sc); 145 extern void mrsas_cmd_done(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd); 146 extern void mrsas_free_frame(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd); 147 extern int mrsas_alloc_mfi_cmds(struct mrsas_softc *sc); 148 extern void mrsas_release_mpt_cmd(struct mrsas_mpt_cmd *cmd); 149 extern struct mrsas_mpt_cmd *mrsas_get_mpt_cmd(struct mrsas_softc *sc); 150 extern int mrsas_passthru(struct mrsas_softc *sc, void *arg, u_long ioctlCmd); 151 extern uint8_t MR_ValidateMapInfo(struct mrsas_softc *sc); 152 extern u_int16_t MR_GetLDTgtId(u_int32_t ld, MR_DRV_RAID_MAP_ALL * map); 153 extern MR_LD_RAID *MR_LdRaidGet(u_int32_t ld, MR_DRV_RAID_MAP_ALL * map); 154 extern void mrsas_xpt_freeze(struct mrsas_softc *sc); 155 extern void mrsas_xpt_release(struct mrsas_softc *sc); 156 extern MRSAS_REQUEST_DESCRIPTOR_UNION * 157 mrsas_get_request_desc(struct mrsas_softc *sc, 158 u_int16_t index); 159 extern int mrsas_bus_scan_sim(struct mrsas_softc *sc, struct cam_sim *sim); 160 static int mrsas_alloc_evt_log_info_cmd(struct mrsas_softc *sc); 161 static void mrsas_free_evt_log_info_cmd(struct mrsas_softc *sc); 162 163 SYSCTL_NODE(_hw, OID_AUTO, mrsas, CTLFLAG_RD, 0, "MRSAS Driver Parameters"); 164 165 /* 166 * PCI device struct and table 167 * 168 */ 169 typedef struct mrsas_ident { 170 uint16_t vendor; 171 uint16_t device; 172 uint16_t subvendor; 173 uint16_t subdevice; 174 const char *desc; 175 } MRSAS_CTLR_ID; 176 177 MRSAS_CTLR_ID device_table[] = { 178 {0x1000, MRSAS_TBOLT, 0xffff, 0xffff, "LSI Thunderbolt SAS Controller"}, 179 {0x1000, MRSAS_INVADER, 0xffff, 0xffff, "LSI Invader SAS Controller"}, 180 {0x1000, MRSAS_FURY, 0xffff, 0xffff, "LSI Fury SAS Controller"}, 181 {0, 0, 0, 0, NULL} 182 }; 183 184 /* 185 * Character device entry points 186 * 187 */ 188 static struct cdevsw mrsas_cdevsw = { 189 .d_version = D_VERSION, 190 .d_open = mrsas_open, 191 .d_close = mrsas_close, 192 .d_read = mrsas_read, 193 .d_write = mrsas_write, 194 .d_ioctl = mrsas_ioctl, 195 .d_poll = mrsas_poll, 196 .d_name = "mrsas", 197 }; 198 199 MALLOC_DEFINE(M_MRSAS, "mrsasbuf", "Buffers for the MRSAS driver"); 200 201 /* 202 * In the cdevsw routines, we find our softc by using the si_drv1 member of 203 * struct cdev. We set this variable to point to our softc in our attach 204 * routine when we create the /dev entry. 205 */ 206 int 207 mrsas_open(struct cdev *dev, int oflags, int devtype, struct thread *td) 208 { 209 struct mrsas_softc *sc; 210 211 sc = dev->si_drv1; 212 return (0); 213 } 214 215 int 216 mrsas_close(struct cdev *dev, int fflag, int devtype, struct thread *td) 217 { 218 struct mrsas_softc *sc; 219 220 sc = dev->si_drv1; 221 return (0); 222 } 223 224 int 225 mrsas_read(struct cdev *dev, struct uio *uio, int ioflag) 226 { 227 struct mrsas_softc *sc; 228 229 sc = dev->si_drv1; 230 return (0); 231 } 232 int 233 mrsas_write(struct cdev *dev, struct uio *uio, int ioflag) 234 { 235 struct mrsas_softc *sc; 236 237 sc = dev->si_drv1; 238 return (0); 239 } 240 241 /* 242 * Register Read/Write Functions 243 * 244 */ 245 void 246 mrsas_write_reg(struct mrsas_softc *sc, int offset, 247 u_int32_t value) 248 { 249 bus_space_tag_t bus_tag = sc->bus_tag; 250 bus_space_handle_t bus_handle = sc->bus_handle; 251 252 bus_space_write_4(bus_tag, bus_handle, offset, value); 253 } 254 255 u_int32_t 256 mrsas_read_reg(struct mrsas_softc *sc, int offset) 257 { 258 bus_space_tag_t bus_tag = sc->bus_tag; 259 bus_space_handle_t bus_handle = sc->bus_handle; 260 261 return ((u_int32_t)bus_space_read_4(bus_tag, bus_handle, offset)); 262 } 263 264 265 /* 266 * Interrupt Disable/Enable/Clear Functions 267 * 268 */ 269 void 270 mrsas_disable_intr(struct mrsas_softc *sc) 271 { 272 u_int32_t mask = 0xFFFFFFFF; 273 u_int32_t status; 274 275 mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask), mask); 276 /* Dummy read to force pci flush */ 277 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask)); 278 } 279 280 void 281 mrsas_enable_intr(struct mrsas_softc *sc) 282 { 283 u_int32_t mask = MFI_FUSION_ENABLE_INTERRUPT_MASK; 284 u_int32_t status; 285 286 mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status), ~0); 287 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status)); 288 289 mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask), ~mask); 290 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask)); 291 } 292 293 static int 294 mrsas_clear_intr(struct mrsas_softc *sc) 295 { 296 u_int32_t status, fw_status, fw_state; 297 298 /* Read received interrupt */ 299 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status)); 300 301 /* 302 * If FW state change interrupt is received, write to it again to 303 * clear 304 */ 305 if (status & MRSAS_FW_STATE_CHNG_INTERRUPT) { 306 fw_status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 307 outbound_scratch_pad)); 308 fw_state = fw_status & MFI_STATE_MASK; 309 if (fw_state == MFI_STATE_FAULT) { 310 device_printf(sc->mrsas_dev, "FW is in FAULT state!\n"); 311 if (sc->ocr_thread_active) 312 wakeup(&sc->ocr_chan); 313 } 314 mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status), status); 315 mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status)); 316 return (1); 317 } 318 /* Not our interrupt, so just return */ 319 if (!(status & MFI_FUSION_ENABLE_INTERRUPT_MASK)) 320 return (0); 321 322 /* We got a reply interrupt */ 323 return (1); 324 } 325 326 /* 327 * PCI Support Functions 328 * 329 */ 330 static struct mrsas_ident * 331 mrsas_find_ident(device_t dev) 332 { 333 struct mrsas_ident *pci_device; 334 335 for (pci_device = device_table; pci_device->vendor != 0; pci_device++) { 336 if ((pci_device->vendor == pci_get_vendor(dev)) && 337 (pci_device->device == pci_get_device(dev)) && 338 ((pci_device->subvendor == pci_get_subvendor(dev)) || 339 (pci_device->subvendor == 0xffff)) && 340 ((pci_device->subdevice == pci_get_subdevice(dev)) || 341 (pci_device->subdevice == 0xffff))) 342 return (pci_device); 343 } 344 return (NULL); 345 } 346 347 static int 348 mrsas_probe(device_t dev) 349 { 350 static u_int8_t first_ctrl = 1; 351 struct mrsas_ident *id; 352 353 if ((id = mrsas_find_ident(dev)) != NULL) { 354 if (first_ctrl) { 355 printf("LSI MegaRAID SAS FreeBSD mrsas driver version: %s\n", 356 MRSAS_VERSION); 357 first_ctrl = 0; 358 } 359 device_set_desc(dev, id->desc); 360 /* between BUS_PROBE_DEFAULT and BUS_PROBE_LOW_PRIORITY */ 361 return (-30); 362 } 363 return (ENXIO); 364 } 365 366 /* 367 * mrsas_setup_sysctl: setup sysctl values for mrsas 368 * input: Adapter instance soft state 369 * 370 * Setup sysctl entries for mrsas driver. 371 */ 372 static void 373 mrsas_setup_sysctl(struct mrsas_softc *sc) 374 { 375 struct sysctl_ctx_list *sysctl_ctx = NULL; 376 struct sysctl_oid *sysctl_tree = NULL; 377 char tmpstr[80], tmpstr2[80]; 378 379 /* 380 * Setup the sysctl variable so the user can change the debug level 381 * on the fly. 382 */ 383 snprintf(tmpstr, sizeof(tmpstr), "MRSAS controller %d", 384 device_get_unit(sc->mrsas_dev)); 385 snprintf(tmpstr2, sizeof(tmpstr2), "%d", device_get_unit(sc->mrsas_dev)); 386 387 sysctl_ctx = device_get_sysctl_ctx(sc->mrsas_dev); 388 if (sysctl_ctx != NULL) 389 sysctl_tree = device_get_sysctl_tree(sc->mrsas_dev); 390 391 if (sysctl_tree == NULL) { 392 sysctl_ctx_init(&sc->sysctl_ctx); 393 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 394 SYSCTL_STATIC_CHILDREN(_hw_mrsas), OID_AUTO, tmpstr2, 395 CTLFLAG_RD, 0, tmpstr); 396 if (sc->sysctl_tree == NULL) 397 return; 398 sysctl_ctx = &sc->sysctl_ctx; 399 sysctl_tree = sc->sysctl_tree; 400 } 401 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 402 OID_AUTO, "disable_ocr", CTLFLAG_RW, &sc->disableOnlineCtrlReset, 0, 403 "Disable the use of OCR"); 404 405 SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 406 OID_AUTO, "driver_version", CTLFLAG_RD, MRSAS_VERSION, 407 strlen(MRSAS_VERSION), "driver version"); 408 409 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 410 OID_AUTO, "reset_count", CTLFLAG_RD, 411 &sc->reset_count, 0, "number of ocr from start of the day"); 412 413 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 414 OID_AUTO, "fw_outstanding", CTLFLAG_RD, 415 &sc->fw_outstanding.val_rdonly, 0, "FW outstanding commands"); 416 417 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 418 OID_AUTO, "io_cmds_highwater", CTLFLAG_RD, 419 &sc->io_cmds_highwater, 0, "Max FW outstanding commands"); 420 421 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 422 OID_AUTO, "mrsas_debug", CTLFLAG_RW, &sc->mrsas_debug, 0, 423 "Driver debug level"); 424 425 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 426 OID_AUTO, "mrsas_io_timeout", CTLFLAG_RW, &sc->mrsas_io_timeout, 427 0, "Driver IO timeout value in mili-second."); 428 429 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 430 OID_AUTO, "mrsas_fw_fault_check_delay", CTLFLAG_RW, 431 &sc->mrsas_fw_fault_check_delay, 432 0, "FW fault check thread delay in seconds. <default is 1 sec>"); 433 434 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 435 OID_AUTO, "reset_in_progress", CTLFLAG_RD, 436 &sc->reset_in_progress, 0, "ocr in progress status"); 437 438 } 439 440 /* 441 * mrsas_get_tunables: get tunable parameters. 442 * input: Adapter instance soft state 443 * 444 * Get tunable parameters. This will help to debug driver at boot time. 445 */ 446 static void 447 mrsas_get_tunables(struct mrsas_softc *sc) 448 { 449 char tmpstr[80]; 450 451 /* XXX default to some debugging for now */ 452 sc->mrsas_debug = MRSAS_FAULT; 453 sc->mrsas_io_timeout = MRSAS_IO_TIMEOUT; 454 sc->mrsas_fw_fault_check_delay = 1; 455 sc->reset_count = 0; 456 sc->reset_in_progress = 0; 457 458 /* 459 * Grab the global variables. 460 */ 461 TUNABLE_INT_FETCH("hw.mrsas.debug_level", &sc->mrsas_debug); 462 463 /* Grab the unit-instance variables */ 464 snprintf(tmpstr, sizeof(tmpstr), "dev.mrsas.%d.debug_level", 465 device_get_unit(sc->mrsas_dev)); 466 TUNABLE_INT_FETCH(tmpstr, &sc->mrsas_debug); 467 } 468 469 /* 470 * mrsas_alloc_evt_log_info cmd: Allocates memory to get event log information. 471 * Used to get sequence number at driver load time. 472 * input: Adapter soft state 473 * 474 * Allocates DMAable memory for the event log info internal command. 475 */ 476 int 477 mrsas_alloc_evt_log_info_cmd(struct mrsas_softc *sc) 478 { 479 int el_info_size; 480 481 /* Allocate get event log info command */ 482 el_info_size = sizeof(struct mrsas_evt_log_info); 483 if (bus_dma_tag_create(sc->mrsas_parent_tag, 484 1, 0, 485 BUS_SPACE_MAXADDR_32BIT, 486 BUS_SPACE_MAXADDR, 487 NULL, NULL, 488 el_info_size, 489 1, 490 el_info_size, 491 BUS_DMA_ALLOCNOW, 492 NULL, NULL, 493 &sc->el_info_tag)) { 494 device_printf(sc->mrsas_dev, "Cannot allocate event log info tag\n"); 495 return (ENOMEM); 496 } 497 if (bus_dmamem_alloc(sc->el_info_tag, (void **)&sc->el_info_mem, 498 BUS_DMA_NOWAIT, &sc->el_info_dmamap)) { 499 device_printf(sc->mrsas_dev, "Cannot allocate event log info cmd mem\n"); 500 return (ENOMEM); 501 } 502 if (bus_dmamap_load(sc->el_info_tag, sc->el_info_dmamap, 503 sc->el_info_mem, el_info_size, mrsas_addr_cb, 504 &sc->el_info_phys_addr, BUS_DMA_NOWAIT)) { 505 device_printf(sc->mrsas_dev, "Cannot load event log info cmd mem\n"); 506 return (ENOMEM); 507 } 508 memset(sc->el_info_mem, 0, el_info_size); 509 return (0); 510 } 511 512 /* 513 * mrsas_free_evt_info_cmd: Free memory for Event log info command 514 * input: Adapter soft state 515 * 516 * Deallocates memory for the event log info internal command. 517 */ 518 void 519 mrsas_free_evt_log_info_cmd(struct mrsas_softc *sc) 520 { 521 if (sc->el_info_phys_addr) 522 bus_dmamap_unload(sc->el_info_tag, sc->el_info_dmamap); 523 if (sc->el_info_mem != NULL) 524 bus_dmamem_free(sc->el_info_tag, sc->el_info_mem, sc->el_info_dmamap); 525 if (sc->el_info_tag != NULL) 526 bus_dma_tag_destroy(sc->el_info_tag); 527 } 528 529 /* 530 * mrsas_get_seq_num: Get latest event sequence number 531 * @sc: Adapter soft state 532 * @eli: Firmware event log sequence number information. 533 * 534 * Firmware maintains a log of all events in a non-volatile area. 535 * Driver get the sequence number using DCMD 536 * "MR_DCMD_CTRL_EVENT_GET_INFO" at driver load time. 537 */ 538 539 static int 540 mrsas_get_seq_num(struct mrsas_softc *sc, 541 struct mrsas_evt_log_info *eli) 542 { 543 struct mrsas_mfi_cmd *cmd; 544 struct mrsas_dcmd_frame *dcmd; 545 546 cmd = mrsas_get_mfi_cmd(sc); 547 548 if (!cmd) { 549 device_printf(sc->mrsas_dev, "Failed to get a free cmd\n"); 550 return -ENOMEM; 551 } 552 dcmd = &cmd->frame->dcmd; 553 554 if (mrsas_alloc_evt_log_info_cmd(sc) != SUCCESS) { 555 device_printf(sc->mrsas_dev, "Cannot allocate evt log info cmd\n"); 556 mrsas_release_mfi_cmd(cmd); 557 return -ENOMEM; 558 } 559 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 560 561 dcmd->cmd = MFI_CMD_DCMD; 562 dcmd->cmd_status = 0x0; 563 dcmd->sge_count = 1; 564 dcmd->flags = MFI_FRAME_DIR_READ; 565 dcmd->timeout = 0; 566 dcmd->pad_0 = 0; 567 dcmd->data_xfer_len = sizeof(struct mrsas_evt_log_info); 568 dcmd->opcode = MR_DCMD_CTRL_EVENT_GET_INFO; 569 dcmd->sgl.sge32[0].phys_addr = sc->el_info_phys_addr; 570 dcmd->sgl.sge32[0].length = sizeof(struct mrsas_evt_log_info); 571 572 mrsas_issue_blocked_cmd(sc, cmd); 573 574 /* 575 * Copy the data back into callers buffer 576 */ 577 memcpy(eli, sc->el_info_mem, sizeof(struct mrsas_evt_log_info)); 578 mrsas_free_evt_log_info_cmd(sc); 579 mrsas_release_mfi_cmd(cmd); 580 581 return 0; 582 } 583 584 585 /* 586 * mrsas_register_aen: Register for asynchronous event notification 587 * @sc: Adapter soft state 588 * @seq_num: Starting sequence number 589 * @class_locale: Class of the event 590 * 591 * This function subscribes for events beyond the @seq_num 592 * and type @class_locale. 593 * 594 */ 595 static int 596 mrsas_register_aen(struct mrsas_softc *sc, u_int32_t seq_num, 597 u_int32_t class_locale_word) 598 { 599 int ret_val; 600 struct mrsas_mfi_cmd *cmd; 601 struct mrsas_dcmd_frame *dcmd; 602 union mrsas_evt_class_locale curr_aen; 603 union mrsas_evt_class_locale prev_aen; 604 605 /* 606 * If there an AEN pending already (aen_cmd), check if the 607 * class_locale of that pending AEN is inclusive of the new AEN 608 * request we currently have. If it is, then we don't have to do 609 * anything. In other words, whichever events the current AEN request 610 * is subscribing to, have already been subscribed to. If the old_cmd 611 * is _not_ inclusive, then we have to abort that command, form a 612 * class_locale that is superset of both old and current and re-issue 613 * to the FW 614 */ 615 616 curr_aen.word = class_locale_word; 617 618 if (sc->aen_cmd) { 619 620 prev_aen.word = sc->aen_cmd->frame->dcmd.mbox.w[1]; 621 622 /* 623 * A class whose enum value is smaller is inclusive of all 624 * higher values. If a PROGRESS (= -1) was previously 625 * registered, then a new registration requests for higher 626 * classes need not be sent to FW. They are automatically 627 * included. Locale numbers don't have such hierarchy. They 628 * are bitmap values 629 */ 630 if ((prev_aen.members.class <= curr_aen.members.class) && 631 !((prev_aen.members.locale & curr_aen.members.locale) ^ 632 curr_aen.members.locale)) { 633 /* 634 * Previously issued event registration includes 635 * current request. Nothing to do. 636 */ 637 return 0; 638 } else { 639 curr_aen.members.locale |= prev_aen.members.locale; 640 641 if (prev_aen.members.class < curr_aen.members.class) 642 curr_aen.members.class = prev_aen.members.class; 643 644 sc->aen_cmd->abort_aen = 1; 645 ret_val = mrsas_issue_blocked_abort_cmd(sc, 646 sc->aen_cmd); 647 648 if (ret_val) { 649 printf("mrsas: Failed to abort " 650 "previous AEN command\n"); 651 return ret_val; 652 } 653 } 654 } 655 cmd = mrsas_get_mfi_cmd(sc); 656 657 if (!cmd) 658 return -ENOMEM; 659 660 dcmd = &cmd->frame->dcmd; 661 662 memset(sc->evt_detail_mem, 0, sizeof(struct mrsas_evt_detail)); 663 664 /* 665 * Prepare DCMD for aen registration 666 */ 667 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 668 669 dcmd->cmd = MFI_CMD_DCMD; 670 dcmd->cmd_status = 0x0; 671 dcmd->sge_count = 1; 672 dcmd->flags = MFI_FRAME_DIR_READ; 673 dcmd->timeout = 0; 674 dcmd->pad_0 = 0; 675 dcmd->data_xfer_len = sizeof(struct mrsas_evt_detail); 676 dcmd->opcode = MR_DCMD_CTRL_EVENT_WAIT; 677 dcmd->mbox.w[0] = seq_num; 678 sc->last_seq_num = seq_num; 679 dcmd->mbox.w[1] = curr_aen.word; 680 dcmd->sgl.sge32[0].phys_addr = (u_int32_t)sc->evt_detail_phys_addr; 681 dcmd->sgl.sge32[0].length = sizeof(struct mrsas_evt_detail); 682 683 if (sc->aen_cmd != NULL) { 684 mrsas_release_mfi_cmd(cmd); 685 return 0; 686 } 687 /* 688 * Store reference to the cmd used to register for AEN. When an 689 * application wants us to register for AEN, we have to abort this 690 * cmd and re-register with a new EVENT LOCALE supplied by that app 691 */ 692 sc->aen_cmd = cmd; 693 694 /* 695 * Issue the aen registration frame 696 */ 697 if (mrsas_issue_dcmd(sc, cmd)) { 698 device_printf(sc->mrsas_dev, "Cannot issue AEN DCMD command.\n"); 699 return (1); 700 } 701 return 0; 702 } 703 704 /* 705 * mrsas_start_aen: Subscribes to AEN during driver load time 706 * @instance: Adapter soft state 707 */ 708 static int 709 mrsas_start_aen(struct mrsas_softc *sc) 710 { 711 struct mrsas_evt_log_info eli; 712 union mrsas_evt_class_locale class_locale; 713 714 715 /* Get the latest sequence number from FW */ 716 717 memset(&eli, 0, sizeof(eli)); 718 719 if (mrsas_get_seq_num(sc, &eli)) 720 return -1; 721 722 /* Register AEN with FW for latest sequence number plus 1 */ 723 class_locale.members.reserved = 0; 724 class_locale.members.locale = MR_EVT_LOCALE_ALL; 725 class_locale.members.class = MR_EVT_CLASS_DEBUG; 726 727 return mrsas_register_aen(sc, eli.newest_seq_num + 1, 728 class_locale.word); 729 730 } 731 732 /* 733 * mrsas_setup_msix: Allocate MSI-x vectors 734 * @sc: adapter soft state 735 */ 736 static int 737 mrsas_setup_msix(struct mrsas_softc *sc) 738 { 739 int i; 740 741 for (i = 0; i < sc->msix_vectors; i++) { 742 sc->irq_context[i].sc = sc; 743 sc->irq_context[i].MSIxIndex = i; 744 sc->irq_id[i] = i + 1; 745 sc->mrsas_irq[i] = bus_alloc_resource_any 746 (sc->mrsas_dev, SYS_RES_IRQ, &sc->irq_id[i] 747 ,RF_ACTIVE); 748 if (sc->mrsas_irq[i] == NULL) { 749 device_printf(sc->mrsas_dev, "Can't allocate MSI-x\n"); 750 goto irq_alloc_failed; 751 } 752 if (bus_setup_intr(sc->mrsas_dev, 753 sc->mrsas_irq[i], 754 INTR_MPSAFE | INTR_TYPE_CAM, 755 NULL, mrsas_isr, &sc->irq_context[i], 756 &sc->intr_handle[i])) { 757 device_printf(sc->mrsas_dev, 758 "Cannot set up MSI-x interrupt handler\n"); 759 goto irq_alloc_failed; 760 } 761 } 762 return SUCCESS; 763 764 irq_alloc_failed: 765 mrsas_teardown_intr(sc); 766 return (FAIL); 767 } 768 769 /* 770 * mrsas_allocate_msix: Setup MSI-x vectors 771 * @sc: adapter soft state 772 */ 773 static int 774 mrsas_allocate_msix(struct mrsas_softc *sc) 775 { 776 if (pci_alloc_msix(sc->mrsas_dev, &sc->msix_vectors) == 0) { 777 device_printf(sc->mrsas_dev, "Using MSI-X with %d number" 778 " of vectors\n", sc->msix_vectors); 779 } else { 780 device_printf(sc->mrsas_dev, "MSI-x setup failed\n"); 781 goto irq_alloc_failed; 782 } 783 return SUCCESS; 784 785 irq_alloc_failed: 786 mrsas_teardown_intr(sc); 787 return (FAIL); 788 } 789 790 /* 791 * mrsas_attach: PCI entry point 792 * input: pointer to device struct 793 * 794 * Performs setup of PCI and registers, initializes mutexes and linked lists, 795 * registers interrupts and CAM, and initializes the adapter/controller to 796 * its proper state. 797 */ 798 static int 799 mrsas_attach(device_t dev) 800 { 801 struct mrsas_softc *sc = device_get_softc(dev); 802 uint32_t cmd, bar, error; 803 804 /* Look up our softc and initialize its fields. */ 805 sc->mrsas_dev = dev; 806 sc->device_id = pci_get_device(dev); 807 808 mrsas_get_tunables(sc); 809 810 /* 811 * Set up PCI and registers 812 */ 813 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 814 if ((cmd & PCIM_CMD_PORTEN) == 0) { 815 return (ENXIO); 816 } 817 /* Force the busmaster enable bit on. */ 818 cmd |= PCIM_CMD_BUSMASTEREN; 819 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 820 821 bar = pci_read_config(dev, MRSAS_PCI_BAR1, 4); 822 823 sc->reg_res_id = MRSAS_PCI_BAR1;/* BAR1 offset */ 824 if ((sc->reg_res = bus_alloc_resource(dev, SYS_RES_MEMORY, 825 &(sc->reg_res_id), 0, ~0, 1, RF_ACTIVE)) 826 == NULL) { 827 device_printf(dev, "Cannot allocate PCI registers\n"); 828 goto attach_fail; 829 } 830 sc->bus_tag = rman_get_bustag(sc->reg_res); 831 sc->bus_handle = rman_get_bushandle(sc->reg_res); 832 833 /* Intialize mutexes */ 834 mtx_init(&sc->sim_lock, "mrsas_sim_lock", NULL, MTX_DEF); 835 mtx_init(&sc->pci_lock, "mrsas_pci_lock", NULL, MTX_DEF); 836 mtx_init(&sc->io_lock, "mrsas_io_lock", NULL, MTX_DEF); 837 mtx_init(&sc->aen_lock, "mrsas_aen_lock", NULL, MTX_DEF); 838 mtx_init(&sc->ioctl_lock, "mrsas_ioctl_lock", NULL, MTX_SPIN); 839 mtx_init(&sc->mpt_cmd_pool_lock, "mrsas_mpt_cmd_pool_lock", NULL, MTX_DEF); 840 mtx_init(&sc->mfi_cmd_pool_lock, "mrsas_mfi_cmd_pool_lock", NULL, MTX_DEF); 841 mtx_init(&sc->raidmap_lock, "mrsas_raidmap_lock", NULL, MTX_DEF); 842 843 /* 844 * Intialize a counting Semaphore to take care no. of concurrent 845 * IOCTLs 846 */ 847 sema_init(&sc->ioctl_count_sema, MRSAS_MAX_MFI_CMDS - 5, IOCTL_SEMA_DESCRIPTION); 848 849 /* Intialize linked list */ 850 TAILQ_INIT(&sc->mrsas_mpt_cmd_list_head); 851 TAILQ_INIT(&sc->mrsas_mfi_cmd_list_head); 852 853 mrsas_atomic_set(&sc->fw_outstanding, 0); 854 855 sc->io_cmds_highwater = 0; 856 857 /* Create a /dev entry for this device. */ 858 sc->mrsas_cdev = make_dev(&mrsas_cdevsw, device_get_unit(dev), UID_ROOT, 859 GID_OPERATOR, (S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP), "mrsas%u", 860 device_get_unit(dev)); 861 if (device_get_unit(dev) == 0) 862 make_dev_alias(sc->mrsas_cdev, "megaraid_sas_ioctl_node"); 863 if (sc->mrsas_cdev) 864 sc->mrsas_cdev->si_drv1 = sc; 865 866 sc->adprecovery = MRSAS_HBA_OPERATIONAL; 867 sc->UnevenSpanSupport = 0; 868 869 sc->msix_enable = 0; 870 871 /* Initialize Firmware */ 872 if (mrsas_init_fw(sc) != SUCCESS) { 873 goto attach_fail_fw; 874 } 875 /* Register SCSI mid-layer */ 876 if ((mrsas_cam_attach(sc) != SUCCESS)) { 877 goto attach_fail_cam; 878 } 879 /* Register IRQs */ 880 if (mrsas_setup_irq(sc) != SUCCESS) { 881 goto attach_fail_irq; 882 } 883 /* Enable Interrupts */ 884 mrsas_enable_intr(sc); 885 886 error = mrsas_kproc_create(mrsas_ocr_thread, sc, 887 &sc->ocr_thread, 0, 0, "mrsas_ocr%d", 888 device_get_unit(sc->mrsas_dev)); 889 if (error) { 890 printf("Error %d starting rescan thread\n", error); 891 goto attach_fail_irq; 892 } 893 mrsas_setup_sysctl(sc); 894 895 /* Initiate AEN (Asynchronous Event Notification) */ 896 897 if (mrsas_start_aen(sc)) { 898 printf("Error: start aen failed\n"); 899 goto fail_start_aen; 900 } 901 /* 902 * Add this controller to mrsas_mgmt_info structure so that it can be 903 * exported to management applications 904 */ 905 if (device_get_unit(dev) == 0) 906 memset(&mrsas_mgmt_info, 0, sizeof(mrsas_mgmt_info)); 907 908 mrsas_mgmt_info.count++; 909 mrsas_mgmt_info.sc_ptr[mrsas_mgmt_info.max_index] = sc; 910 mrsas_mgmt_info.max_index++; 911 912 return (0); 913 914 fail_start_aen: 915 attach_fail_irq: 916 mrsas_teardown_intr(sc); 917 attach_fail_cam: 918 mrsas_cam_detach(sc); 919 attach_fail_fw: 920 /* if MSIX vector is allocated and FW Init FAILED then release MSIX */ 921 if (sc->msix_enable == 1) 922 pci_release_msi(sc->mrsas_dev); 923 mrsas_free_mem(sc); 924 mtx_destroy(&sc->sim_lock); 925 mtx_destroy(&sc->aen_lock); 926 mtx_destroy(&sc->pci_lock); 927 mtx_destroy(&sc->io_lock); 928 mtx_destroy(&sc->ioctl_lock); 929 mtx_destroy(&sc->mpt_cmd_pool_lock); 930 mtx_destroy(&sc->mfi_cmd_pool_lock); 931 mtx_destroy(&sc->raidmap_lock); 932 /* Destroy the counting semaphore created for Ioctl */ 933 sema_destroy(&sc->ioctl_count_sema); 934 attach_fail: 935 destroy_dev(sc->mrsas_cdev); 936 if (sc->reg_res) { 937 bus_release_resource(sc->mrsas_dev, SYS_RES_MEMORY, 938 sc->reg_res_id, sc->reg_res); 939 } 940 return (ENXIO); 941 } 942 943 /* 944 * mrsas_detach: De-allocates and teardown resources 945 * input: pointer to device struct 946 * 947 * This function is the entry point for device disconnect and detach. 948 * It performs memory de-allocations, shutdown of the controller and various 949 * teardown and destroy resource functions. 950 */ 951 static int 952 mrsas_detach(device_t dev) 953 { 954 struct mrsas_softc *sc; 955 int i = 0; 956 957 sc = device_get_softc(dev); 958 sc->remove_in_progress = 1; 959 960 /* Destroy the character device so no other IOCTL will be handled */ 961 destroy_dev(sc->mrsas_cdev); 962 963 /* 964 * Take the instance off the instance array. Note that we will not 965 * decrement the max_index. We let this array be sparse array 966 */ 967 for (i = 0; i < mrsas_mgmt_info.max_index; i++) { 968 if (mrsas_mgmt_info.sc_ptr[i] == sc) { 969 mrsas_mgmt_info.count--; 970 mrsas_mgmt_info.sc_ptr[i] = NULL; 971 break; 972 } 973 } 974 975 if (sc->ocr_thread_active) 976 wakeup(&sc->ocr_chan); 977 while (sc->reset_in_progress) { 978 i++; 979 if (!(i % MRSAS_RESET_NOTICE_INTERVAL)) { 980 mrsas_dprint(sc, MRSAS_INFO, 981 "[%2d]waiting for ocr to be finished\n", i); 982 } 983 pause("mr_shutdown", hz); 984 } 985 i = 0; 986 while (sc->ocr_thread_active) { 987 i++; 988 if (!(i % MRSAS_RESET_NOTICE_INTERVAL)) { 989 mrsas_dprint(sc, MRSAS_INFO, 990 "[%2d]waiting for " 991 "mrsas_ocr thread to quit ocr %d\n", i, 992 sc->ocr_thread_active); 993 } 994 pause("mr_shutdown", hz); 995 } 996 mrsas_flush_cache(sc); 997 mrsas_shutdown_ctlr(sc, MR_DCMD_CTRL_SHUTDOWN); 998 mrsas_disable_intr(sc); 999 mrsas_cam_detach(sc); 1000 mrsas_teardown_intr(sc); 1001 mrsas_free_mem(sc); 1002 mtx_destroy(&sc->sim_lock); 1003 mtx_destroy(&sc->aen_lock); 1004 mtx_destroy(&sc->pci_lock); 1005 mtx_destroy(&sc->io_lock); 1006 mtx_destroy(&sc->ioctl_lock); 1007 mtx_destroy(&sc->mpt_cmd_pool_lock); 1008 mtx_destroy(&sc->mfi_cmd_pool_lock); 1009 mtx_destroy(&sc->raidmap_lock); 1010 1011 /* Wait for all the semaphores to be released */ 1012 while (sema_value(&sc->ioctl_count_sema) != (MRSAS_MAX_MFI_CMDS - 5)) 1013 pause("mr_shutdown", hz); 1014 1015 /* Destroy the counting semaphore created for Ioctl */ 1016 sema_destroy(&sc->ioctl_count_sema); 1017 1018 if (sc->reg_res) { 1019 bus_release_resource(sc->mrsas_dev, 1020 SYS_RES_MEMORY, sc->reg_res_id, sc->reg_res); 1021 } 1022 if (sc->sysctl_tree != NULL) 1023 sysctl_ctx_free(&sc->sysctl_ctx); 1024 1025 return (0); 1026 } 1027 1028 /* 1029 * mrsas_free_mem: Frees allocated memory 1030 * input: Adapter instance soft state 1031 * 1032 * This function is called from mrsas_detach() to free previously allocated 1033 * memory. 1034 */ 1035 void 1036 mrsas_free_mem(struct mrsas_softc *sc) 1037 { 1038 int i; 1039 u_int32_t max_cmd; 1040 struct mrsas_mfi_cmd *mfi_cmd; 1041 struct mrsas_mpt_cmd *mpt_cmd; 1042 1043 /* 1044 * Free RAID map memory 1045 */ 1046 for (i = 0; i < 2; i++) { 1047 if (sc->raidmap_phys_addr[i]) 1048 bus_dmamap_unload(sc->raidmap_tag[i], sc->raidmap_dmamap[i]); 1049 if (sc->raidmap_mem[i] != NULL) 1050 bus_dmamem_free(sc->raidmap_tag[i], sc->raidmap_mem[i], sc->raidmap_dmamap[i]); 1051 if (sc->raidmap_tag[i] != NULL) 1052 bus_dma_tag_destroy(sc->raidmap_tag[i]); 1053 1054 if (sc->ld_drv_map[i] != NULL) 1055 free(sc->ld_drv_map[i], M_MRSAS); 1056 } 1057 1058 /* 1059 * Free version buffer memroy 1060 */ 1061 if (sc->verbuf_phys_addr) 1062 bus_dmamap_unload(sc->verbuf_tag, sc->verbuf_dmamap); 1063 if (sc->verbuf_mem != NULL) 1064 bus_dmamem_free(sc->verbuf_tag, sc->verbuf_mem, sc->verbuf_dmamap); 1065 if (sc->verbuf_tag != NULL) 1066 bus_dma_tag_destroy(sc->verbuf_tag); 1067 1068 1069 /* 1070 * Free sense buffer memory 1071 */ 1072 if (sc->sense_phys_addr) 1073 bus_dmamap_unload(sc->sense_tag, sc->sense_dmamap); 1074 if (sc->sense_mem != NULL) 1075 bus_dmamem_free(sc->sense_tag, sc->sense_mem, sc->sense_dmamap); 1076 if (sc->sense_tag != NULL) 1077 bus_dma_tag_destroy(sc->sense_tag); 1078 1079 /* 1080 * Free chain frame memory 1081 */ 1082 if (sc->chain_frame_phys_addr) 1083 bus_dmamap_unload(sc->chain_frame_tag, sc->chain_frame_dmamap); 1084 if (sc->chain_frame_mem != NULL) 1085 bus_dmamem_free(sc->chain_frame_tag, sc->chain_frame_mem, sc->chain_frame_dmamap); 1086 if (sc->chain_frame_tag != NULL) 1087 bus_dma_tag_destroy(sc->chain_frame_tag); 1088 1089 /* 1090 * Free IO Request memory 1091 */ 1092 if (sc->io_request_phys_addr) 1093 bus_dmamap_unload(sc->io_request_tag, sc->io_request_dmamap); 1094 if (sc->io_request_mem != NULL) 1095 bus_dmamem_free(sc->io_request_tag, sc->io_request_mem, sc->io_request_dmamap); 1096 if (sc->io_request_tag != NULL) 1097 bus_dma_tag_destroy(sc->io_request_tag); 1098 1099 /* 1100 * Free Reply Descriptor memory 1101 */ 1102 if (sc->reply_desc_phys_addr) 1103 bus_dmamap_unload(sc->reply_desc_tag, sc->reply_desc_dmamap); 1104 if (sc->reply_desc_mem != NULL) 1105 bus_dmamem_free(sc->reply_desc_tag, sc->reply_desc_mem, sc->reply_desc_dmamap); 1106 if (sc->reply_desc_tag != NULL) 1107 bus_dma_tag_destroy(sc->reply_desc_tag); 1108 1109 /* 1110 * Free event detail memory 1111 */ 1112 if (sc->evt_detail_phys_addr) 1113 bus_dmamap_unload(sc->evt_detail_tag, sc->evt_detail_dmamap); 1114 if (sc->evt_detail_mem != NULL) 1115 bus_dmamem_free(sc->evt_detail_tag, sc->evt_detail_mem, sc->evt_detail_dmamap); 1116 if (sc->evt_detail_tag != NULL) 1117 bus_dma_tag_destroy(sc->evt_detail_tag); 1118 1119 /* 1120 * Free MFI frames 1121 */ 1122 if (sc->mfi_cmd_list) { 1123 for (i = 0; i < MRSAS_MAX_MFI_CMDS; i++) { 1124 mfi_cmd = sc->mfi_cmd_list[i]; 1125 mrsas_free_frame(sc, mfi_cmd); 1126 } 1127 } 1128 if (sc->mficmd_frame_tag != NULL) 1129 bus_dma_tag_destroy(sc->mficmd_frame_tag); 1130 1131 /* 1132 * Free MPT internal command list 1133 */ 1134 max_cmd = sc->max_fw_cmds; 1135 if (sc->mpt_cmd_list) { 1136 for (i = 0; i < max_cmd; i++) { 1137 mpt_cmd = sc->mpt_cmd_list[i]; 1138 bus_dmamap_destroy(sc->data_tag, mpt_cmd->data_dmamap); 1139 free(sc->mpt_cmd_list[i], M_MRSAS); 1140 } 1141 free(sc->mpt_cmd_list, M_MRSAS); 1142 sc->mpt_cmd_list = NULL; 1143 } 1144 /* 1145 * Free MFI internal command list 1146 */ 1147 1148 if (sc->mfi_cmd_list) { 1149 for (i = 0; i < MRSAS_MAX_MFI_CMDS; i++) { 1150 free(sc->mfi_cmd_list[i], M_MRSAS); 1151 } 1152 free(sc->mfi_cmd_list, M_MRSAS); 1153 sc->mfi_cmd_list = NULL; 1154 } 1155 /* 1156 * Free request descriptor memory 1157 */ 1158 free(sc->req_desc, M_MRSAS); 1159 sc->req_desc = NULL; 1160 1161 /* 1162 * Destroy parent tag 1163 */ 1164 if (sc->mrsas_parent_tag != NULL) 1165 bus_dma_tag_destroy(sc->mrsas_parent_tag); 1166 } 1167 1168 /* 1169 * mrsas_teardown_intr: Teardown interrupt 1170 * input: Adapter instance soft state 1171 * 1172 * This function is called from mrsas_detach() to teardown and release bus 1173 * interrupt resourse. 1174 */ 1175 void 1176 mrsas_teardown_intr(struct mrsas_softc *sc) 1177 { 1178 int i; 1179 1180 if (!sc->msix_enable) { 1181 if (sc->intr_handle[0]) 1182 bus_teardown_intr(sc->mrsas_dev, sc->mrsas_irq[0], sc->intr_handle[0]); 1183 if (sc->mrsas_irq[0] != NULL) 1184 bus_release_resource(sc->mrsas_dev, SYS_RES_IRQ, 1185 sc->irq_id[0], sc->mrsas_irq[0]); 1186 sc->intr_handle[0] = NULL; 1187 } else { 1188 for (i = 0; i < sc->msix_vectors; i++) { 1189 if (sc->intr_handle[i]) 1190 bus_teardown_intr(sc->mrsas_dev, sc->mrsas_irq[i], 1191 sc->intr_handle[i]); 1192 1193 if (sc->mrsas_irq[i] != NULL) 1194 bus_release_resource(sc->mrsas_dev, SYS_RES_IRQ, 1195 sc->irq_id[i], sc->mrsas_irq[i]); 1196 1197 sc->intr_handle[i] = NULL; 1198 } 1199 pci_release_msi(sc->mrsas_dev); 1200 } 1201 1202 } 1203 1204 /* 1205 * mrsas_suspend: Suspend entry point 1206 * input: Device struct pointer 1207 * 1208 * This function is the entry point for system suspend from the OS. 1209 */ 1210 static int 1211 mrsas_suspend(device_t dev) 1212 { 1213 struct mrsas_softc *sc; 1214 1215 sc = device_get_softc(dev); 1216 return (0); 1217 } 1218 1219 /* 1220 * mrsas_resume: Resume entry point 1221 * input: Device struct pointer 1222 * 1223 * This function is the entry point for system resume from the OS. 1224 */ 1225 static int 1226 mrsas_resume(device_t dev) 1227 { 1228 struct mrsas_softc *sc; 1229 1230 sc = device_get_softc(dev); 1231 return (0); 1232 } 1233 1234 /* 1235 * mrsas_ioctl: IOCtl commands entry point. 1236 * 1237 * This function is the entry point for IOCtls from the OS. It calls the 1238 * appropriate function for processing depending on the command received. 1239 */ 1240 static int 1241 mrsas_ioctl(struct cdev *dev, u_long cmd, caddr_t arg, int flag, 1242 struct thread *td) 1243 { 1244 struct mrsas_softc *sc; 1245 int ret = 0, i = 0; 1246 1247 struct mrsas_iocpacket *user_ioc = (struct mrsas_iocpacket *)arg; 1248 1249 /* get the Host number & the softc from data sent by the Application */ 1250 sc = mrsas_mgmt_info.sc_ptr[user_ioc->host_no]; 1251 1252 if ((mrsas_mgmt_info.max_index == user_ioc->host_no) || (sc == NULL)) { 1253 printf("Please check the controller number\n"); 1254 if (sc == NULL) 1255 printf("There is NO such Host no. %d\n", user_ioc->host_no); 1256 1257 return ENOENT; 1258 } 1259 if (sc->remove_in_progress) { 1260 mrsas_dprint(sc, MRSAS_INFO, 1261 "Driver remove or shutdown called.\n"); 1262 return ENOENT; 1263 } 1264 mtx_lock_spin(&sc->ioctl_lock); 1265 if (!sc->reset_in_progress) { 1266 mtx_unlock_spin(&sc->ioctl_lock); 1267 goto do_ioctl; 1268 } 1269 mtx_unlock_spin(&sc->ioctl_lock); 1270 while (sc->reset_in_progress) { 1271 i++; 1272 if (!(i % MRSAS_RESET_NOTICE_INTERVAL)) { 1273 mrsas_dprint(sc, MRSAS_INFO, 1274 "[%2d]waiting for " 1275 "OCR to be finished %d\n", i, 1276 sc->ocr_thread_active); 1277 } 1278 pause("mr_ioctl", hz); 1279 } 1280 1281 do_ioctl: 1282 switch (cmd) { 1283 case MRSAS_IOC_FIRMWARE_PASS_THROUGH64: 1284 #ifdef COMPAT_FREEBSD32 1285 case MRSAS_IOC_FIRMWARE_PASS_THROUGH32: 1286 #endif 1287 /* 1288 * Decrement the Ioctl counting Semaphore before getting an 1289 * mfi command 1290 */ 1291 sema_wait(&sc->ioctl_count_sema); 1292 1293 ret = mrsas_passthru(sc, (void *)arg, cmd); 1294 1295 /* Increment the Ioctl counting semaphore value */ 1296 sema_post(&sc->ioctl_count_sema); 1297 1298 break; 1299 case MRSAS_IOC_SCAN_BUS: 1300 ret = mrsas_bus_scan(sc); 1301 break; 1302 default: 1303 mrsas_dprint(sc, MRSAS_TRACE, "IOCTL command 0x%lx is not handled\n", cmd); 1304 ret = ENOENT; 1305 } 1306 1307 return (ret); 1308 } 1309 1310 /* 1311 * mrsas_poll: poll entry point for mrsas driver fd 1312 * 1313 * This function is the entry point for poll from the OS. It waits for some AEN 1314 * events to be triggered from the controller and notifies back. 1315 */ 1316 static int 1317 mrsas_poll(struct cdev *dev, int poll_events, struct thread *td) 1318 { 1319 struct mrsas_softc *sc; 1320 int revents = 0; 1321 1322 sc = dev->si_drv1; 1323 1324 if (poll_events & (POLLIN | POLLRDNORM)) { 1325 if (sc->mrsas_aen_triggered) { 1326 revents |= poll_events & (POLLIN | POLLRDNORM); 1327 } 1328 } 1329 if (revents == 0) { 1330 if (poll_events & (POLLIN | POLLRDNORM)) { 1331 sc->mrsas_poll_waiting = 1; 1332 selrecord(td, &sc->mrsas_select); 1333 } 1334 } 1335 return revents; 1336 } 1337 1338 /* 1339 * mrsas_setup_irq: Set up interrupt 1340 * input: Adapter instance soft state 1341 * 1342 * This function sets up interrupts as a bus resource, with flags indicating 1343 * resource permitting contemporaneous sharing and for resource to activate 1344 * atomically. 1345 */ 1346 static int 1347 mrsas_setup_irq(struct mrsas_softc *sc) 1348 { 1349 if (sc->msix_enable && (mrsas_setup_msix(sc) == SUCCESS)) 1350 device_printf(sc->mrsas_dev, "MSI-x interrupts setup success\n"); 1351 1352 else { 1353 device_printf(sc->mrsas_dev, "Fall back to legacy interrupt\n"); 1354 sc->irq_context[0].sc = sc; 1355 sc->irq_context[0].MSIxIndex = 0; 1356 sc->irq_id[0] = 0; 1357 sc->mrsas_irq[0] = bus_alloc_resource_any(sc->mrsas_dev, 1358 SYS_RES_IRQ, &sc->irq_id[0], RF_SHAREABLE | RF_ACTIVE); 1359 if (sc->mrsas_irq[0] == NULL) { 1360 device_printf(sc->mrsas_dev, "Cannot allocate legcay" 1361 "interrupt\n"); 1362 return (FAIL); 1363 } 1364 if (bus_setup_intr(sc->mrsas_dev, sc->mrsas_irq[0], 1365 INTR_MPSAFE | INTR_TYPE_CAM, NULL, mrsas_isr, 1366 &sc->irq_context[0], &sc->intr_handle[0])) { 1367 device_printf(sc->mrsas_dev, "Cannot set up legacy" 1368 "interrupt\n"); 1369 return (FAIL); 1370 } 1371 } 1372 return (0); 1373 } 1374 1375 /* 1376 * mrsas_isr: ISR entry point 1377 * input: argument pointer 1378 * 1379 * This function is the interrupt service routine entry point. There are two 1380 * types of interrupts, state change interrupt and response interrupt. If an 1381 * interrupt is not ours, we just return. 1382 */ 1383 void 1384 mrsas_isr(void *arg) 1385 { 1386 struct mrsas_irq_context *irq_context = (struct mrsas_irq_context *)arg; 1387 struct mrsas_softc *sc = irq_context->sc; 1388 int status = 0; 1389 1390 if (!sc->msix_vectors) { 1391 status = mrsas_clear_intr(sc); 1392 if (!status) 1393 return; 1394 } 1395 /* If we are resetting, bail */ 1396 if (mrsas_test_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags)) { 1397 printf(" Entered into ISR when OCR is going active. \n"); 1398 mrsas_clear_intr(sc); 1399 return; 1400 } 1401 /* Process for reply request and clear response interrupt */ 1402 if (mrsas_complete_cmd(sc, irq_context->MSIxIndex) != SUCCESS) 1403 mrsas_clear_intr(sc); 1404 1405 return; 1406 } 1407 1408 /* 1409 * mrsas_complete_cmd: Process reply request 1410 * input: Adapter instance soft state 1411 * 1412 * This function is called from mrsas_isr() to process reply request and clear 1413 * response interrupt. Processing of the reply request entails walking 1414 * through the reply descriptor array for the command request pended from 1415 * Firmware. We look at the Function field to determine the command type and 1416 * perform the appropriate action. Before we return, we clear the response 1417 * interrupt. 1418 */ 1419 static int 1420 mrsas_complete_cmd(struct mrsas_softc *sc, u_int32_t MSIxIndex) 1421 { 1422 Mpi2ReplyDescriptorsUnion_t *desc; 1423 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR *reply_desc; 1424 MRSAS_RAID_SCSI_IO_REQUEST *scsi_io_req; 1425 struct mrsas_mpt_cmd *cmd_mpt; 1426 struct mrsas_mfi_cmd *cmd_mfi; 1427 u_int8_t arm, reply_descript_type; 1428 u_int16_t smid, num_completed; 1429 u_int8_t status, extStatus; 1430 union desc_value desc_val; 1431 PLD_LOAD_BALANCE_INFO lbinfo; 1432 u_int32_t device_id; 1433 int threshold_reply_count = 0; 1434 1435 1436 /* If we have a hardware error, not need to continue */ 1437 if (sc->adprecovery == MRSAS_HW_CRITICAL_ERROR) 1438 return (DONE); 1439 1440 desc = sc->reply_desc_mem; 1441 desc += ((MSIxIndex * sc->reply_alloc_sz) / sizeof(MPI2_REPLY_DESCRIPTORS_UNION)) 1442 + sc->last_reply_idx[MSIxIndex]; 1443 1444 reply_desc = (MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR *) desc; 1445 1446 desc_val.word = desc->Words; 1447 num_completed = 0; 1448 1449 reply_descript_type = reply_desc->ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 1450 1451 /* Find our reply descriptor for the command and process */ 1452 while ((desc_val.u.low != 0xFFFFFFFF) && (desc_val.u.high != 0xFFFFFFFF)) { 1453 smid = reply_desc->SMID; 1454 cmd_mpt = sc->mpt_cmd_list[smid - 1]; 1455 scsi_io_req = (MRSAS_RAID_SCSI_IO_REQUEST *) cmd_mpt->io_request; 1456 1457 status = scsi_io_req->RaidContext.status; 1458 extStatus = scsi_io_req->RaidContext.exStatus; 1459 1460 switch (scsi_io_req->Function) { 1461 case MPI2_FUNCTION_SCSI_IO_REQUEST: /* Fast Path IO. */ 1462 device_id = cmd_mpt->ccb_ptr->ccb_h.target_id; 1463 lbinfo = &sc->load_balance_info[device_id]; 1464 if (cmd_mpt->load_balance == MRSAS_LOAD_BALANCE_FLAG) { 1465 arm = lbinfo->raid1DevHandle[0] == scsi_io_req->DevHandle ? 0 : 1; 1466 mrsas_atomic_dec(&lbinfo->scsi_pending_cmds[arm]); 1467 cmd_mpt->load_balance &= ~MRSAS_LOAD_BALANCE_FLAG; 1468 } 1469 /* Fall thru and complete IO */ 1470 case MRSAS_MPI2_FUNCTION_LD_IO_REQUEST: 1471 mrsas_map_mpt_cmd_status(cmd_mpt, status, extStatus); 1472 mrsas_cmd_done(sc, cmd_mpt); 1473 scsi_io_req->RaidContext.status = 0; 1474 scsi_io_req->RaidContext.exStatus = 0; 1475 mrsas_atomic_dec(&sc->fw_outstanding); 1476 break; 1477 case MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST: /* MFI command */ 1478 cmd_mfi = sc->mfi_cmd_list[cmd_mpt->sync_cmd_idx]; 1479 mrsas_complete_mptmfi_passthru(sc, cmd_mfi, status); 1480 cmd_mpt->flags = 0; 1481 mrsas_release_mpt_cmd(cmd_mpt); 1482 break; 1483 } 1484 1485 sc->last_reply_idx[MSIxIndex]++; 1486 if (sc->last_reply_idx[MSIxIndex] >= sc->reply_q_depth) 1487 sc->last_reply_idx[MSIxIndex] = 0; 1488 1489 desc->Words = ~((uint64_t)0x00); /* set it back to all 1490 * 0xFFFFFFFFs */ 1491 num_completed++; 1492 threshold_reply_count++; 1493 1494 /* Get the next reply descriptor */ 1495 if (!sc->last_reply_idx[MSIxIndex]) { 1496 desc = sc->reply_desc_mem; 1497 desc += ((MSIxIndex * sc->reply_alloc_sz) / sizeof(MPI2_REPLY_DESCRIPTORS_UNION)); 1498 } else 1499 desc++; 1500 1501 reply_desc = (MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR *) desc; 1502 desc_val.word = desc->Words; 1503 1504 reply_descript_type = reply_desc->ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 1505 1506 if (reply_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) 1507 break; 1508 1509 /* 1510 * Write to reply post index after completing threshold reply 1511 * count and still there are more replies in reply queue 1512 * pending to be completed. 1513 */ 1514 if (threshold_reply_count >= THRESHOLD_REPLY_COUNT) { 1515 if (sc->msix_enable) { 1516 if ((sc->device_id == MRSAS_INVADER) || 1517 (sc->device_id == MRSAS_FURY)) 1518 mrsas_write_reg(sc, sc->msix_reg_offset[MSIxIndex / 8], 1519 ((MSIxIndex & 0x7) << 24) | 1520 sc->last_reply_idx[MSIxIndex]); 1521 else 1522 mrsas_write_reg(sc, sc->msix_reg_offset[0], (MSIxIndex << 24) | 1523 sc->last_reply_idx[MSIxIndex]); 1524 } else 1525 mrsas_write_reg(sc, offsetof(mrsas_reg_set, 1526 reply_post_host_index), sc->last_reply_idx[0]); 1527 1528 threshold_reply_count = 0; 1529 } 1530 } 1531 1532 /* No match, just return */ 1533 if (num_completed == 0) 1534 return (DONE); 1535 1536 /* Clear response interrupt */ 1537 if (sc->msix_enable) { 1538 if ((sc->device_id == MRSAS_INVADER) || 1539 (sc->device_id == MRSAS_FURY)) { 1540 mrsas_write_reg(sc, sc->msix_reg_offset[MSIxIndex / 8], 1541 ((MSIxIndex & 0x7) << 24) | 1542 sc->last_reply_idx[MSIxIndex]); 1543 } else 1544 mrsas_write_reg(sc, sc->msix_reg_offset[0], (MSIxIndex << 24) | 1545 sc->last_reply_idx[MSIxIndex]); 1546 } else 1547 mrsas_write_reg(sc, offsetof(mrsas_reg_set, 1548 reply_post_host_index), sc->last_reply_idx[0]); 1549 1550 return (0); 1551 } 1552 1553 /* 1554 * mrsas_map_mpt_cmd_status: Allocate DMAable memory. 1555 * input: Adapter instance soft state 1556 * 1557 * This function is called from mrsas_complete_cmd(), for LD IO and FastPath IO. 1558 * It checks the command status and maps the appropriate CAM status for the 1559 * CCB. 1560 */ 1561 void 1562 mrsas_map_mpt_cmd_status(struct mrsas_mpt_cmd *cmd, u_int8_t status, u_int8_t extStatus) 1563 { 1564 struct mrsas_softc *sc = cmd->sc; 1565 u_int8_t *sense_data; 1566 1567 switch (status) { 1568 case MFI_STAT_OK: 1569 cmd->ccb_ptr->ccb_h.status = CAM_REQ_CMP; 1570 break; 1571 case MFI_STAT_SCSI_IO_FAILED: 1572 case MFI_STAT_SCSI_DONE_WITH_ERROR: 1573 cmd->ccb_ptr->ccb_h.status = CAM_SCSI_STATUS_ERROR; 1574 sense_data = (u_int8_t *)&cmd->ccb_ptr->csio.sense_data; 1575 if (sense_data) { 1576 /* For now just copy 18 bytes back */ 1577 memcpy(sense_data, cmd->sense, 18); 1578 cmd->ccb_ptr->csio.sense_len = 18; 1579 cmd->ccb_ptr->ccb_h.status |= CAM_AUTOSNS_VALID; 1580 } 1581 break; 1582 case MFI_STAT_LD_OFFLINE: 1583 case MFI_STAT_DEVICE_NOT_FOUND: 1584 if (cmd->ccb_ptr->ccb_h.target_lun) 1585 cmd->ccb_ptr->ccb_h.status |= CAM_LUN_INVALID; 1586 else 1587 cmd->ccb_ptr->ccb_h.status |= CAM_DEV_NOT_THERE; 1588 break; 1589 case MFI_STAT_CONFIG_SEQ_MISMATCH: 1590 cmd->ccb_ptr->ccb_h.status |= CAM_REQUEUE_REQ; 1591 break; 1592 default: 1593 device_printf(sc->mrsas_dev, "FW cmd complete status %x\n", status); 1594 cmd->ccb_ptr->ccb_h.status = CAM_REQ_CMP_ERR; 1595 cmd->ccb_ptr->csio.scsi_status = status; 1596 } 1597 return; 1598 } 1599 1600 /* 1601 * mrsas_alloc_mem: Allocate DMAable memory 1602 * input: Adapter instance soft state 1603 * 1604 * This function creates the parent DMA tag and allocates DMAable memory. DMA 1605 * tag describes constraints of DMA mapping. Memory allocated is mapped into 1606 * Kernel virtual address. Callback argument is physical memory address. 1607 */ 1608 static int 1609 mrsas_alloc_mem(struct mrsas_softc *sc) 1610 { 1611 u_int32_t verbuf_size, io_req_size, reply_desc_size, sense_size, chain_frame_size, 1612 evt_detail_size, count; 1613 1614 /* 1615 * Allocate parent DMA tag 1616 */ 1617 if (bus_dma_tag_create(NULL, /* parent */ 1618 1, /* alignment */ 1619 0, /* boundary */ 1620 BUS_SPACE_MAXADDR, /* lowaddr */ 1621 BUS_SPACE_MAXADDR, /* highaddr */ 1622 NULL, NULL, /* filter, filterarg */ 1623 MRSAS_MAX_IO_SIZE, /* maxsize */ 1624 MRSAS_MAX_SGL, /* nsegments */ 1625 MRSAS_MAX_IO_SIZE, /* maxsegsize */ 1626 0, /* flags */ 1627 NULL, NULL, /* lockfunc, lockarg */ 1628 &sc->mrsas_parent_tag /* tag */ 1629 )) { 1630 device_printf(sc->mrsas_dev, "Cannot allocate parent DMA tag\n"); 1631 return (ENOMEM); 1632 } 1633 /* 1634 * Allocate for version buffer 1635 */ 1636 verbuf_size = MRSAS_MAX_NAME_LENGTH * (sizeof(bus_addr_t)); 1637 if (bus_dma_tag_create(sc->mrsas_parent_tag, 1638 1, 0, 1639 BUS_SPACE_MAXADDR_32BIT, 1640 BUS_SPACE_MAXADDR, 1641 NULL, NULL, 1642 verbuf_size, 1643 1, 1644 verbuf_size, 1645 BUS_DMA_ALLOCNOW, 1646 NULL, NULL, 1647 &sc->verbuf_tag)) { 1648 device_printf(sc->mrsas_dev, "Cannot allocate verbuf DMA tag\n"); 1649 return (ENOMEM); 1650 } 1651 if (bus_dmamem_alloc(sc->verbuf_tag, (void **)&sc->verbuf_mem, 1652 BUS_DMA_NOWAIT, &sc->verbuf_dmamap)) { 1653 device_printf(sc->mrsas_dev, "Cannot allocate verbuf memory\n"); 1654 return (ENOMEM); 1655 } 1656 bzero(sc->verbuf_mem, verbuf_size); 1657 if (bus_dmamap_load(sc->verbuf_tag, sc->verbuf_dmamap, sc->verbuf_mem, 1658 verbuf_size, mrsas_addr_cb, &sc->verbuf_phys_addr, 1659 BUS_DMA_NOWAIT)) { 1660 device_printf(sc->mrsas_dev, "Cannot load verbuf DMA map\n"); 1661 return (ENOMEM); 1662 } 1663 /* 1664 * Allocate IO Request Frames 1665 */ 1666 io_req_size = sc->io_frames_alloc_sz; 1667 if (bus_dma_tag_create(sc->mrsas_parent_tag, 1668 16, 0, 1669 BUS_SPACE_MAXADDR_32BIT, 1670 BUS_SPACE_MAXADDR, 1671 NULL, NULL, 1672 io_req_size, 1673 1, 1674 io_req_size, 1675 BUS_DMA_ALLOCNOW, 1676 NULL, NULL, 1677 &sc->io_request_tag)) { 1678 device_printf(sc->mrsas_dev, "Cannot create IO request tag\n"); 1679 return (ENOMEM); 1680 } 1681 if (bus_dmamem_alloc(sc->io_request_tag, (void **)&sc->io_request_mem, 1682 BUS_DMA_NOWAIT, &sc->io_request_dmamap)) { 1683 device_printf(sc->mrsas_dev, "Cannot alloc IO request memory\n"); 1684 return (ENOMEM); 1685 } 1686 bzero(sc->io_request_mem, io_req_size); 1687 if (bus_dmamap_load(sc->io_request_tag, sc->io_request_dmamap, 1688 sc->io_request_mem, io_req_size, mrsas_addr_cb, 1689 &sc->io_request_phys_addr, BUS_DMA_NOWAIT)) { 1690 device_printf(sc->mrsas_dev, "Cannot load IO request memory\n"); 1691 return (ENOMEM); 1692 } 1693 /* 1694 * Allocate Chain Frames 1695 */ 1696 chain_frame_size = sc->chain_frames_alloc_sz; 1697 if (bus_dma_tag_create(sc->mrsas_parent_tag, 1698 4, 0, 1699 BUS_SPACE_MAXADDR_32BIT, 1700 BUS_SPACE_MAXADDR, 1701 NULL, NULL, 1702 chain_frame_size, 1703 1, 1704 chain_frame_size, 1705 BUS_DMA_ALLOCNOW, 1706 NULL, NULL, 1707 &sc->chain_frame_tag)) { 1708 device_printf(sc->mrsas_dev, "Cannot create chain frame tag\n"); 1709 return (ENOMEM); 1710 } 1711 if (bus_dmamem_alloc(sc->chain_frame_tag, (void **)&sc->chain_frame_mem, 1712 BUS_DMA_NOWAIT, &sc->chain_frame_dmamap)) { 1713 device_printf(sc->mrsas_dev, "Cannot alloc chain frame memory\n"); 1714 return (ENOMEM); 1715 } 1716 bzero(sc->chain_frame_mem, chain_frame_size); 1717 if (bus_dmamap_load(sc->chain_frame_tag, sc->chain_frame_dmamap, 1718 sc->chain_frame_mem, chain_frame_size, mrsas_addr_cb, 1719 &sc->chain_frame_phys_addr, BUS_DMA_NOWAIT)) { 1720 device_printf(sc->mrsas_dev, "Cannot load chain frame memory\n"); 1721 return (ENOMEM); 1722 } 1723 count = sc->msix_vectors > 0 ? sc->msix_vectors : 1; 1724 /* 1725 * Allocate Reply Descriptor Array 1726 */ 1727 reply_desc_size = sc->reply_alloc_sz * count; 1728 if (bus_dma_tag_create(sc->mrsas_parent_tag, 1729 16, 0, 1730 BUS_SPACE_MAXADDR_32BIT, 1731 BUS_SPACE_MAXADDR, 1732 NULL, NULL, 1733 reply_desc_size, 1734 1, 1735 reply_desc_size, 1736 BUS_DMA_ALLOCNOW, 1737 NULL, NULL, 1738 &sc->reply_desc_tag)) { 1739 device_printf(sc->mrsas_dev, "Cannot create reply descriptor tag\n"); 1740 return (ENOMEM); 1741 } 1742 if (bus_dmamem_alloc(sc->reply_desc_tag, (void **)&sc->reply_desc_mem, 1743 BUS_DMA_NOWAIT, &sc->reply_desc_dmamap)) { 1744 device_printf(sc->mrsas_dev, "Cannot alloc reply descriptor memory\n"); 1745 return (ENOMEM); 1746 } 1747 if (bus_dmamap_load(sc->reply_desc_tag, sc->reply_desc_dmamap, 1748 sc->reply_desc_mem, reply_desc_size, mrsas_addr_cb, 1749 &sc->reply_desc_phys_addr, BUS_DMA_NOWAIT)) { 1750 device_printf(sc->mrsas_dev, "Cannot load reply descriptor memory\n"); 1751 return (ENOMEM); 1752 } 1753 /* 1754 * Allocate Sense Buffer Array. Keep in lower 4GB 1755 */ 1756 sense_size = sc->max_fw_cmds * MRSAS_SENSE_LEN; 1757 if (bus_dma_tag_create(sc->mrsas_parent_tag, 1758 64, 0, 1759 BUS_SPACE_MAXADDR_32BIT, 1760 BUS_SPACE_MAXADDR, 1761 NULL, NULL, 1762 sense_size, 1763 1, 1764 sense_size, 1765 BUS_DMA_ALLOCNOW, 1766 NULL, NULL, 1767 &sc->sense_tag)) { 1768 device_printf(sc->mrsas_dev, "Cannot allocate sense buf tag\n"); 1769 return (ENOMEM); 1770 } 1771 if (bus_dmamem_alloc(sc->sense_tag, (void **)&sc->sense_mem, 1772 BUS_DMA_NOWAIT, &sc->sense_dmamap)) { 1773 device_printf(sc->mrsas_dev, "Cannot allocate sense buf memory\n"); 1774 return (ENOMEM); 1775 } 1776 if (bus_dmamap_load(sc->sense_tag, sc->sense_dmamap, 1777 sc->sense_mem, sense_size, mrsas_addr_cb, &sc->sense_phys_addr, 1778 BUS_DMA_NOWAIT)) { 1779 device_printf(sc->mrsas_dev, "Cannot load sense buf memory\n"); 1780 return (ENOMEM); 1781 } 1782 /* 1783 * Allocate for Event detail structure 1784 */ 1785 evt_detail_size = sizeof(struct mrsas_evt_detail); 1786 if (bus_dma_tag_create(sc->mrsas_parent_tag, 1787 1, 0, 1788 BUS_SPACE_MAXADDR_32BIT, 1789 BUS_SPACE_MAXADDR, 1790 NULL, NULL, 1791 evt_detail_size, 1792 1, 1793 evt_detail_size, 1794 BUS_DMA_ALLOCNOW, 1795 NULL, NULL, 1796 &sc->evt_detail_tag)) { 1797 device_printf(sc->mrsas_dev, "Cannot create Event detail tag\n"); 1798 return (ENOMEM); 1799 } 1800 if (bus_dmamem_alloc(sc->evt_detail_tag, (void **)&sc->evt_detail_mem, 1801 BUS_DMA_NOWAIT, &sc->evt_detail_dmamap)) { 1802 device_printf(sc->mrsas_dev, "Cannot alloc Event detail buffer memory\n"); 1803 return (ENOMEM); 1804 } 1805 bzero(sc->evt_detail_mem, evt_detail_size); 1806 if (bus_dmamap_load(sc->evt_detail_tag, sc->evt_detail_dmamap, 1807 sc->evt_detail_mem, evt_detail_size, mrsas_addr_cb, 1808 &sc->evt_detail_phys_addr, BUS_DMA_NOWAIT)) { 1809 device_printf(sc->mrsas_dev, "Cannot load Event detail buffer memory\n"); 1810 return (ENOMEM); 1811 } 1812 /* 1813 * Create a dma tag for data buffers; size will be the maximum 1814 * possible I/O size (280kB). 1815 */ 1816 if (bus_dma_tag_create(sc->mrsas_parent_tag, 1817 1, 1818 0, 1819 BUS_SPACE_MAXADDR, 1820 BUS_SPACE_MAXADDR, 1821 NULL, NULL, 1822 MRSAS_MAX_IO_SIZE, 1823 MRSAS_MAX_SGL, 1824 MRSAS_MAX_IO_SIZE, 1825 BUS_DMA_ALLOCNOW, 1826 busdma_lock_mutex, 1827 &sc->io_lock, 1828 &sc->data_tag)) { 1829 device_printf(sc->mrsas_dev, "Cannot create data dma tag\n"); 1830 return (ENOMEM); 1831 } 1832 return (0); 1833 } 1834 1835 /* 1836 * mrsas_addr_cb: Callback function of bus_dmamap_load() 1837 * input: callback argument, machine dependent type 1838 * that describes DMA segments, number of segments, error code 1839 * 1840 * This function is for the driver to receive mapping information resultant of 1841 * the bus_dmamap_load(). The information is actually not being used, but the 1842 * address is saved anyway. 1843 */ 1844 void 1845 mrsas_addr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1846 { 1847 bus_addr_t *addr; 1848 1849 addr = arg; 1850 *addr = segs[0].ds_addr; 1851 } 1852 1853 /* 1854 * mrsas_setup_raidmap: Set up RAID map. 1855 * input: Adapter instance soft state 1856 * 1857 * Allocate DMA memory for the RAID maps and perform setup. 1858 */ 1859 static int 1860 mrsas_setup_raidmap(struct mrsas_softc *sc) 1861 { 1862 int i; 1863 1864 sc->drv_supported_vd_count = 1865 MRSAS_MAX_LD_CHANNELS * MRSAS_MAX_DEV_PER_CHANNEL; 1866 sc->drv_supported_pd_count = 1867 MRSAS_MAX_PD_CHANNELS * MRSAS_MAX_DEV_PER_CHANNEL; 1868 1869 if (sc->max256vdSupport) { 1870 sc->fw_supported_vd_count = MAX_LOGICAL_DRIVES_EXT; 1871 sc->fw_supported_pd_count = MAX_PHYSICAL_DEVICES; 1872 } else { 1873 sc->fw_supported_vd_count = MAX_LOGICAL_DRIVES; 1874 sc->fw_supported_pd_count = MAX_PHYSICAL_DEVICES; 1875 } 1876 1877 #if VD_EXT_DEBUG 1878 device_printf(sc->mrsas_dev, "FW supports: max256vdSupport = %s\n", 1879 sc->max256vdSupport ? "YES" : "NO"); 1880 device_printf(sc->mrsas_dev, "FW supports %dVDs %dPDs\n" 1881 "DRIVER supports %dVDs %dPDs \n", 1882 sc->fw_supported_vd_count, sc->fw_supported_pd_count, 1883 sc->drv_supported_vd_count, sc->drv_supported_pd_count); 1884 #endif 1885 1886 sc->old_map_sz = sizeof(MR_FW_RAID_MAP) + 1887 (sizeof(MR_LD_SPAN_MAP) * (sc->fw_supported_vd_count - 1)); 1888 sc->new_map_sz = sizeof(MR_FW_RAID_MAP_EXT); 1889 sc->drv_map_sz = sizeof(MR_DRV_RAID_MAP) + 1890 (sizeof(MR_LD_SPAN_MAP) * (sc->drv_supported_vd_count - 1)); 1891 1892 for (i = 0; i < 2; i++) { 1893 sc->ld_drv_map[i] = 1894 (void *)malloc(sc->drv_map_sz, M_MRSAS, M_NOWAIT); 1895 /* Do Error handling */ 1896 if (!sc->ld_drv_map[i]) { 1897 device_printf(sc->mrsas_dev, "Could not allocate memory for local map"); 1898 1899 if (i == 1) 1900 free(sc->ld_drv_map[0], M_MRSAS); 1901 /* ABORT driver initialization */ 1902 goto ABORT; 1903 } 1904 } 1905 1906 sc->max_map_sz = max(sc->old_map_sz, sc->new_map_sz); 1907 1908 if (sc->max256vdSupport) 1909 sc->current_map_sz = sc->new_map_sz; 1910 else 1911 sc->current_map_sz = sc->old_map_sz; 1912 1913 1914 for (int i = 0; i < 2; i++) { 1915 if (bus_dma_tag_create(sc->mrsas_parent_tag, 1916 4, 0, 1917 BUS_SPACE_MAXADDR_32BIT, 1918 BUS_SPACE_MAXADDR, 1919 NULL, NULL, 1920 sc->max_map_sz, 1921 1, 1922 sc->max_map_sz, 1923 BUS_DMA_ALLOCNOW, 1924 NULL, NULL, 1925 &sc->raidmap_tag[i])) { 1926 device_printf(sc->mrsas_dev, 1927 "Cannot allocate raid map tag.\n"); 1928 return (ENOMEM); 1929 } 1930 if (bus_dmamem_alloc(sc->raidmap_tag[i], 1931 (void **)&sc->raidmap_mem[i], 1932 BUS_DMA_NOWAIT, &sc->raidmap_dmamap[i])) { 1933 device_printf(sc->mrsas_dev, 1934 "Cannot allocate raidmap memory.\n"); 1935 return (ENOMEM); 1936 } 1937 bzero(sc->raidmap_mem[i], sc->max_map_sz); 1938 1939 if (bus_dmamap_load(sc->raidmap_tag[i], sc->raidmap_dmamap[i], 1940 sc->raidmap_mem[i], sc->max_map_sz, 1941 mrsas_addr_cb, &sc->raidmap_phys_addr[i], 1942 BUS_DMA_NOWAIT)) { 1943 device_printf(sc->mrsas_dev, "Cannot load raidmap memory.\n"); 1944 return (ENOMEM); 1945 } 1946 if (!sc->raidmap_mem[i]) { 1947 device_printf(sc->mrsas_dev, 1948 "Cannot allocate memory for raid map.\n"); 1949 return (ENOMEM); 1950 } 1951 } 1952 1953 if (!mrsas_get_map_info(sc)) 1954 mrsas_sync_map_info(sc); 1955 1956 return (0); 1957 1958 ABORT: 1959 return (1); 1960 } 1961 1962 /* 1963 * mrsas_init_fw: Initialize Firmware 1964 * input: Adapter soft state 1965 * 1966 * Calls transition_to_ready() to make sure Firmware is in operational state and 1967 * calls mrsas_init_adapter() to send IOC_INIT command to Firmware. It 1968 * issues internal commands to get the controller info after the IOC_INIT 1969 * command response is received by Firmware. Note: code relating to 1970 * get_pdlist, get_ld_list and max_sectors are currently not being used, it 1971 * is left here as placeholder. 1972 */ 1973 static int 1974 mrsas_init_fw(struct mrsas_softc *sc) 1975 { 1976 1977 int ret, loop, ocr = 0; 1978 u_int32_t max_sectors_1; 1979 u_int32_t max_sectors_2; 1980 u_int32_t tmp_sectors; 1981 struct mrsas_ctrl_info *ctrl_info; 1982 u_int32_t scratch_pad_2; 1983 int msix_enable = 0; 1984 int fw_msix_count = 0; 1985 1986 /* Make sure Firmware is ready */ 1987 ret = mrsas_transition_to_ready(sc, ocr); 1988 if (ret != SUCCESS) { 1989 return (ret); 1990 } 1991 /* MSI-x index 0- reply post host index register */ 1992 sc->msix_reg_offset[0] = MPI2_REPLY_POST_HOST_INDEX_OFFSET; 1993 /* Check if MSI-X is supported while in ready state */ 1994 msix_enable = (mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_scratch_pad)) & 0x4000000) >> 0x1a; 1995 1996 if (msix_enable) { 1997 scratch_pad_2 = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 1998 outbound_scratch_pad_2)); 1999 2000 /* Check max MSI-X vectors */ 2001 if (sc->device_id == MRSAS_TBOLT) { 2002 sc->msix_vectors = (scratch_pad_2 2003 & MR_MAX_REPLY_QUEUES_OFFSET) + 1; 2004 fw_msix_count = sc->msix_vectors; 2005 } else { 2006 /* Invader/Fury supports 96 MSI-X vectors */ 2007 sc->msix_vectors = ((scratch_pad_2 2008 & MR_MAX_REPLY_QUEUES_EXT_OFFSET) 2009 >> MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT) + 1; 2010 fw_msix_count = sc->msix_vectors; 2011 2012 for (loop = 1; loop < MR_MAX_MSIX_REG_ARRAY; 2013 loop++) { 2014 sc->msix_reg_offset[loop] = 2015 MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET + 2016 (loop * 0x10); 2017 } 2018 } 2019 2020 /* Don't bother allocating more MSI-X vectors than cpus */ 2021 sc->msix_vectors = min(sc->msix_vectors, 2022 mp_ncpus); 2023 2024 /* Allocate MSI-x vectors */ 2025 if (mrsas_allocate_msix(sc) == SUCCESS) 2026 sc->msix_enable = 1; 2027 else 2028 sc->msix_enable = 0; 2029 2030 device_printf(sc->mrsas_dev, "FW supports <%d> MSIX vector," 2031 "Online CPU %d Current MSIX <%d>\n", 2032 fw_msix_count, mp_ncpus, sc->msix_vectors); 2033 } 2034 if (mrsas_init_adapter(sc) != SUCCESS) { 2035 device_printf(sc->mrsas_dev, "Adapter initialize Fail.\n"); 2036 return (1); 2037 } 2038 /* Allocate internal commands for pass-thru */ 2039 if (mrsas_alloc_mfi_cmds(sc) != SUCCESS) { 2040 device_printf(sc->mrsas_dev, "Allocate MFI cmd failed.\n"); 2041 return (1); 2042 } 2043 /* 2044 * Get the controller info from FW, so that the MAX VD support 2045 * availability can be decided. 2046 */ 2047 ctrl_info = malloc(sizeof(struct mrsas_ctrl_info), M_MRSAS, M_NOWAIT); 2048 if (!ctrl_info) 2049 device_printf(sc->mrsas_dev, "Malloc for ctrl_info failed.\n"); 2050 2051 if (mrsas_get_ctrl_info(sc, ctrl_info)) { 2052 device_printf(sc->mrsas_dev, "Unable to get FW ctrl_info.\n"); 2053 } 2054 sc->max256vdSupport = 2055 (u_int8_t)ctrl_info->adapterOperations3.supportMaxExtLDs; 2056 2057 if (ctrl_info->max_lds > 64) { 2058 sc->max256vdSupport = 1; 2059 } 2060 if (mrsas_setup_raidmap(sc) != SUCCESS) { 2061 device_printf(sc->mrsas_dev, "Set up RAID map failed.\n"); 2062 return (1); 2063 } 2064 /* For pass-thru, get PD/LD list and controller info */ 2065 memset(sc->pd_list, 0, 2066 MRSAS_MAX_PD * sizeof(struct mrsas_pd_list)); 2067 mrsas_get_pd_list(sc); 2068 2069 memset(sc->ld_ids, 0xff, MRSAS_MAX_LD_IDS); 2070 mrsas_get_ld_list(sc); 2071 2072 /* 2073 * Compute the max allowed sectors per IO: The controller info has 2074 * two limits on max sectors. Driver should use the minimum of these 2075 * two. 2076 * 2077 * 1 << stripe_sz_ops.min = max sectors per strip 2078 * 2079 * Note that older firmwares ( < FW ver 30) didn't report information to 2080 * calculate max_sectors_1. So the number ended up as zero always. 2081 */ 2082 tmp_sectors = 0; 2083 max_sectors_1 = (1 << ctrl_info->stripe_sz_ops.min) * 2084 ctrl_info->max_strips_per_io; 2085 max_sectors_2 = ctrl_info->max_request_size; 2086 tmp_sectors = min(max_sectors_1, max_sectors_2); 2087 sc->max_sectors_per_req = sc->max_num_sge * MRSAS_PAGE_SIZE / 512; 2088 2089 if (tmp_sectors && (sc->max_sectors_per_req > tmp_sectors)) 2090 sc->max_sectors_per_req = tmp_sectors; 2091 2092 sc->disableOnlineCtrlReset = 2093 ctrl_info->properties.OnOffProperties.disableOnlineCtrlReset; 2094 sc->UnevenSpanSupport = 2095 ctrl_info->adapterOperations2.supportUnevenSpans; 2096 if (sc->UnevenSpanSupport) { 2097 device_printf(sc->mrsas_dev, "FW supports: UnevenSpanSupport=%x\n\n", 2098 sc->UnevenSpanSupport); 2099 2100 if (MR_ValidateMapInfo(sc)) 2101 sc->fast_path_io = 1; 2102 else 2103 sc->fast_path_io = 0; 2104 } 2105 if (ctrl_info) 2106 free(ctrl_info, M_MRSAS); 2107 2108 return (0); 2109 } 2110 2111 /* 2112 * mrsas_init_adapter: Initializes the adapter/controller 2113 * input: Adapter soft state 2114 * 2115 * Prepares for the issuing of the IOC Init cmd to FW for initializing the 2116 * ROC/controller. The FW register is read to determined the number of 2117 * commands that is supported. All memory allocations for IO is based on 2118 * max_cmd. Appropriate calculations are performed in this function. 2119 */ 2120 int 2121 mrsas_init_adapter(struct mrsas_softc *sc) 2122 { 2123 uint32_t status; 2124 u_int32_t max_cmd; 2125 int ret; 2126 int i = 0; 2127 2128 /* Read FW status register */ 2129 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_scratch_pad)); 2130 2131 /* Get operational params from status register */ 2132 sc->max_fw_cmds = status & MRSAS_FWSTATE_MAXCMD_MASK; 2133 2134 /* Decrement the max supported by 1, to correlate with FW */ 2135 sc->max_fw_cmds = sc->max_fw_cmds - 1; 2136 max_cmd = sc->max_fw_cmds; 2137 2138 /* Determine allocation size of command frames */ 2139 sc->reply_q_depth = ((max_cmd + 1 + 15) / 16 * 16); 2140 sc->request_alloc_sz = sizeof(MRSAS_REQUEST_DESCRIPTOR_UNION) * max_cmd; 2141 sc->reply_alloc_sz = sizeof(MPI2_REPLY_DESCRIPTORS_UNION) * (sc->reply_q_depth); 2142 sc->io_frames_alloc_sz = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE + (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * (max_cmd + 1)); 2143 sc->chain_frames_alloc_sz = 1024 * max_cmd; 2144 sc->max_sge_in_main_msg = (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE - 2145 offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL)) / 16; 2146 2147 sc->max_sge_in_chain = MRSAS_MAX_SZ_CHAIN_FRAME / sizeof(MPI2_SGE_IO_UNION); 2148 sc->max_num_sge = sc->max_sge_in_main_msg + sc->max_sge_in_chain - 2; 2149 2150 /* Used for pass thru MFI frame (DCMD) */ 2151 sc->chain_offset_mfi_pthru = offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL) / 16; 2152 2153 sc->chain_offset_io_request = (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE - 2154 sizeof(MPI2_SGE_IO_UNION)) / 16; 2155 2156 int count = sc->msix_vectors > 0 ? sc->msix_vectors : 1; 2157 2158 for (i = 0; i < count; i++) 2159 sc->last_reply_idx[i] = 0; 2160 2161 ret = mrsas_alloc_mem(sc); 2162 if (ret != SUCCESS) 2163 return (ret); 2164 2165 ret = mrsas_alloc_mpt_cmds(sc); 2166 if (ret != SUCCESS) 2167 return (ret); 2168 2169 ret = mrsas_ioc_init(sc); 2170 if (ret != SUCCESS) 2171 return (ret); 2172 2173 return (0); 2174 } 2175 2176 /* 2177 * mrsas_alloc_ioc_cmd: Allocates memory for IOC Init command 2178 * input: Adapter soft state 2179 * 2180 * Allocates for the IOC Init cmd to FW to initialize the ROC/controller. 2181 */ 2182 int 2183 mrsas_alloc_ioc_cmd(struct mrsas_softc *sc) 2184 { 2185 int ioc_init_size; 2186 2187 /* Allocate IOC INIT command */ 2188 ioc_init_size = 1024 + sizeof(MPI2_IOC_INIT_REQUEST); 2189 if (bus_dma_tag_create(sc->mrsas_parent_tag, 2190 1, 0, 2191 BUS_SPACE_MAXADDR_32BIT, 2192 BUS_SPACE_MAXADDR, 2193 NULL, NULL, 2194 ioc_init_size, 2195 1, 2196 ioc_init_size, 2197 BUS_DMA_ALLOCNOW, 2198 NULL, NULL, 2199 &sc->ioc_init_tag)) { 2200 device_printf(sc->mrsas_dev, "Cannot allocate ioc init tag\n"); 2201 return (ENOMEM); 2202 } 2203 if (bus_dmamem_alloc(sc->ioc_init_tag, (void **)&sc->ioc_init_mem, 2204 BUS_DMA_NOWAIT, &sc->ioc_init_dmamap)) { 2205 device_printf(sc->mrsas_dev, "Cannot allocate ioc init cmd mem\n"); 2206 return (ENOMEM); 2207 } 2208 bzero(sc->ioc_init_mem, ioc_init_size); 2209 if (bus_dmamap_load(sc->ioc_init_tag, sc->ioc_init_dmamap, 2210 sc->ioc_init_mem, ioc_init_size, mrsas_addr_cb, 2211 &sc->ioc_init_phys_mem, BUS_DMA_NOWAIT)) { 2212 device_printf(sc->mrsas_dev, "Cannot load ioc init cmd mem\n"); 2213 return (ENOMEM); 2214 } 2215 return (0); 2216 } 2217 2218 /* 2219 * mrsas_free_ioc_cmd: Allocates memory for IOC Init command 2220 * input: Adapter soft state 2221 * 2222 * Deallocates memory of the IOC Init cmd. 2223 */ 2224 void 2225 mrsas_free_ioc_cmd(struct mrsas_softc *sc) 2226 { 2227 if (sc->ioc_init_phys_mem) 2228 bus_dmamap_unload(sc->ioc_init_tag, sc->ioc_init_dmamap); 2229 if (sc->ioc_init_mem != NULL) 2230 bus_dmamem_free(sc->ioc_init_tag, sc->ioc_init_mem, sc->ioc_init_dmamap); 2231 if (sc->ioc_init_tag != NULL) 2232 bus_dma_tag_destroy(sc->ioc_init_tag); 2233 } 2234 2235 /* 2236 * mrsas_ioc_init: Sends IOC Init command to FW 2237 * input: Adapter soft state 2238 * 2239 * Issues the IOC Init cmd to FW to initialize the ROC/controller. 2240 */ 2241 int 2242 mrsas_ioc_init(struct mrsas_softc *sc) 2243 { 2244 struct mrsas_init_frame *init_frame; 2245 pMpi2IOCInitRequest_t IOCInitMsg; 2246 MRSAS_REQUEST_DESCRIPTOR_UNION req_desc; 2247 u_int8_t max_wait = MRSAS_IOC_INIT_WAIT_TIME; 2248 bus_addr_t phys_addr; 2249 int i, retcode = 0; 2250 2251 /* Allocate memory for the IOC INIT command */ 2252 if (mrsas_alloc_ioc_cmd(sc)) { 2253 device_printf(sc->mrsas_dev, "Cannot allocate IOC command.\n"); 2254 return (1); 2255 } 2256 IOCInitMsg = (pMpi2IOCInitRequest_t)(((char *)sc->ioc_init_mem) + 1024); 2257 IOCInitMsg->Function = MPI2_FUNCTION_IOC_INIT; 2258 IOCInitMsg->WhoInit = MPI2_WHOINIT_HOST_DRIVER; 2259 IOCInitMsg->MsgVersion = MPI2_VERSION; 2260 IOCInitMsg->HeaderVersion = MPI2_HEADER_VERSION; 2261 IOCInitMsg->SystemRequestFrameSize = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE / 4; 2262 IOCInitMsg->ReplyDescriptorPostQueueDepth = sc->reply_q_depth; 2263 IOCInitMsg->ReplyDescriptorPostQueueAddress = sc->reply_desc_phys_addr; 2264 IOCInitMsg->SystemRequestFrameBaseAddress = sc->io_request_phys_addr; 2265 IOCInitMsg->HostMSIxVectors = (sc->msix_vectors > 0 ? sc->msix_vectors : 0); 2266 2267 init_frame = (struct mrsas_init_frame *)sc->ioc_init_mem; 2268 init_frame->cmd = MFI_CMD_INIT; 2269 init_frame->cmd_status = 0xFF; 2270 init_frame->flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE; 2271 2272 /* driver support Extended MSIX */ 2273 if ((sc->device_id == MRSAS_INVADER) || 2274 (sc->device_id == MRSAS_FURY)) { 2275 init_frame->driver_operations. 2276 mfi_capabilities.support_additional_msix = 1; 2277 } 2278 if (sc->verbuf_mem) { 2279 snprintf((char *)sc->verbuf_mem, strlen(MRSAS_VERSION) + 2, "%s\n", 2280 MRSAS_VERSION); 2281 init_frame->driver_ver_lo = (bus_addr_t)sc->verbuf_phys_addr; 2282 init_frame->driver_ver_hi = 0; 2283 } 2284 init_frame->driver_operations.mfi_capabilities.support_max_255lds = 1; 2285 phys_addr = (bus_addr_t)sc->ioc_init_phys_mem + 1024; 2286 init_frame->queue_info_new_phys_addr_lo = phys_addr; 2287 init_frame->data_xfer_len = sizeof(Mpi2IOCInitRequest_t); 2288 2289 req_desc.addr.Words = (bus_addr_t)sc->ioc_init_phys_mem; 2290 req_desc.MFAIo.RequestFlags = 2291 (MRSAS_REQ_DESCRIPT_FLAGS_MFA << MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT); 2292 2293 mrsas_disable_intr(sc); 2294 mrsas_dprint(sc, MRSAS_OCR, "Issuing IOC INIT command to FW.\n"); 2295 mrsas_fire_cmd(sc, req_desc.addr.u.low, req_desc.addr.u.high); 2296 2297 /* 2298 * Poll response timer to wait for Firmware response. While this 2299 * timer with the DELAY call could block CPU, the time interval for 2300 * this is only 1 millisecond. 2301 */ 2302 if (init_frame->cmd_status == 0xFF) { 2303 for (i = 0; i < (max_wait * 1000); i++) { 2304 if (init_frame->cmd_status == 0xFF) 2305 DELAY(1000); 2306 else 2307 break; 2308 } 2309 } 2310 if (init_frame->cmd_status == 0) 2311 mrsas_dprint(sc, MRSAS_OCR, 2312 "IOC INIT response received from FW.\n"); 2313 else { 2314 if (init_frame->cmd_status == 0xFF) 2315 device_printf(sc->mrsas_dev, "IOC Init timed out after %d seconds.\n", max_wait); 2316 else 2317 device_printf(sc->mrsas_dev, "IOC Init failed, status = 0x%x\n", init_frame->cmd_status); 2318 retcode = 1; 2319 } 2320 2321 mrsas_free_ioc_cmd(sc); 2322 return (retcode); 2323 } 2324 2325 /* 2326 * mrsas_alloc_mpt_cmds: Allocates the command packets 2327 * input: Adapter instance soft state 2328 * 2329 * This function allocates the internal commands for IOs. Each command that is 2330 * issued to FW is wrapped in a local data structure called mrsas_mpt_cmd. An 2331 * array is allocated with mrsas_mpt_cmd context. The free commands are 2332 * maintained in a linked list (cmd pool). SMID value range is from 1 to 2333 * max_fw_cmds. 2334 */ 2335 int 2336 mrsas_alloc_mpt_cmds(struct mrsas_softc *sc) 2337 { 2338 int i, j; 2339 u_int32_t max_cmd, count; 2340 struct mrsas_mpt_cmd *cmd; 2341 pMpi2ReplyDescriptorsUnion_t reply_desc; 2342 u_int32_t offset, chain_offset, sense_offset; 2343 bus_addr_t io_req_base_phys, chain_frame_base_phys, sense_base_phys; 2344 u_int8_t *io_req_base, *chain_frame_base, *sense_base; 2345 2346 max_cmd = sc->max_fw_cmds; 2347 2348 sc->req_desc = malloc(sc->request_alloc_sz, M_MRSAS, M_NOWAIT); 2349 if (!sc->req_desc) { 2350 device_printf(sc->mrsas_dev, "Out of memory, cannot alloc req desc\n"); 2351 return (ENOMEM); 2352 } 2353 memset(sc->req_desc, 0, sc->request_alloc_sz); 2354 2355 /* 2356 * sc->mpt_cmd_list is an array of struct mrsas_mpt_cmd pointers. 2357 * Allocate the dynamic array first and then allocate individual 2358 * commands. 2359 */ 2360 sc->mpt_cmd_list = malloc(sizeof(struct mrsas_mpt_cmd *) * max_cmd, M_MRSAS, M_NOWAIT); 2361 if (!sc->mpt_cmd_list) { 2362 device_printf(sc->mrsas_dev, "Cannot alloc memory for mpt_cmd_list.\n"); 2363 return (ENOMEM); 2364 } 2365 memset(sc->mpt_cmd_list, 0, sizeof(struct mrsas_mpt_cmd *) * max_cmd); 2366 for (i = 0; i < max_cmd; i++) { 2367 sc->mpt_cmd_list[i] = malloc(sizeof(struct mrsas_mpt_cmd), 2368 M_MRSAS, M_NOWAIT); 2369 if (!sc->mpt_cmd_list[i]) { 2370 for (j = 0; j < i; j++) 2371 free(sc->mpt_cmd_list[j], M_MRSAS); 2372 free(sc->mpt_cmd_list, M_MRSAS); 2373 sc->mpt_cmd_list = NULL; 2374 return (ENOMEM); 2375 } 2376 } 2377 2378 io_req_base = (u_int8_t *)sc->io_request_mem + MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE; 2379 io_req_base_phys = (bus_addr_t)sc->io_request_phys_addr + MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE; 2380 chain_frame_base = (u_int8_t *)sc->chain_frame_mem; 2381 chain_frame_base_phys = (bus_addr_t)sc->chain_frame_phys_addr; 2382 sense_base = (u_int8_t *)sc->sense_mem; 2383 sense_base_phys = (bus_addr_t)sc->sense_phys_addr; 2384 for (i = 0; i < max_cmd; i++) { 2385 cmd = sc->mpt_cmd_list[i]; 2386 offset = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * i; 2387 chain_offset = 1024 * i; 2388 sense_offset = MRSAS_SENSE_LEN * i; 2389 memset(cmd, 0, sizeof(struct mrsas_mpt_cmd)); 2390 cmd->index = i + 1; 2391 cmd->ccb_ptr = NULL; 2392 callout_init(&cmd->cm_callout, 0); 2393 cmd->sync_cmd_idx = (u_int32_t)MRSAS_ULONG_MAX; 2394 cmd->sc = sc; 2395 cmd->io_request = (MRSAS_RAID_SCSI_IO_REQUEST *) (io_req_base + offset); 2396 memset(cmd->io_request, 0, sizeof(MRSAS_RAID_SCSI_IO_REQUEST)); 2397 cmd->io_request_phys_addr = io_req_base_phys + offset; 2398 cmd->chain_frame = (MPI2_SGE_IO_UNION *) (chain_frame_base + chain_offset); 2399 cmd->chain_frame_phys_addr = chain_frame_base_phys + chain_offset; 2400 cmd->sense = sense_base + sense_offset; 2401 cmd->sense_phys_addr = sense_base_phys + sense_offset; 2402 if (bus_dmamap_create(sc->data_tag, 0, &cmd->data_dmamap)) { 2403 return (FAIL); 2404 } 2405 TAILQ_INSERT_TAIL(&(sc->mrsas_mpt_cmd_list_head), cmd, next); 2406 } 2407 2408 /* Initialize reply descriptor array to 0xFFFFFFFF */ 2409 reply_desc = sc->reply_desc_mem; 2410 count = sc->msix_vectors > 0 ? sc->msix_vectors : 1; 2411 for (i = 0; i < sc->reply_q_depth * count; i++, reply_desc++) { 2412 reply_desc->Words = MRSAS_ULONG_MAX; 2413 } 2414 return (0); 2415 } 2416 2417 /* 2418 * mrsas_fire_cmd: Sends command to FW 2419 * input: Adapter softstate 2420 * request descriptor address low 2421 * request descriptor address high 2422 * 2423 * This functions fires the command to Firmware by writing to the 2424 * inbound_low_queue_port and inbound_high_queue_port. 2425 */ 2426 void 2427 mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo, 2428 u_int32_t req_desc_hi) 2429 { 2430 mtx_lock(&sc->pci_lock); 2431 mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_low_queue_port), 2432 req_desc_lo); 2433 mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_high_queue_port), 2434 req_desc_hi); 2435 mtx_unlock(&sc->pci_lock); 2436 } 2437 2438 /* 2439 * mrsas_transition_to_ready: Move FW to Ready state input: 2440 * Adapter instance soft state 2441 * 2442 * During the initialization, FW passes can potentially be in any one of several 2443 * possible states. If the FW in operational, waiting-for-handshake states, 2444 * driver must take steps to bring it to ready state. Otherwise, it has to 2445 * wait for the ready state. 2446 */ 2447 int 2448 mrsas_transition_to_ready(struct mrsas_softc *sc, int ocr) 2449 { 2450 int i; 2451 u_int8_t max_wait; 2452 u_int32_t val, fw_state; 2453 u_int32_t cur_state; 2454 u_int32_t abs_state, curr_abs_state; 2455 2456 val = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_scratch_pad)); 2457 fw_state = val & MFI_STATE_MASK; 2458 max_wait = MRSAS_RESET_WAIT_TIME; 2459 2460 if (fw_state != MFI_STATE_READY) 2461 device_printf(sc->mrsas_dev, "Waiting for FW to come to ready state\n"); 2462 2463 while (fw_state != MFI_STATE_READY) { 2464 abs_state = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_scratch_pad)); 2465 switch (fw_state) { 2466 case MFI_STATE_FAULT: 2467 device_printf(sc->mrsas_dev, "FW is in FAULT state!!\n"); 2468 if (ocr) { 2469 cur_state = MFI_STATE_FAULT; 2470 break; 2471 } else 2472 return -ENODEV; 2473 case MFI_STATE_WAIT_HANDSHAKE: 2474 /* Set the CLR bit in inbound doorbell */ 2475 mrsas_write_reg(sc, offsetof(mrsas_reg_set, doorbell), 2476 MFI_INIT_CLEAR_HANDSHAKE | MFI_INIT_HOTPLUG); 2477 cur_state = MFI_STATE_WAIT_HANDSHAKE; 2478 break; 2479 case MFI_STATE_BOOT_MESSAGE_PENDING: 2480 mrsas_write_reg(sc, offsetof(mrsas_reg_set, doorbell), 2481 MFI_INIT_HOTPLUG); 2482 cur_state = MFI_STATE_BOOT_MESSAGE_PENDING; 2483 break; 2484 case MFI_STATE_OPERATIONAL: 2485 /* 2486 * Bring it to READY state; assuming max wait 10 2487 * secs 2488 */ 2489 mrsas_disable_intr(sc); 2490 mrsas_write_reg(sc, offsetof(mrsas_reg_set, doorbell), MFI_RESET_FLAGS); 2491 for (i = 0; i < max_wait * 1000; i++) { 2492 if (mrsas_read_reg(sc, offsetof(mrsas_reg_set, doorbell)) & 1) 2493 DELAY(1000); 2494 else 2495 break; 2496 } 2497 cur_state = MFI_STATE_OPERATIONAL; 2498 break; 2499 case MFI_STATE_UNDEFINED: 2500 /* 2501 * This state should not last for more than 2 2502 * seconds 2503 */ 2504 cur_state = MFI_STATE_UNDEFINED; 2505 break; 2506 case MFI_STATE_BB_INIT: 2507 cur_state = MFI_STATE_BB_INIT; 2508 break; 2509 case MFI_STATE_FW_INIT: 2510 cur_state = MFI_STATE_FW_INIT; 2511 break; 2512 case MFI_STATE_FW_INIT_2: 2513 cur_state = MFI_STATE_FW_INIT_2; 2514 break; 2515 case MFI_STATE_DEVICE_SCAN: 2516 cur_state = MFI_STATE_DEVICE_SCAN; 2517 break; 2518 case MFI_STATE_FLUSH_CACHE: 2519 cur_state = MFI_STATE_FLUSH_CACHE; 2520 break; 2521 default: 2522 device_printf(sc->mrsas_dev, "Unknown state 0x%x\n", fw_state); 2523 return -ENODEV; 2524 } 2525 2526 /* 2527 * The cur_state should not last for more than max_wait secs 2528 */ 2529 for (i = 0; i < (max_wait * 1000); i++) { 2530 fw_state = (mrsas_read_reg(sc, offsetof(mrsas_reg_set, 2531 outbound_scratch_pad)) & MFI_STATE_MASK); 2532 curr_abs_state = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 2533 outbound_scratch_pad)); 2534 if (abs_state == curr_abs_state) 2535 DELAY(1000); 2536 else 2537 break; 2538 } 2539 2540 /* 2541 * Return error if fw_state hasn't changed after max_wait 2542 */ 2543 if (curr_abs_state == abs_state) { 2544 device_printf(sc->mrsas_dev, "FW state [%d] hasn't changed " 2545 "in %d secs\n", fw_state, max_wait); 2546 return -ENODEV; 2547 } 2548 } 2549 mrsas_dprint(sc, MRSAS_OCR, "FW now in Ready state\n"); 2550 return 0; 2551 } 2552 2553 /* 2554 * mrsas_get_mfi_cmd: Get a cmd from free command pool 2555 * input: Adapter soft state 2556 * 2557 * This function removes an MFI command from the command list. 2558 */ 2559 struct mrsas_mfi_cmd * 2560 mrsas_get_mfi_cmd(struct mrsas_softc *sc) 2561 { 2562 struct mrsas_mfi_cmd *cmd = NULL; 2563 2564 mtx_lock(&sc->mfi_cmd_pool_lock); 2565 if (!TAILQ_EMPTY(&sc->mrsas_mfi_cmd_list_head)) { 2566 cmd = TAILQ_FIRST(&sc->mrsas_mfi_cmd_list_head); 2567 TAILQ_REMOVE(&sc->mrsas_mfi_cmd_list_head, cmd, next); 2568 } 2569 mtx_unlock(&sc->mfi_cmd_pool_lock); 2570 2571 return cmd; 2572 } 2573 2574 /* 2575 * mrsas_ocr_thread: Thread to handle OCR/Kill Adapter. 2576 * input: Adapter Context. 2577 * 2578 * This function will check FW status register and flag do_timeout_reset flag. 2579 * It will do OCR/Kill adapter if FW is in fault state or IO timed out has 2580 * trigger reset. 2581 */ 2582 static void 2583 mrsas_ocr_thread(void *arg) 2584 { 2585 struct mrsas_softc *sc; 2586 u_int32_t fw_status, fw_state; 2587 2588 sc = (struct mrsas_softc *)arg; 2589 2590 mrsas_dprint(sc, MRSAS_TRACE, "%s\n", __func__); 2591 2592 sc->ocr_thread_active = 1; 2593 mtx_lock(&sc->sim_lock); 2594 for (;;) { 2595 /* Sleep for 1 second and check the queue status */ 2596 msleep(&sc->ocr_chan, &sc->sim_lock, PRIBIO, 2597 "mrsas_ocr", sc->mrsas_fw_fault_check_delay * hz); 2598 if (sc->remove_in_progress) { 2599 mrsas_dprint(sc, MRSAS_OCR, 2600 "Exit due to shutdown from %s\n", __func__); 2601 break; 2602 } 2603 fw_status = mrsas_read_reg(sc, 2604 offsetof(mrsas_reg_set, outbound_scratch_pad)); 2605 fw_state = fw_status & MFI_STATE_MASK; 2606 if (fw_state == MFI_STATE_FAULT || sc->do_timedout_reset) { 2607 device_printf(sc->mrsas_dev, "OCR started due to %s!\n", 2608 sc->do_timedout_reset ? "IO Timeout" : 2609 "FW fault detected"); 2610 mtx_lock_spin(&sc->ioctl_lock); 2611 sc->reset_in_progress = 1; 2612 sc->reset_count++; 2613 mtx_unlock_spin(&sc->ioctl_lock); 2614 mrsas_xpt_freeze(sc); 2615 mrsas_reset_ctrl(sc); 2616 mrsas_xpt_release(sc); 2617 sc->reset_in_progress = 0; 2618 sc->do_timedout_reset = 0; 2619 } 2620 } 2621 mtx_unlock(&sc->sim_lock); 2622 sc->ocr_thread_active = 0; 2623 mrsas_kproc_exit(0); 2624 } 2625 2626 /* 2627 * mrsas_reset_reply_desc: Reset Reply descriptor as part of OCR. 2628 * input: Adapter Context. 2629 * 2630 * This function will clear reply descriptor so that post OCR driver and FW will 2631 * lost old history. 2632 */ 2633 void 2634 mrsas_reset_reply_desc(struct mrsas_softc *sc) 2635 { 2636 int i, count; 2637 pMpi2ReplyDescriptorsUnion_t reply_desc; 2638 2639 count = sc->msix_vectors > 0 ? sc->msix_vectors : 1; 2640 for (i = 0; i < count; i++) 2641 sc->last_reply_idx[i] = 0; 2642 2643 reply_desc = sc->reply_desc_mem; 2644 for (i = 0; i < sc->reply_q_depth; i++, reply_desc++) { 2645 reply_desc->Words = MRSAS_ULONG_MAX; 2646 } 2647 } 2648 2649 /* 2650 * mrsas_reset_ctrl: Core function to OCR/Kill adapter. 2651 * input: Adapter Context. 2652 * 2653 * This function will run from thread context so that it can sleep. 1. Do not 2654 * handle OCR if FW is in HW critical error. 2. Wait for outstanding command 2655 * to complete for 180 seconds. 3. If #2 does not find any outstanding 2656 * command Controller is in working state, so skip OCR. Otherwise, do 2657 * OCR/kill Adapter based on flag disableOnlineCtrlReset. 4. Start of the 2658 * OCR, return all SCSI command back to CAM layer which has ccb_ptr. 5. Post 2659 * OCR, Re-fire Managment command and move Controller to Operation state. 2660 */ 2661 int 2662 mrsas_reset_ctrl(struct mrsas_softc *sc) 2663 { 2664 int retval = SUCCESS, i, j, retry = 0; 2665 u_int32_t host_diag, abs_state, status_reg, reset_adapter; 2666 union ccb *ccb; 2667 struct mrsas_mfi_cmd *mfi_cmd; 2668 struct mrsas_mpt_cmd *mpt_cmd; 2669 MRSAS_REQUEST_DESCRIPTOR_UNION *req_desc; 2670 2671 if (sc->adprecovery == MRSAS_HW_CRITICAL_ERROR) { 2672 device_printf(sc->mrsas_dev, 2673 "mrsas: Hardware critical error, returning FAIL.\n"); 2674 return FAIL; 2675 } 2676 mrsas_set_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags); 2677 sc->adprecovery = MRSAS_ADPRESET_SM_INFAULT; 2678 mrsas_disable_intr(sc); 2679 DELAY(1000 * 1000); 2680 2681 /* First try waiting for commands to complete */ 2682 if (mrsas_wait_for_outstanding(sc)) { 2683 mrsas_dprint(sc, MRSAS_OCR, 2684 "resetting adapter from %s.\n", 2685 __func__); 2686 /* Now return commands back to the CAM layer */ 2687 for (i = 0; i < sc->max_fw_cmds; i++) { 2688 mpt_cmd = sc->mpt_cmd_list[i]; 2689 if (mpt_cmd->ccb_ptr) { 2690 ccb = (union ccb *)(mpt_cmd->ccb_ptr); 2691 ccb->ccb_h.status = CAM_SCSI_BUS_RESET; 2692 mrsas_cmd_done(sc, mpt_cmd); 2693 mrsas_atomic_dec(&sc->fw_outstanding); 2694 } 2695 } 2696 2697 status_reg = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 2698 outbound_scratch_pad)); 2699 abs_state = status_reg & MFI_STATE_MASK; 2700 reset_adapter = status_reg & MFI_RESET_ADAPTER; 2701 if (sc->disableOnlineCtrlReset || 2702 (abs_state == MFI_STATE_FAULT && !reset_adapter)) { 2703 /* Reset not supported, kill adapter */ 2704 mrsas_dprint(sc, MRSAS_OCR, "Reset not supported, killing adapter.\n"); 2705 mrsas_kill_hba(sc); 2706 sc->adprecovery = MRSAS_HW_CRITICAL_ERROR; 2707 retval = FAIL; 2708 goto out; 2709 } 2710 /* Now try to reset the chip */ 2711 for (i = 0; i < MRSAS_FUSION_MAX_RESET_TRIES; i++) { 2712 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 2713 MPI2_WRSEQ_FLUSH_KEY_VALUE); 2714 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 2715 MPI2_WRSEQ_1ST_KEY_VALUE); 2716 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 2717 MPI2_WRSEQ_2ND_KEY_VALUE); 2718 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 2719 MPI2_WRSEQ_3RD_KEY_VALUE); 2720 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 2721 MPI2_WRSEQ_4TH_KEY_VALUE); 2722 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 2723 MPI2_WRSEQ_5TH_KEY_VALUE); 2724 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 2725 MPI2_WRSEQ_6TH_KEY_VALUE); 2726 2727 /* Check that the diag write enable (DRWE) bit is on */ 2728 host_diag = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 2729 fusion_host_diag)); 2730 retry = 0; 2731 while (!(host_diag & HOST_DIAG_WRITE_ENABLE)) { 2732 DELAY(100 * 1000); 2733 host_diag = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 2734 fusion_host_diag)); 2735 if (retry++ == 100) { 2736 mrsas_dprint(sc, MRSAS_OCR, 2737 "Host diag unlock failed!\n"); 2738 break; 2739 } 2740 } 2741 if (!(host_diag & HOST_DIAG_WRITE_ENABLE)) 2742 continue; 2743 2744 /* Send chip reset command */ 2745 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_host_diag), 2746 host_diag | HOST_DIAG_RESET_ADAPTER); 2747 DELAY(3000 * 1000); 2748 2749 /* Make sure reset adapter bit is cleared */ 2750 host_diag = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 2751 fusion_host_diag)); 2752 retry = 0; 2753 while (host_diag & HOST_DIAG_RESET_ADAPTER) { 2754 DELAY(100 * 1000); 2755 host_diag = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 2756 fusion_host_diag)); 2757 if (retry++ == 1000) { 2758 mrsas_dprint(sc, MRSAS_OCR, 2759 "Diag reset adapter never cleared!\n"); 2760 break; 2761 } 2762 } 2763 if (host_diag & HOST_DIAG_RESET_ADAPTER) 2764 continue; 2765 2766 abs_state = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 2767 outbound_scratch_pad)) & MFI_STATE_MASK; 2768 retry = 0; 2769 2770 while ((abs_state <= MFI_STATE_FW_INIT) && (retry++ < 1000)) { 2771 DELAY(100 * 1000); 2772 abs_state = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 2773 outbound_scratch_pad)) & MFI_STATE_MASK; 2774 } 2775 if (abs_state <= MFI_STATE_FW_INIT) { 2776 mrsas_dprint(sc, MRSAS_OCR, "firmware state < MFI_STATE_FW_INIT," 2777 " state = 0x%x\n", abs_state); 2778 continue; 2779 } 2780 /* Wait for FW to become ready */ 2781 if (mrsas_transition_to_ready(sc, 1)) { 2782 mrsas_dprint(sc, MRSAS_OCR, 2783 "mrsas: Failed to transition controller to ready.\n"); 2784 continue; 2785 } 2786 mrsas_reset_reply_desc(sc); 2787 if (mrsas_ioc_init(sc)) { 2788 mrsas_dprint(sc, MRSAS_OCR, "mrsas_ioc_init() failed!\n"); 2789 continue; 2790 } 2791 mrsas_clear_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags); 2792 mrsas_enable_intr(sc); 2793 sc->adprecovery = MRSAS_HBA_OPERATIONAL; 2794 2795 /* Re-fire management commands */ 2796 for (j = 0; j < sc->max_fw_cmds; j++) { 2797 mpt_cmd = sc->mpt_cmd_list[j]; 2798 if (mpt_cmd->sync_cmd_idx != (u_int32_t)MRSAS_ULONG_MAX) { 2799 mfi_cmd = sc->mfi_cmd_list[mpt_cmd->sync_cmd_idx]; 2800 if (mfi_cmd->frame->dcmd.opcode == 2801 MR_DCMD_LD_MAP_GET_INFO) { 2802 mrsas_release_mfi_cmd(mfi_cmd); 2803 mrsas_release_mpt_cmd(mpt_cmd); 2804 } else { 2805 req_desc = mrsas_get_request_desc(sc, 2806 mfi_cmd->cmd_id.context.smid - 1); 2807 mrsas_dprint(sc, MRSAS_OCR, 2808 "Re-fire command DCMD opcode 0x%x index %d\n ", 2809 mfi_cmd->frame->dcmd.opcode, j); 2810 if (!req_desc) 2811 device_printf(sc->mrsas_dev, 2812 "Cannot build MPT cmd.\n"); 2813 else 2814 mrsas_fire_cmd(sc, req_desc->addr.u.low, 2815 req_desc->addr.u.high); 2816 } 2817 } 2818 } 2819 2820 /* Reset load balance info */ 2821 memset(sc->load_balance_info, 0, 2822 sizeof(LD_LOAD_BALANCE_INFO) * MAX_LOGICAL_DRIVES_EXT); 2823 2824 if (!mrsas_get_map_info(sc)) 2825 mrsas_sync_map_info(sc); 2826 2827 /* Adapter reset completed successfully */ 2828 device_printf(sc->mrsas_dev, "Reset successful\n"); 2829 retval = SUCCESS; 2830 goto out; 2831 } 2832 /* Reset failed, kill the adapter */ 2833 device_printf(sc->mrsas_dev, "Reset failed, killing adapter.\n"); 2834 mrsas_kill_hba(sc); 2835 retval = FAIL; 2836 } else { 2837 mrsas_clear_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags); 2838 mrsas_enable_intr(sc); 2839 sc->adprecovery = MRSAS_HBA_OPERATIONAL; 2840 } 2841 out: 2842 mrsas_clear_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags); 2843 mrsas_dprint(sc, MRSAS_OCR, 2844 "Reset Exit with %d.\n", retval); 2845 return retval; 2846 } 2847 2848 /* 2849 * mrsas_kill_hba: Kill HBA when OCR is not supported 2850 * input: Adapter Context. 2851 * 2852 * This function will kill HBA when OCR is not supported. 2853 */ 2854 void 2855 mrsas_kill_hba(struct mrsas_softc *sc) 2856 { 2857 mrsas_dprint(sc, MRSAS_OCR, "%s\n", __func__); 2858 mrsas_write_reg(sc, offsetof(mrsas_reg_set, doorbell), 2859 MFI_STOP_ADP); 2860 /* Flush */ 2861 mrsas_read_reg(sc, offsetof(mrsas_reg_set, doorbell)); 2862 } 2863 2864 /* 2865 * mrsas_wait_for_outstanding: Wait for outstanding commands 2866 * input: Adapter Context. 2867 * 2868 * This function will wait for 180 seconds for outstanding commands to be 2869 * completed. 2870 */ 2871 int 2872 mrsas_wait_for_outstanding(struct mrsas_softc *sc) 2873 { 2874 int i, outstanding, retval = 0; 2875 u_int32_t fw_state, count, MSIxIndex; 2876 2877 2878 for (i = 0; i < MRSAS_RESET_WAIT_TIME; i++) { 2879 if (sc->remove_in_progress) { 2880 mrsas_dprint(sc, MRSAS_OCR, 2881 "Driver remove or shutdown called.\n"); 2882 retval = 1; 2883 goto out; 2884 } 2885 /* Check if firmware is in fault state */ 2886 fw_state = mrsas_read_reg(sc, offsetof(mrsas_reg_set, 2887 outbound_scratch_pad)) & MFI_STATE_MASK; 2888 if (fw_state == MFI_STATE_FAULT) { 2889 mrsas_dprint(sc, MRSAS_OCR, 2890 "Found FW in FAULT state, will reset adapter.\n"); 2891 retval = 1; 2892 goto out; 2893 } 2894 outstanding = mrsas_atomic_read(&sc->fw_outstanding); 2895 if (!outstanding) 2896 goto out; 2897 2898 if (!(i % MRSAS_RESET_NOTICE_INTERVAL)) { 2899 mrsas_dprint(sc, MRSAS_OCR, "[%2d]waiting for %d " 2900 "commands to complete\n", i, outstanding); 2901 count = sc->msix_vectors > 0 ? sc->msix_vectors : 1; 2902 for (MSIxIndex = 0; MSIxIndex < count; MSIxIndex++) 2903 mrsas_complete_cmd(sc, MSIxIndex); 2904 } 2905 DELAY(1000 * 1000); 2906 } 2907 2908 if (mrsas_atomic_read(&sc->fw_outstanding)) { 2909 mrsas_dprint(sc, MRSAS_OCR, 2910 " pending commands remain after waiting," 2911 " will reset adapter.\n"); 2912 retval = 1; 2913 } 2914 out: 2915 return retval; 2916 } 2917 2918 /* 2919 * mrsas_release_mfi_cmd: Return a cmd to free command pool 2920 * input: Command packet for return to free cmd pool 2921 * 2922 * This function returns the MFI command to the command list. 2923 */ 2924 void 2925 mrsas_release_mfi_cmd(struct mrsas_mfi_cmd *cmd) 2926 { 2927 struct mrsas_softc *sc = cmd->sc; 2928 2929 mtx_lock(&sc->mfi_cmd_pool_lock); 2930 cmd->ccb_ptr = NULL; 2931 cmd->cmd_id.frame_count = 0; 2932 TAILQ_INSERT_TAIL(&(sc->mrsas_mfi_cmd_list_head), cmd, next); 2933 mtx_unlock(&sc->mfi_cmd_pool_lock); 2934 2935 return; 2936 } 2937 2938 /* 2939 * mrsas_get_controller_info: Returns FW's controller structure 2940 * input: Adapter soft state 2941 * Controller information structure 2942 * 2943 * Issues an internal command (DCMD) to get the FW's controller structure. This 2944 * information is mainly used to find out the maximum IO transfer per command 2945 * supported by the FW. 2946 */ 2947 static int 2948 mrsas_get_ctrl_info(struct mrsas_softc *sc, 2949 struct mrsas_ctrl_info *ctrl_info) 2950 { 2951 int retcode = 0; 2952 struct mrsas_mfi_cmd *cmd; 2953 struct mrsas_dcmd_frame *dcmd; 2954 2955 cmd = mrsas_get_mfi_cmd(sc); 2956 2957 if (!cmd) { 2958 device_printf(sc->mrsas_dev, "Failed to get a free cmd\n"); 2959 return -ENOMEM; 2960 } 2961 dcmd = &cmd->frame->dcmd; 2962 2963 if (mrsas_alloc_ctlr_info_cmd(sc) != SUCCESS) { 2964 device_printf(sc->mrsas_dev, "Cannot allocate get ctlr info cmd\n"); 2965 mrsas_release_mfi_cmd(cmd); 2966 return -ENOMEM; 2967 } 2968 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 2969 2970 dcmd->cmd = MFI_CMD_DCMD; 2971 dcmd->cmd_status = 0xFF; 2972 dcmd->sge_count = 1; 2973 dcmd->flags = MFI_FRAME_DIR_READ; 2974 dcmd->timeout = 0; 2975 dcmd->pad_0 = 0; 2976 dcmd->data_xfer_len = sizeof(struct mrsas_ctrl_info); 2977 dcmd->opcode = MR_DCMD_CTRL_GET_INFO; 2978 dcmd->sgl.sge32[0].phys_addr = sc->ctlr_info_phys_addr; 2979 dcmd->sgl.sge32[0].length = sizeof(struct mrsas_ctrl_info); 2980 2981 if (!mrsas_issue_polled(sc, cmd)) 2982 memcpy(ctrl_info, sc->ctlr_info_mem, sizeof(struct mrsas_ctrl_info)); 2983 else 2984 retcode = 1; 2985 2986 mrsas_free_ctlr_info_cmd(sc); 2987 mrsas_release_mfi_cmd(cmd); 2988 return (retcode); 2989 } 2990 2991 /* 2992 * mrsas_alloc_ctlr_info_cmd: Allocates memory for controller info command 2993 * input: Adapter soft state 2994 * 2995 * Allocates DMAable memory for the controller info internal command. 2996 */ 2997 int 2998 mrsas_alloc_ctlr_info_cmd(struct mrsas_softc *sc) 2999 { 3000 int ctlr_info_size; 3001 3002 /* Allocate get controller info command */ 3003 ctlr_info_size = sizeof(struct mrsas_ctrl_info); 3004 if (bus_dma_tag_create(sc->mrsas_parent_tag, 3005 1, 0, 3006 BUS_SPACE_MAXADDR_32BIT, 3007 BUS_SPACE_MAXADDR, 3008 NULL, NULL, 3009 ctlr_info_size, 3010 1, 3011 ctlr_info_size, 3012 BUS_DMA_ALLOCNOW, 3013 NULL, NULL, 3014 &sc->ctlr_info_tag)) { 3015 device_printf(sc->mrsas_dev, "Cannot allocate ctlr info tag\n"); 3016 return (ENOMEM); 3017 } 3018 if (bus_dmamem_alloc(sc->ctlr_info_tag, (void **)&sc->ctlr_info_mem, 3019 BUS_DMA_NOWAIT, &sc->ctlr_info_dmamap)) { 3020 device_printf(sc->mrsas_dev, "Cannot allocate ctlr info cmd mem\n"); 3021 return (ENOMEM); 3022 } 3023 if (bus_dmamap_load(sc->ctlr_info_tag, sc->ctlr_info_dmamap, 3024 sc->ctlr_info_mem, ctlr_info_size, mrsas_addr_cb, 3025 &sc->ctlr_info_phys_addr, BUS_DMA_NOWAIT)) { 3026 device_printf(sc->mrsas_dev, "Cannot load ctlr info cmd mem\n"); 3027 return (ENOMEM); 3028 } 3029 memset(sc->ctlr_info_mem, 0, ctlr_info_size); 3030 return (0); 3031 } 3032 3033 /* 3034 * mrsas_free_ctlr_info_cmd: Free memory for controller info command 3035 * input: Adapter soft state 3036 * 3037 * Deallocates memory of the get controller info cmd. 3038 */ 3039 void 3040 mrsas_free_ctlr_info_cmd(struct mrsas_softc *sc) 3041 { 3042 if (sc->ctlr_info_phys_addr) 3043 bus_dmamap_unload(sc->ctlr_info_tag, sc->ctlr_info_dmamap); 3044 if (sc->ctlr_info_mem != NULL) 3045 bus_dmamem_free(sc->ctlr_info_tag, sc->ctlr_info_mem, sc->ctlr_info_dmamap); 3046 if (sc->ctlr_info_tag != NULL) 3047 bus_dma_tag_destroy(sc->ctlr_info_tag); 3048 } 3049 3050 /* 3051 * mrsas_issue_polled: Issues a polling command 3052 * inputs: Adapter soft state 3053 * Command packet to be issued 3054 * 3055 * This function is for posting of internal commands to Firmware. MFI requires 3056 * the cmd_status to be set to 0xFF before posting. The maximun wait time of 3057 * the poll response timer is 180 seconds. 3058 */ 3059 int 3060 mrsas_issue_polled(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 3061 { 3062 struct mrsas_header *frame_hdr = &cmd->frame->hdr; 3063 u_int8_t max_wait = MRSAS_INTERNAL_CMD_WAIT_TIME; 3064 int i, retcode = 0; 3065 3066 frame_hdr->cmd_status = 0xFF; 3067 frame_hdr->flags |= MFI_FRAME_DONT_POST_IN_REPLY_QUEUE; 3068 3069 /* Issue the frame using inbound queue port */ 3070 if (mrsas_issue_dcmd(sc, cmd)) { 3071 device_printf(sc->mrsas_dev, "Cannot issue DCMD internal command.\n"); 3072 return (1); 3073 } 3074 /* 3075 * Poll response timer to wait for Firmware response. While this 3076 * timer with the DELAY call could block CPU, the time interval for 3077 * this is only 1 millisecond. 3078 */ 3079 if (frame_hdr->cmd_status == 0xFF) { 3080 for (i = 0; i < (max_wait * 1000); i++) { 3081 if (frame_hdr->cmd_status == 0xFF) 3082 DELAY(1000); 3083 else 3084 break; 3085 } 3086 } 3087 if (frame_hdr->cmd_status != 0) { 3088 if (frame_hdr->cmd_status == 0xFF) 3089 device_printf(sc->mrsas_dev, "DCMD timed out after %d seconds.\n", max_wait); 3090 else 3091 device_printf(sc->mrsas_dev, "DCMD failed, status = 0x%x\n", frame_hdr->cmd_status); 3092 retcode = 1; 3093 } 3094 return (retcode); 3095 } 3096 3097 /* 3098 * mrsas_issue_dcmd: Issues a MFI Pass thru cmd 3099 * input: Adapter soft state mfi cmd pointer 3100 * 3101 * This function is called by mrsas_issued_blocked_cmd() and 3102 * mrsas_issued_polled(), to build the MPT command and then fire the command 3103 * to Firmware. 3104 */ 3105 int 3106 mrsas_issue_dcmd(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 3107 { 3108 MRSAS_REQUEST_DESCRIPTOR_UNION *req_desc; 3109 3110 req_desc = mrsas_build_mpt_cmd(sc, cmd); 3111 if (!req_desc) { 3112 device_printf(sc->mrsas_dev, "Cannot build MPT cmd.\n"); 3113 return (1); 3114 } 3115 mrsas_fire_cmd(sc, req_desc->addr.u.low, req_desc->addr.u.high); 3116 3117 return (0); 3118 } 3119 3120 /* 3121 * mrsas_build_mpt_cmd: Calls helper function to build Passthru cmd 3122 * input: Adapter soft state mfi cmd to build 3123 * 3124 * This function is called by mrsas_issue_cmd() to build the MPT-MFI passthru 3125 * command and prepares the MPT command to send to Firmware. 3126 */ 3127 MRSAS_REQUEST_DESCRIPTOR_UNION * 3128 mrsas_build_mpt_cmd(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 3129 { 3130 MRSAS_REQUEST_DESCRIPTOR_UNION *req_desc; 3131 u_int16_t index; 3132 3133 if (mrsas_build_mptmfi_passthru(sc, cmd)) { 3134 device_printf(sc->mrsas_dev, "Cannot build MPT-MFI passthru cmd.\n"); 3135 return NULL; 3136 } 3137 index = cmd->cmd_id.context.smid; 3138 3139 req_desc = mrsas_get_request_desc(sc, index - 1); 3140 if (!req_desc) 3141 return NULL; 3142 3143 req_desc->addr.Words = 0; 3144 req_desc->SCSIIO.RequestFlags = (MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO << MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT); 3145 3146 req_desc->SCSIIO.SMID = index; 3147 3148 return (req_desc); 3149 } 3150 3151 /* 3152 * mrsas_build_mptmfi_passthru: Builds a MPT MFI Passthru command 3153 * input: Adapter soft state mfi cmd pointer 3154 * 3155 * The MPT command and the io_request are setup as a passthru command. The SGE 3156 * chain address is set to frame_phys_addr of the MFI command. 3157 */ 3158 u_int8_t 3159 mrsas_build_mptmfi_passthru(struct mrsas_softc *sc, struct mrsas_mfi_cmd *mfi_cmd) 3160 { 3161 MPI25_IEEE_SGE_CHAIN64 *mpi25_ieee_chain; 3162 PTR_MRSAS_RAID_SCSI_IO_REQUEST io_req; 3163 struct mrsas_mpt_cmd *mpt_cmd; 3164 struct mrsas_header *frame_hdr = &mfi_cmd->frame->hdr; 3165 3166 mpt_cmd = mrsas_get_mpt_cmd(sc); 3167 if (!mpt_cmd) 3168 return (1); 3169 3170 /* Save the smid. To be used for returning the cmd */ 3171 mfi_cmd->cmd_id.context.smid = mpt_cmd->index; 3172 3173 mpt_cmd->sync_cmd_idx = mfi_cmd->index; 3174 3175 /* 3176 * For cmds where the flag is set, store the flag and check on 3177 * completion. For cmds with this flag, don't call 3178 * mrsas_complete_cmd. 3179 */ 3180 3181 if (frame_hdr->flags & MFI_FRAME_DONT_POST_IN_REPLY_QUEUE) 3182 mpt_cmd->flags = MFI_FRAME_DONT_POST_IN_REPLY_QUEUE; 3183 3184 io_req = mpt_cmd->io_request; 3185 3186 if ((sc->device_id == MRSAS_INVADER) || (sc->device_id == MRSAS_FURY)) { 3187 pMpi25IeeeSgeChain64_t sgl_ptr_end = (pMpi25IeeeSgeChain64_t)&io_req->SGL; 3188 3189 sgl_ptr_end += sc->max_sge_in_main_msg - 1; 3190 sgl_ptr_end->Flags = 0; 3191 } 3192 mpi25_ieee_chain = (MPI25_IEEE_SGE_CHAIN64 *) & io_req->SGL.IeeeChain; 3193 3194 io_req->Function = MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST; 3195 io_req->SGLOffset0 = offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL) / 4; 3196 io_req->ChainOffset = sc->chain_offset_mfi_pthru; 3197 3198 mpi25_ieee_chain->Address = mfi_cmd->frame_phys_addr; 3199 3200 mpi25_ieee_chain->Flags = IEEE_SGE_FLAGS_CHAIN_ELEMENT | 3201 MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR; 3202 3203 mpi25_ieee_chain->Length = MRSAS_MAX_SZ_CHAIN_FRAME; 3204 3205 return (0); 3206 } 3207 3208 /* 3209 * mrsas_issue_blocked_cmd: Synchronous wrapper around regular FW cmds 3210 * input: Adapter soft state Command to be issued 3211 * 3212 * This function waits on an event for the command to be returned from the ISR. 3213 * Max wait time is MRSAS_INTERNAL_CMD_WAIT_TIME secs. Used for issuing 3214 * internal and ioctl commands. 3215 */ 3216 int 3217 mrsas_issue_blocked_cmd(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 3218 { 3219 u_int8_t max_wait = MRSAS_INTERNAL_CMD_WAIT_TIME; 3220 unsigned long total_time = 0; 3221 int retcode = 0; 3222 3223 /* Initialize cmd_status */ 3224 cmd->cmd_status = ECONNREFUSED; 3225 3226 /* Build MPT-MFI command for issue to FW */ 3227 if (mrsas_issue_dcmd(sc, cmd)) { 3228 device_printf(sc->mrsas_dev, "Cannot issue DCMD internal command.\n"); 3229 return (1); 3230 } 3231 sc->chan = (void *)&cmd; 3232 3233 while (1) { 3234 if (cmd->cmd_status == ECONNREFUSED) { 3235 tsleep((void *)&sc->chan, 0, "mrsas_sleep", hz); 3236 } else 3237 break; 3238 total_time++; 3239 if (total_time >= max_wait) { 3240 device_printf(sc->mrsas_dev, 3241 "Internal command timed out after %d seconds.\n", max_wait); 3242 retcode = 1; 3243 break; 3244 } 3245 } 3246 return (retcode); 3247 } 3248 3249 /* 3250 * mrsas_complete_mptmfi_passthru: Completes a command 3251 * input: @sc: Adapter soft state 3252 * @cmd: Command to be completed 3253 * @status: cmd completion status 3254 * 3255 * This function is called from mrsas_complete_cmd() after an interrupt is 3256 * received from Firmware, and io_request->Function is 3257 * MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST. 3258 */ 3259 void 3260 mrsas_complete_mptmfi_passthru(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd, 3261 u_int8_t status) 3262 { 3263 struct mrsas_header *hdr = &cmd->frame->hdr; 3264 u_int8_t cmd_status = cmd->frame->hdr.cmd_status; 3265 3266 /* Reset the retry counter for future re-tries */ 3267 cmd->retry_for_fw_reset = 0; 3268 3269 if (cmd->ccb_ptr) 3270 cmd->ccb_ptr = NULL; 3271 3272 switch (hdr->cmd) { 3273 case MFI_CMD_INVALID: 3274 device_printf(sc->mrsas_dev, "MFI_CMD_INVALID command.\n"); 3275 break; 3276 case MFI_CMD_PD_SCSI_IO: 3277 case MFI_CMD_LD_SCSI_IO: 3278 /* 3279 * MFI_CMD_PD_SCSI_IO and MFI_CMD_LD_SCSI_IO could have been 3280 * issued either through an IO path or an IOCTL path. If it 3281 * was via IOCTL, we will send it to internal completion. 3282 */ 3283 if (cmd->sync_cmd) { 3284 cmd->sync_cmd = 0; 3285 mrsas_wakeup(sc, cmd); 3286 break; 3287 } 3288 case MFI_CMD_SMP: 3289 case MFI_CMD_STP: 3290 case MFI_CMD_DCMD: 3291 /* Check for LD map update */ 3292 if ((cmd->frame->dcmd.opcode == MR_DCMD_LD_MAP_GET_INFO) && 3293 (cmd->frame->dcmd.mbox.b[1] == 1)) { 3294 sc->fast_path_io = 0; 3295 mtx_lock(&sc->raidmap_lock); 3296 if (cmd_status != 0) { 3297 if (cmd_status != MFI_STAT_NOT_FOUND) 3298 device_printf(sc->mrsas_dev, "map sync failed, status=%x\n", cmd_status); 3299 else { 3300 mrsas_release_mfi_cmd(cmd); 3301 mtx_unlock(&sc->raidmap_lock); 3302 break; 3303 } 3304 } else 3305 sc->map_id++; 3306 mrsas_release_mfi_cmd(cmd); 3307 if (MR_ValidateMapInfo(sc)) 3308 sc->fast_path_io = 0; 3309 else 3310 sc->fast_path_io = 1; 3311 mrsas_sync_map_info(sc); 3312 mtx_unlock(&sc->raidmap_lock); 3313 break; 3314 } 3315 if (cmd->frame->dcmd.opcode == MR_DCMD_CTRL_EVENT_GET_INFO || 3316 cmd->frame->dcmd.opcode == MR_DCMD_CTRL_EVENT_GET) { 3317 sc->mrsas_aen_triggered = 0; 3318 } 3319 /* See if got an event notification */ 3320 if (cmd->frame->dcmd.opcode == MR_DCMD_CTRL_EVENT_WAIT) 3321 mrsas_complete_aen(sc, cmd); 3322 else 3323 mrsas_wakeup(sc, cmd); 3324 break; 3325 case MFI_CMD_ABORT: 3326 /* Command issued to abort another cmd return */ 3327 mrsas_complete_abort(sc, cmd); 3328 break; 3329 default: 3330 device_printf(sc->mrsas_dev, "Unknown command completed! [0x%X]\n", hdr->cmd); 3331 break; 3332 } 3333 } 3334 3335 /* 3336 * mrsas_wakeup: Completes an internal command 3337 * input: Adapter soft state 3338 * Command to be completed 3339 * 3340 * In mrsas_issue_blocked_cmd(), after a command is issued to Firmware, a wait 3341 * timer is started. This function is called from 3342 * mrsas_complete_mptmfi_passthru() as it completes the command, to wake up 3343 * from the command wait. 3344 */ 3345 void 3346 mrsas_wakeup(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 3347 { 3348 cmd->cmd_status = cmd->frame->io.cmd_status; 3349 3350 if (cmd->cmd_status == ECONNREFUSED) 3351 cmd->cmd_status = 0; 3352 3353 sc->chan = (void *)&cmd; 3354 wakeup_one((void *)&sc->chan); 3355 return; 3356 } 3357 3358 /* 3359 * mrsas_shutdown_ctlr: Instructs FW to shutdown the controller input: 3360 * Adapter soft state Shutdown/Hibernate 3361 * 3362 * This function issues a DCMD internal command to Firmware to initiate shutdown 3363 * of the controller. 3364 */ 3365 static void 3366 mrsas_shutdown_ctlr(struct mrsas_softc *sc, u_int32_t opcode) 3367 { 3368 struct mrsas_mfi_cmd *cmd; 3369 struct mrsas_dcmd_frame *dcmd; 3370 3371 if (sc->adprecovery == MRSAS_HW_CRITICAL_ERROR) 3372 return; 3373 3374 cmd = mrsas_get_mfi_cmd(sc); 3375 if (!cmd) { 3376 device_printf(sc->mrsas_dev, "Cannot allocate for shutdown cmd.\n"); 3377 return; 3378 } 3379 if (sc->aen_cmd) 3380 mrsas_issue_blocked_abort_cmd(sc, sc->aen_cmd); 3381 3382 if (sc->map_update_cmd) 3383 mrsas_issue_blocked_abort_cmd(sc, sc->map_update_cmd); 3384 3385 dcmd = &cmd->frame->dcmd; 3386 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 3387 3388 dcmd->cmd = MFI_CMD_DCMD; 3389 dcmd->cmd_status = 0x0; 3390 dcmd->sge_count = 0; 3391 dcmd->flags = MFI_FRAME_DIR_NONE; 3392 dcmd->timeout = 0; 3393 dcmd->pad_0 = 0; 3394 dcmd->data_xfer_len = 0; 3395 dcmd->opcode = opcode; 3396 3397 device_printf(sc->mrsas_dev, "Preparing to shut down controller.\n"); 3398 3399 mrsas_issue_blocked_cmd(sc, cmd); 3400 mrsas_release_mfi_cmd(cmd); 3401 3402 return; 3403 } 3404 3405 /* 3406 * mrsas_flush_cache: Requests FW to flush all its caches input: 3407 * Adapter soft state 3408 * 3409 * This function is issues a DCMD internal command to Firmware to initiate 3410 * flushing of all caches. 3411 */ 3412 static void 3413 mrsas_flush_cache(struct mrsas_softc *sc) 3414 { 3415 struct mrsas_mfi_cmd *cmd; 3416 struct mrsas_dcmd_frame *dcmd; 3417 3418 if (sc->adprecovery == MRSAS_HW_CRITICAL_ERROR) 3419 return; 3420 3421 cmd = mrsas_get_mfi_cmd(sc); 3422 if (!cmd) { 3423 device_printf(sc->mrsas_dev, "Cannot allocate for flush cache cmd.\n"); 3424 return; 3425 } 3426 dcmd = &cmd->frame->dcmd; 3427 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 3428 3429 dcmd->cmd = MFI_CMD_DCMD; 3430 dcmd->cmd_status = 0x0; 3431 dcmd->sge_count = 0; 3432 dcmd->flags = MFI_FRAME_DIR_NONE; 3433 dcmd->timeout = 0; 3434 dcmd->pad_0 = 0; 3435 dcmd->data_xfer_len = 0; 3436 dcmd->opcode = MR_DCMD_CTRL_CACHE_FLUSH; 3437 dcmd->mbox.b[0] = MR_FLUSH_CTRL_CACHE | MR_FLUSH_DISK_CACHE; 3438 3439 mrsas_issue_blocked_cmd(sc, cmd); 3440 mrsas_release_mfi_cmd(cmd); 3441 3442 return; 3443 } 3444 3445 /* 3446 * mrsas_get_map_info: Load and validate RAID map input: 3447 * Adapter instance soft state 3448 * 3449 * This function calls mrsas_get_ld_map_info() and MR_ValidateMapInfo() to load 3450 * and validate RAID map. It returns 0 if successful, 1 other- wise. 3451 */ 3452 static int 3453 mrsas_get_map_info(struct mrsas_softc *sc) 3454 { 3455 uint8_t retcode = 0; 3456 3457 sc->fast_path_io = 0; 3458 if (!mrsas_get_ld_map_info(sc)) { 3459 retcode = MR_ValidateMapInfo(sc); 3460 if (retcode == 0) { 3461 sc->fast_path_io = 1; 3462 return 0; 3463 } 3464 } 3465 return 1; 3466 } 3467 3468 /* 3469 * mrsas_get_ld_map_info: Get FW's ld_map structure input: 3470 * Adapter instance soft state 3471 * 3472 * Issues an internal command (DCMD) to get the FW's controller PD list 3473 * structure. 3474 */ 3475 static int 3476 mrsas_get_ld_map_info(struct mrsas_softc *sc) 3477 { 3478 int retcode = 0; 3479 struct mrsas_mfi_cmd *cmd; 3480 struct mrsas_dcmd_frame *dcmd; 3481 void *map; 3482 bus_addr_t map_phys_addr = 0; 3483 3484 cmd = mrsas_get_mfi_cmd(sc); 3485 if (!cmd) { 3486 device_printf(sc->mrsas_dev, 3487 "Cannot alloc for ld map info cmd.\n"); 3488 return 1; 3489 } 3490 dcmd = &cmd->frame->dcmd; 3491 3492 map = (void *)sc->raidmap_mem[(sc->map_id & 1)]; 3493 map_phys_addr = sc->raidmap_phys_addr[(sc->map_id & 1)]; 3494 if (!map) { 3495 device_printf(sc->mrsas_dev, 3496 "Failed to alloc mem for ld map info.\n"); 3497 mrsas_release_mfi_cmd(cmd); 3498 return (ENOMEM); 3499 } 3500 memset(map, 0, sizeof(sc->max_map_sz)); 3501 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 3502 3503 dcmd->cmd = MFI_CMD_DCMD; 3504 dcmd->cmd_status = 0xFF; 3505 dcmd->sge_count = 1; 3506 dcmd->flags = MFI_FRAME_DIR_READ; 3507 dcmd->timeout = 0; 3508 dcmd->pad_0 = 0; 3509 dcmd->data_xfer_len = sc->current_map_sz; 3510 dcmd->opcode = MR_DCMD_LD_MAP_GET_INFO; 3511 dcmd->sgl.sge32[0].phys_addr = map_phys_addr; 3512 dcmd->sgl.sge32[0].length = sc->current_map_sz; 3513 3514 if (!mrsas_issue_polled(sc, cmd)) 3515 retcode = 0; 3516 else { 3517 device_printf(sc->mrsas_dev, 3518 "Fail to send get LD map info cmd.\n"); 3519 retcode = 1; 3520 } 3521 mrsas_release_mfi_cmd(cmd); 3522 3523 return (retcode); 3524 } 3525 3526 /* 3527 * mrsas_sync_map_info: Get FW's ld_map structure input: 3528 * Adapter instance soft state 3529 * 3530 * Issues an internal command (DCMD) to get the FW's controller PD list 3531 * structure. 3532 */ 3533 static int 3534 mrsas_sync_map_info(struct mrsas_softc *sc) 3535 { 3536 int retcode = 0, i; 3537 struct mrsas_mfi_cmd *cmd; 3538 struct mrsas_dcmd_frame *dcmd; 3539 uint32_t size_sync_info, num_lds; 3540 MR_LD_TARGET_SYNC *target_map = NULL; 3541 MR_DRV_RAID_MAP_ALL *map; 3542 MR_LD_RAID *raid; 3543 MR_LD_TARGET_SYNC *ld_sync; 3544 bus_addr_t map_phys_addr = 0; 3545 3546 cmd = mrsas_get_mfi_cmd(sc); 3547 if (!cmd) { 3548 device_printf(sc->mrsas_dev, 3549 "Cannot alloc for sync map info cmd\n"); 3550 return 1; 3551 } 3552 map = sc->ld_drv_map[sc->map_id & 1]; 3553 num_lds = map->raidMap.ldCount; 3554 3555 dcmd = &cmd->frame->dcmd; 3556 size_sync_info = sizeof(MR_LD_TARGET_SYNC) * num_lds; 3557 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 3558 3559 target_map = (MR_LD_TARGET_SYNC *) sc->raidmap_mem[(sc->map_id - 1) & 1]; 3560 memset(target_map, 0, sc->max_map_sz); 3561 3562 map_phys_addr = sc->raidmap_phys_addr[(sc->map_id - 1) & 1]; 3563 3564 ld_sync = (MR_LD_TARGET_SYNC *) target_map; 3565 3566 for (i = 0; i < num_lds; i++, ld_sync++) { 3567 raid = MR_LdRaidGet(i, map); 3568 ld_sync->targetId = MR_GetLDTgtId(i, map); 3569 ld_sync->seqNum = raid->seqNum; 3570 } 3571 3572 dcmd->cmd = MFI_CMD_DCMD; 3573 dcmd->cmd_status = 0xFF; 3574 dcmd->sge_count = 1; 3575 dcmd->flags = MFI_FRAME_DIR_WRITE; 3576 dcmd->timeout = 0; 3577 dcmd->pad_0 = 0; 3578 dcmd->data_xfer_len = sc->current_map_sz; 3579 dcmd->mbox.b[0] = num_lds; 3580 dcmd->mbox.b[1] = MRSAS_DCMD_MBOX_PEND_FLAG; 3581 dcmd->opcode = MR_DCMD_LD_MAP_GET_INFO; 3582 dcmd->sgl.sge32[0].phys_addr = map_phys_addr; 3583 dcmd->sgl.sge32[0].length = sc->current_map_sz; 3584 3585 sc->map_update_cmd = cmd; 3586 if (mrsas_issue_dcmd(sc, cmd)) { 3587 device_printf(sc->mrsas_dev, 3588 "Fail to send sync map info command.\n"); 3589 return (1); 3590 } 3591 return (retcode); 3592 } 3593 3594 /* 3595 * mrsas_get_pd_list: Returns FW's PD list structure input: 3596 * Adapter soft state 3597 * 3598 * Issues an internal command (DCMD) to get the FW's controller PD list 3599 * structure. This information is mainly used to find out about system 3600 * supported by Firmware. 3601 */ 3602 static int 3603 mrsas_get_pd_list(struct mrsas_softc *sc) 3604 { 3605 int retcode = 0, pd_index = 0, pd_count = 0, pd_list_size; 3606 struct mrsas_mfi_cmd *cmd; 3607 struct mrsas_dcmd_frame *dcmd; 3608 struct MR_PD_LIST *pd_list_mem; 3609 struct MR_PD_ADDRESS *pd_addr; 3610 bus_addr_t pd_list_phys_addr = 0; 3611 struct mrsas_tmp_dcmd *tcmd; 3612 3613 cmd = mrsas_get_mfi_cmd(sc); 3614 if (!cmd) { 3615 device_printf(sc->mrsas_dev, 3616 "Cannot alloc for get PD list cmd\n"); 3617 return 1; 3618 } 3619 dcmd = &cmd->frame->dcmd; 3620 3621 tcmd = malloc(sizeof(struct mrsas_tmp_dcmd), M_MRSAS, M_NOWAIT); 3622 pd_list_size = MRSAS_MAX_PD * sizeof(struct MR_PD_LIST); 3623 if (mrsas_alloc_tmp_dcmd(sc, tcmd, pd_list_size) != SUCCESS) { 3624 device_printf(sc->mrsas_dev, 3625 "Cannot alloc dmamap for get PD list cmd\n"); 3626 mrsas_release_mfi_cmd(cmd); 3627 return (ENOMEM); 3628 } else { 3629 pd_list_mem = tcmd->tmp_dcmd_mem; 3630 pd_list_phys_addr = tcmd->tmp_dcmd_phys_addr; 3631 } 3632 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 3633 3634 dcmd->mbox.b[0] = MR_PD_QUERY_TYPE_EXPOSED_TO_HOST; 3635 dcmd->mbox.b[1] = 0; 3636 dcmd->cmd = MFI_CMD_DCMD; 3637 dcmd->cmd_status = 0xFF; 3638 dcmd->sge_count = 1; 3639 dcmd->flags = MFI_FRAME_DIR_READ; 3640 dcmd->timeout = 0; 3641 dcmd->pad_0 = 0; 3642 dcmd->data_xfer_len = MRSAS_MAX_PD * sizeof(struct MR_PD_LIST); 3643 dcmd->opcode = MR_DCMD_PD_LIST_QUERY; 3644 dcmd->sgl.sge32[0].phys_addr = pd_list_phys_addr; 3645 dcmd->sgl.sge32[0].length = MRSAS_MAX_PD * sizeof(struct MR_PD_LIST); 3646 3647 if (!mrsas_issue_polled(sc, cmd)) 3648 retcode = 0; 3649 else 3650 retcode = 1; 3651 3652 /* Get the instance PD list */ 3653 pd_count = MRSAS_MAX_PD; 3654 pd_addr = pd_list_mem->addr; 3655 if (retcode == 0 && pd_list_mem->count < pd_count) { 3656 memset(sc->local_pd_list, 0, 3657 MRSAS_MAX_PD * sizeof(struct mrsas_pd_list)); 3658 for (pd_index = 0; pd_index < pd_list_mem->count; pd_index++) { 3659 sc->local_pd_list[pd_addr->deviceId].tid = pd_addr->deviceId; 3660 sc->local_pd_list[pd_addr->deviceId].driveType = 3661 pd_addr->scsiDevType; 3662 sc->local_pd_list[pd_addr->deviceId].driveState = 3663 MR_PD_STATE_SYSTEM; 3664 pd_addr++; 3665 } 3666 } 3667 /* 3668 * Use mutext/spinlock if pd_list component size increase more than 3669 * 32 bit. 3670 */ 3671 memcpy(sc->pd_list, sc->local_pd_list, sizeof(sc->local_pd_list)); 3672 mrsas_free_tmp_dcmd(tcmd); 3673 mrsas_release_mfi_cmd(cmd); 3674 free(tcmd, M_MRSAS); 3675 return (retcode); 3676 } 3677 3678 /* 3679 * mrsas_get_ld_list: Returns FW's LD list structure input: 3680 * Adapter soft state 3681 * 3682 * Issues an internal command (DCMD) to get the FW's controller PD list 3683 * structure. This information is mainly used to find out about supported by 3684 * the FW. 3685 */ 3686 static int 3687 mrsas_get_ld_list(struct mrsas_softc *sc) 3688 { 3689 int ld_list_size, retcode = 0, ld_index = 0, ids = 0; 3690 struct mrsas_mfi_cmd *cmd; 3691 struct mrsas_dcmd_frame *dcmd; 3692 struct MR_LD_LIST *ld_list_mem; 3693 bus_addr_t ld_list_phys_addr = 0; 3694 struct mrsas_tmp_dcmd *tcmd; 3695 3696 cmd = mrsas_get_mfi_cmd(sc); 3697 if (!cmd) { 3698 device_printf(sc->mrsas_dev, 3699 "Cannot alloc for get LD list cmd\n"); 3700 return 1; 3701 } 3702 dcmd = &cmd->frame->dcmd; 3703 3704 tcmd = malloc(sizeof(struct mrsas_tmp_dcmd), M_MRSAS, M_NOWAIT); 3705 ld_list_size = sizeof(struct MR_LD_LIST); 3706 if (mrsas_alloc_tmp_dcmd(sc, tcmd, ld_list_size) != SUCCESS) { 3707 device_printf(sc->mrsas_dev, 3708 "Cannot alloc dmamap for get LD list cmd\n"); 3709 mrsas_release_mfi_cmd(cmd); 3710 return (ENOMEM); 3711 } else { 3712 ld_list_mem = tcmd->tmp_dcmd_mem; 3713 ld_list_phys_addr = tcmd->tmp_dcmd_phys_addr; 3714 } 3715 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 3716 3717 if (sc->max256vdSupport) 3718 dcmd->mbox.b[0] = 1; 3719 3720 dcmd->cmd = MFI_CMD_DCMD; 3721 dcmd->cmd_status = 0xFF; 3722 dcmd->sge_count = 1; 3723 dcmd->flags = MFI_FRAME_DIR_READ; 3724 dcmd->timeout = 0; 3725 dcmd->data_xfer_len = sizeof(struct MR_LD_LIST); 3726 dcmd->opcode = MR_DCMD_LD_GET_LIST; 3727 dcmd->sgl.sge32[0].phys_addr = ld_list_phys_addr; 3728 dcmd->sgl.sge32[0].length = sizeof(struct MR_LD_LIST); 3729 dcmd->pad_0 = 0; 3730 3731 if (!mrsas_issue_polled(sc, cmd)) 3732 retcode = 0; 3733 else 3734 retcode = 1; 3735 3736 #if VD_EXT_DEBUG 3737 printf("Number of LDs %d\n", ld_list_mem->ldCount); 3738 #endif 3739 3740 /* Get the instance LD list */ 3741 if ((retcode == 0) && 3742 (ld_list_mem->ldCount <= sc->fw_supported_vd_count)) { 3743 sc->CurLdCount = ld_list_mem->ldCount; 3744 memset(sc->ld_ids, 0xff, MAX_LOGICAL_DRIVES_EXT); 3745 for (ld_index = 0; ld_index < ld_list_mem->ldCount; ld_index++) { 3746 if (ld_list_mem->ldList[ld_index].state != 0) { 3747 ids = ld_list_mem->ldList[ld_index].ref.ld_context.targetId; 3748 sc->ld_ids[ids] = ld_list_mem->ldList[ld_index].ref.ld_context.targetId; 3749 } 3750 } 3751 } 3752 mrsas_free_tmp_dcmd(tcmd); 3753 mrsas_release_mfi_cmd(cmd); 3754 free(tcmd, M_MRSAS); 3755 return (retcode); 3756 } 3757 3758 /* 3759 * mrsas_alloc_tmp_dcmd: Allocates memory for temporary command input: 3760 * Adapter soft state Temp command Size of alloction 3761 * 3762 * Allocates DMAable memory for a temporary internal command. The allocated 3763 * memory is initialized to all zeros upon successful loading of the dma 3764 * mapped memory. 3765 */ 3766 int 3767 mrsas_alloc_tmp_dcmd(struct mrsas_softc *sc, 3768 struct mrsas_tmp_dcmd *tcmd, int size) 3769 { 3770 if (bus_dma_tag_create(sc->mrsas_parent_tag, 3771 1, 0, 3772 BUS_SPACE_MAXADDR_32BIT, 3773 BUS_SPACE_MAXADDR, 3774 NULL, NULL, 3775 size, 3776 1, 3777 size, 3778 BUS_DMA_ALLOCNOW, 3779 NULL, NULL, 3780 &tcmd->tmp_dcmd_tag)) { 3781 device_printf(sc->mrsas_dev, "Cannot allocate tmp dcmd tag\n"); 3782 return (ENOMEM); 3783 } 3784 if (bus_dmamem_alloc(tcmd->tmp_dcmd_tag, (void **)&tcmd->tmp_dcmd_mem, 3785 BUS_DMA_NOWAIT, &tcmd->tmp_dcmd_dmamap)) { 3786 device_printf(sc->mrsas_dev, "Cannot allocate tmp dcmd mem\n"); 3787 return (ENOMEM); 3788 } 3789 if (bus_dmamap_load(tcmd->tmp_dcmd_tag, tcmd->tmp_dcmd_dmamap, 3790 tcmd->tmp_dcmd_mem, size, mrsas_addr_cb, 3791 &tcmd->tmp_dcmd_phys_addr, BUS_DMA_NOWAIT)) { 3792 device_printf(sc->mrsas_dev, "Cannot load tmp dcmd mem\n"); 3793 return (ENOMEM); 3794 } 3795 memset(tcmd->tmp_dcmd_mem, 0, size); 3796 return (0); 3797 } 3798 3799 /* 3800 * mrsas_free_tmp_dcmd: Free memory for temporary command input: 3801 * temporary dcmd pointer 3802 * 3803 * Deallocates memory of the temporary command for use in the construction of 3804 * the internal DCMD. 3805 */ 3806 void 3807 mrsas_free_tmp_dcmd(struct mrsas_tmp_dcmd *tmp) 3808 { 3809 if (tmp->tmp_dcmd_phys_addr) 3810 bus_dmamap_unload(tmp->tmp_dcmd_tag, tmp->tmp_dcmd_dmamap); 3811 if (tmp->tmp_dcmd_mem != NULL) 3812 bus_dmamem_free(tmp->tmp_dcmd_tag, tmp->tmp_dcmd_mem, tmp->tmp_dcmd_dmamap); 3813 if (tmp->tmp_dcmd_tag != NULL) 3814 bus_dma_tag_destroy(tmp->tmp_dcmd_tag); 3815 } 3816 3817 /* 3818 * mrsas_issue_blocked_abort_cmd: Aborts previously issued cmd input: 3819 * Adapter soft state Previously issued cmd to be aborted 3820 * 3821 * This function is used to abort previously issued commands, such as AEN and 3822 * RAID map sync map commands. The abort command is sent as a DCMD internal 3823 * command and subsequently the driver will wait for a return status. The 3824 * max wait time is MRSAS_INTERNAL_CMD_WAIT_TIME seconds. 3825 */ 3826 static int 3827 mrsas_issue_blocked_abort_cmd(struct mrsas_softc *sc, 3828 struct mrsas_mfi_cmd *cmd_to_abort) 3829 { 3830 struct mrsas_mfi_cmd *cmd; 3831 struct mrsas_abort_frame *abort_fr; 3832 u_int8_t retcode = 0; 3833 unsigned long total_time = 0; 3834 u_int8_t max_wait = MRSAS_INTERNAL_CMD_WAIT_TIME; 3835 3836 cmd = mrsas_get_mfi_cmd(sc); 3837 if (!cmd) { 3838 device_printf(sc->mrsas_dev, "Cannot alloc for abort cmd\n"); 3839 return (1); 3840 } 3841 abort_fr = &cmd->frame->abort; 3842 3843 /* Prepare and issue the abort frame */ 3844 abort_fr->cmd = MFI_CMD_ABORT; 3845 abort_fr->cmd_status = 0xFF; 3846 abort_fr->flags = 0; 3847 abort_fr->abort_context = cmd_to_abort->index; 3848 abort_fr->abort_mfi_phys_addr_lo = cmd_to_abort->frame_phys_addr; 3849 abort_fr->abort_mfi_phys_addr_hi = 0; 3850 3851 cmd->sync_cmd = 1; 3852 cmd->cmd_status = 0xFF; 3853 3854 if (mrsas_issue_dcmd(sc, cmd)) { 3855 device_printf(sc->mrsas_dev, "Fail to send abort command.\n"); 3856 return (1); 3857 } 3858 /* Wait for this cmd to complete */ 3859 sc->chan = (void *)&cmd; 3860 while (1) { 3861 if (cmd->cmd_status == 0xFF) { 3862 tsleep((void *)&sc->chan, 0, "mrsas_sleep", hz); 3863 } else 3864 break; 3865 total_time++; 3866 if (total_time >= max_wait) { 3867 device_printf(sc->mrsas_dev, "Abort cmd timed out after %d sec.\n", max_wait); 3868 retcode = 1; 3869 break; 3870 } 3871 } 3872 3873 cmd->sync_cmd = 0; 3874 mrsas_release_mfi_cmd(cmd); 3875 return (retcode); 3876 } 3877 3878 /* 3879 * mrsas_complete_abort: Completes aborting a command input: 3880 * Adapter soft state Cmd that was issued to abort another cmd 3881 * 3882 * The mrsas_issue_blocked_abort_cmd() function waits for the command status to 3883 * change after sending the command. This function is called from 3884 * mrsas_complete_mptmfi_passthru() to wake up the sleep thread associated. 3885 */ 3886 void 3887 mrsas_complete_abort(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 3888 { 3889 if (cmd->sync_cmd) { 3890 cmd->sync_cmd = 0; 3891 cmd->cmd_status = 0; 3892 sc->chan = (void *)&cmd; 3893 wakeup_one((void *)&sc->chan); 3894 } 3895 return; 3896 } 3897 3898 /* 3899 * mrsas_aen_handler: AEN processing callback function from thread context 3900 * input: Adapter soft state 3901 * 3902 * Asynchronous event handler 3903 */ 3904 void 3905 mrsas_aen_handler(struct mrsas_softc *sc) 3906 { 3907 union mrsas_evt_class_locale class_locale; 3908 int doscan = 0; 3909 u_int32_t seq_num; 3910 int error; 3911 3912 if (!sc) { 3913 device_printf(sc->mrsas_dev, "invalid instance!\n"); 3914 return; 3915 } 3916 if (sc->evt_detail_mem) { 3917 switch (sc->evt_detail_mem->code) { 3918 case MR_EVT_PD_INSERTED: 3919 mrsas_get_pd_list(sc); 3920 mrsas_bus_scan_sim(sc, sc->sim_1); 3921 doscan = 0; 3922 break; 3923 case MR_EVT_PD_REMOVED: 3924 mrsas_get_pd_list(sc); 3925 mrsas_bus_scan_sim(sc, sc->sim_1); 3926 doscan = 0; 3927 break; 3928 case MR_EVT_LD_OFFLINE: 3929 case MR_EVT_CFG_CLEARED: 3930 case MR_EVT_LD_DELETED: 3931 mrsas_bus_scan_sim(sc, sc->sim_0); 3932 doscan = 0; 3933 break; 3934 case MR_EVT_LD_CREATED: 3935 mrsas_get_ld_list(sc); 3936 mrsas_bus_scan_sim(sc, sc->sim_0); 3937 doscan = 0; 3938 break; 3939 case MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED: 3940 case MR_EVT_FOREIGN_CFG_IMPORTED: 3941 case MR_EVT_LD_STATE_CHANGE: 3942 doscan = 1; 3943 break; 3944 default: 3945 doscan = 0; 3946 break; 3947 } 3948 } else { 3949 device_printf(sc->mrsas_dev, "invalid evt_detail\n"); 3950 return; 3951 } 3952 if (doscan) { 3953 mrsas_get_pd_list(sc); 3954 mrsas_dprint(sc, MRSAS_AEN, "scanning ...sim 1\n"); 3955 mrsas_bus_scan_sim(sc, sc->sim_1); 3956 mrsas_get_ld_list(sc); 3957 mrsas_dprint(sc, MRSAS_AEN, "scanning ...sim 0\n"); 3958 mrsas_bus_scan_sim(sc, sc->sim_0); 3959 } 3960 seq_num = sc->evt_detail_mem->seq_num + 1; 3961 3962 /* Register AEN with FW for latest sequence number plus 1 */ 3963 class_locale.members.reserved = 0; 3964 class_locale.members.locale = MR_EVT_LOCALE_ALL; 3965 class_locale.members.class = MR_EVT_CLASS_DEBUG; 3966 3967 if (sc->aen_cmd != NULL) 3968 return; 3969 3970 mtx_lock(&sc->aen_lock); 3971 error = mrsas_register_aen(sc, seq_num, 3972 class_locale.word); 3973 mtx_unlock(&sc->aen_lock); 3974 3975 if (error) 3976 device_printf(sc->mrsas_dev, "register aen failed error %x\n", error); 3977 3978 } 3979 3980 3981 /* 3982 * mrsas_complete_aen: Completes AEN command 3983 * input: Adapter soft state 3984 * Cmd that was issued to abort another cmd 3985 * 3986 * This function will be called from ISR and will continue event processing from 3987 * thread context by enqueuing task in ev_tq (callback function 3988 * "mrsas_aen_handler"). 3989 */ 3990 void 3991 mrsas_complete_aen(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 3992 { 3993 /* 3994 * Don't signal app if it is just an aborted previously registered 3995 * aen 3996 */ 3997 if ((!cmd->abort_aen) && (sc->remove_in_progress == 0)) { 3998 sc->mrsas_aen_triggered = 1; 3999 if (sc->mrsas_poll_waiting) { 4000 sc->mrsas_poll_waiting = 0; 4001 selwakeup(&sc->mrsas_select); 4002 } 4003 } else 4004 cmd->abort_aen = 0; 4005 4006 sc->aen_cmd = NULL; 4007 mrsas_release_mfi_cmd(cmd); 4008 4009 if (!sc->remove_in_progress) 4010 taskqueue_enqueue(sc->ev_tq, &sc->ev_task); 4011 4012 return; 4013 } 4014 4015 static device_method_t mrsas_methods[] = { 4016 DEVMETHOD(device_probe, mrsas_probe), 4017 DEVMETHOD(device_attach, mrsas_attach), 4018 DEVMETHOD(device_detach, mrsas_detach), 4019 DEVMETHOD(device_suspend, mrsas_suspend), 4020 DEVMETHOD(device_resume, mrsas_resume), 4021 DEVMETHOD(bus_print_child, bus_generic_print_child), 4022 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 4023 {0, 0} 4024 }; 4025 4026 static driver_t mrsas_driver = { 4027 "mrsas", 4028 mrsas_methods, 4029 sizeof(struct mrsas_softc) 4030 }; 4031 4032 static devclass_t mrsas_devclass; 4033 4034 DRIVER_MODULE(mrsas, pci, mrsas_driver, mrsas_devclass, 0, 0); 4035 MODULE_DEPEND(mrsas, cam, 1, 1, 1); 4036