1 /* 2 * Copyright (c) 2015, AVAGO Tech. All rights reserved. Author: Marian Choy 3 * Copyright (c) 2014, LSI Corp. All rights reserved. Author: Marian Choy 4 * Support: freebsdraid@avagotech.com 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 10 * 1. Redistributions of source code must retain the above copyright notice, 11 * this list of conditions and the following disclaimer. 2. Redistributions 12 * in binary form must reproduce the above copyright notice, this list of 13 * conditions and the following disclaimer in the documentation and/or other 14 * materials provided with the distribution. 3. Neither the name of the 15 * <ORGANIZATION> nor the names of its contributors may be used to endorse or 16 * promote products derived from this software without specific prior written 17 * permission. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 22 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 23 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 * 31 * The views and conclusions contained in the software and documentation are 32 * those of the authors and should not be interpreted as representing 33 * official policies,either expressed or implied, of the FreeBSD Project. 34 * 35 * Send feedback to: <megaraidfbsd@avagotech.com> Mail to: AVAGO TECHNOLOGIES 1621 36 * Barber Lane, Milpitas, CA 95035 ATTN: MegaRaid FreeBSD 37 * 38 */ 39 40 #include <sys/cdefs.h> 41 __FBSDID("$FreeBSD$"); 42 43 #include <dev/mrsas/mrsas.h> 44 #include <dev/mrsas/mrsas_ioctl.h> 45 46 #include <cam/cam.h> 47 #include <cam/cam_ccb.h> 48 49 #include <sys/sysctl.h> 50 #include <sys/types.h> 51 #include <sys/sysent.h> 52 #include <sys/kthread.h> 53 #include <sys/taskqueue.h> 54 #include <sys/smp.h> 55 #include <sys/endian.h> 56 57 /* 58 * Function prototypes 59 */ 60 static d_open_t mrsas_open; 61 static d_close_t mrsas_close; 62 static d_read_t mrsas_read; 63 static d_write_t mrsas_write; 64 static d_ioctl_t mrsas_ioctl; 65 static d_poll_t mrsas_poll; 66 67 static void mrsas_ich_startup(void *arg); 68 static struct mrsas_mgmt_info mrsas_mgmt_info; 69 static struct mrsas_ident *mrsas_find_ident(device_t); 70 static int mrsas_setup_msix(struct mrsas_softc *sc); 71 static int mrsas_allocate_msix(struct mrsas_softc *sc); 72 static void mrsas_shutdown_ctlr(struct mrsas_softc *sc, u_int32_t opcode); 73 static void mrsas_flush_cache(struct mrsas_softc *sc); 74 static void mrsas_reset_reply_desc(struct mrsas_softc *sc); 75 static void mrsas_ocr_thread(void *arg); 76 static int mrsas_get_map_info(struct mrsas_softc *sc); 77 static int mrsas_get_ld_map_info(struct mrsas_softc *sc); 78 static int mrsas_sync_map_info(struct mrsas_softc *sc); 79 static int mrsas_get_pd_list(struct mrsas_softc *sc); 80 static int mrsas_get_ld_list(struct mrsas_softc *sc); 81 static int mrsas_setup_irq(struct mrsas_softc *sc); 82 static int mrsas_alloc_mem(struct mrsas_softc *sc); 83 static int mrsas_init_fw(struct mrsas_softc *sc); 84 static int mrsas_setup_raidmap(struct mrsas_softc *sc); 85 static void megasas_setup_jbod_map(struct mrsas_softc *sc); 86 static int megasas_sync_pd_seq_num(struct mrsas_softc *sc, boolean_t pend); 87 static int mrsas_clear_intr(struct mrsas_softc *sc); 88 static int mrsas_get_ctrl_info(struct mrsas_softc *sc); 89 static void mrsas_update_ext_vd_details(struct mrsas_softc *sc); 90 static int 91 mrsas_issue_blocked_abort_cmd(struct mrsas_softc *sc, 92 struct mrsas_mfi_cmd *cmd_to_abort); 93 static void 94 mrsas_get_pd_info(struct mrsas_softc *sc, u_int16_t device_id); 95 static struct mrsas_softc * 96 mrsas_get_softc_instance(struct cdev *dev, 97 u_long cmd, caddr_t arg); 98 u_int32_t 99 mrsas_read_reg_with_retries(struct mrsas_softc *sc, int offset); 100 u_int32_t mrsas_read_reg(struct mrsas_softc *sc, int offset); 101 u_int8_t 102 mrsas_build_mptmfi_passthru(struct mrsas_softc *sc, 103 struct mrsas_mfi_cmd *mfi_cmd); 104 void mrsas_complete_outstanding_ioctls(struct mrsas_softc *sc); 105 int mrsas_transition_to_ready(struct mrsas_softc *sc, int ocr); 106 int mrsas_init_adapter(struct mrsas_softc *sc); 107 int mrsas_alloc_mpt_cmds(struct mrsas_softc *sc); 108 int mrsas_alloc_ioc_cmd(struct mrsas_softc *sc); 109 int mrsas_alloc_ctlr_info_cmd(struct mrsas_softc *sc); 110 int mrsas_ioc_init(struct mrsas_softc *sc); 111 int mrsas_bus_scan(struct mrsas_softc *sc); 112 int mrsas_issue_dcmd(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd); 113 int mrsas_issue_polled(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd); 114 int mrsas_reset_ctrl(struct mrsas_softc *sc, u_int8_t reset_reason); 115 int mrsas_wait_for_outstanding(struct mrsas_softc *sc, u_int8_t check_reason); 116 int mrsas_complete_cmd(struct mrsas_softc *sc, u_int32_t MSIxIndex); 117 int mrsas_reset_targets(struct mrsas_softc *sc); 118 int 119 mrsas_issue_blocked_cmd(struct mrsas_softc *sc, 120 struct mrsas_mfi_cmd *cmd); 121 int 122 mrsas_alloc_tmp_dcmd(struct mrsas_softc *sc, struct mrsas_tmp_dcmd *tcmd, 123 int size); 124 void mrsas_release_mfi_cmd(struct mrsas_mfi_cmd *cmd); 125 void mrsas_wakeup(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd); 126 void mrsas_complete_aen(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd); 127 void mrsas_complete_abort(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd); 128 void mrsas_disable_intr(struct mrsas_softc *sc); 129 void mrsas_enable_intr(struct mrsas_softc *sc); 130 void mrsas_free_ioc_cmd(struct mrsas_softc *sc); 131 void mrsas_free_mem(struct mrsas_softc *sc); 132 void mrsas_free_tmp_dcmd(struct mrsas_tmp_dcmd *tmp); 133 void mrsas_isr(void *arg); 134 void mrsas_teardown_intr(struct mrsas_softc *sc); 135 void mrsas_addr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 136 void mrsas_kill_hba(struct mrsas_softc *sc); 137 void mrsas_aen_handler(struct mrsas_softc *sc); 138 void 139 mrsas_write_reg(struct mrsas_softc *sc, int offset, 140 u_int32_t value); 141 void 142 mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo, 143 u_int32_t req_desc_hi); 144 void mrsas_free_ctlr_info_cmd(struct mrsas_softc *sc); 145 void 146 mrsas_complete_mptmfi_passthru(struct mrsas_softc *sc, 147 struct mrsas_mfi_cmd *cmd, u_int8_t status); 148 struct mrsas_mfi_cmd *mrsas_get_mfi_cmd(struct mrsas_softc *sc); 149 150 MRSAS_REQUEST_DESCRIPTOR_UNION *mrsas_build_mpt_cmd 151 (struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd); 152 153 extern int mrsas_cam_attach(struct mrsas_softc *sc); 154 extern void mrsas_cam_detach(struct mrsas_softc *sc); 155 extern void mrsas_cmd_done(struct mrsas_softc *sc, struct mrsas_mpt_cmd *cmd); 156 extern void mrsas_free_frame(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd); 157 extern int mrsas_alloc_mfi_cmds(struct mrsas_softc *sc); 158 extern struct mrsas_mpt_cmd *mrsas_get_mpt_cmd(struct mrsas_softc *sc); 159 extern int mrsas_passthru(struct mrsas_softc *sc, void *arg, u_long ioctlCmd); 160 extern uint8_t MR_ValidateMapInfo(struct mrsas_softc *sc); 161 extern u_int16_t MR_GetLDTgtId(u_int32_t ld, MR_DRV_RAID_MAP_ALL * map); 162 extern MR_LD_RAID *MR_LdRaidGet(u_int32_t ld, MR_DRV_RAID_MAP_ALL * map); 163 extern void mrsas_xpt_freeze(struct mrsas_softc *sc); 164 extern void mrsas_xpt_release(struct mrsas_softc *sc); 165 extern MRSAS_REQUEST_DESCRIPTOR_UNION * 166 mrsas_get_request_desc(struct mrsas_softc *sc, 167 u_int16_t index); 168 extern int mrsas_bus_scan_sim(struct mrsas_softc *sc, struct cam_sim *sim); 169 static int mrsas_alloc_evt_log_info_cmd(struct mrsas_softc *sc); 170 static void mrsas_free_evt_log_info_cmd(struct mrsas_softc *sc); 171 void mrsas_release_mpt_cmd(struct mrsas_mpt_cmd *cmd); 172 173 void mrsas_map_mpt_cmd_status(struct mrsas_mpt_cmd *cmd, 174 union ccb *ccb_ptr, u_int8_t status, u_int8_t extStatus, 175 u_int32_t data_length, u_int8_t *sense); 176 void 177 mrsas_write_64bit_req_desc(struct mrsas_softc *sc, u_int32_t req_desc_lo, 178 u_int32_t req_desc_hi); 179 180 SYSCTL_NODE(_hw, OID_AUTO, mrsas, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 181 "MRSAS Driver Parameters"); 182 183 /* 184 * PCI device struct and table 185 * 186 */ 187 typedef struct mrsas_ident { 188 uint16_t vendor; 189 uint16_t device; 190 uint16_t subvendor; 191 uint16_t subdevice; 192 const char *desc; 193 } MRSAS_CTLR_ID; 194 195 MRSAS_CTLR_ID device_table[] = { 196 {0x1000, MRSAS_TBOLT, 0xffff, 0xffff, "AVAGO Thunderbolt SAS Controller"}, 197 {0x1000, MRSAS_INVADER, 0xffff, 0xffff, "AVAGO Invader SAS Controller"}, 198 {0x1000, MRSAS_FURY, 0xffff, 0xffff, "AVAGO Fury SAS Controller"}, 199 {0x1000, MRSAS_INTRUDER, 0xffff, 0xffff, "AVAGO Intruder SAS Controller"}, 200 {0x1000, MRSAS_INTRUDER_24, 0xffff, 0xffff, "AVAGO Intruder_24 SAS Controller"}, 201 {0x1000, MRSAS_CUTLASS_52, 0xffff, 0xffff, "AVAGO Cutlass_52 SAS Controller"}, 202 {0x1000, MRSAS_CUTLASS_53, 0xffff, 0xffff, "AVAGO Cutlass_53 SAS Controller"}, 203 {0x1000, MRSAS_VENTURA, 0xffff, 0xffff, "AVAGO Ventura SAS Controller"}, 204 {0x1000, MRSAS_CRUSADER, 0xffff, 0xffff, "AVAGO Crusader SAS Controller"}, 205 {0x1000, MRSAS_HARPOON, 0xffff, 0xffff, "AVAGO Harpoon SAS Controller"}, 206 {0x1000, MRSAS_TOMCAT, 0xffff, 0xffff, "AVAGO Tomcat SAS Controller"}, 207 {0x1000, MRSAS_VENTURA_4PORT, 0xffff, 0xffff, "AVAGO Ventura_4Port SAS Controller"}, 208 {0x1000, MRSAS_CRUSADER_4PORT, 0xffff, 0xffff, "AVAGO Crusader_4Port SAS Controller"}, 209 {0x1000, MRSAS_AERO_10E0, 0xffff, 0xffff, "BROADCOM AERO-10E0 SAS Controller"}, 210 {0x1000, MRSAS_AERO_10E1, 0xffff, 0xffff, "BROADCOM AERO-10E1 SAS Controller"}, 211 {0x1000, MRSAS_AERO_10E2, 0xffff, 0xffff, "BROADCOM AERO-10E2 SAS Controller"}, 212 {0x1000, MRSAS_AERO_10E3, 0xffff, 0xffff, "BROADCOM AERO-10E3 SAS Controller"}, 213 {0x1000, MRSAS_AERO_10E4, 0xffff, 0xffff, "BROADCOM AERO-10E4 SAS Controller"}, 214 {0x1000, MRSAS_AERO_10E5, 0xffff, 0xffff, "BROADCOM AERO-10E5 SAS Controller"}, 215 {0x1000, MRSAS_AERO_10E6, 0xffff, 0xffff, "BROADCOM AERO-10E6 SAS Controller"}, 216 {0x1000, MRSAS_AERO_10E7, 0xffff, 0xffff, "BROADCOM AERO-10E7 SAS Controller"}, 217 {0, 0, 0, 0, NULL} 218 }; 219 220 /* 221 * Character device entry points 222 * 223 */ 224 static struct cdevsw mrsas_cdevsw = { 225 .d_version = D_VERSION, 226 .d_open = mrsas_open, 227 .d_close = mrsas_close, 228 .d_read = mrsas_read, 229 .d_write = mrsas_write, 230 .d_ioctl = mrsas_ioctl, 231 .d_poll = mrsas_poll, 232 .d_name = "mrsas", 233 }; 234 235 MALLOC_DEFINE(M_MRSAS, "mrsasbuf", "Buffers for the MRSAS driver"); 236 237 /* 238 * In the cdevsw routines, we find our softc by using the si_drv1 member of 239 * struct cdev. We set this variable to point to our softc in our attach 240 * routine when we create the /dev entry. 241 */ 242 int 243 mrsas_open(struct cdev *dev, int oflags, int devtype, struct thread *td) 244 { 245 struct mrsas_softc *sc; 246 247 sc = dev->si_drv1; 248 return (0); 249 } 250 251 int 252 mrsas_close(struct cdev *dev, int fflag, int devtype, struct thread *td) 253 { 254 struct mrsas_softc *sc; 255 256 sc = dev->si_drv1; 257 return (0); 258 } 259 260 int 261 mrsas_read(struct cdev *dev, struct uio *uio, int ioflag) 262 { 263 struct mrsas_softc *sc; 264 265 sc = dev->si_drv1; 266 return (0); 267 } 268 int 269 mrsas_write(struct cdev *dev, struct uio *uio, int ioflag) 270 { 271 struct mrsas_softc *sc; 272 273 sc = dev->si_drv1; 274 return (0); 275 } 276 277 u_int32_t 278 mrsas_read_reg_with_retries(struct mrsas_softc *sc, int offset) 279 { 280 u_int32_t i = 0, ret_val; 281 282 if (sc->is_aero) { 283 do { 284 ret_val = mrsas_read_reg(sc, offset); 285 i++; 286 } while(ret_val == 0 && i < 3); 287 } else 288 ret_val = mrsas_read_reg(sc, offset); 289 290 return ret_val; 291 } 292 293 /* 294 * Register Read/Write Functions 295 * 296 */ 297 void 298 mrsas_write_reg(struct mrsas_softc *sc, int offset, 299 u_int32_t value) 300 { 301 bus_space_tag_t bus_tag = sc->bus_tag; 302 bus_space_handle_t bus_handle = sc->bus_handle; 303 304 bus_space_write_4(bus_tag, bus_handle, offset, value); 305 } 306 307 u_int32_t 308 mrsas_read_reg(struct mrsas_softc *sc, int offset) 309 { 310 bus_space_tag_t bus_tag = sc->bus_tag; 311 bus_space_handle_t bus_handle = sc->bus_handle; 312 313 return ((u_int32_t)bus_space_read_4(bus_tag, bus_handle, offset)); 314 } 315 316 /* 317 * Interrupt Disable/Enable/Clear Functions 318 * 319 */ 320 void 321 mrsas_disable_intr(struct mrsas_softc *sc) 322 { 323 u_int32_t mask = 0xFFFFFFFF; 324 u_int32_t status; 325 326 sc->mask_interrupts = 1; 327 mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask), mask); 328 /* Dummy read to force pci flush */ 329 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask)); 330 } 331 332 void 333 mrsas_enable_intr(struct mrsas_softc *sc) 334 { 335 u_int32_t mask = MFI_FUSION_ENABLE_INTERRUPT_MASK; 336 u_int32_t status; 337 338 sc->mask_interrupts = 0; 339 mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status), ~0); 340 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_status)); 341 342 mrsas_write_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask), ~mask); 343 status = mrsas_read_reg(sc, offsetof(mrsas_reg_set, outbound_intr_mask)); 344 } 345 346 static int 347 mrsas_clear_intr(struct mrsas_softc *sc) 348 { 349 u_int32_t status; 350 351 /* Read received interrupt */ 352 status = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, outbound_intr_status)); 353 354 /* Not our interrupt, so just return */ 355 if (!(status & MFI_FUSION_ENABLE_INTERRUPT_MASK)) 356 return (0); 357 358 /* We got a reply interrupt */ 359 return (1); 360 } 361 362 /* 363 * PCI Support Functions 364 * 365 */ 366 static struct mrsas_ident * 367 mrsas_find_ident(device_t dev) 368 { 369 struct mrsas_ident *pci_device; 370 371 for (pci_device = device_table; pci_device->vendor != 0; pci_device++) { 372 if ((pci_device->vendor == pci_get_vendor(dev)) && 373 (pci_device->device == pci_get_device(dev)) && 374 ((pci_device->subvendor == pci_get_subvendor(dev)) || 375 (pci_device->subvendor == 0xffff)) && 376 ((pci_device->subdevice == pci_get_subdevice(dev)) || 377 (pci_device->subdevice == 0xffff))) 378 return (pci_device); 379 } 380 return (NULL); 381 } 382 383 static int 384 mrsas_probe(device_t dev) 385 { 386 static u_int8_t first_ctrl = 1; 387 struct mrsas_ident *id; 388 389 if ((id = mrsas_find_ident(dev)) != NULL) { 390 if (first_ctrl) { 391 printf("AVAGO MegaRAID SAS FreeBSD mrsas driver version: %s\n", 392 MRSAS_VERSION); 393 first_ctrl = 0; 394 } 395 device_set_desc(dev, id->desc); 396 /* between BUS_PROBE_DEFAULT and BUS_PROBE_LOW_PRIORITY */ 397 return (-30); 398 } 399 return (ENXIO); 400 } 401 402 /* 403 * mrsas_setup_sysctl: setup sysctl values for mrsas 404 * input: Adapter instance soft state 405 * 406 * Setup sysctl entries for mrsas driver. 407 */ 408 static void 409 mrsas_setup_sysctl(struct mrsas_softc *sc) 410 { 411 struct sysctl_ctx_list *sysctl_ctx = NULL; 412 struct sysctl_oid *sysctl_tree = NULL; 413 char tmpstr[80], tmpstr2[80]; 414 415 /* 416 * Setup the sysctl variable so the user can change the debug level 417 * on the fly. 418 */ 419 snprintf(tmpstr, sizeof(tmpstr), "MRSAS controller %d", 420 device_get_unit(sc->mrsas_dev)); 421 snprintf(tmpstr2, sizeof(tmpstr2), "%d", device_get_unit(sc->mrsas_dev)); 422 423 sysctl_ctx = device_get_sysctl_ctx(sc->mrsas_dev); 424 if (sysctl_ctx != NULL) 425 sysctl_tree = device_get_sysctl_tree(sc->mrsas_dev); 426 427 if (sysctl_tree == NULL) { 428 sysctl_ctx_init(&sc->sysctl_ctx); 429 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 430 SYSCTL_STATIC_CHILDREN(_hw_mrsas), OID_AUTO, tmpstr2, 431 CTLFLAG_RD | CTLFLAG_MPSAFE, 0, tmpstr); 432 if (sc->sysctl_tree == NULL) 433 return; 434 sysctl_ctx = &sc->sysctl_ctx; 435 sysctl_tree = sc->sysctl_tree; 436 } 437 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 438 OID_AUTO, "disable_ocr", CTLFLAG_RW, &sc->disableOnlineCtrlReset, 0, 439 "Disable the use of OCR"); 440 441 SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 442 OID_AUTO, "driver_version", CTLFLAG_RD, MRSAS_VERSION, 443 strlen(MRSAS_VERSION), "driver version"); 444 445 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 446 OID_AUTO, "reset_count", CTLFLAG_RD, 447 &sc->reset_count, 0, "number of ocr from start of the day"); 448 449 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 450 OID_AUTO, "fw_outstanding", CTLFLAG_RD, 451 &sc->fw_outstanding.val_rdonly, 0, "FW outstanding commands"); 452 453 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 454 OID_AUTO, "io_cmds_highwater", CTLFLAG_RD, 455 &sc->io_cmds_highwater, 0, "Max FW outstanding commands"); 456 457 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 458 OID_AUTO, "mrsas_debug", CTLFLAG_RW, &sc->mrsas_debug, 0, 459 "Driver debug level"); 460 461 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 462 OID_AUTO, "mrsas_io_timeout", CTLFLAG_RW, &sc->mrsas_io_timeout, 463 0, "Driver IO timeout value in mili-second."); 464 465 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 466 OID_AUTO, "mrsas_fw_fault_check_delay", CTLFLAG_RW, 467 &sc->mrsas_fw_fault_check_delay, 468 0, "FW fault check thread delay in seconds. <default is 1 sec>"); 469 470 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 471 OID_AUTO, "reset_in_progress", CTLFLAG_RD, 472 &sc->reset_in_progress, 0, "ocr in progress status"); 473 474 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 475 OID_AUTO, "block_sync_cache", CTLFLAG_RW, 476 &sc->block_sync_cache, 0, 477 "Block SYNC CACHE at driver. <default: 0, send it to FW>"); 478 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 479 OID_AUTO, "stream detection", CTLFLAG_RW, 480 &sc->drv_stream_detection, 0, 481 "Disable/Enable Stream detection. <default: 1, Enable Stream Detection>"); 482 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 483 OID_AUTO, "prp_count", CTLFLAG_RD, 484 &sc->prp_count.val_rdonly, 0, "Number of IOs for which PRPs are built"); 485 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 486 OID_AUTO, "SGE holes", CTLFLAG_RD, 487 &sc->sge_holes.val_rdonly, 0, "Number of IOs with holes in SGEs"); 488 } 489 490 /* 491 * mrsas_get_tunables: get tunable parameters. 492 * input: Adapter instance soft state 493 * 494 * Get tunable parameters. This will help to debug driver at boot time. 495 */ 496 static void 497 mrsas_get_tunables(struct mrsas_softc *sc) 498 { 499 char tmpstr[80]; 500 501 /* XXX default to some debugging for now */ 502 sc->mrsas_debug = 503 (MRSAS_FAULT | MRSAS_OCR | MRSAS_INFO | MRSAS_TRACE | MRSAS_AEN); 504 sc->mrsas_io_timeout = MRSAS_IO_TIMEOUT; 505 sc->mrsas_fw_fault_check_delay = 1; 506 sc->reset_count = 0; 507 sc->reset_in_progress = 0; 508 sc->block_sync_cache = 0; 509 sc->drv_stream_detection = 1; 510 511 /* 512 * Grab the global variables. 513 */ 514 TUNABLE_INT_FETCH("hw.mrsas.debug_level", &sc->mrsas_debug); 515 516 /* 517 * Grab the global variables. 518 */ 519 TUNABLE_INT_FETCH("hw.mrsas.lb_pending_cmds", &sc->lb_pending_cmds); 520 521 /* Grab the unit-instance variables */ 522 snprintf(tmpstr, sizeof(tmpstr), "dev.mrsas.%d.debug_level", 523 device_get_unit(sc->mrsas_dev)); 524 TUNABLE_INT_FETCH(tmpstr, &sc->mrsas_debug); 525 } 526 527 /* 528 * mrsas_alloc_evt_log_info cmd: Allocates memory to get event log information. 529 * Used to get sequence number at driver load time. 530 * input: Adapter soft state 531 * 532 * Allocates DMAable memory for the event log info internal command. 533 */ 534 int 535 mrsas_alloc_evt_log_info_cmd(struct mrsas_softc *sc) 536 { 537 int el_info_size; 538 539 /* Allocate get event log info command */ 540 el_info_size = sizeof(struct mrsas_evt_log_info); 541 if (bus_dma_tag_create(sc->mrsas_parent_tag, 542 1, 0, 543 BUS_SPACE_MAXADDR_32BIT, 544 BUS_SPACE_MAXADDR, 545 NULL, NULL, 546 el_info_size, 547 1, 548 el_info_size, 549 BUS_DMA_ALLOCNOW, 550 NULL, NULL, 551 &sc->el_info_tag)) { 552 device_printf(sc->mrsas_dev, "Cannot allocate event log info tag\n"); 553 return (ENOMEM); 554 } 555 if (bus_dmamem_alloc(sc->el_info_tag, (void **)&sc->el_info_mem, 556 BUS_DMA_NOWAIT, &sc->el_info_dmamap)) { 557 device_printf(sc->mrsas_dev, "Cannot allocate event log info cmd mem\n"); 558 return (ENOMEM); 559 } 560 if (bus_dmamap_load(sc->el_info_tag, sc->el_info_dmamap, 561 sc->el_info_mem, el_info_size, mrsas_addr_cb, 562 &sc->el_info_phys_addr, BUS_DMA_NOWAIT)) { 563 device_printf(sc->mrsas_dev, "Cannot load event log info cmd mem\n"); 564 return (ENOMEM); 565 } 566 memset(sc->el_info_mem, 0, el_info_size); 567 return (0); 568 } 569 570 /* 571 * mrsas_free_evt_info_cmd: Free memory for Event log info command 572 * input: Adapter soft state 573 * 574 * Deallocates memory for the event log info internal command. 575 */ 576 void 577 mrsas_free_evt_log_info_cmd(struct mrsas_softc *sc) 578 { 579 if (sc->el_info_phys_addr) 580 bus_dmamap_unload(sc->el_info_tag, sc->el_info_dmamap); 581 if (sc->el_info_mem != NULL) 582 bus_dmamem_free(sc->el_info_tag, sc->el_info_mem, sc->el_info_dmamap); 583 if (sc->el_info_tag != NULL) 584 bus_dma_tag_destroy(sc->el_info_tag); 585 } 586 587 /* 588 * mrsas_get_seq_num: Get latest event sequence number 589 * @sc: Adapter soft state 590 * @eli: Firmware event log sequence number information. 591 * 592 * Firmware maintains a log of all events in a non-volatile area. 593 * Driver get the sequence number using DCMD 594 * "MR_DCMD_CTRL_EVENT_GET_INFO" at driver load time. 595 */ 596 597 static int 598 mrsas_get_seq_num(struct mrsas_softc *sc, 599 struct mrsas_evt_log_info *eli) 600 { 601 struct mrsas_mfi_cmd *cmd; 602 struct mrsas_dcmd_frame *dcmd; 603 u_int8_t do_ocr = 1, retcode = 0; 604 605 cmd = mrsas_get_mfi_cmd(sc); 606 607 if (!cmd) { 608 device_printf(sc->mrsas_dev, "Failed to get a free cmd\n"); 609 return -ENOMEM; 610 } 611 dcmd = &cmd->frame->dcmd; 612 613 if (mrsas_alloc_evt_log_info_cmd(sc) != SUCCESS) { 614 device_printf(sc->mrsas_dev, "Cannot allocate evt log info cmd\n"); 615 mrsas_release_mfi_cmd(cmd); 616 return -ENOMEM; 617 } 618 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 619 620 dcmd->cmd = MFI_CMD_DCMD; 621 dcmd->cmd_status = 0x0; 622 dcmd->sge_count = 1; 623 dcmd->flags = htole16(MFI_FRAME_DIR_READ); 624 dcmd->timeout = 0; 625 dcmd->pad_0 = 0; 626 dcmd->data_xfer_len = htole32(sizeof(struct mrsas_evt_log_info)); 627 dcmd->opcode = htole32(MR_DCMD_CTRL_EVENT_GET_INFO); 628 dcmd->sgl.sge32[0].phys_addr = htole32(sc->el_info_phys_addr & 0xFFFFFFFF); 629 dcmd->sgl.sge32[0].length = htole32(sizeof(struct mrsas_evt_log_info)); 630 631 retcode = mrsas_issue_blocked_cmd(sc, cmd); 632 if (retcode == ETIMEDOUT) 633 goto dcmd_timeout; 634 635 do_ocr = 0; 636 /* 637 * Copy the data back into callers buffer 638 */ 639 memcpy(eli, sc->el_info_mem, sizeof(struct mrsas_evt_log_info)); 640 mrsas_free_evt_log_info_cmd(sc); 641 642 dcmd_timeout: 643 if (do_ocr) 644 sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR; 645 else 646 mrsas_release_mfi_cmd(cmd); 647 648 return retcode; 649 } 650 651 /* 652 * mrsas_register_aen: Register for asynchronous event notification 653 * @sc: Adapter soft state 654 * @seq_num: Starting sequence number 655 * @class_locale: Class of the event 656 * 657 * This function subscribes for events beyond the @seq_num 658 * and type @class_locale. 659 * 660 */ 661 static int 662 mrsas_register_aen(struct mrsas_softc *sc, u_int32_t seq_num, 663 u_int32_t class_locale_word) 664 { 665 int ret_val; 666 struct mrsas_mfi_cmd *cmd; 667 struct mrsas_dcmd_frame *dcmd; 668 union mrsas_evt_class_locale curr_aen; 669 union mrsas_evt_class_locale prev_aen; 670 671 /* 672 * If there an AEN pending already (aen_cmd), check if the 673 * class_locale of that pending AEN is inclusive of the new AEN 674 * request we currently have. If it is, then we don't have to do 675 * anything. In other words, whichever events the current AEN request 676 * is subscribing to, have already been subscribed to. If the old_cmd 677 * is _not_ inclusive, then we have to abort that command, form a 678 * class_locale that is superset of both old and current and re-issue 679 * to the FW 680 */ 681 682 curr_aen.word = class_locale_word; 683 684 if (sc->aen_cmd) { 685 prev_aen.word = le32toh(sc->aen_cmd->frame->dcmd.mbox.w[1]); 686 687 /* 688 * A class whose enum value is smaller is inclusive of all 689 * higher values. If a PROGRESS (= -1) was previously 690 * registered, then a new registration requests for higher 691 * classes need not be sent to FW. They are automatically 692 * included. Locale numbers don't have such hierarchy. They 693 * are bitmap values 694 */ 695 if ((prev_aen.members.class <= curr_aen.members.class) && 696 !((prev_aen.members.locale & curr_aen.members.locale) ^ 697 curr_aen.members.locale)) { 698 /* 699 * Previously issued event registration includes 700 * current request. Nothing to do. 701 */ 702 return 0; 703 } else { 704 curr_aen.members.locale |= prev_aen.members.locale; 705 706 if (prev_aen.members.class < curr_aen.members.class) 707 curr_aen.members.class = prev_aen.members.class; 708 709 sc->aen_cmd->abort_aen = 1; 710 ret_val = mrsas_issue_blocked_abort_cmd(sc, 711 sc->aen_cmd); 712 713 if (ret_val) { 714 printf("mrsas: Failed to abort previous AEN command\n"); 715 return ret_val; 716 } else 717 sc->aen_cmd = NULL; 718 } 719 } 720 cmd = mrsas_get_mfi_cmd(sc); 721 if (!cmd) 722 return ENOMEM; 723 724 dcmd = &cmd->frame->dcmd; 725 726 memset(sc->evt_detail_mem, 0, sizeof(struct mrsas_evt_detail)); 727 728 /* 729 * Prepare DCMD for aen registration 730 */ 731 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 732 733 dcmd->cmd = MFI_CMD_DCMD; 734 dcmd->cmd_status = 0x0; 735 dcmd->sge_count = 1; 736 dcmd->flags = htole16(MFI_FRAME_DIR_READ); 737 dcmd->timeout = 0; 738 dcmd->pad_0 = 0; 739 dcmd->data_xfer_len = htole32(sizeof(struct mrsas_evt_detail)); 740 dcmd->opcode = htole32(MR_DCMD_CTRL_EVENT_WAIT); 741 dcmd->mbox.w[0] = htole32(seq_num); 742 sc->last_seq_num = seq_num; 743 dcmd->mbox.w[1] = htole32(curr_aen.word); 744 dcmd->sgl.sge32[0].phys_addr = htole32((u_int32_t)sc->evt_detail_phys_addr & 0xFFFFFFFF); 745 dcmd->sgl.sge32[0].length = htole32(sizeof(struct mrsas_evt_detail)); 746 747 if (sc->aen_cmd != NULL) { 748 mrsas_release_mfi_cmd(cmd); 749 return 0; 750 } 751 /* 752 * Store reference to the cmd used to register for AEN. When an 753 * application wants us to register for AEN, we have to abort this 754 * cmd and re-register with a new EVENT LOCALE supplied by that app 755 */ 756 sc->aen_cmd = cmd; 757 758 /* 759 * Issue the aen registration frame 760 */ 761 if (mrsas_issue_dcmd(sc, cmd)) { 762 device_printf(sc->mrsas_dev, "Cannot issue AEN DCMD command.\n"); 763 return (1); 764 } 765 return 0; 766 } 767 768 /* 769 * mrsas_start_aen: Subscribes to AEN during driver load time 770 * @instance: Adapter soft state 771 */ 772 static int 773 mrsas_start_aen(struct mrsas_softc *sc) 774 { 775 struct mrsas_evt_log_info eli; 776 union mrsas_evt_class_locale class_locale; 777 778 /* Get the latest sequence number from FW */ 779 780 memset(&eli, 0, sizeof(eli)); 781 782 if (mrsas_get_seq_num(sc, &eli)) 783 return -1; 784 785 /* Register AEN with FW for latest sequence number plus 1 */ 786 class_locale.members.reserved = 0; 787 class_locale.members.locale = MR_EVT_LOCALE_ALL; 788 class_locale.members.class = MR_EVT_CLASS_DEBUG; 789 790 return mrsas_register_aen(sc, eli.newest_seq_num + 1, 791 class_locale.word); 792 793 } 794 795 /* 796 * mrsas_setup_msix: Allocate MSI-x vectors 797 * @sc: adapter soft state 798 */ 799 static int 800 mrsas_setup_msix(struct mrsas_softc *sc) 801 { 802 int i; 803 804 for (i = 0; i < sc->msix_vectors; i++) { 805 sc->irq_context[i].sc = sc; 806 sc->irq_context[i].MSIxIndex = i; 807 sc->irq_id[i] = i + 1; 808 sc->mrsas_irq[i] = bus_alloc_resource_any 809 (sc->mrsas_dev, SYS_RES_IRQ, &sc->irq_id[i] 810 ,RF_ACTIVE); 811 if (sc->mrsas_irq[i] == NULL) { 812 device_printf(sc->mrsas_dev, "Can't allocate MSI-x\n"); 813 goto irq_alloc_failed; 814 } 815 if (bus_setup_intr(sc->mrsas_dev, 816 sc->mrsas_irq[i], 817 INTR_MPSAFE | INTR_TYPE_CAM, 818 NULL, mrsas_isr, &sc->irq_context[i], 819 &sc->intr_handle[i])) { 820 device_printf(sc->mrsas_dev, 821 "Cannot set up MSI-x interrupt handler\n"); 822 goto irq_alloc_failed; 823 } 824 } 825 return SUCCESS; 826 827 irq_alloc_failed: 828 mrsas_teardown_intr(sc); 829 return (FAIL); 830 } 831 832 /* 833 * mrsas_allocate_msix: Setup MSI-x vectors 834 * @sc: adapter soft state 835 */ 836 static int 837 mrsas_allocate_msix(struct mrsas_softc *sc) 838 { 839 if (pci_alloc_msix(sc->mrsas_dev, &sc->msix_vectors) == 0) { 840 device_printf(sc->mrsas_dev, "Using MSI-X with %d number" 841 " of vectors\n", sc->msix_vectors); 842 } else { 843 device_printf(sc->mrsas_dev, "MSI-x setup failed\n"); 844 goto irq_alloc_failed; 845 } 846 return SUCCESS; 847 848 irq_alloc_failed: 849 mrsas_teardown_intr(sc); 850 return (FAIL); 851 } 852 853 /* 854 * mrsas_attach: PCI entry point 855 * input: pointer to device struct 856 * 857 * Performs setup of PCI and registers, initializes mutexes and linked lists, 858 * registers interrupts and CAM, and initializes the adapter/controller to 859 * its proper state. 860 */ 861 static int 862 mrsas_attach(device_t dev) 863 { 864 struct mrsas_softc *sc = device_get_softc(dev); 865 uint32_t cmd, error; 866 867 memset(sc, 0, sizeof(struct mrsas_softc)); 868 869 /* Look up our softc and initialize its fields. */ 870 sc->mrsas_dev = dev; 871 sc->device_id = pci_get_device(dev); 872 873 switch (sc->device_id) { 874 case MRSAS_INVADER: 875 case MRSAS_FURY: 876 case MRSAS_INTRUDER: 877 case MRSAS_INTRUDER_24: 878 case MRSAS_CUTLASS_52: 879 case MRSAS_CUTLASS_53: 880 sc->mrsas_gen3_ctrl = 1; 881 break; 882 case MRSAS_VENTURA: 883 case MRSAS_CRUSADER: 884 case MRSAS_HARPOON: 885 case MRSAS_TOMCAT: 886 case MRSAS_VENTURA_4PORT: 887 case MRSAS_CRUSADER_4PORT: 888 sc->is_ventura = true; 889 break; 890 case MRSAS_AERO_10E1: 891 case MRSAS_AERO_10E5: 892 device_printf(dev, "Adapter is in configurable secure mode\n"); 893 case MRSAS_AERO_10E2: 894 case MRSAS_AERO_10E6: 895 sc->is_aero = true; 896 break; 897 case MRSAS_AERO_10E0: 898 case MRSAS_AERO_10E3: 899 case MRSAS_AERO_10E4: 900 case MRSAS_AERO_10E7: 901 device_printf(dev, "Adapter is in non-secure mode\n"); 902 return SUCCESS; 903 } 904 905 mrsas_get_tunables(sc); 906 907 /* 908 * Set up PCI and registers 909 */ 910 cmd = pci_read_config(dev, PCIR_COMMAND, 2); 911 /* Force the busmaster enable bit on. */ 912 cmd |= PCIM_CMD_BUSMASTEREN; 913 pci_write_config(dev, PCIR_COMMAND, cmd, 2); 914 915 /* For Ventura/Aero system registers are mapped to BAR0 */ 916 if (sc->is_ventura || sc->is_aero) 917 sc->reg_res_id = PCIR_BAR(0); /* BAR0 offset */ 918 else 919 sc->reg_res_id = PCIR_BAR(1); /* BAR1 offset */ 920 921 if ((sc->reg_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 922 &(sc->reg_res_id), RF_ACTIVE)) 923 == NULL) { 924 device_printf(dev, "Cannot allocate PCI registers\n"); 925 goto attach_fail; 926 } 927 sc->bus_tag = rman_get_bustag(sc->reg_res); 928 sc->bus_handle = rman_get_bushandle(sc->reg_res); 929 930 /* Intialize mutexes */ 931 mtx_init(&sc->sim_lock, "mrsas_sim_lock", NULL, MTX_DEF); 932 mtx_init(&sc->pci_lock, "mrsas_pci_lock", NULL, MTX_DEF); 933 mtx_init(&sc->io_lock, "mrsas_io_lock", NULL, MTX_DEF); 934 mtx_init(&sc->aen_lock, "mrsas_aen_lock", NULL, MTX_DEF); 935 mtx_init(&sc->ioctl_lock, "mrsas_ioctl_lock", NULL, MTX_SPIN); 936 mtx_init(&sc->mpt_cmd_pool_lock, "mrsas_mpt_cmd_pool_lock", NULL, MTX_DEF); 937 mtx_init(&sc->mfi_cmd_pool_lock, "mrsas_mfi_cmd_pool_lock", NULL, MTX_DEF); 938 mtx_init(&sc->raidmap_lock, "mrsas_raidmap_lock", NULL, MTX_DEF); 939 mtx_init(&sc->stream_lock, "mrsas_stream_lock", NULL, MTX_DEF); 940 941 /* Intialize linked list */ 942 TAILQ_INIT(&sc->mrsas_mpt_cmd_list_head); 943 TAILQ_INIT(&sc->mrsas_mfi_cmd_list_head); 944 945 mrsas_atomic_set(&sc->fw_outstanding, 0); 946 mrsas_atomic_set(&sc->target_reset_outstanding, 0); 947 mrsas_atomic_set(&sc->prp_count, 0); 948 mrsas_atomic_set(&sc->sge_holes, 0); 949 950 sc->io_cmds_highwater = 0; 951 952 sc->adprecovery = MRSAS_HBA_OPERATIONAL; 953 sc->UnevenSpanSupport = 0; 954 955 sc->msix_enable = 0; 956 957 /* Initialize Firmware */ 958 if (mrsas_init_fw(sc) != SUCCESS) { 959 goto attach_fail_fw; 960 } 961 /* Register mrsas to CAM layer */ 962 if ((mrsas_cam_attach(sc) != SUCCESS)) { 963 goto attach_fail_cam; 964 } 965 /* Register IRQs */ 966 if (mrsas_setup_irq(sc) != SUCCESS) { 967 goto attach_fail_irq; 968 } 969 error = mrsas_kproc_create(mrsas_ocr_thread, sc, 970 &sc->ocr_thread, 0, 0, "mrsas_ocr%d", 971 device_get_unit(sc->mrsas_dev)); 972 if (error) { 973 device_printf(sc->mrsas_dev, "Error %d starting OCR thread\n", error); 974 goto attach_fail_ocr_thread; 975 } 976 /* 977 * After FW initialization and OCR thread creation 978 * we will defer the cdev creation, AEN setup on ICH callback 979 */ 980 sc->mrsas_ich.ich_func = mrsas_ich_startup; 981 sc->mrsas_ich.ich_arg = sc; 982 if (config_intrhook_establish(&sc->mrsas_ich) != 0) { 983 device_printf(sc->mrsas_dev, "Config hook is already established\n"); 984 } 985 mrsas_setup_sysctl(sc); 986 return SUCCESS; 987 988 attach_fail_ocr_thread: 989 if (sc->ocr_thread_active) 990 wakeup(&sc->ocr_chan); 991 attach_fail_irq: 992 mrsas_teardown_intr(sc); 993 attach_fail_cam: 994 mrsas_cam_detach(sc); 995 attach_fail_fw: 996 /* if MSIX vector is allocated and FW Init FAILED then release MSIX */ 997 if (sc->msix_enable == 1) 998 pci_release_msi(sc->mrsas_dev); 999 mrsas_free_mem(sc); 1000 mtx_destroy(&sc->sim_lock); 1001 mtx_destroy(&sc->aen_lock); 1002 mtx_destroy(&sc->pci_lock); 1003 mtx_destroy(&sc->io_lock); 1004 mtx_destroy(&sc->ioctl_lock); 1005 mtx_destroy(&sc->mpt_cmd_pool_lock); 1006 mtx_destroy(&sc->mfi_cmd_pool_lock); 1007 mtx_destroy(&sc->raidmap_lock); 1008 mtx_destroy(&sc->stream_lock); 1009 attach_fail: 1010 if (sc->reg_res) { 1011 bus_release_resource(sc->mrsas_dev, SYS_RES_MEMORY, 1012 sc->reg_res_id, sc->reg_res); 1013 } 1014 return (ENXIO); 1015 } 1016 1017 /* 1018 * Interrupt config hook 1019 */ 1020 static void 1021 mrsas_ich_startup(void *arg) 1022 { 1023 int i = 0; 1024 struct mrsas_softc *sc = (struct mrsas_softc *)arg; 1025 1026 /* 1027 * Intialize a counting Semaphore to take care no. of concurrent IOCTLs 1028 */ 1029 sema_init(&sc->ioctl_count_sema, MRSAS_MAX_IOCTL_CMDS, 1030 IOCTL_SEMA_DESCRIPTION); 1031 1032 /* Create a /dev entry for mrsas controller. */ 1033 sc->mrsas_cdev = make_dev(&mrsas_cdevsw, device_get_unit(sc->mrsas_dev), UID_ROOT, 1034 GID_OPERATOR, (S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP), "mrsas%u", 1035 device_get_unit(sc->mrsas_dev)); 1036 1037 if (device_get_unit(sc->mrsas_dev) == 0) { 1038 make_dev_alias_p(MAKEDEV_CHECKNAME, 1039 &sc->mrsas_linux_emulator_cdev, sc->mrsas_cdev, 1040 "megaraid_sas_ioctl_node"); 1041 } 1042 if (sc->mrsas_cdev) 1043 sc->mrsas_cdev->si_drv1 = sc; 1044 1045 /* 1046 * Add this controller to mrsas_mgmt_info structure so that it can be 1047 * exported to management applications 1048 */ 1049 if (device_get_unit(sc->mrsas_dev) == 0) 1050 memset(&mrsas_mgmt_info, 0, sizeof(mrsas_mgmt_info)); 1051 1052 mrsas_mgmt_info.count++; 1053 mrsas_mgmt_info.sc_ptr[mrsas_mgmt_info.max_index] = sc; 1054 mrsas_mgmt_info.max_index++; 1055 1056 /* Enable Interrupts */ 1057 mrsas_enable_intr(sc); 1058 1059 /* Call DCMD get_pd_info for all system PDs */ 1060 for (i = 0; i < MRSAS_MAX_PD; i++) { 1061 if ((sc->target_list[i].target_id != 0xffff) && 1062 sc->pd_info_mem) 1063 mrsas_get_pd_info(sc, sc->target_list[i].target_id); 1064 } 1065 1066 /* Initiate AEN (Asynchronous Event Notification) */ 1067 if (mrsas_start_aen(sc)) { 1068 device_printf(sc->mrsas_dev, "Error: AEN registration FAILED !!! " 1069 "Further events from the controller will not be communicated.\n" 1070 "Either there is some problem in the controller" 1071 "or the controller does not support AEN.\n" 1072 "Please contact to the SUPPORT TEAM if the problem persists\n"); 1073 } 1074 if (sc->mrsas_ich.ich_arg != NULL) { 1075 device_printf(sc->mrsas_dev, "Disestablish mrsas intr hook\n"); 1076 config_intrhook_disestablish(&sc->mrsas_ich); 1077 sc->mrsas_ich.ich_arg = NULL; 1078 } 1079 } 1080 1081 /* 1082 * mrsas_detach: De-allocates and teardown resources 1083 * input: pointer to device struct 1084 * 1085 * This function is the entry point for device disconnect and detach. 1086 * It performs memory de-allocations, shutdown of the controller and various 1087 * teardown and destroy resource functions. 1088 */ 1089 static int 1090 mrsas_detach(device_t dev) 1091 { 1092 struct mrsas_softc *sc; 1093 int i = 0; 1094 1095 sc = device_get_softc(dev); 1096 sc->remove_in_progress = 1; 1097 1098 /* Destroy the character device so no other IOCTL will be handled */ 1099 if ((device_get_unit(dev) == 0) && sc->mrsas_linux_emulator_cdev) 1100 destroy_dev(sc->mrsas_linux_emulator_cdev); 1101 destroy_dev(sc->mrsas_cdev); 1102 1103 /* 1104 * Take the instance off the instance array. Note that we will not 1105 * decrement the max_index. We let this array be sparse array 1106 */ 1107 for (i = 0; i < mrsas_mgmt_info.max_index; i++) { 1108 if (mrsas_mgmt_info.sc_ptr[i] == sc) { 1109 mrsas_mgmt_info.count--; 1110 mrsas_mgmt_info.sc_ptr[i] = NULL; 1111 break; 1112 } 1113 } 1114 1115 if (sc->ocr_thread_active) 1116 wakeup(&sc->ocr_chan); 1117 while (sc->reset_in_progress) { 1118 i++; 1119 if (!(i % MRSAS_RESET_NOTICE_INTERVAL)) { 1120 mrsas_dprint(sc, MRSAS_INFO, 1121 "[%2d]waiting for OCR to be finished from %s\n", i, __func__); 1122 } 1123 pause("mr_shutdown", hz); 1124 } 1125 i = 0; 1126 while (sc->ocr_thread_active) { 1127 i++; 1128 if (!(i % MRSAS_RESET_NOTICE_INTERVAL)) { 1129 mrsas_dprint(sc, MRSAS_INFO, 1130 "[%2d]waiting for " 1131 "mrsas_ocr thread to quit ocr %d\n", i, 1132 sc->ocr_thread_active); 1133 } 1134 pause("mr_shutdown", hz); 1135 } 1136 mrsas_flush_cache(sc); 1137 mrsas_shutdown_ctlr(sc, MR_DCMD_CTRL_SHUTDOWN); 1138 mrsas_disable_intr(sc); 1139 1140 if ((sc->is_ventura || sc->is_aero) && sc->streamDetectByLD) { 1141 for (i = 0; i < MAX_LOGICAL_DRIVES_EXT; ++i) 1142 free(sc->streamDetectByLD[i], M_MRSAS); 1143 free(sc->streamDetectByLD, M_MRSAS); 1144 sc->streamDetectByLD = NULL; 1145 } 1146 1147 mrsas_cam_detach(sc); 1148 mrsas_teardown_intr(sc); 1149 mrsas_free_mem(sc); 1150 mtx_destroy(&sc->sim_lock); 1151 mtx_destroy(&sc->aen_lock); 1152 mtx_destroy(&sc->pci_lock); 1153 mtx_destroy(&sc->io_lock); 1154 mtx_destroy(&sc->ioctl_lock); 1155 mtx_destroy(&sc->mpt_cmd_pool_lock); 1156 mtx_destroy(&sc->mfi_cmd_pool_lock); 1157 mtx_destroy(&sc->raidmap_lock); 1158 mtx_destroy(&sc->stream_lock); 1159 1160 /* Wait for all the semaphores to be released */ 1161 while (sema_value(&sc->ioctl_count_sema) != MRSAS_MAX_IOCTL_CMDS) 1162 pause("mr_shutdown", hz); 1163 1164 /* Destroy the counting semaphore created for Ioctl */ 1165 sema_destroy(&sc->ioctl_count_sema); 1166 1167 if (sc->reg_res) { 1168 bus_release_resource(sc->mrsas_dev, 1169 SYS_RES_MEMORY, sc->reg_res_id, sc->reg_res); 1170 } 1171 if (sc->sysctl_tree != NULL) 1172 sysctl_ctx_free(&sc->sysctl_ctx); 1173 1174 return (0); 1175 } 1176 1177 static int 1178 mrsas_shutdown(device_t dev) 1179 { 1180 struct mrsas_softc *sc; 1181 int i; 1182 1183 sc = device_get_softc(dev); 1184 sc->remove_in_progress = 1; 1185 if (!KERNEL_PANICKED()) { 1186 if (sc->ocr_thread_active) 1187 wakeup(&sc->ocr_chan); 1188 i = 0; 1189 while (sc->reset_in_progress && i < 15) { 1190 i++; 1191 if ((i % MRSAS_RESET_NOTICE_INTERVAL) == 0) { 1192 mrsas_dprint(sc, MRSAS_INFO, 1193 "[%2d]waiting for OCR to be finished " 1194 "from %s\n", i, __func__); 1195 } 1196 pause("mr_shutdown", hz); 1197 } 1198 if (sc->reset_in_progress) { 1199 mrsas_dprint(sc, MRSAS_INFO, 1200 "gave up waiting for OCR to be finished\n"); 1201 } 1202 } 1203 1204 mrsas_flush_cache(sc); 1205 mrsas_shutdown_ctlr(sc, MR_DCMD_CTRL_SHUTDOWN); 1206 mrsas_disable_intr(sc); 1207 return (0); 1208 } 1209 1210 /* 1211 * mrsas_free_mem: Frees allocated memory 1212 * input: Adapter instance soft state 1213 * 1214 * This function is called from mrsas_detach() to free previously allocated 1215 * memory. 1216 */ 1217 void 1218 mrsas_free_mem(struct mrsas_softc *sc) 1219 { 1220 int i; 1221 u_int32_t max_fw_cmds; 1222 struct mrsas_mfi_cmd *mfi_cmd; 1223 struct mrsas_mpt_cmd *mpt_cmd; 1224 1225 /* 1226 * Free RAID map memory 1227 */ 1228 for (i = 0; i < 2; i++) { 1229 if (sc->raidmap_phys_addr[i]) 1230 bus_dmamap_unload(sc->raidmap_tag[i], sc->raidmap_dmamap[i]); 1231 if (sc->raidmap_mem[i] != NULL) 1232 bus_dmamem_free(sc->raidmap_tag[i], sc->raidmap_mem[i], sc->raidmap_dmamap[i]); 1233 if (sc->raidmap_tag[i] != NULL) 1234 bus_dma_tag_destroy(sc->raidmap_tag[i]); 1235 1236 if (sc->ld_drv_map[i] != NULL) 1237 free(sc->ld_drv_map[i], M_MRSAS); 1238 } 1239 for (i = 0; i < 2; i++) { 1240 if (sc->jbodmap_phys_addr[i]) 1241 bus_dmamap_unload(sc->jbodmap_tag[i], sc->jbodmap_dmamap[i]); 1242 if (sc->jbodmap_mem[i] != NULL) 1243 bus_dmamem_free(sc->jbodmap_tag[i], sc->jbodmap_mem[i], sc->jbodmap_dmamap[i]); 1244 if (sc->jbodmap_tag[i] != NULL) 1245 bus_dma_tag_destroy(sc->jbodmap_tag[i]); 1246 } 1247 /* 1248 * Free version buffer memory 1249 */ 1250 if (sc->verbuf_phys_addr) 1251 bus_dmamap_unload(sc->verbuf_tag, sc->verbuf_dmamap); 1252 if (sc->verbuf_mem != NULL) 1253 bus_dmamem_free(sc->verbuf_tag, sc->verbuf_mem, sc->verbuf_dmamap); 1254 if (sc->verbuf_tag != NULL) 1255 bus_dma_tag_destroy(sc->verbuf_tag); 1256 1257 /* 1258 * Free sense buffer memory 1259 */ 1260 if (sc->sense_phys_addr) 1261 bus_dmamap_unload(sc->sense_tag, sc->sense_dmamap); 1262 if (sc->sense_mem != NULL) 1263 bus_dmamem_free(sc->sense_tag, sc->sense_mem, sc->sense_dmamap); 1264 if (sc->sense_tag != NULL) 1265 bus_dma_tag_destroy(sc->sense_tag); 1266 1267 /* 1268 * Free chain frame memory 1269 */ 1270 if (sc->chain_frame_phys_addr) 1271 bus_dmamap_unload(sc->chain_frame_tag, sc->chain_frame_dmamap); 1272 if (sc->chain_frame_mem != NULL) 1273 bus_dmamem_free(sc->chain_frame_tag, sc->chain_frame_mem, sc->chain_frame_dmamap); 1274 if (sc->chain_frame_tag != NULL) 1275 bus_dma_tag_destroy(sc->chain_frame_tag); 1276 1277 /* 1278 * Free IO Request memory 1279 */ 1280 if (sc->io_request_phys_addr) 1281 bus_dmamap_unload(sc->io_request_tag, sc->io_request_dmamap); 1282 if (sc->io_request_mem != NULL) 1283 bus_dmamem_free(sc->io_request_tag, sc->io_request_mem, sc->io_request_dmamap); 1284 if (sc->io_request_tag != NULL) 1285 bus_dma_tag_destroy(sc->io_request_tag); 1286 1287 /* 1288 * Free Reply Descriptor memory 1289 */ 1290 if (sc->reply_desc_phys_addr) 1291 bus_dmamap_unload(sc->reply_desc_tag, sc->reply_desc_dmamap); 1292 if (sc->reply_desc_mem != NULL) 1293 bus_dmamem_free(sc->reply_desc_tag, sc->reply_desc_mem, sc->reply_desc_dmamap); 1294 if (sc->reply_desc_tag != NULL) 1295 bus_dma_tag_destroy(sc->reply_desc_tag); 1296 1297 /* 1298 * Free event detail memory 1299 */ 1300 if (sc->evt_detail_phys_addr) 1301 bus_dmamap_unload(sc->evt_detail_tag, sc->evt_detail_dmamap); 1302 if (sc->evt_detail_mem != NULL) 1303 bus_dmamem_free(sc->evt_detail_tag, sc->evt_detail_mem, sc->evt_detail_dmamap); 1304 if (sc->evt_detail_tag != NULL) 1305 bus_dma_tag_destroy(sc->evt_detail_tag); 1306 1307 /* 1308 * Free PD info memory 1309 */ 1310 if (sc->pd_info_phys_addr) 1311 bus_dmamap_unload(sc->pd_info_tag, sc->pd_info_dmamap); 1312 if (sc->pd_info_mem != NULL) 1313 bus_dmamem_free(sc->pd_info_tag, sc->pd_info_mem, sc->pd_info_dmamap); 1314 if (sc->pd_info_tag != NULL) 1315 bus_dma_tag_destroy(sc->pd_info_tag); 1316 1317 /* 1318 * Free MFI frames 1319 */ 1320 if (sc->mfi_cmd_list) { 1321 for (i = 0; i < MRSAS_MAX_MFI_CMDS; i++) { 1322 mfi_cmd = sc->mfi_cmd_list[i]; 1323 mrsas_free_frame(sc, mfi_cmd); 1324 } 1325 } 1326 if (sc->mficmd_frame_tag != NULL) 1327 bus_dma_tag_destroy(sc->mficmd_frame_tag); 1328 1329 /* 1330 * Free MPT internal command list 1331 */ 1332 max_fw_cmds = sc->max_fw_cmds; 1333 if (sc->mpt_cmd_list) { 1334 for (i = 0; i < max_fw_cmds; i++) { 1335 mpt_cmd = sc->mpt_cmd_list[i]; 1336 bus_dmamap_destroy(sc->data_tag, mpt_cmd->data_dmamap); 1337 free(sc->mpt_cmd_list[i], M_MRSAS); 1338 } 1339 free(sc->mpt_cmd_list, M_MRSAS); 1340 sc->mpt_cmd_list = NULL; 1341 } 1342 /* 1343 * Free MFI internal command list 1344 */ 1345 1346 if (sc->mfi_cmd_list) { 1347 for (i = 0; i < MRSAS_MAX_MFI_CMDS; i++) { 1348 free(sc->mfi_cmd_list[i], M_MRSAS); 1349 } 1350 free(sc->mfi_cmd_list, M_MRSAS); 1351 sc->mfi_cmd_list = NULL; 1352 } 1353 /* 1354 * Free request descriptor memory 1355 */ 1356 free(sc->req_desc, M_MRSAS); 1357 sc->req_desc = NULL; 1358 1359 /* 1360 * Destroy parent tag 1361 */ 1362 if (sc->mrsas_parent_tag != NULL) 1363 bus_dma_tag_destroy(sc->mrsas_parent_tag); 1364 1365 /* 1366 * Free ctrl_info memory 1367 */ 1368 if (sc->ctrl_info != NULL) 1369 free(sc->ctrl_info, M_MRSAS); 1370 } 1371 1372 /* 1373 * mrsas_teardown_intr: Teardown interrupt 1374 * input: Adapter instance soft state 1375 * 1376 * This function is called from mrsas_detach() to teardown and release bus 1377 * interrupt resourse. 1378 */ 1379 void 1380 mrsas_teardown_intr(struct mrsas_softc *sc) 1381 { 1382 int i; 1383 1384 if (!sc->msix_enable) { 1385 if (sc->intr_handle[0]) 1386 bus_teardown_intr(sc->mrsas_dev, sc->mrsas_irq[0], sc->intr_handle[0]); 1387 if (sc->mrsas_irq[0] != NULL) 1388 bus_release_resource(sc->mrsas_dev, SYS_RES_IRQ, 1389 sc->irq_id[0], sc->mrsas_irq[0]); 1390 sc->intr_handle[0] = NULL; 1391 } else { 1392 for (i = 0; i < sc->msix_vectors; i++) { 1393 if (sc->intr_handle[i]) 1394 bus_teardown_intr(sc->mrsas_dev, sc->mrsas_irq[i], 1395 sc->intr_handle[i]); 1396 1397 if (sc->mrsas_irq[i] != NULL) 1398 bus_release_resource(sc->mrsas_dev, SYS_RES_IRQ, 1399 sc->irq_id[i], sc->mrsas_irq[i]); 1400 1401 sc->intr_handle[i] = NULL; 1402 } 1403 pci_release_msi(sc->mrsas_dev); 1404 } 1405 1406 } 1407 1408 /* 1409 * mrsas_suspend: Suspend entry point 1410 * input: Device struct pointer 1411 * 1412 * This function is the entry point for system suspend from the OS. 1413 */ 1414 static int 1415 mrsas_suspend(device_t dev) 1416 { 1417 /* This will be filled when the driver will have hibernation support */ 1418 return (0); 1419 } 1420 1421 /* 1422 * mrsas_resume: Resume entry point 1423 * input: Device struct pointer 1424 * 1425 * This function is the entry point for system resume from the OS. 1426 */ 1427 static int 1428 mrsas_resume(device_t dev) 1429 { 1430 /* This will be filled when the driver will have hibernation support */ 1431 return (0); 1432 } 1433 1434 /** 1435 * mrsas_get_softc_instance: Find softc instance based on cmd type 1436 * 1437 * This function will return softc instance based on cmd type. 1438 * In some case, application fire ioctl on required management instance and 1439 * do not provide host_no. Use cdev->si_drv1 to get softc instance for those 1440 * case, else get the softc instance from host_no provided by application in 1441 * user data. 1442 */ 1443 1444 static struct mrsas_softc * 1445 mrsas_get_softc_instance(struct cdev *dev, u_long cmd, caddr_t arg) 1446 { 1447 struct mrsas_softc *sc = NULL; 1448 struct mrsas_iocpacket *user_ioc = (struct mrsas_iocpacket *)arg; 1449 1450 if (cmd == MRSAS_IOC_GET_PCI_INFO) { 1451 sc = dev->si_drv1; 1452 } else { 1453 /* 1454 * get the Host number & the softc from data sent by the 1455 * Application 1456 */ 1457 sc = mrsas_mgmt_info.sc_ptr[user_ioc->host_no]; 1458 if (sc == NULL) 1459 printf("There is no Controller number %d\n", 1460 user_ioc->host_no); 1461 else if (user_ioc->host_no >= mrsas_mgmt_info.max_index) 1462 mrsas_dprint(sc, MRSAS_FAULT, 1463 "Invalid Controller number %d\n", user_ioc->host_no); 1464 } 1465 1466 return sc; 1467 } 1468 1469 /* 1470 * mrsas_ioctl: IOCtl commands entry point. 1471 * 1472 * This function is the entry point for IOCtls from the OS. It calls the 1473 * appropriate function for processing depending on the command received. 1474 */ 1475 static int 1476 mrsas_ioctl(struct cdev *dev, u_long cmd, caddr_t arg, int flag, 1477 struct thread *td) 1478 { 1479 struct mrsas_softc *sc; 1480 int ret = 0, i = 0; 1481 MRSAS_DRV_PCI_INFORMATION *pciDrvInfo; 1482 1483 sc = mrsas_get_softc_instance(dev, cmd, arg); 1484 if (!sc) 1485 return ENOENT; 1486 1487 if (sc->remove_in_progress || 1488 (sc->adprecovery == MRSAS_HW_CRITICAL_ERROR)) { 1489 mrsas_dprint(sc, MRSAS_INFO, 1490 "Either driver remove or shutdown called or " 1491 "HW is in unrecoverable critical error state.\n"); 1492 return ENOENT; 1493 } 1494 mtx_lock_spin(&sc->ioctl_lock); 1495 if (!sc->reset_in_progress) { 1496 mtx_unlock_spin(&sc->ioctl_lock); 1497 goto do_ioctl; 1498 } 1499 mtx_unlock_spin(&sc->ioctl_lock); 1500 while (sc->reset_in_progress) { 1501 i++; 1502 if (!(i % MRSAS_RESET_NOTICE_INTERVAL)) { 1503 mrsas_dprint(sc, MRSAS_INFO, 1504 "[%2d]waiting for OCR to be finished from %s\n", i, __func__); 1505 } 1506 pause("mr_ioctl", hz); 1507 } 1508 1509 do_ioctl: 1510 switch (cmd) { 1511 case MRSAS_IOC_FIRMWARE_PASS_THROUGH64: 1512 #ifdef COMPAT_FREEBSD32 1513 case MRSAS_IOC_FIRMWARE_PASS_THROUGH32: 1514 #endif 1515 /* 1516 * Decrement the Ioctl counting Semaphore before getting an 1517 * mfi command 1518 */ 1519 sema_wait(&sc->ioctl_count_sema); 1520 1521 ret = mrsas_passthru(sc, (void *)arg, cmd); 1522 1523 /* Increment the Ioctl counting semaphore value */ 1524 sema_post(&sc->ioctl_count_sema); 1525 1526 break; 1527 case MRSAS_IOC_SCAN_BUS: 1528 ret = mrsas_bus_scan(sc); 1529 break; 1530 1531 case MRSAS_IOC_GET_PCI_INFO: 1532 pciDrvInfo = (MRSAS_DRV_PCI_INFORMATION *) arg; 1533 memset(pciDrvInfo, 0, sizeof(MRSAS_DRV_PCI_INFORMATION)); 1534 pciDrvInfo->busNumber = pci_get_bus(sc->mrsas_dev); 1535 pciDrvInfo->deviceNumber = pci_get_slot(sc->mrsas_dev); 1536 pciDrvInfo->functionNumber = pci_get_function(sc->mrsas_dev); 1537 pciDrvInfo->domainID = pci_get_domain(sc->mrsas_dev); 1538 mrsas_dprint(sc, MRSAS_INFO, "pci bus no: %d," 1539 "pci device no: %d, pci function no: %d," 1540 "pci domain ID: %d\n", 1541 pciDrvInfo->busNumber, pciDrvInfo->deviceNumber, 1542 pciDrvInfo->functionNumber, pciDrvInfo->domainID); 1543 ret = 0; 1544 break; 1545 1546 default: 1547 mrsas_dprint(sc, MRSAS_TRACE, "IOCTL command 0x%lx is not handled\n", cmd); 1548 ret = ENOENT; 1549 } 1550 1551 return (ret); 1552 } 1553 1554 /* 1555 * mrsas_poll: poll entry point for mrsas driver fd 1556 * 1557 * This function is the entry point for poll from the OS. It waits for some AEN 1558 * events to be triggered from the controller and notifies back. 1559 */ 1560 static int 1561 mrsas_poll(struct cdev *dev, int poll_events, struct thread *td) 1562 { 1563 struct mrsas_softc *sc; 1564 int revents = 0; 1565 1566 sc = dev->si_drv1; 1567 1568 if (poll_events & (POLLIN | POLLRDNORM)) { 1569 if (sc->mrsas_aen_triggered) { 1570 revents |= poll_events & (POLLIN | POLLRDNORM); 1571 } 1572 } 1573 if (revents == 0) { 1574 if (poll_events & (POLLIN | POLLRDNORM)) { 1575 mtx_lock(&sc->aen_lock); 1576 sc->mrsas_poll_waiting = 1; 1577 selrecord(td, &sc->mrsas_select); 1578 mtx_unlock(&sc->aen_lock); 1579 } 1580 } 1581 return revents; 1582 } 1583 1584 /* 1585 * mrsas_setup_irq: Set up interrupt 1586 * input: Adapter instance soft state 1587 * 1588 * This function sets up interrupts as a bus resource, with flags indicating 1589 * resource permitting contemporaneous sharing and for resource to activate 1590 * atomically. 1591 */ 1592 static int 1593 mrsas_setup_irq(struct mrsas_softc *sc) 1594 { 1595 if (sc->msix_enable && (mrsas_setup_msix(sc) == SUCCESS)) 1596 device_printf(sc->mrsas_dev, "MSI-x interrupts setup success\n"); 1597 1598 else { 1599 device_printf(sc->mrsas_dev, "Fall back to legacy interrupt\n"); 1600 sc->irq_context[0].sc = sc; 1601 sc->irq_context[0].MSIxIndex = 0; 1602 sc->irq_id[0] = 0; 1603 sc->mrsas_irq[0] = bus_alloc_resource_any(sc->mrsas_dev, 1604 SYS_RES_IRQ, &sc->irq_id[0], RF_SHAREABLE | RF_ACTIVE); 1605 if (sc->mrsas_irq[0] == NULL) { 1606 device_printf(sc->mrsas_dev, "Cannot allocate legcay" 1607 "interrupt\n"); 1608 return (FAIL); 1609 } 1610 if (bus_setup_intr(sc->mrsas_dev, sc->mrsas_irq[0], 1611 INTR_MPSAFE | INTR_TYPE_CAM, NULL, mrsas_isr, 1612 &sc->irq_context[0], &sc->intr_handle[0])) { 1613 device_printf(sc->mrsas_dev, "Cannot set up legacy" 1614 "interrupt\n"); 1615 return (FAIL); 1616 } 1617 } 1618 return (0); 1619 } 1620 1621 /* 1622 * mrsas_isr: ISR entry point 1623 * input: argument pointer 1624 * 1625 * This function is the interrupt service routine entry point. There are two 1626 * types of interrupts, state change interrupt and response interrupt. If an 1627 * interrupt is not ours, we just return. 1628 */ 1629 void 1630 mrsas_isr(void *arg) 1631 { 1632 struct mrsas_irq_context *irq_context = (struct mrsas_irq_context *)arg; 1633 struct mrsas_softc *sc = irq_context->sc; 1634 int status = 0; 1635 1636 if (sc->mask_interrupts) 1637 return; 1638 1639 if (!sc->msix_vectors) { 1640 status = mrsas_clear_intr(sc); 1641 if (!status) 1642 return; 1643 } 1644 /* If we are resetting, bail */ 1645 if (mrsas_test_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags)) { 1646 printf(" Entered into ISR when OCR is going active. \n"); 1647 mrsas_clear_intr(sc); 1648 return; 1649 } 1650 /* Process for reply request and clear response interrupt */ 1651 if (mrsas_complete_cmd(sc, irq_context->MSIxIndex) != SUCCESS) 1652 mrsas_clear_intr(sc); 1653 1654 return; 1655 } 1656 1657 /* 1658 * mrsas_complete_cmd: Process reply request 1659 * input: Adapter instance soft state 1660 * 1661 * This function is called from mrsas_isr() to process reply request and clear 1662 * response interrupt. Processing of the reply request entails walking 1663 * through the reply descriptor array for the command request pended from 1664 * Firmware. We look at the Function field to determine the command type and 1665 * perform the appropriate action. Before we return, we clear the response 1666 * interrupt. 1667 */ 1668 int 1669 mrsas_complete_cmd(struct mrsas_softc *sc, u_int32_t MSIxIndex) 1670 { 1671 Mpi2ReplyDescriptorsUnion_t *desc; 1672 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR *reply_desc; 1673 MRSAS_RAID_SCSI_IO_REQUEST *scsi_io_req; 1674 struct mrsas_mpt_cmd *cmd_mpt, *r1_cmd = NULL; 1675 struct mrsas_mfi_cmd *cmd_mfi; 1676 u_int8_t reply_descript_type, *sense; 1677 u_int16_t smid, num_completed; 1678 u_int8_t status, extStatus; 1679 union desc_value desc_val; 1680 PLD_LOAD_BALANCE_INFO lbinfo; 1681 u_int32_t device_id, data_length; 1682 int threshold_reply_count = 0; 1683 #if TM_DEBUG 1684 MR_TASK_MANAGE_REQUEST *mr_tm_req; 1685 MPI2_SCSI_TASK_MANAGE_REQUEST *mpi_tm_req; 1686 #endif 1687 1688 /* If we have a hardware error, not need to continue */ 1689 if (sc->adprecovery == MRSAS_HW_CRITICAL_ERROR) 1690 return (DONE); 1691 1692 desc = sc->reply_desc_mem; 1693 desc += ((MSIxIndex * sc->reply_alloc_sz) / sizeof(MPI2_REPLY_DESCRIPTORS_UNION)) 1694 + sc->last_reply_idx[MSIxIndex]; 1695 1696 reply_desc = (MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR *) desc; 1697 1698 desc_val.word = desc->Words; 1699 num_completed = 0; 1700 1701 reply_descript_type = reply_desc->ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 1702 1703 /* Find our reply descriptor for the command and process */ 1704 while ((desc_val.u.low != 0xFFFFFFFF) && (desc_val.u.high != 0xFFFFFFFF)) { 1705 smid = le16toh(reply_desc->SMID); 1706 cmd_mpt = sc->mpt_cmd_list[smid - 1]; 1707 scsi_io_req = (MRSAS_RAID_SCSI_IO_REQUEST *) cmd_mpt->io_request; 1708 1709 status = scsi_io_req->RaidContext.raid_context.status; 1710 extStatus = scsi_io_req->RaidContext.raid_context.exStatus; 1711 sense = cmd_mpt->sense; 1712 data_length = scsi_io_req->DataLength; 1713 1714 switch (scsi_io_req->Function) { 1715 case MPI2_FUNCTION_SCSI_TASK_MGMT: 1716 #if TM_DEBUG 1717 mr_tm_req = (MR_TASK_MANAGE_REQUEST *) cmd_mpt->io_request; 1718 mpi_tm_req = (MPI2_SCSI_TASK_MANAGE_REQUEST *) 1719 &mr_tm_req->TmRequest; 1720 device_printf(sc->mrsas_dev, "TM completion type 0x%X, " 1721 "TaskMID: 0x%X", mpi_tm_req->TaskType, mpi_tm_req->TaskMID); 1722 #endif 1723 wakeup_one((void *)&sc->ocr_chan); 1724 break; 1725 case MPI2_FUNCTION_SCSI_IO_REQUEST: /* Fast Path IO. */ 1726 device_id = cmd_mpt->ccb_ptr->ccb_h.target_id; 1727 lbinfo = &sc->load_balance_info[device_id]; 1728 /* R1 load balancing for READ */ 1729 if (cmd_mpt->load_balance == MRSAS_LOAD_BALANCE_FLAG) { 1730 mrsas_atomic_dec(&lbinfo->scsi_pending_cmds[cmd_mpt->pd_r1_lb]); 1731 cmd_mpt->load_balance &= ~MRSAS_LOAD_BALANCE_FLAG; 1732 } 1733 /* Fall thru and complete IO */ 1734 case MRSAS_MPI2_FUNCTION_LD_IO_REQUEST: 1735 if (cmd_mpt->r1_alt_dev_handle == MR_DEVHANDLE_INVALID) { 1736 mrsas_map_mpt_cmd_status(cmd_mpt, cmd_mpt->ccb_ptr, status, 1737 extStatus, le32toh(data_length), sense); 1738 mrsas_cmd_done(sc, cmd_mpt); 1739 mrsas_atomic_dec(&sc->fw_outstanding); 1740 } else { 1741 /* 1742 * If the peer Raid 1/10 fast path failed, 1743 * mark IO as failed to the scsi layer. 1744 * Overwrite the current status by the failed status 1745 * and make sure that if any command fails, 1746 * driver returns fail status to CAM. 1747 */ 1748 cmd_mpt->cmd_completed = 1; 1749 r1_cmd = cmd_mpt->peer_cmd; 1750 if (r1_cmd->cmd_completed) { 1751 if (r1_cmd->io_request->RaidContext.raid_context.status != MFI_STAT_OK) { 1752 status = r1_cmd->io_request->RaidContext.raid_context.status; 1753 extStatus = r1_cmd->io_request->RaidContext.raid_context.exStatus; 1754 data_length = r1_cmd->io_request->DataLength; 1755 sense = r1_cmd->sense; 1756 } 1757 r1_cmd->ccb_ptr = NULL; 1758 if (r1_cmd->callout_owner) { 1759 callout_stop(&r1_cmd->cm_callout); 1760 r1_cmd->callout_owner = false; 1761 } 1762 mrsas_release_mpt_cmd(r1_cmd); 1763 mrsas_atomic_dec(&sc->fw_outstanding); 1764 mrsas_map_mpt_cmd_status(cmd_mpt, cmd_mpt->ccb_ptr, status, 1765 extStatus, le32toh(data_length), sense); 1766 mrsas_cmd_done(sc, cmd_mpt); 1767 mrsas_atomic_dec(&sc->fw_outstanding); 1768 } 1769 } 1770 break; 1771 case MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST: /* MFI command */ 1772 cmd_mfi = sc->mfi_cmd_list[cmd_mpt->sync_cmd_idx]; 1773 /* 1774 * Make sure NOT TO release the mfi command from the called 1775 * function's context if it is fired with issue_polled call. 1776 * And also make sure that the issue_polled call should only be 1777 * used if INTERRUPT IS DISABLED. 1778 */ 1779 if (cmd_mfi->frame->hdr.flags & htole16(MFI_FRAME_DONT_POST_IN_REPLY_QUEUE)) 1780 mrsas_release_mfi_cmd(cmd_mfi); 1781 else 1782 mrsas_complete_mptmfi_passthru(sc, cmd_mfi, status); 1783 break; 1784 } 1785 1786 sc->last_reply_idx[MSIxIndex]++; 1787 if (sc->last_reply_idx[MSIxIndex] >= sc->reply_q_depth) 1788 sc->last_reply_idx[MSIxIndex] = 0; 1789 1790 desc->Words = ~((uint64_t)0x00); /* set it back to all 1791 * 0xFFFFFFFFs */ 1792 num_completed++; 1793 threshold_reply_count++; 1794 1795 /* Get the next reply descriptor */ 1796 if (!sc->last_reply_idx[MSIxIndex]) { 1797 desc = sc->reply_desc_mem; 1798 desc += ((MSIxIndex * sc->reply_alloc_sz) / sizeof(MPI2_REPLY_DESCRIPTORS_UNION)); 1799 } else 1800 desc++; 1801 1802 reply_desc = (MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR *) desc; 1803 desc_val.word = desc->Words; 1804 1805 reply_descript_type = reply_desc->ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 1806 1807 if (reply_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) 1808 break; 1809 1810 /* 1811 * Write to reply post index after completing threshold reply 1812 * count and still there are more replies in reply queue 1813 * pending to be completed. 1814 */ 1815 if (threshold_reply_count >= THRESHOLD_REPLY_COUNT) { 1816 if (sc->msix_enable) { 1817 if (sc->msix_combined) 1818 mrsas_write_reg(sc, sc->msix_reg_offset[MSIxIndex / 8], 1819 ((MSIxIndex & 0x7) << 24) | 1820 sc->last_reply_idx[MSIxIndex]); 1821 else 1822 mrsas_write_reg(sc, sc->msix_reg_offset[0], (MSIxIndex << 24) | 1823 sc->last_reply_idx[MSIxIndex]); 1824 } else 1825 mrsas_write_reg(sc, offsetof(mrsas_reg_set, 1826 reply_post_host_index), sc->last_reply_idx[0]); 1827 1828 threshold_reply_count = 0; 1829 } 1830 } 1831 1832 /* No match, just return */ 1833 if (num_completed == 0) 1834 return (DONE); 1835 1836 /* Clear response interrupt */ 1837 if (sc->msix_enable) { 1838 if (sc->msix_combined) { 1839 mrsas_write_reg(sc, sc->msix_reg_offset[MSIxIndex / 8], 1840 ((MSIxIndex & 0x7) << 24) | 1841 sc->last_reply_idx[MSIxIndex]); 1842 } else 1843 mrsas_write_reg(sc, sc->msix_reg_offset[0], (MSIxIndex << 24) | 1844 sc->last_reply_idx[MSIxIndex]); 1845 } else 1846 mrsas_write_reg(sc, offsetof(mrsas_reg_set, 1847 reply_post_host_index), sc->last_reply_idx[0]); 1848 1849 return (0); 1850 } 1851 1852 /* 1853 * mrsas_map_mpt_cmd_status: Allocate DMAable memory. 1854 * input: Adapter instance soft state 1855 * 1856 * This function is called from mrsas_complete_cmd(), for LD IO and FastPath IO. 1857 * It checks the command status and maps the appropriate CAM status for the 1858 * CCB. 1859 */ 1860 void 1861 mrsas_map_mpt_cmd_status(struct mrsas_mpt_cmd *cmd, union ccb *ccb_ptr, u_int8_t status, 1862 u_int8_t extStatus, u_int32_t data_length, u_int8_t *sense) 1863 { 1864 struct mrsas_softc *sc = cmd->sc; 1865 u_int8_t *sense_data; 1866 1867 switch (status) { 1868 case MFI_STAT_OK: 1869 ccb_ptr->ccb_h.status = CAM_REQ_CMP; 1870 break; 1871 case MFI_STAT_SCSI_IO_FAILED: 1872 case MFI_STAT_SCSI_DONE_WITH_ERROR: 1873 ccb_ptr->ccb_h.status = CAM_SCSI_STATUS_ERROR; 1874 sense_data = (u_int8_t *)&ccb_ptr->csio.sense_data; 1875 if (sense_data) { 1876 /* For now just copy 18 bytes back */ 1877 memcpy(sense_data, sense, 18); 1878 ccb_ptr->csio.sense_len = 18; 1879 ccb_ptr->ccb_h.status |= CAM_AUTOSNS_VALID; 1880 } 1881 break; 1882 case MFI_STAT_LD_OFFLINE: 1883 case MFI_STAT_DEVICE_NOT_FOUND: 1884 if (ccb_ptr->ccb_h.target_lun) 1885 ccb_ptr->ccb_h.status |= CAM_LUN_INVALID; 1886 else 1887 ccb_ptr->ccb_h.status |= CAM_DEV_NOT_THERE; 1888 break; 1889 case MFI_STAT_CONFIG_SEQ_MISMATCH: 1890 ccb_ptr->ccb_h.status |= CAM_REQUEUE_REQ; 1891 break; 1892 default: 1893 device_printf(sc->mrsas_dev, "FW cmd complete status %x\n", status); 1894 ccb_ptr->ccb_h.status = CAM_REQ_CMP_ERR; 1895 ccb_ptr->csio.scsi_status = status; 1896 } 1897 return; 1898 } 1899 1900 /* 1901 * mrsas_alloc_mem: Allocate DMAable memory 1902 * input: Adapter instance soft state 1903 * 1904 * This function creates the parent DMA tag and allocates DMAable memory. DMA 1905 * tag describes constraints of DMA mapping. Memory allocated is mapped into 1906 * Kernel virtual address. Callback argument is physical memory address. 1907 */ 1908 static int 1909 mrsas_alloc_mem(struct mrsas_softc *sc) 1910 { 1911 u_int32_t verbuf_size, io_req_size, reply_desc_size, sense_size, chain_frame_size, 1912 evt_detail_size, count, pd_info_size; 1913 1914 /* 1915 * Allocate parent DMA tag 1916 */ 1917 if (bus_dma_tag_create( 1918 bus_get_dma_tag(sc->mrsas_dev), /* parent */ 1919 1, /* alignment */ 1920 0, /* boundary */ 1921 BUS_SPACE_MAXADDR, /* lowaddr */ 1922 BUS_SPACE_MAXADDR, /* highaddr */ 1923 NULL, NULL, /* filter, filterarg */ 1924 BUS_SPACE_MAXSIZE, /* maxsize */ 1925 BUS_SPACE_UNRESTRICTED, /* nsegments */ 1926 BUS_SPACE_MAXSIZE, /* maxsegsize */ 1927 0, /* flags */ 1928 NULL, NULL, /* lockfunc, lockarg */ 1929 &sc->mrsas_parent_tag /* tag */ 1930 )) { 1931 device_printf(sc->mrsas_dev, "Cannot allocate parent DMA tag\n"); 1932 return (ENOMEM); 1933 } 1934 /* 1935 * Allocate for version buffer 1936 */ 1937 verbuf_size = MRSAS_MAX_NAME_LENGTH * (sizeof(bus_addr_t)); 1938 if (bus_dma_tag_create(sc->mrsas_parent_tag, 1939 1, 0, 1940 BUS_SPACE_MAXADDR_32BIT, 1941 BUS_SPACE_MAXADDR, 1942 NULL, NULL, 1943 verbuf_size, 1944 1, 1945 verbuf_size, 1946 BUS_DMA_ALLOCNOW, 1947 NULL, NULL, 1948 &sc->verbuf_tag)) { 1949 device_printf(sc->mrsas_dev, "Cannot allocate verbuf DMA tag\n"); 1950 return (ENOMEM); 1951 } 1952 if (bus_dmamem_alloc(sc->verbuf_tag, (void **)&sc->verbuf_mem, 1953 BUS_DMA_NOWAIT, &sc->verbuf_dmamap)) { 1954 device_printf(sc->mrsas_dev, "Cannot allocate verbuf memory\n"); 1955 return (ENOMEM); 1956 } 1957 bzero(sc->verbuf_mem, verbuf_size); 1958 if (bus_dmamap_load(sc->verbuf_tag, sc->verbuf_dmamap, sc->verbuf_mem, 1959 verbuf_size, mrsas_addr_cb, &sc->verbuf_phys_addr, 1960 BUS_DMA_NOWAIT)) { 1961 device_printf(sc->mrsas_dev, "Cannot load verbuf DMA map\n"); 1962 return (ENOMEM); 1963 } 1964 /* 1965 * Allocate IO Request Frames 1966 */ 1967 io_req_size = sc->io_frames_alloc_sz; 1968 if (bus_dma_tag_create(sc->mrsas_parent_tag, 1969 16, 0, 1970 BUS_SPACE_MAXADDR_32BIT, 1971 BUS_SPACE_MAXADDR, 1972 NULL, NULL, 1973 io_req_size, 1974 1, 1975 io_req_size, 1976 BUS_DMA_ALLOCNOW, 1977 NULL, NULL, 1978 &sc->io_request_tag)) { 1979 device_printf(sc->mrsas_dev, "Cannot create IO request tag\n"); 1980 return (ENOMEM); 1981 } 1982 if (bus_dmamem_alloc(sc->io_request_tag, (void **)&sc->io_request_mem, 1983 BUS_DMA_NOWAIT, &sc->io_request_dmamap)) { 1984 device_printf(sc->mrsas_dev, "Cannot alloc IO request memory\n"); 1985 return (ENOMEM); 1986 } 1987 bzero(sc->io_request_mem, io_req_size); 1988 if (bus_dmamap_load(sc->io_request_tag, sc->io_request_dmamap, 1989 sc->io_request_mem, io_req_size, mrsas_addr_cb, 1990 &sc->io_request_phys_addr, BUS_DMA_NOWAIT)) { 1991 device_printf(sc->mrsas_dev, "Cannot load IO request memory\n"); 1992 return (ENOMEM); 1993 } 1994 /* 1995 * Allocate Chain Frames 1996 */ 1997 chain_frame_size = sc->chain_frames_alloc_sz; 1998 if (bus_dma_tag_create(sc->mrsas_parent_tag, 1999 4, 0, 2000 BUS_SPACE_MAXADDR_32BIT, 2001 BUS_SPACE_MAXADDR, 2002 NULL, NULL, 2003 chain_frame_size, 2004 1, 2005 chain_frame_size, 2006 BUS_DMA_ALLOCNOW, 2007 NULL, NULL, 2008 &sc->chain_frame_tag)) { 2009 device_printf(sc->mrsas_dev, "Cannot create chain frame tag\n"); 2010 return (ENOMEM); 2011 } 2012 if (bus_dmamem_alloc(sc->chain_frame_tag, (void **)&sc->chain_frame_mem, 2013 BUS_DMA_NOWAIT, &sc->chain_frame_dmamap)) { 2014 device_printf(sc->mrsas_dev, "Cannot alloc chain frame memory\n"); 2015 return (ENOMEM); 2016 } 2017 bzero(sc->chain_frame_mem, chain_frame_size); 2018 if (bus_dmamap_load(sc->chain_frame_tag, sc->chain_frame_dmamap, 2019 sc->chain_frame_mem, chain_frame_size, mrsas_addr_cb, 2020 &sc->chain_frame_phys_addr, BUS_DMA_NOWAIT)) { 2021 device_printf(sc->mrsas_dev, "Cannot load chain frame memory\n"); 2022 return (ENOMEM); 2023 } 2024 count = sc->msix_vectors > 0 ? sc->msix_vectors : 1; 2025 /* 2026 * Allocate Reply Descriptor Array 2027 */ 2028 reply_desc_size = sc->reply_alloc_sz * count; 2029 if (bus_dma_tag_create(sc->mrsas_parent_tag, 2030 16, 0, 2031 BUS_SPACE_MAXADDR_32BIT, 2032 BUS_SPACE_MAXADDR, 2033 NULL, NULL, 2034 reply_desc_size, 2035 1, 2036 reply_desc_size, 2037 BUS_DMA_ALLOCNOW, 2038 NULL, NULL, 2039 &sc->reply_desc_tag)) { 2040 device_printf(sc->mrsas_dev, "Cannot create reply descriptor tag\n"); 2041 return (ENOMEM); 2042 } 2043 if (bus_dmamem_alloc(sc->reply_desc_tag, (void **)&sc->reply_desc_mem, 2044 BUS_DMA_NOWAIT, &sc->reply_desc_dmamap)) { 2045 device_printf(sc->mrsas_dev, "Cannot alloc reply descriptor memory\n"); 2046 return (ENOMEM); 2047 } 2048 if (bus_dmamap_load(sc->reply_desc_tag, sc->reply_desc_dmamap, 2049 sc->reply_desc_mem, reply_desc_size, mrsas_addr_cb, 2050 &sc->reply_desc_phys_addr, BUS_DMA_NOWAIT)) { 2051 device_printf(sc->mrsas_dev, "Cannot load reply descriptor memory\n"); 2052 return (ENOMEM); 2053 } 2054 /* 2055 * Allocate Sense Buffer Array. Keep in lower 4GB 2056 */ 2057 sense_size = sc->max_fw_cmds * MRSAS_SENSE_LEN; 2058 if (bus_dma_tag_create(sc->mrsas_parent_tag, 2059 64, 0, 2060 BUS_SPACE_MAXADDR_32BIT, 2061 BUS_SPACE_MAXADDR, 2062 NULL, NULL, 2063 sense_size, 2064 1, 2065 sense_size, 2066 BUS_DMA_ALLOCNOW, 2067 NULL, NULL, 2068 &sc->sense_tag)) { 2069 device_printf(sc->mrsas_dev, "Cannot allocate sense buf tag\n"); 2070 return (ENOMEM); 2071 } 2072 if (bus_dmamem_alloc(sc->sense_tag, (void **)&sc->sense_mem, 2073 BUS_DMA_NOWAIT, &sc->sense_dmamap)) { 2074 device_printf(sc->mrsas_dev, "Cannot allocate sense buf memory\n"); 2075 return (ENOMEM); 2076 } 2077 if (bus_dmamap_load(sc->sense_tag, sc->sense_dmamap, 2078 sc->sense_mem, sense_size, mrsas_addr_cb, &sc->sense_phys_addr, 2079 BUS_DMA_NOWAIT)) { 2080 device_printf(sc->mrsas_dev, "Cannot load sense buf memory\n"); 2081 return (ENOMEM); 2082 } 2083 2084 /* 2085 * Allocate for Event detail structure 2086 */ 2087 evt_detail_size = sizeof(struct mrsas_evt_detail); 2088 if (bus_dma_tag_create(sc->mrsas_parent_tag, 2089 1, 0, 2090 BUS_SPACE_MAXADDR_32BIT, 2091 BUS_SPACE_MAXADDR, 2092 NULL, NULL, 2093 evt_detail_size, 2094 1, 2095 evt_detail_size, 2096 BUS_DMA_ALLOCNOW, 2097 NULL, NULL, 2098 &sc->evt_detail_tag)) { 2099 device_printf(sc->mrsas_dev, "Cannot create Event detail tag\n"); 2100 return (ENOMEM); 2101 } 2102 if (bus_dmamem_alloc(sc->evt_detail_tag, (void **)&sc->evt_detail_mem, 2103 BUS_DMA_NOWAIT, &sc->evt_detail_dmamap)) { 2104 device_printf(sc->mrsas_dev, "Cannot alloc Event detail buffer memory\n"); 2105 return (ENOMEM); 2106 } 2107 bzero(sc->evt_detail_mem, evt_detail_size); 2108 if (bus_dmamap_load(sc->evt_detail_tag, sc->evt_detail_dmamap, 2109 sc->evt_detail_mem, evt_detail_size, mrsas_addr_cb, 2110 &sc->evt_detail_phys_addr, BUS_DMA_NOWAIT)) { 2111 device_printf(sc->mrsas_dev, "Cannot load Event detail buffer memory\n"); 2112 return (ENOMEM); 2113 } 2114 2115 /* 2116 * Allocate for PD INFO structure 2117 */ 2118 pd_info_size = sizeof(struct mrsas_pd_info); 2119 if (bus_dma_tag_create(sc->mrsas_parent_tag, 2120 1, 0, 2121 BUS_SPACE_MAXADDR_32BIT, 2122 BUS_SPACE_MAXADDR, 2123 NULL, NULL, 2124 pd_info_size, 2125 1, 2126 pd_info_size, 2127 BUS_DMA_ALLOCNOW, 2128 NULL, NULL, 2129 &sc->pd_info_tag)) { 2130 device_printf(sc->mrsas_dev, "Cannot create PD INFO tag\n"); 2131 return (ENOMEM); 2132 } 2133 if (bus_dmamem_alloc(sc->pd_info_tag, (void **)&sc->pd_info_mem, 2134 BUS_DMA_NOWAIT, &sc->pd_info_dmamap)) { 2135 device_printf(sc->mrsas_dev, "Cannot alloc PD INFO buffer memory\n"); 2136 return (ENOMEM); 2137 } 2138 bzero(sc->pd_info_mem, pd_info_size); 2139 if (bus_dmamap_load(sc->pd_info_tag, sc->pd_info_dmamap, 2140 sc->pd_info_mem, pd_info_size, mrsas_addr_cb, 2141 &sc->pd_info_phys_addr, BUS_DMA_NOWAIT)) { 2142 device_printf(sc->mrsas_dev, "Cannot load PD INFO buffer memory\n"); 2143 return (ENOMEM); 2144 } 2145 2146 /* 2147 * Create a dma tag for data buffers; size will be the maximum 2148 * possible I/O size (280kB). 2149 */ 2150 if (bus_dma_tag_create(sc->mrsas_parent_tag, 2151 1, 2152 0, 2153 BUS_SPACE_MAXADDR, 2154 BUS_SPACE_MAXADDR, 2155 NULL, NULL, 2156 maxphys, 2157 sc->max_num_sge, /* nsegments */ 2158 maxphys, 2159 BUS_DMA_ALLOCNOW, 2160 busdma_lock_mutex, 2161 &sc->io_lock, 2162 &sc->data_tag)) { 2163 device_printf(sc->mrsas_dev, "Cannot create data dma tag\n"); 2164 return (ENOMEM); 2165 } 2166 return (0); 2167 } 2168 2169 /* 2170 * mrsas_addr_cb: Callback function of bus_dmamap_load() 2171 * input: callback argument, machine dependent type 2172 * that describes DMA segments, number of segments, error code 2173 * 2174 * This function is for the driver to receive mapping information resultant of 2175 * the bus_dmamap_load(). The information is actually not being used, but the 2176 * address is saved anyway. 2177 */ 2178 void 2179 mrsas_addr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 2180 { 2181 bus_addr_t *addr; 2182 2183 addr = arg; 2184 *addr = segs[0].ds_addr; 2185 } 2186 2187 /* 2188 * mrsas_setup_raidmap: Set up RAID map. 2189 * input: Adapter instance soft state 2190 * 2191 * Allocate DMA memory for the RAID maps and perform setup. 2192 */ 2193 static int 2194 mrsas_setup_raidmap(struct mrsas_softc *sc) 2195 { 2196 int i; 2197 2198 for (i = 0; i < 2; i++) { 2199 sc->ld_drv_map[i] = 2200 (void *)malloc(sc->drv_map_sz, M_MRSAS, M_NOWAIT); 2201 /* Do Error handling */ 2202 if (!sc->ld_drv_map[i]) { 2203 device_printf(sc->mrsas_dev, "Could not allocate memory for local map"); 2204 2205 if (i == 1) 2206 free(sc->ld_drv_map[0], M_MRSAS); 2207 /* ABORT driver initialization */ 2208 goto ABORT; 2209 } 2210 } 2211 2212 for (int i = 0; i < 2; i++) { 2213 if (bus_dma_tag_create(sc->mrsas_parent_tag, 2214 4, 0, 2215 BUS_SPACE_MAXADDR_32BIT, 2216 BUS_SPACE_MAXADDR, 2217 NULL, NULL, 2218 sc->max_map_sz, 2219 1, 2220 sc->max_map_sz, 2221 BUS_DMA_ALLOCNOW, 2222 NULL, NULL, 2223 &sc->raidmap_tag[i])) { 2224 device_printf(sc->mrsas_dev, 2225 "Cannot allocate raid map tag.\n"); 2226 return (ENOMEM); 2227 } 2228 if (bus_dmamem_alloc(sc->raidmap_tag[i], 2229 (void **)&sc->raidmap_mem[i], 2230 BUS_DMA_NOWAIT, &sc->raidmap_dmamap[i])) { 2231 device_printf(sc->mrsas_dev, 2232 "Cannot allocate raidmap memory.\n"); 2233 return (ENOMEM); 2234 } 2235 bzero(sc->raidmap_mem[i], sc->max_map_sz); 2236 2237 if (bus_dmamap_load(sc->raidmap_tag[i], sc->raidmap_dmamap[i], 2238 sc->raidmap_mem[i], sc->max_map_sz, 2239 mrsas_addr_cb, &sc->raidmap_phys_addr[i], 2240 BUS_DMA_NOWAIT)) { 2241 device_printf(sc->mrsas_dev, "Cannot load raidmap memory.\n"); 2242 return (ENOMEM); 2243 } 2244 if (!sc->raidmap_mem[i]) { 2245 device_printf(sc->mrsas_dev, 2246 "Cannot allocate memory for raid map.\n"); 2247 return (ENOMEM); 2248 } 2249 } 2250 2251 if (!mrsas_get_map_info(sc)) 2252 mrsas_sync_map_info(sc); 2253 2254 return (0); 2255 2256 ABORT: 2257 return (1); 2258 } 2259 2260 /** 2261 * megasas_setup_jbod_map - setup jbod map for FP seq_number. 2262 * @sc: Adapter soft state 2263 * 2264 * Return 0 on success. 2265 */ 2266 void 2267 megasas_setup_jbod_map(struct mrsas_softc *sc) 2268 { 2269 int i; 2270 uint32_t pd_seq_map_sz; 2271 2272 pd_seq_map_sz = sizeof(struct MR_PD_CFG_SEQ_NUM_SYNC) + 2273 (sizeof(struct MR_PD_CFG_SEQ) * (MAX_PHYSICAL_DEVICES - 1)); 2274 2275 if (!sc->ctrl_info->adapterOperations3.useSeqNumJbodFP) { 2276 sc->use_seqnum_jbod_fp = 0; 2277 return; 2278 } 2279 if (sc->jbodmap_mem[0]) 2280 goto skip_alloc; 2281 2282 for (i = 0; i < 2; i++) { 2283 if (bus_dma_tag_create(sc->mrsas_parent_tag, 2284 4, 0, 2285 BUS_SPACE_MAXADDR_32BIT, 2286 BUS_SPACE_MAXADDR, 2287 NULL, NULL, 2288 pd_seq_map_sz, 2289 1, 2290 pd_seq_map_sz, 2291 BUS_DMA_ALLOCNOW, 2292 NULL, NULL, 2293 &sc->jbodmap_tag[i])) { 2294 device_printf(sc->mrsas_dev, 2295 "Cannot allocate jbod map tag.\n"); 2296 return; 2297 } 2298 if (bus_dmamem_alloc(sc->jbodmap_tag[i], 2299 (void **)&sc->jbodmap_mem[i], 2300 BUS_DMA_NOWAIT, &sc->jbodmap_dmamap[i])) { 2301 device_printf(sc->mrsas_dev, 2302 "Cannot allocate jbod map memory.\n"); 2303 return; 2304 } 2305 bzero(sc->jbodmap_mem[i], pd_seq_map_sz); 2306 2307 if (bus_dmamap_load(sc->jbodmap_tag[i], sc->jbodmap_dmamap[i], 2308 sc->jbodmap_mem[i], pd_seq_map_sz, 2309 mrsas_addr_cb, &sc->jbodmap_phys_addr[i], 2310 BUS_DMA_NOWAIT)) { 2311 device_printf(sc->mrsas_dev, "Cannot load jbod map memory.\n"); 2312 return; 2313 } 2314 if (!sc->jbodmap_mem[i]) { 2315 device_printf(sc->mrsas_dev, 2316 "Cannot allocate memory for jbod map.\n"); 2317 sc->use_seqnum_jbod_fp = 0; 2318 return; 2319 } 2320 } 2321 2322 skip_alloc: 2323 if (!megasas_sync_pd_seq_num(sc, false) && 2324 !megasas_sync_pd_seq_num(sc, true)) 2325 sc->use_seqnum_jbod_fp = 1; 2326 else 2327 sc->use_seqnum_jbod_fp = 0; 2328 2329 device_printf(sc->mrsas_dev, "Jbod map is supported\n"); 2330 } 2331 2332 /* 2333 * mrsas_init_fw: Initialize Firmware 2334 * input: Adapter soft state 2335 * 2336 * Calls transition_to_ready() to make sure Firmware is in operational state and 2337 * calls mrsas_init_adapter() to send IOC_INIT command to Firmware. It 2338 * issues internal commands to get the controller info after the IOC_INIT 2339 * command response is received by Firmware. Note: code relating to 2340 * get_pdlist, get_ld_list and max_sectors are currently not being used, it 2341 * is left here as placeholder. 2342 */ 2343 static int 2344 mrsas_init_fw(struct mrsas_softc *sc) 2345 { 2346 2347 int ret, loop, ocr = 0; 2348 u_int32_t max_sectors_1; 2349 u_int32_t max_sectors_2; 2350 u_int32_t tmp_sectors; 2351 u_int32_t scratch_pad_2, scratch_pad_3, scratch_pad_4; 2352 int msix_enable = 0; 2353 int fw_msix_count = 0; 2354 int i, j; 2355 2356 /* Make sure Firmware is ready */ 2357 ret = mrsas_transition_to_ready(sc, ocr); 2358 if (ret != SUCCESS) { 2359 return (ret); 2360 } 2361 if (sc->is_ventura || sc->is_aero) { 2362 scratch_pad_3 = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, outbound_scratch_pad_3)); 2363 #if VD_EXT_DEBUG 2364 device_printf(sc->mrsas_dev, "scratch_pad_3 0x%x\n", scratch_pad_3); 2365 #endif 2366 sc->maxRaidMapSize = ((scratch_pad_3 >> 2367 MR_MAX_RAID_MAP_SIZE_OFFSET_SHIFT) & 2368 MR_MAX_RAID_MAP_SIZE_MASK); 2369 } 2370 /* MSI-x index 0- reply post host index register */ 2371 sc->msix_reg_offset[0] = MPI2_REPLY_POST_HOST_INDEX_OFFSET; 2372 /* Check if MSI-X is supported while in ready state */ 2373 msix_enable = (mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, outbound_scratch_pad)) & 0x4000000) >> 0x1a; 2374 2375 if (msix_enable) { 2376 scratch_pad_2 = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, 2377 outbound_scratch_pad_2)); 2378 2379 /* Check max MSI-X vectors */ 2380 if (sc->device_id == MRSAS_TBOLT) { 2381 sc->msix_vectors = (scratch_pad_2 2382 & MR_MAX_REPLY_QUEUES_OFFSET) + 1; 2383 fw_msix_count = sc->msix_vectors; 2384 } else { 2385 /* Invader/Fury supports 96 MSI-X vectors */ 2386 sc->msix_vectors = ((scratch_pad_2 2387 & MR_MAX_REPLY_QUEUES_EXT_OFFSET) 2388 >> MR_MAX_REPLY_QUEUES_EXT_OFFSET_SHIFT) + 1; 2389 fw_msix_count = sc->msix_vectors; 2390 2391 if ((sc->mrsas_gen3_ctrl && (sc->msix_vectors > 8)) || 2392 ((sc->is_ventura || sc->is_aero) && (sc->msix_vectors > 16))) 2393 sc->msix_combined = true; 2394 /* 2395 * Save 1-15 reply post index 2396 * address to local memory Index 0 2397 * is already saved from reg offset 2398 * MPI2_REPLY_POST_HOST_INDEX_OFFSET 2399 */ 2400 for (loop = 1; loop < MR_MAX_MSIX_REG_ARRAY; 2401 loop++) { 2402 sc->msix_reg_offset[loop] = 2403 MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET + 2404 (loop * 0x10); 2405 } 2406 } 2407 2408 /* Don't bother allocating more MSI-X vectors than cpus */ 2409 sc->msix_vectors = min(sc->msix_vectors, 2410 mp_ncpus); 2411 2412 /* Allocate MSI-x vectors */ 2413 if (mrsas_allocate_msix(sc) == SUCCESS) 2414 sc->msix_enable = 1; 2415 else 2416 sc->msix_enable = 0; 2417 2418 device_printf(sc->mrsas_dev, "FW supports <%d> MSIX vector," 2419 "Online CPU %d Current MSIX <%d>\n", 2420 fw_msix_count, mp_ncpus, sc->msix_vectors); 2421 } 2422 /* 2423 * MSI-X host index 0 is common for all adapter. 2424 * It is used for all MPT based Adapters. 2425 */ 2426 if (sc->msix_combined) { 2427 sc->msix_reg_offset[0] = 2428 MPI2_SUP_REPLY_POST_HOST_INDEX_OFFSET; 2429 } 2430 if (mrsas_init_adapter(sc) != SUCCESS) { 2431 device_printf(sc->mrsas_dev, "Adapter initialize Fail.\n"); 2432 return (1); 2433 } 2434 2435 if (sc->is_ventura || sc->is_aero) { 2436 scratch_pad_4 = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, 2437 outbound_scratch_pad_4)); 2438 if ((scratch_pad_4 & MR_NVME_PAGE_SIZE_MASK) >= MR_DEFAULT_NVME_PAGE_SHIFT) 2439 sc->nvme_page_size = 1 << (scratch_pad_4 & MR_NVME_PAGE_SIZE_MASK); 2440 2441 device_printf(sc->mrsas_dev, "NVME page size\t: (%d)\n", sc->nvme_page_size); 2442 } 2443 2444 /* Allocate internal commands for pass-thru */ 2445 if (mrsas_alloc_mfi_cmds(sc) != SUCCESS) { 2446 device_printf(sc->mrsas_dev, "Allocate MFI cmd failed.\n"); 2447 return (1); 2448 } 2449 sc->ctrl_info = malloc(sizeof(struct mrsas_ctrl_info), M_MRSAS, M_NOWAIT); 2450 if (!sc->ctrl_info) { 2451 device_printf(sc->mrsas_dev, "Malloc for ctrl_info failed.\n"); 2452 return (1); 2453 } 2454 /* 2455 * Get the controller info from FW, so that the MAX VD support 2456 * availability can be decided. 2457 */ 2458 if (mrsas_get_ctrl_info(sc)) { 2459 device_printf(sc->mrsas_dev, "Unable to get FW ctrl_info.\n"); 2460 return (1); 2461 } 2462 sc->secure_jbod_support = 2463 (u_int8_t)sc->ctrl_info->adapterOperations3.supportSecurityonJBOD; 2464 2465 if (sc->secure_jbod_support) 2466 device_printf(sc->mrsas_dev, "FW supports SED \n"); 2467 2468 if (sc->use_seqnum_jbod_fp) 2469 device_printf(sc->mrsas_dev, "FW supports JBOD Map \n"); 2470 2471 if (sc->support_morethan256jbod) 2472 device_printf(sc->mrsas_dev, "FW supports JBOD Map Ext \n"); 2473 2474 if (mrsas_setup_raidmap(sc) != SUCCESS) { 2475 device_printf(sc->mrsas_dev, "Error: RAID map setup FAILED !!! " 2476 "There seems to be some problem in the controller\n" 2477 "Please contact to the SUPPORT TEAM if the problem persists\n"); 2478 } 2479 megasas_setup_jbod_map(sc); 2480 2481 memset(sc->target_list, 0, 2482 MRSAS_MAX_TM_TARGETS * sizeof(struct mrsas_target)); 2483 for (i = 0; i < MRSAS_MAX_TM_TARGETS; i++) 2484 sc->target_list[i].target_id = 0xffff; 2485 2486 /* For pass-thru, get PD/LD list and controller info */ 2487 memset(sc->pd_list, 0, 2488 MRSAS_MAX_PD * sizeof(struct mrsas_pd_list)); 2489 if (mrsas_get_pd_list(sc) != SUCCESS) { 2490 device_printf(sc->mrsas_dev, "Get PD list failed.\n"); 2491 return (1); 2492 } 2493 memset(sc->ld_ids, 0xff, MRSAS_MAX_LD_IDS); 2494 if (mrsas_get_ld_list(sc) != SUCCESS) { 2495 device_printf(sc->mrsas_dev, "Get LD lsit failed.\n"); 2496 return (1); 2497 } 2498 2499 if ((sc->is_ventura || sc->is_aero) && sc->drv_stream_detection) { 2500 sc->streamDetectByLD = malloc(sizeof(PTR_LD_STREAM_DETECT) * 2501 MAX_LOGICAL_DRIVES_EXT, M_MRSAS, M_NOWAIT); 2502 if (!sc->streamDetectByLD) { 2503 device_printf(sc->mrsas_dev, 2504 "unable to allocate stream detection for pool of LDs\n"); 2505 return (1); 2506 } 2507 for (i = 0; i < MAX_LOGICAL_DRIVES_EXT; ++i) { 2508 sc->streamDetectByLD[i] = malloc(sizeof(LD_STREAM_DETECT), M_MRSAS, M_NOWAIT); 2509 if (!sc->streamDetectByLD[i]) { 2510 device_printf(sc->mrsas_dev, "unable to allocate stream detect by LD\n"); 2511 for (j = 0; j < i; ++j) 2512 free(sc->streamDetectByLD[j], M_MRSAS); 2513 free(sc->streamDetectByLD, M_MRSAS); 2514 sc->streamDetectByLD = NULL; 2515 return (1); 2516 } 2517 memset(sc->streamDetectByLD[i], 0, sizeof(LD_STREAM_DETECT)); 2518 sc->streamDetectByLD[i]->mruBitMap = MR_STREAM_BITMAP; 2519 } 2520 } 2521 2522 /* 2523 * Compute the max allowed sectors per IO: The controller info has 2524 * two limits on max sectors. Driver should use the minimum of these 2525 * two. 2526 * 2527 * 1 << stripe_sz_ops.min = max sectors per strip 2528 * 2529 * Note that older firmwares ( < FW ver 30) didn't report information to 2530 * calculate max_sectors_1. So the number ended up as zero always. 2531 */ 2532 tmp_sectors = 0; 2533 max_sectors_1 = (1 << sc->ctrl_info->stripe_sz_ops.min) * 2534 sc->ctrl_info->max_strips_per_io; 2535 max_sectors_2 = sc->ctrl_info->max_request_size; 2536 tmp_sectors = min(max_sectors_1, max_sectors_2); 2537 sc->max_sectors_per_req = (sc->max_num_sge - 1) * MRSAS_PAGE_SIZE / 512; 2538 2539 if (tmp_sectors && (sc->max_sectors_per_req > tmp_sectors)) 2540 sc->max_sectors_per_req = tmp_sectors; 2541 2542 sc->disableOnlineCtrlReset = 2543 sc->ctrl_info->properties.OnOffProperties.disableOnlineCtrlReset; 2544 sc->UnevenSpanSupport = 2545 sc->ctrl_info->adapterOperations2.supportUnevenSpans; 2546 if (sc->UnevenSpanSupport) { 2547 device_printf(sc->mrsas_dev, "FW supports: UnevenSpanSupport=%x\n\n", 2548 sc->UnevenSpanSupport); 2549 2550 if (MR_ValidateMapInfo(sc)) 2551 sc->fast_path_io = 1; 2552 else 2553 sc->fast_path_io = 0; 2554 } 2555 2556 device_printf(sc->mrsas_dev, "max_fw_cmds: %u max_scsi_cmds: %u\n", 2557 sc->max_fw_cmds, sc->max_scsi_cmds); 2558 return (0); 2559 } 2560 2561 /* 2562 * mrsas_init_adapter: Initializes the adapter/controller 2563 * input: Adapter soft state 2564 * 2565 * Prepares for the issuing of the IOC Init cmd to FW for initializing the 2566 * ROC/controller. The FW register is read to determined the number of 2567 * commands that is supported. All memory allocations for IO is based on 2568 * max_cmd. Appropriate calculations are performed in this function. 2569 */ 2570 int 2571 mrsas_init_adapter(struct mrsas_softc *sc) 2572 { 2573 uint32_t status; 2574 u_int32_t scratch_pad_2; 2575 int ret; 2576 int i = 0; 2577 2578 /* Read FW status register */ 2579 status = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, outbound_scratch_pad)); 2580 2581 sc->max_fw_cmds = status & MRSAS_FWSTATE_MAXCMD_MASK; 2582 2583 /* Decrement the max supported by 1, to correlate with FW */ 2584 sc->max_fw_cmds = sc->max_fw_cmds - 1; 2585 sc->max_scsi_cmds = sc->max_fw_cmds - MRSAS_MAX_MFI_CMDS; 2586 2587 /* Determine allocation size of command frames */ 2588 sc->reply_q_depth = ((sc->max_fw_cmds + 1 + 15) / 16 * 16) * 2; 2589 sc->request_alloc_sz = sizeof(MRSAS_REQUEST_DESCRIPTOR_UNION) * sc->max_fw_cmds; 2590 sc->reply_alloc_sz = sizeof(MPI2_REPLY_DESCRIPTORS_UNION) * (sc->reply_q_depth); 2591 sc->io_frames_alloc_sz = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE + 2592 (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * (sc->max_fw_cmds + 1)); 2593 scratch_pad_2 = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, 2594 outbound_scratch_pad_2)); 2595 2596 mrsas_dprint(sc, MRSAS_TRACE, "%s: sc->reply_q_depth 0x%x," 2597 "sc->request_alloc_sz 0x%x, sc->reply_alloc_sz 0x%x," 2598 "sc->io_frames_alloc_sz 0x%x\n", __func__, 2599 sc->reply_q_depth, sc->request_alloc_sz, 2600 sc->reply_alloc_sz, sc->io_frames_alloc_sz); 2601 2602 /* 2603 * If scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK is set, 2604 * Firmware support extended IO chain frame which is 4 time more 2605 * than legacy Firmware. Legacy Firmware - Frame size is (8 * 128) = 2606 * 1K 1M IO Firmware - Frame size is (8 * 128 * 4) = 4K 2607 */ 2608 if (scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_UNITS_MASK) 2609 sc->max_chain_frame_sz = 2610 ((scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_MASK) >> 5) 2611 * MEGASAS_1MB_IO; 2612 else 2613 sc->max_chain_frame_sz = 2614 ((scratch_pad_2 & MEGASAS_MAX_CHAIN_SIZE_MASK) >> 5) 2615 * MEGASAS_256K_IO; 2616 2617 sc->chain_frames_alloc_sz = sc->max_chain_frame_sz * sc->max_fw_cmds; 2618 sc->max_sge_in_main_msg = (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE - 2619 offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL)) / 16; 2620 2621 sc->max_sge_in_chain = sc->max_chain_frame_sz / sizeof(MPI2_SGE_IO_UNION); 2622 sc->max_num_sge = sc->max_sge_in_main_msg + sc->max_sge_in_chain - 2; 2623 2624 mrsas_dprint(sc, MRSAS_INFO, 2625 "max sge: 0x%x, max chain frame size: 0x%x, " 2626 "max fw cmd: 0x%x sc->chain_frames_alloc_sz: 0x%x\n", 2627 sc->max_num_sge, 2628 sc->max_chain_frame_sz, sc->max_fw_cmds, 2629 sc->chain_frames_alloc_sz); 2630 2631 /* Used for pass thru MFI frame (DCMD) */ 2632 sc->chain_offset_mfi_pthru = offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL) / 16; 2633 2634 sc->chain_offset_io_request = (MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE - 2635 sizeof(MPI2_SGE_IO_UNION)) / 16; 2636 2637 int count = sc->msix_vectors > 0 ? sc->msix_vectors : 1; 2638 2639 for (i = 0; i < count; i++) 2640 sc->last_reply_idx[i] = 0; 2641 2642 ret = mrsas_alloc_mem(sc); 2643 if (ret != SUCCESS) 2644 return (ret); 2645 2646 ret = mrsas_alloc_mpt_cmds(sc); 2647 if (ret != SUCCESS) 2648 return (ret); 2649 2650 ret = mrsas_ioc_init(sc); 2651 if (ret != SUCCESS) 2652 return (ret); 2653 2654 return (0); 2655 } 2656 2657 /* 2658 * mrsas_alloc_ioc_cmd: Allocates memory for IOC Init command 2659 * input: Adapter soft state 2660 * 2661 * Allocates for the IOC Init cmd to FW to initialize the ROC/controller. 2662 */ 2663 int 2664 mrsas_alloc_ioc_cmd(struct mrsas_softc *sc) 2665 { 2666 int ioc_init_size; 2667 2668 /* Allocate IOC INIT command */ 2669 ioc_init_size = 1024 + sizeof(MPI2_IOC_INIT_REQUEST); 2670 if (bus_dma_tag_create(sc->mrsas_parent_tag, 2671 1, 0, 2672 BUS_SPACE_MAXADDR_32BIT, 2673 BUS_SPACE_MAXADDR, 2674 NULL, NULL, 2675 ioc_init_size, 2676 1, 2677 ioc_init_size, 2678 BUS_DMA_ALLOCNOW, 2679 NULL, NULL, 2680 &sc->ioc_init_tag)) { 2681 device_printf(sc->mrsas_dev, "Cannot allocate ioc init tag\n"); 2682 return (ENOMEM); 2683 } 2684 if (bus_dmamem_alloc(sc->ioc_init_tag, (void **)&sc->ioc_init_mem, 2685 BUS_DMA_NOWAIT, &sc->ioc_init_dmamap)) { 2686 device_printf(sc->mrsas_dev, "Cannot allocate ioc init cmd mem\n"); 2687 return (ENOMEM); 2688 } 2689 bzero(sc->ioc_init_mem, ioc_init_size); 2690 if (bus_dmamap_load(sc->ioc_init_tag, sc->ioc_init_dmamap, 2691 sc->ioc_init_mem, ioc_init_size, mrsas_addr_cb, 2692 &sc->ioc_init_phys_mem, BUS_DMA_NOWAIT)) { 2693 device_printf(sc->mrsas_dev, "Cannot load ioc init cmd mem\n"); 2694 return (ENOMEM); 2695 } 2696 return (0); 2697 } 2698 2699 /* 2700 * mrsas_free_ioc_cmd: Allocates memory for IOC Init command 2701 * input: Adapter soft state 2702 * 2703 * Deallocates memory of the IOC Init cmd. 2704 */ 2705 void 2706 mrsas_free_ioc_cmd(struct mrsas_softc *sc) 2707 { 2708 if (sc->ioc_init_phys_mem) 2709 bus_dmamap_unload(sc->ioc_init_tag, sc->ioc_init_dmamap); 2710 if (sc->ioc_init_mem != NULL) 2711 bus_dmamem_free(sc->ioc_init_tag, sc->ioc_init_mem, sc->ioc_init_dmamap); 2712 if (sc->ioc_init_tag != NULL) 2713 bus_dma_tag_destroy(sc->ioc_init_tag); 2714 } 2715 2716 /* 2717 * mrsas_ioc_init: Sends IOC Init command to FW 2718 * input: Adapter soft state 2719 * 2720 * Issues the IOC Init cmd to FW to initialize the ROC/controller. 2721 */ 2722 int 2723 mrsas_ioc_init(struct mrsas_softc *sc) 2724 { 2725 struct mrsas_init_frame *init_frame; 2726 pMpi2IOCInitRequest_t IOCInitMsg; 2727 MRSAS_REQUEST_DESCRIPTOR_UNION req_desc; 2728 u_int8_t max_wait = MRSAS_INTERNAL_CMD_WAIT_TIME; 2729 bus_addr_t phys_addr; 2730 int i, retcode = 0; 2731 u_int32_t scratch_pad_2; 2732 2733 /* Allocate memory for the IOC INIT command */ 2734 if (mrsas_alloc_ioc_cmd(sc)) { 2735 device_printf(sc->mrsas_dev, "Cannot allocate IOC command.\n"); 2736 return (1); 2737 } 2738 2739 if (!sc->block_sync_cache) { 2740 scratch_pad_2 = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, 2741 outbound_scratch_pad_2)); 2742 sc->fw_sync_cache_support = (scratch_pad_2 & 2743 MR_CAN_HANDLE_SYNC_CACHE_OFFSET) ? 1 : 0; 2744 } 2745 2746 IOCInitMsg = (pMpi2IOCInitRequest_t)(((char *)sc->ioc_init_mem) + 1024); 2747 IOCInitMsg->Function = MPI2_FUNCTION_IOC_INIT; 2748 IOCInitMsg->WhoInit = MPI2_WHOINIT_HOST_DRIVER; 2749 IOCInitMsg->MsgVersion = htole16(MPI2_VERSION); 2750 IOCInitMsg->HeaderVersion = htole16(MPI2_HEADER_VERSION); 2751 IOCInitMsg->SystemRequestFrameSize = htole16(MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE / 4); 2752 IOCInitMsg->ReplyDescriptorPostQueueDepth = htole16(sc->reply_q_depth); 2753 IOCInitMsg->ReplyDescriptorPostQueueAddress = htole64(sc->reply_desc_phys_addr); 2754 IOCInitMsg->SystemRequestFrameBaseAddress = htole64(sc->io_request_phys_addr); 2755 IOCInitMsg->HostMSIxVectors = (sc->msix_vectors > 0 ? sc->msix_vectors : 0); 2756 IOCInitMsg->HostPageSize = MR_DEFAULT_NVME_PAGE_SHIFT; 2757 2758 init_frame = (struct mrsas_init_frame *)sc->ioc_init_mem; 2759 init_frame->cmd = MFI_CMD_INIT; 2760 init_frame->cmd_status = 0xFF; 2761 init_frame->flags |= htole16(MFI_FRAME_DONT_POST_IN_REPLY_QUEUE); 2762 2763 /* driver support Extended MSIX */ 2764 if (sc->mrsas_gen3_ctrl || sc->is_ventura || sc->is_aero) { 2765 init_frame->driver_operations. 2766 mfi_capabilities.support_additional_msix = 1; 2767 } 2768 if (sc->verbuf_mem) { 2769 snprintf((char *)sc->verbuf_mem, strlen(MRSAS_VERSION) + 2, "%s\n", 2770 MRSAS_VERSION); 2771 init_frame->driver_ver_lo = (bus_addr_t)sc->verbuf_phys_addr; 2772 init_frame->driver_ver_hi = 0; 2773 } 2774 init_frame->driver_operations.mfi_capabilities.support_ndrive_r1_lb = 1; 2775 init_frame->driver_operations.mfi_capabilities.support_max_255lds = 1; 2776 init_frame->driver_operations.mfi_capabilities.security_protocol_cmds_fw = 1; 2777 if (sc->max_chain_frame_sz > MEGASAS_CHAIN_FRAME_SZ_MIN) 2778 init_frame->driver_operations.mfi_capabilities.support_ext_io_size = 1; 2779 2780 init_frame->driver_operations.reg = htole32(init_frame->driver_operations.reg); 2781 2782 phys_addr = (bus_addr_t)sc->ioc_init_phys_mem + 1024; 2783 init_frame->queue_info_new_phys_addr_lo = htole32(phys_addr); 2784 init_frame->data_xfer_len = htole32(sizeof(Mpi2IOCInitRequest_t)); 2785 2786 req_desc.addr.Words = htole64((bus_addr_t)sc->ioc_init_phys_mem); 2787 req_desc.MFAIo.RequestFlags = 2788 (MRSAS_REQ_DESCRIPT_FLAGS_MFA << MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT); 2789 2790 mrsas_disable_intr(sc); 2791 mrsas_dprint(sc, MRSAS_OCR, "Issuing IOC INIT command to FW.\n"); 2792 mrsas_write_64bit_req_desc(sc, req_desc.addr.u.low, req_desc.addr.u.high); 2793 2794 /* 2795 * Poll response timer to wait for Firmware response. While this 2796 * timer with the DELAY call could block CPU, the time interval for 2797 * this is only 1 millisecond. 2798 */ 2799 if (init_frame->cmd_status == 0xFF) { 2800 for (i = 0; i < (max_wait * 1000); i++) { 2801 if (init_frame->cmd_status == 0xFF) 2802 DELAY(1000); 2803 else 2804 break; 2805 } 2806 } 2807 if (init_frame->cmd_status == 0) 2808 mrsas_dprint(sc, MRSAS_OCR, 2809 "IOC INIT response received from FW.\n"); 2810 else { 2811 if (init_frame->cmd_status == 0xFF) 2812 device_printf(sc->mrsas_dev, "IOC Init timed out after %d seconds.\n", max_wait); 2813 else 2814 device_printf(sc->mrsas_dev, "IOC Init failed, status = 0x%x\n", init_frame->cmd_status); 2815 retcode = 1; 2816 } 2817 2818 if (sc->is_aero) { 2819 scratch_pad_2 = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, 2820 outbound_scratch_pad_2)); 2821 sc->atomic_desc_support = (scratch_pad_2 & 2822 MR_ATOMIC_DESCRIPTOR_SUPPORT_OFFSET) ? 1 : 0; 2823 device_printf(sc->mrsas_dev, "FW supports atomic descriptor: %s\n", 2824 sc->atomic_desc_support ? "Yes" : "No"); 2825 } 2826 2827 mrsas_free_ioc_cmd(sc); 2828 return (retcode); 2829 } 2830 2831 /* 2832 * mrsas_alloc_mpt_cmds: Allocates the command packets 2833 * input: Adapter instance soft state 2834 * 2835 * This function allocates the internal commands for IOs. Each command that is 2836 * issued to FW is wrapped in a local data structure called mrsas_mpt_cmd. An 2837 * array is allocated with mrsas_mpt_cmd context. The free commands are 2838 * maintained in a linked list (cmd pool). SMID value range is from 1 to 2839 * max_fw_cmds. 2840 */ 2841 int 2842 mrsas_alloc_mpt_cmds(struct mrsas_softc *sc) 2843 { 2844 int i, j; 2845 u_int32_t max_fw_cmds, count; 2846 struct mrsas_mpt_cmd *cmd; 2847 pMpi2ReplyDescriptorsUnion_t reply_desc; 2848 u_int32_t offset, chain_offset, sense_offset; 2849 bus_addr_t io_req_base_phys, chain_frame_base_phys, sense_base_phys; 2850 u_int8_t *io_req_base, *chain_frame_base, *sense_base; 2851 2852 max_fw_cmds = sc->max_fw_cmds; 2853 2854 sc->req_desc = malloc(sc->request_alloc_sz, M_MRSAS, M_NOWAIT); 2855 if (!sc->req_desc) { 2856 device_printf(sc->mrsas_dev, "Out of memory, cannot alloc req desc\n"); 2857 return (ENOMEM); 2858 } 2859 memset(sc->req_desc, 0, sc->request_alloc_sz); 2860 2861 /* 2862 * sc->mpt_cmd_list is an array of struct mrsas_mpt_cmd pointers. 2863 * Allocate the dynamic array first and then allocate individual 2864 * commands. 2865 */ 2866 sc->mpt_cmd_list = malloc(sizeof(struct mrsas_mpt_cmd *) * max_fw_cmds, 2867 M_MRSAS, M_NOWAIT); 2868 if (!sc->mpt_cmd_list) { 2869 device_printf(sc->mrsas_dev, "Cannot alloc memory for mpt_cmd_list.\n"); 2870 return (ENOMEM); 2871 } 2872 memset(sc->mpt_cmd_list, 0, sizeof(struct mrsas_mpt_cmd *) * max_fw_cmds); 2873 for (i = 0; i < max_fw_cmds; i++) { 2874 sc->mpt_cmd_list[i] = malloc(sizeof(struct mrsas_mpt_cmd), 2875 M_MRSAS, M_NOWAIT); 2876 if (!sc->mpt_cmd_list[i]) { 2877 for (j = 0; j < i; j++) 2878 free(sc->mpt_cmd_list[j], M_MRSAS); 2879 free(sc->mpt_cmd_list, M_MRSAS); 2880 sc->mpt_cmd_list = NULL; 2881 return (ENOMEM); 2882 } 2883 } 2884 2885 io_req_base = (u_int8_t *)sc->io_request_mem + MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE; 2886 io_req_base_phys = (bus_addr_t)sc->io_request_phys_addr + MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE; 2887 chain_frame_base = (u_int8_t *)sc->chain_frame_mem; 2888 chain_frame_base_phys = (bus_addr_t)sc->chain_frame_phys_addr; 2889 sense_base = (u_int8_t *)sc->sense_mem; 2890 sense_base_phys = (bus_addr_t)sc->sense_phys_addr; 2891 for (i = 0; i < max_fw_cmds; i++) { 2892 cmd = sc->mpt_cmd_list[i]; 2893 offset = MRSAS_MPI2_RAID_DEFAULT_IO_FRAME_SIZE * i; 2894 chain_offset = sc->max_chain_frame_sz * i; 2895 sense_offset = MRSAS_SENSE_LEN * i; 2896 memset(cmd, 0, sizeof(struct mrsas_mpt_cmd)); 2897 cmd->index = i + 1; 2898 cmd->ccb_ptr = NULL; 2899 cmd->r1_alt_dev_handle = MR_DEVHANDLE_INVALID; 2900 callout_init_mtx(&cmd->cm_callout, &sc->sim_lock, 0); 2901 cmd->sync_cmd_idx = (u_int32_t)MRSAS_ULONG_MAX; 2902 cmd->sc = sc; 2903 cmd->io_request = (MRSAS_RAID_SCSI_IO_REQUEST *) (io_req_base + offset); 2904 memset(cmd->io_request, 0, sizeof(MRSAS_RAID_SCSI_IO_REQUEST)); 2905 cmd->io_request_phys_addr = io_req_base_phys + offset; 2906 cmd->chain_frame = (MPI2_SGE_IO_UNION *) (chain_frame_base + chain_offset); 2907 cmd->chain_frame_phys_addr = chain_frame_base_phys + chain_offset; 2908 cmd->sense = sense_base + sense_offset; 2909 cmd->sense_phys_addr = sense_base_phys + sense_offset; 2910 if (bus_dmamap_create(sc->data_tag, 0, &cmd->data_dmamap)) { 2911 return (FAIL); 2912 } 2913 TAILQ_INSERT_TAIL(&(sc->mrsas_mpt_cmd_list_head), cmd, next); 2914 } 2915 2916 /* Initialize reply descriptor array to 0xFFFFFFFF */ 2917 reply_desc = sc->reply_desc_mem; 2918 count = sc->msix_vectors > 0 ? sc->msix_vectors : 1; 2919 for (i = 0; i < sc->reply_q_depth * count; i++, reply_desc++) { 2920 reply_desc->Words = MRSAS_ULONG_MAX; 2921 } 2922 return (0); 2923 } 2924 2925 /* 2926 * mrsas_write_64bit_req_dsc: Writes 64 bit request descriptor to FW 2927 * input: Adapter softstate 2928 * request descriptor address low 2929 * request descriptor address high 2930 */ 2931 void 2932 mrsas_write_64bit_req_desc(struct mrsas_softc *sc, u_int32_t req_desc_lo, 2933 u_int32_t req_desc_hi) 2934 { 2935 mtx_lock(&sc->pci_lock); 2936 mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_low_queue_port), 2937 le32toh(req_desc_lo)); 2938 mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_high_queue_port), 2939 le32toh(req_desc_hi)); 2940 mtx_unlock(&sc->pci_lock); 2941 } 2942 2943 /* 2944 * mrsas_fire_cmd: Sends command to FW 2945 * input: Adapter softstate 2946 * request descriptor address low 2947 * request descriptor address high 2948 * 2949 * This functions fires the command to Firmware by writing to the 2950 * inbound_low_queue_port and inbound_high_queue_port. 2951 */ 2952 void 2953 mrsas_fire_cmd(struct mrsas_softc *sc, u_int32_t req_desc_lo, 2954 u_int32_t req_desc_hi) 2955 { 2956 if (sc->atomic_desc_support) 2957 mrsas_write_reg(sc, offsetof(mrsas_reg_set, inbound_single_queue_port), 2958 le32toh(req_desc_lo)); 2959 else 2960 mrsas_write_64bit_req_desc(sc, req_desc_lo, req_desc_hi); 2961 } 2962 2963 /* 2964 * mrsas_transition_to_ready: Move FW to Ready state input: 2965 * Adapter instance soft state 2966 * 2967 * During the initialization, FW passes can potentially be in any one of several 2968 * possible states. If the FW in operational, waiting-for-handshake states, 2969 * driver must take steps to bring it to ready state. Otherwise, it has to 2970 * wait for the ready state. 2971 */ 2972 int 2973 mrsas_transition_to_ready(struct mrsas_softc *sc, int ocr) 2974 { 2975 int i; 2976 u_int8_t max_wait; 2977 u_int32_t val, fw_state; 2978 u_int32_t cur_state; 2979 u_int32_t abs_state, curr_abs_state; 2980 2981 val = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, outbound_scratch_pad)); 2982 fw_state = val & MFI_STATE_MASK; 2983 max_wait = MRSAS_RESET_WAIT_TIME; 2984 2985 if (fw_state != MFI_STATE_READY) 2986 device_printf(sc->mrsas_dev, "Waiting for FW to come to ready state\n"); 2987 2988 while (fw_state != MFI_STATE_READY) { 2989 abs_state = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, outbound_scratch_pad)); 2990 switch (fw_state) { 2991 case MFI_STATE_FAULT: 2992 device_printf(sc->mrsas_dev, "FW is in FAULT state!!\n"); 2993 if (ocr) { 2994 cur_state = MFI_STATE_FAULT; 2995 break; 2996 } else 2997 return -ENODEV; 2998 case MFI_STATE_WAIT_HANDSHAKE: 2999 /* Set the CLR bit in inbound doorbell */ 3000 mrsas_write_reg(sc, offsetof(mrsas_reg_set, doorbell), 3001 MFI_INIT_CLEAR_HANDSHAKE | MFI_INIT_HOTPLUG); 3002 cur_state = MFI_STATE_WAIT_HANDSHAKE; 3003 break; 3004 case MFI_STATE_BOOT_MESSAGE_PENDING: 3005 mrsas_write_reg(sc, offsetof(mrsas_reg_set, doorbell), 3006 MFI_INIT_HOTPLUG); 3007 cur_state = MFI_STATE_BOOT_MESSAGE_PENDING; 3008 break; 3009 case MFI_STATE_OPERATIONAL: 3010 /* 3011 * Bring it to READY state; assuming max wait 10 3012 * secs 3013 */ 3014 mrsas_disable_intr(sc); 3015 mrsas_write_reg(sc, offsetof(mrsas_reg_set, doorbell), MFI_RESET_FLAGS); 3016 for (i = 0; i < max_wait * 1000; i++) { 3017 if (mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, doorbell)) & 1) 3018 DELAY(1000); 3019 else 3020 break; 3021 } 3022 cur_state = MFI_STATE_OPERATIONAL; 3023 break; 3024 case MFI_STATE_UNDEFINED: 3025 /* 3026 * This state should not last for more than 2 3027 * seconds 3028 */ 3029 cur_state = MFI_STATE_UNDEFINED; 3030 break; 3031 case MFI_STATE_BB_INIT: 3032 cur_state = MFI_STATE_BB_INIT; 3033 break; 3034 case MFI_STATE_FW_INIT: 3035 cur_state = MFI_STATE_FW_INIT; 3036 break; 3037 case MFI_STATE_FW_INIT_2: 3038 cur_state = MFI_STATE_FW_INIT_2; 3039 break; 3040 case MFI_STATE_DEVICE_SCAN: 3041 cur_state = MFI_STATE_DEVICE_SCAN; 3042 break; 3043 case MFI_STATE_FLUSH_CACHE: 3044 cur_state = MFI_STATE_FLUSH_CACHE; 3045 break; 3046 default: 3047 device_printf(sc->mrsas_dev, "Unknown state 0x%x\n", fw_state); 3048 return -ENODEV; 3049 } 3050 3051 /* 3052 * The cur_state should not last for more than max_wait secs 3053 */ 3054 for (i = 0; i < (max_wait * 1000); i++) { 3055 fw_state = (mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, 3056 outbound_scratch_pad)) & MFI_STATE_MASK); 3057 curr_abs_state = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, 3058 outbound_scratch_pad)); 3059 if (abs_state == curr_abs_state) 3060 DELAY(1000); 3061 else 3062 break; 3063 } 3064 3065 /* 3066 * Return error if fw_state hasn't changed after max_wait 3067 */ 3068 if (curr_abs_state == abs_state) { 3069 device_printf(sc->mrsas_dev, "FW state [%d] hasn't changed " 3070 "in %d secs\n", fw_state, max_wait); 3071 return -ENODEV; 3072 } 3073 } 3074 mrsas_dprint(sc, MRSAS_OCR, "FW now in Ready state\n"); 3075 return 0; 3076 } 3077 3078 /* 3079 * mrsas_get_mfi_cmd: Get a cmd from free command pool 3080 * input: Adapter soft state 3081 * 3082 * This function removes an MFI command from the command list. 3083 */ 3084 struct mrsas_mfi_cmd * 3085 mrsas_get_mfi_cmd(struct mrsas_softc *sc) 3086 { 3087 struct mrsas_mfi_cmd *cmd = NULL; 3088 3089 mtx_lock(&sc->mfi_cmd_pool_lock); 3090 if (!TAILQ_EMPTY(&sc->mrsas_mfi_cmd_list_head)) { 3091 cmd = TAILQ_FIRST(&sc->mrsas_mfi_cmd_list_head); 3092 TAILQ_REMOVE(&sc->mrsas_mfi_cmd_list_head, cmd, next); 3093 } 3094 mtx_unlock(&sc->mfi_cmd_pool_lock); 3095 3096 return cmd; 3097 } 3098 3099 /* 3100 * mrsas_ocr_thread: Thread to handle OCR/Kill Adapter. 3101 * input: Adapter Context. 3102 * 3103 * This function will check FW status register and flag do_timeout_reset flag. 3104 * It will do OCR/Kill adapter if FW is in fault state or IO timed out has 3105 * trigger reset. 3106 */ 3107 static void 3108 mrsas_ocr_thread(void *arg) 3109 { 3110 struct mrsas_softc *sc; 3111 u_int32_t fw_status, fw_state; 3112 u_int8_t tm_target_reset_failed = 0; 3113 3114 sc = (struct mrsas_softc *)arg; 3115 3116 mrsas_dprint(sc, MRSAS_TRACE, "%s\n", __func__); 3117 sc->ocr_thread_active = 1; 3118 mtx_lock(&sc->sim_lock); 3119 for (;;) { 3120 /* Sleep for 1 second and check the queue status */ 3121 msleep(&sc->ocr_chan, &sc->sim_lock, PRIBIO, 3122 "mrsas_ocr", sc->mrsas_fw_fault_check_delay * hz); 3123 if (sc->remove_in_progress || 3124 sc->adprecovery == MRSAS_HW_CRITICAL_ERROR) { 3125 mrsas_dprint(sc, MRSAS_OCR, 3126 "Exit due to %s from %s\n", 3127 sc->remove_in_progress ? "Shutdown" : 3128 "Hardware critical error", __func__); 3129 break; 3130 } 3131 fw_status = mrsas_read_reg_with_retries(sc, 3132 offsetof(mrsas_reg_set, outbound_scratch_pad)); 3133 fw_state = fw_status & MFI_STATE_MASK; 3134 if (fw_state == MFI_STATE_FAULT || sc->do_timedout_reset || 3135 mrsas_atomic_read(&sc->target_reset_outstanding)) { 3136 /* First, freeze further IOs to come to the SIM */ 3137 mrsas_xpt_freeze(sc); 3138 3139 /* If this is an IO timeout then go for target reset */ 3140 if (mrsas_atomic_read(&sc->target_reset_outstanding)) { 3141 device_printf(sc->mrsas_dev, "Initiating Target RESET " 3142 "because of SCSI IO timeout!\n"); 3143 3144 /* Let the remaining IOs to complete */ 3145 msleep(&sc->ocr_chan, &sc->sim_lock, PRIBIO, 3146 "mrsas_reset_targets", 5 * hz); 3147 3148 /* Try to reset the target device */ 3149 if (mrsas_reset_targets(sc) == FAIL) 3150 tm_target_reset_failed = 1; 3151 } 3152 3153 /* If this is a DCMD timeout or FW fault, 3154 * then go for controller reset 3155 */ 3156 if (fw_state == MFI_STATE_FAULT || tm_target_reset_failed || 3157 (sc->do_timedout_reset == MFI_DCMD_TIMEOUT_OCR)) { 3158 if (tm_target_reset_failed) 3159 device_printf(sc->mrsas_dev, "Initiaiting OCR because of " 3160 "TM FAILURE!\n"); 3161 else 3162 device_printf(sc->mrsas_dev, "Initiaiting OCR " 3163 "because of %s!\n", sc->do_timedout_reset ? 3164 "DCMD IO Timeout" : "FW fault"); 3165 3166 mtx_lock_spin(&sc->ioctl_lock); 3167 sc->reset_in_progress = 1; 3168 mtx_unlock_spin(&sc->ioctl_lock); 3169 sc->reset_count++; 3170 3171 /* 3172 * Wait for the AEN task to be completed if it is running. 3173 */ 3174 mtx_unlock(&sc->sim_lock); 3175 taskqueue_drain(sc->ev_tq, &sc->ev_task); 3176 mtx_lock(&sc->sim_lock); 3177 3178 taskqueue_block(sc->ev_tq); 3179 /* Try to reset the controller */ 3180 mrsas_reset_ctrl(sc, sc->do_timedout_reset); 3181 3182 sc->do_timedout_reset = 0; 3183 sc->reset_in_progress = 0; 3184 tm_target_reset_failed = 0; 3185 mrsas_atomic_set(&sc->target_reset_outstanding, 0); 3186 memset(sc->target_reset_pool, 0, 3187 sizeof(sc->target_reset_pool)); 3188 taskqueue_unblock(sc->ev_tq); 3189 } 3190 3191 /* Now allow IOs to come to the SIM */ 3192 mrsas_xpt_release(sc); 3193 } 3194 } 3195 mtx_unlock(&sc->sim_lock); 3196 sc->ocr_thread_active = 0; 3197 mrsas_kproc_exit(0); 3198 } 3199 3200 /* 3201 * mrsas_reset_reply_desc: Reset Reply descriptor as part of OCR. 3202 * input: Adapter Context. 3203 * 3204 * This function will clear reply descriptor so that post OCR driver and FW will 3205 * lost old history. 3206 */ 3207 void 3208 mrsas_reset_reply_desc(struct mrsas_softc *sc) 3209 { 3210 int i, count; 3211 pMpi2ReplyDescriptorsUnion_t reply_desc; 3212 3213 count = sc->msix_vectors > 0 ? sc->msix_vectors : 1; 3214 for (i = 0; i < count; i++) 3215 sc->last_reply_idx[i] = 0; 3216 3217 reply_desc = sc->reply_desc_mem; 3218 for (i = 0; i < sc->reply_q_depth; i++, reply_desc++) { 3219 reply_desc->Words = MRSAS_ULONG_MAX; 3220 } 3221 } 3222 3223 /* 3224 * mrsas_reset_ctrl: Core function to OCR/Kill adapter. 3225 * input: Adapter Context. 3226 * 3227 * This function will run from thread context so that it can sleep. 1. Do not 3228 * handle OCR if FW is in HW critical error. 2. Wait for outstanding command 3229 * to complete for 180 seconds. 3. If #2 does not find any outstanding 3230 * command Controller is in working state, so skip OCR. Otherwise, do 3231 * OCR/kill Adapter based on flag disableOnlineCtrlReset. 4. Start of the 3232 * OCR, return all SCSI command back to CAM layer which has ccb_ptr. 5. Post 3233 * OCR, Re-fire Management command and move Controller to Operation state. 3234 */ 3235 int 3236 mrsas_reset_ctrl(struct mrsas_softc *sc, u_int8_t reset_reason) 3237 { 3238 int retval = SUCCESS, i, j, retry = 0; 3239 u_int32_t host_diag, abs_state, status_reg, reset_adapter; 3240 union ccb *ccb; 3241 struct mrsas_mfi_cmd *mfi_cmd; 3242 struct mrsas_mpt_cmd *mpt_cmd; 3243 union mrsas_evt_class_locale class_locale; 3244 MRSAS_REQUEST_DESCRIPTOR_UNION *req_desc; 3245 3246 if (sc->adprecovery == MRSAS_HW_CRITICAL_ERROR) { 3247 device_printf(sc->mrsas_dev, 3248 "mrsas: Hardware critical error, returning FAIL.\n"); 3249 return FAIL; 3250 } 3251 mrsas_set_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags); 3252 sc->adprecovery = MRSAS_ADPRESET_SM_INFAULT; 3253 mrsas_disable_intr(sc); 3254 msleep(&sc->ocr_chan, &sc->sim_lock, PRIBIO, "mrsas_ocr", 3255 sc->mrsas_fw_fault_check_delay * hz); 3256 3257 /* First try waiting for commands to complete */ 3258 if (mrsas_wait_for_outstanding(sc, reset_reason)) { 3259 mrsas_dprint(sc, MRSAS_OCR, 3260 "resetting adapter from %s.\n", 3261 __func__); 3262 /* Now return commands back to the CAM layer */ 3263 mtx_unlock(&sc->sim_lock); 3264 for (i = 0; i < sc->max_fw_cmds; i++) { 3265 mpt_cmd = sc->mpt_cmd_list[i]; 3266 3267 if (mpt_cmd->peer_cmd) { 3268 mrsas_dprint(sc, MRSAS_OCR, 3269 "R1 FP command [%d] - (mpt_cmd) %p, (peer_cmd) %p\n", 3270 i, mpt_cmd, mpt_cmd->peer_cmd); 3271 } 3272 3273 if (mpt_cmd->ccb_ptr) { 3274 if (mpt_cmd->callout_owner) { 3275 ccb = (union ccb *)(mpt_cmd->ccb_ptr); 3276 ccb->ccb_h.status = CAM_SCSI_BUS_RESET; 3277 mrsas_cmd_done(sc, mpt_cmd); 3278 } else { 3279 mpt_cmd->ccb_ptr = NULL; 3280 mrsas_release_mpt_cmd(mpt_cmd); 3281 } 3282 } 3283 } 3284 3285 mrsas_atomic_set(&sc->fw_outstanding, 0); 3286 3287 mtx_lock(&sc->sim_lock); 3288 3289 status_reg = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, 3290 outbound_scratch_pad)); 3291 abs_state = status_reg & MFI_STATE_MASK; 3292 reset_adapter = status_reg & MFI_RESET_ADAPTER; 3293 if (sc->disableOnlineCtrlReset || 3294 (abs_state == MFI_STATE_FAULT && !reset_adapter)) { 3295 /* Reset not supported, kill adapter */ 3296 mrsas_dprint(sc, MRSAS_OCR, "Reset not supported, killing adapter.\n"); 3297 mrsas_kill_hba(sc); 3298 retval = FAIL; 3299 goto out; 3300 } 3301 /* Now try to reset the chip */ 3302 for (i = 0; i < MRSAS_FUSION_MAX_RESET_TRIES; i++) { 3303 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 3304 MPI2_WRSEQ_FLUSH_KEY_VALUE); 3305 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 3306 MPI2_WRSEQ_1ST_KEY_VALUE); 3307 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 3308 MPI2_WRSEQ_2ND_KEY_VALUE); 3309 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 3310 MPI2_WRSEQ_3RD_KEY_VALUE); 3311 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 3312 MPI2_WRSEQ_4TH_KEY_VALUE); 3313 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 3314 MPI2_WRSEQ_5TH_KEY_VALUE); 3315 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_seq_offset), 3316 MPI2_WRSEQ_6TH_KEY_VALUE); 3317 3318 /* Check that the diag write enable (DRWE) bit is on */ 3319 host_diag = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, 3320 fusion_host_diag)); 3321 retry = 0; 3322 while (!(host_diag & HOST_DIAG_WRITE_ENABLE)) { 3323 DELAY(100 * 1000); 3324 host_diag = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, 3325 fusion_host_diag)); 3326 if (retry++ == 100) { 3327 mrsas_dprint(sc, MRSAS_OCR, 3328 "Host diag unlock failed!\n"); 3329 break; 3330 } 3331 } 3332 if (!(host_diag & HOST_DIAG_WRITE_ENABLE)) 3333 continue; 3334 3335 /* Send chip reset command */ 3336 mrsas_write_reg(sc, offsetof(mrsas_reg_set, fusion_host_diag), 3337 host_diag | HOST_DIAG_RESET_ADAPTER); 3338 DELAY(3000 * 1000); 3339 3340 /* Make sure reset adapter bit is cleared */ 3341 host_diag = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, 3342 fusion_host_diag)); 3343 retry = 0; 3344 while (host_diag & HOST_DIAG_RESET_ADAPTER) { 3345 DELAY(100 * 1000); 3346 host_diag = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, 3347 fusion_host_diag)); 3348 if (retry++ == 1000) { 3349 mrsas_dprint(sc, MRSAS_OCR, 3350 "Diag reset adapter never cleared!\n"); 3351 break; 3352 } 3353 } 3354 if (host_diag & HOST_DIAG_RESET_ADAPTER) 3355 continue; 3356 3357 abs_state = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, 3358 outbound_scratch_pad)) & MFI_STATE_MASK; 3359 retry = 0; 3360 3361 while ((abs_state <= MFI_STATE_FW_INIT) && (retry++ < 1000)) { 3362 DELAY(100 * 1000); 3363 abs_state = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, 3364 outbound_scratch_pad)) & MFI_STATE_MASK; 3365 } 3366 if (abs_state <= MFI_STATE_FW_INIT) { 3367 mrsas_dprint(sc, MRSAS_OCR, "firmware state < MFI_STATE_FW_INIT," 3368 " state = 0x%x\n", abs_state); 3369 continue; 3370 } 3371 /* Wait for FW to become ready */ 3372 if (mrsas_transition_to_ready(sc, 1)) { 3373 mrsas_dprint(sc, MRSAS_OCR, 3374 "mrsas: Failed to transition controller to ready.\n"); 3375 continue; 3376 } 3377 mrsas_reset_reply_desc(sc); 3378 if (mrsas_ioc_init(sc)) { 3379 mrsas_dprint(sc, MRSAS_OCR, "mrsas_ioc_init() failed!\n"); 3380 continue; 3381 } 3382 for (j = 0; j < sc->max_fw_cmds; j++) { 3383 mpt_cmd = sc->mpt_cmd_list[j]; 3384 if (mpt_cmd->sync_cmd_idx != (u_int32_t)MRSAS_ULONG_MAX) { 3385 mfi_cmd = sc->mfi_cmd_list[mpt_cmd->sync_cmd_idx]; 3386 /* If not an IOCTL then release the command else re-fire */ 3387 if (!mfi_cmd->sync_cmd) { 3388 mrsas_release_mfi_cmd(mfi_cmd); 3389 } else { 3390 req_desc = mrsas_get_request_desc(sc, 3391 mfi_cmd->cmd_id.context.smid - 1); 3392 mrsas_dprint(sc, MRSAS_OCR, 3393 "Re-fire command DCMD opcode 0x%x index %d\n ", 3394 mfi_cmd->frame->dcmd.opcode, j); 3395 if (!req_desc) 3396 device_printf(sc->mrsas_dev, 3397 "Cannot build MPT cmd.\n"); 3398 else 3399 mrsas_fire_cmd(sc, req_desc->addr.u.low, 3400 req_desc->addr.u.high); 3401 } 3402 } 3403 } 3404 3405 /* Reset load balance info */ 3406 memset(sc->load_balance_info, 0, 3407 sizeof(LD_LOAD_BALANCE_INFO) * MAX_LOGICAL_DRIVES_EXT); 3408 3409 if (mrsas_get_ctrl_info(sc)) { 3410 mrsas_kill_hba(sc); 3411 retval = FAIL; 3412 goto out; 3413 } 3414 if (!mrsas_get_map_info(sc)) 3415 mrsas_sync_map_info(sc); 3416 3417 megasas_setup_jbod_map(sc); 3418 3419 if ((sc->is_ventura || sc->is_aero) && sc->streamDetectByLD) { 3420 for (j = 0; j < MAX_LOGICAL_DRIVES_EXT; ++j) { 3421 memset(sc->streamDetectByLD[i], 0, sizeof(LD_STREAM_DETECT)); 3422 sc->streamDetectByLD[i]->mruBitMap = MR_STREAM_BITMAP; 3423 } 3424 } 3425 3426 mrsas_clear_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags); 3427 mrsas_enable_intr(sc); 3428 sc->adprecovery = MRSAS_HBA_OPERATIONAL; 3429 3430 /* Register AEN with FW for last sequence number */ 3431 class_locale.members.reserved = 0; 3432 class_locale.members.locale = MR_EVT_LOCALE_ALL; 3433 class_locale.members.class = MR_EVT_CLASS_DEBUG; 3434 3435 mtx_unlock(&sc->sim_lock); 3436 if (mrsas_register_aen(sc, sc->last_seq_num, 3437 class_locale.word)) { 3438 device_printf(sc->mrsas_dev, 3439 "ERROR: AEN registration FAILED from OCR !!! " 3440 "Further events from the controller cannot be notified." 3441 "Either there is some problem in the controller" 3442 "or the controller does not support AEN.\n" 3443 "Please contact to the SUPPORT TEAM if the problem persists\n"); 3444 } 3445 mtx_lock(&sc->sim_lock); 3446 3447 /* Adapter reset completed successfully */ 3448 device_printf(sc->mrsas_dev, "Reset successful\n"); 3449 retval = SUCCESS; 3450 goto out; 3451 } 3452 /* Reset failed, kill the adapter */ 3453 device_printf(sc->mrsas_dev, "Reset failed, killing adapter.\n"); 3454 mrsas_kill_hba(sc); 3455 retval = FAIL; 3456 } else { 3457 mrsas_clear_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags); 3458 mrsas_enable_intr(sc); 3459 sc->adprecovery = MRSAS_HBA_OPERATIONAL; 3460 } 3461 out: 3462 mrsas_clear_bit(MRSAS_FUSION_IN_RESET, &sc->reset_flags); 3463 mrsas_dprint(sc, MRSAS_OCR, 3464 "Reset Exit with %d.\n", retval); 3465 return retval; 3466 } 3467 3468 /* 3469 * mrsas_kill_hba: Kill HBA when OCR is not supported 3470 * input: Adapter Context. 3471 * 3472 * This function will kill HBA when OCR is not supported. 3473 */ 3474 void 3475 mrsas_kill_hba(struct mrsas_softc *sc) 3476 { 3477 sc->adprecovery = MRSAS_HW_CRITICAL_ERROR; 3478 DELAY(1000 * 1000); 3479 mrsas_dprint(sc, MRSAS_OCR, "%s\n", __func__); 3480 mrsas_write_reg(sc, offsetof(mrsas_reg_set, doorbell), 3481 MFI_STOP_ADP); 3482 /* Flush */ 3483 mrsas_read_reg(sc, offsetof(mrsas_reg_set, doorbell)); 3484 mrsas_complete_outstanding_ioctls(sc); 3485 } 3486 3487 /** 3488 * mrsas_complete_outstanding_ioctls Complete pending IOCTLS after kill_hba 3489 * input: Controller softc 3490 * 3491 * Returns void 3492 */ 3493 void 3494 mrsas_complete_outstanding_ioctls(struct mrsas_softc *sc) 3495 { 3496 int i; 3497 struct mrsas_mpt_cmd *cmd_mpt; 3498 struct mrsas_mfi_cmd *cmd_mfi; 3499 u_int32_t count, MSIxIndex; 3500 3501 count = sc->msix_vectors > 0 ? sc->msix_vectors : 1; 3502 for (i = 0; i < sc->max_fw_cmds; i++) { 3503 cmd_mpt = sc->mpt_cmd_list[i]; 3504 3505 if (cmd_mpt->sync_cmd_idx != (u_int32_t)MRSAS_ULONG_MAX) { 3506 cmd_mfi = sc->mfi_cmd_list[cmd_mpt->sync_cmd_idx]; 3507 if (cmd_mfi->sync_cmd && cmd_mfi->frame->hdr.cmd != MFI_CMD_ABORT) { 3508 for (MSIxIndex = 0; MSIxIndex < count; MSIxIndex++) 3509 mrsas_complete_mptmfi_passthru(sc, cmd_mfi, 3510 cmd_mpt->io_request->RaidContext.raid_context.status); 3511 } 3512 } 3513 } 3514 } 3515 3516 /* 3517 * mrsas_wait_for_outstanding: Wait for outstanding commands 3518 * input: Adapter Context. 3519 * 3520 * This function will wait for 180 seconds for outstanding commands to be 3521 * completed. 3522 */ 3523 int 3524 mrsas_wait_for_outstanding(struct mrsas_softc *sc, u_int8_t check_reason) 3525 { 3526 int i, outstanding, retval = 0; 3527 u_int32_t fw_state, count, MSIxIndex; 3528 3529 for (i = 0; i < MRSAS_RESET_WAIT_TIME; i++) { 3530 if (sc->remove_in_progress) { 3531 mrsas_dprint(sc, MRSAS_OCR, 3532 "Driver remove or shutdown called.\n"); 3533 retval = 1; 3534 goto out; 3535 } 3536 /* Check if firmware is in fault state */ 3537 fw_state = mrsas_read_reg_with_retries(sc, offsetof(mrsas_reg_set, 3538 outbound_scratch_pad)) & MFI_STATE_MASK; 3539 if (fw_state == MFI_STATE_FAULT) { 3540 mrsas_dprint(sc, MRSAS_OCR, 3541 "Found FW in FAULT state, will reset adapter.\n"); 3542 count = sc->msix_vectors > 0 ? sc->msix_vectors : 1; 3543 mtx_unlock(&sc->sim_lock); 3544 for (MSIxIndex = 0; MSIxIndex < count; MSIxIndex++) 3545 mrsas_complete_cmd(sc, MSIxIndex); 3546 mtx_lock(&sc->sim_lock); 3547 retval = 1; 3548 goto out; 3549 } 3550 if (check_reason == MFI_DCMD_TIMEOUT_OCR) { 3551 mrsas_dprint(sc, MRSAS_OCR, 3552 "DCMD IO TIMEOUT detected, will reset adapter.\n"); 3553 retval = 1; 3554 goto out; 3555 } 3556 outstanding = mrsas_atomic_read(&sc->fw_outstanding); 3557 if (!outstanding) 3558 goto out; 3559 3560 if (!(i % MRSAS_RESET_NOTICE_INTERVAL)) { 3561 mrsas_dprint(sc, MRSAS_OCR, "[%2d]waiting for %d " 3562 "commands to complete\n", i, outstanding); 3563 count = sc->msix_vectors > 0 ? sc->msix_vectors : 1; 3564 mtx_unlock(&sc->sim_lock); 3565 for (MSIxIndex = 0; MSIxIndex < count; MSIxIndex++) 3566 mrsas_complete_cmd(sc, MSIxIndex); 3567 mtx_lock(&sc->sim_lock); 3568 } 3569 DELAY(1000 * 1000); 3570 } 3571 3572 if (mrsas_atomic_read(&sc->fw_outstanding)) { 3573 mrsas_dprint(sc, MRSAS_OCR, 3574 " pending commands remain after waiting," 3575 " will reset adapter.\n"); 3576 retval = 1; 3577 } 3578 out: 3579 return retval; 3580 } 3581 3582 /* 3583 * mrsas_release_mfi_cmd: Return a cmd to free command pool 3584 * input: Command packet for return to free cmd pool 3585 * 3586 * This function returns the MFI & MPT command to the command list. 3587 */ 3588 void 3589 mrsas_release_mfi_cmd(struct mrsas_mfi_cmd *cmd_mfi) 3590 { 3591 struct mrsas_softc *sc = cmd_mfi->sc; 3592 struct mrsas_mpt_cmd *cmd_mpt; 3593 3594 mtx_lock(&sc->mfi_cmd_pool_lock); 3595 /* 3596 * Release the mpt command (if at all it is allocated 3597 * associated with the mfi command 3598 */ 3599 if (cmd_mfi->cmd_id.context.smid) { 3600 mtx_lock(&sc->mpt_cmd_pool_lock); 3601 /* Get the mpt cmd from mfi cmd frame's smid value */ 3602 cmd_mpt = sc->mpt_cmd_list[cmd_mfi->cmd_id.context.smid-1]; 3603 cmd_mpt->flags = 0; 3604 cmd_mpt->sync_cmd_idx = (u_int32_t)MRSAS_ULONG_MAX; 3605 TAILQ_INSERT_HEAD(&(sc->mrsas_mpt_cmd_list_head), cmd_mpt, next); 3606 mtx_unlock(&sc->mpt_cmd_pool_lock); 3607 } 3608 /* Release the mfi command */ 3609 cmd_mfi->ccb_ptr = NULL; 3610 cmd_mfi->cmd_id.frame_count = 0; 3611 TAILQ_INSERT_HEAD(&(sc->mrsas_mfi_cmd_list_head), cmd_mfi, next); 3612 mtx_unlock(&sc->mfi_cmd_pool_lock); 3613 3614 return; 3615 } 3616 3617 /* 3618 * mrsas_get_controller_info: Returns FW's controller structure 3619 * input: Adapter soft state 3620 * Controller information structure 3621 * 3622 * Issues an internal command (DCMD) to get the FW's controller structure. This 3623 * information is mainly used to find out the maximum IO transfer per command 3624 * supported by the FW. 3625 */ 3626 static int 3627 mrsas_get_ctrl_info(struct mrsas_softc *sc) 3628 { 3629 int retcode = 0; 3630 u_int8_t do_ocr = 1; 3631 struct mrsas_mfi_cmd *cmd; 3632 struct mrsas_dcmd_frame *dcmd; 3633 3634 cmd = mrsas_get_mfi_cmd(sc); 3635 3636 if (!cmd) { 3637 device_printf(sc->mrsas_dev, "Failed to get a free cmd\n"); 3638 return -ENOMEM; 3639 } 3640 dcmd = &cmd->frame->dcmd; 3641 3642 if (mrsas_alloc_ctlr_info_cmd(sc) != SUCCESS) { 3643 device_printf(sc->mrsas_dev, "Cannot allocate get ctlr info cmd\n"); 3644 mrsas_release_mfi_cmd(cmd); 3645 return -ENOMEM; 3646 } 3647 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 3648 3649 dcmd->cmd = MFI_CMD_DCMD; 3650 dcmd->cmd_status = 0xFF; 3651 dcmd->sge_count = 1; 3652 dcmd->flags = MFI_FRAME_DIR_READ; 3653 dcmd->timeout = 0; 3654 dcmd->pad_0 = 0; 3655 dcmd->data_xfer_len = htole32(sizeof(struct mrsas_ctrl_info)); 3656 dcmd->opcode = htole32(MR_DCMD_CTRL_GET_INFO); 3657 dcmd->sgl.sge32[0].phys_addr = htole32(sc->ctlr_info_phys_addr & 0xFFFFFFFF); 3658 dcmd->sgl.sge32[0].length = htole32(sizeof(struct mrsas_ctrl_info)); 3659 3660 if (!sc->mask_interrupts) 3661 retcode = mrsas_issue_blocked_cmd(sc, cmd); 3662 else 3663 retcode = mrsas_issue_polled(sc, cmd); 3664 3665 if (retcode == ETIMEDOUT) 3666 goto dcmd_timeout; 3667 else { 3668 memcpy(sc->ctrl_info, sc->ctlr_info_mem, sizeof(struct mrsas_ctrl_info)); 3669 le32_to_cpus(&sc->ctrl_info->properties.OnOffProperties); 3670 le32_to_cpus(&sc->ctrl_info->adapterOperations2); 3671 le32_to_cpus(&sc->ctrl_info->adapterOperations3); 3672 le16_to_cpus(&sc->ctrl_info->adapterOperations4); 3673 } 3674 3675 do_ocr = 0; 3676 mrsas_update_ext_vd_details(sc); 3677 3678 sc->use_seqnum_jbod_fp = 3679 sc->ctrl_info->adapterOperations3.useSeqNumJbodFP; 3680 sc->support_morethan256jbod = 3681 sc->ctrl_info->adapterOperations4.supportPdMapTargetId; 3682 3683 sc->disableOnlineCtrlReset = 3684 sc->ctrl_info->properties.OnOffProperties.disableOnlineCtrlReset; 3685 3686 dcmd_timeout: 3687 mrsas_free_ctlr_info_cmd(sc); 3688 3689 if (do_ocr) 3690 sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR; 3691 3692 if (!sc->mask_interrupts) 3693 mrsas_release_mfi_cmd(cmd); 3694 3695 return (retcode); 3696 } 3697 3698 /* 3699 * mrsas_update_ext_vd_details : Update details w.r.t Extended VD 3700 * input: 3701 * sc - Controller's softc 3702 */ 3703 static void 3704 mrsas_update_ext_vd_details(struct mrsas_softc *sc) 3705 { 3706 u_int32_t ventura_map_sz = 0; 3707 sc->max256vdSupport = 3708 sc->ctrl_info->adapterOperations3.supportMaxExtLDs; 3709 3710 /* Below is additional check to address future FW enhancement */ 3711 if (sc->ctrl_info->max_lds > 64) 3712 sc->max256vdSupport = 1; 3713 3714 sc->drv_supported_vd_count = MRSAS_MAX_LD_CHANNELS 3715 * MRSAS_MAX_DEV_PER_CHANNEL; 3716 sc->drv_supported_pd_count = MRSAS_MAX_PD_CHANNELS 3717 * MRSAS_MAX_DEV_PER_CHANNEL; 3718 if (sc->max256vdSupport) { 3719 sc->fw_supported_vd_count = MAX_LOGICAL_DRIVES_EXT; 3720 sc->fw_supported_pd_count = MAX_PHYSICAL_DEVICES; 3721 } else { 3722 sc->fw_supported_vd_count = MAX_LOGICAL_DRIVES; 3723 sc->fw_supported_pd_count = MAX_PHYSICAL_DEVICES; 3724 } 3725 3726 if (sc->maxRaidMapSize) { 3727 ventura_map_sz = sc->maxRaidMapSize * 3728 MR_MIN_MAP_SIZE; 3729 sc->current_map_sz = ventura_map_sz; 3730 sc->max_map_sz = ventura_map_sz; 3731 } else { 3732 sc->old_map_sz = sizeof(MR_FW_RAID_MAP) + 3733 (sizeof(MR_LD_SPAN_MAP) * (sc->fw_supported_vd_count - 1)); 3734 sc->new_map_sz = sizeof(MR_FW_RAID_MAP_EXT); 3735 sc->max_map_sz = max(sc->old_map_sz, sc->new_map_sz); 3736 if (sc->max256vdSupport) 3737 sc->current_map_sz = sc->new_map_sz; 3738 else 3739 sc->current_map_sz = sc->old_map_sz; 3740 } 3741 3742 sc->drv_map_sz = sizeof(MR_DRV_RAID_MAP_ALL); 3743 #if VD_EXT_DEBUG 3744 device_printf(sc->mrsas_dev, "sc->maxRaidMapSize 0x%x \n", 3745 sc->maxRaidMapSize); 3746 device_printf(sc->mrsas_dev, 3747 "new_map_sz = 0x%x, old_map_sz = 0x%x, " 3748 "ventura_map_sz = 0x%x, current_map_sz = 0x%x " 3749 "fusion->drv_map_sz =0x%x, size of driver raid map 0x%lx \n", 3750 sc->new_map_sz, sc->old_map_sz, ventura_map_sz, 3751 sc->current_map_sz, sc->drv_map_sz, sizeof(MR_DRV_RAID_MAP_ALL)); 3752 #endif 3753 } 3754 3755 /* 3756 * mrsas_alloc_ctlr_info_cmd: Allocates memory for controller info command 3757 * input: Adapter soft state 3758 * 3759 * Allocates DMAable memory for the controller info internal command. 3760 */ 3761 int 3762 mrsas_alloc_ctlr_info_cmd(struct mrsas_softc *sc) 3763 { 3764 int ctlr_info_size; 3765 3766 /* Allocate get controller info command */ 3767 ctlr_info_size = sizeof(struct mrsas_ctrl_info); 3768 if (bus_dma_tag_create(sc->mrsas_parent_tag, 3769 1, 0, 3770 BUS_SPACE_MAXADDR_32BIT, 3771 BUS_SPACE_MAXADDR, 3772 NULL, NULL, 3773 ctlr_info_size, 3774 1, 3775 ctlr_info_size, 3776 BUS_DMA_ALLOCNOW, 3777 NULL, NULL, 3778 &sc->ctlr_info_tag)) { 3779 device_printf(sc->mrsas_dev, "Cannot allocate ctlr info tag\n"); 3780 return (ENOMEM); 3781 } 3782 if (bus_dmamem_alloc(sc->ctlr_info_tag, (void **)&sc->ctlr_info_mem, 3783 BUS_DMA_NOWAIT, &sc->ctlr_info_dmamap)) { 3784 device_printf(sc->mrsas_dev, "Cannot allocate ctlr info cmd mem\n"); 3785 return (ENOMEM); 3786 } 3787 if (bus_dmamap_load(sc->ctlr_info_tag, sc->ctlr_info_dmamap, 3788 sc->ctlr_info_mem, ctlr_info_size, mrsas_addr_cb, 3789 &sc->ctlr_info_phys_addr, BUS_DMA_NOWAIT)) { 3790 device_printf(sc->mrsas_dev, "Cannot load ctlr info cmd mem\n"); 3791 return (ENOMEM); 3792 } 3793 memset(sc->ctlr_info_mem, 0, ctlr_info_size); 3794 return (0); 3795 } 3796 3797 /* 3798 * mrsas_free_ctlr_info_cmd: Free memory for controller info command 3799 * input: Adapter soft state 3800 * 3801 * Deallocates memory of the get controller info cmd. 3802 */ 3803 void 3804 mrsas_free_ctlr_info_cmd(struct mrsas_softc *sc) 3805 { 3806 if (sc->ctlr_info_phys_addr) 3807 bus_dmamap_unload(sc->ctlr_info_tag, sc->ctlr_info_dmamap); 3808 if (sc->ctlr_info_mem != NULL) 3809 bus_dmamem_free(sc->ctlr_info_tag, sc->ctlr_info_mem, sc->ctlr_info_dmamap); 3810 if (sc->ctlr_info_tag != NULL) 3811 bus_dma_tag_destroy(sc->ctlr_info_tag); 3812 } 3813 3814 /* 3815 * mrsas_issue_polled: Issues a polling command 3816 * inputs: Adapter soft state 3817 * Command packet to be issued 3818 * 3819 * This function is for posting of internal commands to Firmware. MFI requires 3820 * the cmd_status to be set to 0xFF before posting. The maximun wait time of 3821 * the poll response timer is 180 seconds. 3822 */ 3823 int 3824 mrsas_issue_polled(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 3825 { 3826 struct mrsas_header *frame_hdr = &cmd->frame->hdr; 3827 u_int8_t max_wait = MRSAS_INTERNAL_CMD_WAIT_TIME; 3828 int i, retcode = SUCCESS; 3829 3830 frame_hdr->cmd_status = 0xFF; 3831 frame_hdr->flags |= htole16(MFI_FRAME_DONT_POST_IN_REPLY_QUEUE); 3832 3833 /* Issue the frame using inbound queue port */ 3834 if (mrsas_issue_dcmd(sc, cmd)) { 3835 device_printf(sc->mrsas_dev, "Cannot issue DCMD internal command.\n"); 3836 return (1); 3837 } 3838 /* 3839 * Poll response timer to wait for Firmware response. While this 3840 * timer with the DELAY call could block CPU, the time interval for 3841 * this is only 1 millisecond. 3842 */ 3843 if (frame_hdr->cmd_status == 0xFF) { 3844 for (i = 0; i < (max_wait * 1000); i++) { 3845 if (frame_hdr->cmd_status == 0xFF) 3846 DELAY(1000); 3847 else 3848 break; 3849 } 3850 } 3851 if (frame_hdr->cmd_status == 0xFF) { 3852 device_printf(sc->mrsas_dev, "DCMD timed out after %d " 3853 "seconds from %s\n", max_wait, __func__); 3854 device_printf(sc->mrsas_dev, "DCMD opcode 0x%X\n", 3855 cmd->frame->dcmd.opcode); 3856 retcode = ETIMEDOUT; 3857 } 3858 return (retcode); 3859 } 3860 3861 /* 3862 * mrsas_issue_dcmd: Issues a MFI Pass thru cmd 3863 * input: Adapter soft state mfi cmd pointer 3864 * 3865 * This function is called by mrsas_issued_blocked_cmd() and 3866 * mrsas_issued_polled(), to build the MPT command and then fire the command 3867 * to Firmware. 3868 */ 3869 int 3870 mrsas_issue_dcmd(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 3871 { 3872 MRSAS_REQUEST_DESCRIPTOR_UNION *req_desc; 3873 3874 req_desc = mrsas_build_mpt_cmd(sc, cmd); 3875 if (!req_desc) { 3876 device_printf(sc->mrsas_dev, "Cannot build MPT cmd.\n"); 3877 return (1); 3878 } 3879 mrsas_fire_cmd(sc, req_desc->addr.u.low, req_desc->addr.u.high); 3880 3881 return (0); 3882 } 3883 3884 /* 3885 * mrsas_build_mpt_cmd: Calls helper function to build Passthru cmd 3886 * input: Adapter soft state mfi cmd to build 3887 * 3888 * This function is called by mrsas_issue_cmd() to build the MPT-MFI passthru 3889 * command and prepares the MPT command to send to Firmware. 3890 */ 3891 MRSAS_REQUEST_DESCRIPTOR_UNION * 3892 mrsas_build_mpt_cmd(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 3893 { 3894 MRSAS_REQUEST_DESCRIPTOR_UNION *req_desc; 3895 u_int16_t index; 3896 3897 if (mrsas_build_mptmfi_passthru(sc, cmd)) { 3898 device_printf(sc->mrsas_dev, "Cannot build MPT-MFI passthru cmd.\n"); 3899 return NULL; 3900 } 3901 index = cmd->cmd_id.context.smid; 3902 3903 req_desc = mrsas_get_request_desc(sc, index - 1); 3904 if (!req_desc) 3905 return NULL; 3906 3907 req_desc->addr.Words = 0; 3908 req_desc->SCSIIO.RequestFlags = (MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO << MRSAS_REQ_DESCRIPT_FLAGS_TYPE_SHIFT); 3909 3910 req_desc->SCSIIO.SMID = htole16(index); 3911 3912 return (req_desc); 3913 } 3914 3915 /* 3916 * mrsas_build_mptmfi_passthru: Builds a MPT MFI Passthru command 3917 * input: Adapter soft state mfi cmd pointer 3918 * 3919 * The MPT command and the io_request are setup as a passthru command. The SGE 3920 * chain address is set to frame_phys_addr of the MFI command. 3921 */ 3922 u_int8_t 3923 mrsas_build_mptmfi_passthru(struct mrsas_softc *sc, struct mrsas_mfi_cmd *mfi_cmd) 3924 { 3925 MPI25_IEEE_SGE_CHAIN64 *mpi25_ieee_chain; 3926 PTR_MRSAS_RAID_SCSI_IO_REQUEST io_req; 3927 struct mrsas_mpt_cmd *mpt_cmd; 3928 struct mrsas_header *frame_hdr = &mfi_cmd->frame->hdr; 3929 3930 mpt_cmd = mrsas_get_mpt_cmd(sc); 3931 if (!mpt_cmd) 3932 return (1); 3933 3934 /* Save the smid. To be used for returning the cmd */ 3935 mfi_cmd->cmd_id.context.smid = mpt_cmd->index; 3936 3937 mpt_cmd->sync_cmd_idx = mfi_cmd->index; 3938 3939 /* 3940 * For cmds where the flag is set, store the flag and check on 3941 * completion. For cmds with this flag, don't call 3942 * mrsas_complete_cmd. 3943 */ 3944 3945 if (frame_hdr->flags & htole16(MFI_FRAME_DONT_POST_IN_REPLY_QUEUE)) 3946 mpt_cmd->flags = MFI_FRAME_DONT_POST_IN_REPLY_QUEUE; 3947 3948 io_req = mpt_cmd->io_request; 3949 3950 if (sc->mrsas_gen3_ctrl || sc->is_ventura || sc->is_aero) { 3951 pMpi25IeeeSgeChain64_t sgl_ptr_end = (pMpi25IeeeSgeChain64_t)&io_req->SGL; 3952 3953 sgl_ptr_end += sc->max_sge_in_main_msg - 1; 3954 sgl_ptr_end->Flags = 0; 3955 } 3956 mpi25_ieee_chain = (MPI25_IEEE_SGE_CHAIN64 *) & io_req->SGL.IeeeChain; 3957 3958 io_req->Function = MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST; 3959 io_req->SGLOffset0 = offsetof(MRSAS_RAID_SCSI_IO_REQUEST, SGL) / 4; 3960 io_req->ChainOffset = sc->chain_offset_mfi_pthru; 3961 3962 mpi25_ieee_chain->Address = htole64(mfi_cmd->frame_phys_addr); 3963 3964 mpi25_ieee_chain->Flags = IEEE_SGE_FLAGS_CHAIN_ELEMENT | 3965 MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR; 3966 3967 mpi25_ieee_chain->Length = htole32(sc->max_chain_frame_sz); 3968 3969 return (0); 3970 } 3971 3972 /* 3973 * mrsas_issue_blocked_cmd: Synchronous wrapper around regular FW cmds 3974 * input: Adapter soft state Command to be issued 3975 * 3976 * This function waits on an event for the command to be returned from the ISR. 3977 * Max wait time is MRSAS_INTERNAL_CMD_WAIT_TIME secs. Used for issuing 3978 * internal and ioctl commands. 3979 */ 3980 int 3981 mrsas_issue_blocked_cmd(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 3982 { 3983 u_int8_t max_wait = MRSAS_INTERNAL_CMD_WAIT_TIME; 3984 unsigned long total_time = 0; 3985 int retcode = SUCCESS; 3986 3987 /* Initialize cmd_status */ 3988 cmd->cmd_status = 0xFF; 3989 3990 /* Build MPT-MFI command for issue to FW */ 3991 if (mrsas_issue_dcmd(sc, cmd)) { 3992 device_printf(sc->mrsas_dev, "Cannot issue DCMD internal command.\n"); 3993 return (1); 3994 } 3995 sc->chan = (void *)&cmd; 3996 3997 while (1) { 3998 if (cmd->cmd_status == 0xFF) { 3999 tsleep((void *)&sc->chan, 0, "mrsas_sleep", hz); 4000 } else 4001 break; 4002 4003 if (!cmd->sync_cmd) { /* cmd->sync will be set for an IOCTL 4004 * command */ 4005 total_time++; 4006 if (total_time >= max_wait) { 4007 device_printf(sc->mrsas_dev, 4008 "Internal command timed out after %d seconds.\n", max_wait); 4009 retcode = 1; 4010 break; 4011 } 4012 } 4013 } 4014 4015 if (cmd->cmd_status == 0xFF) { 4016 device_printf(sc->mrsas_dev, "DCMD timed out after %d " 4017 "seconds from %s\n", max_wait, __func__); 4018 device_printf(sc->mrsas_dev, "DCMD opcode 0x%X\n", 4019 cmd->frame->dcmd.opcode); 4020 retcode = ETIMEDOUT; 4021 } 4022 return (retcode); 4023 } 4024 4025 /* 4026 * mrsas_complete_mptmfi_passthru: Completes a command 4027 * input: @sc: Adapter soft state 4028 * @cmd: Command to be completed 4029 * @status: cmd completion status 4030 * 4031 * This function is called from mrsas_complete_cmd() after an interrupt is 4032 * received from Firmware, and io_request->Function is 4033 * MRSAS_MPI2_FUNCTION_PASSTHRU_IO_REQUEST. 4034 */ 4035 void 4036 mrsas_complete_mptmfi_passthru(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd, 4037 u_int8_t status) 4038 { 4039 struct mrsas_header *hdr = &cmd->frame->hdr; 4040 u_int8_t cmd_status = cmd->frame->hdr.cmd_status; 4041 4042 /* Reset the retry counter for future re-tries */ 4043 cmd->retry_for_fw_reset = 0; 4044 4045 if (cmd->ccb_ptr) 4046 cmd->ccb_ptr = NULL; 4047 4048 switch (hdr->cmd) { 4049 case MFI_CMD_INVALID: 4050 device_printf(sc->mrsas_dev, "MFI_CMD_INVALID command.\n"); 4051 break; 4052 case MFI_CMD_PD_SCSI_IO: 4053 case MFI_CMD_LD_SCSI_IO: 4054 /* 4055 * MFI_CMD_PD_SCSI_IO and MFI_CMD_LD_SCSI_IO could have been 4056 * issued either through an IO path or an IOCTL path. If it 4057 * was via IOCTL, we will send it to internal completion. 4058 */ 4059 if (cmd->sync_cmd) { 4060 cmd->sync_cmd = 0; 4061 mrsas_wakeup(sc, cmd); 4062 break; 4063 } 4064 case MFI_CMD_SMP: 4065 case MFI_CMD_STP: 4066 case MFI_CMD_DCMD: 4067 /* Check for LD map update */ 4068 if ((cmd->frame->dcmd.opcode == MR_DCMD_LD_MAP_GET_INFO) && 4069 (cmd->frame->dcmd.mbox.b[1] == 1)) { 4070 sc->fast_path_io = 0; 4071 mtx_lock(&sc->raidmap_lock); 4072 sc->map_update_cmd = NULL; 4073 if (cmd_status != 0) { 4074 if (cmd_status != MFI_STAT_NOT_FOUND) 4075 device_printf(sc->mrsas_dev, "map sync failed, status=%x\n", cmd_status); 4076 else { 4077 mrsas_release_mfi_cmd(cmd); 4078 mtx_unlock(&sc->raidmap_lock); 4079 break; 4080 } 4081 } else 4082 sc->map_id++; 4083 mrsas_release_mfi_cmd(cmd); 4084 if (MR_ValidateMapInfo(sc)) 4085 sc->fast_path_io = 0; 4086 else 4087 sc->fast_path_io = 1; 4088 mrsas_sync_map_info(sc); 4089 mtx_unlock(&sc->raidmap_lock); 4090 break; 4091 } 4092 if (cmd->frame->dcmd.opcode == MR_DCMD_CTRL_EVENT_GET_INFO || 4093 cmd->frame->dcmd.opcode == MR_DCMD_CTRL_EVENT_GET) { 4094 sc->mrsas_aen_triggered = 0; 4095 } 4096 /* FW has an updated PD sequence */ 4097 if ((cmd->frame->dcmd.opcode == 4098 MR_DCMD_SYSTEM_PD_MAP_GET_INFO) && 4099 (cmd->frame->dcmd.mbox.b[0] == 1)) { 4100 mtx_lock(&sc->raidmap_lock); 4101 sc->jbod_seq_cmd = NULL; 4102 mrsas_release_mfi_cmd(cmd); 4103 4104 if (cmd_status == MFI_STAT_OK) { 4105 sc->pd_seq_map_id++; 4106 /* Re-register a pd sync seq num cmd */ 4107 if (megasas_sync_pd_seq_num(sc, true)) 4108 sc->use_seqnum_jbod_fp = 0; 4109 } else { 4110 sc->use_seqnum_jbod_fp = 0; 4111 device_printf(sc->mrsas_dev, 4112 "Jbod map sync failed, status=%x\n", cmd_status); 4113 } 4114 mtx_unlock(&sc->raidmap_lock); 4115 break; 4116 } 4117 /* See if got an event notification */ 4118 if (le32toh(cmd->frame->dcmd.opcode) == MR_DCMD_CTRL_EVENT_WAIT) 4119 mrsas_complete_aen(sc, cmd); 4120 else 4121 mrsas_wakeup(sc, cmd); 4122 break; 4123 case MFI_CMD_ABORT: 4124 /* Command issued to abort another cmd return */ 4125 mrsas_complete_abort(sc, cmd); 4126 break; 4127 default: 4128 device_printf(sc->mrsas_dev, "Unknown command completed! [0x%X]\n", hdr->cmd); 4129 break; 4130 } 4131 } 4132 4133 /* 4134 * mrsas_wakeup: Completes an internal command 4135 * input: Adapter soft state 4136 * Command to be completed 4137 * 4138 * In mrsas_issue_blocked_cmd(), after a command is issued to Firmware, a wait 4139 * timer is started. This function is called from 4140 * mrsas_complete_mptmfi_passthru() as it completes the command, to wake up 4141 * from the command wait. 4142 */ 4143 void 4144 mrsas_wakeup(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 4145 { 4146 cmd->cmd_status = cmd->frame->io.cmd_status; 4147 4148 if (cmd->cmd_status == 0xFF) 4149 cmd->cmd_status = 0; 4150 4151 sc->chan = (void *)&cmd; 4152 wakeup_one((void *)&sc->chan); 4153 return; 4154 } 4155 4156 /* 4157 * mrsas_shutdown_ctlr: Instructs FW to shutdown the controller input: 4158 * Adapter soft state Shutdown/Hibernate 4159 * 4160 * This function issues a DCMD internal command to Firmware to initiate shutdown 4161 * of the controller. 4162 */ 4163 static void 4164 mrsas_shutdown_ctlr(struct mrsas_softc *sc, u_int32_t opcode) 4165 { 4166 struct mrsas_mfi_cmd *cmd; 4167 struct mrsas_dcmd_frame *dcmd; 4168 4169 if (sc->adprecovery == MRSAS_HW_CRITICAL_ERROR) 4170 return; 4171 4172 cmd = mrsas_get_mfi_cmd(sc); 4173 if (!cmd) { 4174 device_printf(sc->mrsas_dev, "Cannot allocate for shutdown cmd.\n"); 4175 return; 4176 } 4177 if (sc->aen_cmd) 4178 mrsas_issue_blocked_abort_cmd(sc, sc->aen_cmd); 4179 if (sc->map_update_cmd) 4180 mrsas_issue_blocked_abort_cmd(sc, sc->map_update_cmd); 4181 if (sc->jbod_seq_cmd) 4182 mrsas_issue_blocked_abort_cmd(sc, sc->jbod_seq_cmd); 4183 4184 dcmd = &cmd->frame->dcmd; 4185 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 4186 4187 dcmd->cmd = MFI_CMD_DCMD; 4188 dcmd->cmd_status = 0x0; 4189 dcmd->sge_count = 0; 4190 dcmd->flags = MFI_FRAME_DIR_NONE; 4191 dcmd->timeout = 0; 4192 dcmd->pad_0 = 0; 4193 dcmd->data_xfer_len = 0; 4194 dcmd->opcode = opcode; 4195 4196 device_printf(sc->mrsas_dev, "Preparing to shut down controller.\n"); 4197 4198 mrsas_issue_blocked_cmd(sc, cmd); 4199 mrsas_release_mfi_cmd(cmd); 4200 4201 return; 4202 } 4203 4204 /* 4205 * mrsas_flush_cache: Requests FW to flush all its caches input: 4206 * Adapter soft state 4207 * 4208 * This function is issues a DCMD internal command to Firmware to initiate 4209 * flushing of all caches. 4210 */ 4211 static void 4212 mrsas_flush_cache(struct mrsas_softc *sc) 4213 { 4214 struct mrsas_mfi_cmd *cmd; 4215 struct mrsas_dcmd_frame *dcmd; 4216 4217 if (sc->adprecovery == MRSAS_HW_CRITICAL_ERROR) 4218 return; 4219 4220 cmd = mrsas_get_mfi_cmd(sc); 4221 if (!cmd) { 4222 device_printf(sc->mrsas_dev, "Cannot allocate for flush cache cmd.\n"); 4223 return; 4224 } 4225 dcmd = &cmd->frame->dcmd; 4226 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 4227 4228 dcmd->cmd = MFI_CMD_DCMD; 4229 dcmd->cmd_status = 0x0; 4230 dcmd->sge_count = 0; 4231 dcmd->flags = MFI_FRAME_DIR_NONE; 4232 dcmd->timeout = 0; 4233 dcmd->pad_0 = 0; 4234 dcmd->data_xfer_len = 0; 4235 dcmd->opcode = MR_DCMD_CTRL_CACHE_FLUSH; 4236 dcmd->mbox.b[0] = MR_FLUSH_CTRL_CACHE | MR_FLUSH_DISK_CACHE; 4237 4238 mrsas_issue_blocked_cmd(sc, cmd); 4239 mrsas_release_mfi_cmd(cmd); 4240 4241 return; 4242 } 4243 4244 int 4245 megasas_sync_pd_seq_num(struct mrsas_softc *sc, boolean_t pend) 4246 { 4247 int retcode = 0; 4248 u_int8_t do_ocr = 1; 4249 struct mrsas_mfi_cmd *cmd; 4250 struct mrsas_dcmd_frame *dcmd; 4251 uint32_t pd_seq_map_sz; 4252 struct MR_PD_CFG_SEQ_NUM_SYNC *pd_sync; 4253 bus_addr_t pd_seq_h; 4254 4255 pd_seq_map_sz = sizeof(struct MR_PD_CFG_SEQ_NUM_SYNC) + 4256 (sizeof(struct MR_PD_CFG_SEQ) * 4257 (MAX_PHYSICAL_DEVICES - 1)); 4258 4259 cmd = mrsas_get_mfi_cmd(sc); 4260 if (!cmd) { 4261 device_printf(sc->mrsas_dev, 4262 "Cannot alloc for ld map info cmd.\n"); 4263 return 1; 4264 } 4265 dcmd = &cmd->frame->dcmd; 4266 4267 pd_sync = (void *)sc->jbodmap_mem[(sc->pd_seq_map_id & 1)]; 4268 pd_seq_h = sc->jbodmap_phys_addr[(sc->pd_seq_map_id & 1)]; 4269 if (!pd_sync) { 4270 device_printf(sc->mrsas_dev, 4271 "Failed to alloc mem for jbod map info.\n"); 4272 mrsas_release_mfi_cmd(cmd); 4273 return (ENOMEM); 4274 } 4275 memset(pd_sync, 0, pd_seq_map_sz); 4276 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 4277 dcmd->cmd = MFI_CMD_DCMD; 4278 dcmd->cmd_status = 0xFF; 4279 dcmd->sge_count = 1; 4280 dcmd->timeout = 0; 4281 dcmd->pad_0 = 0; 4282 dcmd->data_xfer_len = htole32(pd_seq_map_sz); 4283 dcmd->opcode = htole32(MR_DCMD_SYSTEM_PD_MAP_GET_INFO); 4284 dcmd->sgl.sge32[0].phys_addr = htole32(pd_seq_h & 0xFFFFFFFF); 4285 dcmd->sgl.sge32[0].length = htole32(pd_seq_map_sz); 4286 4287 if (pend) { 4288 dcmd->mbox.b[0] = MRSAS_DCMD_MBOX_PEND_FLAG; 4289 dcmd->flags = htole16(MFI_FRAME_DIR_WRITE); 4290 sc->jbod_seq_cmd = cmd; 4291 if (mrsas_issue_dcmd(sc, cmd)) { 4292 device_printf(sc->mrsas_dev, 4293 "Fail to send sync map info command.\n"); 4294 return 1; 4295 } else 4296 return 0; 4297 } else 4298 dcmd->flags = htole16(MFI_FRAME_DIR_READ); 4299 4300 retcode = mrsas_issue_polled(sc, cmd); 4301 if (retcode == ETIMEDOUT) 4302 goto dcmd_timeout; 4303 4304 if (le32toh(pd_sync->count) > MAX_PHYSICAL_DEVICES) { 4305 device_printf(sc->mrsas_dev, 4306 "driver supports max %d JBOD, but FW reports %d\n", 4307 MAX_PHYSICAL_DEVICES, pd_sync->count); 4308 retcode = -EINVAL; 4309 } 4310 if (!retcode) 4311 sc->pd_seq_map_id++; 4312 do_ocr = 0; 4313 4314 dcmd_timeout: 4315 if (do_ocr) 4316 sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR; 4317 4318 return (retcode); 4319 } 4320 4321 /* 4322 * mrsas_get_map_info: Load and validate RAID map input: 4323 * Adapter instance soft state 4324 * 4325 * This function calls mrsas_get_ld_map_info() and MR_ValidateMapInfo() to load 4326 * and validate RAID map. It returns 0 if successful, 1 other- wise. 4327 */ 4328 static int 4329 mrsas_get_map_info(struct mrsas_softc *sc) 4330 { 4331 uint8_t retcode = 0; 4332 4333 sc->fast_path_io = 0; 4334 if (!mrsas_get_ld_map_info(sc)) { 4335 retcode = MR_ValidateMapInfo(sc); 4336 if (retcode == 0) { 4337 sc->fast_path_io = 1; 4338 return 0; 4339 } 4340 } 4341 return 1; 4342 } 4343 4344 /* 4345 * mrsas_get_ld_map_info: Get FW's ld_map structure input: 4346 * Adapter instance soft state 4347 * 4348 * Issues an internal command (DCMD) to get the FW's controller PD list 4349 * structure. 4350 */ 4351 static int 4352 mrsas_get_ld_map_info(struct mrsas_softc *sc) 4353 { 4354 int retcode = 0; 4355 struct mrsas_mfi_cmd *cmd; 4356 struct mrsas_dcmd_frame *dcmd; 4357 void *map; 4358 bus_addr_t map_phys_addr = 0; 4359 4360 cmd = mrsas_get_mfi_cmd(sc); 4361 if (!cmd) { 4362 device_printf(sc->mrsas_dev, 4363 "Cannot alloc for ld map info cmd.\n"); 4364 return 1; 4365 } 4366 dcmd = &cmd->frame->dcmd; 4367 4368 map = (void *)sc->raidmap_mem[(sc->map_id & 1)]; 4369 map_phys_addr = sc->raidmap_phys_addr[(sc->map_id & 1)]; 4370 if (!map) { 4371 device_printf(sc->mrsas_dev, 4372 "Failed to alloc mem for ld map info.\n"); 4373 mrsas_release_mfi_cmd(cmd); 4374 return (ENOMEM); 4375 } 4376 memset(map, 0, sizeof(sc->max_map_sz)); 4377 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 4378 4379 dcmd->cmd = MFI_CMD_DCMD; 4380 dcmd->cmd_status = 0xFF; 4381 dcmd->sge_count = 1; 4382 dcmd->flags = htole16(MFI_FRAME_DIR_READ); 4383 dcmd->timeout = 0; 4384 dcmd->pad_0 = 0; 4385 dcmd->data_xfer_len = htole32(sc->current_map_sz); 4386 dcmd->opcode = htole32(MR_DCMD_LD_MAP_GET_INFO); 4387 dcmd->sgl.sge32[0].phys_addr = htole32(map_phys_addr & 0xFFFFFFFF); 4388 dcmd->sgl.sge32[0].length = htole32(sc->current_map_sz); 4389 4390 retcode = mrsas_issue_polled(sc, cmd); 4391 if (retcode == ETIMEDOUT) 4392 sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR; 4393 4394 return (retcode); 4395 } 4396 4397 /* 4398 * mrsas_sync_map_info: Get FW's ld_map structure input: 4399 * Adapter instance soft state 4400 * 4401 * Issues an internal command (DCMD) to get the FW's controller PD list 4402 * structure. 4403 */ 4404 static int 4405 mrsas_sync_map_info(struct mrsas_softc *sc) 4406 { 4407 int retcode = 0, i; 4408 struct mrsas_mfi_cmd *cmd; 4409 struct mrsas_dcmd_frame *dcmd; 4410 uint32_t size_sync_info, num_lds; 4411 MR_LD_TARGET_SYNC *target_map = NULL; 4412 MR_DRV_RAID_MAP_ALL *map; 4413 MR_LD_RAID *raid; 4414 MR_LD_TARGET_SYNC *ld_sync; 4415 bus_addr_t map_phys_addr = 0; 4416 4417 cmd = mrsas_get_mfi_cmd(sc); 4418 if (!cmd) { 4419 device_printf(sc->mrsas_dev, "Cannot alloc for sync map info cmd\n"); 4420 return ENOMEM; 4421 } 4422 map = sc->ld_drv_map[sc->map_id & 1]; 4423 num_lds = map->raidMap.ldCount; 4424 4425 dcmd = &cmd->frame->dcmd; 4426 size_sync_info = sizeof(MR_LD_TARGET_SYNC) * num_lds; 4427 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 4428 4429 target_map = (MR_LD_TARGET_SYNC *) sc->raidmap_mem[(sc->map_id - 1) & 1]; 4430 memset(target_map, 0, sc->max_map_sz); 4431 4432 map_phys_addr = sc->raidmap_phys_addr[(sc->map_id - 1) & 1]; 4433 4434 ld_sync = (MR_LD_TARGET_SYNC *) target_map; 4435 4436 for (i = 0; i < num_lds; i++, ld_sync++) { 4437 raid = MR_LdRaidGet(i, map); 4438 ld_sync->targetId = MR_GetLDTgtId(i, map); 4439 ld_sync->seqNum = raid->seqNum; 4440 } 4441 4442 dcmd->cmd = MFI_CMD_DCMD; 4443 dcmd->cmd_status = 0xFF; 4444 dcmd->sge_count = 1; 4445 dcmd->flags = htole16(MFI_FRAME_DIR_WRITE); 4446 dcmd->timeout = 0; 4447 dcmd->pad_0 = 0; 4448 dcmd->data_xfer_len = htole32(sc->current_map_sz); 4449 dcmd->mbox.b[0] = num_lds; 4450 dcmd->mbox.b[1] = MRSAS_DCMD_MBOX_PEND_FLAG; 4451 dcmd->opcode = htole32(MR_DCMD_LD_MAP_GET_INFO); 4452 dcmd->sgl.sge32[0].phys_addr = htole32(map_phys_addr & 0xFFFFFFFF); 4453 dcmd->sgl.sge32[0].length = htole32(sc->current_map_sz); 4454 4455 sc->map_update_cmd = cmd; 4456 if (mrsas_issue_dcmd(sc, cmd)) { 4457 device_printf(sc->mrsas_dev, 4458 "Fail to send sync map info command.\n"); 4459 return (1); 4460 } 4461 return (retcode); 4462 } 4463 4464 /* Input: dcmd.opcode - MR_DCMD_PD_GET_INFO 4465 * dcmd.mbox.s[0] - deviceId for this physical drive 4466 * dcmd.sge IN - ptr to returned MR_PD_INFO structure 4467 * Desc: Firmware return the physical drive info structure 4468 * 4469 */ 4470 static void 4471 mrsas_get_pd_info(struct mrsas_softc *sc, u_int16_t device_id) 4472 { 4473 int retcode; 4474 u_int8_t do_ocr = 1; 4475 struct mrsas_mfi_cmd *cmd; 4476 struct mrsas_dcmd_frame *dcmd; 4477 4478 cmd = mrsas_get_mfi_cmd(sc); 4479 4480 if (!cmd) { 4481 device_printf(sc->mrsas_dev, 4482 "Cannot alloc for get PD info cmd\n"); 4483 return; 4484 } 4485 dcmd = &cmd->frame->dcmd; 4486 4487 memset(sc->pd_info_mem, 0, sizeof(struct mrsas_pd_info)); 4488 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 4489 4490 dcmd->mbox.s[0] = htole16(device_id); 4491 dcmd->cmd = MFI_CMD_DCMD; 4492 dcmd->cmd_status = 0xFF; 4493 dcmd->sge_count = 1; 4494 dcmd->flags = MFI_FRAME_DIR_READ; 4495 dcmd->timeout = 0; 4496 dcmd->pad_0 = 0; 4497 dcmd->data_xfer_len = htole32(sizeof(struct mrsas_pd_info)); 4498 dcmd->opcode = htole32(MR_DCMD_PD_GET_INFO); 4499 dcmd->sgl.sge32[0].phys_addr = htole32((u_int32_t)sc->pd_info_phys_addr & 0xFFFFFFFF); 4500 dcmd->sgl.sge32[0].length = htole32(sizeof(struct mrsas_pd_info)); 4501 4502 if (!sc->mask_interrupts) 4503 retcode = mrsas_issue_blocked_cmd(sc, cmd); 4504 else 4505 retcode = mrsas_issue_polled(sc, cmd); 4506 4507 if (retcode == ETIMEDOUT) 4508 goto dcmd_timeout; 4509 4510 sc->target_list[device_id].interface_type = 4511 le16toh(sc->pd_info_mem->state.ddf.pdType.intf); 4512 4513 do_ocr = 0; 4514 4515 dcmd_timeout: 4516 4517 if (do_ocr) 4518 sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR; 4519 4520 if (!sc->mask_interrupts) 4521 mrsas_release_mfi_cmd(cmd); 4522 } 4523 4524 /* 4525 * mrsas_add_target: Add target ID of system PD/VD to driver's data structure. 4526 * sc: Adapter's soft state 4527 * target_id: Unique target id per controller(managed by driver) 4528 * for system PDs- target ID ranges from 0 to (MRSAS_MAX_PD - 1) 4529 * for VDs- target ID ranges from MRSAS_MAX_PD to MRSAS_MAX_TM_TARGETS 4530 * return: void 4531 * Descripton: This function will be called whenever system PD or VD is created. 4532 */ 4533 static void mrsas_add_target(struct mrsas_softc *sc, 4534 u_int16_t target_id) 4535 { 4536 sc->target_list[target_id].target_id = target_id; 4537 4538 device_printf(sc->mrsas_dev, 4539 "%s created target ID: 0x%x\n", 4540 (target_id < MRSAS_MAX_PD ? "System PD" : "VD"), 4541 (target_id < MRSAS_MAX_PD ? target_id : (target_id - MRSAS_MAX_PD))); 4542 /* 4543 * If interrupts are enabled, then only fire DCMD to get pd_info 4544 * for system PDs 4545 */ 4546 if (!sc->mask_interrupts && sc->pd_info_mem && 4547 (target_id < MRSAS_MAX_PD)) 4548 mrsas_get_pd_info(sc, target_id); 4549 4550 } 4551 4552 /* 4553 * mrsas_remove_target: Remove target ID of system PD/VD from driver's data structure. 4554 * sc: Adapter's soft state 4555 * target_id: Unique target id per controller(managed by driver) 4556 * for system PDs- target ID ranges from 0 to (MRSAS_MAX_PD - 1) 4557 * for VDs- target ID ranges from MRSAS_MAX_PD to MRSAS_MAX_TM_TARGETS 4558 * return: void 4559 * Descripton: This function will be called whenever system PD or VD is deleted 4560 */ 4561 static void mrsas_remove_target(struct mrsas_softc *sc, 4562 u_int16_t target_id) 4563 { 4564 sc->target_list[target_id].target_id = 0xffff; 4565 device_printf(sc->mrsas_dev, 4566 "%s deleted target ID: 0x%x\n", 4567 (target_id < MRSAS_MAX_PD ? "System PD" : "VD"), 4568 (target_id < MRSAS_MAX_PD ? target_id : (target_id - MRSAS_MAX_PD))); 4569 } 4570 4571 /* 4572 * mrsas_get_pd_list: Returns FW's PD list structure input: 4573 * Adapter soft state 4574 * 4575 * Issues an internal command (DCMD) to get the FW's controller PD list 4576 * structure. This information is mainly used to find out about system 4577 * supported by Firmware. 4578 */ 4579 static int 4580 mrsas_get_pd_list(struct mrsas_softc *sc) 4581 { 4582 int retcode = 0, pd_index = 0, pd_count = 0, pd_list_size; 4583 u_int8_t do_ocr = 1; 4584 struct mrsas_mfi_cmd *cmd; 4585 struct mrsas_dcmd_frame *dcmd; 4586 struct MR_PD_LIST *pd_list_mem; 4587 struct MR_PD_ADDRESS *pd_addr; 4588 bus_addr_t pd_list_phys_addr = 0; 4589 struct mrsas_tmp_dcmd *tcmd; 4590 u_int16_t dev_id; 4591 4592 cmd = mrsas_get_mfi_cmd(sc); 4593 if (!cmd) { 4594 device_printf(sc->mrsas_dev, 4595 "Cannot alloc for get PD list cmd\n"); 4596 return 1; 4597 } 4598 dcmd = &cmd->frame->dcmd; 4599 4600 tcmd = malloc(sizeof(struct mrsas_tmp_dcmd), M_MRSAS, M_NOWAIT); 4601 pd_list_size = MRSAS_MAX_PD * sizeof(struct MR_PD_LIST); 4602 if (mrsas_alloc_tmp_dcmd(sc, tcmd, pd_list_size) != SUCCESS) { 4603 device_printf(sc->mrsas_dev, 4604 "Cannot alloc dmamap for get PD list cmd\n"); 4605 mrsas_release_mfi_cmd(cmd); 4606 mrsas_free_tmp_dcmd(tcmd); 4607 free(tcmd, M_MRSAS); 4608 return (ENOMEM); 4609 } else { 4610 pd_list_mem = tcmd->tmp_dcmd_mem; 4611 pd_list_phys_addr = tcmd->tmp_dcmd_phys_addr; 4612 } 4613 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 4614 4615 dcmd->mbox.b[0] = MR_PD_QUERY_TYPE_EXPOSED_TO_HOST; 4616 dcmd->mbox.b[1] = 0; 4617 dcmd->cmd = MFI_CMD_DCMD; 4618 dcmd->cmd_status = 0xFF; 4619 dcmd->sge_count = 1; 4620 dcmd->flags = htole16(MFI_FRAME_DIR_READ); 4621 dcmd->timeout = 0; 4622 dcmd->pad_0 = 0; 4623 dcmd->data_xfer_len = htole32(MRSAS_MAX_PD * sizeof(struct MR_PD_LIST)); 4624 dcmd->opcode = htole32(MR_DCMD_PD_LIST_QUERY); 4625 dcmd->sgl.sge32[0].phys_addr = htole32(pd_list_phys_addr & 0xFFFFFFFF); 4626 dcmd->sgl.sge32[0].length = htole32(MRSAS_MAX_PD * sizeof(struct MR_PD_LIST)); 4627 4628 if (!sc->mask_interrupts) 4629 retcode = mrsas_issue_blocked_cmd(sc, cmd); 4630 else 4631 retcode = mrsas_issue_polled(sc, cmd); 4632 4633 if (retcode == ETIMEDOUT) 4634 goto dcmd_timeout; 4635 4636 /* Get the instance PD list */ 4637 pd_count = MRSAS_MAX_PD; 4638 pd_addr = pd_list_mem->addr; 4639 if (le32toh(pd_list_mem->count) < pd_count) { 4640 memset(sc->local_pd_list, 0, 4641 MRSAS_MAX_PD * sizeof(struct mrsas_pd_list)); 4642 for (pd_index = 0; pd_index < le32toh(pd_list_mem->count); pd_index++) { 4643 dev_id = le16toh(pd_addr->deviceId); 4644 sc->local_pd_list[dev_id].tid = dev_id; 4645 sc->local_pd_list[dev_id].driveType = 4646 le16toh(pd_addr->scsiDevType); 4647 sc->local_pd_list[dev_id].driveState = 4648 MR_PD_STATE_SYSTEM; 4649 if (sc->target_list[dev_id].target_id == 0xffff) 4650 mrsas_add_target(sc, dev_id); 4651 pd_addr++; 4652 } 4653 for (pd_index = 0; pd_index < MRSAS_MAX_PD; pd_index++) { 4654 if ((sc->local_pd_list[pd_index].driveState != 4655 MR_PD_STATE_SYSTEM) && 4656 (sc->target_list[pd_index].target_id != 4657 0xffff)) { 4658 mrsas_remove_target(sc, pd_index); 4659 } 4660 } 4661 /* 4662 * Use mutext/spinlock if pd_list component size increase more than 4663 * 32 bit. 4664 */ 4665 memcpy(sc->pd_list, sc->local_pd_list, sizeof(sc->local_pd_list)); 4666 do_ocr = 0; 4667 } 4668 dcmd_timeout: 4669 mrsas_free_tmp_dcmd(tcmd); 4670 free(tcmd, M_MRSAS); 4671 4672 if (do_ocr) 4673 sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR; 4674 4675 if (!sc->mask_interrupts) 4676 mrsas_release_mfi_cmd(cmd); 4677 4678 return (retcode); 4679 } 4680 4681 /* 4682 * mrsas_get_ld_list: Returns FW's LD list structure input: 4683 * Adapter soft state 4684 * 4685 * Issues an internal command (DCMD) to get the FW's controller PD list 4686 * structure. This information is mainly used to find out about supported by 4687 * the FW. 4688 */ 4689 static int 4690 mrsas_get_ld_list(struct mrsas_softc *sc) 4691 { 4692 int ld_list_size, retcode = 0, ld_index = 0, ids = 0, drv_tgt_id; 4693 u_int8_t do_ocr = 1; 4694 struct mrsas_mfi_cmd *cmd; 4695 struct mrsas_dcmd_frame *dcmd; 4696 struct MR_LD_LIST *ld_list_mem; 4697 bus_addr_t ld_list_phys_addr = 0; 4698 struct mrsas_tmp_dcmd *tcmd; 4699 4700 cmd = mrsas_get_mfi_cmd(sc); 4701 if (!cmd) { 4702 device_printf(sc->mrsas_dev, 4703 "Cannot alloc for get LD list cmd\n"); 4704 return 1; 4705 } 4706 dcmd = &cmd->frame->dcmd; 4707 4708 tcmd = malloc(sizeof(struct mrsas_tmp_dcmd), M_MRSAS, M_NOWAIT); 4709 ld_list_size = sizeof(struct MR_LD_LIST); 4710 if (mrsas_alloc_tmp_dcmd(sc, tcmd, ld_list_size) != SUCCESS) { 4711 device_printf(sc->mrsas_dev, 4712 "Cannot alloc dmamap for get LD list cmd\n"); 4713 mrsas_release_mfi_cmd(cmd); 4714 mrsas_free_tmp_dcmd(tcmd); 4715 free(tcmd, M_MRSAS); 4716 return (ENOMEM); 4717 } else { 4718 ld_list_mem = tcmd->tmp_dcmd_mem; 4719 ld_list_phys_addr = tcmd->tmp_dcmd_phys_addr; 4720 } 4721 memset(dcmd->mbox.b, 0, MFI_MBOX_SIZE); 4722 4723 if (sc->max256vdSupport) 4724 dcmd->mbox.b[0] = 1; 4725 4726 dcmd->cmd = MFI_CMD_DCMD; 4727 dcmd->cmd_status = 0xFF; 4728 dcmd->sge_count = 1; 4729 dcmd->flags = MFI_FRAME_DIR_READ; 4730 dcmd->timeout = 0; 4731 dcmd->data_xfer_len = htole32(sizeof(struct MR_LD_LIST)); 4732 dcmd->opcode = htole32(MR_DCMD_LD_GET_LIST); 4733 dcmd->sgl.sge32[0].phys_addr = htole32(ld_list_phys_addr); 4734 dcmd->sgl.sge32[0].length = htole32(sizeof(struct MR_LD_LIST)); 4735 dcmd->pad_0 = 0; 4736 4737 if (!sc->mask_interrupts) 4738 retcode = mrsas_issue_blocked_cmd(sc, cmd); 4739 else 4740 retcode = mrsas_issue_polled(sc, cmd); 4741 4742 if (retcode == ETIMEDOUT) 4743 goto dcmd_timeout; 4744 4745 #if VD_EXT_DEBUG 4746 printf("Number of LDs %d\n", ld_list_mem->ldCount); 4747 #endif 4748 4749 /* Get the instance LD list */ 4750 if (le32toh(ld_list_mem->ldCount) <= sc->fw_supported_vd_count) { 4751 sc->CurLdCount = le32toh(ld_list_mem->ldCount); 4752 memset(sc->ld_ids, 0xff, MAX_LOGICAL_DRIVES_EXT); 4753 for (ld_index = 0; ld_index < le32toh(ld_list_mem->ldCount); ld_index++) { 4754 ids = ld_list_mem->ldList[ld_index].ref.ld_context.targetId; 4755 drv_tgt_id = ids + MRSAS_MAX_PD; 4756 if (ld_list_mem->ldList[ld_index].state != 0) { 4757 sc->ld_ids[ids] = ld_list_mem->ldList[ld_index].ref.ld_context.targetId; 4758 if (sc->target_list[drv_tgt_id].target_id == 4759 0xffff) 4760 mrsas_add_target(sc, drv_tgt_id); 4761 } else { 4762 if (sc->target_list[drv_tgt_id].target_id != 4763 0xffff) 4764 mrsas_remove_target(sc, 4765 drv_tgt_id); 4766 } 4767 } 4768 4769 do_ocr = 0; 4770 } 4771 dcmd_timeout: 4772 mrsas_free_tmp_dcmd(tcmd); 4773 free(tcmd, M_MRSAS); 4774 4775 if (do_ocr) 4776 sc->do_timedout_reset = MFI_DCMD_TIMEOUT_OCR; 4777 if (!sc->mask_interrupts) 4778 mrsas_release_mfi_cmd(cmd); 4779 4780 return (retcode); 4781 } 4782 4783 /* 4784 * mrsas_alloc_tmp_dcmd: Allocates memory for temporary command input: 4785 * Adapter soft state Temp command Size of alloction 4786 * 4787 * Allocates DMAable memory for a temporary internal command. The allocated 4788 * memory is initialized to all zeros upon successful loading of the dma 4789 * mapped memory. 4790 */ 4791 int 4792 mrsas_alloc_tmp_dcmd(struct mrsas_softc *sc, 4793 struct mrsas_tmp_dcmd *tcmd, int size) 4794 { 4795 if (bus_dma_tag_create(sc->mrsas_parent_tag, 4796 1, 0, 4797 BUS_SPACE_MAXADDR_32BIT, 4798 BUS_SPACE_MAXADDR, 4799 NULL, NULL, 4800 size, 4801 1, 4802 size, 4803 BUS_DMA_ALLOCNOW, 4804 NULL, NULL, 4805 &tcmd->tmp_dcmd_tag)) { 4806 device_printf(sc->mrsas_dev, "Cannot allocate tmp dcmd tag\n"); 4807 return (ENOMEM); 4808 } 4809 if (bus_dmamem_alloc(tcmd->tmp_dcmd_tag, (void **)&tcmd->tmp_dcmd_mem, 4810 BUS_DMA_NOWAIT, &tcmd->tmp_dcmd_dmamap)) { 4811 device_printf(sc->mrsas_dev, "Cannot allocate tmp dcmd mem\n"); 4812 return (ENOMEM); 4813 } 4814 if (bus_dmamap_load(tcmd->tmp_dcmd_tag, tcmd->tmp_dcmd_dmamap, 4815 tcmd->tmp_dcmd_mem, size, mrsas_addr_cb, 4816 &tcmd->tmp_dcmd_phys_addr, BUS_DMA_NOWAIT)) { 4817 device_printf(sc->mrsas_dev, "Cannot load tmp dcmd mem\n"); 4818 return (ENOMEM); 4819 } 4820 memset(tcmd->tmp_dcmd_mem, 0, size); 4821 return (0); 4822 } 4823 4824 /* 4825 * mrsas_free_tmp_dcmd: Free memory for temporary command input: 4826 * temporary dcmd pointer 4827 * 4828 * Deallocates memory of the temporary command for use in the construction of 4829 * the internal DCMD. 4830 */ 4831 void 4832 mrsas_free_tmp_dcmd(struct mrsas_tmp_dcmd *tmp) 4833 { 4834 if (tmp->tmp_dcmd_phys_addr) 4835 bus_dmamap_unload(tmp->tmp_dcmd_tag, tmp->tmp_dcmd_dmamap); 4836 if (tmp->tmp_dcmd_mem != NULL) 4837 bus_dmamem_free(tmp->tmp_dcmd_tag, tmp->tmp_dcmd_mem, tmp->tmp_dcmd_dmamap); 4838 if (tmp->tmp_dcmd_tag != NULL) 4839 bus_dma_tag_destroy(tmp->tmp_dcmd_tag); 4840 } 4841 4842 /* 4843 * mrsas_issue_blocked_abort_cmd: Aborts previously issued cmd input: 4844 * Adapter soft state Previously issued cmd to be aborted 4845 * 4846 * This function is used to abort previously issued commands, such as AEN and 4847 * RAID map sync map commands. The abort command is sent as a DCMD internal 4848 * command and subsequently the driver will wait for a return status. The 4849 * max wait time is MRSAS_INTERNAL_CMD_WAIT_TIME seconds. 4850 */ 4851 static int 4852 mrsas_issue_blocked_abort_cmd(struct mrsas_softc *sc, 4853 struct mrsas_mfi_cmd *cmd_to_abort) 4854 { 4855 struct mrsas_mfi_cmd *cmd; 4856 struct mrsas_abort_frame *abort_fr; 4857 u_int8_t retcode = 0; 4858 unsigned long total_time = 0; 4859 u_int8_t max_wait = MRSAS_INTERNAL_CMD_WAIT_TIME; 4860 4861 cmd = mrsas_get_mfi_cmd(sc); 4862 if (!cmd) { 4863 device_printf(sc->mrsas_dev, "Cannot alloc for abort cmd\n"); 4864 return (1); 4865 } 4866 abort_fr = &cmd->frame->abort; 4867 4868 /* Prepare and issue the abort frame */ 4869 abort_fr->cmd = MFI_CMD_ABORT; 4870 abort_fr->cmd_status = 0xFF; 4871 abort_fr->flags = 0; 4872 abort_fr->abort_context = cmd_to_abort->index; 4873 abort_fr->abort_mfi_phys_addr_lo = cmd_to_abort->frame_phys_addr; 4874 abort_fr->abort_mfi_phys_addr_hi = 0; 4875 4876 cmd->sync_cmd = 1; 4877 cmd->cmd_status = 0xFF; 4878 4879 if (mrsas_issue_dcmd(sc, cmd)) { 4880 device_printf(sc->mrsas_dev, "Fail to send abort command.\n"); 4881 return (1); 4882 } 4883 /* Wait for this cmd to complete */ 4884 sc->chan = (void *)&cmd; 4885 while (1) { 4886 if (cmd->cmd_status == 0xFF) { 4887 tsleep((void *)&sc->chan, 0, "mrsas_sleep", hz); 4888 } else 4889 break; 4890 total_time++; 4891 if (total_time >= max_wait) { 4892 device_printf(sc->mrsas_dev, "Abort cmd timed out after %d sec.\n", max_wait); 4893 retcode = 1; 4894 break; 4895 } 4896 } 4897 4898 cmd->sync_cmd = 0; 4899 mrsas_release_mfi_cmd(cmd); 4900 return (retcode); 4901 } 4902 4903 /* 4904 * mrsas_complete_abort: Completes aborting a command input: 4905 * Adapter soft state Cmd that was issued to abort another cmd 4906 * 4907 * The mrsas_issue_blocked_abort_cmd() function waits for the command status to 4908 * change after sending the command. This function is called from 4909 * mrsas_complete_mptmfi_passthru() to wake up the sleep thread associated. 4910 */ 4911 void 4912 mrsas_complete_abort(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 4913 { 4914 if (cmd->sync_cmd) { 4915 cmd->sync_cmd = 0; 4916 cmd->cmd_status = 0; 4917 sc->chan = (void *)&cmd; 4918 wakeup_one((void *)&sc->chan); 4919 } 4920 return; 4921 } 4922 4923 /* 4924 * mrsas_aen_handler: AEN processing callback function from thread context 4925 * input: Adapter soft state 4926 * 4927 * Asynchronous event handler 4928 */ 4929 void 4930 mrsas_aen_handler(struct mrsas_softc *sc) 4931 { 4932 union mrsas_evt_class_locale class_locale; 4933 int doscan = 0; 4934 u_int32_t seq_num; 4935 int error, fail_aen = 0; 4936 4937 if (sc == NULL) { 4938 printf("invalid instance!\n"); 4939 return; 4940 } 4941 if (sc->remove_in_progress || sc->reset_in_progress) { 4942 device_printf(sc->mrsas_dev, "Returning from %s, line no %d\n", 4943 __func__, __LINE__); 4944 return; 4945 } 4946 if (sc->evt_detail_mem) { 4947 switch (sc->evt_detail_mem->code) { 4948 case MR_EVT_PD_INSERTED: 4949 fail_aen = mrsas_get_pd_list(sc); 4950 if (!fail_aen) 4951 mrsas_bus_scan_sim(sc, sc->sim_1); 4952 else 4953 goto skip_register_aen; 4954 break; 4955 case MR_EVT_PD_REMOVED: 4956 fail_aen = mrsas_get_pd_list(sc); 4957 if (!fail_aen) 4958 mrsas_bus_scan_sim(sc, sc->sim_1); 4959 else 4960 goto skip_register_aen; 4961 break; 4962 case MR_EVT_LD_OFFLINE: 4963 case MR_EVT_CFG_CLEARED: 4964 case MR_EVT_LD_DELETED: 4965 mrsas_bus_scan_sim(sc, sc->sim_0); 4966 break; 4967 case MR_EVT_LD_CREATED: 4968 fail_aen = mrsas_get_ld_list(sc); 4969 if (!fail_aen) 4970 mrsas_bus_scan_sim(sc, sc->sim_0); 4971 else 4972 goto skip_register_aen; 4973 break; 4974 case MR_EVT_CTRL_HOST_BUS_SCAN_REQUESTED: 4975 case MR_EVT_FOREIGN_CFG_IMPORTED: 4976 case MR_EVT_LD_STATE_CHANGE: 4977 doscan = 1; 4978 break; 4979 case MR_EVT_CTRL_PROP_CHANGED: 4980 fail_aen = mrsas_get_ctrl_info(sc); 4981 if (fail_aen) 4982 goto skip_register_aen; 4983 break; 4984 default: 4985 break; 4986 } 4987 } else { 4988 device_printf(sc->mrsas_dev, "invalid evt_detail\n"); 4989 return; 4990 } 4991 if (doscan) { 4992 fail_aen = mrsas_get_pd_list(sc); 4993 if (!fail_aen) { 4994 mrsas_dprint(sc, MRSAS_AEN, "scanning ...sim 1\n"); 4995 mrsas_bus_scan_sim(sc, sc->sim_1); 4996 } else 4997 goto skip_register_aen; 4998 4999 fail_aen = mrsas_get_ld_list(sc); 5000 if (!fail_aen) { 5001 mrsas_dprint(sc, MRSAS_AEN, "scanning ...sim 0\n"); 5002 mrsas_bus_scan_sim(sc, sc->sim_0); 5003 } else 5004 goto skip_register_aen; 5005 } 5006 seq_num = sc->evt_detail_mem->seq_num + 1; 5007 5008 /* Register AEN with FW for latest sequence number plus 1 */ 5009 class_locale.members.reserved = 0; 5010 class_locale.members.locale = MR_EVT_LOCALE_ALL; 5011 class_locale.members.class = MR_EVT_CLASS_DEBUG; 5012 5013 if (sc->aen_cmd != NULL) 5014 return; 5015 5016 mtx_lock(&sc->aen_lock); 5017 error = mrsas_register_aen(sc, seq_num, 5018 class_locale.word); 5019 mtx_unlock(&sc->aen_lock); 5020 5021 if (error) 5022 device_printf(sc->mrsas_dev, "register aen failed error %x\n", error); 5023 5024 skip_register_aen: 5025 return; 5026 5027 } 5028 5029 /* 5030 * mrsas_complete_aen: Completes AEN command 5031 * input: Adapter soft state 5032 * Cmd that was issued to abort another cmd 5033 * 5034 * This function will be called from ISR and will continue event processing from 5035 * thread context by enqueuing task in ev_tq (callback function 5036 * "mrsas_aen_handler"). 5037 */ 5038 void 5039 mrsas_complete_aen(struct mrsas_softc *sc, struct mrsas_mfi_cmd *cmd) 5040 { 5041 /* 5042 * Don't signal app if it is just an aborted previously registered 5043 * aen 5044 */ 5045 if ((!cmd->abort_aen) && (sc->remove_in_progress == 0)) { 5046 sc->mrsas_aen_triggered = 1; 5047 mtx_lock(&sc->aen_lock); 5048 if (sc->mrsas_poll_waiting) { 5049 sc->mrsas_poll_waiting = 0; 5050 selwakeup(&sc->mrsas_select); 5051 } 5052 mtx_unlock(&sc->aen_lock); 5053 } else 5054 cmd->abort_aen = 0; 5055 5056 sc->aen_cmd = NULL; 5057 mrsas_release_mfi_cmd(cmd); 5058 5059 taskqueue_enqueue(sc->ev_tq, &sc->ev_task); 5060 5061 return; 5062 } 5063 5064 static device_method_t mrsas_methods[] = { 5065 DEVMETHOD(device_probe, mrsas_probe), 5066 DEVMETHOD(device_attach, mrsas_attach), 5067 DEVMETHOD(device_detach, mrsas_detach), 5068 DEVMETHOD(device_shutdown, mrsas_shutdown), 5069 DEVMETHOD(device_suspend, mrsas_suspend), 5070 DEVMETHOD(device_resume, mrsas_resume), 5071 DEVMETHOD(bus_print_child, bus_generic_print_child), 5072 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 5073 {0, 0} 5074 }; 5075 5076 static driver_t mrsas_driver = { 5077 "mrsas", 5078 mrsas_methods, 5079 sizeof(struct mrsas_softc) 5080 }; 5081 5082 static devclass_t mrsas_devclass; 5083 5084 DRIVER_MODULE(mrsas, pci, mrsas_driver, mrsas_devclass, 0, 0); 5085 MODULE_DEPEND(mrsas, cam, 1, 1, 1); 5086