1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2000-2005, LSI Logic Corporation and its contributors. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * substantially similar to the "NO WARRANTY" disclaimer below 13 * ("Disclaimer") and any redistribution must be conditioned upon including 14 * a substantially similar Disclaimer requirement for further binary 15 * redistribution. 16 * 3. Neither the name of the LSI Logic Corporation nor the names of its 17 * contributors may be used to endorse or promote products derived from 18 * this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT 30 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * Name: mpi_init.h 33 * Title: MPI initiator mode messages and structures 34 * Creation Date: June 8, 2000 35 * 36 * mpi_init.h Version: 01.05.09 37 * 38 * Version History 39 * --------------- 40 * 41 * Date Version Description 42 * -------- -------- ------------------------------------------------------ 43 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 44 * 05-24-00 00.10.02 Added SenseBufferLength to _MSG_SCSI_IO_REPLY. 45 * 06-06-00 01.00.01 Update version number for 1.0 release. 46 * 06-08-00 01.00.02 Added MPI_SCSI_RSP_INFO_ definitions. 47 * 11-02-00 01.01.01 Original release for post 1.0 work. 48 * 12-04-00 01.01.02 Added MPI_SCSIIO_CONTROL_NO_DISCONNECT. 49 * 02-20-01 01.01.03 Started using MPI_POINTER. 50 * 03-27-01 01.01.04 Added structure offset comments. 51 * 04-10-01 01.01.05 Added new MsgFlag for MSG_SCSI_TASK_MGMT. 52 * 08-08-01 01.02.01 Original release for v1.2 work. 53 * 08-29-01 01.02.02 Added MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET. 54 * Added MPI_SCSI_STATE_QUEUE_TAG_REJECTED for 55 * MSG_SCSI_IO_REPLY. 56 * 09-28-01 01.02.03 Added structures and defines for SCSI Enclosure 57 * Processor messages. 58 * 10-04-01 01.02.04 Added defines for SEP request Action field. 59 * 05-31-02 01.02.05 Added MPI_SCSIIO_MSGFLGS_CMD_DETERMINES_DATA_DIR define 60 * for SCSI IO requests. 61 * 11-15-02 01.02.06 Added special extended SCSI Status defines for FCP. 62 * 06-26-03 01.02.07 Added MPI_SCSI_STATUS_FCPEXT_UNASSIGNED define. 63 * 05-11-04 01.03.01 Original release for MPI v1.3. 64 * 08-19-04 01.05.01 Added MsgFlags defines for EEDP to SCSI IO request. 65 * Added new word to MSG_SCSI_IO_REPLY to add TaskTag field 66 * and a reserved U16. 67 * Added new MSG_SCSI_IO32_REQUEST structure. 68 * Added a TaskType of Clear Task Set to SCSI 69 * Task Management request. 70 * 12-07-04 01.05.02 Added support for Task Management Query Task. 71 * 01-15-05 01.05.03 Modified SCSI Enclosure Processor Request to support 72 * WWID addressing. 73 * 03-11-05 01.05.04 Removed EEDP flags from SCSI IO Request. 74 * Removed SCSI IO 32 Request. 75 * Modified SCSI Enclosure Processor Request and Reply to 76 * support Enclosure/Slot addressing rather than WWID 77 * addressing. 78 * 06-24-05 01.05.05 Added SCSI IO 32 structures and defines. 79 * Added four new defines for SEP SlotStatus. 80 * 08-03-05 01.05.06 Fixed some MPI_SCSIIO32_MSGFLGS_ defines to make them 81 * unique in the first 32 characters. 82 * 03-27-06 01.05.07 Added Task Management type of Clear ACA. 83 * 10-11-06 01.05.08 Shortened define for Task Management type of Clear ACA. 84 * 02-28-07 01.05.09 Defined two new MsgFlags bits for SCSI Task Management 85 * Request: Do Not Send Task IU and Soft Reset Option. 86 * -------------------------------------------------------------------------- 87 */ 88 89 #ifndef MPI_INIT_H 90 #define MPI_INIT_H 91 92 93 /***************************************************************************** 94 * 95 * S C S I I n i t i a t o r M e s s a g e s 96 * 97 *****************************************************************************/ 98 99 /****************************************************************************/ 100 /* SCSI IO messages and associated structures */ 101 /****************************************************************************/ 102 103 typedef struct _MSG_SCSI_IO_REQUEST 104 { 105 U8 TargetID; /* 00h */ 106 U8 Bus; /* 01h */ 107 U8 ChainOffset; /* 02h */ 108 U8 Function; /* 03h */ 109 U8 CDBLength; /* 04h */ 110 U8 SenseBufferLength; /* 05h */ 111 U8 Reserved; /* 06h */ 112 U8 MsgFlags; /* 07h */ 113 U32 MsgContext; /* 08h */ 114 U8 LUN[8]; /* 0Ch */ 115 U32 Control; /* 14h */ 116 U8 CDB[16]; /* 18h */ 117 U32 DataLength; /* 28h */ 118 U32 SenseBufferLowAddr; /* 2Ch */ 119 SGE_IO_UNION SGL; /* 30h */ 120 } MSG_SCSI_IO_REQUEST, MPI_POINTER PTR_MSG_SCSI_IO_REQUEST, 121 SCSIIORequest_t, MPI_POINTER pSCSIIORequest_t; 122 123 124 /* SCSI IO MsgFlags bits */ 125 126 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH (0x01) 127 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_32 (0x00) 128 #define MPI_SCSIIO_MSGFLGS_SENSE_WIDTH_64 (0x01) 129 130 #define MPI_SCSIIO_MSGFLGS_SENSE_LOCATION (0x02) 131 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_HOST (0x00) 132 #define MPI_SCSIIO_MSGFLGS_SENSE_LOC_IOC (0x02) 133 134 #define MPI_SCSIIO_MSGFLGS_CMD_DETERMINES_DATA_DIR (0x04) 135 136 /* SCSI IO LUN fields */ 137 138 #define MPI_SCSIIO_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 139 #define MPI_SCSIIO_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 140 #define MPI_SCSIIO_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 141 #define MPI_SCSIIO_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 142 #define MPI_SCSIIO_LUN_LEVEL_1_WORD (0xFF00) 143 #define MPI_SCSIIO_LUN_LEVEL_1_DWORD (0x0000FF00) 144 145 /* SCSI IO Control bits */ 146 147 #define MPI_SCSIIO_CONTROL_DATADIRECTION_MASK (0x03000000) 148 #define MPI_SCSIIO_CONTROL_NODATATRANSFER (0x00000000) 149 #define MPI_SCSIIO_CONTROL_WRITE (0x01000000) 150 #define MPI_SCSIIO_CONTROL_READ (0x02000000) 151 152 #define MPI_SCSIIO_CONTROL_ADDCDBLEN_MASK (0x3C000000) 153 #define MPI_SCSIIO_CONTROL_ADDCDBLEN_SHIFT (26) 154 155 #define MPI_SCSIIO_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 156 #define MPI_SCSIIO_CONTROL_SIMPLEQ (0x00000000) 157 #define MPI_SCSIIO_CONTROL_HEADOFQ (0x00000100) 158 #define MPI_SCSIIO_CONTROL_ORDEREDQ (0x00000200) 159 #define MPI_SCSIIO_CONTROL_ACAQ (0x00000400) 160 #define MPI_SCSIIO_CONTROL_UNTAGGED (0x00000500) 161 #define MPI_SCSIIO_CONTROL_NO_DISCONNECT (0x00000700) 162 163 #define MPI_SCSIIO_CONTROL_TASKMANAGE_MASK (0x00FF0000) 164 #define MPI_SCSIIO_CONTROL_OBSOLETE (0x00800000) 165 #define MPI_SCSIIO_CONTROL_CLEAR_ACA_RSV (0x00400000) 166 #define MPI_SCSIIO_CONTROL_TARGET_RESET (0x00200000) 167 #define MPI_SCSIIO_CONTROL_LUN_RESET_RSV (0x00100000) 168 #define MPI_SCSIIO_CONTROL_RESERVED (0x00080000) 169 #define MPI_SCSIIO_CONTROL_CLR_TASK_SET_RSV (0x00040000) 170 #define MPI_SCSIIO_CONTROL_ABORT_TASK_SET (0x00020000) 171 #define MPI_SCSIIO_CONTROL_RESERVED2 (0x00010000) 172 173 174 /* SCSI IO reply structure */ 175 typedef struct _MSG_SCSI_IO_REPLY 176 { 177 U8 TargetID; /* 00h */ 178 U8 Bus; /* 01h */ 179 U8 MsgLength; /* 02h */ 180 U8 Function; /* 03h */ 181 U8 CDBLength; /* 04h */ 182 U8 SenseBufferLength; /* 05h */ 183 U8 Reserved; /* 06h */ 184 U8 MsgFlags; /* 07h */ 185 U32 MsgContext; /* 08h */ 186 U8 SCSIStatus; /* 0Ch */ 187 U8 SCSIState; /* 0Dh */ 188 U16 IOCStatus; /* 0Eh */ 189 U32 IOCLogInfo; /* 10h */ 190 U32 TransferCount; /* 14h */ 191 U32 SenseCount; /* 18h */ 192 U32 ResponseInfo; /* 1Ch */ 193 U16 TaskTag; /* 20h */ 194 U16 Reserved1; /* 22h */ 195 } MSG_SCSI_IO_REPLY, MPI_POINTER PTR_MSG_SCSI_IO_REPLY, 196 SCSIIOReply_t, MPI_POINTER pSCSIIOReply_t; 197 198 199 /* SCSI IO Reply SCSIStatus values (SAM-2 status codes) */ 200 201 #define MPI_SCSI_STATUS_SUCCESS (0x00) 202 #define MPI_SCSI_STATUS_CHECK_CONDITION (0x02) 203 #define MPI_SCSI_STATUS_CONDITION_MET (0x04) 204 #define MPI_SCSI_STATUS_BUSY (0x08) 205 #define MPI_SCSI_STATUS_INTERMEDIATE (0x10) 206 #define MPI_SCSI_STATUS_INTERMEDIATE_CONDMET (0x14) 207 #define MPI_SCSI_STATUS_RESERVATION_CONFLICT (0x18) 208 #define MPI_SCSI_STATUS_COMMAND_TERMINATED (0x22) 209 #define MPI_SCSI_STATUS_TASK_SET_FULL (0x28) 210 #define MPI_SCSI_STATUS_ACA_ACTIVE (0x30) 211 212 #define MPI_SCSI_STATUS_FCPEXT_DEVICE_LOGGED_OUT (0x80) 213 #define MPI_SCSI_STATUS_FCPEXT_NO_LINK (0x81) 214 #define MPI_SCSI_STATUS_FCPEXT_UNASSIGNED (0x82) 215 216 217 /* SCSI IO Reply SCSIState values */ 218 219 #define MPI_SCSI_STATE_AUTOSENSE_VALID (0x01) 220 #define MPI_SCSI_STATE_AUTOSENSE_FAILED (0x02) 221 #define MPI_SCSI_STATE_NO_SCSI_STATUS (0x04) 222 #define MPI_SCSI_STATE_TERMINATED (0x08) 223 #define MPI_SCSI_STATE_RESPONSE_INFO_VALID (0x10) 224 #define MPI_SCSI_STATE_QUEUE_TAG_REJECTED (0x20) 225 226 /* SCSI IO Reply ResponseInfo values */ 227 /* (FCP-1 RSP_CODE values and SPI-3 Packetized Failure codes) */ 228 229 #define MPI_SCSI_RSP_INFO_FUNCTION_COMPLETE (0x00000000) 230 #define MPI_SCSI_RSP_INFO_FCP_BURST_LEN_ERROR (0x01000000) 231 #define MPI_SCSI_RSP_INFO_CMND_FIELDS_INVALID (0x02000000) 232 #define MPI_SCSI_RSP_INFO_FCP_DATA_RO_ERROR (0x03000000) 233 #define MPI_SCSI_RSP_INFO_TASK_MGMT_UNSUPPORTED (0x04000000) 234 #define MPI_SCSI_RSP_INFO_TASK_MGMT_FAILED (0x05000000) 235 #define MPI_SCSI_RSP_INFO_SPI_LQ_INVALID_TYPE (0x06000000) 236 237 #define MPI_SCSI_TASKTAG_UNKNOWN (0xFFFF) 238 239 240 /****************************************************************************/ 241 /* SCSI IO 32 messages and associated structures */ 242 /****************************************************************************/ 243 244 typedef struct 245 { 246 U8 CDB[20]; /* 00h */ 247 U32 PrimaryReferenceTag; /* 14h */ 248 U16 PrimaryApplicationTag; /* 18h */ 249 U16 PrimaryApplicationTagMask; /* 1Ah */ 250 U32 TransferLength; /* 1Ch */ 251 } MPI_SCSI_IO32_CDB_EEDP32, MPI_POINTER PTR_MPI_SCSI_IO32_CDB_EEDP32, 252 MpiScsiIo32CdbEedp32_t, MPI_POINTER pMpiScsiIo32CdbEedp32_t; 253 254 typedef struct 255 { 256 U8 CDB[16]; /* 00h */ 257 U32 DataLength; /* 10h */ 258 U32 PrimaryReferenceTag; /* 14h */ 259 U16 PrimaryApplicationTag; /* 18h */ 260 U16 PrimaryApplicationTagMask; /* 1Ah */ 261 U32 TransferLength; /* 1Ch */ 262 } MPI_SCSI_IO32_CDB_EEDP16, MPI_POINTER PTR_MPI_SCSI_IO32_CDB_EEDP16, 263 MpiScsiIo32CdbEedp16_t, MPI_POINTER pMpiScsiIo32CdbEedp16_t; 264 265 typedef union 266 { 267 U8 CDB32[32]; 268 MPI_SCSI_IO32_CDB_EEDP32 EEDP32; 269 MPI_SCSI_IO32_CDB_EEDP16 EEDP16; 270 SGE_SIMPLE_UNION SGE; 271 } MPI_SCSI_IO32_CDB_UNION, MPI_POINTER PTR_MPI_SCSI_IO32_CDB_UNION, 272 MpiScsiIo32Cdb_t, MPI_POINTER pMpiScsiIo32Cdb_t; 273 274 typedef struct 275 { 276 U8 TargetID; /* 00h */ 277 U8 Bus; /* 01h */ 278 U16 Reserved1; /* 02h */ 279 U32 Reserved2; /* 04h */ 280 } MPI_SCSI_IO32_BUS_TARGET_ID_FORM, MPI_POINTER PTR_MPI_SCSI_IO32_BUS_TARGET_ID_FORM, 281 MpiScsiIo32BusTargetIdForm_t, MPI_POINTER pMpiScsiIo32BusTargetIdForm_t; 282 283 typedef union 284 { 285 MPI_SCSI_IO32_BUS_TARGET_ID_FORM SCSIID; 286 U64 WWID; 287 } MPI_SCSI_IO32_ADDRESS, MPI_POINTER PTR_MPI_SCSI_IO32_ADDRESS, 288 MpiScsiIo32Address_t, MPI_POINTER pMpiScsiIo32Address_t; 289 290 typedef struct _MSG_SCSI_IO32_REQUEST 291 { 292 U8 Port; /* 00h */ 293 U8 Reserved1; /* 01h */ 294 U8 ChainOffset; /* 02h */ 295 U8 Function; /* 03h */ 296 U8 CDBLength; /* 04h */ 297 U8 SenseBufferLength; /* 05h */ 298 U8 Flags; /* 06h */ 299 U8 MsgFlags; /* 07h */ 300 U32 MsgContext; /* 08h */ 301 U8 LUN[8]; /* 0Ch */ 302 U32 Control; /* 14h */ 303 MPI_SCSI_IO32_CDB_UNION CDB; /* 18h */ 304 U32 DataLength; /* 38h */ 305 U32 BidirectionalDataLength; /* 3Ch */ 306 U32 SecondaryReferenceTag; /* 40h */ 307 U16 SecondaryApplicationTag; /* 44h */ 308 U16 Reserved2; /* 46h */ 309 U16 EEDPFlags; /* 48h */ 310 U16 ApplicationTagTranslationMask; /* 4Ah */ 311 U32 EEDPBlockSize; /* 4Ch */ 312 MPI_SCSI_IO32_ADDRESS DeviceAddress; /* 50h */ 313 U8 SGLOffset0; /* 58h */ 314 U8 SGLOffset1; /* 59h */ 315 U8 SGLOffset2; /* 5Ah */ 316 U8 SGLOffset3; /* 5Bh */ 317 U32 Reserved3; /* 5Ch */ 318 U32 Reserved4; /* 60h */ 319 U32 SenseBufferLowAddr; /* 64h */ 320 SGE_IO_UNION SGL; /* 68h */ 321 } MSG_SCSI_IO32_REQUEST, MPI_POINTER PTR_MSG_SCSI_IO32_REQUEST, 322 SCSIIO32Request_t, MPI_POINTER pSCSIIO32Request_t; 323 324 /* SCSI IO 32 MsgFlags bits */ 325 #define MPI_SCSIIO32_MSGFLGS_SENSE_WIDTH (0x01) 326 #define MPI_SCSIIO32_MSGFLGS_32_SENSE_WIDTH (0x00) 327 #define MPI_SCSIIO32_MSGFLGS_64_SENSE_WIDTH (0x01) 328 329 #define MPI_SCSIIO32_MSGFLGS_SENSE_LOCATION (0x02) 330 #define MPI_SCSIIO32_MSGFLGS_SENSE_LOC_HOST (0x00) 331 #define MPI_SCSIIO32_MSGFLGS_SENSE_LOC_IOC (0x02) 332 333 #define MPI_SCSIIO32_MSGFLGS_CMD_DETERMINES_DATA_DIR (0x04) 334 #define MPI_SCSIIO32_MSGFLGS_SGL_OFFSETS_CHAINS (0x08) 335 #define MPI_SCSIIO32_MSGFLGS_MULTICAST (0x10) 336 #define MPI_SCSIIO32_MSGFLGS_BIDIRECTIONAL (0x20) 337 #define MPI_SCSIIO32_MSGFLGS_LARGE_CDB (0x40) 338 339 /* SCSI IO 32 Flags bits */ 340 #define MPI_SCSIIO32_FLAGS_FORM_MASK (0x03) 341 #define MPI_SCSIIO32_FLAGS_FORM_SCSIID (0x00) 342 #define MPI_SCSIIO32_FLAGS_FORM_WWID (0x01) 343 344 /* SCSI IO 32 LUN fields */ 345 #define MPI_SCSIIO32_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 346 #define MPI_SCSIIO32_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 347 #define MPI_SCSIIO32_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 348 #define MPI_SCSIIO32_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 349 #define MPI_SCSIIO32_LUN_LEVEL_1_WORD (0xFF00) 350 #define MPI_SCSIIO32_LUN_LEVEL_1_DWORD (0x0000FF00) 351 352 /* SCSI IO 32 Control bits */ 353 #define MPI_SCSIIO32_CONTROL_DATADIRECTION_MASK (0x03000000) 354 #define MPI_SCSIIO32_CONTROL_NODATATRANSFER (0x00000000) 355 #define MPI_SCSIIO32_CONTROL_WRITE (0x01000000) 356 #define MPI_SCSIIO32_CONTROL_READ (0x02000000) 357 #define MPI_SCSIIO32_CONTROL_BIDIRECTIONAL (0x03000000) 358 359 #define MPI_SCSIIO32_CONTROL_ADDCDBLEN_MASK (0xFC000000) 360 #define MPI_SCSIIO32_CONTROL_ADDCDBLEN_SHIFT (26) 361 362 #define MPI_SCSIIO32_CONTROL_TASKATTRIBUTE_MASK (0x00000700) 363 #define MPI_SCSIIO32_CONTROL_SIMPLEQ (0x00000000) 364 #define MPI_SCSIIO32_CONTROL_HEADOFQ (0x00000100) 365 #define MPI_SCSIIO32_CONTROL_ORDEREDQ (0x00000200) 366 #define MPI_SCSIIO32_CONTROL_ACAQ (0x00000400) 367 #define MPI_SCSIIO32_CONTROL_UNTAGGED (0x00000500) 368 #define MPI_SCSIIO32_CONTROL_NO_DISCONNECT (0x00000700) 369 370 #define MPI_SCSIIO32_CONTROL_TASKMANAGE_MASK (0x00FF0000) 371 #define MPI_SCSIIO32_CONTROL_OBSOLETE (0x00800000) 372 #define MPI_SCSIIO32_CONTROL_CLEAR_ACA_RSV (0x00400000) 373 #define MPI_SCSIIO32_CONTROL_TARGET_RESET (0x00200000) 374 #define MPI_SCSIIO32_CONTROL_LUN_RESET_RSV (0x00100000) 375 #define MPI_SCSIIO32_CONTROL_RESERVED (0x00080000) 376 #define MPI_SCSIIO32_CONTROL_CLR_TASK_SET_RSV (0x00040000) 377 #define MPI_SCSIIO32_CONTROL_ABORT_TASK_SET (0x00020000) 378 #define MPI_SCSIIO32_CONTROL_RESERVED2 (0x00010000) 379 380 /* SCSI IO 32 EEDPFlags */ 381 #define MPI_SCSIIO32_EEDPFLAGS_MASK_OP (0x0007) 382 #define MPI_SCSIIO32_EEDPFLAGS_NOOP_OP (0x0000) 383 #define MPI_SCSIIO32_EEDPFLAGS_CHK_OP (0x0001) 384 #define MPI_SCSIIO32_EEDPFLAGS_STRIP_OP (0x0002) 385 #define MPI_SCSIIO32_EEDPFLAGS_CHKRM_OP (0x0003) 386 #define MPI_SCSIIO32_EEDPFLAGS_INSERT_OP (0x0004) 387 #define MPI_SCSIIO32_EEDPFLAGS_REPLACE_OP (0x0006) 388 #define MPI_SCSIIO32_EEDPFLAGS_CHKREGEN_OP (0x0007) 389 390 #define MPI_SCSIIO32_EEDPFLAGS_PASS_REF_TAG (0x0008) 391 #define MPI_SCSIIO32_EEDPFLAGS_8_9THS_MODE (0x0010) 392 393 #define MPI_SCSIIO32_EEDPFLAGS_T10_CHK_MASK (0x0700) 394 #define MPI_SCSIIO32_EEDPFLAGS_T10_CHK_GUARD (0x0100) 395 #define MPI_SCSIIO32_EEDPFLAGS_T10_CHK_REFTAG (0x0200) 396 #define MPI_SCSIIO32_EEDPFLAGS_T10_CHK_LBATAG (0x0400) 397 #define MPI_SCSIIO32_EEDPFLAGS_T10_CHK_SHIFT (8) 398 399 #define MPI_SCSIIO32_EEDPFLAGS_INC_SEC_APPTAG (0x1000) 400 #define MPI_SCSIIO32_EEDPFLAGS_INC_PRI_APPTAG (0x2000) 401 #define MPI_SCSIIO32_EEDPFLAGS_INC_SEC_REFTAG (0x4000) 402 #define MPI_SCSIIO32_EEDPFLAGS_INC_PRI_REFTAG (0x8000) 403 404 405 /* SCSIIO32 IO reply structure */ 406 typedef struct _MSG_SCSIIO32_IO_REPLY 407 { 408 U8 Port; /* 00h */ 409 U8 Reserved1; /* 01h */ 410 U8 MsgLength; /* 02h */ 411 U8 Function; /* 03h */ 412 U8 CDBLength; /* 04h */ 413 U8 SenseBufferLength; /* 05h */ 414 U8 Flags; /* 06h */ 415 U8 MsgFlags; /* 07h */ 416 U32 MsgContext; /* 08h */ 417 U8 SCSIStatus; /* 0Ch */ 418 U8 SCSIState; /* 0Dh */ 419 U16 IOCStatus; /* 0Eh */ 420 U32 IOCLogInfo; /* 10h */ 421 U32 TransferCount; /* 14h */ 422 U32 SenseCount; /* 18h */ 423 U32 ResponseInfo; /* 1Ch */ 424 U16 TaskTag; /* 20h */ 425 U16 Reserved2; /* 22h */ 426 U32 BidirectionalTransferCount; /* 24h */ 427 } MSG_SCSIIO32_IO_REPLY, MPI_POINTER PTR_MSG_SCSIIO32_IO_REPLY, 428 SCSIIO32Reply_t, MPI_POINTER pSCSIIO32Reply_t; 429 430 431 /****************************************************************************/ 432 /* SCSI Task Management messages */ 433 /****************************************************************************/ 434 435 typedef struct _MSG_SCSI_TASK_MGMT 436 { 437 U8 TargetID; /* 00h */ 438 U8 Bus; /* 01h */ 439 U8 ChainOffset; /* 02h */ 440 U8 Function; /* 03h */ 441 U8 Reserved; /* 04h */ 442 U8 TaskType; /* 05h */ 443 U8 Reserved1; /* 06h */ 444 U8 MsgFlags; /* 07h */ 445 U32 MsgContext; /* 08h */ 446 U8 LUN[8]; /* 0Ch */ 447 U32 Reserved2[7]; /* 14h */ 448 U32 TaskMsgContext; /* 30h */ 449 } MSG_SCSI_TASK_MGMT, MPI_POINTER PTR_SCSI_TASK_MGMT, 450 SCSITaskMgmt_t, MPI_POINTER pSCSITaskMgmt_t; 451 452 /* TaskType values */ 453 454 #define MPI_SCSITASKMGMT_TASKTYPE_ABORT_TASK (0x01) 455 #define MPI_SCSITASKMGMT_TASKTYPE_ABRT_TASK_SET (0x02) 456 #define MPI_SCSITASKMGMT_TASKTYPE_TARGET_RESET (0x03) 457 #define MPI_SCSITASKMGMT_TASKTYPE_RESET_BUS (0x04) 458 #define MPI_SCSITASKMGMT_TASKTYPE_LOGICAL_UNIT_RESET (0x05) 459 #define MPI_SCSITASKMGMT_TASKTYPE_CLEAR_TASK_SET (0x06) 460 #define MPI_SCSITASKMGMT_TASKTYPE_QUERY_TASK (0x07) 461 #define MPI_SCSITASKMGMT_TASKTYPE_CLR_ACA (0x08) 462 463 /* MsgFlags bits */ 464 #define MPI_SCSITASKMGMT_MSGFLAGS_DO_NOT_SEND_TASK_IU (0x01) 465 466 #define MPI_SCSITASKMGMT_MSGFLAGS_TARGET_RESET_OPTION (0x00) 467 #define MPI_SCSITASKMGMT_MSGFLAGS_LIP_RESET_OPTION (0x02) 468 #define MPI_SCSITASKMGMT_MSGFLAGS_LIPRESET_RESET_OPTION (0x04) 469 470 #define MPI_SCSITASKMGMT_MSGFLAGS_SOFT_RESET_OPTION (0x08) 471 472 /* SCSI Task Management Reply */ 473 typedef struct _MSG_SCSI_TASK_MGMT_REPLY 474 { 475 U8 TargetID; /* 00h */ 476 U8 Bus; /* 01h */ 477 U8 MsgLength; /* 02h */ 478 U8 Function; /* 03h */ 479 U8 ResponseCode; /* 04h */ 480 U8 TaskType; /* 05h */ 481 U8 Reserved1; /* 06h */ 482 U8 MsgFlags; /* 07h */ 483 U32 MsgContext; /* 08h */ 484 U8 Reserved2[2]; /* 0Ch */ 485 U16 IOCStatus; /* 0Eh */ 486 U32 IOCLogInfo; /* 10h */ 487 U32 TerminationCount; /* 14h */ 488 } MSG_SCSI_TASK_MGMT_REPLY, MPI_POINTER PTR_MSG_SCSI_TASK_MGMT_REPLY, 489 SCSITaskMgmtReply_t, MPI_POINTER pSCSITaskMgmtReply_t; 490 491 /* ResponseCode values */ 492 #define MPI_SCSITASKMGMT_RSP_TM_COMPLETE (0x00) 493 #define MPI_SCSITASKMGMT_RSP_INVALID_FRAME (0x02) 494 #define MPI_SCSITASKMGMT_RSP_TM_NOT_SUPPORTED (0x04) 495 #define MPI_SCSITASKMGMT_RSP_TM_FAILED (0x05) 496 #define MPI_SCSITASKMGMT_RSP_TM_SUCCEEDED (0x08) 497 #define MPI_SCSITASKMGMT_RSP_TM_INVALID_LUN (0x09) 498 #define MPI_SCSITASKMGMT_RSP_IO_QUEUED_ON_IOC (0x80) 499 500 501 /****************************************************************************/ 502 /* SCSI Enclosure Processor messages */ 503 /****************************************************************************/ 504 505 typedef struct _MSG_SEP_REQUEST 506 { 507 U8 TargetID; /* 00h */ 508 U8 Bus; /* 01h */ 509 U8 ChainOffset; /* 02h */ 510 U8 Function; /* 03h */ 511 U8 Action; /* 04h */ 512 U8 Flags; /* 05h */ 513 U8 Reserved1; /* 06h */ 514 U8 MsgFlags; /* 07h */ 515 U32 MsgContext; /* 08h */ 516 U32 SlotStatus; /* 0Ch */ 517 U32 Reserved2; /* 10h */ 518 U32 Reserved3; /* 14h */ 519 U32 Reserved4; /* 18h */ 520 U16 Slot; /* 1Ch */ 521 U16 EnclosureHandle; /* 1Eh */ 522 } MSG_SEP_REQUEST, MPI_POINTER PTR_MSG_SEP_REQUEST, 523 SEPRequest_t, MPI_POINTER pSEPRequest_t; 524 525 /* Action defines */ 526 #define MPI_SEP_REQ_ACTION_WRITE_STATUS (0x00) 527 #define MPI_SEP_REQ_ACTION_READ_STATUS (0x01) 528 529 /* Flags defines */ 530 #define MPI_SEP_REQ_FLAGS_ENCLOSURE_SLOT_ADDRESS (0x01) 531 #define MPI_SEP_REQ_FLAGS_BUS_TARGETID_ADDRESS (0x00) 532 533 /* SlotStatus bits for MSG_SEP_REQUEST */ 534 #define MPI_SEP_REQ_SLOTSTATUS_NO_ERROR (0x00000001) 535 #define MPI_SEP_REQ_SLOTSTATUS_DEV_FAULTY (0x00000002) 536 #define MPI_SEP_REQ_SLOTSTATUS_DEV_REBUILDING (0x00000004) 537 #define MPI_SEP_REQ_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008) 538 #define MPI_SEP_REQ_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010) 539 #define MPI_SEP_REQ_SLOTSTATUS_PARITY_CHECK (0x00000020) 540 #define MPI_SEP_REQ_SLOTSTATUS_PREDICTED_FAULT (0x00000040) 541 #define MPI_SEP_REQ_SLOTSTATUS_UNCONFIGURED (0x00000080) 542 #define MPI_SEP_REQ_SLOTSTATUS_HOT_SPARE (0x00000100) 543 #define MPI_SEP_REQ_SLOTSTATUS_REBUILD_STOPPED (0x00000200) 544 #define MPI_SEP_REQ_SLOTSTATUS_REQ_CONSISTENCY_CHECK (0x00001000) 545 #define MPI_SEP_REQ_SLOTSTATUS_DISABLE (0x00002000) 546 #define MPI_SEP_REQ_SLOTSTATUS_REQ_RESERVED_DEVICE (0x00004000) 547 #define MPI_SEP_REQ_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000) 548 #define MPI_SEP_REQ_SLOTSTATUS_REQUEST_REMOVE (0x00040000) 549 #define MPI_SEP_REQ_SLOTSTATUS_REQUEST_INSERT (0x00080000) 550 #define MPI_SEP_REQ_SLOTSTATUS_DO_NOT_MOVE (0x00400000) 551 #define MPI_SEP_REQ_SLOTSTATUS_ACTIVE (0x00800000) 552 #define MPI_SEP_REQ_SLOTSTATUS_B_ENABLE_BYPASS (0x04000000) 553 #define MPI_SEP_REQ_SLOTSTATUS_A_ENABLE_BYPASS (0x08000000) 554 #define MPI_SEP_REQ_SLOTSTATUS_DEV_OFF (0x10000000) 555 #define MPI_SEP_REQ_SLOTSTATUS_SWAP_RESET (0x80000000) 556 557 558 typedef struct _MSG_SEP_REPLY 559 { 560 U8 TargetID; /* 00h */ 561 U8 Bus; /* 01h */ 562 U8 MsgLength; /* 02h */ 563 U8 Function; /* 03h */ 564 U8 Action; /* 04h */ 565 U8 Reserved1; /* 05h */ 566 U8 Reserved2; /* 06h */ 567 U8 MsgFlags; /* 07h */ 568 U32 MsgContext; /* 08h */ 569 U16 Reserved3; /* 0Ch */ 570 U16 IOCStatus; /* 0Eh */ 571 U32 IOCLogInfo; /* 10h */ 572 U32 SlotStatus; /* 14h */ 573 U32 Reserved4; /* 18h */ 574 U16 Slot; /* 1Ch */ 575 U16 EnclosureHandle; /* 1Eh */ 576 } MSG_SEP_REPLY, MPI_POINTER PTR_MSG_SEP_REPLY, 577 SEPReply_t, MPI_POINTER pSEPReply_t; 578 579 /* SlotStatus bits for MSG_SEP_REPLY */ 580 #define MPI_SEP_REPLY_SLOTSTATUS_NO_ERROR (0x00000001) 581 #define MPI_SEP_REPLY_SLOTSTATUS_DEV_FAULTY (0x00000002) 582 #define MPI_SEP_REPLY_SLOTSTATUS_DEV_REBUILDING (0x00000004) 583 #define MPI_SEP_REPLY_SLOTSTATUS_IN_FAILED_ARRAY (0x00000008) 584 #define MPI_SEP_REPLY_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000010) 585 #define MPI_SEP_REPLY_SLOTSTATUS_PARITY_CHECK (0x00000020) 586 #define MPI_SEP_REPLY_SLOTSTATUS_PREDICTED_FAULT (0x00000040) 587 #define MPI_SEP_REPLY_SLOTSTATUS_UNCONFIGURED (0x00000080) 588 #define MPI_SEP_REPLY_SLOTSTATUS_HOT_SPARE (0x00000100) 589 #define MPI_SEP_REPLY_SLOTSTATUS_REBUILD_STOPPED (0x00000200) 590 #define MPI_SEP_REPLY_SLOTSTATUS_CONSISTENCY_CHECK (0x00001000) 591 #define MPI_SEP_REPLY_SLOTSTATUS_DISABLE (0x00002000) 592 #define MPI_SEP_REPLY_SLOTSTATUS_RESERVED_DEVICE (0x00004000) 593 #define MPI_SEP_REPLY_SLOTSTATUS_REPORT (0x00010000) 594 #define MPI_SEP_REPLY_SLOTSTATUS_IDENTIFY_REQUEST (0x00020000) 595 #define MPI_SEP_REPLY_SLOTSTATUS_REMOVE_READY (0x00040000) 596 #define MPI_SEP_REPLY_SLOTSTATUS_INSERT_READY (0x00080000) 597 #define MPI_SEP_REPLY_SLOTSTATUS_DO_NOT_REMOVE (0x00400000) 598 #define MPI_SEP_REPLY_SLOTSTATUS_ACTIVE (0x00800000) 599 #define MPI_SEP_REPLY_SLOTSTATUS_B_BYPASS_ENABLED (0x01000000) 600 #define MPI_SEP_REPLY_SLOTSTATUS_A_BYPASS_ENABLED (0x02000000) 601 #define MPI_SEP_REPLY_SLOTSTATUS_B_ENABLE_BYPASS (0x04000000) 602 #define MPI_SEP_REPLY_SLOTSTATUS_A_ENABLE_BYPASS (0x08000000) 603 #define MPI_SEP_REPLY_SLOTSTATUS_DEV_OFF (0x10000000) 604 #define MPI_SEP_REPLY_SLOTSTATUS_FAULT_SENSED (0x40000000) 605 #define MPI_SEP_REPLY_SLOTSTATUS_SWAPPED (0x80000000) 606 607 #endif 608