1 /* $FreeBSD$ */ 2 /* 3 * Copyright (c) 2000-2001 LSI Logic Corporation. 4 * 5 * 6 * Name: MPI_CNFG.H 7 * Title: MPI Config message, structures, and Pages 8 * Creation Date: July 27, 2000 9 * 10 * MPI Version: 01.02.05 11 * 12 * Version History 13 * --------------- 14 * 15 * Date Version Description 16 * -------- -------- ------------------------------------------------------ 17 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 18 * 06-06-00 01.00.01 Update version number for 1.0 release. 19 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages. 20 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2 21 * fields to FC_DEVICE_0 page, updated the page version. 22 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in 23 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages 24 * and updated the page versions. 25 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1 26 * page and updated the page version. 27 * Added Information field and _INFO_PARAMS_NEGOTIATED 28 * definitionto SCSI_DEVICE_0 page. 29 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the 30 * page version. 31 * Added BucketsRemaining to LAN_1 page, redefined the 32 * state values, and updated the page version. 33 * Revised bus width definitions in SCSI_PORT_0, 34 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages. 35 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page 36 * version. 37 * Moved FC_DEVICE_0 PageAddress description to spec. 38 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field 39 * widths in IOC_0 page and updated the page version. 40 * 11-02-00 01.01.01 Original release for post 1.0 work 41 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI 42 * Port Page 2, FC Port Page 4, FC Port Page 5 43 * 11-15-00 01.01.02 Interim changes to match proposals 44 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01. 45 * 12-05-00 01.01.04 Modified config page actions. 46 * 01-09-01 01.01.05 Added defines for page address formats. 47 * Data size for Manufacturing pages 2 and 3 no longer 48 * defined here. 49 * Io Unit Page 2 size is fixed at 4 adapters and some 50 * flags were changed. 51 * SCSI Port Page 2 Device Settings modified. 52 * New fields added to FC Port Page 0 and some flags 53 * cleaned up. 54 * Removed impedance flash from FC Port Page 1. 55 * Added FC Port pages 6 and 7. 56 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0. 57 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique. 58 * Added some LinkType defines for FcPortPage0. 59 * 02-20-01 01.01.08 Started using MPI_POINTER. 60 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with 61 * MPI_CONFIG_PAGETYPE_RAID_VOLUME. 62 * Added definitions and structures for IOC Page 2 and 63 * RAID Volume Page 2. 64 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9. 65 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID. 66 * Added VendorId and ProductRevLevel fields to 67 * RAIDVOL2_IM_PHYS_ID struct. 68 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_ 69 * defines to make them compatible to MPI version 1.0. 70 * Added structure offset comments. 71 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and 72 * removed some obsolete ones. 73 * Added IO Unit Page 3. 74 * Modified defines for Scsi Port Page 2. 75 * Modified RAID Volume Pages. 76 * 08-08-01 01.02.01 Original release for v1.2 work. 77 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct. 78 * Added defines for the SEP bits in RVP2 VolumeSettings. 79 * Modified the DeviceSettings field in RVP2 to use the 80 * proper structure. 81 * Added defines for SES, SAF-TE, and cross channel for 82 * IOCPage2 CapabilitiesFlags. 83 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE. 84 * Removed define for 85 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE. 86 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT. 87 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035. 88 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY 89 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY. 90 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS, 91 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and 92 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and 93 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED. 94 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED 95 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED. 96 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1. 97 * Added rejected bits to SCSI Device Page 0 Information. 98 * Increased size of ALPA array in FC Port Page 2 by one 99 * and removed a one byte reserved field. 100 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in 101 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering. 102 * Added structures for Manufacturing Page 4, IO Unit 103 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and 104 * RAID PhysDisk Page 0. 105 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK. 106 * Modified some of the new defines to make them 32 107 * character unique. 108 * Modified how variable length pages (arrays) are defined. 109 * Added generic defines for hot spare pools and RAID 110 * volume types. 111 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR. 112 * -------------------------------------------------------------------------- 113 */ 114 115 #ifndef MPI_CNFG_H 116 #define MPI_CNFG_H 117 118 119 /***************************************************************************** 120 * 121 * C o n f i g M e s s a g e a n d S t r u c t u r e s 122 * 123 *****************************************************************************/ 124 125 typedef struct _CONFIG_PAGE_HEADER 126 { 127 U8 PageVersion; /* 00h */ 128 U8 PageLength; /* 01h */ 129 U8 PageNumber; /* 02h */ 130 U8 PageType; /* 03h */ 131 } fCONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER, 132 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t; 133 134 typedef union _CONFIG_PAGE_HEADER_UNION 135 { 136 ConfigPageHeader_t Struct; 137 U8 Bytes[4]; 138 U16 Word16[2]; 139 U32 Word32; 140 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion, 141 fCONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION; 142 143 144 /**************************************************************************** 145 * PageType field values 146 ****************************************************************************/ 147 #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00) 148 #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10) 149 #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20) 150 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30) 151 #define MPI_CONFIG_PAGEATTR_MASK (0xF0) 152 153 #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00) 154 #define MPI_CONFIG_PAGETYPE_IOC (0x01) 155 #define MPI_CONFIG_PAGETYPE_BIOS (0x02) 156 #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03) 157 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04) 158 #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05) 159 #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06) 160 #define MPI_CONFIG_PAGETYPE_LAN (0x07) 161 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 162 #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09) 163 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 164 #define MPI_CONFIG_PAGETYPE_MASK (0x0F) 165 166 #define MPI_CONFIG_TYPENUM_MASK (0x0FFF) 167 168 169 /**************************************************************************** 170 * PageAddress field values 171 ****************************************************************************/ 172 #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF) 173 174 #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF) 175 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0) 176 #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00) 177 #define MPI_SCSI_DEVICE_BUS_SHIFT (8) 178 179 #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000) 180 #define MPI_FC_PORT_PGAD_PORT_SHIFT (28) 181 #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000) 182 #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000) 183 #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF) 184 #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0) 185 186 #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000) 187 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28) 188 #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000) 189 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000) 190 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000) 191 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28) 192 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF) 193 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0) 194 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000) 195 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 196 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8) 197 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 198 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0) 199 200 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 201 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0) 202 203 204 205 /**************************************************************************** 206 * Config Request Message 207 ****************************************************************************/ 208 typedef struct _MSG_CONFIG 209 { 210 U8 Action; /* 00h */ 211 U8 Reserved; /* 01h */ 212 U8 ChainOffset; /* 02h */ 213 U8 Function; /* 03h */ 214 U8 Reserved1[3]; /* 04h */ 215 U8 MsgFlags; /* 07h */ 216 U32 MsgContext; /* 08h */ 217 U8 Reserved2[8]; /* 0Ch */ 218 fCONFIG_PAGE_HEADER Header; /* 14h */ 219 U32 PageAddress; /* 18h */ 220 SGE_IO_UNION PageBufferSGE; /* 1Ch */ 221 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG, 222 Config_t, MPI_POINTER pConfig_t; 223 224 225 /**************************************************************************** 226 * Action field values 227 ****************************************************************************/ 228 #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00) 229 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 230 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 231 #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03) 232 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 233 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 234 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 235 236 237 /* Config Reply Message */ 238 typedef struct _MSG_CONFIG_REPLY 239 { 240 U8 Action; /* 00h */ 241 U8 Reserved; /* 01h */ 242 U8 MsgLength; /* 02h */ 243 U8 Function; /* 03h */ 244 U8 Reserved1[3]; /* 04h */ 245 U8 MsgFlags; /* 07h */ 246 U32 MsgContext; /* 08h */ 247 U8 Reserved2[2]; /* 0Ch */ 248 U16 IOCStatus; /* 0Eh */ 249 U32 IOCLogInfo; /* 10h */ 250 fCONFIG_PAGE_HEADER Header; /* 14h */ 251 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY, 252 ConfigReply_t, MPI_POINTER pConfigReply_t; 253 254 255 256 /***************************************************************************** 257 * 258 * C o n f i g u r a t i o n P a g e s 259 * 260 *****************************************************************************/ 261 262 /**************************************************************************** 263 * Manufacturing Config pages 264 ****************************************************************************/ 265 #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621) 266 #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624) 267 #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622) 268 #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628) 269 #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626) 270 #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030) 271 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031) 272 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032) 273 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033) 274 #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040) 275 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041) 276 277 typedef struct _CONFIG_PAGE_MANUFACTURING_0 278 { 279 fCONFIG_PAGE_HEADER Header; /* 00h */ 280 U8 ChipName[16]; /* 04h */ 281 U8 ChipRevision[8]; /* 14h */ 282 U8 BoardName[16]; /* 1Ch */ 283 U8 BoardAssembly[16]; /* 2Ch */ 284 U8 BoardTracerNumber[16]; /* 3Ch */ 285 286 } fCONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0, 287 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t; 288 289 #define MPI_MANUFACTURING0_PAGEVERSION (0x00) 290 291 292 typedef struct _CONFIG_PAGE_MANUFACTURING_1 293 { 294 fCONFIG_PAGE_HEADER Header; /* 00h */ 295 U8 VPD[256]; /* 04h */ 296 } fCONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1, 297 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t; 298 299 #define MPI_MANUFACTURING1_PAGEVERSION (0x00) 300 301 302 typedef struct _MPI_CHIP_REVISION_ID 303 { 304 U16 DeviceID; /* 00h */ 305 U8 PCIRevisionID; /* 02h */ 306 U8 Reserved; /* 03h */ 307 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID, 308 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t; 309 310 311 /* 312 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 313 * one and check Header.PageLength at runtime. 314 */ 315 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS 316 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 317 #endif 318 319 typedef struct _CONFIG_PAGE_MANUFACTURING_2 320 { 321 fCONFIG_PAGE_HEADER Header; /* 00h */ 322 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 323 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */ 324 } fCONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2, 325 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t; 326 327 #define MPI_MANUFACTURING2_PAGEVERSION (0x00) 328 329 330 /* 331 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 332 * one and check Header.PageLength at runtime. 333 */ 334 #ifndef MPI_MAN_PAGE_3_INFO_WORDS 335 #define MPI_MAN_PAGE_3_INFO_WORDS (1) 336 #endif 337 338 typedef struct _CONFIG_PAGE_MANUFACTURING_3 339 { 340 fCONFIG_PAGE_HEADER Header; /* 00h */ 341 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 342 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */ 343 } fCONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3, 344 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t; 345 346 #define MPI_MANUFACTURING3_PAGEVERSION (0x00) 347 348 349 typedef struct _CONFIG_PAGE_MANUFACTURING_4 350 { 351 fCONFIG_PAGE_HEADER Header; /* 00h */ 352 U32 Reserved1; /* 04h */ 353 U8 InfoOffset0; /* 08h */ 354 U8 InfoSize0; /* 09h */ 355 U8 InfoOffset1; /* 0Ah */ 356 U8 InfoSize1; /* 0Bh */ 357 U8 InquirySize; /* 0Ch */ 358 U8 Reserved2; /* 0Dh */ 359 U16 Reserved3; /* 0Eh */ 360 U8 InquiryData[56]; /* 10h */ 361 U32 ISVolumeSettings; /* 48h */ 362 U32 IMEVolumeSettings; /* 4Ch */ 363 U32 IMVolumeSettings; /* 50h */ 364 } fCONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4, 365 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t; 366 367 #define MPI_MANUFACTURING4_PAGEVERSION (0x00) 368 369 370 /**************************************************************************** 371 * IO Unit Config Pages 372 ****************************************************************************/ 373 374 typedef struct _CONFIG_PAGE_IO_UNIT_0 375 { 376 fCONFIG_PAGE_HEADER Header; /* 00h */ 377 U64 UniqueValue; /* 04h */ 378 } fCONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0, 379 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t; 380 381 #define MPI_IOUNITPAGE0_PAGEVERSION (0x00) 382 383 384 typedef struct _CONFIG_PAGE_IO_UNIT_1 385 { 386 fCONFIG_PAGE_HEADER Header; /* 00h */ 387 U32 Flags; /* 04h */ 388 } fCONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1, 389 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t; 390 391 #define MPI_IOUNITPAGE1_PAGEVERSION (0x00) 392 393 /* IO Unit Page 1 Flags defines */ 394 395 #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000) 396 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001) 397 #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002) 398 #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000) 399 #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040) 400 #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080) 401 402 403 typedef struct _MPI_ADAPTER_INFO 404 { 405 U8 PciBusNumber; /* 00h */ 406 U8 PciDeviceAndFunctionNumber; /* 01h */ 407 U16 AdapterFlags; /* 02h */ 408 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO, 409 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t; 410 411 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 412 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 413 414 typedef struct _CONFIG_PAGE_IO_UNIT_2 415 { 416 fCONFIG_PAGE_HEADER Header; /* 00h */ 417 U32 Flags; /* 04h */ 418 U32 BiosVersion; /* 08h */ 419 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */ 420 } fCONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2, 421 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t; 422 423 #define MPI_IOUNITPAGE2_PAGEVERSION (0x00) 424 425 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002) 426 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004) 427 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008) 428 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010) 429 430 431 /* 432 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 433 * one and check Header.PageLength at runtime. 434 */ 435 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX 436 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 437 #endif 438 439 typedef struct _CONFIG_PAGE_IO_UNIT_3 440 { 441 fCONFIG_PAGE_HEADER Header; /* 00h */ 442 U8 GPIOCount; /* 04h */ 443 U8 Reserved1; /* 05h */ 444 U16 Reserved2; /* 06h */ 445 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */ 446 } fCONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3, 447 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t; 448 449 #define MPI_IOUNITPAGE3_PAGEVERSION (0x01) 450 451 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC) 452 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 453 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00) 454 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01) 455 456 457 /**************************************************************************** 458 * IOC Config Pages 459 ****************************************************************************/ 460 461 typedef struct _CONFIG_PAGE_IOC_0 462 { 463 fCONFIG_PAGE_HEADER Header; /* 00h */ 464 U32 TotalNVStore; /* 04h */ 465 U32 FreeNVStore; /* 08h */ 466 U16 VendorID; /* 0Ch */ 467 U16 DeviceID; /* 0Eh */ 468 U8 RevisionID; /* 10h */ 469 U8 Reserved[3]; /* 11h */ 470 U32 ClassCode; /* 14h */ 471 U16 SubsystemVendorID; /* 18h */ 472 U16 SubsystemID; /* 1Ah */ 473 } fCONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0, 474 IOCPage0_t, MPI_POINTER pIOCPage0_t; 475 476 #define MPI_IOCPAGE0_PAGEVERSION (0x01) 477 478 479 typedef struct _CONFIG_PAGE_IOC_1 480 { 481 fCONFIG_PAGE_HEADER Header; /* 00h */ 482 U32 Flags; /* 04h */ 483 U32 CoalescingTimeout; /* 08h */ 484 U8 CoalescingDepth; /* 0Ch */ 485 U8 Reserved[3]; /* 0Dh */ 486 } fCONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1, 487 IOCPage1_t, MPI_POINTER pIOCPage1_t; 488 489 #define MPI_IOCPAGE1_PAGEVERSION (0x00) 490 491 #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001) 492 493 494 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL 495 { 496 U8 VolumeID; /* 00h */ 497 U8 VolumeBus; /* 01h */ 498 U8 VolumeIOC; /* 02h */ 499 U8 VolumePageNumber; /* 03h */ 500 U8 VolumeType; /* 04h */ 501 U8 Reserved2; /* 05h */ 502 U16 Reserved3; /* 06h */ 503 } fCONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL, 504 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t; 505 506 /* 507 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 508 * one and check Header.PageLength at runtime. 509 */ 510 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX 511 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1) 512 #endif 513 514 typedef struct _CONFIG_PAGE_IOC_2 515 { 516 fCONFIG_PAGE_HEADER Header; /* 00h */ 517 U32 CapabilitiesFlags; /* 04h */ 518 U8 NumActiveVolumes; /* 08h */ 519 U8 MaxVolumes; /* 09h */ 520 U8 NumActivePhysDisks; /* 0Ah */ 521 U8 MaxPhysDisks; /* 0Bh */ 522 fCONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */ 523 } fCONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2, 524 IOCPage2_t, MPI_POINTER pIOCPage2_t; 525 526 #define MPI_IOCPAGE2_PAGEVERSION (0x01) 527 528 /* IOC Page 2 Capabilities flags */ 529 530 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001) 531 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002) 532 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004) 533 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000) 534 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000) 535 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000) 536 537 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */ 538 539 #define MPI_RAID_VOL_TYPE_IS (0x00) 540 #define MPI_RAID_VOL_TYPE_IME (0x01) 541 #define MPI_RAID_VOL_TYPE_IM (0x02) 542 543 544 typedef struct _IOC_3_PHYS_DISK 545 { 546 U8 PhysDiskID; /* 00h */ 547 U8 PhysDiskBus; /* 01h */ 548 U8 PhysDiskIOC; /* 02h */ 549 U8 PhysDiskNum; /* 03h */ 550 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK, 551 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t; 552 553 /* 554 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 555 * one and check Header.PageLength at runtime. 556 */ 557 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX 558 #define MPI_IOC_PAGE_3_PHYSDISK_MAX (1) 559 #endif 560 561 typedef struct _CONFIG_PAGE_IOC_3 562 { 563 fCONFIG_PAGE_HEADER Header; /* 00h */ 564 U8 NumPhysDisks; /* 04h */ 565 U8 Reserved1; /* 05h */ 566 U16 Reserved2; /* 06h */ 567 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */ 568 } fCONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3, 569 IOCPage3_t, MPI_POINTER pIOCPage3_t; 570 571 #define MPI_IOCPAGE3_PAGEVERSION (0x00) 572 573 574 typedef struct _IOC_4_SEP 575 { 576 U8 SEPTargetID; /* 00h */ 577 U8 SEPBus; /* 01h */ 578 U16 Reserved; /* 02h */ 579 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP, 580 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t; 581 582 /* 583 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 584 * one and check Header.PageLength at runtime. 585 */ 586 #ifndef MPI_IOC_PAGE_4_SEP_MAX 587 #define MPI_IOC_PAGE_4_SEP_MAX (1) 588 #endif 589 590 typedef struct _CONFIG_PAGE_IOC_4 591 { 592 fCONFIG_PAGE_HEADER Header; /* 00h */ 593 U8 ActiveSEP; /* 04h */ 594 U8 MaxSEP; /* 05h */ 595 U16 Reserved1; /* 06h */ 596 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */ 597 } fCONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4, 598 IOCPage4_t, MPI_POINTER pIOCPage4_t; 599 600 #define MPI_IOCPAGE4_PAGEVERSION (0x00) 601 602 603 /**************************************************************************** 604 * SCSI Port Config Pages 605 ****************************************************************************/ 606 607 typedef struct _CONFIG_PAGE_SCSI_PORT_0 608 { 609 fCONFIG_PAGE_HEADER Header; /* 00h */ 610 U32 Capabilities; /* 04h */ 611 U32 PhysicalInterface; /* 08h */ 612 } fCONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0, 613 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t; 614 615 #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x01) 616 617 #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001) 618 #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002) 619 #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004) 620 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 621 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 622 #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000) 623 #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000) 624 625 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003) 626 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01) 627 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02) 628 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03) 629 630 631 typedef struct _CONFIG_PAGE_SCSI_PORT_1 632 { 633 fCONFIG_PAGE_HEADER Header; /* 00h */ 634 U32 Configuration; /* 04h */ 635 U32 OnBusTimerValue; /* 08h */ 636 } fCONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1, 637 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t; 638 639 #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x02) 640 641 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF) 642 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000) 643 644 645 typedef struct _MPI_DEVICE_INFO 646 { 647 U8 Timeout; /* 00h */ 648 U8 SyncFactor; /* 01h */ 649 U16 DeviceFlags; /* 02h */ 650 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO, 651 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t; 652 653 typedef struct _CONFIG_PAGE_SCSI_PORT_2 654 { 655 fCONFIG_PAGE_HEADER Header; /* 00h */ 656 U32 PortFlags; /* 04h */ 657 U32 PortSettings; /* 08h */ 658 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */ 659 } fCONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2, 660 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t; 661 662 #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x01) 663 664 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001) 665 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004) 666 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 667 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010) 668 669 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F) 670 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030) 671 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000) 672 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010) 673 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020) 674 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030) 675 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0) 676 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00) 677 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000) 678 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000) 679 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000) 680 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000) 681 682 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001) 683 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002) 684 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004) 685 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008) 686 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010) 687 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020) 688 689 690 /**************************************************************************** 691 * SCSI Target Device Config Pages 692 ****************************************************************************/ 693 694 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0 695 { 696 fCONFIG_PAGE_HEADER Header; /* 00h */ 697 U32 NegotiatedParameters; /* 04h */ 698 U32 Information; /* 08h */ 699 } fCONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0, 700 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t; 701 702 #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x02) 703 704 #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001) 705 #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002) 706 #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004) 707 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00) 708 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000) 709 #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000) 710 #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000) 711 712 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001) 713 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002) 714 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004) 715 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008) 716 717 718 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1 719 { 720 fCONFIG_PAGE_HEADER Header; /* 00h */ 721 U32 RequestedParameters; /* 04h */ 722 U32 Reserved; /* 08h */ 723 U32 Configuration; /* 0Ch */ 724 } fCONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1, 725 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t; 726 727 #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x03) 728 729 #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001) 730 #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002) 731 #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004) 732 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 733 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 734 #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000) 735 #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000) 736 737 #define MPI_SCSIDEVPAGE1_DV_LVD_DRIVE_STRENGTH_MASK (0x00000003) 738 #define MPI_SCSIDEVPAGE1_DV_SE_SLEW_RATE_MASK (0x00000300) 739 740 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002) 741 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004) 742 743 744 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2 745 { 746 fCONFIG_PAGE_HEADER Header; /* 00h */ 747 U32 DomainValidation; /* 04h */ 748 U32 ParityPipeSelect; /* 08h */ 749 U32 DataPipeSelect; /* 0Ch */ 750 } fCONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2, 751 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t; 752 753 #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x00) 754 755 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010) 756 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020) 757 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380) 758 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00) 759 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000) 760 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000) 761 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000) 762 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000) 763 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000) 764 765 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003) 766 767 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003) 768 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C) 769 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030) 770 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0) 771 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300) 772 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00) 773 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000) 774 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000) 775 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000) 776 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000) 777 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000) 778 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000) 779 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000) 780 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000) 781 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000) 782 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000) 783 784 785 /**************************************************************************** 786 * FC Port Config Pages 787 ****************************************************************************/ 788 789 typedef struct _CONFIG_PAGE_FC_PORT_0 790 { 791 fCONFIG_PAGE_HEADER Header; /* 00h */ 792 U32 Flags; /* 04h */ 793 U8 MPIPortNumber; /* 08h */ 794 U8 LinkType; /* 09h */ 795 U8 PortState; /* 0Ah */ 796 U8 Reserved; /* 0Bh */ 797 U32 PortIdentifier; /* 0Ch */ 798 U64 WWNN; /* 10h */ 799 U64 WWPN; /* 18h */ 800 U32 SupportedServiceClass; /* 20h */ 801 U32 SupportedSpeeds; /* 24h */ 802 U32 CurrentSpeed; /* 28h */ 803 U32 MaxFrameSize; /* 2Ch */ 804 U64 FabricWWNN; /* 30h */ 805 U64 FabricWWPN; /* 38h */ 806 U32 DiscoveredPortsCount; /* 40h */ 807 U32 MaxInitiators; /* 44h */ 808 } fCONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0, 809 FCPortPage0_t, MPI_POINTER pFCPortPage0_t; 810 811 #define MPI_FCPORTPAGE0_PAGEVERSION (0x01) 812 813 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F) 814 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR) 815 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET) 816 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN) 817 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR) 818 819 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010) 820 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020) 821 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000030) 822 823 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00) 824 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000) 825 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100) 826 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200) 827 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400) 828 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800) 829 830 #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00) 831 #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01) 832 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02) 833 #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03) 834 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04) 835 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05) 836 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06) 837 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07) 838 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08) 839 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09) 840 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A) 841 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B) 842 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C) 843 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D) 844 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E) 845 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F) 846 847 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */ 848 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */ 849 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */ 850 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */ 851 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */ 852 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */ 853 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */ 854 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */ 855 856 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001) 857 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002) 858 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004) 859 860 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */ 861 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */ 862 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */ 863 864 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED 865 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED 866 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED 867 868 869 typedef struct _CONFIG_PAGE_FC_PORT_1 870 { 871 fCONFIG_PAGE_HEADER Header; /* 00h */ 872 U32 Flags; /* 04h */ 873 U64 NoSEEPROMWWNN; /* 08h */ 874 U64 NoSEEPROMWWPN; /* 10h */ 875 U8 HardALPA; /* 18h */ 876 U8 LinkConfig; /* 19h */ 877 U8 TopologyConfig; /* 1Ah */ 878 U8 Reserved; /* 1Bh */ 879 } fCONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1, 880 FCPortPage1_t, MPI_POINTER pFCPortPage1_t; 881 882 #define MPI_FCPORTPAGE1_PAGEVERSION (0x02) 883 884 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000) 885 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000) 886 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001) 887 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000) 888 889 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000) 890 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28) 891 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 892 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 893 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 894 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 895 896 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF) 897 898 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F) 899 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00) 900 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01) 901 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02) 902 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03) 903 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F) 904 905 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F) 906 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01) 907 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02) 908 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F) 909 910 911 typedef struct _CONFIG_PAGE_FC_PORT_2 912 { 913 fCONFIG_PAGE_HEADER Header; /* 00h */ 914 U8 NumberActive; /* 04h */ 915 U8 ALPA[127]; /* 05h */ 916 } fCONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2, 917 FCPortPage2_t, MPI_POINTER pFCPortPage2_t; 918 919 #define MPI_FCPORTPAGE2_PAGEVERSION (0x01) 920 921 922 typedef struct _WWN_FORMAT 923 { 924 U64 WWNN; /* 00h */ 925 U64 WWPN; /* 08h */ 926 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT, 927 WWNFormat, MPI_POINTER pWWNFormat; 928 929 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID 930 { 931 WWN_FORMAT WWN; 932 U32 Did; 933 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID, 934 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t; 935 936 typedef struct _FC_PORT_PERSISTENT 937 { 938 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */ 939 U8 TargetID; /* 10h */ 940 U8 Bus; /* 11h */ 941 U16 Flags; /* 12h */ 942 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT, 943 PersistentData_t, MPI_POINTER pPersistentData_t; 944 945 #define MPI_PERSISTENT_FLAGS_SHIFT (16) 946 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001) 947 #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002) 948 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004) 949 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008) 950 #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080) 951 952 /* 953 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 954 * one and check Header.PageLength at runtime. 955 */ 956 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX 957 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1) 958 #endif 959 960 typedef struct _CONFIG_PAGE_FC_PORT_3 961 { 962 fCONFIG_PAGE_HEADER Header; /* 00h */ 963 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */ 964 } fCONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3, 965 FCPortPage3_t, MPI_POINTER pFCPortPage3_t; 966 967 #define MPI_FCPORTPAGE3_PAGEVERSION (0x01) 968 969 970 typedef struct _CONFIG_PAGE_FC_PORT_4 971 { 972 fCONFIG_PAGE_HEADER Header; /* 00h */ 973 U32 PortFlags; /* 04h */ 974 U32 PortSettings; /* 08h */ 975 } fCONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4, 976 FCPortPage4_t, MPI_POINTER pFCPortPage4_t; 977 978 #define MPI_FCPORTPAGE4_PAGEVERSION (0x00) 979 980 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 981 982 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030) 983 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000) 984 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010) 985 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020) 986 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030) 987 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0) 988 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00) 989 990 991 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO 992 { 993 U8 Flags; /* 00h */ 994 U8 AliasAlpa; /* 01h */ 995 U16 Reserved; /* 02h */ 996 U64 AliasWWNN; /* 04h */ 997 U64 AliasWWPN; /* 0Ch */ 998 } fCONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 999 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1000 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t; 1001 1002 /* 1003 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1004 * one and check Header.PageLength at runtime. 1005 */ 1006 #ifndef MPI_FC_PORT_PAGE_5_ALIAS_MAX 1007 #define MPI_FC_PORT_PAGE_5_ALIAS_MAX (1) 1008 #endif 1009 1010 typedef struct _CONFIG_PAGE_FC_PORT_5 1011 { 1012 fCONFIG_PAGE_HEADER Header; /* 00h */ 1013 fCONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo[MPI_FC_PORT_PAGE_5_ALIAS_MAX];/* 04h */ 1014 } fCONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5, 1015 FCPortPage5_t, MPI_POINTER pFCPortPage5_t; 1016 1017 #define MPI_FCPORTPAGE5_PAGEVERSION (0x00) 1018 1019 #define MPI_FCPORTPAGE5_FLAGS_ALIAS_ALPA_VALID (0x01) 1020 #define MPI_FCPORTPAGE5_FLAGS_ALIAS_WWN_VALID (0x02) 1021 1022 1023 typedef struct _CONFIG_PAGE_FC_PORT_6 1024 { 1025 fCONFIG_PAGE_HEADER Header; /* 00h */ 1026 U32 Reserved; /* 04h */ 1027 U64 TimeSinceReset; /* 08h */ 1028 U64 TxFrames; /* 10h */ 1029 U64 RxFrames; /* 18h */ 1030 U64 TxWords; /* 20h */ 1031 U64 RxWords; /* 28h */ 1032 U64 LipCount; /* 30h */ 1033 U64 NosCount; /* 38h */ 1034 U64 ErrorFrames; /* 40h */ 1035 U64 DumpedFrames; /* 48h */ 1036 U64 LinkFailureCount; /* 50h */ 1037 U64 LossOfSyncCount; /* 58h */ 1038 U64 LossOfSignalCount; /* 60h */ 1039 U64 PrimativeSeqErrCount; /* 68h */ 1040 U64 InvalidTxWordCount; /* 70h */ 1041 U64 InvalidCrcCount; /* 78h */ 1042 U64 FcpInitiatorIoCount; /* 80h */ 1043 } fCONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6, 1044 FCPortPage6_t, MPI_POINTER pFCPortPage6_t; 1045 1046 #define MPI_FCPORTPAGE6_PAGEVERSION (0x00) 1047 1048 1049 typedef struct _CONFIG_PAGE_FC_PORT_7 1050 { 1051 fCONFIG_PAGE_HEADER Header; /* 00h */ 1052 U32 Reserved; /* 04h */ 1053 U8 PortSymbolicName[256]; /* 08h */ 1054 } fCONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7, 1055 FCPortPage7_t, MPI_POINTER pFCPortPage7_t; 1056 1057 #define MPI_FCPORTPAGE7_PAGEVERSION (0x00) 1058 1059 1060 typedef struct _CONFIG_PAGE_FC_PORT_8 1061 { 1062 fCONFIG_PAGE_HEADER Header; /* 00h */ 1063 U32 BitVector[8]; /* 04h */ 1064 } fCONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8, 1065 FCPortPage8_t, MPI_POINTER pFCPortPage8_t; 1066 1067 #define MPI_FCPORTPAGE8_PAGEVERSION (0x00) 1068 1069 1070 typedef struct _CONFIG_PAGE_FC_PORT_9 1071 { 1072 fCONFIG_PAGE_HEADER Header; /* 00h */ 1073 U32 Reserved; /* 04h */ 1074 U64 GlobalWWPN; /* 08h */ 1075 U64 GlobalWWNN; /* 10h */ 1076 U32 UnitType; /* 18h */ 1077 U32 PhysicalPortNumber; /* 1Ch */ 1078 U32 NumAttachedNodes; /* 20h */ 1079 U16 IPVersion; /* 24h */ 1080 U16 UDPPortNumber; /* 26h */ 1081 U8 IPAddress[16]; /* 28h */ 1082 U16 Reserved1; /* 38h */ 1083 U16 TopologyDiscoveryFlags; /* 3Ah */ 1084 } fCONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9, 1085 FCPortPage9_t, MPI_POINTER pFCPortPage9_t; 1086 1087 #define MPI_FCPORTPAGE9_PAGEVERSION (0x00) 1088 1089 1090 /**************************************************************************** 1091 * FC Device Config Pages 1092 ****************************************************************************/ 1093 1094 typedef struct _CONFIG_PAGE_FC_DEVICE_0 1095 { 1096 fCONFIG_PAGE_HEADER Header; /* 00h */ 1097 U64 WWNN; /* 04h */ 1098 U64 WWPN; /* 0Ch */ 1099 U32 PortIdentifier; /* 14h */ 1100 U8 Protocol; /* 18h */ 1101 U8 Flags; /* 19h */ 1102 U16 BBCredit; /* 1Ah */ 1103 U16 MaxRxFrameSize; /* 1Ch */ 1104 U8 Reserved1; /* 1Eh */ 1105 U8 PortNumber; /* 1Fh */ 1106 U8 FcPhLowestVersion; /* 20h */ 1107 U8 FcPhHighestVersion; /* 21h */ 1108 U8 CurrentTargetID; /* 22h */ 1109 U8 CurrentBus; /* 23h */ 1110 } fCONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0, 1111 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t; 1112 1113 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x02) 1114 1115 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01) 1116 1117 #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01) 1118 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02) 1119 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04) 1120 1121 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK) 1122 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK) 1123 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) 1124 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID) 1125 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK) 1126 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK) 1127 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT) 1128 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK) 1129 1130 1131 /**************************************************************************** 1132 * RAID Volume Config Pages 1133 ****************************************************************************/ 1134 1135 typedef struct _RAID_VOL0_PHYS_DISK 1136 { 1137 U16 Reserved; /* 00h */ 1138 U8 PhysDiskMap; /* 02h */ 1139 U8 PhysDiskNum; /* 03h */ 1140 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK, 1141 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t; 1142 1143 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1144 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1145 1146 typedef struct _RAID_VOL0_STATUS 1147 { 1148 U8 Flags; /* 00h */ 1149 U8 State; /* 01h */ 1150 U16 Reserved; /* 02h */ 1151 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS, 1152 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t; 1153 1154 /* RAID Volume Page 0 VolumeStatus defines */ 1155 1156 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01) 1157 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02) 1158 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04) 1159 1160 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00) 1161 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01) 1162 #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02) 1163 1164 typedef struct _RAID_VOL0_SETTINGS 1165 { 1166 U16 Settings; /* 00h */ 1167 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 1168 U8 Reserved; /* 02h */ 1169 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS, 1170 RaidVol0Settings, MPI_POINTER pRaidVol0Settings; 1171 1172 /* RAID Volume Page 0 VolumeSettings defines */ 1173 1174 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001) 1175 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002) 1176 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004) 1177 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008) 1178 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010) 1179 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000) 1180 1181 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1182 #define MPI_RAID_HOT_SPARE_POOL_0 (0x01) 1183 #define MPI_RAID_HOT_SPARE_POOL_1 (0x02) 1184 #define MPI_RAID_HOT_SPARE_POOL_2 (0x04) 1185 #define MPI_RAID_HOT_SPARE_POOL_3 (0x08) 1186 #define MPI_RAID_HOT_SPARE_POOL_4 (0x10) 1187 #define MPI_RAID_HOT_SPARE_POOL_5 (0x20) 1188 #define MPI_RAID_HOT_SPARE_POOL_6 (0x40) 1189 #define MPI_RAID_HOT_SPARE_POOL_7 (0x80) 1190 1191 /* 1192 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1193 * one and check Header.PageLength at runtime. 1194 */ 1195 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX 1196 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1197 #endif 1198 1199 typedef struct _CONFIG_PAGE_RAID_VOL_0 1200 { 1201 fCONFIG_PAGE_HEADER Header; /* 00h */ 1202 U8 VolumeID; /* 04h */ 1203 U8 VolumeBus; /* 05h */ 1204 U8 VolumeIOC; /* 06h */ 1205 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */ 1206 RAID_VOL0_STATUS VolumeStatus; /* 08h */ 1207 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */ 1208 U32 MaxLBA; /* 10h */ 1209 U32 Reserved1; /* 14h */ 1210 U32 StripeSize; /* 18h */ 1211 U32 Reserved2; /* 1Ch */ 1212 U32 Reserved3; /* 20h */ 1213 U8 NumPhysDisks; /* 24h */ 1214 U8 Reserved4; /* 25h */ 1215 U16 Reserved5; /* 26h */ 1216 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */ 1217 } fCONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0, 1218 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t; 1219 1220 #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x00) 1221 1222 1223 /**************************************************************************** 1224 * RAID Physical Disk Config Pages 1225 ****************************************************************************/ 1226 1227 typedef struct _RAID_PHYS_DISK0_ERROR_DATA 1228 { 1229 U8 ErrorCdbByte; /* 00h */ 1230 U8 ErrorSenseKey; /* 01h */ 1231 U16 Reserved; /* 02h */ 1232 U16 ErrorCount; /* 04h */ 1233 U8 ErrorASC; /* 06h */ 1234 U8 ErrorASCQ; /* 07h */ 1235 U16 SmartCount; /* 08h */ 1236 U8 SmartASC; /* 0Ah */ 1237 U8 SmartASCQ; /* 0Bh */ 1238 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA, 1239 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t; 1240 1241 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA 1242 { 1243 U8 VendorID[8]; /* 00h */ 1244 U8 ProductID[16]; /* 08h */ 1245 U8 ProductRevLevel[4]; /* 18h */ 1246 U8 Info[32]; /* 1Ch */ 1247 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA, 1248 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData; 1249 1250 typedef struct _RAID_PHYS_DISK0_SETTINGS 1251 { 1252 U8 SepID; /* 00h */ 1253 U8 SepBus; /* 01h */ 1254 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 1255 U8 PhysDiskSettings; /* 03h */ 1256 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS, 1257 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t; 1258 1259 typedef struct _RAID_PHYS_DISK0_STATUS 1260 { 1261 U8 Flags; /* 00h */ 1262 U8 State; /* 01h */ 1263 U16 Reserved; /* 02h */ 1264 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS, 1265 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t; 1266 1267 /* RAID Volume 2 IM Physical Disk DiskStatus flags */ 1268 1269 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01) 1270 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02) 1271 1272 #define MPI_PHYSDISK0_STATUS_ONLINE (0x00) 1273 #define MPI_PHYSDISK0_STATUS_MISSING (0x01) 1274 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02) 1275 #define MPI_PHYSDISK0_STATUS_FAILED (0x03) 1276 #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04) 1277 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05) 1278 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06) 1279 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF) 1280 1281 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0 1282 { 1283 fCONFIG_PAGE_HEADER Header; /* 00h */ 1284 U8 PhysDiskID; /* 04h */ 1285 U8 PhysDiskBus; /* 05h */ 1286 U8 PhysDiskIOC; /* 06h */ 1287 U8 PhysDiskNum; /* 07h */ 1288 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */ 1289 U32 Reserved1; /* 0Ch */ 1290 U32 Reserved2; /* 10h */ 1291 U32 Reserved3; /* 14h */ 1292 U8 DiskIdentifier[16]; /* 18h */ 1293 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */ 1294 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */ 1295 U32 MaxLBA; /* 68h */ 1296 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */ 1297 } fCONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0, 1298 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t; 1299 1300 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x00) 1301 1302 1303 /**************************************************************************** 1304 * LAN Config Pages 1305 ****************************************************************************/ 1306 1307 typedef struct _CONFIG_PAGE_LAN_0 1308 { 1309 ConfigPageHeader_t Header; /* 00h */ 1310 U16 TxRxModes; /* 04h */ 1311 U16 Reserved; /* 06h */ 1312 U32 PacketPrePad; /* 08h */ 1313 } fCONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0, 1314 LANPage0_t, MPI_POINTER pLANPage0_t; 1315 1316 #define MPI_LAN_PAGE0_PAGEVERSION (0x01) 1317 1318 #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000) 1319 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001) 1320 #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001) 1321 1322 typedef struct _CONFIG_PAGE_LAN_1 1323 { 1324 ConfigPageHeader_t Header; /* 00h */ 1325 U16 Reserved; /* 04h */ 1326 U8 CurrentDeviceState; /* 06h */ 1327 U8 Reserved1; /* 07h */ 1328 U32 MinPacketSize; /* 08h */ 1329 U32 MaxPacketSize; /* 0Ch */ 1330 U32 HardwareAddressLow; /* 10h */ 1331 U32 HardwareAddressHigh; /* 14h */ 1332 U32 MaxWireSpeedLow; /* 18h */ 1333 U32 MaxWireSpeedHigh; /* 1Ch */ 1334 U32 BucketsRemaining; /* 20h */ 1335 U32 MaxReplySize; /* 24h */ 1336 U32 NegWireSpeedLow; /* 28h */ 1337 U32 NegWireSpeedHigh; /* 2Ch */ 1338 } fCONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1, 1339 LANPage1_t, MPI_POINTER pLANPage1_t; 1340 1341 #define MPI_LAN_PAGE1_PAGEVERSION (0x03) 1342 1343 #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00) 1344 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01) 1345 1346 #endif 1347 1348