1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2000-2005, LSI Logic Corporation and its contributors. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * substantially similar to the "NO WARRANTY" disclaimer below 13 * ("Disclaimer") and any redistribution must be conditioned upon including 14 * a substantially similar Disclaimer requirement for further binary 15 * redistribution. 16 * 3. Neither the name of the LSI Logic Corporation nor the names of its 17 * contributors may be used to endorse or promote products derived from 18 * this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT 30 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * Name: mpi_cnfg.h 33 * Title: MPI Config message, structures, and Pages 34 * Creation Date: July 27, 2000 35 * 36 * mpi_cnfg.h Version: 01.05.11 37 * 38 * Version History 39 * --------------- 40 * 41 * Date Version Description 42 * -------- -------- ------------------------------------------------------ 43 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 44 * 06-06-00 01.00.01 Update version number for 1.0 release. 45 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages. 46 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2 47 * fields to FC_DEVICE_0 page, updated the page version. 48 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in 49 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages 50 * and updated the page versions. 51 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1 52 * page and updated the page version. 53 * Added Information field and _INFO_PARAMS_NEGOTIATED 54 * definitionto SCSI_DEVICE_0 page. 55 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the 56 * page version. 57 * Added BucketsRemaining to LAN_1 page, redefined the 58 * state values, and updated the page version. 59 * Revised bus width definitions in SCSI_PORT_0, 60 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages. 61 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page 62 * version. 63 * Moved FC_DEVICE_0 PageAddress description to spec. 64 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field 65 * widths in IOC_0 page and updated the page version. 66 * 11-02-00 01.01.01 Original release for post 1.0 work 67 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI 68 * Port Page 2, FC Port Page 4, FC Port Page 5 69 * 11-15-00 01.01.02 Interim changes to match proposals 70 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01. 71 * 12-05-00 01.01.04 Modified config page actions. 72 * 01-09-01 01.01.05 Added defines for page address formats. 73 * Data size for Manufacturing pages 2 and 3 no longer 74 * defined here. 75 * Io Unit Page 2 size is fixed at 4 adapters and some 76 * flags were changed. 77 * SCSI Port Page 2 Device Settings modified. 78 * New fields added to FC Port Page 0 and some flags 79 * cleaned up. 80 * Removed impedance flash from FC Port Page 1. 81 * Added FC Port pages 6 and 7. 82 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0. 83 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique. 84 * Added some LinkType defines for FcPortPage0. 85 * 02-20-01 01.01.08 Started using MPI_POINTER. 86 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with 87 * MPI_CONFIG_PAGETYPE_RAID_VOLUME. 88 * Added definitions and structures for IOC Page 2 and 89 * RAID Volume Page 2. 90 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9. 91 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID. 92 * Added VendorId and ProductRevLevel fields to 93 * RAIDVOL2_IM_PHYS_ID struct. 94 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_ 95 * defines to make them compatible to MPI version 1.0. 96 * Added structure offset comments. 97 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and 98 * removed some obsolete ones. 99 * Added IO Unit Page 3. 100 * Modified defines for Scsi Port Page 2. 101 * Modified RAID Volume Pages. 102 * 08-08-01 01.02.01 Original release for v1.2 work. 103 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct. 104 * Added defines for the SEP bits in RVP2 VolumeSettings. 105 * Modified the DeviceSettings field in RVP2 to use the 106 * proper structure. 107 * Added defines for SES, SAF-TE, and cross channel for 108 * IOCPage2 CapabilitiesFlags. 109 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE. 110 * Removed define for 111 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE. 112 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT. 113 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035. 114 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY 115 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY. 116 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS, 117 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and 118 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and 119 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED. 120 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED 121 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED. 122 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1. 123 * Added rejected bits to SCSI Device Page 0 Information. 124 * Increased size of ALPA array in FC Port Page 2 by one 125 * and removed a one byte reserved field. 126 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in 127 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering. 128 * Added structures for Manufacturing Page 4, IO Unit 129 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and 130 * RAID PhysDisk Page 0. 131 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK. 132 * Modified some of the new defines to make them 32 133 * character unique. 134 * Modified how variable length pages (arrays) are defined. 135 * Added generic defines for hot spare pools and RAID 136 * volume types. 137 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR. 138 * 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with 139 * related define, and bumped the page version define. 140 * 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a 141 * reserved byte and added a define. 142 * Added define for 143 * MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE. 144 * Added new config page: CONFIG_PAGE_IOC_5. 145 * Added MaxAliases, MaxHardAliases, and NumCurrentAliases 146 * fields to CONFIG_PAGE_FC_PORT_0. 147 * Added AltConnector and NumRequestedAliases fields to 148 * CONFIG_PAGE_FC_PORT_1. 149 * Added new config page: CONFIG_PAGE_FC_PORT_10. 150 * 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines. 151 * Added additional MPI_SCSIDEVPAGE0_NP_ defines. 152 * Added more MPI_SCSIDEVPAGE1_RP_ defines. 153 * Added define for 154 * MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE. 155 * Added new config page: CONFIG_PAGE_SCSI_DEVICE_3. 156 * Modified MPI_FCPORTPAGE5_FLAGS_ defines. 157 * 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define. 158 * 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0. 159 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1. 160 * Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0. 161 * 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for 162 * CONFIG_PAGE_FC_PORT_1. 163 * Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable 164 * an alias. 165 * Added more device id defines. 166 * 06-26-03 01.02.12 Added MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID define. 167 * Added TargetConfig and IDConfig fields to 168 * CONFIG_PAGE_SCSI_PORT_1. 169 * Added more PortFlags defines for CONFIG_PAGE_SCSI_PORT_2 170 * to control DV. 171 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1. 172 * In CONFIG_PAGE_FC_DEVICE_0, replaced Reserved1 field 173 * with ADISCHardALPA. 174 * Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define. 175 * 01-16-04 01.02.13 Added InitiatorDeviceTimeout and InitiatorIoPendTimeout 176 * fields and related defines to CONFIG_PAGE_FC_PORT_1. 177 * Added define for 178 * MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK. 179 * Added new fields to the substructures of 180 * CONFIG_PAGE_FC_PORT_10. 181 * 04-29-04 01.02.14 Added define for IDP bit for CONFIG_PAGE_SCSI_PORT_0, 182 * CONFIG_PAGE_SCSI_DEVICE_0, and 183 * CONFIG_PAGE_SCSI_DEVICE_1. Also bumped Page Version for 184 * these pages. 185 * 05-11-04 01.03.01 Added structure for CONFIG_PAGE_INBAND_0. 186 * 08-19-04 01.05.01 Modified MSG_CONFIG request to support extended config 187 * pages. 188 * Added a new structure for extended config page header. 189 * Added new extended config pages types and structures for 190 * SAS IO Unit, SAS Expander, SAS Device, and SAS PHY. 191 * Replaced a reserved byte in CONFIG_PAGE_MANUFACTURING_4 192 * to add a Flags field. 193 * Two new Manufacturing config pages (5 and 6). 194 * Two new bits defined for IO Unit Page 1 Flags field. 195 * Modified CONFIG_PAGE_IO_UNIT_2 to add three new fields 196 * to specify the BIOS boot device. 197 * Four new Flags bits defined for IO Unit Page 2. 198 * Added IO Unit Page 4. 199 * Added EEDP Flags settings to IOC Page 1. 200 * Added new BIOS Page 1 config page. 201 * 10-05-04 01.05.02 Added define for 202 * MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE. 203 * Added new Flags field to CONFIG_PAGE_MANUFACTURING_5 and 204 * associated defines. 205 * Added more defines for SAS IO Unit Page 0 206 * DiscoveryStatus field. 207 * Added define for MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK 208 * and MPI_SAS_IOUNIT0_DS_TABLE_LINK. 209 * Added defines for Physical Mapping Modes to SAS IO Unit 210 * Page 2. 211 * Added define for 212 * MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH. 213 * 10-27-04 01.05.03 Added defines for new SAS PHY page addressing mode. 214 * Added defines for MaxTargetSpinUp to BIOS Page 1. 215 * Added 5 new ControlFlags defines for SAS IO Unit 216 * Page 1. 217 * Added MaxNumPhysicalMappedIDs field to SAS IO Unit 218 * Page 2. 219 * Added AccessStatus field to SAS Device Page 0 and added 220 * new Flags bits for supported SATA features. 221 * 12-07-04 01.05.04 Added config page structures for BIOS Page 2, RAID 222 * Volume Page 1, and RAID Physical Disk Page 1. 223 * Replaced IO Unit Page 1 BootTargetID,BootBus, and 224 * BootAdapterNum with reserved field. 225 * Added DataScrubRate and ResyncRate to RAID Volume 226 * Page 0. 227 * Added MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT 228 * define. 229 * 12-09-04 01.05.05 Added Target Mode Large CDB Enable to FC Port Page 1 230 * Flags field. 231 * Added Auto Port Config flag define for SAS IOUNIT 232 * Page 1 ControlFlags. 233 * Added Disabled bad Phy define to Expander Page 1 234 * Discovery Info field. 235 * Added SAS/SATA device support to SAS IOUnit Page 1 236 * ControlFlags. 237 * Added Unsupported device to SAS Dev Page 0 Flags field 238 * Added disable use SATA Hash Address for SAS IOUNIT 239 * page 1 in ControlFields. 240 * 01-15-05 01.05.06 Added defaults for data scrub rate and resync rate to 241 * Manufacturing Page 4. 242 * Added new defines for BIOS Page 1 IOCSettings field. 243 * Added ExtDiskIdentifier field to RAID Physical Disk 244 * Page 0. 245 * Added new defines for SAS IO Unit Page 1 ControlFlags 246 * and to SAS Device Page 0 Flags to control SATA devices. 247 * Added defines and structures for the new Log Page 0, a 248 * new type of configuration page. 249 * 02-09-05 01.05.07 Added InactiveStatus field to RAID Volume Page 0. 250 * Added WWID field to RAID Volume Page 1. 251 * Added PhysicalPort field to SAS Expander pages 0 and 1. 252 * 03-11-05 01.05.08 Removed the EEDP flags from IOC Page 1. 253 * Added Enclosure/Slot boot device format to BIOS Page 2. 254 * New status value for RAID Volume Page 0 VolumeStatus 255 * (VolumeState subfield). 256 * New value for RAID Physical Page 0 InactiveStatus. 257 * Added Inactive Volume Member flag RAID Physical Disk 258 * Page 0 PhysDiskStatus field. 259 * New physical mapping mode in SAS IO Unit Page 2. 260 * Added CONFIG_PAGE_SAS_ENCLOSURE_0. 261 * Added Slot and Enclosure fields to SAS Device Page 0. 262 * 06-24-05 01.05.09 Added EEDP defines to IOC Page 1. 263 * Added more RAID type defines to IOC Page 2. 264 * Added Port Enable Delay settings to BIOS Page 1. 265 * Added Bad Block Table Full define to RAID Volume Page 0. 266 * Added Previous State defines to RAID Physical Disk 267 * Page 0. 268 * Added Max Sata Targets define for DiscoveryStatus field 269 * of SAS IO Unit Page 0. 270 * Added Device Self Test to Control Flags of SAS IO Unit 271 * Page 1. 272 * Added Direct Attach Starting Slot Number define for SAS 273 * IO Unit Page 2. 274 * Added new fields in SAS Device Page 2 for enclosure 275 * mapping. 276 * Added OwnerDevHandle and Flags field to SAS PHY Page 0. 277 * Added IOC GPIO Flags define to SAS Enclosure Page 0. 278 * Fixed the value for MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT. 279 * 08-03-05 01.05.10 Removed ISDataScrubRate and ISResyncRate from 280 * Manufacturing Page 4. 281 * Added MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE bit. 282 * Added NumDevsPerEnclosure field to SAS IO Unit page 2. 283 * Added MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP 284 * define. 285 * Added EnclosureHandle field to SAS Expander page 0. 286 * Removed redundant NumTableEntriesProg field from SAS 287 * Expander Page 1. 288 * 08-30-05 01.05.11 Added DeviceID for FC949E and changed the DeviceID for 289 * SAS1078. 290 * Added more defines for Manufacturing Page 4 Flags field. 291 * Added more defines for IOCSettings and added 292 * ExpanderSpinup field to Bios Page 1. 293 * Added postpone SATA Init bit to SAS IO Unit Page 1 294 * ControlFlags. 295 * Changed LogEntry format for Log Page 0. 296 * -------------------------------------------------------------------------- 297 */ 298 299 #ifndef MPI_CNFG_H 300 #define MPI_CNFG_H 301 302 303 /***************************************************************************** 304 * 305 * C o n f i g M e s s a g e a n d S t r u c t u r e s 306 * 307 *****************************************************************************/ 308 309 typedef struct _CONFIG_PAGE_HEADER 310 { 311 U8 PageVersion; /* 00h */ 312 U8 PageLength; /* 01h */ 313 U8 PageNumber; /* 02h */ 314 U8 PageType; /* 03h */ 315 } CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER, 316 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t; 317 318 typedef union _CONFIG_PAGE_HEADER_UNION 319 { 320 ConfigPageHeader_t Struct; 321 U8 Bytes[4]; 322 U16 Word16[2]; 323 U32 Word32; 324 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion, 325 CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION; 326 327 typedef struct _CONFIG_EXTENDED_PAGE_HEADER 328 { 329 U8 PageVersion; /* 00h */ 330 U8 Reserved1; /* 01h */ 331 U8 PageNumber; /* 02h */ 332 U8 PageType; /* 03h */ 333 U16 ExtPageLength; /* 04h */ 334 U8 ExtPageType; /* 06h */ 335 U8 Reserved2; /* 07h */ 336 } CONFIG_EXTENDED_PAGE_HEADER, MPI_POINTER PTR_CONFIG_EXTENDED_PAGE_HEADER, 337 ConfigExtendedPageHeader_t, MPI_POINTER pConfigExtendedPageHeader_t; 338 339 340 341 /**************************************************************************** 342 * PageType field values 343 ****************************************************************************/ 344 #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00) 345 #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10) 346 #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20) 347 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30) 348 #define MPI_CONFIG_PAGEATTR_MASK (0xF0) 349 350 #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00) 351 #define MPI_CONFIG_PAGETYPE_IOC (0x01) 352 #define MPI_CONFIG_PAGETYPE_BIOS (0x02) 353 #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03) 354 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04) 355 #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05) 356 #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06) 357 #define MPI_CONFIG_PAGETYPE_LAN (0x07) 358 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 359 #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09) 360 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 361 #define MPI_CONFIG_PAGETYPE_INBAND (0x0B) 362 #define MPI_CONFIG_PAGETYPE_EXTENDED (0x0F) 363 #define MPI_CONFIG_PAGETYPE_MASK (0x0F) 364 365 #define MPI_CONFIG_TYPENUM_MASK (0x0FFF) 366 367 368 /**************************************************************************** 369 * ExtPageType field values 370 ****************************************************************************/ 371 #define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 372 #define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 373 #define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 374 #define MPI_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 375 #define MPI_CONFIG_EXTPAGETYPE_LOG (0x14) 376 #define MPI_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 377 378 379 /**************************************************************************** 380 * PageAddress field values 381 ****************************************************************************/ 382 #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF) 383 384 #define MPI_SCSI_DEVICE_FORM_MASK (0xF0000000) 385 #define MPI_SCSI_DEVICE_FORM_BUS_TID (0x00000000) 386 #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF) 387 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0) 388 #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00) 389 #define MPI_SCSI_DEVICE_BUS_SHIFT (8) 390 #define MPI_SCSI_DEVICE_FORM_TARGET_MODE (0x10000000) 391 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_MASK (0x000000FF) 392 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_SHIFT (0) 393 #define MPI_SCSI_DEVICE_TM_BUS_MASK (0x0000FF00) 394 #define MPI_SCSI_DEVICE_TM_BUS_SHIFT (8) 395 #define MPI_SCSI_DEVICE_TM_INIT_ID_MASK (0x00FF0000) 396 #define MPI_SCSI_DEVICE_TM_INIT_ID_SHIFT (16) 397 398 #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000) 399 #define MPI_FC_PORT_PGAD_PORT_SHIFT (28) 400 #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000) 401 #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000) 402 #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF) 403 #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0) 404 405 #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000) 406 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28) 407 #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000) 408 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000) 409 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000) 410 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28) 411 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF) 412 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0) 413 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000) 414 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 415 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8) 416 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 417 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0) 418 419 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 420 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0) 421 422 #define MPI_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 423 #define MPI_SAS_EXPAND_PGAD_FORM_SHIFT (28) 424 #define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 425 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x00000001) 426 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE (0x00000002) 427 #define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE (0x0000FFFF) 428 #define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE (0) 429 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY (0x00FF0000) 430 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY (16) 431 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE (0x0000FFFF) 432 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE (0) 433 #define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE (0x0000FFFF) 434 #define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE (0) 435 436 #define MPI_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 437 #define MPI_SAS_DEVICE_PGAD_FORM_SHIFT (28) 438 #define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 439 #define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID (0x00000001) 440 #define MPI_SAS_DEVICE_PGAD_FORM_HANDLE (0x00000002) 441 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK (0x0000FFFF) 442 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT (0) 443 #define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 444 #define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT (8) 445 #define MPI_SAS_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 446 #define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT (0) 447 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK (0x0000FFFF) 448 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT (0) 449 450 #define MPI_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 451 #define MPI_SAS_PHY_PGAD_FORM_SHIFT (28) 452 #define MPI_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x0) 453 #define MPI_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x1) 454 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 455 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (0) 456 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 457 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_SHIFT (0) 458 459 #define MPI_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 460 #define MPI_SAS_ENCLOS_PGAD_FORM_SHIFT (28) 461 #define MPI_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 462 #define MPI_SAS_ENCLOS_PGAD_FORM_HANDLE (0x00000001) 463 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_MASK (0x0000FFFF) 464 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_SHIFT (0) 465 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_MASK (0x0000FFFF) 466 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_SHIFT (0) 467 468 469 470 /**************************************************************************** 471 * Config Request Message 472 ****************************************************************************/ 473 typedef struct _MSG_CONFIG 474 { 475 U8 Action; /* 00h */ 476 U8 Reserved; /* 01h */ 477 U8 ChainOffset; /* 02h */ 478 U8 Function; /* 03h */ 479 U16 ExtPageLength; /* 04h */ 480 U8 ExtPageType; /* 06h */ 481 U8 MsgFlags; /* 07h */ 482 U32 MsgContext; /* 08h */ 483 U8 Reserved2[8]; /* 0Ch */ 484 CONFIG_PAGE_HEADER Header; /* 14h */ 485 U32 PageAddress; /* 18h */ 486 SGE_IO_UNION PageBufferSGE; /* 1Ch */ 487 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG, 488 Config_t, MPI_POINTER pConfig_t; 489 490 491 /**************************************************************************** 492 * Action field values 493 ****************************************************************************/ 494 #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00) 495 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 496 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 497 #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03) 498 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 499 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 500 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 501 502 503 /* Config Reply Message */ 504 typedef struct _MSG_CONFIG_REPLY 505 { 506 U8 Action; /* 00h */ 507 U8 Reserved; /* 01h */ 508 U8 MsgLength; /* 02h */ 509 U8 Function; /* 03h */ 510 U16 ExtPageLength; /* 04h */ 511 U8 ExtPageType; /* 06h */ 512 U8 MsgFlags; /* 07h */ 513 U32 MsgContext; /* 08h */ 514 U8 Reserved2[2]; /* 0Ch */ 515 U16 IOCStatus; /* 0Eh */ 516 U32 IOCLogInfo; /* 10h */ 517 CONFIG_PAGE_HEADER Header; /* 14h */ 518 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY, 519 ConfigReply_t, MPI_POINTER pConfigReply_t; 520 521 522 523 /***************************************************************************** 524 * 525 * C o n f i g u r a t i o n P a g e s 526 * 527 *****************************************************************************/ 528 529 /**************************************************************************** 530 * Manufacturing Config pages 531 ****************************************************************************/ 532 #define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000) 533 /* Fibre Channel */ 534 #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621) 535 #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624) 536 #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622) 537 #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628) 538 #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626) 539 #define MPI_MANUFACTPAGE_DEVICEID_FC939X (0x0642) 540 #define MPI_MANUFACTPAGE_DEVICEID_FC949X (0x0640) 541 #define MPI_MANUFACTPAGE_DEVICEID_FC949E (0x0646) 542 /* SCSI */ 543 #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030) 544 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031) 545 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032) 546 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033) 547 #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040) 548 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041) 549 /* SAS */ 550 #define MPI_MANUFACTPAGE_DEVID_SAS1064 (0x0050) 551 #define MPI_MANUFACTPAGE_DEVID_SAS1064A (0x005C) 552 #define MPI_MANUFACTPAGE_DEVID_SAS1064E (0x0056) 553 #define MPI_MANUFACTPAGE_DEVID_SAS1066 (0x005E) 554 #define MPI_MANUFACTPAGE_DEVID_SAS1066E (0x005A) 555 #define MPI_MANUFACTPAGE_DEVID_SAS1068 (0x0054) 556 #define MPI_MANUFACTPAGE_DEVID_SAS1068E (0x0058) 557 #define MPI_MANUFACTPAGE_DEVID_SAS1078 (0x0062) 558 559 560 typedef struct _CONFIG_PAGE_MANUFACTURING_0 561 { 562 CONFIG_PAGE_HEADER Header; /* 00h */ 563 U8 ChipName[16]; /* 04h */ 564 U8 ChipRevision[8]; /* 14h */ 565 U8 BoardName[16]; /* 1Ch */ 566 U8 BoardAssembly[16]; /* 2Ch */ 567 U8 BoardTracerNumber[16]; /* 3Ch */ 568 569 } CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0, 570 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t; 571 572 #define MPI_MANUFACTURING0_PAGEVERSION (0x00) 573 574 575 typedef struct _CONFIG_PAGE_MANUFACTURING_1 576 { 577 CONFIG_PAGE_HEADER Header; /* 00h */ 578 U8 VPD[256]; /* 04h */ 579 } CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1, 580 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t; 581 582 #define MPI_MANUFACTURING1_PAGEVERSION (0x00) 583 584 585 typedef struct _MPI_CHIP_REVISION_ID 586 { 587 U16 DeviceID; /* 00h */ 588 U8 PCIRevisionID; /* 02h */ 589 U8 Reserved; /* 03h */ 590 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID, 591 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t; 592 593 594 /* 595 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 596 * one and check Header.PageLength at runtime. 597 */ 598 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS 599 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 600 #endif 601 602 typedef struct _CONFIG_PAGE_MANUFACTURING_2 603 { 604 CONFIG_PAGE_HEADER Header; /* 00h */ 605 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 606 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */ 607 } CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2, 608 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t; 609 610 #define MPI_MANUFACTURING2_PAGEVERSION (0x00) 611 612 613 /* 614 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 615 * one and check Header.PageLength at runtime. 616 */ 617 #ifndef MPI_MAN_PAGE_3_INFO_WORDS 618 #define MPI_MAN_PAGE_3_INFO_WORDS (1) 619 #endif 620 621 typedef struct _CONFIG_PAGE_MANUFACTURING_3 622 { 623 CONFIG_PAGE_HEADER Header; /* 00h */ 624 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 625 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */ 626 } CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3, 627 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t; 628 629 #define MPI_MANUFACTURING3_PAGEVERSION (0x00) 630 631 632 typedef struct _CONFIG_PAGE_MANUFACTURING_4 633 { 634 CONFIG_PAGE_HEADER Header; /* 00h */ 635 U32 Reserved1; /* 04h */ 636 U8 InfoOffset0; /* 08h */ 637 U8 InfoSize0; /* 09h */ 638 U8 InfoOffset1; /* 0Ah */ 639 U8 InfoSize1; /* 0Bh */ 640 U8 InquirySize; /* 0Ch */ 641 U8 Flags; /* 0Dh */ 642 U16 Reserved2; /* 0Eh */ 643 U8 InquiryData[56]; /* 10h */ 644 U32 ISVolumeSettings; /* 48h */ 645 U32 IMEVolumeSettings; /* 4Ch */ 646 U32 IMVolumeSettings; /* 50h */ 647 U32 Reserved3; /* 54h */ 648 U32 Reserved4; /* 58h */ 649 U32 Reserved5; /* 5Ch */ 650 U8 IMEDataScrubRate; /* 60h */ 651 U8 IMEResyncRate; /* 61h */ 652 U16 Reserved6; /* 62h */ 653 U8 IMDataScrubRate; /* 64h */ 654 U8 IMResyncRate; /* 65h */ 655 U16 Reserved7; /* 66h */ 656 U32 Reserved8; /* 68h */ 657 U32 Reserved9; /* 6Ch */ 658 } CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4, 659 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t; 660 661 #define MPI_MANUFACTURING4_PAGEVERSION (0x03) 662 663 /* defines for the Flags field */ 664 #define MPI_MANPAGE4_IME_DISABLE (0x20) 665 #define MPI_MANPAGE4_IM_DISABLE (0x10) 666 #define MPI_MANPAGE4_IS_DISABLE (0x08) 667 #define MPI_MANPAGE4_IR_MODEPAGE8_DISABLE (0x04) 668 #define MPI_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x02) 669 #define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA (0x01) 670 671 672 typedef struct _CONFIG_PAGE_MANUFACTURING_5 673 { 674 CONFIG_PAGE_HEADER Header; /* 00h */ 675 U64 BaseWWID; /* 04h */ 676 U8 Flags; /* 0Ch */ 677 U8 Reserved1; /* 0Dh */ 678 U16 Reserved2; /* 0Eh */ 679 } CONFIG_PAGE_MANUFACTURING_5, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_5, 680 ManufacturingPage5_t, MPI_POINTER pManufacturingPage5_t; 681 682 #define MPI_MANUFACTURING5_PAGEVERSION (0x01) 683 684 /* defines for the Flags field */ 685 #define MPI_MANPAGE5_TWO_WWID_PER_PHY (0x01) 686 687 688 typedef struct _CONFIG_PAGE_MANUFACTURING_6 689 { 690 CONFIG_PAGE_HEADER Header; /* 00h */ 691 U32 ProductSpecificInfo;/* 04h */ 692 } CONFIG_PAGE_MANUFACTURING_6, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_6, 693 ManufacturingPage6_t, MPI_POINTER pManufacturingPage6_t; 694 695 #define MPI_MANUFACTURING6_PAGEVERSION (0x00) 696 697 698 /**************************************************************************** 699 * IO Unit Config Pages 700 ****************************************************************************/ 701 702 typedef struct _CONFIG_PAGE_IO_UNIT_0 703 { 704 CONFIG_PAGE_HEADER Header; /* 00h */ 705 U64 UniqueValue; /* 04h */ 706 } CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0, 707 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t; 708 709 #define MPI_IOUNITPAGE0_PAGEVERSION (0x00) 710 711 712 typedef struct _CONFIG_PAGE_IO_UNIT_1 713 { 714 CONFIG_PAGE_HEADER Header; /* 00h */ 715 U32 Flags; /* 04h */ 716 } CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1, 717 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t; 718 719 #define MPI_IOUNITPAGE1_PAGEVERSION (0x02) 720 721 /* IO Unit Page 1 Flags defines */ 722 #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000) 723 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001) 724 #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002) 725 #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000) 726 #define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 727 #define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING (0x00000020) 728 #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040) 729 #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080) 730 #define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 731 #define MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE (0x00000200) 732 733 typedef struct _MPI_ADAPTER_INFO 734 { 735 U8 PciBusNumber; /* 00h */ 736 U8 PciDeviceAndFunctionNumber; /* 01h */ 737 U16 AdapterFlags; /* 02h */ 738 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO, 739 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t; 740 741 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 742 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 743 744 typedef struct _CONFIG_PAGE_IO_UNIT_2 745 { 746 CONFIG_PAGE_HEADER Header; /* 00h */ 747 U32 Flags; /* 04h */ 748 U32 BiosVersion; /* 08h */ 749 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */ 750 U32 Reserved1; /* 1Ch */ 751 } CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2, 752 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t; 753 754 #define MPI_IOUNITPAGE2_PAGEVERSION (0x02) 755 756 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002) 757 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004) 758 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008) 759 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010) 760 761 #define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 762 #define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 763 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY (0x00000020) 764 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 765 766 767 /* 768 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 769 * one and check Header.PageLength at runtime. 770 */ 771 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX 772 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 773 #endif 774 775 typedef struct _CONFIG_PAGE_IO_UNIT_3 776 { 777 CONFIG_PAGE_HEADER Header; /* 00h */ 778 U8 GPIOCount; /* 04h */ 779 U8 Reserved1; /* 05h */ 780 U16 Reserved2; /* 06h */ 781 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */ 782 } CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3, 783 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t; 784 785 #define MPI_IOUNITPAGE3_PAGEVERSION (0x01) 786 787 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC) 788 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 789 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00) 790 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01) 791 792 793 typedef struct _CONFIG_PAGE_IO_UNIT_4 794 { 795 CONFIG_PAGE_HEADER Header; /* 00h */ 796 U32 Reserved1; /* 04h */ 797 SGE_SIMPLE_UNION FWImageSGE; /* 08h */ 798 } CONFIG_PAGE_IO_UNIT_4, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_4, 799 IOUnitPage4_t, MPI_POINTER pIOUnitPage4_t; 800 801 #define MPI_IOUNITPAGE4_PAGEVERSION (0x00) 802 803 804 /**************************************************************************** 805 * IOC Config Pages 806 ****************************************************************************/ 807 808 typedef struct _CONFIG_PAGE_IOC_0 809 { 810 CONFIG_PAGE_HEADER Header; /* 00h */ 811 U32 TotalNVStore; /* 04h */ 812 U32 FreeNVStore; /* 08h */ 813 U16 VendorID; /* 0Ch */ 814 U16 DeviceID; /* 0Eh */ 815 U8 RevisionID; /* 10h */ 816 U8 Reserved[3]; /* 11h */ 817 U32 ClassCode; /* 14h */ 818 U16 SubsystemVendorID; /* 18h */ 819 U16 SubsystemID; /* 1Ah */ 820 } CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0, 821 IOCPage0_t, MPI_POINTER pIOCPage0_t; 822 823 #define MPI_IOCPAGE0_PAGEVERSION (0x01) 824 825 826 typedef struct _CONFIG_PAGE_IOC_1 827 { 828 CONFIG_PAGE_HEADER Header; /* 00h */ 829 U32 Flags; /* 04h */ 830 U32 CoalescingTimeout; /* 08h */ 831 U8 CoalescingDepth; /* 0Ch */ 832 U8 PCISlotNum; /* 0Dh */ 833 U8 Reserved[2]; /* 0Eh */ 834 } CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1, 835 IOCPage1_t, MPI_POINTER pIOCPage1_t; 836 837 #define MPI_IOCPAGE1_PAGEVERSION (0x03) 838 839 /* defines for the Flags field */ 840 #define MPI_IOCPAGE1_EEDP_MODE_MASK (0x07000000) 841 #define MPI_IOCPAGE1_EEDP_MODE_OFF (0x00000000) 842 #define MPI_IOCPAGE1_EEDP_MODE_T10 (0x01000000) 843 #define MPI_IOCPAGE1_EEDP_MODE_LSI_1 (0x02000000) 844 #define MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE (0x00000010) 845 #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001) 846 847 #define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 848 849 850 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL 851 { 852 U8 VolumeID; /* 00h */ 853 U8 VolumeBus; /* 01h */ 854 U8 VolumeIOC; /* 02h */ 855 U8 VolumePageNumber; /* 03h */ 856 U8 VolumeType; /* 04h */ 857 U8 Flags; /* 05h */ 858 U16 Reserved3; /* 06h */ 859 } CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL, 860 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t; 861 862 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */ 863 864 #define MPI_RAID_VOL_TYPE_IS (0x00) 865 #define MPI_RAID_VOL_TYPE_IME (0x01) 866 #define MPI_RAID_VOL_TYPE_IM (0x02) 867 #define MPI_RAID_VOL_TYPE_RAID_5 (0x03) 868 #define MPI_RAID_VOL_TYPE_RAID_6 (0x04) 869 #define MPI_RAID_VOL_TYPE_RAID_10 (0x05) 870 #define MPI_RAID_VOL_TYPE_RAID_50 (0x06) 871 #define MPI_RAID_VOL_TYPE_UNKNOWN (0xFF) 872 873 /* IOC Page 2 Volume Flags values */ 874 875 #define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08) 876 877 /* 878 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 879 * one and check Header.PageLength at runtime. 880 */ 881 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX 882 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1) 883 #endif 884 885 typedef struct _CONFIG_PAGE_IOC_2 886 { 887 CONFIG_PAGE_HEADER Header; /* 00h */ 888 U32 CapabilitiesFlags; /* 04h */ 889 U8 NumActiveVolumes; /* 08h */ 890 U8 MaxVolumes; /* 09h */ 891 U8 NumActivePhysDisks; /* 0Ah */ 892 U8 MaxPhysDisks; /* 0Bh */ 893 CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */ 894 } CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2, 895 IOCPage2_t, MPI_POINTER pIOCPage2_t; 896 897 #define MPI_IOCPAGE2_PAGEVERSION (0x03) 898 899 /* IOC Page 2 Capabilities flags */ 900 901 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001) 902 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002) 903 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004) 904 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_5_SUPPORT (0x00000008) 905 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_6_SUPPORT (0x00000010) 906 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_10_SUPPORT (0x00000020) 907 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_50_SUPPORT (0x00000040) 908 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000) 909 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000) 910 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000) 911 912 913 typedef struct _IOC_3_PHYS_DISK 914 { 915 U8 PhysDiskID; /* 00h */ 916 U8 PhysDiskBus; /* 01h */ 917 U8 PhysDiskIOC; /* 02h */ 918 U8 PhysDiskNum; /* 03h */ 919 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK, 920 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t; 921 922 /* 923 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 924 * one and check Header.PageLength at runtime. 925 */ 926 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX 927 #define MPI_IOC_PAGE_3_PHYSDISK_MAX (1) 928 #endif 929 930 typedef struct _CONFIG_PAGE_IOC_3 931 { 932 CONFIG_PAGE_HEADER Header; /* 00h */ 933 U8 NumPhysDisks; /* 04h */ 934 U8 Reserved1; /* 05h */ 935 U16 Reserved2; /* 06h */ 936 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */ 937 } CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3, 938 IOCPage3_t, MPI_POINTER pIOCPage3_t; 939 940 #define MPI_IOCPAGE3_PAGEVERSION (0x00) 941 942 943 typedef struct _IOC_4_SEP 944 { 945 U8 SEPTargetID; /* 00h */ 946 U8 SEPBus; /* 01h */ 947 U16 Reserved; /* 02h */ 948 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP, 949 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t; 950 951 /* 952 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 953 * one and check Header.PageLength at runtime. 954 */ 955 #ifndef MPI_IOC_PAGE_4_SEP_MAX 956 #define MPI_IOC_PAGE_4_SEP_MAX (1) 957 #endif 958 959 typedef struct _CONFIG_PAGE_IOC_4 960 { 961 CONFIG_PAGE_HEADER Header; /* 00h */ 962 U8 ActiveSEP; /* 04h */ 963 U8 MaxSEP; /* 05h */ 964 U16 Reserved1; /* 06h */ 965 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */ 966 } CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4, 967 IOCPage4_t, MPI_POINTER pIOCPage4_t; 968 969 #define MPI_IOCPAGE4_PAGEVERSION (0x00) 970 971 972 typedef struct _IOC_5_HOT_SPARE 973 { 974 U8 PhysDiskNum; /* 00h */ 975 U8 Reserved; /* 01h */ 976 U8 HotSparePool; /* 02h */ 977 U8 Flags; /* 03h */ 978 } IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE, 979 Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t; 980 981 /* IOC Page 5 HotSpare Flags */ 982 #define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01) 983 984 /* 985 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 986 * one and check Header.PageLength at runtime. 987 */ 988 #ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX 989 #define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1) 990 #endif 991 992 typedef struct _CONFIG_PAGE_IOC_5 993 { 994 CONFIG_PAGE_HEADER Header; /* 00h */ 995 U32 Reserved1; /* 04h */ 996 U8 NumHotSpares; /* 08h */ 997 U8 Reserved2; /* 09h */ 998 U16 Reserved3; /* 0Ah */ 999 IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */ 1000 } CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5, 1001 IOCPage5_t, MPI_POINTER pIOCPage5_t; 1002 1003 #define MPI_IOCPAGE5_PAGEVERSION (0x00) 1004 1005 1006 /**************************************************************************** 1007 * BIOS Config Pages 1008 ****************************************************************************/ 1009 1010 typedef struct _CONFIG_PAGE_BIOS_1 1011 { 1012 CONFIG_PAGE_HEADER Header; /* 00h */ 1013 U32 BiosOptions; /* 04h */ 1014 U32 IOCSettings; /* 08h */ 1015 U32 Reserved1; /* 0Ch */ 1016 U32 DeviceSettings; /* 10h */ 1017 U16 NumberOfDevices; /* 14h */ 1018 U8 ExpanderSpinup; /* 16h */ 1019 U8 Reserved2; /* 17h */ 1020 U16 IOTimeoutBlockDevicesNonRM; /* 18h */ 1021 U16 IOTimeoutSequential; /* 1Ah */ 1022 U16 IOTimeoutOther; /* 1Ch */ 1023 U16 IOTimeoutBlockDevicesRM; /* 1Eh */ 1024 } CONFIG_PAGE_BIOS_1, MPI_POINTER PTR_CONFIG_PAGE_BIOS_1, 1025 BIOSPage1_t, MPI_POINTER pBIOSPage1_t; 1026 1027 #define MPI_BIOSPAGE1_PAGEVERSION (0x03) 1028 1029 /* values for the BiosOptions field */ 1030 #define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE (0x00000400) 1031 #define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE (0x00000200) 1032 #define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE (0x00000100) 1033 #define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1034 1035 /* values for the IOCSettings field */ 1036 #define MPI_BIOSPAGE1_IOCSET_MASK_INITIAL_SPINUP_DELAY (0x0F000000) 1037 #define MPI_BIOSPAGE1_IOCSET_SHIFT_INITIAL_SPINUP_DELAY (24) 1038 1039 #define MPI_BIOSPAGE1_IOCSET_MASK_PORT_ENABLE_DELAY (0x00F00000) 1040 #define MPI_BIOSPAGE1_IOCSET_SHIFT_PORT_ENABLE_DELAY (20) 1041 1042 #define MPI_BIOSPAGE1_IOCSET_AUTO_PORT_ENABLE (0x00080000) 1043 #define MPI_BIOSPAGE1_IOCSET_DIRECT_ATTACH_SPINUP_MODE (0x00040000) 1044 1045 #define MPI_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1046 #define MPI_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1047 #define MPI_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1048 1049 #define MPI_BIOSPAGE1_IOCSET_MASK_MAX_TARGET_SPIN_UP (0x0000F000) 1050 #define MPI_BIOSPAGE1_IOCSET_SHIFT_MAX_TARGET_SPIN_UP (12) 1051 1052 #define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY (0x00000F00) 1053 #define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY (8) 1054 1055 #define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1056 #define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1057 #define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1058 #define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1059 1060 #define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1061 #define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1062 #define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1063 #define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1064 #define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1065 1066 #define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1067 1068 /* values for the DeviceSettings field */ 1069 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1070 #define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1071 #define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1072 #define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1073 1074 /* defines for the ExpanderSpinup field */ 1075 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_MAX_TARGET (0xF0) 1076 #define MPI_BIOSPAGE1_EXPSPINUP_SHIFT_MAX_TARGET (4) 1077 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_DELAY (0x0F) 1078 1079 typedef struct _MPI_BOOT_DEVICE_ADAPTER_ORDER 1080 { 1081 U32 Reserved1; /* 00h */ 1082 U32 Reserved2; /* 04h */ 1083 U32 Reserved3; /* 08h */ 1084 U32 Reserved4; /* 0Ch */ 1085 U32 Reserved5; /* 10h */ 1086 U32 Reserved6; /* 14h */ 1087 U32 Reserved7; /* 18h */ 1088 U32 Reserved8; /* 1Ch */ 1089 U32 Reserved9; /* 20h */ 1090 U32 Reserved10; /* 24h */ 1091 U32 Reserved11; /* 28h */ 1092 U32 Reserved12; /* 2Ch */ 1093 U32 Reserved13; /* 30h */ 1094 U32 Reserved14; /* 34h */ 1095 U32 Reserved15; /* 38h */ 1096 U32 Reserved16; /* 3Ch */ 1097 U32 Reserved17; /* 40h */ 1098 } MPI_BOOT_DEVICE_ADAPTER_ORDER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_ORDER; 1099 1100 typedef struct _MPI_BOOT_DEVICE_ADAPTER_NUMBER 1101 { 1102 U8 TargetID; /* 00h */ 1103 U8 Bus; /* 01h */ 1104 U8 AdapterNumber; /* 02h */ 1105 U8 Reserved1; /* 03h */ 1106 U32 Reserved2; /* 04h */ 1107 U32 Reserved3; /* 08h */ 1108 U32 Reserved4; /* 0Ch */ 1109 U8 LUN[8]; /* 10h */ 1110 U32 Reserved5; /* 18h */ 1111 U32 Reserved6; /* 1Ch */ 1112 U32 Reserved7; /* 20h */ 1113 U32 Reserved8; /* 24h */ 1114 U32 Reserved9; /* 28h */ 1115 U32 Reserved10; /* 2Ch */ 1116 U32 Reserved11; /* 30h */ 1117 U32 Reserved12; /* 34h */ 1118 U32 Reserved13; /* 38h */ 1119 U32 Reserved14; /* 3Ch */ 1120 U32 Reserved15; /* 40h */ 1121 } MPI_BOOT_DEVICE_ADAPTER_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_NUMBER; 1122 1123 typedef struct _MPI_BOOT_DEVICE_PCI_ADDRESS 1124 { 1125 U8 TargetID; /* 00h */ 1126 U8 Bus; /* 01h */ 1127 U16 PCIAddress; /* 02h */ 1128 U32 Reserved1; /* 04h */ 1129 U32 Reserved2; /* 08h */ 1130 U32 Reserved3; /* 0Ch */ 1131 U8 LUN[8]; /* 10h */ 1132 U32 Reserved4; /* 18h */ 1133 U32 Reserved5; /* 1Ch */ 1134 U32 Reserved6; /* 20h */ 1135 U32 Reserved7; /* 24h */ 1136 U32 Reserved8; /* 28h */ 1137 U32 Reserved9; /* 2Ch */ 1138 U32 Reserved10; /* 30h */ 1139 U32 Reserved11; /* 34h */ 1140 U32 Reserved12; /* 38h */ 1141 U32 Reserved13; /* 3Ch */ 1142 U32 Reserved14; /* 40h */ 1143 } MPI_BOOT_DEVICE_PCI_ADDRESS, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_ADDRESS; 1144 1145 typedef struct _MPI_BOOT_DEVICE_SLOT_NUMBER 1146 { 1147 U8 TargetID; /* 00h */ 1148 U8 Bus; /* 01h */ 1149 U8 PCISlotNumber; /* 02h */ 1150 U8 Reserved1; /* 03h */ 1151 U32 Reserved2; /* 04h */ 1152 U32 Reserved3; /* 08h */ 1153 U32 Reserved4; /* 0Ch */ 1154 U8 LUN[8]; /* 10h */ 1155 U32 Reserved5; /* 18h */ 1156 U32 Reserved6; /* 1Ch */ 1157 U32 Reserved7; /* 20h */ 1158 U32 Reserved8; /* 24h */ 1159 U32 Reserved9; /* 28h */ 1160 U32 Reserved10; /* 2Ch */ 1161 U32 Reserved11; /* 30h */ 1162 U32 Reserved12; /* 34h */ 1163 U32 Reserved13; /* 38h */ 1164 U32 Reserved14; /* 3Ch */ 1165 U32 Reserved15; /* 40h */ 1166 } MPI_BOOT_DEVICE_PCI_SLOT_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_SLOT_NUMBER; 1167 1168 typedef struct _MPI_BOOT_DEVICE_FC_WWN 1169 { 1170 U64 WWPN; /* 00h */ 1171 U32 Reserved1; /* 08h */ 1172 U32 Reserved2; /* 0Ch */ 1173 U8 LUN[8]; /* 10h */ 1174 U32 Reserved3; /* 18h */ 1175 U32 Reserved4; /* 1Ch */ 1176 U32 Reserved5; /* 20h */ 1177 U32 Reserved6; /* 24h */ 1178 U32 Reserved7; /* 28h */ 1179 U32 Reserved8; /* 2Ch */ 1180 U32 Reserved9; /* 30h */ 1181 U32 Reserved10; /* 34h */ 1182 U32 Reserved11; /* 38h */ 1183 U32 Reserved12; /* 3Ch */ 1184 U32 Reserved13; /* 40h */ 1185 } MPI_BOOT_DEVICE_FC_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_FC_WWN; 1186 1187 typedef struct _MPI_BOOT_DEVICE_SAS_WWN 1188 { 1189 U64 SASAddress; /* 00h */ 1190 U32 Reserved1; /* 08h */ 1191 U32 Reserved2; /* 0Ch */ 1192 U8 LUN[8]; /* 10h */ 1193 U32 Reserved3; /* 18h */ 1194 U32 Reserved4; /* 1Ch */ 1195 U32 Reserved5; /* 20h */ 1196 U32 Reserved6; /* 24h */ 1197 U32 Reserved7; /* 28h */ 1198 U32 Reserved8; /* 2Ch */ 1199 U32 Reserved9; /* 30h */ 1200 U32 Reserved10; /* 34h */ 1201 U32 Reserved11; /* 38h */ 1202 U32 Reserved12; /* 3Ch */ 1203 U32 Reserved13; /* 40h */ 1204 } MPI_BOOT_DEVICE_SAS_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_SAS_WWN; 1205 1206 typedef struct _MPI_BOOT_DEVICE_ENCLOSURE_SLOT 1207 { 1208 U64 EnclosureLogicalID; /* 00h */ 1209 U32 Reserved1; /* 08h */ 1210 U32 Reserved2; /* 0Ch */ 1211 U8 LUN[8]; /* 10h */ 1212 U16 SlotNumber; /* 18h */ 1213 U16 Reserved3; /* 1Ah */ 1214 U32 Reserved4; /* 1Ch */ 1215 U32 Reserved5; /* 20h */ 1216 U32 Reserved6; /* 24h */ 1217 U32 Reserved7; /* 28h */ 1218 U32 Reserved8; /* 2Ch */ 1219 U32 Reserved9; /* 30h */ 1220 U32 Reserved10; /* 34h */ 1221 U32 Reserved11; /* 38h */ 1222 U32 Reserved12; /* 3Ch */ 1223 U32 Reserved13; /* 40h */ 1224 } MPI_BOOT_DEVICE_ENCLOSURE_SLOT, 1225 MPI_POINTER PTR_MPI_BOOT_DEVICE_ENCLOSURE_SLOT; 1226 1227 typedef union _MPI_BIOSPAGE2_BOOT_DEVICE 1228 { 1229 MPI_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1230 MPI_BOOT_DEVICE_ADAPTER_NUMBER AdapterNumber; 1231 MPI_BOOT_DEVICE_PCI_ADDRESS PCIAddress; 1232 MPI_BOOT_DEVICE_PCI_SLOT_NUMBER PCISlotNumber; 1233 MPI_BOOT_DEVICE_FC_WWN FcWwn; 1234 MPI_BOOT_DEVICE_SAS_WWN SasWwn; 1235 MPI_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1236 } MPI_BIOSPAGE2_BOOT_DEVICE, MPI_POINTER PTR_MPI_BIOSPAGE2_BOOT_DEVICE; 1237 1238 typedef struct _CONFIG_PAGE_BIOS_2 1239 { 1240 CONFIG_PAGE_HEADER Header; /* 00h */ 1241 U32 Reserved1; /* 04h */ 1242 U32 Reserved2; /* 08h */ 1243 U32 Reserved3; /* 0Ch */ 1244 U32 Reserved4; /* 10h */ 1245 U32 Reserved5; /* 14h */ 1246 U32 Reserved6; /* 18h */ 1247 U8 BootDeviceForm; /* 1Ch */ 1248 U8 Reserved7; /* 1Dh */ 1249 U16 Reserved8; /* 1Eh */ 1250 MPI_BIOSPAGE2_BOOT_DEVICE BootDevice; /* 20h */ 1251 } CONFIG_PAGE_BIOS_2, MPI_POINTER PTR_CONFIG_PAGE_BIOS_2, 1252 BIOSPage2_t, MPI_POINTER pBIOSPage2_t; 1253 1254 #define MPI_BIOSPAGE2_PAGEVERSION (0x01) 1255 1256 #define MPI_BIOSPAGE2_FORM_MASK (0x0F) 1257 #define MPI_BIOSPAGE2_FORM_ADAPTER_ORDER (0x00) 1258 #define MPI_BIOSPAGE2_FORM_ADAPTER_NUMBER (0x01) 1259 #define MPI_BIOSPAGE2_FORM_PCI_ADDRESS (0x02) 1260 #define MPI_BIOSPAGE2_FORM_PCI_SLOT_NUMBER (0x03) 1261 #define MPI_BIOSPAGE2_FORM_FC_WWN (0x04) 1262 #define MPI_BIOSPAGE2_FORM_SAS_WWN (0x05) 1263 #define MPI_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1264 1265 1266 /**************************************************************************** 1267 * SCSI Port Config Pages 1268 ****************************************************************************/ 1269 1270 typedef struct _CONFIG_PAGE_SCSI_PORT_0 1271 { 1272 CONFIG_PAGE_HEADER Header; /* 00h */ 1273 U32 Capabilities; /* 04h */ 1274 U32 PhysicalInterface; /* 08h */ 1275 } CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0, 1276 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t; 1277 1278 #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x02) 1279 1280 #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001) 1281 #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002) 1282 #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004) 1283 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 1284 #define MPI_SCSIPORTPAGE0_SYNC_ASYNC (0x00) 1285 #define MPI_SCSIPORTPAGE0_SYNC_5 (0x32) 1286 #define MPI_SCSIPORTPAGE0_SYNC_10 (0x19) 1287 #define MPI_SCSIPORTPAGE0_SYNC_20 (0x0C) 1288 #define MPI_SCSIPORTPAGE0_SYNC_33_33 (0x0B) 1289 #define MPI_SCSIPORTPAGE0_SYNC_40 (0x0A) 1290 #define MPI_SCSIPORTPAGE0_SYNC_80 (0x09) 1291 #define MPI_SCSIPORTPAGE0_SYNC_160 (0x08) 1292 #define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN (0xFF) 1293 1294 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD (8) 1295 #define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap) \ 1296 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK) \ 1297 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD \ 1298 ) 1299 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 1300 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET (16) 1301 #define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap) \ 1302 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK) \ 1303 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET \ 1304 ) 1305 #define MPI_SCSIPORTPAGE0_CAP_IDP (0x08000000) 1306 #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000) 1307 #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000) 1308 1309 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003) 1310 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01) 1311 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02) 1312 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03) 1313 #define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000) 1314 #define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24) 1315 #define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE) 1316 #define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF) 1317 1318 1319 typedef struct _CONFIG_PAGE_SCSI_PORT_1 1320 { 1321 CONFIG_PAGE_HEADER Header; /* 00h */ 1322 U32 Configuration; /* 04h */ 1323 U32 OnBusTimerValue; /* 08h */ 1324 U8 TargetConfig; /* 0Ch */ 1325 U8 Reserved1; /* 0Dh */ 1326 U16 IDConfig; /* 0Eh */ 1327 } CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1, 1328 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t; 1329 1330 #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03) 1331 1332 /* Configuration values */ 1333 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF) 1334 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000) 1335 #define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID (16) 1336 1337 /* TargetConfig values */ 1338 #define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01) 1339 #define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG (0x02) 1340 1341 1342 typedef struct _MPI_DEVICE_INFO 1343 { 1344 U8 Timeout; /* 00h */ 1345 U8 SyncFactor; /* 01h */ 1346 U16 DeviceFlags; /* 02h */ 1347 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO, 1348 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t; 1349 1350 typedef struct _CONFIG_PAGE_SCSI_PORT_2 1351 { 1352 CONFIG_PAGE_HEADER Header; /* 00h */ 1353 U32 PortFlags; /* 04h */ 1354 U32 PortSettings; /* 08h */ 1355 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */ 1356 } CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2, 1357 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t; 1358 1359 #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x02) 1360 1361 /* PortFlags values */ 1362 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001) 1363 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004) 1364 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1365 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010) 1366 1367 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK (0x00000060) 1368 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV (0x00000000) 1369 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020) 1370 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060) 1371 1372 1373 /* PortSettings values */ 1374 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F) 1375 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030) 1376 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000) 1377 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010) 1378 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020) 1379 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030) 1380 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0) 1381 #define MPI_SCSIPORTPAGE2_PORT_RM_NONE (0x00000000) 1382 #define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY (0x00000040) 1383 #define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA (0x00000080) 1384 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00) 1385 #define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY (8) 1386 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000) 1387 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000) 1388 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000) 1389 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000) 1390 1391 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001) 1392 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002) 1393 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004) 1394 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008) 1395 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010) 1396 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020) 1397 1398 1399 /**************************************************************************** 1400 * SCSI Target Device Config Pages 1401 ****************************************************************************/ 1402 1403 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0 1404 { 1405 CONFIG_PAGE_HEADER Header; /* 00h */ 1406 U32 NegotiatedParameters; /* 04h */ 1407 U32 Information; /* 08h */ 1408 } CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0, 1409 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t; 1410 1411 #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x04) 1412 1413 #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001) 1414 #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002) 1415 #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004) 1416 #define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008) 1417 #define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010) 1418 #define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020) 1419 #define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040) 1420 #define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080) 1421 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00) 1422 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD (8) 1423 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000) 1424 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET (16) 1425 #define MPI_SCSIDEVPAGE0_NP_IDP (0x08000000) 1426 #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000) 1427 #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000) 1428 1429 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001) 1430 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002) 1431 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004) 1432 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008) 1433 1434 1435 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1 1436 { 1437 CONFIG_PAGE_HEADER Header; /* 00h */ 1438 U32 RequestedParameters; /* 04h */ 1439 U32 Reserved; /* 08h */ 1440 U32 Configuration; /* 0Ch */ 1441 } CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1, 1442 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t; 1443 1444 #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x05) 1445 1446 #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001) 1447 #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002) 1448 #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004) 1449 #define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008) 1450 #define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010) 1451 #define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020) 1452 #define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040) 1453 #define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080) 1454 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 1455 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD (8) 1456 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 1457 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET (16) 1458 #define MPI_SCSIDEVPAGE1_RP_IDP (0x08000000) 1459 #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000) 1460 #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000) 1461 1462 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002) 1463 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004) 1464 #define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008) 1465 #define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010) 1466 1467 1468 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2 1469 { 1470 CONFIG_PAGE_HEADER Header; /* 00h */ 1471 U32 DomainValidation; /* 04h */ 1472 U32 ParityPipeSelect; /* 08h */ 1473 U32 DataPipeSelect; /* 0Ch */ 1474 } CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2, 1475 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t; 1476 1477 #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01) 1478 1479 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010) 1480 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020) 1481 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380) 1482 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00) 1483 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000) 1484 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000) 1485 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000) 1486 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000) 1487 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000) 1488 1489 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003) 1490 1491 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003) 1492 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C) 1493 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030) 1494 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0) 1495 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300) 1496 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00) 1497 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000) 1498 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000) 1499 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000) 1500 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000) 1501 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000) 1502 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000) 1503 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000) 1504 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000) 1505 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000) 1506 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000) 1507 1508 1509 typedef struct _CONFIG_PAGE_SCSI_DEVICE_3 1510 { 1511 CONFIG_PAGE_HEADER Header; /* 00h */ 1512 U16 MsgRejectCount; /* 04h */ 1513 U16 PhaseErrorCount; /* 06h */ 1514 U16 ParityErrorCount; /* 08h */ 1515 U16 Reserved; /* 0Ah */ 1516 } CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3, 1517 SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t; 1518 1519 #define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00) 1520 1521 #define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE) 1522 #define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF) 1523 1524 1525 /**************************************************************************** 1526 * FC Port Config Pages 1527 ****************************************************************************/ 1528 1529 typedef struct _CONFIG_PAGE_FC_PORT_0 1530 { 1531 CONFIG_PAGE_HEADER Header; /* 00h */ 1532 U32 Flags; /* 04h */ 1533 U8 MPIPortNumber; /* 08h */ 1534 U8 LinkType; /* 09h */ 1535 U8 PortState; /* 0Ah */ 1536 U8 Reserved; /* 0Bh */ 1537 U32 PortIdentifier; /* 0Ch */ 1538 U64 WWNN; /* 10h */ 1539 U64 WWPN; /* 18h */ 1540 U32 SupportedServiceClass; /* 20h */ 1541 U32 SupportedSpeeds; /* 24h */ 1542 U32 CurrentSpeed; /* 28h */ 1543 U32 MaxFrameSize; /* 2Ch */ 1544 U64 FabricWWNN; /* 30h */ 1545 U64 FabricWWPN; /* 38h */ 1546 U32 DiscoveredPortsCount; /* 40h */ 1547 U32 MaxInitiators; /* 44h */ 1548 U8 MaxAliasesSupported; /* 48h */ 1549 U8 MaxHardAliasesSupported; /* 49h */ 1550 U8 NumCurrentAliases; /* 4Ah */ 1551 U8 Reserved1; /* 4Bh */ 1552 } CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0, 1553 FCPortPage0_t, MPI_POINTER pFCPortPage0_t; 1554 1555 #define MPI_FCPORTPAGE0_PAGEVERSION (0x02) 1556 1557 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F) 1558 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR) 1559 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET) 1560 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN) 1561 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR) 1562 1563 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010) 1564 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020) 1565 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040) 1566 1567 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00) 1568 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000) 1569 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100) 1570 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200) 1571 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400) 1572 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800) 1573 1574 #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00) 1575 #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01) 1576 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02) 1577 #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03) 1578 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04) 1579 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05) 1580 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06) 1581 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07) 1582 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08) 1583 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09) 1584 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A) 1585 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B) 1586 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C) 1587 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D) 1588 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E) 1589 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F) 1590 1591 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */ 1592 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */ 1593 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */ 1594 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */ 1595 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */ 1596 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */ 1597 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */ 1598 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */ 1599 1600 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001) 1601 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002) 1602 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004) 1603 1604 #define MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN (0x00000000) /* (SNIA)HBA_PORTSPEED_UNKNOWN 0 Unknown - transceiver incapable of reporting */ 1605 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */ 1606 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */ 1607 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */ 1608 #define MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED (0x00000008) /* (SNIA)HBA_PORTSPEED_4GBIT 8 4 GBit/sec */ 1609 1610 #define MPI_FCPORTPAGE0_CURRENT_SPEED_UKNOWN MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN 1611 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED 1612 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED 1613 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED 1614 #define MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED 1615 #define MPI_FCPORTPAGE0_CURRENT_SPEED_NOT_NEGOTIATED (0x00008000) /* (SNIA)HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) Speed not established */ 1616 1617 1618 typedef struct _CONFIG_PAGE_FC_PORT_1 1619 { 1620 CONFIG_PAGE_HEADER Header; /* 00h */ 1621 U32 Flags; /* 04h */ 1622 U64 NoSEEPROMWWNN; /* 08h */ 1623 U64 NoSEEPROMWWPN; /* 10h */ 1624 U8 HardALPA; /* 18h */ 1625 U8 LinkConfig; /* 19h */ 1626 U8 TopologyConfig; /* 1Ah */ 1627 U8 AltConnector; /* 1Bh */ 1628 U8 NumRequestedAliases; /* 1Ch */ 1629 U8 RR_TOV; /* 1Dh */ 1630 U8 InitiatorDeviceTimeout; /* 1Eh */ 1631 U8 InitiatorIoPendTimeout; /* 1Fh */ 1632 } CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1, 1633 FCPortPage1_t, MPI_POINTER pFCPortPage1_t; 1634 1635 #define MPI_FCPORTPAGE1_PAGEVERSION (0x06) 1636 1637 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000) 1638 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000) 1639 #define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000) 1640 #define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000) 1641 #define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000) 1642 #define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE (0x00400000) 1643 #define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK (0x00200000) 1644 #define MPI_FCPORTPAGE1_FLAGS_TARGET_LARGE_CDB_ENABLE (0x00000080) 1645 #define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070) 1646 #define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG (0x00000008) 1647 #define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO (0x00000004) 1648 #define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002) 1649 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001) 1650 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000) 1651 1652 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000) 1653 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28) 1654 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1655 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1656 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1657 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1658 1659 #define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000) 1660 #define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010) 1661 #define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030) 1662 #define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050) 1663 1664 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF) 1665 1666 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F) 1667 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00) 1668 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01) 1669 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02) 1670 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03) 1671 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F) 1672 1673 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F) 1674 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01) 1675 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02) 1676 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F) 1677 1678 #define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00) 1679 1680 #define MPI_FCPORTPAGE1_INITIATOR_DEV_TIMEOUT_MASK (0x7F) 1681 #define MPI_FCPORTPAGE1_INITIATOR_DEV_UNIT_16 (0x80) 1682 1683 1684 typedef struct _CONFIG_PAGE_FC_PORT_2 1685 { 1686 CONFIG_PAGE_HEADER Header; /* 00h */ 1687 U8 NumberActive; /* 04h */ 1688 U8 ALPA[127]; /* 05h */ 1689 } CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2, 1690 FCPortPage2_t, MPI_POINTER pFCPortPage2_t; 1691 1692 #define MPI_FCPORTPAGE2_PAGEVERSION (0x01) 1693 1694 1695 typedef struct _WWN_FORMAT 1696 { 1697 U64 WWNN; /* 00h */ 1698 U64 WWPN; /* 08h */ 1699 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT, 1700 WWNFormat, MPI_POINTER pWWNFormat; 1701 1702 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID 1703 { 1704 WWN_FORMAT WWN; 1705 U32 Did; 1706 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID, 1707 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t; 1708 1709 typedef struct _FC_PORT_PERSISTENT 1710 { 1711 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */ 1712 U8 TargetID; /* 10h */ 1713 U8 Bus; /* 11h */ 1714 U16 Flags; /* 12h */ 1715 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT, 1716 PersistentData_t, MPI_POINTER pPersistentData_t; 1717 1718 #define MPI_PERSISTENT_FLAGS_SHIFT (16) 1719 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001) 1720 #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002) 1721 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004) 1722 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008) 1723 #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080) 1724 1725 /* 1726 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1727 * one and check Header.PageLength at runtime. 1728 */ 1729 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX 1730 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1) 1731 #endif 1732 1733 typedef struct _CONFIG_PAGE_FC_PORT_3 1734 { 1735 CONFIG_PAGE_HEADER Header; /* 00h */ 1736 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */ 1737 } CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3, 1738 FCPortPage3_t, MPI_POINTER pFCPortPage3_t; 1739 1740 #define MPI_FCPORTPAGE3_PAGEVERSION (0x01) 1741 1742 1743 typedef struct _CONFIG_PAGE_FC_PORT_4 1744 { 1745 CONFIG_PAGE_HEADER Header; /* 00h */ 1746 U32 PortFlags; /* 04h */ 1747 U32 PortSettings; /* 08h */ 1748 } CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4, 1749 FCPortPage4_t, MPI_POINTER pFCPortPage4_t; 1750 1751 #define MPI_FCPORTPAGE4_PAGEVERSION (0x00) 1752 1753 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1754 1755 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030) 1756 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000) 1757 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010) 1758 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020) 1759 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030) 1760 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0) 1761 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00) 1762 1763 1764 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO 1765 { 1766 U8 Flags; /* 00h */ 1767 U8 AliasAlpa; /* 01h */ 1768 U16 Reserved; /* 02h */ 1769 U64 AliasWWNN; /* 04h */ 1770 U64 AliasWWPN; /* 0Ch */ 1771 } CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1772 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1773 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t; 1774 1775 typedef struct _CONFIG_PAGE_FC_PORT_5 1776 { 1777 CONFIG_PAGE_HEADER Header; /* 00h */ 1778 CONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */ 1779 } CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5, 1780 FCPortPage5_t, MPI_POINTER pFCPortPage5_t; 1781 1782 #define MPI_FCPORTPAGE5_PAGEVERSION (0x02) 1783 1784 #define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01) 1785 #define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02) 1786 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04) 1787 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08) 1788 #define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10) 1789 1790 typedef struct _CONFIG_PAGE_FC_PORT_6 1791 { 1792 CONFIG_PAGE_HEADER Header; /* 00h */ 1793 U32 Reserved; /* 04h */ 1794 U64 TimeSinceReset; /* 08h */ 1795 U64 TxFrames; /* 10h */ 1796 U64 RxFrames; /* 18h */ 1797 U64 TxWords; /* 20h */ 1798 U64 RxWords; /* 28h */ 1799 U64 LipCount; /* 30h */ 1800 U64 NosCount; /* 38h */ 1801 U64 ErrorFrames; /* 40h */ 1802 U64 DumpedFrames; /* 48h */ 1803 U64 LinkFailureCount; /* 50h */ 1804 U64 LossOfSyncCount; /* 58h */ 1805 U64 LossOfSignalCount; /* 60h */ 1806 U64 PrimativeSeqErrCount; /* 68h */ 1807 U64 InvalidTxWordCount; /* 70h */ 1808 U64 InvalidCrcCount; /* 78h */ 1809 U64 FcpInitiatorIoCount; /* 80h */ 1810 } CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6, 1811 FCPortPage6_t, MPI_POINTER pFCPortPage6_t; 1812 1813 #define MPI_FCPORTPAGE6_PAGEVERSION (0x00) 1814 1815 1816 typedef struct _CONFIG_PAGE_FC_PORT_7 1817 { 1818 CONFIG_PAGE_HEADER Header; /* 00h */ 1819 U32 Reserved; /* 04h */ 1820 U8 PortSymbolicName[256]; /* 08h */ 1821 } CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7, 1822 FCPortPage7_t, MPI_POINTER pFCPortPage7_t; 1823 1824 #define MPI_FCPORTPAGE7_PAGEVERSION (0x00) 1825 1826 1827 typedef struct _CONFIG_PAGE_FC_PORT_8 1828 { 1829 CONFIG_PAGE_HEADER Header; /* 00h */ 1830 U32 BitVector[8]; /* 04h */ 1831 } CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8, 1832 FCPortPage8_t, MPI_POINTER pFCPortPage8_t; 1833 1834 #define MPI_FCPORTPAGE8_PAGEVERSION (0x00) 1835 1836 1837 typedef struct _CONFIG_PAGE_FC_PORT_9 1838 { 1839 CONFIG_PAGE_HEADER Header; /* 00h */ 1840 U32 Reserved; /* 04h */ 1841 U64 GlobalWWPN; /* 08h */ 1842 U64 GlobalWWNN; /* 10h */ 1843 U32 UnitType; /* 18h */ 1844 U32 PhysicalPortNumber; /* 1Ch */ 1845 U32 NumAttachedNodes; /* 20h */ 1846 U16 IPVersion; /* 24h */ 1847 U16 UDPPortNumber; /* 26h */ 1848 U8 IPAddress[16]; /* 28h */ 1849 U16 Reserved1; /* 38h */ 1850 U16 TopologyDiscoveryFlags; /* 3Ah */ 1851 } CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9, 1852 FCPortPage9_t, MPI_POINTER pFCPortPage9_t; 1853 1854 #define MPI_FCPORTPAGE9_PAGEVERSION (0x00) 1855 1856 1857 typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA 1858 { 1859 U8 Id; /* 10h */ 1860 U8 ExtId; /* 11h */ 1861 U8 Connector; /* 12h */ 1862 U8 Transceiver[8]; /* 13h */ 1863 U8 Encoding; /* 1Bh */ 1864 U8 BitRate_100mbs; /* 1Ch */ 1865 U8 Reserved1; /* 1Dh */ 1866 U8 Length9u_km; /* 1Eh */ 1867 U8 Length9u_100m; /* 1Fh */ 1868 U8 Length50u_10m; /* 20h */ 1869 U8 Length62p5u_10m; /* 21h */ 1870 U8 LengthCopper_m; /* 22h */ 1871 U8 Reseverved2; /* 22h */ 1872 U8 VendorName[16]; /* 24h */ 1873 U8 Reserved3; /* 34h */ 1874 U8 VendorOUI[3]; /* 35h */ 1875 U8 VendorPN[16]; /* 38h */ 1876 U8 VendorRev[4]; /* 48h */ 1877 U16 Wavelength; /* 4Ch */ 1878 U8 Reserved4; /* 4Eh */ 1879 U8 CC_BASE; /* 4Fh */ 1880 } CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA, 1881 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA, 1882 FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t; 1883 1884 #define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00) 1885 #define MPI_FCPORT10_BASE_ID_GBIC (0x01) 1886 #define MPI_FCPORT10_BASE_ID_FIXED (0x02) 1887 #define MPI_FCPORT10_BASE_ID_SFP (0x03) 1888 #define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04) 1889 #define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F) 1890 #define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80) 1891 1892 #define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00) 1893 #define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01) 1894 #define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02) 1895 #define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03) 1896 #define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04) 1897 #define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05) 1898 #define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06) 1899 #define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07) 1900 #define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80) 1901 1902 #define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00) 1903 #define MPI_FCPORT10_BASE_CONN_SC (0x01) 1904 #define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02) 1905 #define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03) 1906 #define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04) 1907 #define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05) 1908 #define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06) 1909 #define MPI_FCPORT10_BASE_CONN_LC (0x07) 1910 #define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08) 1911 #define MPI_FCPORT10_BASE_CONN_MU (0x09) 1912 #define MPI_FCPORT10_BASE_CONN_SG (0x0A) 1913 #define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B) 1914 #define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C) 1915 #define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F) 1916 #define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20) 1917 #define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21) 1918 #define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22) 1919 #define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F) 1920 #define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80) 1921 1922 #define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00) 1923 #define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01) 1924 #define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02) 1925 #define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03) 1926 #define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04) 1927 1928 1929 typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA 1930 { 1931 U8 Options[2]; /* 50h */ 1932 U8 BitRateMax; /* 52h */ 1933 U8 BitRateMin; /* 53h */ 1934 U8 VendorSN[16]; /* 54h */ 1935 U8 DateCode[8]; /* 64h */ 1936 U8 DiagMonitoringType; /* 6Ch */ 1937 U8 EnhancedOptions; /* 6Dh */ 1938 U8 SFF8472Compliance; /* 6Eh */ 1939 U8 CC_EXT; /* 6Fh */ 1940 } CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA, 1941 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA, 1942 FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t; 1943 1944 #define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20) 1945 #define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10) 1946 #define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08) 1947 #define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04) 1948 #define MPI_FCPORT10_EXT_OPTION1_LOS (0x02) 1949 1950 1951 typedef struct _CONFIG_PAGE_FC_PORT_10 1952 { 1953 CONFIG_PAGE_HEADER Header; /* 00h */ 1954 U8 Flags; /* 04h */ 1955 U8 Reserved1; /* 05h */ 1956 U16 Reserved2; /* 06h */ 1957 U32 HwConfig1; /* 08h */ 1958 U32 HwConfig2; /* 0Ch */ 1959 CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */ 1960 CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */ 1961 U8 VendorSpecific[32]; /* 70h */ 1962 } CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10, 1963 FCPortPage10_t, MPI_POINTER pFCPortPage10_t; 1964 1965 #define MPI_FCPORTPAGE10_PAGEVERSION (0x01) 1966 1967 /* standard MODDEF pin definitions (from GBIC spec.) */ 1968 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007) 1969 #define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001) 1970 #define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002) 1971 #define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004) 1972 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007) 1973 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006) 1974 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005) 1975 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004) 1976 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003) 1977 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002) 1978 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001) 1979 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000) 1980 1981 #define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010) 1982 #define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020) 1983 1984 1985 /**************************************************************************** 1986 * FC Device Config Pages 1987 ****************************************************************************/ 1988 1989 typedef struct _CONFIG_PAGE_FC_DEVICE_0 1990 { 1991 CONFIG_PAGE_HEADER Header; /* 00h */ 1992 U64 WWNN; /* 04h */ 1993 U64 WWPN; /* 0Ch */ 1994 U32 PortIdentifier; /* 14h */ 1995 U8 Protocol; /* 18h */ 1996 U8 Flags; /* 19h */ 1997 U16 BBCredit; /* 1Ah */ 1998 U16 MaxRxFrameSize; /* 1Ch */ 1999 U8 ADISCHardALPA; /* 1Eh */ 2000 U8 PortNumber; /* 1Fh */ 2001 U8 FcPhLowestVersion; /* 20h */ 2002 U8 FcPhHighestVersion; /* 21h */ 2003 U8 CurrentTargetID; /* 22h */ 2004 U8 CurrentBus; /* 23h */ 2005 } CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0, 2006 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t; 2007 2008 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x03) 2009 2010 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01) 2011 #define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02) 2012 #define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04) 2013 2014 #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01) 2015 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02) 2016 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04) 2017 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY (0x08) 2018 2019 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK) 2020 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK) 2021 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) 2022 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID) 2023 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK) 2024 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK) 2025 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT) 2026 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK) 2027 2028 #define MPI_FC_DEVICE_PAGE0_HARD_ALPA_UNKNOWN (0xFF) 2029 2030 /**************************************************************************** 2031 * RAID Volume Config Pages 2032 ****************************************************************************/ 2033 2034 typedef struct _RAID_VOL0_PHYS_DISK 2035 { 2036 U16 Reserved; /* 00h */ 2037 U8 PhysDiskMap; /* 02h */ 2038 U8 PhysDiskNum; /* 03h */ 2039 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK, 2040 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t; 2041 2042 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 2043 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 2044 2045 typedef struct _RAID_VOL0_STATUS 2046 { 2047 U8 Flags; /* 00h */ 2048 U8 State; /* 01h */ 2049 U16 Reserved; /* 02h */ 2050 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS, 2051 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t; 2052 2053 /* RAID Volume Page 0 VolumeStatus defines */ 2054 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01) 2055 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02) 2056 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04) 2057 #define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08) 2058 #define MPI_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x10) 2059 2060 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00) 2061 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01) 2062 #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02) 2063 #define MPI_RAIDVOL0_STATUS_STATE_MISSING (0x03) 2064 2065 typedef struct _RAID_VOL0_SETTINGS 2066 { 2067 U16 Settings; /* 00h */ 2068 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 2069 U8 Reserved; /* 02h */ 2070 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS, 2071 RaidVol0Settings, MPI_POINTER pRaidVol0Settings; 2072 2073 /* RAID Volume Page 0 VolumeSettings defines */ 2074 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001) 2075 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002) 2076 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004) 2077 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008) 2078 #define MPI_RAIDVOL0_SETTING_FAST_DATA_SCRUBBING_0102 (0x0020) /* obsolete */ 2079 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010) 2080 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000) 2081 2082 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 2083 #define MPI_RAID_HOT_SPARE_POOL_0 (0x01) 2084 #define MPI_RAID_HOT_SPARE_POOL_1 (0x02) 2085 #define MPI_RAID_HOT_SPARE_POOL_2 (0x04) 2086 #define MPI_RAID_HOT_SPARE_POOL_3 (0x08) 2087 #define MPI_RAID_HOT_SPARE_POOL_4 (0x10) 2088 #define MPI_RAID_HOT_SPARE_POOL_5 (0x20) 2089 #define MPI_RAID_HOT_SPARE_POOL_6 (0x40) 2090 #define MPI_RAID_HOT_SPARE_POOL_7 (0x80) 2091 2092 /* 2093 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2094 * one and check Header.PageLength at runtime. 2095 */ 2096 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX 2097 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 2098 #endif 2099 2100 typedef struct _CONFIG_PAGE_RAID_VOL_0 2101 { 2102 CONFIG_PAGE_HEADER Header; /* 00h */ 2103 U8 VolumeID; /* 04h */ 2104 U8 VolumeBus; /* 05h */ 2105 U8 VolumeIOC; /* 06h */ 2106 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */ 2107 RAID_VOL0_STATUS VolumeStatus; /* 08h */ 2108 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */ 2109 U32 MaxLBA; /* 10h */ 2110 U32 Reserved1; /* 14h */ 2111 U32 StripeSize; /* 18h */ 2112 U32 Reserved2; /* 1Ch */ 2113 U32 Reserved3; /* 20h */ 2114 U8 NumPhysDisks; /* 24h */ 2115 U8 DataScrubRate; /* 25h */ 2116 U8 ResyncRate; /* 26h */ 2117 U8 InactiveStatus; /* 27h */ 2118 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */ 2119 } CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0, 2120 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t; 2121 2122 #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x05) 2123 2124 /* values for RAID Volume Page 0 InactiveStatus field */ 2125 #define MPI_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 2126 #define MPI_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 2127 #define MPI_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 2128 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 2129 #define MPI_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 2130 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 2131 #define MPI_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 2132 2133 2134 typedef struct _CONFIG_PAGE_RAID_VOL_1 2135 { 2136 CONFIG_PAGE_HEADER Header; /* 00h */ 2137 U8 VolumeID; /* 01h */ 2138 U8 VolumeBus; /* 02h */ 2139 U8 VolumeIOC; /* 03h */ 2140 U8 Reserved0; /* 04h */ 2141 U8 GUID[24]; /* 05h */ 2142 U8 Name[32]; /* 20h */ 2143 U64 WWID; /* 40h */ 2144 U32 Reserved1; /* 48h */ 2145 U32 Reserved2; /* 4Ch */ 2146 } CONFIG_PAGE_RAID_VOL_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_1, 2147 RaidVolumePage1_t, MPI_POINTER pRaidVolumePage1_t; 2148 2149 #define MPI_RAIDVOLPAGE1_PAGEVERSION (0x01) 2150 2151 2152 /**************************************************************************** 2153 * RAID Physical Disk Config Pages 2154 ****************************************************************************/ 2155 2156 typedef struct _RAID_PHYS_DISK0_ERROR_DATA 2157 { 2158 U8 ErrorCdbByte; /* 00h */ 2159 U8 ErrorSenseKey; /* 01h */ 2160 U16 Reserved; /* 02h */ 2161 U16 ErrorCount; /* 04h */ 2162 U8 ErrorASC; /* 06h */ 2163 U8 ErrorASCQ; /* 07h */ 2164 U16 SmartCount; /* 08h */ 2165 U8 SmartASC; /* 0Ah */ 2166 U8 SmartASCQ; /* 0Bh */ 2167 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA, 2168 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t; 2169 2170 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA 2171 { 2172 U8 VendorID[8]; /* 00h */ 2173 U8 ProductID[16]; /* 08h */ 2174 U8 ProductRevLevel[4]; /* 18h */ 2175 U8 Info[32]; /* 1Ch */ 2176 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA, 2177 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData; 2178 2179 typedef struct _RAID_PHYS_DISK0_SETTINGS 2180 { 2181 U8 SepID; /* 00h */ 2182 U8 SepBus; /* 01h */ 2183 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 2184 U8 PhysDiskSettings; /* 03h */ 2185 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS, 2186 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t; 2187 2188 typedef struct _RAID_PHYS_DISK0_STATUS 2189 { 2190 U8 Flags; /* 00h */ 2191 U8 State; /* 01h */ 2192 U16 Reserved; /* 02h */ 2193 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS, 2194 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t; 2195 2196 /* RAID Volume 2 IM Physical Disk DiskStatus flags */ 2197 2198 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01) 2199 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02) 2200 #define MPI_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x04) 2201 #define MPI_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00) 2202 #define MPI_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x08) 2203 2204 #define MPI_PHYSDISK0_STATUS_ONLINE (0x00) 2205 #define MPI_PHYSDISK0_STATUS_MISSING (0x01) 2206 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02) 2207 #define MPI_PHYSDISK0_STATUS_FAILED (0x03) 2208 #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04) 2209 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05) 2210 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06) 2211 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF) 2212 2213 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0 2214 { 2215 CONFIG_PAGE_HEADER Header; /* 00h */ 2216 U8 PhysDiskID; /* 04h */ 2217 U8 PhysDiskBus; /* 05h */ 2218 U8 PhysDiskIOC; /* 06h */ 2219 U8 PhysDiskNum; /* 07h */ 2220 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */ 2221 U32 Reserved1; /* 0Ch */ 2222 U8 ExtDiskIdentifier[8]; /* 10h */ 2223 U8 DiskIdentifier[16]; /* 18h */ 2224 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */ 2225 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */ 2226 U32 MaxLBA; /* 68h */ 2227 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */ 2228 } CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0, 2229 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t; 2230 2231 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x02) 2232 2233 2234 typedef struct _RAID_PHYS_DISK1_PATH 2235 { 2236 U8 PhysDiskID; /* 00h */ 2237 U8 PhysDiskBus; /* 01h */ 2238 U16 Reserved1; /* 02h */ 2239 U64 WWID; /* 04h */ 2240 U64 OwnerWWID; /* 0Ch */ 2241 U8 OwnerIdentifier; /* 14h */ 2242 U8 Reserved2; /* 15h */ 2243 U16 Flags; /* 16h */ 2244 } RAID_PHYS_DISK1_PATH, MPI_POINTER PTR_RAID_PHYS_DISK1_PATH, 2245 RaidPhysDisk1Path_t, MPI_POINTER pRaidPhysDisk1Path_t; 2246 2247 /* RAID Physical Disk Page 1 Flags field defines */ 2248 #define MPI_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 2249 #define MPI_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 2250 2251 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_1 2252 { 2253 CONFIG_PAGE_HEADER Header; /* 00h */ 2254 U8 NumPhysDiskPaths; /* 04h */ 2255 U8 PhysDiskNum; /* 05h */ 2256 U16 Reserved2; /* 06h */ 2257 U32 Reserved1; /* 08h */ 2258 RAID_PHYS_DISK1_PATH Path[1]; /* 0Ch */ 2259 } CONFIG_PAGE_RAID_PHYS_DISK_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_1, 2260 RaidPhysDiskPage1_t, MPI_POINTER pRaidPhysDiskPage1_t; 2261 2262 #define MPI_RAIDPHYSDISKPAGE1_PAGEVERSION (0x00) 2263 2264 2265 /**************************************************************************** 2266 * LAN Config Pages 2267 ****************************************************************************/ 2268 2269 typedef struct _CONFIG_PAGE_LAN_0 2270 { 2271 ConfigPageHeader_t Header; /* 00h */ 2272 U16 TxRxModes; /* 04h */ 2273 U16 Reserved; /* 06h */ 2274 U32 PacketPrePad; /* 08h */ 2275 } CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0, 2276 LANPage0_t, MPI_POINTER pLANPage0_t; 2277 2278 #define MPI_LAN_PAGE0_PAGEVERSION (0x01) 2279 2280 #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000) 2281 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001) 2282 #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001) 2283 2284 typedef struct _CONFIG_PAGE_LAN_1 2285 { 2286 ConfigPageHeader_t Header; /* 00h */ 2287 U16 Reserved; /* 04h */ 2288 U8 CurrentDeviceState; /* 06h */ 2289 U8 Reserved1; /* 07h */ 2290 U32 MinPacketSize; /* 08h */ 2291 U32 MaxPacketSize; /* 0Ch */ 2292 U32 HardwareAddressLow; /* 10h */ 2293 U32 HardwareAddressHigh; /* 14h */ 2294 U32 MaxWireSpeedLow; /* 18h */ 2295 U32 MaxWireSpeedHigh; /* 1Ch */ 2296 U32 BucketsRemaining; /* 20h */ 2297 U32 MaxReplySize; /* 24h */ 2298 U32 NegWireSpeedLow; /* 28h */ 2299 U32 NegWireSpeedHigh; /* 2Ch */ 2300 } CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1, 2301 LANPage1_t, MPI_POINTER pLANPage1_t; 2302 2303 #define MPI_LAN_PAGE1_PAGEVERSION (0x03) 2304 2305 #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00) 2306 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01) 2307 2308 2309 /**************************************************************************** 2310 * Inband Config Pages 2311 ****************************************************************************/ 2312 2313 typedef struct _CONFIG_PAGE_INBAND_0 2314 { 2315 CONFIG_PAGE_HEADER Header; /* 00h */ 2316 MPI_VERSION_FORMAT InbandVersion; /* 04h */ 2317 U16 MaximumBuffers; /* 08h */ 2318 U16 Reserved1; /* 0Ah */ 2319 } CONFIG_PAGE_INBAND_0, MPI_POINTER PTR_CONFIG_PAGE_INBAND_0, 2320 InbandPage0_t, MPI_POINTER pInbandPage0_t; 2321 2322 #define MPI_INBAND_PAGEVERSION (0x00) 2323 2324 2325 2326 /**************************************************************************** 2327 * SAS IO Unit Config Pages 2328 ****************************************************************************/ 2329 2330 typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA 2331 { 2332 U8 Port; /* 00h */ 2333 U8 PortFlags; /* 01h */ 2334 U8 PhyFlags; /* 02h */ 2335 U8 NegotiatedLinkRate; /* 03h */ 2336 U32 ControllerPhyDeviceInfo;/* 04h */ 2337 U16 AttachedDeviceHandle; /* 08h */ 2338 U16 ControllerDevHandle; /* 0Ah */ 2339 U32 DiscoveryStatus; /* 0Ch */ 2340 } MPI_SAS_IO_UNIT0_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT0_PHY_DATA, 2341 SasIOUnit0PhyData, MPI_POINTER pSasIOUnit0PhyData; 2342 2343 /* 2344 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2345 * one and check Header.PageLength at runtime. 2346 */ 2347 #ifndef MPI_SAS_IOUNIT0_PHY_MAX 2348 #define MPI_SAS_IOUNIT0_PHY_MAX (1) 2349 #endif 2350 2351 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_0 2352 { 2353 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2354 U32 Reserved1; /* 08h */ 2355 U8 NumPhys; /* 0Ch */ 2356 U8 Reserved2; /* 0Dh */ 2357 U16 Reserved3; /* 0Eh */ 2358 MPI_SAS_IO_UNIT0_PHY_DATA PhyData[MPI_SAS_IOUNIT0_PHY_MAX]; /* 10h */ 2359 } CONFIG_PAGE_SAS_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_0, 2360 SasIOUnitPage0_t, MPI_POINTER pSasIOUnitPage0_t; 2361 2362 #define MPI_SASIOUNITPAGE0_PAGEVERSION (0x03) 2363 2364 /* values for SAS IO Unit Page 0 PortFlags */ 2365 #define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS (0x08) 2366 #define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM (0x00) 2367 #define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM (0x04) 2368 #define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2369 2370 /* values for SAS IO Unit Page 0 PhyFlags */ 2371 #define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED (0x04) 2372 #define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT (0x02) 2373 #define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT (0x01) 2374 2375 /* values for SAS IO Unit Page 0 NegotiatedLinkRate */ 2376 #define MPI_SAS_IOUNIT0_RATE_UNKNOWN (0x00) 2377 #define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED (0x01) 2378 #define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION (0x02) 2379 #define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE (0x03) 2380 #define MPI_SAS_IOUNIT0_RATE_1_5 (0x08) 2381 #define MPI_SAS_IOUNIT0_RATE_3_0 (0x09) 2382 2383 /* see mpi_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 2384 2385 /* values for SAS IO Unit Page 0 DiscoveryStatus */ 2386 #define MPI_SAS_IOUNIT0_DS_LOOP_DETECTED (0x00000001) 2387 #define MPI_SAS_IOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2388 #define MPI_SAS_IOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2389 #define MPI_SAS_IOUNIT0_DS_EXPANDER_ERR (0x00000008) 2390 #define MPI_SAS_IOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2391 #define MPI_SAS_IOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2392 #define MPI_SAS_IOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2393 #define MPI_SAS_IOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2394 #define MPI_SAS_IOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2395 #define MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2396 #define MPI_SAS_IOUNIT0_DS_TABLE_LINK (0x00000400) 2397 #define MPI_SAS_IOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2398 #define MPI_SAS_IOUNIT0_DS_MAX_SATA_TARGETS (0x00001000) 2399 2400 2401 typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA 2402 { 2403 U8 Port; /* 00h */ 2404 U8 PortFlags; /* 01h */ 2405 U8 PhyFlags; /* 02h */ 2406 U8 MaxMinLinkRate; /* 03h */ 2407 U32 ControllerPhyDeviceInfo;/* 04h */ 2408 U32 Reserved1; /* 08h */ 2409 } MPI_SAS_IO_UNIT1_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT1_PHY_DATA, 2410 SasIOUnit1PhyData, MPI_POINTER pSasIOUnit1PhyData; 2411 2412 /* 2413 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2414 * one and check Header.PageLength at runtime. 2415 */ 2416 #ifndef MPI_SAS_IOUNIT1_PHY_MAX 2417 #define MPI_SAS_IOUNIT1_PHY_MAX (1) 2418 #endif 2419 2420 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_1 2421 { 2422 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2423 U16 ControlFlags; /* 08h */ 2424 U16 MaxNumSATATargets; /* 0Ah */ 2425 U32 Reserved1; /* 0Ch */ 2426 U8 NumPhys; /* 10h */ 2427 U8 SATAMaxQDepth; /* 11h */ 2428 U16 Reserved2; /* 12h */ 2429 MPI_SAS_IO_UNIT1_PHY_DATA PhyData[MPI_SAS_IOUNIT1_PHY_MAX]; /* 14h */ 2430 } CONFIG_PAGE_SAS_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_1, 2431 SasIOUnitPage1_t, MPI_POINTER pSasIOUnitPage1_t; 2432 2433 #define MPI_SASIOUNITPAGE1_PAGEVERSION (0x05) 2434 2435 /* values for SAS IO Unit Page 1 ControlFlags */ 2436 #define MPI_SAS_IOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2437 #define MPI_SAS_IOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2438 #define MPI_SAS_IOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 2439 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2440 #define MPI_SAS_IOUNIT1_CONTROL_DISABLE_SAS_HASH (0x0800) 2441 2442 #define MPI_SAS_IOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2443 #define MPI_SAS_IOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2444 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x00) 2445 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x01) 2446 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x02) 2447 2448 #define MPI_SAS_IOUNIT1_CONTROL_POSTPONE_SATA_INIT (0x0100) 2449 #define MPI_SAS_IOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2450 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2451 #define MPI_SAS_IOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2452 #define MPI_SAS_IOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2453 #define MPI_SAS_IOUNIT1_CONTROL_PHY_ENABLE_ORDER_HIGH (0x0008) 2454 #define MPI_SAS_IOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2455 #define MPI_SAS_IOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2456 #define MPI_SAS_IOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 2457 2458 /* values for SAS IO Unit Page 1 PortFlags */ 2459 #define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM (0x00) 2460 #define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM (0x04) 2461 #define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2462 2463 /* values for SAS IO Unit Page 0 PhyFlags */ 2464 #define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE (0x04) 2465 #define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT (0x02) 2466 #define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT (0x01) 2467 2468 /* values for SAS IO Unit Page 0 MaxMinLinkRate */ 2469 #define MPI_SAS_IOUNIT1_MAX_RATE_MASK (0xF0) 2470 #define MPI_SAS_IOUNIT1_MAX_RATE_1_5 (0x80) 2471 #define MPI_SAS_IOUNIT1_MAX_RATE_3_0 (0x90) 2472 #define MPI_SAS_IOUNIT1_MIN_RATE_MASK (0x0F) 2473 #define MPI_SAS_IOUNIT1_MIN_RATE_1_5 (0x08) 2474 #define MPI_SAS_IOUNIT1_MIN_RATE_3_0 (0x09) 2475 2476 /* see mpi_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2477 2478 2479 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_2 2480 { 2481 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2482 U8 NumDevsPerEnclosure; /* 08h */ 2483 U8 Reserved1; /* 09h */ 2484 U16 Reserved2; /* 0Ah */ 2485 U16 MaxPersistentIDs; /* 0Ch */ 2486 U16 NumPersistentIDsUsed; /* 0Eh */ 2487 U8 Status; /* 10h */ 2488 U8 Flags; /* 11h */ 2489 U16 MaxNumPhysicalMappedIDs;/* 12h */ 2490 } CONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2, 2491 SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t; 2492 2493 #define MPI_SASIOUNITPAGE2_PAGEVERSION (0x05) 2494 2495 /* values for SAS IO Unit Page 2 Status field */ 2496 #define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS (0x02) 2497 #define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS (0x01) 2498 2499 /* values for SAS IO Unit Page 2 Flags field */ 2500 #define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS (0x01) 2501 /* Physical Mapping Modes */ 2502 #define MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE (0x0E) 2503 #define MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE (1) 2504 #define MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP (0x00) 2505 #define MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP (0x01) 2506 #define MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP (0x02) 2507 #define MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP (0x07) 2508 2509 #define MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT (0x10) 2510 #define MPI_SAS_IOUNIT2_FLAGS_DA_STARTING_SLOT (0x20) 2511 2512 2513 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_3 2514 { 2515 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2516 U32 Reserved1; /* 08h */ 2517 U32 MaxInvalidDwordCount; /* 0Ch */ 2518 U32 InvalidDwordCountTime; /* 10h */ 2519 U32 MaxRunningDisparityErrorCount; /* 14h */ 2520 U32 RunningDisparityErrorTime; /* 18h */ 2521 U32 MaxLossDwordSynchCount; /* 1Ch */ 2522 U32 LossDwordSynchCountTime; /* 20h */ 2523 U32 MaxPhyResetProblemCount; /* 24h */ 2524 U32 PhyResetProblemTime; /* 28h */ 2525 } CONFIG_PAGE_SAS_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_3, 2526 SasIOUnitPage3_t, MPI_POINTER pSasIOUnitPage3_t; 2527 2528 #define MPI_SASIOUNITPAGE3_PAGEVERSION (0x00) 2529 2530 2531 /**************************************************************************** 2532 * SAS Expander Config Pages 2533 ****************************************************************************/ 2534 2535 typedef struct _CONFIG_PAGE_SAS_EXPANDER_0 2536 { 2537 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2538 U8 PhysicalPort; /* 08h */ 2539 U8 Reserved1; /* 09h */ 2540 U16 EnclosureHandle; /* 0Ah */ 2541 U64 SASAddress; /* 0Ch */ 2542 U32 DiscoveryStatus; /* 14h */ 2543 U16 DevHandle; /* 18h */ 2544 U16 ParentDevHandle; /* 1Ah */ 2545 U16 ExpanderChangeCount; /* 1Ch */ 2546 U16 ExpanderRouteIndexes; /* 1Eh */ 2547 U8 NumPhys; /* 20h */ 2548 U8 SASLevel; /* 21h */ 2549 U8 Flags; /* 22h */ 2550 U8 Reserved3; /* 23h */ 2551 } CONFIG_PAGE_SAS_EXPANDER_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_0, 2552 SasExpanderPage0_t, MPI_POINTER pSasExpanderPage0_t; 2553 2554 #define MPI_SASEXPANDER0_PAGEVERSION (0x03) 2555 2556 /* values for SAS Expander Page 0 DiscoveryStatus field */ 2557 #define MPI_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2558 #define MPI_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2559 #define MPI_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2560 #define MPI_SAS_EXPANDER0_DS_EXPANDER_ERR (0x00000008) 2561 #define MPI_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2562 #define MPI_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2563 #define MPI_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2564 #define MPI_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2565 #define MPI_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2566 #define MPI_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2567 #define MPI_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2568 #define MPI_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2569 2570 /* values for SAS Expander Page 0 Flags field */ 2571 #define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x02) 2572 #define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x01) 2573 2574 2575 typedef struct _CONFIG_PAGE_SAS_EXPANDER_1 2576 { 2577 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2578 U8 PhysicalPort; /* 08h */ 2579 U8 Reserved1; /* 09h */ 2580 U16 Reserved2; /* 0Ah */ 2581 U8 NumPhys; /* 0Ch */ 2582 U8 Phy; /* 0Dh */ 2583 U16 NumTableEntriesProgrammed; /* 0Eh */ 2584 U8 ProgrammedLinkRate; /* 10h */ 2585 U8 HwLinkRate; /* 11h */ 2586 U16 AttachedDevHandle; /* 12h */ 2587 U32 PhyInfo; /* 14h */ 2588 U32 AttachedDeviceInfo; /* 18h */ 2589 U16 OwnerDevHandle; /* 1Ch */ 2590 U8 ChangeCount; /* 1Eh */ 2591 U8 NegotiatedLinkRate; /* 1Fh */ 2592 U8 PhyIdentifier; /* 20h */ 2593 U8 AttachedPhyIdentifier; /* 21h */ 2594 U8 Reserved3; /* 22h */ 2595 U8 DiscoveryInfo; /* 23h */ 2596 U32 Reserved4; /* 24h */ 2597 } CONFIG_PAGE_SAS_EXPANDER_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_1, 2598 SasExpanderPage1_t, MPI_POINTER pSasExpanderPage1_t; 2599 2600 #define MPI_SASEXPANDER1_PAGEVERSION (0x01) 2601 2602 /* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */ 2603 2604 /* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */ 2605 2606 /* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */ 2607 2608 /* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */ 2609 2610 /* values for SAS Expander Page 1 DiscoveryInfo field */ 2611 #define MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY DISABLED (0x04) 2612 #define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2613 #define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2614 2615 /* values for SAS Expander Page 1 NegotiatedLinkRate field */ 2616 #define MPI_SAS_EXPANDER1_NEG_RATE_UNKNOWN (0x00) 2617 #define MPI_SAS_EXPANDER1_NEG_RATE_PHY_DISABLED (0x01) 2618 #define MPI_SAS_EXPANDER1_NEG_RATE_FAILED_NEGOTIATION (0x02) 2619 #define MPI_SAS_EXPANDER1_NEG_RATE_SATA_OOB_COMPLETE (0x03) 2620 #define MPI_SAS_EXPANDER1_NEG_RATE_1_5 (0x08) 2621 #define MPI_SAS_EXPANDER1_NEG_RATE_3_0 (0x09) 2622 2623 2624 /**************************************************************************** 2625 * SAS Device Config Pages 2626 ****************************************************************************/ 2627 2628 typedef struct _CONFIG_PAGE_SAS_DEVICE_0 2629 { 2630 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2631 U16 Slot; /* 08h */ 2632 U16 EnclosureHandle; /* 0Ah */ 2633 U64 SASAddress; /* 0Ch */ 2634 U16 ParentDevHandle; /* 14h */ 2635 U8 PhyNum; /* 16h */ 2636 U8 AccessStatus; /* 17h */ 2637 U16 DevHandle; /* 18h */ 2638 U8 TargetID; /* 1Ah */ 2639 U8 Bus; /* 1Bh */ 2640 U32 DeviceInfo; /* 1Ch */ 2641 U16 Flags; /* 20h */ 2642 U8 PhysicalPort; /* 22h */ 2643 U8 Reserved2; /* 23h */ 2644 } CONFIG_PAGE_SAS_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_0, 2645 SasDevicePage0_t, MPI_POINTER pSasDevicePage0_t; 2646 2647 #define MPI_SASDEVICE0_PAGEVERSION (0x04) 2648 2649 /* values for SAS Device Page 0 AccessStatus field */ 2650 #define MPI_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2651 #define MPI_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2652 #define MPI_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2653 2654 /* values for SAS Device Page 0 Flags field */ 2655 #define MPI_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2656 #define MPI_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2657 #define MPI_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2658 #define MPI_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2659 #define MPI_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2660 #define MPI_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2661 #define MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2662 #define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT (0x0004) 2663 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED (0x0002) 2664 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2665 2666 /* see mpi_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2667 2668 2669 typedef struct _CONFIG_PAGE_SAS_DEVICE_1 2670 { 2671 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2672 U32 Reserved1; /* 08h */ 2673 U64 SASAddress; /* 0Ch */ 2674 U32 Reserved2; /* 14h */ 2675 U16 DevHandle; /* 18h */ 2676 U8 TargetID; /* 1Ah */ 2677 U8 Bus; /* 1Bh */ 2678 U8 InitialRegDeviceFIS[20];/* 1Ch */ 2679 } CONFIG_PAGE_SAS_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_1, 2680 SasDevicePage1_t, MPI_POINTER pSasDevicePage1_t; 2681 2682 #define MPI_SASDEVICE1_PAGEVERSION (0x00) 2683 2684 2685 typedef struct _CONFIG_PAGE_SAS_DEVICE_2 2686 { 2687 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2688 U64 PhysicalIdentifier; /* 08h */ 2689 U32 EnclosureMapping; /* 10h */ 2690 } CONFIG_PAGE_SAS_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_2, 2691 SasDevicePage2_t, MPI_POINTER pSasDevicePage2_t; 2692 2693 #define MPI_SASDEVICE2_PAGEVERSION (0x01) 2694 2695 /* defines for SAS Device Page 2 EnclosureMapping field */ 2696 #define MPI_SASDEVICE2_ENC_MAP_MASK_MISSING_COUNT (0x0000000F) 2697 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_MISSING_COUNT (0) 2698 #define MPI_SASDEVICE2_ENC_MAP_MASK_NUM_SLOTS (0x000007F0) 2699 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_NUM_SLOTS (4) 2700 #define MPI_SASDEVICE2_ENC_MAP_MASK_START_INDEX (0x001FF800) 2701 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_START_INDEX (11) 2702 2703 2704 /**************************************************************************** 2705 * SAS PHY Config Pages 2706 ****************************************************************************/ 2707 2708 typedef struct _CONFIG_PAGE_SAS_PHY_0 2709 { 2710 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2711 U16 OwnerDevHandle; /* 08h */ 2712 U16 Reserved1; /* 0Ah */ 2713 U64 SASAddress; /* 0Ch */ 2714 U16 AttachedDevHandle; /* 14h */ 2715 U8 AttachedPhyIdentifier; /* 16h */ 2716 U8 Reserved2; /* 17h */ 2717 U32 AttachedDeviceInfo; /* 18h */ 2718 U8 ProgrammedLinkRate; /* 20h */ 2719 U8 HwLinkRate; /* 21h */ 2720 U8 ChangeCount; /* 22h */ 2721 U8 Flags; /* 23h */ 2722 U32 PhyInfo; /* 24h */ 2723 } CONFIG_PAGE_SAS_PHY_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_0, 2724 SasPhyPage0_t, MPI_POINTER pSasPhyPage0_t; 2725 2726 #define MPI_SASPHY0_PAGEVERSION (0x01) 2727 2728 /* values for SAS PHY Page 0 ProgrammedLinkRate field */ 2729 #define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK (0xF0) 2730 #define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 2731 #define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5 (0x80) 2732 #define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0 (0x90) 2733 #define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK (0x0F) 2734 #define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 2735 #define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5 (0x08) 2736 #define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0 (0x09) 2737 2738 /* values for SAS PHY Page 0 HwLinkRate field */ 2739 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK (0xF0) 2740 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5 (0x80) 2741 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0 (0x90) 2742 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK (0x0F) 2743 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5 (0x08) 2744 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0 (0x09) 2745 2746 /* values for SAS PHY Page 0 Flags field */ 2747 #define MPI_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2748 2749 /* values for SAS PHY Page 0 PhyInfo field */ 2750 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 2751 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR (0x00002000) 2752 #define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY (0x00001000) 2753 2754 #define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 2755 #define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 2756 2757 #define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 2758 #define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING (0x00000000) 2759 #define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 2760 #define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING (0x00000020) 2761 2762 #define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE (0x0000000F) 2763 #define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE (0x00000000) 2764 #define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED (0x00000001) 2765 #define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED (0x00000002) 2766 #define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE (0x00000003) 2767 #define MPI_SAS_PHY0_PHYINFO_RATE_1_5 (0x00000008) 2768 #define MPI_SAS_PHY0_PHYINFO_RATE_3_0 (0x00000009) 2769 2770 2771 typedef struct _CONFIG_PAGE_SAS_PHY_1 2772 { 2773 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2774 U32 Reserved1; /* 08h */ 2775 U32 InvalidDwordCount; /* 0Ch */ 2776 U32 RunningDisparityErrorCount; /* 10h */ 2777 U32 LossDwordSynchCount; /* 14h */ 2778 U32 PhyResetProblemCount; /* 18h */ 2779 } CONFIG_PAGE_SAS_PHY_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_1, 2780 SasPhyPage1_t, MPI_POINTER pSasPhyPage1_t; 2781 2782 #define MPI_SASPHY1_PAGEVERSION (0x00) 2783 2784 2785 /**************************************************************************** 2786 * SAS Enclosure Config Pages 2787 ****************************************************************************/ 2788 2789 typedef struct _CONFIG_PAGE_SAS_ENCLOSURE_0 2790 { 2791 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2792 U32 Reserved1; /* 08h */ 2793 U64 EnclosureLogicalID; /* 0Ch */ 2794 U16 Flags; /* 14h */ 2795 U16 EnclosureHandle; /* 16h */ 2796 U16 NumSlots; /* 18h */ 2797 U16 StartSlot; /* 1Ah */ 2798 U8 StartTargetID; /* 1Ch */ 2799 U8 StartBus; /* 1Dh */ 2800 U8 SEPTargetID; /* 1Eh */ 2801 U8 SEPBus; /* 1Fh */ 2802 U32 Reserved2; /* 20h */ 2803 U32 Reserved3; /* 24h */ 2804 } CONFIG_PAGE_SAS_ENCLOSURE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_ENCLOSURE_0, 2805 SasEnclosurePage0_t, MPI_POINTER pSasEnclosurePage0_t; 2806 2807 #define MPI_SASENCLOSURE0_PAGEVERSION (0x01) 2808 2809 /* values for SAS Enclosure Page 0 Flags field */ 2810 #define MPI_SAS_ENCLS0_FLAGS_SEP_BUS_ID_VALID (0x0020) 2811 #define MPI_SAS_ENCLS0_FLAGS_START_BUS_ID_VALID (0x0010) 2812 2813 #define MPI_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 2814 #define MPI_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 2815 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 2816 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 2817 #define MPI_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 2818 #define MPI_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 2819 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 2820 2821 2822 /**************************************************************************** 2823 * Log Config Pages 2824 ****************************************************************************/ 2825 /* 2826 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2827 * one and check NumLogEntries at runtime. 2828 */ 2829 #ifndef MPI_LOG_0_NUM_LOG_ENTRIES 2830 #define MPI_LOG_0_NUM_LOG_ENTRIES (1) 2831 #endif 2832 2833 #define MPI_LOG_0_LOG_DATA_LENGTH (0x1C) 2834 2835 typedef struct _MPI_LOG_0_ENTRY 2836 { 2837 U32 TimeStamp; /* 00h */ 2838 U32 Reserved1; /* 04h */ 2839 U16 LogSequence; /* 08h */ 2840 U16 LogEntryQualifier; /* 0Ah */ 2841 U8 LogData[MPI_LOG_0_LOG_DATA_LENGTH]; /* 0Ch */ 2842 } MPI_LOG_0_ENTRY, MPI_POINTER PTR_MPI_LOG_0_ENTRY, 2843 MpiLog0Entry_t, MPI_POINTER pMpiLog0Entry_t; 2844 2845 /* values for Log Page 0 LogEntry LogEntryQualifier field */ 2846 #define MPI_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 2847 #define MPI_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 2848 2849 typedef struct _CONFIG_PAGE_LOG_0 2850 { 2851 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2852 U32 Reserved1; /* 08h */ 2853 U32 Reserved2; /* 0Ch */ 2854 U16 NumLogEntries; /* 10h */ 2855 U16 Reserved3; /* 12h */ 2856 MPI_LOG_0_ENTRY LogEntry[MPI_LOG_0_NUM_LOG_ENTRIES]; /* 14h */ 2857 } CONFIG_PAGE_LOG_0, MPI_POINTER PTR_CONFIG_PAGE_LOG_0, 2858 LogPage0_t, MPI_POINTER pLogPage0_t; 2859 2860 #define MPI_LOG_0_PAGEVERSION (0x01) 2861 2862 2863 #endif 2864 2865