1 /* $FreeBSD$ */ 2 /*- 3 * SPDX-License-Identifier: BSD-3-Clause 4 * 5 * Copyright (c) 2000-2010, LSI Logic Corporation and its contributors. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions are 10 * met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * substantially similar to the "NO WARRANTY" disclaimer below 15 * ("Disclaimer") and any redistribution must be conditioned upon including 16 * a substantially similar Disclaimer requirement for further binary 17 * redistribution. 18 * 3. Neither the name of the LSI Logic Corporation nor the names of its 19 * contributors may be used to endorse or promote products derived from 20 * this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT 32 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * Name: mpi_cnfg.h 35 * Title: MPI Config message, structures, and Pages 36 * Creation Date: July 27, 2000 37 * 38 * mpi_cnfg.h Version: 01.05.19 39 * 40 * Version History 41 * --------------- 42 * 43 * Date Version Description 44 * -------- -------- ------------------------------------------------------ 45 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 46 * 06-06-00 01.00.01 Update version number for 1.0 release. 47 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages. 48 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2 49 * fields to FC_DEVICE_0 page, updated the page version. 50 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in 51 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages 52 * and updated the page versions. 53 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1 54 * page and updated the page version. 55 * Added Information field and _INFO_PARAMS_NEGOTIATED 56 * definitionto SCSI_DEVICE_0 page. 57 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the 58 * page version. 59 * Added BucketsRemaining to LAN_1 page, redefined the 60 * state values, and updated the page version. 61 * Revised bus width definitions in SCSI_PORT_0, 62 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages. 63 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page 64 * version. 65 * Moved FC_DEVICE_0 PageAddress description to spec. 66 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field 67 * widths in IOC_0 page and updated the page version. 68 * 11-02-00 01.01.01 Original release for post 1.0 work 69 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI 70 * Port Page 2, FC Port Page 4, FC Port Page 5 71 * 11-15-00 01.01.02 Interim changes to match proposals 72 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01. 73 * 12-05-00 01.01.04 Modified config page actions. 74 * 01-09-01 01.01.05 Added defines for page address formats. 75 * Data size for Manufacturing pages 2 and 3 no longer 76 * defined here. 77 * Io Unit Page 2 size is fixed at 4 adapters and some 78 * flags were changed. 79 * SCSI Port Page 2 Device Settings modified. 80 * New fields added to FC Port Page 0 and some flags 81 * cleaned up. 82 * Removed impedance flash from FC Port Page 1. 83 * Added FC Port pages 6 and 7. 84 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0. 85 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique. 86 * Added some LinkType defines for FcPortPage0. 87 * 02-20-01 01.01.08 Started using MPI_POINTER. 88 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with 89 * MPI_CONFIG_PAGETYPE_RAID_VOLUME. 90 * Added definitions and structures for IOC Page 2 and 91 * RAID Volume Page 2. 92 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9. 93 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID. 94 * Added VendorId and ProductRevLevel fields to 95 * RAIDVOL2_IM_PHYS_ID struct. 96 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_ 97 * defines to make them compatible to MPI version 1.0. 98 * Added structure offset comments. 99 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and 100 * removed some obsolete ones. 101 * Added IO Unit Page 3. 102 * Modified defines for Scsi Port Page 2. 103 * Modified RAID Volume Pages. 104 * 08-08-01 01.02.01 Original release for v1.2 work. 105 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct. 106 * Added defines for the SEP bits in RVP2 VolumeSettings. 107 * Modified the DeviceSettings field in RVP2 to use the 108 * proper structure. 109 * Added defines for SES, SAF-TE, and cross channel for 110 * IOCPage2 CapabilitiesFlags. 111 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE. 112 * Removed define for 113 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE. 114 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT. 115 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035. 116 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY 117 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY. 118 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS, 119 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and 120 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and 121 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED. 122 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED 123 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED. 124 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1. 125 * Added rejected bits to SCSI Device Page 0 Information. 126 * Increased size of ALPA array in FC Port Page 2 by one 127 * and removed a one byte reserved field. 128 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in 129 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering. 130 * Added structures for Manufacturing Page 4, IO Unit 131 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and 132 * RAID PhysDisk Page 0. 133 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK. 134 * Modified some of the new defines to make them 32 135 * character unique. 136 * Modified how variable length pages (arrays) are defined. 137 * Added generic defines for hot spare pools and RAID 138 * volume types. 139 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR. 140 * 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with 141 * related define, and bumped the page version define. 142 * 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a 143 * reserved byte and added a define. 144 * Added define for 145 * MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE. 146 * Added new config page: CONFIG_PAGE_IOC_5. 147 * Added MaxAliases, MaxHardAliases, and NumCurrentAliases 148 * fields to CONFIG_PAGE_FC_PORT_0. 149 * Added AltConnector and NumRequestedAliases fields to 150 * CONFIG_PAGE_FC_PORT_1. 151 * Added new config page: CONFIG_PAGE_FC_PORT_10. 152 * 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines. 153 * Added additional MPI_SCSIDEVPAGE0_NP_ defines. 154 * Added more MPI_SCSIDEVPAGE1_RP_ defines. 155 * Added define for 156 * MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE. 157 * Added new config page: CONFIG_PAGE_SCSI_DEVICE_3. 158 * Modified MPI_FCPORTPAGE5_FLAGS_ defines. 159 * 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define. 160 * 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0. 161 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1. 162 * Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0. 163 * 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for 164 * CONFIG_PAGE_FC_PORT_1. 165 * Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable 166 * an alias. 167 * Added more device id defines. 168 * 06-26-03 01.02.12 Added MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID define. 169 * Added TargetConfig and IDConfig fields to 170 * CONFIG_PAGE_SCSI_PORT_1. 171 * Added more PortFlags defines for CONFIG_PAGE_SCSI_PORT_2 172 * to control DV. 173 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1. 174 * In CONFIG_PAGE_FC_DEVICE_0, replaced Reserved1 field 175 * with ADISCHardALPA. 176 * Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define. 177 * 01-16-04 01.02.13 Added InitiatorDeviceTimeout and InitiatorIoPendTimeout 178 * fields and related defines to CONFIG_PAGE_FC_PORT_1. 179 * Added define for 180 * MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK. 181 * Added new fields to the substructures of 182 * CONFIG_PAGE_FC_PORT_10. 183 * 04-29-04 01.02.14 Added define for IDP bit for CONFIG_PAGE_SCSI_PORT_0, 184 * CONFIG_PAGE_SCSI_DEVICE_0, and 185 * CONFIG_PAGE_SCSI_DEVICE_1. Also bumped Page Version for 186 * these pages. 187 * 05-11-04 01.03.01 Added structure for CONFIG_PAGE_INBAND_0. 188 * 08-19-04 01.05.01 Modified MSG_CONFIG request to support extended config 189 * pages. 190 * Added a new structure for extended config page header. 191 * Added new extended config pages types and structures for 192 * SAS IO Unit, SAS Expander, SAS Device, and SAS PHY. 193 * Replaced a reserved byte in CONFIG_PAGE_MANUFACTURING_4 194 * to add a Flags field. 195 * Two new Manufacturing config pages (5 and 6). 196 * Two new bits defined for IO Unit Page 1 Flags field. 197 * Modified CONFIG_PAGE_IO_UNIT_2 to add three new fields 198 * to specify the BIOS boot device. 199 * Four new Flags bits defined for IO Unit Page 2. 200 * Added IO Unit Page 4. 201 * Added EEDP Flags settings to IOC Page 1. 202 * Added new BIOS Page 1 config page. 203 * 10-05-04 01.05.02 Added define for 204 * MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE. 205 * Added new Flags field to CONFIG_PAGE_MANUFACTURING_5 and 206 * associated defines. 207 * Added more defines for SAS IO Unit Page 0 208 * DiscoveryStatus field. 209 * Added define for MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK 210 * and MPI_SAS_IOUNIT0_DS_TABLE_LINK. 211 * Added defines for Physical Mapping Modes to SAS IO Unit 212 * Page 2. 213 * Added define for 214 * MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH. 215 * 10-27-04 01.05.03 Added defines for new SAS PHY page addressing mode. 216 * Added defines for MaxTargetSpinUp to BIOS Page 1. 217 * Added 5 new ControlFlags defines for SAS IO Unit 218 * Page 1. 219 * Added MaxNumPhysicalMappedIDs field to SAS IO Unit 220 * Page 2. 221 * Added AccessStatus field to SAS Device Page 0 and added 222 * new Flags bits for supported SATA features. 223 * 12-07-04 01.05.04 Added config page structures for BIOS Page 2, RAID 224 * Volume Page 1, and RAID Physical Disk Page 1. 225 * Replaced IO Unit Page 1 BootTargetID,BootBus, and 226 * BootAdapterNum with reserved field. 227 * Added DataScrubRate and ResyncRate to RAID Volume 228 * Page 0. 229 * Added MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT 230 * define. 231 * 12-09-04 01.05.05 Added Target Mode Large CDB Enable to FC Port Page 1 232 * Flags field. 233 * Added Auto Port Config flag define for SAS IOUNIT 234 * Page 1 ControlFlags. 235 * Added Disabled bad Phy define to Expander Page 1 236 * Discovery Info field. 237 * Added SAS/SATA device support to SAS IOUnit Page 1 238 * ControlFlags. 239 * Added Unsupported device to SAS Dev Page 0 Flags field 240 * Added disable use SATA Hash Address for SAS IOUNIT 241 * page 1 in ControlFields. 242 * 01-15-05 01.05.06 Added defaults for data scrub rate and resync rate to 243 * Manufacturing Page 4. 244 * Added new defines for BIOS Page 1 IOCSettings field. 245 * Added ExtDiskIdentifier field to RAID Physical Disk 246 * Page 0. 247 * Added new defines for SAS IO Unit Page 1 ControlFlags 248 * and to SAS Device Page 0 Flags to control SATA devices. 249 * Added defines and structures for the new Log Page 0, a 250 * new type of configuration page. 251 * 02-09-05 01.05.07 Added InactiveStatus field to RAID Volume Page 0. 252 * Added WWID field to RAID Volume Page 1. 253 * Added PhysicalPort field to SAS Expander pages 0 and 1. 254 * 03-11-05 01.05.08 Removed the EEDP flags from IOC Page 1. 255 * Added Enclosure/Slot boot device format to BIOS Page 2. 256 * New status value for RAID Volume Page 0 VolumeStatus 257 * (VolumeState subfield). 258 * New value for RAID Physical Page 0 InactiveStatus. 259 * Added Inactive Volume Member flag RAID Physical Disk 260 * Page 0 PhysDiskStatus field. 261 * New physical mapping mode in SAS IO Unit Page 2. 262 * Added CONFIG_PAGE_SAS_ENCLOSURE_0. 263 * Added Slot and Enclosure fields to SAS Device Page 0. 264 * 06-24-05 01.05.09 Added EEDP defines to IOC Page 1. 265 * Added more RAID type defines to IOC Page 2. 266 * Added Port Enable Delay settings to BIOS Page 1. 267 * Added Bad Block Table Full define to RAID Volume Page 0. 268 * Added Previous State defines to RAID Physical Disk 269 * Page 0. 270 * Added Max Sata Targets define for DiscoveryStatus field 271 * of SAS IO Unit Page 0. 272 * Added Device Self Test to Control Flags of SAS IO Unit 273 * Page 1. 274 * Added Direct Attach Starting Slot Number define for SAS 275 * IO Unit Page 2. 276 * Added new fields in SAS Device Page 2 for enclosure 277 * mapping. 278 * Added OwnerDevHandle and Flags field to SAS PHY Page 0. 279 * Added IOC GPIO Flags define to SAS Enclosure Page 0. 280 * Fixed the value for MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT. 281 * 08-03-05 01.05.10 Removed ISDataScrubRate and ISResyncRate from 282 * Manufacturing Page 4. 283 * Added MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE bit. 284 * Added NumDevsPerEnclosure field to SAS IO Unit page 2. 285 * Added MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP 286 * define. 287 * Added EnclosureHandle field to SAS Expander page 0. 288 * Removed redundant NumTableEntriesProg field from SAS 289 * Expander Page 1. 290 * 08-30-05 01.05.11 Added DeviceID for FC949E and changed the DeviceID for 291 * SAS1078. 292 * Added more defines for Manufacturing Page 4 Flags field. 293 * Added more defines for IOCSettings and added 294 * ExpanderSpinup field to Bios Page 1. 295 * Added postpone SATA Init bit to SAS IO Unit Page 1 296 * ControlFlags. 297 * Changed LogEntry format for Log Page 0. 298 * 03-27-06 01.05.12 Added two new Flags defines for Manufacturing Page 4. 299 * Added Manufacturing Page 7. 300 * Added MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING. 301 * Added IOC Page 6. 302 * Added PrevBootDeviceForm field to CONFIG_PAGE_BIOS_2. 303 * Added MaxLBAHigh field to RAID Volume Page 0. 304 * Added Nvdata version fields to SAS IO Unit Page 0. 305 * Added AdditionalControlFlags, MaxTargetPortConnectTime, 306 * ReportDeviceMissingDelay, and IODeviceMissingDelay 307 * fields to SAS IO Unit Page 1. 308 * 10-11-06 01.05.13 Added NumForceWWID field and ForceWWID array to 309 * Manufacturing Page 5. 310 * Added Manufacturing pages 8 through 10. 311 * Added defines for supported metadata size bits in 312 * CapabilitiesFlags field of IOC Page 6. 313 * Added defines for metadata size bits in VolumeSettings 314 * field of RAID Volume Page 0. 315 * Added SATA Link Reset settings, Enable SATA Asynchronous 316 * Notification bit, and HideNonZeroAttachedPhyIdentifiers 317 * bit to AdditionalControlFlags field of SAS IO Unit 318 * Page 1. 319 * Added defines for Enclosure Devices Unmapped and 320 * Device Limit Exceeded bits in Status field of SAS IO 321 * Unit Page 2. 322 * Added more AccessStatus values for SAS Device Page 0. 323 * Added bit for SATA Asynchronous Notification Support in 324 * Flags field of SAS Device Page 0. 325 * 02-28-07 01.05.14 Added ExtFlags field to Manufacturing Page 4. 326 * Added Disable SMART Polling for CapabilitiesFlags of 327 * IOC Page 6. 328 * Added Disable SMART Polling to DeviceSettings of BIOS 329 * Page 1. 330 * Added Multi-Port Domain bit for DiscoveryStatus field 331 * of SAS IO Unit Page. 332 * Added Multi-Port Domain Illegal flag for SAS IO Unit 333 * Page 1 AdditionalControlFlags field. 334 * 05-24-07 01.05.15 Added Hide Physical Disks with Non-Integrated RAID 335 * Metadata bit to Manufacturing Page 4 ExtFlags field. 336 * Added Internal Connector to End Device Present bit to 337 * Expander Page 0 Flags field. 338 * Fixed define for 339 * MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED. 340 * 08-07-07 01.05.16 Added MPI_IOCPAGE6_CAP_FLAGS_MULTIPORT_DRIVE_SUPPORT 341 * define. 342 * Added BIOS Page 4 structure. 343 * Added MPI_RAID_PHYS_DISK1_PATH_MAX define for RAID 344 * Physical Disk Page 1. 345 * 01-15-07 01.05.17 Added additional bit defines for ExtFlags field of 346 * Manufacturing Page 4. 347 * Added Solid State Drives Supported bit to IOC Page 6 348 * Capabilities Flags. 349 * Added new value for AccessStatus field of SAS Device 350 * Page 0 (_SATA_NEEDS_INITIALIZATION). 351 * 03-28-08 01.05.18 Defined new bits in Manufacturing Page 4 ExtFlags field 352 * to control coercion size and the mixing of SAS and SATA 353 * SSD drives. 354 * 07-11-08 01.05.19 Added defines MPI_MANPAGE4_EXTFLAGS_RAID0_SINGLE_DRIVE 355 * and MPI_MANPAGE4_EXTFLAGS_SSD_SCRUB_DISABLE for ExtFlags 356 * field of Manufacturing Page 4. 357 * Added defines for a new bit in BIOS Page 1 BiosOptions 358 * field to control adapter scan order. 359 * Added BootDeviceWaitTime field to SAS IO Unit Page 2. 360 * Added MPI_SAS_PHY0_PHYINFO_PHY_VACANT for use in PhyInfo 361 * field of SAS Expander Page 1. 362 * -------------------------------------------------------------------------- 363 */ 364 365 #ifndef MPI_CNFG_H 366 #define MPI_CNFG_H 367 368 369 /***************************************************************************** 370 * 371 * C o n f i g M e s s a g e a n d S t r u c t u r e s 372 * 373 *****************************************************************************/ 374 375 typedef struct _CONFIG_PAGE_HEADER 376 { 377 U8 PageVersion; /* 00h */ 378 U8 PageLength; /* 01h */ 379 U8 PageNumber; /* 02h */ 380 U8 PageType; /* 03h */ 381 } CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER, 382 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t; 383 384 typedef union _CONFIG_PAGE_HEADER_UNION 385 { 386 ConfigPageHeader_t Struct; 387 U8 Bytes[4]; 388 U16 Word16[2]; 389 U32 Word32; 390 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion, 391 CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION; 392 393 typedef struct _CONFIG_EXTENDED_PAGE_HEADER 394 { 395 U8 PageVersion; /* 00h */ 396 U8 Reserved1; /* 01h */ 397 U8 PageNumber; /* 02h */ 398 U8 PageType; /* 03h */ 399 U16 ExtPageLength; /* 04h */ 400 U8 ExtPageType; /* 06h */ 401 U8 Reserved2; /* 07h */ 402 } CONFIG_EXTENDED_PAGE_HEADER, MPI_POINTER PTR_CONFIG_EXTENDED_PAGE_HEADER, 403 ConfigExtendedPageHeader_t, MPI_POINTER pConfigExtendedPageHeader_t; 404 405 406 407 /**************************************************************************** 408 * PageType field values 409 ****************************************************************************/ 410 #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00) 411 #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10) 412 #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20) 413 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30) 414 #define MPI_CONFIG_PAGEATTR_MASK (0xF0) 415 416 #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00) 417 #define MPI_CONFIG_PAGETYPE_IOC (0x01) 418 #define MPI_CONFIG_PAGETYPE_BIOS (0x02) 419 #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03) 420 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04) 421 #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05) 422 #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06) 423 #define MPI_CONFIG_PAGETYPE_LAN (0x07) 424 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 425 #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09) 426 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 427 #define MPI_CONFIG_PAGETYPE_INBAND (0x0B) 428 #define MPI_CONFIG_PAGETYPE_EXTENDED (0x0F) 429 #define MPI_CONFIG_PAGETYPE_MASK (0x0F) 430 431 #define MPI_CONFIG_TYPENUM_MASK (0x0FFF) 432 433 434 /**************************************************************************** 435 * ExtPageType field values 436 ****************************************************************************/ 437 #define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 438 #define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 439 #define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 440 #define MPI_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 441 #define MPI_CONFIG_EXTPAGETYPE_LOG (0x14) 442 #define MPI_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 443 444 445 /**************************************************************************** 446 * PageAddress field values 447 ****************************************************************************/ 448 #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF) 449 450 #define MPI_SCSI_DEVICE_FORM_MASK (0xF0000000) 451 #define MPI_SCSI_DEVICE_FORM_BUS_TID (0x00000000) 452 #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF) 453 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0) 454 #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00) 455 #define MPI_SCSI_DEVICE_BUS_SHIFT (8) 456 #define MPI_SCSI_DEVICE_FORM_TARGET_MODE (0x10000000) 457 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_MASK (0x000000FF) 458 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_SHIFT (0) 459 #define MPI_SCSI_DEVICE_TM_BUS_MASK (0x0000FF00) 460 #define MPI_SCSI_DEVICE_TM_BUS_SHIFT (8) 461 #define MPI_SCSI_DEVICE_TM_INIT_ID_MASK (0x00FF0000) 462 #define MPI_SCSI_DEVICE_TM_INIT_ID_SHIFT (16) 463 464 #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000) 465 #define MPI_FC_PORT_PGAD_PORT_SHIFT (28) 466 #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000) 467 #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000) 468 #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF) 469 #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0) 470 471 #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000) 472 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28) 473 #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000) 474 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000) 475 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000) 476 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28) 477 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF) 478 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0) 479 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000) 480 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 481 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8) 482 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 483 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0) 484 485 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 486 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0) 487 488 #define MPI_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 489 #define MPI_SAS_EXPAND_PGAD_FORM_SHIFT (28) 490 #define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 491 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x00000001) 492 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE (0x00000002) 493 #define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE (0x0000FFFF) 494 #define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE (0) 495 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY (0x00FF0000) 496 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY (16) 497 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE (0x0000FFFF) 498 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE (0) 499 #define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE (0x0000FFFF) 500 #define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE (0) 501 502 #define MPI_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 503 #define MPI_SAS_DEVICE_PGAD_FORM_SHIFT (28) 504 #define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 505 #define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID (0x00000001) 506 #define MPI_SAS_DEVICE_PGAD_FORM_HANDLE (0x00000002) 507 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK (0x0000FFFF) 508 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT (0) 509 #define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 510 #define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT (8) 511 #define MPI_SAS_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 512 #define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT (0) 513 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK (0x0000FFFF) 514 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT (0) 515 516 #define MPI_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 517 #define MPI_SAS_PHY_PGAD_FORM_SHIFT (28) 518 #define MPI_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x0) 519 #define MPI_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x1) 520 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 521 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (0) 522 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 523 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_SHIFT (0) 524 525 #define MPI_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 526 #define MPI_SAS_ENCLOS_PGAD_FORM_SHIFT (28) 527 #define MPI_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 528 #define MPI_SAS_ENCLOS_PGAD_FORM_HANDLE (0x00000001) 529 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_MASK (0x0000FFFF) 530 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_SHIFT (0) 531 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_MASK (0x0000FFFF) 532 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_SHIFT (0) 533 534 535 536 /**************************************************************************** 537 * Config Request Message 538 ****************************************************************************/ 539 typedef struct _MSG_CONFIG 540 { 541 U8 Action; /* 00h */ 542 U8 Reserved; /* 01h */ 543 U8 ChainOffset; /* 02h */ 544 U8 Function; /* 03h */ 545 U16 ExtPageLength; /* 04h */ 546 U8 ExtPageType; /* 06h */ 547 U8 MsgFlags; /* 07h */ 548 U32 MsgContext; /* 08h */ 549 U8 Reserved2[8]; /* 0Ch */ 550 CONFIG_PAGE_HEADER Header; /* 14h */ 551 U32 PageAddress; /* 18h */ 552 SGE_IO_UNION PageBufferSGE; /* 1Ch */ 553 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG, 554 Config_t, MPI_POINTER pConfig_t; 555 556 557 /**************************************************************************** 558 * Action field values 559 ****************************************************************************/ 560 #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00) 561 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 562 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 563 #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03) 564 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 565 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 566 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 567 568 569 /* Config Reply Message */ 570 typedef struct _MSG_CONFIG_REPLY 571 { 572 U8 Action; /* 00h */ 573 U8 Reserved; /* 01h */ 574 U8 MsgLength; /* 02h */ 575 U8 Function; /* 03h */ 576 U16 ExtPageLength; /* 04h */ 577 U8 ExtPageType; /* 06h */ 578 U8 MsgFlags; /* 07h */ 579 U32 MsgContext; /* 08h */ 580 U8 Reserved2[2]; /* 0Ch */ 581 U16 IOCStatus; /* 0Eh */ 582 U32 IOCLogInfo; /* 10h */ 583 CONFIG_PAGE_HEADER Header; /* 14h */ 584 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY, 585 ConfigReply_t, MPI_POINTER pConfigReply_t; 586 587 588 589 /***************************************************************************** 590 * 591 * C o n f i g u r a t i o n P a g e s 592 * 593 *****************************************************************************/ 594 595 /**************************************************************************** 596 * Manufacturing Config pages 597 ****************************************************************************/ 598 #define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000) 599 /* Fibre Channel */ 600 #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621) 601 #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624) 602 #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622) 603 #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628) 604 #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626) 605 #define MPI_MANUFACTPAGE_DEVICEID_FC939X (0x0642) 606 #define MPI_MANUFACTPAGE_DEVICEID_FC949X (0x0640) 607 #define MPI_MANUFACTPAGE_DEVICEID_FC949E (0x0646) 608 /* SCSI */ 609 #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030) 610 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031) 611 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032) 612 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033) 613 #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040) 614 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041) 615 /* SAS */ 616 #define MPI_MANUFACTPAGE_DEVID_SAS1064 (0x0050) 617 #define MPI_MANUFACTPAGE_DEVID_SAS1064A (0x005C) 618 #define MPI_MANUFACTPAGE_DEVID_SAS1064E (0x0056) 619 #define MPI_MANUFACTPAGE_DEVID_SAS1066 (0x005E) 620 #define MPI_MANUFACTPAGE_DEVID_SAS1066E (0x005A) 621 #define MPI_MANUFACTPAGE_DEVID_SAS1068 (0x0054) 622 #define MPI_MANUFACTPAGE_DEVID_SAS1068E (0x0058) 623 #define MPI_MANUFACTPAGE_DEVID_SAS1078 (0x0062) 624 625 626 typedef struct _CONFIG_PAGE_MANUFACTURING_0 627 { 628 CONFIG_PAGE_HEADER Header; /* 00h */ 629 U8 ChipName[16]; /* 04h */ 630 U8 ChipRevision[8]; /* 14h */ 631 U8 BoardName[16]; /* 1Ch */ 632 U8 BoardAssembly[16]; /* 2Ch */ 633 U8 BoardTracerNumber[16]; /* 3Ch */ 634 635 } CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0, 636 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t; 637 638 #define MPI_MANUFACTURING0_PAGEVERSION (0x00) 639 640 641 typedef struct _CONFIG_PAGE_MANUFACTURING_1 642 { 643 CONFIG_PAGE_HEADER Header; /* 00h */ 644 U8 VPD[256]; /* 04h */ 645 } CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1, 646 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t; 647 648 #define MPI_MANUFACTURING1_PAGEVERSION (0x00) 649 650 651 typedef struct _MPI_CHIP_REVISION_ID 652 { 653 U16 DeviceID; /* 00h */ 654 U8 PCIRevisionID; /* 02h */ 655 U8 Reserved; /* 03h */ 656 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID, 657 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t; 658 659 660 /* 661 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 662 * one and check Header.PageLength at runtime. 663 */ 664 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS 665 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 666 #endif 667 668 typedef struct _CONFIG_PAGE_MANUFACTURING_2 669 { 670 CONFIG_PAGE_HEADER Header; /* 00h */ 671 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 672 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */ 673 } CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2, 674 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t; 675 676 #define MPI_MANUFACTURING2_PAGEVERSION (0x00) 677 678 679 /* 680 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 681 * one and check Header.PageLength at runtime. 682 */ 683 #ifndef MPI_MAN_PAGE_3_INFO_WORDS 684 #define MPI_MAN_PAGE_3_INFO_WORDS (1) 685 #endif 686 687 typedef struct _CONFIG_PAGE_MANUFACTURING_3 688 { 689 CONFIG_PAGE_HEADER Header; /* 00h */ 690 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 691 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */ 692 } CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3, 693 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t; 694 695 #define MPI_MANUFACTURING3_PAGEVERSION (0x00) 696 697 698 typedef struct _CONFIG_PAGE_MANUFACTURING_4 699 { 700 CONFIG_PAGE_HEADER Header; /* 00h */ 701 U32 Reserved1; /* 04h */ 702 U8 InfoOffset0; /* 08h */ 703 U8 InfoSize0; /* 09h */ 704 U8 InfoOffset1; /* 0Ah */ 705 U8 InfoSize1; /* 0Bh */ 706 U8 InquirySize; /* 0Ch */ 707 U8 Flags; /* 0Dh */ 708 U16 ExtFlags; /* 0Eh */ 709 U8 InquiryData[56]; /* 10h */ 710 U32 ISVolumeSettings; /* 48h */ 711 U32 IMEVolumeSettings; /* 4Ch */ 712 U32 IMVolumeSettings; /* 50h */ 713 U32 Reserved3; /* 54h */ 714 U32 Reserved4; /* 58h */ 715 U32 Reserved5; /* 5Ch */ 716 U8 IMEDataScrubRate; /* 60h */ 717 U8 IMEResyncRate; /* 61h */ 718 U16 Reserved6; /* 62h */ 719 U8 IMDataScrubRate; /* 64h */ 720 U8 IMResyncRate; /* 65h */ 721 U16 Reserved7; /* 66h */ 722 U32 Reserved8; /* 68h */ 723 U32 Reserved9; /* 6Ch */ 724 } CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4, 725 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t; 726 727 #define MPI_MANUFACTURING4_PAGEVERSION (0x05) 728 729 /* defines for the Flags field */ 730 #define MPI_MANPAGE4_FORCE_BAD_BLOCK_TABLE (0x80) 731 #define MPI_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x40) 732 #define MPI_MANPAGE4_IME_DISABLE (0x20) 733 #define MPI_MANPAGE4_IM_DISABLE (0x10) 734 #define MPI_MANPAGE4_IS_DISABLE (0x08) 735 #define MPI_MANPAGE4_IR_MODEPAGE8_DISABLE (0x04) 736 #define MPI_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x02) 737 #define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA (0x01) 738 739 /* defines for the ExtFlags field */ 740 #define MPI_MANPAGE4_EXTFLAGS_RAID0_SINGLE_DRIVE (0x0400) 741 #define MPI_MANPAGE4_EXTFLAGS_SSD_SCRUB_DISABLE (0x0200) 742 #define MPI_MANPAGE4_EXTFLAGS_MASK_COERCION_SIZE (0x0180) 743 #define MPI_MANPAGE4_EXTFLAGS_SHIFT_COERCION_SIZE (7) 744 #define MPI_MANPAGE4_EXTFLAGS_1GB_COERCION_SIZE (0) 745 #define MPI_MANPAGE4_EXTFLAGS_128MB_COERCION_SIZE (1) 746 747 #define MPI_MANPAGE4_EXTFLAGS_NO_MIX_SSD_SAS_SATA (0x0040) 748 #define MPI_MANPAGE4_EXTFLAGS_MIX_SSD_AND_NON_SSD (0x0020) 749 #define MPI_MANPAGE4_EXTFLAGS_DUAL_PORT_SUPPORT (0x0010) 750 #define MPI_MANPAGE4_EXTFLAGS_HIDE_NON_IR_METADATA (0x0008) 751 #define MPI_MANPAGE4_EXTFLAGS_SAS_CACHE_DISABLE (0x0004) 752 #define MPI_MANPAGE4_EXTFLAGS_SATA_CACHE_DISABLE (0x0002) 753 #define MPI_MANPAGE4_EXTFLAGS_LEGACY_MODE (0x0001) 754 755 756 #ifndef MPI_MANPAGE5_NUM_FORCEWWID 757 #define MPI_MANPAGE5_NUM_FORCEWWID (1) 758 #endif 759 760 typedef struct _CONFIG_PAGE_MANUFACTURING_5 761 { 762 CONFIG_PAGE_HEADER Header; /* 00h */ 763 U64 BaseWWID; /* 04h */ 764 U8 Flags; /* 0Ch */ 765 U8 NumForceWWID; /* 0Dh */ 766 U16 Reserved2; /* 0Eh */ 767 U32 Reserved3; /* 10h */ 768 U32 Reserved4; /* 14h */ 769 U64 ForceWWID[MPI_MANPAGE5_NUM_FORCEWWID]; /* 18h */ 770 } CONFIG_PAGE_MANUFACTURING_5, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_5, 771 ManufacturingPage5_t, MPI_POINTER pManufacturingPage5_t; 772 773 #define MPI_MANUFACTURING5_PAGEVERSION (0x02) 774 775 /* defines for the Flags field */ 776 #define MPI_MANPAGE5_TWO_WWID_PER_PHY (0x01) 777 778 779 typedef struct _CONFIG_PAGE_MANUFACTURING_6 780 { 781 CONFIG_PAGE_HEADER Header; /* 00h */ 782 U32 ProductSpecificInfo;/* 04h */ 783 } CONFIG_PAGE_MANUFACTURING_6, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_6, 784 ManufacturingPage6_t, MPI_POINTER pManufacturingPage6_t; 785 786 #define MPI_MANUFACTURING6_PAGEVERSION (0x00) 787 788 789 typedef struct _MPI_MANPAGE7_CONNECTOR_INFO 790 { 791 U32 Pinout; /* 00h */ 792 U8 Connector[16]; /* 04h */ 793 U8 Location; /* 14h */ 794 U8 Reserved1; /* 15h */ 795 U16 Slot; /* 16h */ 796 U32 Reserved2; /* 18h */ 797 } MPI_MANPAGE7_CONNECTOR_INFO, MPI_POINTER PTR_MPI_MANPAGE7_CONNECTOR_INFO, 798 MpiManPage7ConnectorInfo_t, MPI_POINTER pMpiManPage7ConnectorInfo_t; 799 800 /* defines for the Pinout field */ 801 #define MPI_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000) 802 #define MPI_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000) 803 #define MPI_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000) 804 #define MPI_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000) 805 #define MPI_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800) 806 #define MPI_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400) 807 #define MPI_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200) 808 #define MPI_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100) 809 #define MPI_MANPAGE7_PINOUT_SFF_8482 (0x00000002) 810 #define MPI_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001) 811 812 /* defines for the Location field */ 813 #define MPI_MANPAGE7_LOCATION_UNKNOWN (0x01) 814 #define MPI_MANPAGE7_LOCATION_INTERNAL (0x02) 815 #define MPI_MANPAGE7_LOCATION_EXTERNAL (0x04) 816 #define MPI_MANPAGE7_LOCATION_SWITCHABLE (0x08) 817 #define MPI_MANPAGE7_LOCATION_AUTO (0x10) 818 #define MPI_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 819 #define MPI_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 820 821 /* 822 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 823 * one and check NumPhys at runtime. 824 */ 825 #ifndef MPI_MANPAGE7_CONNECTOR_INFO_MAX 826 #define MPI_MANPAGE7_CONNECTOR_INFO_MAX (1) 827 #endif 828 829 typedef struct _CONFIG_PAGE_MANUFACTURING_7 830 { 831 CONFIG_PAGE_HEADER Header; /* 00h */ 832 U32 Reserved1; /* 04h */ 833 U32 Reserved2; /* 08h */ 834 U32 Flags; /* 0Ch */ 835 U8 EnclosureName[16]; /* 10h */ 836 U8 NumPhys; /* 20h */ 837 U8 Reserved3; /* 21h */ 838 U16 Reserved4; /* 22h */ 839 MPI_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI_MANPAGE7_CONNECTOR_INFO_MAX]; /* 24h */ 840 } CONFIG_PAGE_MANUFACTURING_7, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_7, 841 ManufacturingPage7_t, MPI_POINTER pManufacturingPage7_t; 842 843 #define MPI_MANUFACTURING7_PAGEVERSION (0x00) 844 845 /* defines for the Flags field */ 846 #define MPI_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 847 848 849 typedef struct _CONFIG_PAGE_MANUFACTURING_8 850 { 851 CONFIG_PAGE_HEADER Header; /* 00h */ 852 U32 ProductSpecificInfo;/* 04h */ 853 } CONFIG_PAGE_MANUFACTURING_8, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_8, 854 ManufacturingPage8_t, MPI_POINTER pManufacturingPage8_t; 855 856 #define MPI_MANUFACTURING8_PAGEVERSION (0x00) 857 858 859 typedef struct _CONFIG_PAGE_MANUFACTURING_9 860 { 861 CONFIG_PAGE_HEADER Header; /* 00h */ 862 U32 ProductSpecificInfo;/* 04h */ 863 } CONFIG_PAGE_MANUFACTURING_9, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_9, 864 ManufacturingPage9_t, MPI_POINTER pManufacturingPage9_t; 865 866 #define MPI_MANUFACTURING9_PAGEVERSION (0x00) 867 868 869 typedef struct _CONFIG_PAGE_MANUFACTURING_10 870 { 871 CONFIG_PAGE_HEADER Header; /* 00h */ 872 U32 ProductSpecificInfo;/* 04h */ 873 } CONFIG_PAGE_MANUFACTURING_10, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_10, 874 ManufacturingPage10_t, MPI_POINTER pManufacturingPage10_t; 875 876 #define MPI_MANUFACTURING10_PAGEVERSION (0x00) 877 878 879 /**************************************************************************** 880 * IO Unit Config Pages 881 ****************************************************************************/ 882 883 typedef struct _CONFIG_PAGE_IO_UNIT_0 884 { 885 CONFIG_PAGE_HEADER Header; /* 00h */ 886 U64 UniqueValue; /* 04h */ 887 } CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0, 888 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t; 889 890 #define MPI_IOUNITPAGE0_PAGEVERSION (0x00) 891 892 893 typedef struct _CONFIG_PAGE_IO_UNIT_1 894 { 895 CONFIG_PAGE_HEADER Header; /* 00h */ 896 U32 Flags; /* 04h */ 897 } CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1, 898 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t; 899 900 #define MPI_IOUNITPAGE1_PAGEVERSION (0x02) 901 902 /* IO Unit Page 1 Flags defines */ 903 #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000) 904 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001) 905 #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002) 906 #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000) 907 #define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 908 #define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING (0x00000020) 909 #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040) 910 #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080) 911 #define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 912 #define MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE (0x00000200) 913 914 typedef struct _MPI_ADAPTER_INFO 915 { 916 U8 PciBusNumber; /* 00h */ 917 U8 PciDeviceAndFunctionNumber; /* 01h */ 918 U16 AdapterFlags; /* 02h */ 919 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO, 920 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t; 921 922 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 923 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 924 925 typedef struct _CONFIG_PAGE_IO_UNIT_2 926 { 927 CONFIG_PAGE_HEADER Header; /* 00h */ 928 U32 Flags; /* 04h */ 929 U32 BiosVersion; /* 08h */ 930 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */ 931 U32 Reserved1; /* 1Ch */ 932 } CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2, 933 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t; 934 935 #define MPI_IOUNITPAGE2_PAGEVERSION (0x02) 936 937 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002) 938 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004) 939 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008) 940 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010) 941 942 #define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 943 #define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 944 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY (0x00000020) 945 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 946 947 948 /* 949 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 950 * one and check Header.PageLength at runtime. 951 */ 952 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX 953 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 954 #endif 955 956 typedef struct _CONFIG_PAGE_IO_UNIT_3 957 { 958 CONFIG_PAGE_HEADER Header; /* 00h */ 959 U8 GPIOCount; /* 04h */ 960 U8 Reserved1; /* 05h */ 961 U16 Reserved2; /* 06h */ 962 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */ 963 } CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3, 964 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t; 965 966 #define MPI_IOUNITPAGE3_PAGEVERSION (0x01) 967 968 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC) 969 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 970 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00) 971 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01) 972 973 974 typedef struct _CONFIG_PAGE_IO_UNIT_4 975 { 976 CONFIG_PAGE_HEADER Header; /* 00h */ 977 U32 Reserved1; /* 04h */ 978 SGE_SIMPLE_UNION FWImageSGE; /* 08h */ 979 } CONFIG_PAGE_IO_UNIT_4, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_4, 980 IOUnitPage4_t, MPI_POINTER pIOUnitPage4_t; 981 982 #define MPI_IOUNITPAGE4_PAGEVERSION (0x00) 983 984 985 /**************************************************************************** 986 * IOC Config Pages 987 ****************************************************************************/ 988 989 typedef struct _CONFIG_PAGE_IOC_0 990 { 991 CONFIG_PAGE_HEADER Header; /* 00h */ 992 U32 TotalNVStore; /* 04h */ 993 U32 FreeNVStore; /* 08h */ 994 U16 VendorID; /* 0Ch */ 995 U16 DeviceID; /* 0Eh */ 996 U8 RevisionID; /* 10h */ 997 U8 Reserved[3]; /* 11h */ 998 U32 ClassCode; /* 14h */ 999 U16 SubsystemVendorID; /* 18h */ 1000 U16 SubsystemID; /* 1Ah */ 1001 } CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0, 1002 IOCPage0_t, MPI_POINTER pIOCPage0_t; 1003 1004 #define MPI_IOCPAGE0_PAGEVERSION (0x01) 1005 1006 1007 typedef struct _CONFIG_PAGE_IOC_1 1008 { 1009 CONFIG_PAGE_HEADER Header; /* 00h */ 1010 U32 Flags; /* 04h */ 1011 U32 CoalescingTimeout; /* 08h */ 1012 U8 CoalescingDepth; /* 0Ch */ 1013 U8 PCISlotNum; /* 0Dh */ 1014 U8 Reserved[2]; /* 0Eh */ 1015 } CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1, 1016 IOCPage1_t, MPI_POINTER pIOCPage1_t; 1017 1018 #define MPI_IOCPAGE1_PAGEVERSION (0x03) 1019 1020 /* defines for the Flags field */ 1021 #define MPI_IOCPAGE1_EEDP_MODE_MASK (0x07000000) 1022 #define MPI_IOCPAGE1_EEDP_MODE_OFF (0x00000000) 1023 #define MPI_IOCPAGE1_EEDP_MODE_T10 (0x01000000) 1024 #define MPI_IOCPAGE1_EEDP_MODE_LSI_1 (0x02000000) 1025 #define MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE (0x00000010) 1026 #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001) 1027 1028 #define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1029 1030 1031 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL 1032 { 1033 U8 VolumeID; /* 00h */ 1034 U8 VolumeBus; /* 01h */ 1035 U8 VolumeIOC; /* 02h */ 1036 U8 VolumePageNumber; /* 03h */ 1037 U8 VolumeType; /* 04h */ 1038 U8 Flags; /* 05h */ 1039 U16 Reserved3; /* 06h */ 1040 } CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL, 1041 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t; 1042 1043 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */ 1044 1045 #define MPI_RAID_VOL_TYPE_IS (0x00) 1046 #define MPI_RAID_VOL_TYPE_IME (0x01) 1047 #define MPI_RAID_VOL_TYPE_IM (0x02) 1048 #define MPI_RAID_VOL_TYPE_RAID_5 (0x03) 1049 #define MPI_RAID_VOL_TYPE_RAID_6 (0x04) 1050 #define MPI_RAID_VOL_TYPE_RAID_10 (0x05) 1051 #define MPI_RAID_VOL_TYPE_RAID_50 (0x06) 1052 #define MPI_RAID_VOL_TYPE_UNKNOWN (0xFF) 1053 1054 /* IOC Page 2 Volume Flags values */ 1055 1056 #define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08) 1057 1058 /* 1059 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1060 * one and check Header.PageLength at runtime. 1061 */ 1062 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX 1063 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1) 1064 #endif 1065 1066 typedef struct _CONFIG_PAGE_IOC_2 1067 { 1068 CONFIG_PAGE_HEADER Header; /* 00h */ 1069 U32 CapabilitiesFlags; /* 04h */ 1070 U8 NumActiveVolumes; /* 08h */ 1071 U8 MaxVolumes; /* 09h */ 1072 U8 NumActivePhysDisks; /* 0Ah */ 1073 U8 MaxPhysDisks; /* 0Bh */ 1074 CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */ 1075 } CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2, 1076 IOCPage2_t, MPI_POINTER pIOCPage2_t; 1077 1078 #define MPI_IOCPAGE2_PAGEVERSION (0x04) 1079 1080 /* IOC Page 2 Capabilities flags */ 1081 1082 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001) 1083 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002) 1084 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004) 1085 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_5_SUPPORT (0x00000008) 1086 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_6_SUPPORT (0x00000010) 1087 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_10_SUPPORT (0x00000020) 1088 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_50_SUPPORT (0x00000040) 1089 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING (0x10000000) 1090 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000) 1091 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000) 1092 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000) 1093 1094 1095 typedef struct _IOC_3_PHYS_DISK 1096 { 1097 U8 PhysDiskID; /* 00h */ 1098 U8 PhysDiskBus; /* 01h */ 1099 U8 PhysDiskIOC; /* 02h */ 1100 U8 PhysDiskNum; /* 03h */ 1101 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK, 1102 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t; 1103 1104 /* 1105 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1106 * one and check Header.PageLength at runtime. 1107 */ 1108 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX 1109 #define MPI_IOC_PAGE_3_PHYSDISK_MAX (1) 1110 #endif 1111 1112 typedef struct _CONFIG_PAGE_IOC_3 1113 { 1114 CONFIG_PAGE_HEADER Header; /* 00h */ 1115 U8 NumPhysDisks; /* 04h */ 1116 U8 Reserved1; /* 05h */ 1117 U16 Reserved2; /* 06h */ 1118 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */ 1119 } CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3, 1120 IOCPage3_t, MPI_POINTER pIOCPage3_t; 1121 1122 #define MPI_IOCPAGE3_PAGEVERSION (0x00) 1123 1124 1125 typedef struct _IOC_4_SEP 1126 { 1127 U8 SEPTargetID; /* 00h */ 1128 U8 SEPBus; /* 01h */ 1129 U16 Reserved; /* 02h */ 1130 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP, 1131 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t; 1132 1133 /* 1134 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1135 * one and check Header.PageLength at runtime. 1136 */ 1137 #ifndef MPI_IOC_PAGE_4_SEP_MAX 1138 #define MPI_IOC_PAGE_4_SEP_MAX (1) 1139 #endif 1140 1141 typedef struct _CONFIG_PAGE_IOC_4 1142 { 1143 CONFIG_PAGE_HEADER Header; /* 00h */ 1144 U8 ActiveSEP; /* 04h */ 1145 U8 MaxSEP; /* 05h */ 1146 U16 Reserved1; /* 06h */ 1147 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */ 1148 } CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4, 1149 IOCPage4_t, MPI_POINTER pIOCPage4_t; 1150 1151 #define MPI_IOCPAGE4_PAGEVERSION (0x00) 1152 1153 1154 typedef struct _IOC_5_HOT_SPARE 1155 { 1156 U8 PhysDiskNum; /* 00h */ 1157 U8 Reserved; /* 01h */ 1158 U8 HotSparePool; /* 02h */ 1159 U8 Flags; /* 03h */ 1160 } IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE, 1161 Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t; 1162 1163 /* IOC Page 5 HotSpare Flags */ 1164 #define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01) 1165 1166 /* 1167 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1168 * one and check Header.PageLength at runtime. 1169 */ 1170 #ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX 1171 #define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1) 1172 #endif 1173 1174 typedef struct _CONFIG_PAGE_IOC_5 1175 { 1176 CONFIG_PAGE_HEADER Header; /* 00h */ 1177 U32 Reserved1; /* 04h */ 1178 U8 NumHotSpares; /* 08h */ 1179 U8 Reserved2; /* 09h */ 1180 U16 Reserved3; /* 0Ah */ 1181 IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */ 1182 } CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5, 1183 IOCPage5_t, MPI_POINTER pIOCPage5_t; 1184 1185 #define MPI_IOCPAGE5_PAGEVERSION (0x00) 1186 1187 typedef struct _CONFIG_PAGE_IOC_6 1188 { 1189 CONFIG_PAGE_HEADER Header; /* 00h */ 1190 U32 CapabilitiesFlags; /* 04h */ 1191 U8 MaxDrivesIS; /* 08h */ 1192 U8 MaxDrivesIM; /* 09h */ 1193 U8 MaxDrivesIME; /* 0Ah */ 1194 U8 Reserved1; /* 0Bh */ 1195 U8 MinDrivesIS; /* 0Ch */ 1196 U8 MinDrivesIM; /* 0Dh */ 1197 U8 MinDrivesIME; /* 0Eh */ 1198 U8 Reserved2; /* 0Fh */ 1199 U8 MaxGlobalHotSpares; /* 10h */ 1200 U8 Reserved3; /* 11h */ 1201 U16 Reserved4; /* 12h */ 1202 U32 Reserved5; /* 14h */ 1203 U32 SupportedStripeSizeMapIS; /* 18h */ 1204 U32 SupportedStripeSizeMapIME; /* 1Ch */ 1205 U32 Reserved6; /* 20h */ 1206 U8 MetadataSize; /* 24h */ 1207 U8 Reserved7; /* 25h */ 1208 U16 Reserved8; /* 26h */ 1209 U16 MaxBadBlockTableEntries; /* 28h */ 1210 U16 Reserved9; /* 2Ah */ 1211 U16 IRNvsramUsage; /* 2Ch */ 1212 U16 Reserved10; /* 2Eh */ 1213 U32 IRNvsramVersion; /* 30h */ 1214 U32 Reserved11; /* 34h */ 1215 U32 Reserved12; /* 38h */ 1216 } CONFIG_PAGE_IOC_6, MPI_POINTER PTR_CONFIG_PAGE_IOC_6, 1217 IOCPage6_t, MPI_POINTER pIOCPage6_t; 1218 1219 #define MPI_IOCPAGE6_PAGEVERSION (0x01) 1220 1221 /* IOC Page 6 Capabilities Flags */ 1222 1223 #define MPI_IOCPAGE6_CAP_FLAGS_SSD_SUPPORT (0x00000020) 1224 #define MPI_IOCPAGE6_CAP_FLAGS_MULTIPORT_DRIVE_SUPPORT (0x00000010) 1225 #define MPI_IOCPAGE6_CAP_FLAGS_DISABLE_SMART_POLLING (0x00000008) 1226 1227 #define MPI_IOCPAGE6_CAP_FLAGS_MASK_METADATA_SIZE (0x00000006) 1228 #define MPI_IOCPAGE6_CAP_FLAGS_64MB_METADATA_SIZE (0x00000000) 1229 #define MPI_IOCPAGE6_CAP_FLAGS_512MB_METADATA_SIZE (0x00000002) 1230 1231 #define MPI_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1232 1233 1234 /**************************************************************************** 1235 * BIOS Config Pages 1236 ****************************************************************************/ 1237 1238 typedef struct _CONFIG_PAGE_BIOS_1 1239 { 1240 CONFIG_PAGE_HEADER Header; /* 00h */ 1241 U32 BiosOptions; /* 04h */ 1242 U32 IOCSettings; /* 08h */ 1243 U32 Reserved1; /* 0Ch */ 1244 U32 DeviceSettings; /* 10h */ 1245 U16 NumberOfDevices; /* 14h */ 1246 U8 ExpanderSpinup; /* 16h */ 1247 U8 Reserved2; /* 17h */ 1248 U16 IOTimeoutBlockDevicesNonRM; /* 18h */ 1249 U16 IOTimeoutSequential; /* 1Ah */ 1250 U16 IOTimeoutOther; /* 1Ch */ 1251 U16 IOTimeoutBlockDevicesRM; /* 1Eh */ 1252 } CONFIG_PAGE_BIOS_1, MPI_POINTER PTR_CONFIG_PAGE_BIOS_1, 1253 BIOSPage1_t, MPI_POINTER pBIOSPage1_t; 1254 1255 #define MPI_BIOSPAGE1_PAGEVERSION (0x03) 1256 1257 /* values for the BiosOptions field */ 1258 #define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE (0x00000400) 1259 #define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE (0x00000200) 1260 #define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE (0x00000100) 1261 1262 #define MPI_BIOSPAGE1_OPTIONS_SCAN_HIGH_TO_LOW (0x00000002) 1263 #define MPI_BIOSPAGE1_OPTIONS_SCAN_LOW_TO_HIGH (0x00000000) 1264 1265 #define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1266 1267 /* values for the IOCSettings field */ 1268 #define MPI_BIOSPAGE1_IOCSET_MASK_INITIAL_SPINUP_DELAY (0x0F000000) 1269 #define MPI_BIOSPAGE1_IOCSET_SHIFT_INITIAL_SPINUP_DELAY (24) 1270 1271 #define MPI_BIOSPAGE1_IOCSET_MASK_PORT_ENABLE_DELAY (0x00F00000) 1272 #define MPI_BIOSPAGE1_IOCSET_SHIFT_PORT_ENABLE_DELAY (20) 1273 1274 #define MPI_BIOSPAGE1_IOCSET_AUTO_PORT_ENABLE (0x00080000) 1275 #define MPI_BIOSPAGE1_IOCSET_DIRECT_ATTACH_SPINUP_MODE (0x00040000) 1276 1277 #define MPI_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1278 #define MPI_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1279 #define MPI_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1280 1281 #define MPI_BIOSPAGE1_IOCSET_MASK_MAX_TARGET_SPIN_UP (0x0000F000) 1282 #define MPI_BIOSPAGE1_IOCSET_SHIFT_MAX_TARGET_SPIN_UP (12) 1283 1284 #define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY (0x00000F00) 1285 #define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY (8) 1286 1287 #define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1288 #define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1289 #define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1290 #define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1291 1292 #define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1293 #define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1294 #define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1295 #define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1296 #define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1297 1298 #define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1299 1300 /* values for the DeviceSettings field */ 1301 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1302 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1303 #define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1304 #define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1305 #define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1306 1307 /* defines for the ExpanderSpinup field */ 1308 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_MAX_TARGET (0xF0) 1309 #define MPI_BIOSPAGE1_EXPSPINUP_SHIFT_MAX_TARGET (4) 1310 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_DELAY (0x0F) 1311 1312 typedef struct _MPI_BOOT_DEVICE_ADAPTER_ORDER 1313 { 1314 U32 Reserved1; /* 00h */ 1315 U32 Reserved2; /* 04h */ 1316 U32 Reserved3; /* 08h */ 1317 U32 Reserved4; /* 0Ch */ 1318 U32 Reserved5; /* 10h */ 1319 U32 Reserved6; /* 14h */ 1320 U32 Reserved7; /* 18h */ 1321 U32 Reserved8; /* 1Ch */ 1322 U32 Reserved9; /* 20h */ 1323 U32 Reserved10; /* 24h */ 1324 U32 Reserved11; /* 28h */ 1325 U32 Reserved12; /* 2Ch */ 1326 U32 Reserved13; /* 30h */ 1327 U32 Reserved14; /* 34h */ 1328 U32 Reserved15; /* 38h */ 1329 U32 Reserved16; /* 3Ch */ 1330 U32 Reserved17; /* 40h */ 1331 } MPI_BOOT_DEVICE_ADAPTER_ORDER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_ORDER; 1332 1333 typedef struct _MPI_BOOT_DEVICE_ADAPTER_NUMBER 1334 { 1335 U8 TargetID; /* 00h */ 1336 U8 Bus; /* 01h */ 1337 U8 AdapterNumber; /* 02h */ 1338 U8 Reserved1; /* 03h */ 1339 U32 Reserved2; /* 04h */ 1340 U32 Reserved3; /* 08h */ 1341 U32 Reserved4; /* 0Ch */ 1342 U8 LUN[8]; /* 10h */ 1343 U32 Reserved5; /* 18h */ 1344 U32 Reserved6; /* 1Ch */ 1345 U32 Reserved7; /* 20h */ 1346 U32 Reserved8; /* 24h */ 1347 U32 Reserved9; /* 28h */ 1348 U32 Reserved10; /* 2Ch */ 1349 U32 Reserved11; /* 30h */ 1350 U32 Reserved12; /* 34h */ 1351 U32 Reserved13; /* 38h */ 1352 U32 Reserved14; /* 3Ch */ 1353 U32 Reserved15; /* 40h */ 1354 } MPI_BOOT_DEVICE_ADAPTER_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_NUMBER; 1355 1356 typedef struct _MPI_BOOT_DEVICE_PCI_ADDRESS 1357 { 1358 U8 TargetID; /* 00h */ 1359 U8 Bus; /* 01h */ 1360 U16 PCIAddress; /* 02h */ 1361 U32 Reserved1; /* 04h */ 1362 U32 Reserved2; /* 08h */ 1363 U32 Reserved3; /* 0Ch */ 1364 U8 LUN[8]; /* 10h */ 1365 U32 Reserved4; /* 18h */ 1366 U32 Reserved5; /* 1Ch */ 1367 U32 Reserved6; /* 20h */ 1368 U32 Reserved7; /* 24h */ 1369 U32 Reserved8; /* 28h */ 1370 U32 Reserved9; /* 2Ch */ 1371 U32 Reserved10; /* 30h */ 1372 U32 Reserved11; /* 34h */ 1373 U32 Reserved12; /* 38h */ 1374 U32 Reserved13; /* 3Ch */ 1375 U32 Reserved14; /* 40h */ 1376 } MPI_BOOT_DEVICE_PCI_ADDRESS, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_ADDRESS; 1377 1378 typedef struct _MPI_BOOT_DEVICE_SLOT_NUMBER 1379 { 1380 U8 TargetID; /* 00h */ 1381 U8 Bus; /* 01h */ 1382 U8 PCISlotNumber; /* 02h */ 1383 U8 Reserved1; /* 03h */ 1384 U32 Reserved2; /* 04h */ 1385 U32 Reserved3; /* 08h */ 1386 U32 Reserved4; /* 0Ch */ 1387 U8 LUN[8]; /* 10h */ 1388 U32 Reserved5; /* 18h */ 1389 U32 Reserved6; /* 1Ch */ 1390 U32 Reserved7; /* 20h */ 1391 U32 Reserved8; /* 24h */ 1392 U32 Reserved9; /* 28h */ 1393 U32 Reserved10; /* 2Ch */ 1394 U32 Reserved11; /* 30h */ 1395 U32 Reserved12; /* 34h */ 1396 U32 Reserved13; /* 38h */ 1397 U32 Reserved14; /* 3Ch */ 1398 U32 Reserved15; /* 40h */ 1399 } MPI_BOOT_DEVICE_PCI_SLOT_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_SLOT_NUMBER; 1400 1401 typedef struct _MPI_BOOT_DEVICE_FC_WWN 1402 { 1403 U64 WWPN; /* 00h */ 1404 U32 Reserved1; /* 08h */ 1405 U32 Reserved2; /* 0Ch */ 1406 U8 LUN[8]; /* 10h */ 1407 U32 Reserved3; /* 18h */ 1408 U32 Reserved4; /* 1Ch */ 1409 U32 Reserved5; /* 20h */ 1410 U32 Reserved6; /* 24h */ 1411 U32 Reserved7; /* 28h */ 1412 U32 Reserved8; /* 2Ch */ 1413 U32 Reserved9; /* 30h */ 1414 U32 Reserved10; /* 34h */ 1415 U32 Reserved11; /* 38h */ 1416 U32 Reserved12; /* 3Ch */ 1417 U32 Reserved13; /* 40h */ 1418 } MPI_BOOT_DEVICE_FC_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_FC_WWN; 1419 1420 typedef struct _MPI_BOOT_DEVICE_SAS_WWN 1421 { 1422 U64 SASAddress; /* 00h */ 1423 U32 Reserved1; /* 08h */ 1424 U32 Reserved2; /* 0Ch */ 1425 U8 LUN[8]; /* 10h */ 1426 U32 Reserved3; /* 18h */ 1427 U32 Reserved4; /* 1Ch */ 1428 U32 Reserved5; /* 20h */ 1429 U32 Reserved6; /* 24h */ 1430 U32 Reserved7; /* 28h */ 1431 U32 Reserved8; /* 2Ch */ 1432 U32 Reserved9; /* 30h */ 1433 U32 Reserved10; /* 34h */ 1434 U32 Reserved11; /* 38h */ 1435 U32 Reserved12; /* 3Ch */ 1436 U32 Reserved13; /* 40h */ 1437 } MPI_BOOT_DEVICE_SAS_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_SAS_WWN; 1438 1439 typedef struct _MPI_BOOT_DEVICE_ENCLOSURE_SLOT 1440 { 1441 U64 EnclosureLogicalID; /* 00h */ 1442 U32 Reserved1; /* 08h */ 1443 U32 Reserved2; /* 0Ch */ 1444 U8 LUN[8]; /* 10h */ 1445 U16 SlotNumber; /* 18h */ 1446 U16 Reserved3; /* 1Ah */ 1447 U32 Reserved4; /* 1Ch */ 1448 U32 Reserved5; /* 20h */ 1449 U32 Reserved6; /* 24h */ 1450 U32 Reserved7; /* 28h */ 1451 U32 Reserved8; /* 2Ch */ 1452 U32 Reserved9; /* 30h */ 1453 U32 Reserved10; /* 34h */ 1454 U32 Reserved11; /* 38h */ 1455 U32 Reserved12; /* 3Ch */ 1456 U32 Reserved13; /* 40h */ 1457 } MPI_BOOT_DEVICE_ENCLOSURE_SLOT, 1458 MPI_POINTER PTR_MPI_BOOT_DEVICE_ENCLOSURE_SLOT; 1459 1460 typedef union _MPI_BIOSPAGE2_BOOT_DEVICE 1461 { 1462 MPI_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1463 MPI_BOOT_DEVICE_ADAPTER_NUMBER AdapterNumber; 1464 MPI_BOOT_DEVICE_PCI_ADDRESS PCIAddress; 1465 MPI_BOOT_DEVICE_PCI_SLOT_NUMBER PCISlotNumber; 1466 MPI_BOOT_DEVICE_FC_WWN FcWwn; 1467 MPI_BOOT_DEVICE_SAS_WWN SasWwn; 1468 MPI_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1469 } MPI_BIOSPAGE2_BOOT_DEVICE, MPI_POINTER PTR_MPI_BIOSPAGE2_BOOT_DEVICE; 1470 1471 typedef struct _CONFIG_PAGE_BIOS_2 1472 { 1473 CONFIG_PAGE_HEADER Header; /* 00h */ 1474 U32 Reserved1; /* 04h */ 1475 U32 Reserved2; /* 08h */ 1476 U32 Reserved3; /* 0Ch */ 1477 U32 Reserved4; /* 10h */ 1478 U32 Reserved5; /* 14h */ 1479 U32 Reserved6; /* 18h */ 1480 U8 BootDeviceForm; /* 1Ch */ 1481 U8 PrevBootDeviceForm; /* 1Ch */ 1482 U16 Reserved8; /* 1Eh */ 1483 MPI_BIOSPAGE2_BOOT_DEVICE BootDevice; /* 20h */ 1484 } CONFIG_PAGE_BIOS_2, MPI_POINTER PTR_CONFIG_PAGE_BIOS_2, 1485 BIOSPage2_t, MPI_POINTER pBIOSPage2_t; 1486 1487 #define MPI_BIOSPAGE2_PAGEVERSION (0x02) 1488 1489 #define MPI_BIOSPAGE2_FORM_MASK (0x0F) 1490 #define MPI_BIOSPAGE2_FORM_ADAPTER_ORDER (0x00) 1491 #define MPI_BIOSPAGE2_FORM_ADAPTER_NUMBER (0x01) 1492 #define MPI_BIOSPAGE2_FORM_PCI_ADDRESS (0x02) 1493 #define MPI_BIOSPAGE2_FORM_PCI_SLOT_NUMBER (0x03) 1494 #define MPI_BIOSPAGE2_FORM_FC_WWN (0x04) 1495 #define MPI_BIOSPAGE2_FORM_SAS_WWN (0x05) 1496 #define MPI_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1497 1498 typedef struct _CONFIG_PAGE_BIOS_4 1499 { 1500 CONFIG_PAGE_HEADER Header; /* 00h */ 1501 U64 ReassignmentBaseWWID; /* 04h */ 1502 } CONFIG_PAGE_BIOS_4, MPI_POINTER PTR_CONFIG_PAGE_BIOS_4, 1503 BIOSPage4_t, MPI_POINTER pBIOSPage4_t; 1504 1505 #define MPI_BIOSPAGE4_PAGEVERSION (0x00) 1506 1507 1508 /**************************************************************************** 1509 * SCSI Port Config Pages 1510 ****************************************************************************/ 1511 1512 typedef struct _CONFIG_PAGE_SCSI_PORT_0 1513 { 1514 CONFIG_PAGE_HEADER Header; /* 00h */ 1515 U32 Capabilities; /* 04h */ 1516 U32 PhysicalInterface; /* 08h */ 1517 } CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0, 1518 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t; 1519 1520 #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x02) 1521 1522 #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001) 1523 #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002) 1524 #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004) 1525 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 1526 #define MPI_SCSIPORTPAGE0_SYNC_ASYNC (0x00) 1527 #define MPI_SCSIPORTPAGE0_SYNC_5 (0x32) 1528 #define MPI_SCSIPORTPAGE0_SYNC_10 (0x19) 1529 #define MPI_SCSIPORTPAGE0_SYNC_20 (0x0C) 1530 #define MPI_SCSIPORTPAGE0_SYNC_33_33 (0x0B) 1531 #define MPI_SCSIPORTPAGE0_SYNC_40 (0x0A) 1532 #define MPI_SCSIPORTPAGE0_SYNC_80 (0x09) 1533 #define MPI_SCSIPORTPAGE0_SYNC_160 (0x08) 1534 #define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN (0xFF) 1535 1536 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD (8) 1537 #define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap) \ 1538 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK) \ 1539 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD \ 1540 ) 1541 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 1542 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET (16) 1543 #define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap) \ 1544 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK) \ 1545 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET \ 1546 ) 1547 #define MPI_SCSIPORTPAGE0_CAP_IDP (0x08000000) 1548 #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000) 1549 #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000) 1550 1551 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003) 1552 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01) 1553 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02) 1554 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03) 1555 #define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000) 1556 #define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24) 1557 #define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE) 1558 #define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF) 1559 1560 1561 typedef struct _CONFIG_PAGE_SCSI_PORT_1 1562 { 1563 CONFIG_PAGE_HEADER Header; /* 00h */ 1564 U32 Configuration; /* 04h */ 1565 U32 OnBusTimerValue; /* 08h */ 1566 U8 TargetConfig; /* 0Ch */ 1567 U8 Reserved1; /* 0Dh */ 1568 U16 IDConfig; /* 0Eh */ 1569 } CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1, 1570 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t; 1571 1572 #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03) 1573 1574 /* Configuration values */ 1575 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF) 1576 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000) 1577 #define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID (16) 1578 1579 /* TargetConfig values */ 1580 #define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01) 1581 #define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG (0x02) 1582 1583 1584 typedef struct _MPI_DEVICE_INFO 1585 { 1586 U8 Timeout; /* 00h */ 1587 U8 SyncFactor; /* 01h */ 1588 U16 DeviceFlags; /* 02h */ 1589 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO, 1590 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t; 1591 1592 typedef struct _CONFIG_PAGE_SCSI_PORT_2 1593 { 1594 CONFIG_PAGE_HEADER Header; /* 00h */ 1595 U32 PortFlags; /* 04h */ 1596 U32 PortSettings; /* 08h */ 1597 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */ 1598 } CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2, 1599 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t; 1600 1601 #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x02) 1602 1603 /* PortFlags values */ 1604 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001) 1605 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004) 1606 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1607 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010) 1608 1609 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK (0x00000060) 1610 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV (0x00000000) 1611 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020) 1612 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060) 1613 1614 1615 /* PortSettings values */ 1616 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F) 1617 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030) 1618 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000) 1619 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010) 1620 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020) 1621 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030) 1622 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0) 1623 #define MPI_SCSIPORTPAGE2_PORT_RM_NONE (0x00000000) 1624 #define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY (0x00000040) 1625 #define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA (0x00000080) 1626 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00) 1627 #define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY (8) 1628 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000) 1629 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000) 1630 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000) 1631 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000) 1632 1633 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001) 1634 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002) 1635 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004) 1636 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008) 1637 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010) 1638 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020) 1639 1640 1641 /**************************************************************************** 1642 * SCSI Target Device Config Pages 1643 ****************************************************************************/ 1644 1645 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0 1646 { 1647 CONFIG_PAGE_HEADER Header; /* 00h */ 1648 U32 NegotiatedParameters; /* 04h */ 1649 U32 Information; /* 08h */ 1650 } CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0, 1651 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t; 1652 1653 #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x04) 1654 1655 #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001) 1656 #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002) 1657 #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004) 1658 #define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008) 1659 #define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010) 1660 #define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020) 1661 #define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040) 1662 #define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080) 1663 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00) 1664 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD (8) 1665 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000) 1666 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET (16) 1667 #define MPI_SCSIDEVPAGE0_NP_IDP (0x08000000) 1668 #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000) 1669 #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000) 1670 1671 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001) 1672 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002) 1673 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004) 1674 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008) 1675 1676 1677 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1 1678 { 1679 CONFIG_PAGE_HEADER Header; /* 00h */ 1680 U32 RequestedParameters; /* 04h */ 1681 U32 Reserved; /* 08h */ 1682 U32 Configuration; /* 0Ch */ 1683 } CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1, 1684 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t; 1685 1686 #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x05) 1687 1688 #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001) 1689 #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002) 1690 #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004) 1691 #define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008) 1692 #define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010) 1693 #define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020) 1694 #define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040) 1695 #define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080) 1696 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 1697 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD (8) 1698 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 1699 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET (16) 1700 #define MPI_SCSIDEVPAGE1_RP_IDP (0x08000000) 1701 #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000) 1702 #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000) 1703 1704 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002) 1705 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004) 1706 #define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008) 1707 #define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010) 1708 1709 1710 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2 1711 { 1712 CONFIG_PAGE_HEADER Header; /* 00h */ 1713 U32 DomainValidation; /* 04h */ 1714 U32 ParityPipeSelect; /* 08h */ 1715 U32 DataPipeSelect; /* 0Ch */ 1716 } CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2, 1717 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t; 1718 1719 #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01) 1720 1721 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010) 1722 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020) 1723 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380) 1724 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00) 1725 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000) 1726 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000) 1727 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000) 1728 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000) 1729 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000) 1730 1731 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003) 1732 1733 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003) 1734 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C) 1735 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030) 1736 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0) 1737 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300) 1738 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00) 1739 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000) 1740 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000) 1741 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000) 1742 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000) 1743 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000) 1744 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000) 1745 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000) 1746 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000) 1747 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000) 1748 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000) 1749 1750 1751 typedef struct _CONFIG_PAGE_SCSI_DEVICE_3 1752 { 1753 CONFIG_PAGE_HEADER Header; /* 00h */ 1754 U16 MsgRejectCount; /* 04h */ 1755 U16 PhaseErrorCount; /* 06h */ 1756 U16 ParityErrorCount; /* 08h */ 1757 U16 Reserved; /* 0Ah */ 1758 } CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3, 1759 SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t; 1760 1761 #define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00) 1762 1763 #define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE) 1764 #define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF) 1765 1766 1767 /**************************************************************************** 1768 * FC Port Config Pages 1769 ****************************************************************************/ 1770 1771 typedef struct _CONFIG_PAGE_FC_PORT_0 1772 { 1773 CONFIG_PAGE_HEADER Header; /* 00h */ 1774 U32 Flags; /* 04h */ 1775 U8 MPIPortNumber; /* 08h */ 1776 U8 LinkType; /* 09h */ 1777 U8 PortState; /* 0Ah */ 1778 U8 Reserved; /* 0Bh */ 1779 U32 PortIdentifier; /* 0Ch */ 1780 U64 WWNN; /* 10h */ 1781 U64 WWPN; /* 18h */ 1782 U32 SupportedServiceClass; /* 20h */ 1783 U32 SupportedSpeeds; /* 24h */ 1784 U32 CurrentSpeed; /* 28h */ 1785 U32 MaxFrameSize; /* 2Ch */ 1786 U64 FabricWWNN; /* 30h */ 1787 U64 FabricWWPN; /* 38h */ 1788 U32 DiscoveredPortsCount; /* 40h */ 1789 U32 MaxInitiators; /* 44h */ 1790 U8 MaxAliasesSupported; /* 48h */ 1791 U8 MaxHardAliasesSupported; /* 49h */ 1792 U8 NumCurrentAliases; /* 4Ah */ 1793 U8 Reserved1; /* 4Bh */ 1794 } CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0, 1795 FCPortPage0_t, MPI_POINTER pFCPortPage0_t; 1796 1797 #define MPI_FCPORTPAGE0_PAGEVERSION (0x02) 1798 1799 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F) 1800 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR) 1801 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET) 1802 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN) 1803 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR) 1804 1805 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010) 1806 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020) 1807 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040) 1808 1809 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00) 1810 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000) 1811 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100) 1812 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200) 1813 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400) 1814 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800) 1815 1816 #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00) 1817 #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01) 1818 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02) 1819 #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03) 1820 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04) 1821 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05) 1822 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06) 1823 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07) 1824 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08) 1825 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09) 1826 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A) 1827 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B) 1828 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C) 1829 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D) 1830 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E) 1831 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F) 1832 1833 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */ 1834 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */ 1835 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */ 1836 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */ 1837 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */ 1838 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */ 1839 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */ 1840 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */ 1841 1842 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001) 1843 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002) 1844 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004) 1845 1846 #define MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN (0x00000000) /* (SNIA)HBA_PORTSPEED_UNKNOWN 0 Unknown - transceiver incapable of reporting */ 1847 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */ 1848 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */ 1849 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */ 1850 #define MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED (0x00000008) /* (SNIA)HBA_PORTSPEED_4GBIT 8 4 GBit/sec */ 1851 1852 #define MPI_FCPORTPAGE0_CURRENT_SPEED_UKNOWN MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN 1853 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED 1854 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED 1855 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED 1856 #define MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED 1857 #define MPI_FCPORTPAGE0_CURRENT_SPEED_NOT_NEGOTIATED (0x00008000) /* (SNIA)HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) Speed not established */ 1858 1859 1860 typedef struct _CONFIG_PAGE_FC_PORT_1 1861 { 1862 CONFIG_PAGE_HEADER Header; /* 00h */ 1863 U32 Flags; /* 04h */ 1864 U64 NoSEEPROMWWNN; /* 08h */ 1865 U64 NoSEEPROMWWPN; /* 10h */ 1866 U8 HardALPA; /* 18h */ 1867 U8 LinkConfig; /* 19h */ 1868 U8 TopologyConfig; /* 1Ah */ 1869 U8 AltConnector; /* 1Bh */ 1870 U8 NumRequestedAliases; /* 1Ch */ 1871 U8 RR_TOV; /* 1Dh */ 1872 U8 InitiatorDeviceTimeout; /* 1Eh */ 1873 U8 InitiatorIoPendTimeout; /* 1Fh */ 1874 } CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1, 1875 FCPortPage1_t, MPI_POINTER pFCPortPage1_t; 1876 1877 #define MPI_FCPORTPAGE1_PAGEVERSION (0x06) 1878 1879 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000) 1880 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000) 1881 #define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000) 1882 #define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000) 1883 #define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000) 1884 #define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE (0x00400000) 1885 #define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK (0x00200000) 1886 #define MPI_FCPORTPAGE1_FLAGS_TARGET_LARGE_CDB_ENABLE (0x00000080) 1887 #define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070) 1888 #define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG (0x00000008) 1889 #define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO (0x00000004) 1890 #define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002) 1891 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001) 1892 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000) 1893 1894 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000) 1895 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28) 1896 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1897 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1898 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1899 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1900 1901 #define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000) 1902 #define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010) 1903 #define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030) 1904 #define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050) 1905 1906 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF) 1907 1908 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F) 1909 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00) 1910 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01) 1911 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02) 1912 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03) 1913 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F) 1914 1915 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F) 1916 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01) 1917 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02) 1918 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F) 1919 1920 #define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00) 1921 1922 #define MPI_FCPORTPAGE1_INITIATOR_DEV_TIMEOUT_MASK (0x7F) 1923 #define MPI_FCPORTPAGE1_INITIATOR_DEV_UNIT_16 (0x80) 1924 1925 1926 typedef struct _CONFIG_PAGE_FC_PORT_2 1927 { 1928 CONFIG_PAGE_HEADER Header; /* 00h */ 1929 U8 NumberActive; /* 04h */ 1930 U8 ALPA[127]; /* 05h */ 1931 } CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2, 1932 FCPortPage2_t, MPI_POINTER pFCPortPage2_t; 1933 1934 #define MPI_FCPORTPAGE2_PAGEVERSION (0x01) 1935 1936 1937 typedef struct _WWN_FORMAT 1938 { 1939 U64 WWNN; /* 00h */ 1940 U64 WWPN; /* 08h */ 1941 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT, 1942 WWNFormat, MPI_POINTER pWWNFormat; 1943 1944 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID 1945 { 1946 WWN_FORMAT WWN; 1947 U32 Did; 1948 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID, 1949 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t; 1950 1951 typedef struct _FC_PORT_PERSISTENT 1952 { 1953 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */ 1954 U8 TargetID; /* 10h */ 1955 U8 Bus; /* 11h */ 1956 U16 Flags; /* 12h */ 1957 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT, 1958 PersistentData_t, MPI_POINTER pPersistentData_t; 1959 1960 #define MPI_PERSISTENT_FLAGS_SHIFT (16) 1961 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001) 1962 #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002) 1963 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004) 1964 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008) 1965 #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080) 1966 1967 /* 1968 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1969 * one and check Header.PageLength at runtime. 1970 */ 1971 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX 1972 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1) 1973 #endif 1974 1975 typedef struct _CONFIG_PAGE_FC_PORT_3 1976 { 1977 CONFIG_PAGE_HEADER Header; /* 00h */ 1978 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */ 1979 } CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3, 1980 FCPortPage3_t, MPI_POINTER pFCPortPage3_t; 1981 1982 #define MPI_FCPORTPAGE3_PAGEVERSION (0x01) 1983 1984 1985 typedef struct _CONFIG_PAGE_FC_PORT_4 1986 { 1987 CONFIG_PAGE_HEADER Header; /* 00h */ 1988 U32 PortFlags; /* 04h */ 1989 U32 PortSettings; /* 08h */ 1990 } CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4, 1991 FCPortPage4_t, MPI_POINTER pFCPortPage4_t; 1992 1993 #define MPI_FCPORTPAGE4_PAGEVERSION (0x00) 1994 1995 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1996 1997 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030) 1998 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000) 1999 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010) 2000 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020) 2001 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030) 2002 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0) 2003 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00) 2004 2005 2006 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO 2007 { 2008 U8 Flags; /* 00h */ 2009 U8 AliasAlpa; /* 01h */ 2010 U16 Reserved; /* 02h */ 2011 U64 AliasWWNN; /* 04h */ 2012 U64 AliasWWPN; /* 0Ch */ 2013 } CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 2014 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 2015 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t; 2016 2017 typedef struct _CONFIG_PAGE_FC_PORT_5 2018 { 2019 CONFIG_PAGE_HEADER Header; /* 00h */ 2020 CONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */ 2021 } CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5, 2022 FCPortPage5_t, MPI_POINTER pFCPortPage5_t; 2023 2024 #define MPI_FCPORTPAGE5_PAGEVERSION (0x02) 2025 2026 #define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01) 2027 #define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02) 2028 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04) 2029 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08) 2030 #define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10) 2031 2032 typedef struct _CONFIG_PAGE_FC_PORT_6 2033 { 2034 CONFIG_PAGE_HEADER Header; /* 00h */ 2035 U32 Reserved; /* 04h */ 2036 U64 TimeSinceReset; /* 08h */ 2037 U64 TxFrames; /* 10h */ 2038 U64 RxFrames; /* 18h */ 2039 U64 TxWords; /* 20h */ 2040 U64 RxWords; /* 28h */ 2041 U64 LipCount; /* 30h */ 2042 U64 NosCount; /* 38h */ 2043 U64 ErrorFrames; /* 40h */ 2044 U64 DumpedFrames; /* 48h */ 2045 U64 LinkFailureCount; /* 50h */ 2046 U64 LossOfSyncCount; /* 58h */ 2047 U64 LossOfSignalCount; /* 60h */ 2048 U64 PrimativeSeqErrCount; /* 68h */ 2049 U64 InvalidTxWordCount; /* 70h */ 2050 U64 InvalidCrcCount; /* 78h */ 2051 U64 FcpInitiatorIoCount; /* 80h */ 2052 } CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6, 2053 FCPortPage6_t, MPI_POINTER pFCPortPage6_t; 2054 2055 #define MPI_FCPORTPAGE6_PAGEVERSION (0x00) 2056 2057 2058 typedef struct _CONFIG_PAGE_FC_PORT_7 2059 { 2060 CONFIG_PAGE_HEADER Header; /* 00h */ 2061 U32 Reserved; /* 04h */ 2062 U8 PortSymbolicName[256]; /* 08h */ 2063 } CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7, 2064 FCPortPage7_t, MPI_POINTER pFCPortPage7_t; 2065 2066 #define MPI_FCPORTPAGE7_PAGEVERSION (0x00) 2067 2068 2069 typedef struct _CONFIG_PAGE_FC_PORT_8 2070 { 2071 CONFIG_PAGE_HEADER Header; /* 00h */ 2072 U32 BitVector[8]; /* 04h */ 2073 } CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8, 2074 FCPortPage8_t, MPI_POINTER pFCPortPage8_t; 2075 2076 #define MPI_FCPORTPAGE8_PAGEVERSION (0x00) 2077 2078 2079 typedef struct _CONFIG_PAGE_FC_PORT_9 2080 { 2081 CONFIG_PAGE_HEADER Header; /* 00h */ 2082 U32 Reserved; /* 04h */ 2083 U64 GlobalWWPN; /* 08h */ 2084 U64 GlobalWWNN; /* 10h */ 2085 U32 UnitType; /* 18h */ 2086 U32 PhysicalPortNumber; /* 1Ch */ 2087 U32 NumAttachedNodes; /* 20h */ 2088 U16 IPVersion; /* 24h */ 2089 U16 UDPPortNumber; /* 26h */ 2090 U8 IPAddress[16]; /* 28h */ 2091 U16 Reserved1; /* 38h */ 2092 U16 TopologyDiscoveryFlags; /* 3Ah */ 2093 } CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9, 2094 FCPortPage9_t, MPI_POINTER pFCPortPage9_t; 2095 2096 #define MPI_FCPORTPAGE9_PAGEVERSION (0x00) 2097 2098 2099 typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA 2100 { 2101 U8 Id; /* 10h */ 2102 U8 ExtId; /* 11h */ 2103 U8 Connector; /* 12h */ 2104 U8 Transceiver[8]; /* 13h */ 2105 U8 Encoding; /* 1Bh */ 2106 U8 BitRate_100mbs; /* 1Ch */ 2107 U8 Reserved1; /* 1Dh */ 2108 U8 Length9u_km; /* 1Eh */ 2109 U8 Length9u_100m; /* 1Fh */ 2110 U8 Length50u_10m; /* 20h */ 2111 U8 Length62p5u_10m; /* 21h */ 2112 U8 LengthCopper_m; /* 22h */ 2113 U8 Reseverved2; /* 22h */ 2114 U8 VendorName[16]; /* 24h */ 2115 U8 Reserved3; /* 34h */ 2116 U8 VendorOUI[3]; /* 35h */ 2117 U8 VendorPN[16]; /* 38h */ 2118 U8 VendorRev[4]; /* 48h */ 2119 U16 Wavelength; /* 4Ch */ 2120 U8 Reserved4; /* 4Eh */ 2121 U8 CC_BASE; /* 4Fh */ 2122 } CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA, 2123 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA, 2124 FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t; 2125 2126 #define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00) 2127 #define MPI_FCPORT10_BASE_ID_GBIC (0x01) 2128 #define MPI_FCPORT10_BASE_ID_FIXED (0x02) 2129 #define MPI_FCPORT10_BASE_ID_SFP (0x03) 2130 #define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04) 2131 #define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F) 2132 #define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80) 2133 2134 #define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00) 2135 #define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01) 2136 #define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02) 2137 #define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03) 2138 #define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04) 2139 #define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05) 2140 #define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06) 2141 #define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07) 2142 #define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80) 2143 2144 #define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00) 2145 #define MPI_FCPORT10_BASE_CONN_SC (0x01) 2146 #define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02) 2147 #define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03) 2148 #define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04) 2149 #define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05) 2150 #define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06) 2151 #define MPI_FCPORT10_BASE_CONN_LC (0x07) 2152 #define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08) 2153 #define MPI_FCPORT10_BASE_CONN_MU (0x09) 2154 #define MPI_FCPORT10_BASE_CONN_SG (0x0A) 2155 #define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B) 2156 #define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C) 2157 #define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F) 2158 #define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20) 2159 #define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21) 2160 #define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22) 2161 #define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F) 2162 #define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80) 2163 2164 #define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00) 2165 #define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01) 2166 #define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02) 2167 #define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03) 2168 #define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04) 2169 2170 2171 typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA 2172 { 2173 U8 Options[2]; /* 50h */ 2174 U8 BitRateMax; /* 52h */ 2175 U8 BitRateMin; /* 53h */ 2176 U8 VendorSN[16]; /* 54h */ 2177 U8 DateCode[8]; /* 64h */ 2178 U8 DiagMonitoringType; /* 6Ch */ 2179 U8 EnhancedOptions; /* 6Dh */ 2180 U8 SFF8472Compliance; /* 6Eh */ 2181 U8 CC_EXT; /* 6Fh */ 2182 } CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA, 2183 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA, 2184 FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t; 2185 2186 #define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20) 2187 #define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10) 2188 #define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08) 2189 #define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04) 2190 #define MPI_FCPORT10_EXT_OPTION1_LOS (0x02) 2191 2192 2193 typedef struct _CONFIG_PAGE_FC_PORT_10 2194 { 2195 CONFIG_PAGE_HEADER Header; /* 00h */ 2196 U8 Flags; /* 04h */ 2197 U8 Reserved1; /* 05h */ 2198 U16 Reserved2; /* 06h */ 2199 U32 HwConfig1; /* 08h */ 2200 U32 HwConfig2; /* 0Ch */ 2201 CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */ 2202 CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */ 2203 U8 VendorSpecific[32]; /* 70h */ 2204 } CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10, 2205 FCPortPage10_t, MPI_POINTER pFCPortPage10_t; 2206 2207 #define MPI_FCPORTPAGE10_PAGEVERSION (0x01) 2208 2209 /* standard MODDEF pin definitions (from GBIC spec.) */ 2210 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007) 2211 #define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001) 2212 #define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002) 2213 #define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004) 2214 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007) 2215 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006) 2216 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005) 2217 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004) 2218 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003) 2219 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002) 2220 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001) 2221 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000) 2222 2223 #define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010) 2224 #define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020) 2225 2226 2227 /**************************************************************************** 2228 * FC Device Config Pages 2229 ****************************************************************************/ 2230 2231 typedef struct _CONFIG_PAGE_FC_DEVICE_0 2232 { 2233 CONFIG_PAGE_HEADER Header; /* 00h */ 2234 U64 WWNN; /* 04h */ 2235 U64 WWPN; /* 0Ch */ 2236 U32 PortIdentifier; /* 14h */ 2237 U8 Protocol; /* 18h */ 2238 U8 Flags; /* 19h */ 2239 U16 BBCredit; /* 1Ah */ 2240 U16 MaxRxFrameSize; /* 1Ch */ 2241 U8 ADISCHardALPA; /* 1Eh */ 2242 U8 PortNumber; /* 1Fh */ 2243 U8 FcPhLowestVersion; /* 20h */ 2244 U8 FcPhHighestVersion; /* 21h */ 2245 U8 CurrentTargetID; /* 22h */ 2246 U8 CurrentBus; /* 23h */ 2247 } CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0, 2248 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t; 2249 2250 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x03) 2251 2252 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01) 2253 #define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02) 2254 #define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04) 2255 2256 #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01) 2257 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02) 2258 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04) 2259 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY (0x08) 2260 2261 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK) 2262 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK) 2263 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) 2264 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID) 2265 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK) 2266 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK) 2267 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT) 2268 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK) 2269 2270 #define MPI_FC_DEVICE_PAGE0_HARD_ALPA_UNKNOWN (0xFF) 2271 2272 /**************************************************************************** 2273 * RAID Volume Config Pages 2274 ****************************************************************************/ 2275 2276 typedef struct _RAID_VOL0_PHYS_DISK 2277 { 2278 U16 Reserved; /* 00h */ 2279 U8 PhysDiskMap; /* 02h */ 2280 U8 PhysDiskNum; /* 03h */ 2281 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK, 2282 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t; 2283 2284 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 2285 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 2286 2287 typedef struct _RAID_VOL0_STATUS 2288 { 2289 U8 Flags; /* 00h */ 2290 U8 State; /* 01h */ 2291 U16 Reserved; /* 02h */ 2292 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS, 2293 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t; 2294 2295 /* RAID Volume Page 0 VolumeStatus defines */ 2296 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01) 2297 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02) 2298 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04) 2299 #define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08) 2300 #define MPI_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x10) 2301 2302 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00) 2303 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01) 2304 #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02) 2305 #define MPI_RAIDVOL0_STATUS_STATE_MISSING (0x03) 2306 2307 typedef struct _RAID_VOL0_SETTINGS 2308 { 2309 U16 Settings; /* 00h */ 2310 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 2311 U8 Reserved; /* 02h */ 2312 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS, 2313 RaidVol0Settings, MPI_POINTER pRaidVol0Settings; 2314 2315 /* RAID Volume Page 0 VolumeSettings defines */ 2316 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001) 2317 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002) 2318 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004) 2319 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008) 2320 #define MPI_RAIDVOL0_SETTING_FAST_DATA_SCRUBBING_0102 (0x0020) /* obsolete */ 2321 2322 #define MPI_RAIDVOL0_SETTING_MASK_METADATA_SIZE (0x00C0) 2323 #define MPI_RAIDVOL0_SETTING_64MB_METADATA_SIZE (0x0000) 2324 #define MPI_RAIDVOL0_SETTING_512MB_METADATA_SIZE (0x0040) 2325 2326 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010) 2327 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000) 2328 2329 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 2330 #define MPI_RAID_HOT_SPARE_POOL_0 (0x01) 2331 #define MPI_RAID_HOT_SPARE_POOL_1 (0x02) 2332 #define MPI_RAID_HOT_SPARE_POOL_2 (0x04) 2333 #define MPI_RAID_HOT_SPARE_POOL_3 (0x08) 2334 #define MPI_RAID_HOT_SPARE_POOL_4 (0x10) 2335 #define MPI_RAID_HOT_SPARE_POOL_5 (0x20) 2336 #define MPI_RAID_HOT_SPARE_POOL_6 (0x40) 2337 #define MPI_RAID_HOT_SPARE_POOL_7 (0x80) 2338 2339 /* 2340 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2341 * one and check Header.PageLength at runtime. 2342 */ 2343 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX 2344 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 2345 #endif 2346 2347 typedef struct _CONFIG_PAGE_RAID_VOL_0 2348 { 2349 CONFIG_PAGE_HEADER Header; /* 00h */ 2350 U8 VolumeID; /* 04h */ 2351 U8 VolumeBus; /* 05h */ 2352 U8 VolumeIOC; /* 06h */ 2353 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */ 2354 RAID_VOL0_STATUS VolumeStatus; /* 08h */ 2355 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */ 2356 U32 MaxLBA; /* 10h */ 2357 U32 MaxLBAHigh; /* 14h */ 2358 U32 StripeSize; /* 18h */ 2359 U32 Reserved2; /* 1Ch */ 2360 U32 Reserved3; /* 20h */ 2361 U8 NumPhysDisks; /* 24h */ 2362 U8 DataScrubRate; /* 25h */ 2363 U8 ResyncRate; /* 26h */ 2364 U8 InactiveStatus; /* 27h */ 2365 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */ 2366 } CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0, 2367 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t; 2368 2369 #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x07) 2370 2371 /* values for RAID Volume Page 0 InactiveStatus field */ 2372 #define MPI_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 2373 #define MPI_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 2374 #define MPI_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 2375 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 2376 #define MPI_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 2377 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 2378 #define MPI_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 2379 2380 2381 typedef struct _CONFIG_PAGE_RAID_VOL_1 2382 { 2383 CONFIG_PAGE_HEADER Header; /* 00h */ 2384 U8 VolumeID; /* 04h */ 2385 U8 VolumeBus; /* 05h */ 2386 U8 VolumeIOC; /* 06h */ 2387 U8 Reserved0; /* 07h */ 2388 U8 GUID[24]; /* 08h */ 2389 U8 Name[32]; /* 20h */ 2390 U64 WWID; /* 40h */ 2391 U32 Reserved1; /* 48h */ 2392 U32 Reserved2; /* 4Ch */ 2393 } CONFIG_PAGE_RAID_VOL_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_1, 2394 RaidVolumePage1_t, MPI_POINTER pRaidVolumePage1_t; 2395 2396 #define MPI_RAIDVOLPAGE1_PAGEVERSION (0x01) 2397 2398 2399 /**************************************************************************** 2400 * RAID Physical Disk Config Pages 2401 ****************************************************************************/ 2402 2403 typedef struct _RAID_PHYS_DISK0_ERROR_DATA 2404 { 2405 U8 ErrorCdbByte; /* 00h */ 2406 U8 ErrorSenseKey; /* 01h */ 2407 U16 Reserved; /* 02h */ 2408 U16 ErrorCount; /* 04h */ 2409 U8 ErrorASC; /* 06h */ 2410 U8 ErrorASCQ; /* 07h */ 2411 U16 SmartCount; /* 08h */ 2412 U8 SmartASC; /* 0Ah */ 2413 U8 SmartASCQ; /* 0Bh */ 2414 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA, 2415 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t; 2416 2417 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA 2418 { 2419 U8 VendorID[8]; /* 00h */ 2420 U8 ProductID[16]; /* 08h */ 2421 U8 ProductRevLevel[4]; /* 18h */ 2422 U8 Info[32]; /* 1Ch */ 2423 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA, 2424 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData; 2425 2426 typedef struct _RAID_PHYS_DISK0_SETTINGS 2427 { 2428 U8 SepID; /* 00h */ 2429 U8 SepBus; /* 01h */ 2430 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 2431 U8 PhysDiskSettings; /* 03h */ 2432 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS, 2433 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t; 2434 2435 typedef struct _RAID_PHYS_DISK0_STATUS 2436 { 2437 U8 Flags; /* 00h */ 2438 U8 State; /* 01h */ 2439 U16 Reserved; /* 02h */ 2440 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS, 2441 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t; 2442 2443 /* RAID Physical Disk PhysDiskStatus flags */ 2444 2445 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01) 2446 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02) 2447 #define MPI_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x04) 2448 #define MPI_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00) 2449 #define MPI_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x08) 2450 2451 #define MPI_PHYSDISK0_STATUS_ONLINE (0x00) 2452 #define MPI_PHYSDISK0_STATUS_MISSING (0x01) 2453 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02) 2454 #define MPI_PHYSDISK0_STATUS_FAILED (0x03) 2455 #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04) 2456 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05) 2457 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06) 2458 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF) 2459 2460 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0 2461 { 2462 CONFIG_PAGE_HEADER Header; /* 00h */ 2463 U8 PhysDiskID; /* 04h */ 2464 U8 PhysDiskBus; /* 05h */ 2465 U8 PhysDiskIOC; /* 06h */ 2466 U8 PhysDiskNum; /* 07h */ 2467 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */ 2468 U32 Reserved1; /* 0Ch */ 2469 U8 ExtDiskIdentifier[8]; /* 10h */ 2470 U8 DiskIdentifier[16]; /* 18h */ 2471 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */ 2472 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */ 2473 U32 MaxLBA; /* 68h */ 2474 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */ 2475 } CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0, 2476 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t; 2477 2478 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x02) 2479 2480 2481 typedef struct _RAID_PHYS_DISK1_PATH 2482 { 2483 U8 PhysDiskID; /* 00h */ 2484 U8 PhysDiskBus; /* 01h */ 2485 U16 Reserved1; /* 02h */ 2486 U64 WWID; /* 04h */ 2487 U64 OwnerWWID; /* 0Ch */ 2488 U8 OwnerIdentifier; /* 14h */ 2489 U8 Reserved2; /* 15h */ 2490 U16 Flags; /* 16h */ 2491 } RAID_PHYS_DISK1_PATH, MPI_POINTER PTR_RAID_PHYS_DISK1_PATH, 2492 RaidPhysDisk1Path_t, MPI_POINTER pRaidPhysDisk1Path_t; 2493 2494 /* RAID Physical Disk Page 1 Flags field defines */ 2495 #define MPI_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 2496 #define MPI_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 2497 2498 2499 /* 2500 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2501 * one and check Header.PageLength or NumPhysDiskPaths at runtime. 2502 */ 2503 #ifndef MPI_RAID_PHYS_DISK1_PATH_MAX 2504 #define MPI_RAID_PHYS_DISK1_PATH_MAX (1) 2505 #endif 2506 2507 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_1 2508 { 2509 CONFIG_PAGE_HEADER Header; /* 00h */ 2510 U8 NumPhysDiskPaths; /* 04h */ 2511 U8 PhysDiskNum; /* 05h */ 2512 U16 Reserved2; /* 06h */ 2513 U32 Reserved1; /* 08h */ 2514 RAID_PHYS_DISK1_PATH Path[MPI_RAID_PHYS_DISK1_PATH_MAX];/* 0Ch */ 2515 } CONFIG_PAGE_RAID_PHYS_DISK_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_1, 2516 RaidPhysDiskPage1_t, MPI_POINTER pRaidPhysDiskPage1_t; 2517 2518 #define MPI_RAIDPHYSDISKPAGE1_PAGEVERSION (0x00) 2519 2520 2521 /**************************************************************************** 2522 * LAN Config Pages 2523 ****************************************************************************/ 2524 2525 typedef struct _CONFIG_PAGE_LAN_0 2526 { 2527 ConfigPageHeader_t Header; /* 00h */ 2528 U16 TxRxModes; /* 04h */ 2529 U16 Reserved; /* 06h */ 2530 U32 PacketPrePad; /* 08h */ 2531 } CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0, 2532 LANPage0_t, MPI_POINTER pLANPage0_t; 2533 2534 #define MPI_LAN_PAGE0_PAGEVERSION (0x01) 2535 2536 #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000) 2537 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001) 2538 #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001) 2539 2540 typedef struct _CONFIG_PAGE_LAN_1 2541 { 2542 ConfigPageHeader_t Header; /* 00h */ 2543 U16 Reserved; /* 04h */ 2544 U8 CurrentDeviceState; /* 06h */ 2545 U8 Reserved1; /* 07h */ 2546 U32 MinPacketSize; /* 08h */ 2547 U32 MaxPacketSize; /* 0Ch */ 2548 U32 HardwareAddressLow; /* 10h */ 2549 U32 HardwareAddressHigh; /* 14h */ 2550 U32 MaxWireSpeedLow; /* 18h */ 2551 U32 MaxWireSpeedHigh; /* 1Ch */ 2552 U32 BucketsRemaining; /* 20h */ 2553 U32 MaxReplySize; /* 24h */ 2554 U32 NegWireSpeedLow; /* 28h */ 2555 U32 NegWireSpeedHigh; /* 2Ch */ 2556 } CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1, 2557 LANPage1_t, MPI_POINTER pLANPage1_t; 2558 2559 #define MPI_LAN_PAGE1_PAGEVERSION (0x03) 2560 2561 #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00) 2562 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01) 2563 2564 2565 /**************************************************************************** 2566 * Inband Config Pages 2567 ****************************************************************************/ 2568 2569 typedef struct _CONFIG_PAGE_INBAND_0 2570 { 2571 CONFIG_PAGE_HEADER Header; /* 00h */ 2572 MPI_VERSION_FORMAT InbandVersion; /* 04h */ 2573 U16 MaximumBuffers; /* 08h */ 2574 U16 Reserved1; /* 0Ah */ 2575 } CONFIG_PAGE_INBAND_0, MPI_POINTER PTR_CONFIG_PAGE_INBAND_0, 2576 InbandPage0_t, MPI_POINTER pInbandPage0_t; 2577 2578 #define MPI_INBAND_PAGEVERSION (0x00) 2579 2580 2581 2582 /**************************************************************************** 2583 * SAS IO Unit Config Pages 2584 ****************************************************************************/ 2585 2586 typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA 2587 { 2588 U8 Port; /* 00h */ 2589 U8 PortFlags; /* 01h */ 2590 U8 PhyFlags; /* 02h */ 2591 U8 NegotiatedLinkRate; /* 03h */ 2592 U32 ControllerPhyDeviceInfo;/* 04h */ 2593 U16 AttachedDeviceHandle; /* 08h */ 2594 U16 ControllerDevHandle; /* 0Ah */ 2595 U32 DiscoveryStatus; /* 0Ch */ 2596 } MPI_SAS_IO_UNIT0_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT0_PHY_DATA, 2597 SasIOUnit0PhyData, MPI_POINTER pSasIOUnit0PhyData; 2598 2599 /* 2600 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2601 * one and check Header.PageLength at runtime. 2602 */ 2603 #ifndef MPI_SAS_IOUNIT0_PHY_MAX 2604 #define MPI_SAS_IOUNIT0_PHY_MAX (1) 2605 #endif 2606 2607 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_0 2608 { 2609 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2610 U16 NvdataVersionDefault; /* 08h */ 2611 U16 NvdataVersionPersistent; /* 0Ah */ 2612 U8 NumPhys; /* 0Ch */ 2613 U8 Reserved2; /* 0Dh */ 2614 U16 Reserved3; /* 0Eh */ 2615 MPI_SAS_IO_UNIT0_PHY_DATA PhyData[MPI_SAS_IOUNIT0_PHY_MAX]; /* 10h */ 2616 } CONFIG_PAGE_SAS_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_0, 2617 SasIOUnitPage0_t, MPI_POINTER pSasIOUnitPage0_t; 2618 2619 #define MPI_SASIOUNITPAGE0_PAGEVERSION (0x04) 2620 2621 /* values for SAS IO Unit Page 0 PortFlags */ 2622 #define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS (0x08) 2623 #define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM (0x00) 2624 #define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM (0x04) 2625 #define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2626 2627 /* values for SAS IO Unit Page 0 PhyFlags */ 2628 #define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED (0x04) 2629 #define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT (0x02) 2630 #define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT (0x01) 2631 2632 /* values for SAS IO Unit Page 0 NegotiatedLinkRate */ 2633 #define MPI_SAS_IOUNIT0_RATE_UNKNOWN (0x00) 2634 #define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED (0x01) 2635 #define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION (0x02) 2636 #define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE (0x03) 2637 #define MPI_SAS_IOUNIT0_RATE_1_5 (0x08) 2638 #define MPI_SAS_IOUNIT0_RATE_3_0 (0x09) 2639 #define MPI_SAS_IOUNIT0_RATE_6_0 (0x0A) 2640 2641 /* see mpi_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 2642 2643 /* values for SAS IO Unit Page 0 DiscoveryStatus */ 2644 #define MPI_SAS_IOUNIT0_DS_LOOP_DETECTED (0x00000001) 2645 #define MPI_SAS_IOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2646 #define MPI_SAS_IOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2647 #define MPI_SAS_IOUNIT0_DS_EXPANDER_ERR (0x00000008) 2648 #define MPI_SAS_IOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2649 #define MPI_SAS_IOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2650 #define MPI_SAS_IOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2651 #define MPI_SAS_IOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2652 #define MPI_SAS_IOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2653 #define MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2654 #define MPI_SAS_IOUNIT0_DS_TABLE_LINK (0x00000400) 2655 #define MPI_SAS_IOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2656 #define MPI_SAS_IOUNIT0_DS_MAX_SATA_TARGETS (0x00001000) 2657 #define MPI_SAS_IOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 2658 2659 2660 typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA 2661 { 2662 U8 Port; /* 00h */ 2663 U8 PortFlags; /* 01h */ 2664 U8 PhyFlags; /* 02h */ 2665 U8 MaxMinLinkRate; /* 03h */ 2666 U32 ControllerPhyDeviceInfo; /* 04h */ 2667 U16 MaxTargetPortConnectTime; /* 08h */ 2668 U16 Reserved1; /* 0Ah */ 2669 } MPI_SAS_IO_UNIT1_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT1_PHY_DATA, 2670 SasIOUnit1PhyData, MPI_POINTER pSasIOUnit1PhyData; 2671 2672 /* 2673 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2674 * one and check Header.PageLength at runtime. 2675 */ 2676 #ifndef MPI_SAS_IOUNIT1_PHY_MAX 2677 #define MPI_SAS_IOUNIT1_PHY_MAX (1) 2678 #endif 2679 2680 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_1 2681 { 2682 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2683 U16 ControlFlags; /* 08h */ 2684 U16 MaxNumSATATargets; /* 0Ah */ 2685 U16 AdditionalControlFlags; /* 0Ch */ 2686 U16 Reserved1; /* 0Eh */ 2687 U8 NumPhys; /* 10h */ 2688 U8 SATAMaxQDepth; /* 11h */ 2689 U8 ReportDeviceMissingDelay; /* 12h */ 2690 U8 IODeviceMissingDelay; /* 13h */ 2691 MPI_SAS_IO_UNIT1_PHY_DATA PhyData[MPI_SAS_IOUNIT1_PHY_MAX]; /* 14h */ 2692 } CONFIG_PAGE_SAS_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_1, 2693 SasIOUnitPage1_t, MPI_POINTER pSasIOUnitPage1_t; 2694 2695 #define MPI_SASIOUNITPAGE1_PAGEVERSION (0x07) 2696 2697 /* values for SAS IO Unit Page 1 ControlFlags */ 2698 #define MPI_SAS_IOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2699 #define MPI_SAS_IOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2700 #define MPI_SAS_IOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 2701 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2702 #define MPI_SAS_IOUNIT1_CONTROL_DISABLE_SAS_HASH (0x0800) 2703 2704 #define MPI_SAS_IOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2705 #define MPI_SAS_IOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2706 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x00) 2707 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x01) 2708 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x02) 2709 2710 #define MPI_SAS_IOUNIT1_CONTROL_POSTPONE_SATA_INIT (0x0100) 2711 #define MPI_SAS_IOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2712 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2713 #define MPI_SAS_IOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2714 #define MPI_SAS_IOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2715 #define MPI_SAS_IOUNIT1_CONTROL_PHY_ENABLE_ORDER_HIGH (0x0008) 2716 #define MPI_SAS_IOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2717 #define MPI_SAS_IOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2718 #define MPI_SAS_IOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 2719 2720 /* values for SAS IO Unit Page 1 AdditionalControlFlags */ 2721 #define MPI_SAS_IOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2722 #define MPI_SAS_IOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2723 #define MPI_SAS_IOUNIT1_ACONTROL_HIDE_NONZERO_ATTACHED_PHY_IDENT (0x0020) 2724 #define MPI_SAS_IOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2725 #define MPI_SAS_IOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2726 #define MPI_SAS_IOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2727 #define MPI_SAS_IOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2728 #define MPI_SAS_IOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2729 2730 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2731 #define MPI_SAS_IOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2732 #define MPI_SAS_IOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2733 2734 /* values for SAS IO Unit Page 1 PortFlags */ 2735 #define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM (0x00) 2736 #define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM (0x04) 2737 #define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2738 2739 /* values for SAS IO Unit Page 0 PhyFlags */ 2740 #define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE (0x04) 2741 #define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT (0x02) 2742 #define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT (0x01) 2743 2744 /* values for SAS IO Unit Page 0 MaxMinLinkRate */ 2745 #define MPI_SAS_IOUNIT1_MAX_RATE_MASK (0xF0) 2746 #define MPI_SAS_IOUNIT1_MAX_RATE_1_5 (0x80) 2747 #define MPI_SAS_IOUNIT1_MAX_RATE_3_0 (0x90) 2748 #define MPI_SAS_IOUNIT1_MIN_RATE_MASK (0x0F) 2749 #define MPI_SAS_IOUNIT1_MIN_RATE_1_5 (0x08) 2750 #define MPI_SAS_IOUNIT1_MIN_RATE_3_0 (0x09) 2751 2752 /* see mpi_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2753 2754 2755 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_2 2756 { 2757 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2758 U8 NumDevsPerEnclosure; /* 08h */ 2759 U8 BootDeviceWaitTime; /* 09h */ 2760 U16 Reserved2; /* 0Ah */ 2761 U16 MaxPersistentIDs; /* 0Ch */ 2762 U16 NumPersistentIDsUsed; /* 0Eh */ 2763 U8 Status; /* 10h */ 2764 U8 Flags; /* 11h */ 2765 U16 MaxNumPhysicalMappedIDs;/* 12h */ 2766 } CONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2, 2767 SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t; 2768 2769 #define MPI_SASIOUNITPAGE2_PAGEVERSION (0x07) 2770 2771 /* values for SAS IO Unit Page 2 Status field */ 2772 #define MPI_SAS_IOUNIT2_STATUS_DEVICE_LIMIT_EXCEEDED (0x08) 2773 #define MPI_SAS_IOUNIT2_STATUS_ENCLOSURE_DEVICES_UNMAPPED (0x04) 2774 #define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS (0x02) 2775 #define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS (0x01) 2776 2777 /* values for SAS IO Unit Page 2 Flags field */ 2778 #define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS (0x01) 2779 /* Physical Mapping Modes */ 2780 #define MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE (0x0E) 2781 #define MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE (1) 2782 #define MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP (0x00) 2783 #define MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP (0x01) 2784 #define MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP (0x02) 2785 #define MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP (0x07) 2786 2787 #define MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT (0x10) 2788 #define MPI_SAS_IOUNIT2_FLAGS_DA_STARTING_SLOT (0x20) 2789 2790 2791 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_3 2792 { 2793 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2794 U32 Reserved1; /* 08h */ 2795 U32 MaxInvalidDwordCount; /* 0Ch */ 2796 U32 InvalidDwordCountTime; /* 10h */ 2797 U32 MaxRunningDisparityErrorCount; /* 14h */ 2798 U32 RunningDisparityErrorTime; /* 18h */ 2799 U32 MaxLossDwordSynchCount; /* 1Ch */ 2800 U32 LossDwordSynchCountTime; /* 20h */ 2801 U32 MaxPhyResetProblemCount; /* 24h */ 2802 U32 PhyResetProblemTime; /* 28h */ 2803 } CONFIG_PAGE_SAS_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_3, 2804 SasIOUnitPage3_t, MPI_POINTER pSasIOUnitPage3_t; 2805 2806 #define MPI_SASIOUNITPAGE3_PAGEVERSION (0x00) 2807 2808 2809 /**************************************************************************** 2810 * SAS Expander Config Pages 2811 ****************************************************************************/ 2812 2813 typedef struct _CONFIG_PAGE_SAS_EXPANDER_0 2814 { 2815 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2816 U8 PhysicalPort; /* 08h */ 2817 U8 Reserved1; /* 09h */ 2818 U16 EnclosureHandle; /* 0Ah */ 2819 U64 SASAddress; /* 0Ch */ 2820 U32 DiscoveryStatus; /* 14h */ 2821 U16 DevHandle; /* 18h */ 2822 U16 ParentDevHandle; /* 1Ah */ 2823 U16 ExpanderChangeCount; /* 1Ch */ 2824 U16 ExpanderRouteIndexes; /* 1Eh */ 2825 U8 NumPhys; /* 20h */ 2826 U8 SASLevel; /* 21h */ 2827 U8 Flags; /* 22h */ 2828 U8 Reserved3; /* 23h */ 2829 } CONFIG_PAGE_SAS_EXPANDER_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_0, 2830 SasExpanderPage0_t, MPI_POINTER pSasExpanderPage0_t; 2831 2832 #define MPI_SASEXPANDER0_PAGEVERSION (0x03) 2833 2834 /* values for SAS Expander Page 0 DiscoveryStatus field */ 2835 #define MPI_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2836 #define MPI_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2837 #define MPI_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2838 #define MPI_SAS_EXPANDER0_DS_EXPANDER_ERR (0x00000008) 2839 #define MPI_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2840 #define MPI_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2841 #define MPI_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2842 #define MPI_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2843 #define MPI_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2844 #define MPI_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2845 #define MPI_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2846 #define MPI_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2847 2848 /* values for SAS Expander Page 0 Flags field */ 2849 #define MPI_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x04) 2850 #define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x02) 2851 #define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x01) 2852 2853 2854 typedef struct _CONFIG_PAGE_SAS_EXPANDER_1 2855 { 2856 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2857 U8 PhysicalPort; /* 08h */ 2858 U8 Reserved1; /* 09h */ 2859 U16 Reserved2; /* 0Ah */ 2860 U8 NumPhys; /* 0Ch */ 2861 U8 Phy; /* 0Dh */ 2862 U16 NumTableEntriesProgrammed; /* 0Eh */ 2863 U8 ProgrammedLinkRate; /* 10h */ 2864 U8 HwLinkRate; /* 11h */ 2865 U16 AttachedDevHandle; /* 12h */ 2866 U32 PhyInfo; /* 14h */ 2867 U32 AttachedDeviceInfo; /* 18h */ 2868 U16 OwnerDevHandle; /* 1Ch */ 2869 U8 ChangeCount; /* 1Eh */ 2870 U8 NegotiatedLinkRate; /* 1Fh */ 2871 U8 PhyIdentifier; /* 20h */ 2872 U8 AttachedPhyIdentifier; /* 21h */ 2873 U8 Reserved3; /* 22h */ 2874 U8 DiscoveryInfo; /* 23h */ 2875 U32 Reserved4; /* 24h */ 2876 } CONFIG_PAGE_SAS_EXPANDER_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_1, 2877 SasExpanderPage1_t, MPI_POINTER pSasExpanderPage1_t; 2878 2879 #define MPI_SASEXPANDER1_PAGEVERSION (0x01) 2880 2881 /* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */ 2882 2883 /* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */ 2884 2885 /* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */ 2886 2887 /* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */ 2888 2889 /* values for SAS Expander Page 1 DiscoveryInfo field */ 2890 #define MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2891 #define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2892 #define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2893 2894 /* values for SAS Expander Page 1 NegotiatedLinkRate field */ 2895 #define MPI_SAS_EXPANDER1_NEG_RATE_UNKNOWN (0x00) 2896 #define MPI_SAS_EXPANDER1_NEG_RATE_PHY_DISABLED (0x01) 2897 #define MPI_SAS_EXPANDER1_NEG_RATE_FAILED_NEGOTIATION (0x02) 2898 #define MPI_SAS_EXPANDER1_NEG_RATE_SATA_OOB_COMPLETE (0x03) 2899 #define MPI_SAS_EXPANDER1_NEG_RATE_1_5 (0x08) 2900 #define MPI_SAS_EXPANDER1_NEG_RATE_3_0 (0x09) 2901 2902 2903 /**************************************************************************** 2904 * SAS Device Config Pages 2905 ****************************************************************************/ 2906 2907 typedef struct _CONFIG_PAGE_SAS_DEVICE_0 2908 { 2909 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2910 U16 Slot; /* 08h */ 2911 U16 EnclosureHandle; /* 0Ah */ 2912 U64 SASAddress; /* 0Ch */ 2913 U16 ParentDevHandle; /* 14h */ 2914 U8 PhyNum; /* 16h */ 2915 U8 AccessStatus; /* 17h */ 2916 U16 DevHandle; /* 18h */ 2917 U8 TargetID; /* 1Ah */ 2918 U8 Bus; /* 1Bh */ 2919 U32 DeviceInfo; /* 1Ch */ 2920 U16 Flags; /* 20h */ 2921 U8 PhysicalPort; /* 22h */ 2922 U8 Reserved2; /* 23h */ 2923 } CONFIG_PAGE_SAS_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_0, 2924 SasDevicePage0_t, MPI_POINTER pSasDevicePage0_t; 2925 2926 #define MPI_SASDEVICE0_PAGEVERSION (0x05) 2927 2928 /* values for SAS Device Page 0 AccessStatus field */ 2929 #define MPI_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2930 #define MPI_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2931 #define MPI_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2932 #define MPI_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2933 #define MPI_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2934 /* specific values for SATA Init failures */ 2935 #define MPI_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2936 #define MPI_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2937 #define MPI_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2938 #define MPI_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2939 #define MPI_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2940 #define MPI_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2941 #define MPI_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2942 #define MPI_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2943 #define MPI_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2944 #define MPI_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2945 #define MPI_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2946 2947 /* values for SAS Device Page 0 Flags field */ 2948 #define MPI_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2949 #define MPI_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2950 #define MPI_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2951 #define MPI_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2952 #define MPI_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2953 #define MPI_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2954 #define MPI_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2955 #define MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2956 #define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT (0x0004) 2957 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED (0x0002) 2958 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2959 2960 /* see mpi_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2961 2962 2963 typedef struct _CONFIG_PAGE_SAS_DEVICE_1 2964 { 2965 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2966 U32 Reserved1; /* 08h */ 2967 U64 SASAddress; /* 0Ch */ 2968 U32 Reserved2; /* 14h */ 2969 U16 DevHandle; /* 18h */ 2970 U8 TargetID; /* 1Ah */ 2971 U8 Bus; /* 1Bh */ 2972 U8 InitialRegDeviceFIS[20];/* 1Ch */ 2973 } CONFIG_PAGE_SAS_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_1, 2974 SasDevicePage1_t, MPI_POINTER pSasDevicePage1_t; 2975 2976 #define MPI_SASDEVICE1_PAGEVERSION (0x00) 2977 2978 2979 typedef struct _CONFIG_PAGE_SAS_DEVICE_2 2980 { 2981 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2982 U64 PhysicalIdentifier; /* 08h */ 2983 U32 EnclosureMapping; /* 10h */ 2984 } CONFIG_PAGE_SAS_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_2, 2985 SasDevicePage2_t, MPI_POINTER pSasDevicePage2_t; 2986 2987 #define MPI_SASDEVICE2_PAGEVERSION (0x01) 2988 2989 /* defines for SAS Device Page 2 EnclosureMapping field */ 2990 #define MPI_SASDEVICE2_ENC_MAP_MASK_MISSING_COUNT (0x0000000F) 2991 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_MISSING_COUNT (0) 2992 #define MPI_SASDEVICE2_ENC_MAP_MASK_NUM_SLOTS (0x000007F0) 2993 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_NUM_SLOTS (4) 2994 #define MPI_SASDEVICE2_ENC_MAP_MASK_START_INDEX (0x001FF800) 2995 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_START_INDEX (11) 2996 2997 2998 /**************************************************************************** 2999 * SAS PHY Config Pages 3000 ****************************************************************************/ 3001 3002 typedef struct _CONFIG_PAGE_SAS_PHY_0 3003 { 3004 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 3005 U16 OwnerDevHandle; /* 08h */ 3006 U16 Reserved1; /* 0Ah */ 3007 U64 SASAddress; /* 0Ch */ 3008 U16 AttachedDevHandle; /* 14h */ 3009 U8 AttachedPhyIdentifier; /* 16h */ 3010 U8 Reserved2; /* 17h */ 3011 U32 AttachedDeviceInfo; /* 18h */ 3012 U8 ProgrammedLinkRate; /* 1Ch */ 3013 U8 HwLinkRate; /* 1Dh */ 3014 U8 ChangeCount; /* 1Eh */ 3015 U8 Flags; /* 1Fh */ 3016 U32 PhyInfo; /* 20h */ 3017 } CONFIG_PAGE_SAS_PHY_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_0, 3018 SasPhyPage0_t, MPI_POINTER pSasPhyPage0_t; 3019 3020 #define MPI_SASPHY0_PAGEVERSION (0x01) 3021 3022 /* values for SAS PHY Page 0 ProgrammedLinkRate field */ 3023 #define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK (0xF0) 3024 #define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 3025 #define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5 (0x80) 3026 #define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0 (0x90) 3027 #define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK (0x0F) 3028 #define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 3029 #define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5 (0x08) 3030 #define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0 (0x09) 3031 3032 /* values for SAS PHY Page 0 HwLinkRate field */ 3033 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK (0xF0) 3034 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5 (0x80) 3035 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0 (0x90) 3036 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK (0x0F) 3037 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5 (0x08) 3038 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0 (0x09) 3039 3040 /* values for SAS PHY Page 0 Flags field */ 3041 #define MPI_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 3042 3043 /* values for SAS PHY Page 0 PhyInfo field */ 3044 #define MPI_SAS_PHY0_PHYINFO_PHY_VACANT (0x80000000) 3045 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 3046 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR (0x00002000) 3047 #define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY (0x00001000) 3048 3049 #define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 3050 #define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 3051 3052 #define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 3053 #define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING (0x00000000) 3054 #define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 3055 #define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING (0x00000020) 3056 3057 #define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE (0x0000000F) 3058 #define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE (0x00000000) 3059 #define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED (0x00000001) 3060 #define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED (0x00000002) 3061 #define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE (0x00000003) 3062 #define MPI_SAS_PHY0_PHYINFO_RATE_1_5 (0x00000008) 3063 #define MPI_SAS_PHY0_PHYINFO_RATE_3_0 (0x00000009) 3064 3065 3066 typedef struct _CONFIG_PAGE_SAS_PHY_1 3067 { 3068 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 3069 U32 Reserved1; /* 08h */ 3070 U32 InvalidDwordCount; /* 0Ch */ 3071 U32 RunningDisparityErrorCount; /* 10h */ 3072 U32 LossDwordSynchCount; /* 14h */ 3073 U32 PhyResetProblemCount; /* 18h */ 3074 } CONFIG_PAGE_SAS_PHY_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_1, 3075 SasPhyPage1_t, MPI_POINTER pSasPhyPage1_t; 3076 3077 #define MPI_SASPHY1_PAGEVERSION (0x00) 3078 3079 3080 /**************************************************************************** 3081 * SAS Enclosure Config Pages 3082 ****************************************************************************/ 3083 3084 typedef struct _CONFIG_PAGE_SAS_ENCLOSURE_0 3085 { 3086 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 3087 U32 Reserved1; /* 08h */ 3088 U64 EnclosureLogicalID; /* 0Ch */ 3089 U16 Flags; /* 14h */ 3090 U16 EnclosureHandle; /* 16h */ 3091 U16 NumSlots; /* 18h */ 3092 U16 StartSlot; /* 1Ah */ 3093 U8 StartTargetID; /* 1Ch */ 3094 U8 StartBus; /* 1Dh */ 3095 U8 SEPTargetID; /* 1Eh */ 3096 U8 SEPBus; /* 1Fh */ 3097 U32 Reserved2; /* 20h */ 3098 U32 Reserved3; /* 24h */ 3099 } CONFIG_PAGE_SAS_ENCLOSURE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_ENCLOSURE_0, 3100 SasEnclosurePage0_t, MPI_POINTER pSasEnclosurePage0_t; 3101 3102 #define MPI_SASENCLOSURE0_PAGEVERSION (0x01) 3103 3104 /* values for SAS Enclosure Page 0 Flags field */ 3105 #define MPI_SAS_ENCLS0_FLAGS_SEP_BUS_ID_VALID (0x0020) 3106 #define MPI_SAS_ENCLS0_FLAGS_START_BUS_ID_VALID (0x0010) 3107 3108 #define MPI_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3109 #define MPI_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3110 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3111 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3112 #define MPI_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3113 #define MPI_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3114 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3115 3116 3117 /**************************************************************************** 3118 * Log Config Pages 3119 ****************************************************************************/ 3120 /* 3121 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3122 * one and check NumLogEntries at runtime. 3123 */ 3124 #ifndef MPI_LOG_0_NUM_LOG_ENTRIES 3125 #define MPI_LOG_0_NUM_LOG_ENTRIES (1) 3126 #endif 3127 3128 #define MPI_LOG_0_LOG_DATA_LENGTH (0x1C) 3129 3130 typedef struct _MPI_LOG_0_ENTRY 3131 { 3132 U32 TimeStamp; /* 00h */ 3133 U32 Reserved1; /* 04h */ 3134 U16 LogSequence; /* 08h */ 3135 U16 LogEntryQualifier; /* 0Ah */ 3136 U8 LogData[MPI_LOG_0_LOG_DATA_LENGTH]; /* 0Ch */ 3137 } MPI_LOG_0_ENTRY, MPI_POINTER PTR_MPI_LOG_0_ENTRY, 3138 MpiLog0Entry_t, MPI_POINTER pMpiLog0Entry_t; 3139 3140 /* values for Log Page 0 LogEntry LogEntryQualifier field */ 3141 #define MPI_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3142 #define MPI_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3143 3144 typedef struct _CONFIG_PAGE_LOG_0 3145 { 3146 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 3147 U32 Reserved1; /* 08h */ 3148 U32 Reserved2; /* 0Ch */ 3149 U16 NumLogEntries; /* 10h */ 3150 U16 Reserved3; /* 12h */ 3151 MPI_LOG_0_ENTRY LogEntry[MPI_LOG_0_NUM_LOG_ENTRIES]; /* 14h */ 3152 } CONFIG_PAGE_LOG_0, MPI_POINTER PTR_CONFIG_PAGE_LOG_0, 3153 LogPage0_t, MPI_POINTER pLogPage0_t; 3154 3155 #define MPI_LOG_0_PAGEVERSION (0x01) 3156 3157 3158 #endif 3159 3160