1 /* $FreeBSD$ */ 2 /* 3 * Copyright (c) 2000, 2001 by LSI Logic Corporation 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice immediately at the beginning of the file, without modification, 10 * this list of conditions, and the following disclaimer. 11 * 2. The name of the author may not be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 18 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * 27 * Name: MPI_CNFG.H 28 * Title: MPI Config message, structures, and Pages 29 * Creation Date: July 27, 2000 30 * 31 * MPI_CNFG.H Version: 01.02.11 32 * 33 * Version History 34 * --------------- 35 * 36 * Date Version Description 37 * -------- -------- ------------------------------------------------------ 38 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 39 * 06-06-00 01.00.01 Update version number for 1.0 release. 40 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages. 41 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2 42 * fields to FC_DEVICE_0 page, updated the page version. 43 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in 44 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages 45 * and updated the page versions. 46 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1 47 * page and updated the page version. 48 * Added Information field and _INFO_PARAMS_NEGOTIATED 49 * definitionto SCSI_DEVICE_0 page. 50 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the 51 * page version. 52 * Added BucketsRemaining to LAN_1 page, redefined the 53 * state values, and updated the page version. 54 * Revised bus width definitions in SCSI_PORT_0, 55 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages. 56 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page 57 * version. 58 * Moved FC_DEVICE_0 PageAddress description to spec. 59 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field 60 * widths in IOC_0 page and updated the page version. 61 * 11-02-00 01.01.01 Original release for post 1.0 work 62 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI 63 * Port Page 2, FC Port Page 4, FC Port Page 5 64 * 11-15-00 01.01.02 Interim changes to match proposals 65 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01. 66 * 12-05-00 01.01.04 Modified config page actions. 67 * 01-09-01 01.01.05 Added defines for page address formats. 68 * Data size for Manufacturing pages 2 and 3 no longer 69 * defined here. 70 * Io Unit Page 2 size is fixed at 4 adapters and some 71 * flags were changed. 72 * SCSI Port Page 2 Device Settings modified. 73 * New fields added to FC Port Page 0 and some flags 74 * cleaned up. 75 * Removed impedance flash from FC Port Page 1. 76 * Added FC Port pages 6 and 7. 77 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0. 78 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique. 79 * Added some LinkType defines for FcPortPage0. 80 * 02-20-01 01.01.08 Started using MPI_POINTER. 81 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with 82 * MPI_CONFIG_PAGETYPE_RAID_VOLUME. 83 * Added definitions and structures for IOC Page 2 and 84 * RAID Volume Page 2. 85 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9. 86 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID. 87 * Added VendorId and ProductRevLevel fields to 88 * RAIDVOL2_IM_PHYS_ID struct. 89 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_ 90 * defines to make them compatible to MPI version 1.0. 91 * Added structure offset comments. 92 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and 93 * removed some obsolete ones. 94 * Added IO Unit Page 3. 95 * Modified defines for Scsi Port Page 2. 96 * Modified RAID Volume Pages. 97 * 08-08-01 01.02.01 Original release for v1.2 work. 98 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct. 99 * Added defines for the SEP bits in RVP2 VolumeSettings. 100 * Modified the DeviceSettings field in RVP2 to use the 101 * proper structure. 102 * Added defines for SES, SAF-TE, and cross channel for 103 * IOCPage2 CapabilitiesFlags. 104 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE. 105 * Removed define for 106 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE. 107 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT. 108 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035. 109 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY 110 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY. 111 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS, 112 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and 113 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and 114 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED. 115 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED 116 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED. 117 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1. 118 * Added rejected bits to SCSI Device Page 0 Information. 119 * Increased size of ALPA array in FC Port Page 2 by one 120 * and removed a one byte reserved field. 121 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in 122 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering. 123 * Added structures for Manufacturing Page 4, IO Unit 124 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and 125 * RAID PhysDisk Page 0. 126 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK. 127 * Modified some of the new defines to make them 32 128 * character unique. 129 * Modified how variable length pages (arrays) are defined. 130 * Added generic defines for hot spare pools and RAID 131 * volume types. 132 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR. 133 * 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with 134 * related define, and bumped the page version define. 135 * 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a 136 * reserved byte and added a define. 137 * Added define for 138 * MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE. 139 * Added new config page: CONFIG_PAGE_IOC_5. 140 * Added MaxAliases, MaxHardAliases, and NumCurrentAliases 141 * fields to CONFIG_PAGE_FC_PORT_0. 142 * Added AltConnector and NumRequestedAliases fields to 143 * CONFIG_PAGE_FC_PORT_1. 144 * Added new config page: CONFIG_PAGE_FC_PORT_10. 145 * 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines. 146 * Added additional MPI_SCSIDEVPAGE0_NP_ defines. 147 * Added more MPI_SCSIDEVPAGE1_RP_ defines. 148 * Added define for 149 * MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE. 150 * Added new config page: CONFIG_PAGE_SCSI_DEVICE_3. 151 * Modified MPI_FCPORTPAGE5_FLAGS_ defines. 152 * 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define. 153 * 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0. 154 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1. 155 * Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0. 156 * 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for 157 * CONFIG_PAGE_FC_PORT_1. 158 * Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable 159 * an alias. 160 * Added more device id defines. 161 * -------------------------------------------------------------------------- 162 */ 163 164 #ifndef MPI_CNFG_H 165 #define MPI_CNFG_H 166 167 168 /***************************************************************************** 169 * 170 * C o n f i g M e s s a g e a n d S t r u c t u r e s 171 * 172 *****************************************************************************/ 173 174 typedef struct _CONFIG_PAGE_HEADER 175 { 176 U8 PageVersion; /* 00h */ 177 U8 PageLength; /* 01h */ 178 U8 PageNumber; /* 02h */ 179 U8 PageType; /* 03h */ 180 } CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER, 181 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t; 182 183 typedef union _CONFIG_PAGE_HEADER_UNION 184 { 185 ConfigPageHeader_t Struct; 186 U8 Bytes[4]; 187 U16 Word16[2]; 188 U32 Word32; 189 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion, 190 CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION; 191 192 193 /**************************************************************************** 194 * PageType field values 195 ****************************************************************************/ 196 #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00) 197 #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10) 198 #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20) 199 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30) 200 #define MPI_CONFIG_PAGEATTR_MASK (0xF0) 201 202 #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00) 203 #define MPI_CONFIG_PAGETYPE_IOC (0x01) 204 #define MPI_CONFIG_PAGETYPE_BIOS (0x02) 205 #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03) 206 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04) 207 #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05) 208 #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06) 209 #define MPI_CONFIG_PAGETYPE_LAN (0x07) 210 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 211 #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09) 212 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 213 #define MPI_CONFIG_PAGETYPE_MASK (0x0F) 214 215 #define MPI_CONFIG_TYPENUM_MASK (0x0FFF) 216 217 218 /**************************************************************************** 219 * PageAddress field values 220 ****************************************************************************/ 221 #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF) 222 223 #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF) 224 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0) 225 #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00) 226 #define MPI_SCSI_DEVICE_BUS_SHIFT (8) 227 228 #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000) 229 #define MPI_FC_PORT_PGAD_PORT_SHIFT (28) 230 #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000) 231 #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000) 232 #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF) 233 #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0) 234 235 #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000) 236 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28) 237 #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000) 238 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000) 239 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000) 240 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28) 241 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF) 242 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0) 243 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000) 244 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 245 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8) 246 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 247 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0) 248 249 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 250 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0) 251 252 253 254 /**************************************************************************** 255 * Config Request Message 256 ****************************************************************************/ 257 typedef struct _MSG_CONFIG 258 { 259 U8 Action; /* 00h */ 260 U8 Reserved; /* 01h */ 261 U8 ChainOffset; /* 02h */ 262 U8 Function; /* 03h */ 263 U8 Reserved1[3]; /* 04h */ 264 U8 MsgFlags; /* 07h */ 265 U32 MsgContext; /* 08h */ 266 U8 Reserved2[8]; /* 0Ch */ 267 CONFIG_PAGE_HEADER Header; /* 14h */ 268 U32 PageAddress; /* 18h */ 269 SGE_IO_UNION PageBufferSGE; /* 1Ch */ 270 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG, 271 Config_t, MPI_POINTER pConfig_t; 272 273 274 /**************************************************************************** 275 * Action field values 276 ****************************************************************************/ 277 #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00) 278 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 279 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 280 #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03) 281 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 282 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 283 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 284 285 286 /* Config Reply Message */ 287 typedef struct _MSG_CONFIG_REPLY 288 { 289 U8 Action; /* 00h */ 290 U8 Reserved; /* 01h */ 291 U8 MsgLength; /* 02h */ 292 U8 Function; /* 03h */ 293 U8 Reserved1[3]; /* 04h */ 294 U8 MsgFlags; /* 07h */ 295 U32 MsgContext; /* 08h */ 296 U8 Reserved2[2]; /* 0Ch */ 297 U16 IOCStatus; /* 0Eh */ 298 U32 IOCLogInfo; /* 10h */ 299 CONFIG_PAGE_HEADER Header; /* 14h */ 300 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY, 301 ConfigReply_t, MPI_POINTER pConfigReply_t; 302 303 304 305 /***************************************************************************** 306 * 307 * C o n f i g u r a t i o n P a g e s 308 * 309 *****************************************************************************/ 310 311 /**************************************************************************** 312 * Manufacturing Config pages 313 ****************************************************************************/ 314 #define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000) 315 #define MPI_MANUFACTPAGE_VENDORID_TREBIA (0x1783) 316 317 #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621) 318 #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624) 319 #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622) 320 #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628) 321 #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626) 322 323 #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030) 324 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031) 325 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032) 326 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033) 327 #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040) 328 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041) 329 330 #define MPI_MANUFACTPAGE_DEVID_SA2010 (0x0804) 331 #define MPI_MANUFACTPAGE_DEVID_SA2010ZC (0x0805) 332 #define MPI_MANUFACTPAGE_DEVID_SA2020 (0x0806) 333 #define MPI_MANUFACTPAGE_DEVID_SA2020ZC (0x0807) 334 335 #define MPI_MANUFACTPAGE_DEVID_SNP1000 (0x0010) 336 #define MPI_MANUFACTPAGE_DEVID_SNP500 (0x0020) 337 338 339 340 typedef struct _CONFIG_PAGE_MANUFACTURING_0 341 { 342 CONFIG_PAGE_HEADER Header; /* 00h */ 343 U8 ChipName[16]; /* 04h */ 344 U8 ChipRevision[8]; /* 14h */ 345 U8 BoardName[16]; /* 1Ch */ 346 U8 BoardAssembly[16]; /* 2Ch */ 347 U8 BoardTracerNumber[16]; /* 3Ch */ 348 349 } CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0, 350 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t; 351 352 #define MPI_MANUFACTURING0_PAGEVERSION (0x00) 353 354 355 typedef struct _CONFIG_PAGE_MANUFACTURING_1 356 { 357 CONFIG_PAGE_HEADER Header; /* 00h */ 358 U8 VPD[256]; /* 04h */ 359 } CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1, 360 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t; 361 362 #define MPI_MANUFACTURING1_PAGEVERSION (0x00) 363 364 365 typedef struct _MPI_CHIP_REVISION_ID 366 { 367 U16 DeviceID; /* 00h */ 368 U8 PCIRevisionID; /* 02h */ 369 U8 Reserved; /* 03h */ 370 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID, 371 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t; 372 373 374 /* 375 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 376 * one and check Header.PageLength at runtime. 377 */ 378 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS 379 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 380 #endif 381 382 typedef struct _CONFIG_PAGE_MANUFACTURING_2 383 { 384 CONFIG_PAGE_HEADER Header; /* 00h */ 385 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 386 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */ 387 } CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2, 388 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t; 389 390 #define MPI_MANUFACTURING2_PAGEVERSION (0x00) 391 392 393 /* 394 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 395 * one and check Header.PageLength at runtime. 396 */ 397 #ifndef MPI_MAN_PAGE_3_INFO_WORDS 398 #define MPI_MAN_PAGE_3_INFO_WORDS (1) 399 #endif 400 401 typedef struct _CONFIG_PAGE_MANUFACTURING_3 402 { 403 CONFIG_PAGE_HEADER Header; /* 00h */ 404 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 405 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */ 406 } CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3, 407 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t; 408 409 #define MPI_MANUFACTURING3_PAGEVERSION (0x00) 410 411 412 typedef struct _CONFIG_PAGE_MANUFACTURING_4 413 { 414 CONFIG_PAGE_HEADER Header; /* 00h */ 415 U32 Reserved1; /* 04h */ 416 U8 InfoOffset0; /* 08h */ 417 U8 InfoSize0; /* 09h */ 418 U8 InfoOffset1; /* 0Ah */ 419 U8 InfoSize1; /* 0Bh */ 420 U8 InquirySize; /* 0Ch */ 421 U8 Reserved2; /* 0Dh */ 422 U16 Reserved3; /* 0Eh */ 423 U8 InquiryData[56]; /* 10h */ 424 U32 ISVolumeSettings; /* 48h */ 425 U32 IMEVolumeSettings; /* 4Ch */ 426 U32 IMVolumeSettings; /* 50h */ 427 } CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4, 428 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t; 429 430 #define MPI_MANUFACTURING4_PAGEVERSION (0x00) 431 432 433 /**************************************************************************** 434 * IO Unit Config Pages 435 ****************************************************************************/ 436 437 typedef struct _CONFIG_PAGE_IO_UNIT_0 438 { 439 CONFIG_PAGE_HEADER Header; /* 00h */ 440 U64 UniqueValue; /* 04h */ 441 } CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0, 442 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t; 443 444 #define MPI_IOUNITPAGE0_PAGEVERSION (0x00) 445 446 447 typedef struct _CONFIG_PAGE_IO_UNIT_1 448 { 449 CONFIG_PAGE_HEADER Header; /* 00h */ 450 U32 Flags; /* 04h */ 451 } CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1, 452 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t; 453 454 #define MPI_IOUNITPAGE1_PAGEVERSION (0x00) 455 456 /* IO Unit Page 1 Flags defines */ 457 458 #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000) 459 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001) 460 #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002) 461 #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000) 462 #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040) 463 #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080) 464 465 466 typedef struct _MPI_ADAPTER_INFO 467 { 468 U8 PciBusNumber; /* 00h */ 469 U8 PciDeviceAndFunctionNumber; /* 01h */ 470 U16 AdapterFlags; /* 02h */ 471 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO, 472 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t; 473 474 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 475 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 476 477 typedef struct _CONFIG_PAGE_IO_UNIT_2 478 { 479 CONFIG_PAGE_HEADER Header; /* 00h */ 480 U32 Flags; /* 04h */ 481 U32 BiosVersion; /* 08h */ 482 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */ 483 } CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2, 484 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t; 485 486 #define MPI_IOUNITPAGE2_PAGEVERSION (0x00) 487 488 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002) 489 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004) 490 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008) 491 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010) 492 493 494 /* 495 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 496 * one and check Header.PageLength at runtime. 497 */ 498 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX 499 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 500 #endif 501 502 typedef struct _CONFIG_PAGE_IO_UNIT_3 503 { 504 CONFIG_PAGE_HEADER Header; /* 00h */ 505 U8 GPIOCount; /* 04h */ 506 U8 Reserved1; /* 05h */ 507 U16 Reserved2; /* 06h */ 508 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */ 509 } CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3, 510 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t; 511 512 #define MPI_IOUNITPAGE3_PAGEVERSION (0x01) 513 514 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC) 515 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 516 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00) 517 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01) 518 519 520 /**************************************************************************** 521 * IOC Config Pages 522 ****************************************************************************/ 523 524 typedef struct _CONFIG_PAGE_IOC_0 525 { 526 CONFIG_PAGE_HEADER Header; /* 00h */ 527 U32 TotalNVStore; /* 04h */ 528 U32 FreeNVStore; /* 08h */ 529 U16 VendorID; /* 0Ch */ 530 U16 DeviceID; /* 0Eh */ 531 U8 RevisionID; /* 10h */ 532 U8 Reserved[3]; /* 11h */ 533 U32 ClassCode; /* 14h */ 534 U16 SubsystemVendorID; /* 18h */ 535 U16 SubsystemID; /* 1Ah */ 536 } CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0, 537 IOCPage0_t, MPI_POINTER pIOCPage0_t; 538 539 #define MPI_IOCPAGE0_PAGEVERSION (0x01) 540 541 542 typedef struct _CONFIG_PAGE_IOC_1 543 { 544 CONFIG_PAGE_HEADER Header; /* 00h */ 545 U32 Flags; /* 04h */ 546 U32 CoalescingTimeout; /* 08h */ 547 U8 CoalescingDepth; /* 0Ch */ 548 U8 PCISlotNum; /* 0Dh */ 549 U8 Reserved[2]; /* 0Eh */ 550 } CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1, 551 IOCPage1_t, MPI_POINTER pIOCPage1_t; 552 553 #define MPI_IOCPAGE1_PAGEVERSION (0x01) 554 555 #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001) 556 557 #define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 558 559 560 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL 561 { 562 U8 VolumeID; /* 00h */ 563 U8 VolumeBus; /* 01h */ 564 U8 VolumeIOC; /* 02h */ 565 U8 VolumePageNumber; /* 03h */ 566 U8 VolumeType; /* 04h */ 567 U8 Flags; /* 05h */ 568 U16 Reserved3; /* 06h */ 569 } CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL, 570 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t; 571 572 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */ 573 574 #define MPI_RAID_VOL_TYPE_IS (0x00) 575 #define MPI_RAID_VOL_TYPE_IME (0x01) 576 #define MPI_RAID_VOL_TYPE_IM (0x02) 577 578 /* IOC Page 2 Volume Flags values */ 579 580 #define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08) 581 582 /* 583 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 584 * one and check Header.PageLength at runtime. 585 */ 586 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX 587 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1) 588 #endif 589 590 typedef struct _CONFIG_PAGE_IOC_2 591 { 592 CONFIG_PAGE_HEADER Header; /* 00h */ 593 U32 CapabilitiesFlags; /* 04h */ 594 U8 NumActiveVolumes; /* 08h */ 595 U8 MaxVolumes; /* 09h */ 596 U8 NumActivePhysDisks; /* 0Ah */ 597 U8 MaxPhysDisks; /* 0Bh */ 598 CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */ 599 } CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2, 600 IOCPage2_t, MPI_POINTER pIOCPage2_t; 601 602 #define MPI_IOCPAGE2_PAGEVERSION (0x02) 603 604 /* IOC Page 2 Capabilities flags */ 605 606 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001) 607 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002) 608 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004) 609 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000) 610 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000) 611 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000) 612 613 614 typedef struct _IOC_3_PHYS_DISK 615 { 616 U8 PhysDiskID; /* 00h */ 617 U8 PhysDiskBus; /* 01h */ 618 U8 PhysDiskIOC; /* 02h */ 619 U8 PhysDiskNum; /* 03h */ 620 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK, 621 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t; 622 623 /* 624 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 625 * one and check Header.PageLength at runtime. 626 */ 627 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX 628 #define MPI_IOC_PAGE_3_PHYSDISK_MAX (1) 629 #endif 630 631 typedef struct _CONFIG_PAGE_IOC_3 632 { 633 CONFIG_PAGE_HEADER Header; /* 00h */ 634 U8 NumPhysDisks; /* 04h */ 635 U8 Reserved1; /* 05h */ 636 U16 Reserved2; /* 06h */ 637 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */ 638 } CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3, 639 IOCPage3_t, MPI_POINTER pIOCPage3_t; 640 641 #define MPI_IOCPAGE3_PAGEVERSION (0x00) 642 643 644 typedef struct _IOC_4_SEP 645 { 646 U8 SEPTargetID; /* 00h */ 647 U8 SEPBus; /* 01h */ 648 U16 Reserved; /* 02h */ 649 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP, 650 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t; 651 652 /* 653 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 654 * one and check Header.PageLength at runtime. 655 */ 656 #ifndef MPI_IOC_PAGE_4_SEP_MAX 657 #define MPI_IOC_PAGE_4_SEP_MAX (1) 658 #endif 659 660 typedef struct _CONFIG_PAGE_IOC_4 661 { 662 CONFIG_PAGE_HEADER Header; /* 00h */ 663 U8 ActiveSEP; /* 04h */ 664 U8 MaxSEP; /* 05h */ 665 U16 Reserved1; /* 06h */ 666 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */ 667 } CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4, 668 IOCPage4_t, MPI_POINTER pIOCPage4_t; 669 670 #define MPI_IOCPAGE4_PAGEVERSION (0x00) 671 672 673 typedef struct _IOC_5_HOT_SPARE 674 { 675 U8 PhysDiskNum; /* 00h */ 676 U8 Reserved; /* 01h */ 677 U8 HotSparePool; /* 02h */ 678 U8 Flags; /* 03h */ 679 } IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE, 680 Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t; 681 682 /* IOC Page 5 HotSpare Flags */ 683 #define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01) 684 685 /* 686 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 687 * one and check Header.PageLength at runtime. 688 */ 689 #ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX 690 #define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1) 691 #endif 692 693 typedef struct _CONFIG_PAGE_IOC_5 694 { 695 CONFIG_PAGE_HEADER Header; /* 00h */ 696 U32 Reserved1; /* 04h */ 697 U8 NumHotSpares; /* 08h */ 698 U8 Reserved2; /* 09h */ 699 U16 Reserved3; /* 0Ah */ 700 IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */ 701 } CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5, 702 IOCPage5_t, MPI_POINTER pIOCPage5_t; 703 704 #define MPI_IOCPAGE5_PAGEVERSION (0x00) 705 706 707 708 /**************************************************************************** 709 * SCSI Port Config Pages 710 ****************************************************************************/ 711 712 typedef struct _CONFIG_PAGE_SCSI_PORT_0 713 { 714 CONFIG_PAGE_HEADER Header; /* 00h */ 715 U32 Capabilities; /* 04h */ 716 U32 PhysicalInterface; /* 08h */ 717 } CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0, 718 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t; 719 720 #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x01) 721 722 #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001) 723 #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002) 724 #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004) 725 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 726 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 727 #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000) 728 #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000) 729 730 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003) 731 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01) 732 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02) 733 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03) 734 #define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000) 735 #define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24) 736 #define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE) 737 #define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF) 738 739 740 typedef struct _CONFIG_PAGE_SCSI_PORT_1 741 { 742 CONFIG_PAGE_HEADER Header; /* 00h */ 743 U32 Configuration; /* 04h */ 744 U32 OnBusTimerValue; /* 08h */ 745 } CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1, 746 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t; 747 748 #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x02) 749 750 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF) 751 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000) 752 753 754 typedef struct _MPI_DEVICE_INFO 755 { 756 U8 Timeout; /* 00h */ 757 U8 SyncFactor; /* 01h */ 758 U16 DeviceFlags; /* 02h */ 759 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO, 760 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t; 761 762 typedef struct _CONFIG_PAGE_SCSI_PORT_2 763 { 764 CONFIG_PAGE_HEADER Header; /* 00h */ 765 U32 PortFlags; /* 04h */ 766 U32 PortSettings; /* 08h */ 767 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */ 768 } CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2, 769 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t; 770 771 #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x01) 772 773 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001) 774 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004) 775 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 776 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010) 777 778 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F) 779 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030) 780 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000) 781 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010) 782 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020) 783 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030) 784 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0) 785 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00) 786 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000) 787 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000) 788 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000) 789 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000) 790 791 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001) 792 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002) 793 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004) 794 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008) 795 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010) 796 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020) 797 798 799 /**************************************************************************** 800 * SCSI Target Device Config Pages 801 ****************************************************************************/ 802 803 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0 804 { 805 CONFIG_PAGE_HEADER Header; /* 00h */ 806 U32 NegotiatedParameters; /* 04h */ 807 U32 Information; /* 08h */ 808 } CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0, 809 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t; 810 811 #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x03) 812 813 #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001) 814 #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002) 815 #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004) 816 #define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008) 817 #define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010) 818 #define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020) 819 #define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040) 820 #define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080) 821 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00) 822 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000) 823 #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000) 824 #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000) 825 826 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001) 827 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002) 828 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004) 829 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008) 830 831 832 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1 833 { 834 CONFIG_PAGE_HEADER Header; /* 00h */ 835 U32 RequestedParameters; /* 04h */ 836 U32 Reserved; /* 08h */ 837 U32 Configuration; /* 0Ch */ 838 } CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1, 839 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t; 840 841 #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x04) 842 843 #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001) 844 #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002) 845 #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004) 846 #define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008) 847 #define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010) 848 #define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020) 849 #define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040) 850 #define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080) 851 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 852 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 853 #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000) 854 #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000) 855 856 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002) 857 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004) 858 #define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008) 859 #define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010) 860 861 862 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2 863 { 864 CONFIG_PAGE_HEADER Header; /* 00h */ 865 U32 DomainValidation; /* 04h */ 866 U32 ParityPipeSelect; /* 08h */ 867 U32 DataPipeSelect; /* 0Ch */ 868 } CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2, 869 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t; 870 871 #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01) 872 873 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010) 874 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020) 875 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380) 876 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00) 877 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000) 878 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000) 879 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000) 880 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000) 881 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000) 882 883 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003) 884 885 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003) 886 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C) 887 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030) 888 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0) 889 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300) 890 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00) 891 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000) 892 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000) 893 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000) 894 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000) 895 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000) 896 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000) 897 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000) 898 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000) 899 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000) 900 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000) 901 902 903 typedef struct _CONFIG_PAGE_SCSI_DEVICE_3 904 { 905 CONFIG_PAGE_HEADER Header; /* 00h */ 906 U16 MsgRejectCount; /* 04h */ 907 U16 PhaseErrorCount; /* 06h */ 908 U16 ParityErrorCount; /* 08h */ 909 U16 Reserved; /* 0Ah */ 910 } CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3, 911 SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t; 912 913 #define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00) 914 915 #define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE) 916 #define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF) 917 918 919 /**************************************************************************** 920 * FC Port Config Pages 921 ****************************************************************************/ 922 923 typedef struct _CONFIG_PAGE_FC_PORT_0 924 { 925 CONFIG_PAGE_HEADER Header; /* 00h */ 926 U32 Flags; /* 04h */ 927 U8 MPIPortNumber; /* 08h */ 928 U8 LinkType; /* 09h */ 929 U8 PortState; /* 0Ah */ 930 U8 Reserved; /* 0Bh */ 931 U32 PortIdentifier; /* 0Ch */ 932 U64 WWNN; /* 10h */ 933 U64 WWPN; /* 18h */ 934 U32 SupportedServiceClass; /* 20h */ 935 U32 SupportedSpeeds; /* 24h */ 936 U32 CurrentSpeed; /* 28h */ 937 U32 MaxFrameSize; /* 2Ch */ 938 U64 FabricWWNN; /* 30h */ 939 U64 FabricWWPN; /* 38h */ 940 U32 DiscoveredPortsCount; /* 40h */ 941 U32 MaxInitiators; /* 44h */ 942 U8 MaxAliasesSupported; /* 48h */ 943 U8 MaxHardAliasesSupported; /* 49h */ 944 U8 NumCurrentAliases; /* 4Ah */ 945 U8 Reserved1; /* 4Bh */ 946 } CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0, 947 FCPortPage0_t, MPI_POINTER pFCPortPage0_t; 948 949 #define MPI_FCPORTPAGE0_PAGEVERSION (0x02) 950 951 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F) 952 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR) 953 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET) 954 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN) 955 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR) 956 957 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010) 958 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020) 959 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040) 960 961 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00) 962 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000) 963 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100) 964 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200) 965 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400) 966 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800) 967 968 #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00) 969 #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01) 970 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02) 971 #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03) 972 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04) 973 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05) 974 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06) 975 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07) 976 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08) 977 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09) 978 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A) 979 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B) 980 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C) 981 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D) 982 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E) 983 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F) 984 985 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */ 986 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */ 987 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */ 988 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */ 989 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */ 990 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */ 991 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */ 992 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */ 993 994 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001) 995 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002) 996 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004) 997 998 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */ 999 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */ 1000 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */ 1001 1002 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED 1003 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED 1004 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED 1005 1006 1007 typedef struct _CONFIG_PAGE_FC_PORT_1 1008 { 1009 CONFIG_PAGE_HEADER Header; /* 00h */ 1010 U32 Flags; /* 04h */ 1011 U64 NoSEEPROMWWNN; /* 08h */ 1012 U64 NoSEEPROMWWPN; /* 10h */ 1013 U8 HardALPA; /* 18h */ 1014 U8 LinkConfig; /* 19h */ 1015 U8 TopologyConfig; /* 1Ah */ 1016 U8 AltConnector; /* 1Bh */ 1017 U8 NumRequestedAliases; /* 1Ch */ 1018 U8 RR_TOV; /* 1Dh */ 1019 U16 Reserved2; /* 1Eh */ 1020 } CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1, 1021 FCPortPage1_t, MPI_POINTER pFCPortPage1_t; 1022 1023 #define MPI_FCPORTPAGE1_PAGEVERSION (0x05) 1024 1025 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000) 1026 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000) 1027 #define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000) 1028 #define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000) 1029 #define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000) 1030 #define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070) 1031 #define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002) 1032 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001) 1033 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000) 1034 1035 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000) 1036 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28) 1037 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1038 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1039 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1040 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1041 1042 #define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000) 1043 #define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010) 1044 #define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030) 1045 #define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050) 1046 1047 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF) 1048 1049 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F) 1050 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00) 1051 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01) 1052 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02) 1053 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03) 1054 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F) 1055 1056 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F) 1057 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01) 1058 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02) 1059 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F) 1060 1061 #define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00) 1062 1063 1064 typedef struct _CONFIG_PAGE_FC_PORT_2 1065 { 1066 CONFIG_PAGE_HEADER Header; /* 00h */ 1067 U8 NumberActive; /* 04h */ 1068 U8 ALPA[127]; /* 05h */ 1069 } CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2, 1070 FCPortPage2_t, MPI_POINTER pFCPortPage2_t; 1071 1072 #define MPI_FCPORTPAGE2_PAGEVERSION (0x01) 1073 1074 1075 typedef struct _WWN_FORMAT 1076 { 1077 U64 WWNN; /* 00h */ 1078 U64 WWPN; /* 08h */ 1079 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT, 1080 WWNFormat, MPI_POINTER pWWNFormat; 1081 1082 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID 1083 { 1084 WWN_FORMAT WWN; 1085 U32 Did; 1086 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID, 1087 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t; 1088 1089 typedef struct _FC_PORT_PERSISTENT 1090 { 1091 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */ 1092 U8 TargetID; /* 10h */ 1093 U8 Bus; /* 11h */ 1094 U16 Flags; /* 12h */ 1095 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT, 1096 PersistentData_t, MPI_POINTER pPersistentData_t; 1097 1098 #define MPI_PERSISTENT_FLAGS_SHIFT (16) 1099 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001) 1100 #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002) 1101 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004) 1102 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008) 1103 #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080) 1104 1105 /* 1106 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1107 * one and check Header.PageLength at runtime. 1108 */ 1109 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX 1110 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1) 1111 #endif 1112 1113 typedef struct _CONFIG_PAGE_FC_PORT_3 1114 { 1115 CONFIG_PAGE_HEADER Header; /* 00h */ 1116 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */ 1117 } CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3, 1118 FCPortPage3_t, MPI_POINTER pFCPortPage3_t; 1119 1120 #define MPI_FCPORTPAGE3_PAGEVERSION (0x01) 1121 1122 1123 typedef struct _CONFIG_PAGE_FC_PORT_4 1124 { 1125 CONFIG_PAGE_HEADER Header; /* 00h */ 1126 U32 PortFlags; /* 04h */ 1127 U32 PortSettings; /* 08h */ 1128 } CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4, 1129 FCPortPage4_t, MPI_POINTER pFCPortPage4_t; 1130 1131 #define MPI_FCPORTPAGE4_PAGEVERSION (0x00) 1132 1133 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1134 1135 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030) 1136 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000) 1137 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010) 1138 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020) 1139 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030) 1140 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0) 1141 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00) 1142 1143 1144 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO 1145 { 1146 U8 Flags; /* 00h */ 1147 U8 AliasAlpa; /* 01h */ 1148 U16 Reserved; /* 02h */ 1149 U64 AliasWWNN; /* 04h */ 1150 U64 AliasWWPN; /* 0Ch */ 1151 } CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1152 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1153 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t; 1154 1155 typedef struct _CONFIG_PAGE_FC_PORT_5 1156 { 1157 CONFIG_PAGE_HEADER Header; /* 00h */ 1158 CONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */ 1159 } CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5, 1160 FCPortPage5_t, MPI_POINTER pFCPortPage5_t; 1161 1162 #define MPI_FCPORTPAGE5_PAGEVERSION (0x02) 1163 1164 #define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01) 1165 #define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02) 1166 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04) 1167 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08) 1168 #define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10) 1169 1170 typedef struct _CONFIG_PAGE_FC_PORT_6 1171 { 1172 CONFIG_PAGE_HEADER Header; /* 00h */ 1173 U32 Reserved; /* 04h */ 1174 U64 TimeSinceReset; /* 08h */ 1175 U64 TxFrames; /* 10h */ 1176 U64 RxFrames; /* 18h */ 1177 U64 TxWords; /* 20h */ 1178 U64 RxWords; /* 28h */ 1179 U64 LipCount; /* 30h */ 1180 U64 NosCount; /* 38h */ 1181 U64 ErrorFrames; /* 40h */ 1182 U64 DumpedFrames; /* 48h */ 1183 U64 LinkFailureCount; /* 50h */ 1184 U64 LossOfSyncCount; /* 58h */ 1185 U64 LossOfSignalCount; /* 60h */ 1186 U64 PrimativeSeqErrCount; /* 68h */ 1187 U64 InvalidTxWordCount; /* 70h */ 1188 U64 InvalidCrcCount; /* 78h */ 1189 U64 FcpInitiatorIoCount; /* 80h */ 1190 } CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6, 1191 FCPortPage6_t, MPI_POINTER pFCPortPage6_t; 1192 1193 #define MPI_FCPORTPAGE6_PAGEVERSION (0x00) 1194 1195 1196 typedef struct _CONFIG_PAGE_FC_PORT_7 1197 { 1198 CONFIG_PAGE_HEADER Header; /* 00h */ 1199 U32 Reserved; /* 04h */ 1200 U8 PortSymbolicName[256]; /* 08h */ 1201 } CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7, 1202 FCPortPage7_t, MPI_POINTER pFCPortPage7_t; 1203 1204 #define MPI_FCPORTPAGE7_PAGEVERSION (0x00) 1205 1206 1207 typedef struct _CONFIG_PAGE_FC_PORT_8 1208 { 1209 CONFIG_PAGE_HEADER Header; /* 00h */ 1210 U32 BitVector[8]; /* 04h */ 1211 } CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8, 1212 FCPortPage8_t, MPI_POINTER pFCPortPage8_t; 1213 1214 #define MPI_FCPORTPAGE8_PAGEVERSION (0x00) 1215 1216 1217 typedef struct _CONFIG_PAGE_FC_PORT_9 1218 { 1219 CONFIG_PAGE_HEADER Header; /* 00h */ 1220 U32 Reserved; /* 04h */ 1221 U64 GlobalWWPN; /* 08h */ 1222 U64 GlobalWWNN; /* 10h */ 1223 U32 UnitType; /* 18h */ 1224 U32 PhysicalPortNumber; /* 1Ch */ 1225 U32 NumAttachedNodes; /* 20h */ 1226 U16 IPVersion; /* 24h */ 1227 U16 UDPPortNumber; /* 26h */ 1228 U8 IPAddress[16]; /* 28h */ 1229 U16 Reserved1; /* 38h */ 1230 U16 TopologyDiscoveryFlags; /* 3Ah */ 1231 } CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9, 1232 FCPortPage9_t, MPI_POINTER pFCPortPage9_t; 1233 1234 #define MPI_FCPORTPAGE9_PAGEVERSION (0x00) 1235 1236 1237 typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA 1238 { 1239 U8 Id; /* 10h */ 1240 U8 ExtId; /* 11h */ 1241 U8 Connector; /* 12h */ 1242 U8 Transceiver[8]; /* 13h */ 1243 U8 Encoding; /* 1Bh */ 1244 U8 BitRate_100mbs; /* 1Ch */ 1245 U8 Reserved1; /* 1Dh */ 1246 U8 Length9u_km; /* 1Eh */ 1247 U8 Length9u_100m; /* 1Fh */ 1248 U8 Length50u_10m; /* 20h */ 1249 U8 Length62p5u_10m; /* 21h */ 1250 U8 LengthCopper_m; /* 22h */ 1251 U8 Reseverved2; /* 22h */ 1252 U8 VendorName[16]; /* 24h */ 1253 U8 Reserved3; /* 34h */ 1254 U8 VendorOUI[3]; /* 35h */ 1255 U8 VendorPN[16]; /* 38h */ 1256 U8 VendorRev[4]; /* 48h */ 1257 U16 Reserved4; /* 4Ch */ 1258 U8 Reserved5; /* 4Eh */ 1259 U8 CC_BASE; /* 4Fh */ 1260 } CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA, 1261 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA, 1262 FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t; 1263 1264 #define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00) 1265 #define MPI_FCPORT10_BASE_ID_GBIC (0x01) 1266 #define MPI_FCPORT10_BASE_ID_FIXED (0x02) 1267 #define MPI_FCPORT10_BASE_ID_SFP (0x03) 1268 #define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04) 1269 #define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F) 1270 #define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80) 1271 1272 #define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00) 1273 #define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01) 1274 #define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02) 1275 #define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03) 1276 #define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04) 1277 #define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05) 1278 #define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06) 1279 #define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07) 1280 #define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80) 1281 1282 #define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00) 1283 #define MPI_FCPORT10_BASE_CONN_SC (0x01) 1284 #define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02) 1285 #define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03) 1286 #define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04) 1287 #define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05) 1288 #define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06) 1289 #define MPI_FCPORT10_BASE_CONN_LC (0x07) 1290 #define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08) 1291 #define MPI_FCPORT10_BASE_CONN_MU (0x09) 1292 #define MPI_FCPORT10_BASE_CONN_SG (0x0A) 1293 #define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B) 1294 #define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C) 1295 #define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F) 1296 #define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20) 1297 #define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21) 1298 #define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22) 1299 #define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F) 1300 #define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80) 1301 1302 #define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00) 1303 #define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01) 1304 #define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02) 1305 #define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03) 1306 #define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04) 1307 1308 1309 typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA 1310 { 1311 U8 Options[2]; /* 50h */ 1312 U8 BitRateMax; /* 52h */ 1313 U8 BitRateMin; /* 53h */ 1314 U8 VendorSN[16]; /* 54h */ 1315 U8 DateCode[8]; /* 64h */ 1316 U8 Reserved5[3]; /* 6Ch */ 1317 U8 CC_EXT; /* 6Fh */ 1318 } CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA, 1319 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA, 1320 FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t; 1321 1322 #define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20) 1323 #define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10) 1324 #define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08) 1325 #define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04) 1326 #define MPI_FCPORT10_EXT_OPTION1_LOS (0x02) 1327 1328 1329 typedef struct _CONFIG_PAGE_FC_PORT_10 1330 { 1331 CONFIG_PAGE_HEADER Header; /* 00h */ 1332 U8 Flags; /* 04h */ 1333 U8 Reserved1; /* 05h */ 1334 U16 Reserved2; /* 06h */ 1335 U32 HwConfig1; /* 08h */ 1336 U32 HwConfig2; /* 0Ch */ 1337 CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */ 1338 CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */ 1339 U8 VendorSpecific[32]; /* 70h */ 1340 } CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10, 1341 FCPortPage10_t, MPI_POINTER pFCPortPage10_t; 1342 1343 #define MPI_FCPORTPAGE10_PAGEVERSION (0x00) 1344 1345 /* standard MODDEF pin definitions (from GBIC spec.) */ 1346 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007) 1347 #define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001) 1348 #define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002) 1349 #define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004) 1350 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007) 1351 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006) 1352 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005) 1353 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004) 1354 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003) 1355 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002) 1356 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001) 1357 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000) 1358 1359 #define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010) 1360 #define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020) 1361 1362 1363 /**************************************************************************** 1364 * FC Device Config Pages 1365 ****************************************************************************/ 1366 1367 typedef struct _CONFIG_PAGE_FC_DEVICE_0 1368 { 1369 CONFIG_PAGE_HEADER Header; /* 00h */ 1370 U64 WWNN; /* 04h */ 1371 U64 WWPN; /* 0Ch */ 1372 U32 PortIdentifier; /* 14h */ 1373 U8 Protocol; /* 18h */ 1374 U8 Flags; /* 19h */ 1375 U16 BBCredit; /* 1Ah */ 1376 U16 MaxRxFrameSize; /* 1Ch */ 1377 U8 Reserved1; /* 1Eh */ 1378 U8 PortNumber; /* 1Fh */ 1379 U8 FcPhLowestVersion; /* 20h */ 1380 U8 FcPhHighestVersion; /* 21h */ 1381 U8 CurrentTargetID; /* 22h */ 1382 U8 CurrentBus; /* 23h */ 1383 } CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0, 1384 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t; 1385 1386 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x02) 1387 1388 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01) 1389 #define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02) 1390 #define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04) 1391 1392 #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01) 1393 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02) 1394 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04) 1395 1396 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK) 1397 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK) 1398 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) 1399 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID) 1400 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK) 1401 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK) 1402 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT) 1403 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK) 1404 1405 1406 /**************************************************************************** 1407 * RAID Volume Config Pages 1408 ****************************************************************************/ 1409 1410 typedef struct _RAID_VOL0_PHYS_DISK 1411 { 1412 U16 Reserved; /* 00h */ 1413 U8 PhysDiskMap; /* 02h */ 1414 U8 PhysDiskNum; /* 03h */ 1415 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK, 1416 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t; 1417 1418 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1419 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1420 1421 typedef struct _RAID_VOL0_STATUS 1422 { 1423 U8 Flags; /* 00h */ 1424 U8 State; /* 01h */ 1425 U16 Reserved; /* 02h */ 1426 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS, 1427 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t; 1428 1429 /* RAID Volume Page 0 VolumeStatus defines */ 1430 1431 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01) 1432 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02) 1433 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04) 1434 #define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08) 1435 1436 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00) 1437 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01) 1438 #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02) 1439 1440 typedef struct _RAID_VOL0_SETTINGS 1441 { 1442 U16 Settings; /* 00h */ 1443 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 1444 U8 Reserved; /* 02h */ 1445 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS, 1446 RaidVol0Settings, MPI_POINTER pRaidVol0Settings; 1447 1448 /* RAID Volume Page 0 VolumeSettings defines */ 1449 1450 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001) 1451 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002) 1452 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004) 1453 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008) 1454 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010) 1455 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000) 1456 1457 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1458 #define MPI_RAID_HOT_SPARE_POOL_0 (0x01) 1459 #define MPI_RAID_HOT_SPARE_POOL_1 (0x02) 1460 #define MPI_RAID_HOT_SPARE_POOL_2 (0x04) 1461 #define MPI_RAID_HOT_SPARE_POOL_3 (0x08) 1462 #define MPI_RAID_HOT_SPARE_POOL_4 (0x10) 1463 #define MPI_RAID_HOT_SPARE_POOL_5 (0x20) 1464 #define MPI_RAID_HOT_SPARE_POOL_6 (0x40) 1465 #define MPI_RAID_HOT_SPARE_POOL_7 (0x80) 1466 1467 /* 1468 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1469 * one and check Header.PageLength at runtime. 1470 */ 1471 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX 1472 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1473 #endif 1474 1475 typedef struct _CONFIG_PAGE_RAID_VOL_0 1476 { 1477 CONFIG_PAGE_HEADER Header; /* 00h */ 1478 U8 VolumeID; /* 04h */ 1479 U8 VolumeBus; /* 05h */ 1480 U8 VolumeIOC; /* 06h */ 1481 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */ 1482 RAID_VOL0_STATUS VolumeStatus; /* 08h */ 1483 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */ 1484 U32 MaxLBA; /* 10h */ 1485 U32 Reserved1; /* 14h */ 1486 U32 StripeSize; /* 18h */ 1487 U32 Reserved2; /* 1Ch */ 1488 U32 Reserved3; /* 20h */ 1489 U8 NumPhysDisks; /* 24h */ 1490 U8 Reserved4; /* 25h */ 1491 U16 Reserved5; /* 26h */ 1492 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */ 1493 } CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0, 1494 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t; 1495 1496 #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x01) 1497 1498 1499 /**************************************************************************** 1500 * RAID Physical Disk Config Pages 1501 ****************************************************************************/ 1502 1503 typedef struct _RAID_PHYS_DISK0_ERROR_DATA 1504 { 1505 U8 ErrorCdbByte; /* 00h */ 1506 U8 ErrorSenseKey; /* 01h */ 1507 U16 Reserved; /* 02h */ 1508 U16 ErrorCount; /* 04h */ 1509 U8 ErrorASC; /* 06h */ 1510 U8 ErrorASCQ; /* 07h */ 1511 U16 SmartCount; /* 08h */ 1512 U8 SmartASC; /* 0Ah */ 1513 U8 SmartASCQ; /* 0Bh */ 1514 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA, 1515 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t; 1516 1517 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA 1518 { 1519 U8 VendorID[8]; /* 00h */ 1520 U8 ProductID[16]; /* 08h */ 1521 U8 ProductRevLevel[4]; /* 18h */ 1522 U8 Info[32]; /* 1Ch */ 1523 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA, 1524 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData; 1525 1526 typedef struct _RAID_PHYS_DISK0_SETTINGS 1527 { 1528 U8 SepID; /* 00h */ 1529 U8 SepBus; /* 01h */ 1530 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 1531 U8 PhysDiskSettings; /* 03h */ 1532 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS, 1533 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t; 1534 1535 typedef struct _RAID_PHYS_DISK0_STATUS 1536 { 1537 U8 Flags; /* 00h */ 1538 U8 State; /* 01h */ 1539 U16 Reserved; /* 02h */ 1540 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS, 1541 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t; 1542 1543 /* RAID Volume 2 IM Physical Disk DiskStatus flags */ 1544 1545 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01) 1546 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02) 1547 1548 #define MPI_PHYSDISK0_STATUS_ONLINE (0x00) 1549 #define MPI_PHYSDISK0_STATUS_MISSING (0x01) 1550 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02) 1551 #define MPI_PHYSDISK0_STATUS_FAILED (0x03) 1552 #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04) 1553 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05) 1554 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06) 1555 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF) 1556 1557 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0 1558 { 1559 CONFIG_PAGE_HEADER Header; /* 00h */ 1560 U8 PhysDiskID; /* 04h */ 1561 U8 PhysDiskBus; /* 05h */ 1562 U8 PhysDiskIOC; /* 06h */ 1563 U8 PhysDiskNum; /* 07h */ 1564 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */ 1565 U32 Reserved1; /* 0Ch */ 1566 U32 Reserved2; /* 10h */ 1567 U32 Reserved3; /* 14h */ 1568 U8 DiskIdentifier[16]; /* 18h */ 1569 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */ 1570 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */ 1571 U32 MaxLBA; /* 68h */ 1572 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */ 1573 } CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0, 1574 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t; 1575 1576 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x00) 1577 1578 1579 /**************************************************************************** 1580 * LAN Config Pages 1581 ****************************************************************************/ 1582 1583 typedef struct _CONFIG_PAGE_LAN_0 1584 { 1585 ConfigPageHeader_t Header; /* 00h */ 1586 U16 TxRxModes; /* 04h */ 1587 U16 Reserved; /* 06h */ 1588 U32 PacketPrePad; /* 08h */ 1589 } CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0, 1590 LANPage0_t, MPI_POINTER pLANPage0_t; 1591 1592 #define MPI_LAN_PAGE0_PAGEVERSION (0x01) 1593 1594 #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000) 1595 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001) 1596 #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001) 1597 1598 typedef struct _CONFIG_PAGE_LAN_1 1599 { 1600 ConfigPageHeader_t Header; /* 00h */ 1601 U16 Reserved; /* 04h */ 1602 U8 CurrentDeviceState; /* 06h */ 1603 U8 Reserved1; /* 07h */ 1604 U32 MinPacketSize; /* 08h */ 1605 U32 MaxPacketSize; /* 0Ch */ 1606 U32 HardwareAddressLow; /* 10h */ 1607 U32 HardwareAddressHigh; /* 14h */ 1608 U32 MaxWireSpeedLow; /* 18h */ 1609 U32 MaxWireSpeedHigh; /* 1Ch */ 1610 U32 BucketsRemaining; /* 20h */ 1611 U32 MaxReplySize; /* 24h */ 1612 U32 NegWireSpeedLow; /* 28h */ 1613 U32 NegWireSpeedHigh; /* 2Ch */ 1614 } CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1, 1615 LANPage1_t, MPI_POINTER pLANPage1_t; 1616 1617 #define MPI_LAN_PAGE1_PAGEVERSION (0x03) 1618 1619 #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00) 1620 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01) 1621 1622 #endif 1623 1624