1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2000-2005, LSI Logic Corporation and its contributors. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * substantially similar to the "NO WARRANTY" disclaimer below 13 * ("Disclaimer") and any redistribution must be conditioned upon including 14 * a substantially similar Disclaimer requirement for further binary 15 * redistribution. 16 * 3. Neither the name of the LSI Logic Corporation nor the names of its 17 * contributors may be used to endorse or promote products derived from 18 * this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT 30 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * 33 * Name: MPI_CNFG.H 34 * Title: MPI Config message, structures, and Pages 35 * Creation Date: July 27, 2000 36 * 37 * MPI_CNFG.H Version: 01.02.13 38 * 39 * Version History 40 * --------------- 41 * 42 * Date Version Description 43 * -------- -------- ------------------------------------------------------ 44 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 45 * 06-06-00 01.00.01 Update version number for 1.0 release. 46 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages. 47 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2 48 * fields to FC_DEVICE_0 page, updated the page version. 49 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in 50 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages 51 * and updated the page versions. 52 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1 53 * page and updated the page version. 54 * Added Information field and _INFO_PARAMS_NEGOTIATED 55 * definitionto SCSI_DEVICE_0 page. 56 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the 57 * page version. 58 * Added BucketsRemaining to LAN_1 page, redefined the 59 * state values, and updated the page version. 60 * Revised bus width definitions in SCSI_PORT_0, 61 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages. 62 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page 63 * version. 64 * Moved FC_DEVICE_0 PageAddress description to spec. 65 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field 66 * widths in IOC_0 page and updated the page version. 67 * 11-02-00 01.01.01 Original release for post 1.0 work 68 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI 69 * Port Page 2, FC Port Page 4, FC Port Page 5 70 * 11-15-00 01.01.02 Interim changes to match proposals 71 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01. 72 * 12-05-00 01.01.04 Modified config page actions. 73 * 01-09-01 01.01.05 Added defines for page address formats. 74 * Data size for Manufacturing pages 2 and 3 no longer 75 * defined here. 76 * Io Unit Page 2 size is fixed at 4 adapters and some 77 * flags were changed. 78 * SCSI Port Page 2 Device Settings modified. 79 * New fields added to FC Port Page 0 and some flags 80 * cleaned up. 81 * Removed impedance flash from FC Port Page 1. 82 * Added FC Port pages 6 and 7. 83 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0. 84 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique. 85 * Added some LinkType defines for FcPortPage0. 86 * 02-20-01 01.01.08 Started using MPI_POINTER. 87 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with 88 * MPI_CONFIG_PAGETYPE_RAID_VOLUME. 89 * Added definitions and structures for IOC Page 2 and 90 * RAID Volume Page 2. 91 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9. 92 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID. 93 * Added VendorId and ProductRevLevel fields to 94 * RAIDVOL2_IM_PHYS_ID struct. 95 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_ 96 * defines to make them compatible to MPI version 1.0. 97 * Added structure offset comments. 98 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and 99 * removed some obsolete ones. 100 * Added IO Unit Page 3. 101 * Modified defines for Scsi Port Page 2. 102 * Modified RAID Volume Pages. 103 * 08-08-01 01.02.01 Original release for v1.2 work. 104 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct. 105 * Added defines for the SEP bits in RVP2 VolumeSettings. 106 * Modified the DeviceSettings field in RVP2 to use the 107 * proper structure. 108 * Added defines for SES, SAF-TE, and cross channel for 109 * IOCPage2 CapabilitiesFlags. 110 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE. 111 * Removed define for 112 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE. 113 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT. 114 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035. 115 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY 116 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY. 117 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS, 118 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and 119 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and 120 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED. 121 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED 122 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED. 123 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1. 124 * Added rejected bits to SCSI Device Page 0 Information. 125 * Increased size of ALPA array in FC Port Page 2 by one 126 * and removed a one byte reserved field. 127 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in 128 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering. 129 * Added structures for Manufacturing Page 4, IO Unit 130 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and 131 * RAID PhysDisk Page 0. 132 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK. 133 * Modified some of the new defines to make them 32 134 * character unique. 135 * Modified how variable length pages (arrays) are defined. 136 * Added generic defines for hot spare pools and RAID 137 * volume types. 138 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR. 139 * 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with 140 * related define, and bumped the page version define. 141 * 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a 142 * reserved byte and added a define. 143 * Added define for 144 * MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE. 145 * Added new config page: CONFIG_PAGE_IOC_5. 146 * Added MaxAliases, MaxHardAliases, and NumCurrentAliases 147 * fields to CONFIG_PAGE_FC_PORT_0. 148 * Added AltConnector and NumRequestedAliases fields to 149 * CONFIG_PAGE_FC_PORT_1. 150 * Added new config page: CONFIG_PAGE_FC_PORT_10. 151 * 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines. 152 * Added additional MPI_SCSIDEVPAGE0_NP_ defines. 153 * Added more MPI_SCSIDEVPAGE1_RP_ defines. 154 * Added define for 155 * MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE. 156 * Added new config page: CONFIG_PAGE_SCSI_DEVICE_3. 157 * Modified MPI_FCPORTPAGE5_FLAGS_ defines. 158 * 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define. 159 * 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0. 160 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1. 161 * Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0. 162 * 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for 163 * CONFIG_PAGE_FC_PORT_1. 164 * Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable 165 * an alias. 166 * Added more device id defines. 167 * 06-26-03 01.02.12 Added MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID define. 168 * Added TargetConfig and IDConfig fields to 169 * CONFIG_PAGE_SCSI_PORT_1. 170 * Added more PortFlags defines for CONFIG_PAGE_SCSI_PORT_2 171 * to control DV. 172 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1. 173 * In CONFIG_PAGE_FC_DEVICE_0, replaced Reserved1 field 174 * with ADISCHardALPA. 175 * Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define. 176 * 01-16-04 01.02.13 Added InitiatorDeviceTimeout and InitiatorIoPendTimeout 177 * fields and related defines to CONFIG_PAGE_FC_PORT_1. 178 * Added define for 179 * MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK. 180 * Added new fields to the substructures of 181 * CONFIG_PAGE_FC_PORT_10. 182 * -------------------------------------------------------------------------- 183 */ 184 185 #ifndef MPI_CNFG_H 186 #define MPI_CNFG_H 187 188 189 /***************************************************************************** 190 * 191 * C o n f i g M e s s a g e a n d S t r u c t u r e s 192 * 193 *****************************************************************************/ 194 195 typedef struct _CONFIG_PAGE_HEADER 196 { 197 U8 PageVersion; /* 00h */ 198 U8 PageLength; /* 01h */ 199 U8 PageNumber; /* 02h */ 200 U8 PageType; /* 03h */ 201 } CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER, 202 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t; 203 204 typedef union _CONFIG_PAGE_HEADER_UNION 205 { 206 ConfigPageHeader_t Struct; 207 U8 Bytes[4]; 208 U16 Word16[2]; 209 U32 Word32; 210 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion, 211 CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION; 212 213 214 /**************************************************************************** 215 * PageType field values 216 ****************************************************************************/ 217 #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00) 218 #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10) 219 #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20) 220 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30) 221 #define MPI_CONFIG_PAGEATTR_MASK (0xF0) 222 223 #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00) 224 #define MPI_CONFIG_PAGETYPE_IOC (0x01) 225 #define MPI_CONFIG_PAGETYPE_BIOS (0x02) 226 #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03) 227 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04) 228 #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05) 229 #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06) 230 #define MPI_CONFIG_PAGETYPE_LAN (0x07) 231 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 232 #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09) 233 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 234 #define MPI_CONFIG_PAGETYPE_MASK (0x0F) 235 236 #define MPI_CONFIG_TYPENUM_MASK (0x0FFF) 237 238 239 /**************************************************************************** 240 * PageAddress field values 241 ****************************************************************************/ 242 #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF) 243 244 #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF) 245 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0) 246 #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00) 247 #define MPI_SCSI_DEVICE_BUS_SHIFT (8) 248 249 #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000) 250 #define MPI_FC_PORT_PGAD_PORT_SHIFT (28) 251 #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000) 252 #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000) 253 #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF) 254 #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0) 255 256 #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000) 257 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28) 258 #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000) 259 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000) 260 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000) 261 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28) 262 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF) 263 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0) 264 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000) 265 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 266 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8) 267 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 268 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0) 269 270 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 271 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0) 272 273 274 275 /**************************************************************************** 276 * Config Request Message 277 ****************************************************************************/ 278 typedef struct _MSG_CONFIG 279 { 280 U8 Action; /* 00h */ 281 U8 Reserved; /* 01h */ 282 U8 ChainOffset; /* 02h */ 283 U8 Function; /* 03h */ 284 U8 Reserved1[3]; /* 04h */ 285 U8 MsgFlags; /* 07h */ 286 U32 MsgContext; /* 08h */ 287 U8 Reserved2[8]; /* 0Ch */ 288 CONFIG_PAGE_HEADER Header; /* 14h */ 289 U32 PageAddress; /* 18h */ 290 SGE_IO_UNION PageBufferSGE; /* 1Ch */ 291 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG, 292 Config_t, MPI_POINTER pConfig_t; 293 294 295 /**************************************************************************** 296 * Action field values 297 ****************************************************************************/ 298 #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00) 299 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 300 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 301 #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03) 302 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 303 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 304 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 305 306 307 /* Config Reply Message */ 308 typedef struct _MSG_CONFIG_REPLY 309 { 310 U8 Action; /* 00h */ 311 U8 Reserved; /* 01h */ 312 U8 MsgLength; /* 02h */ 313 U8 Function; /* 03h */ 314 U8 Reserved1[3]; /* 04h */ 315 U8 MsgFlags; /* 07h */ 316 U32 MsgContext; /* 08h */ 317 U8 Reserved2[2]; /* 0Ch */ 318 U16 IOCStatus; /* 0Eh */ 319 U32 IOCLogInfo; /* 10h */ 320 CONFIG_PAGE_HEADER Header; /* 14h */ 321 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY, 322 ConfigReply_t, MPI_POINTER pConfigReply_t; 323 324 325 326 /***************************************************************************** 327 * 328 * C o n f i g u r a t i o n P a g e s 329 * 330 *****************************************************************************/ 331 332 /**************************************************************************** 333 * Manufacturing Config pages 334 ****************************************************************************/ 335 #define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000) 336 #define MPI_MANUFACTPAGE_VENDORID_TREBIA (0x1783) 337 338 #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621) 339 #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624) 340 #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622) 341 #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628) 342 #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626) 343 344 #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030) 345 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031) 346 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032) 347 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033) 348 #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040) 349 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041) 350 351 #define MPI_MANUFACTPAGE_DEVID_SA2010 (0x0804) 352 #define MPI_MANUFACTPAGE_DEVID_SA2010ZC (0x0805) 353 #define MPI_MANUFACTPAGE_DEVID_SA2020 (0x0806) 354 #define MPI_MANUFACTPAGE_DEVID_SA2020ZC (0x0807) 355 356 #define MPI_MANUFACTPAGE_DEVID_SNP1000 (0x0010) 357 #define MPI_MANUFACTPAGE_DEVID_SNP500 (0x0020) 358 359 360 361 typedef struct _CONFIG_PAGE_MANUFACTURING_0 362 { 363 CONFIG_PAGE_HEADER Header; /* 00h */ 364 U8 ChipName[16]; /* 04h */ 365 U8 ChipRevision[8]; /* 14h */ 366 U8 BoardName[16]; /* 1Ch */ 367 U8 BoardAssembly[16]; /* 2Ch */ 368 U8 BoardTracerNumber[16]; /* 3Ch */ 369 370 } CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0, 371 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t; 372 373 #define MPI_MANUFACTURING0_PAGEVERSION (0x00) 374 375 376 typedef struct _CONFIG_PAGE_MANUFACTURING_1 377 { 378 CONFIG_PAGE_HEADER Header; /* 00h */ 379 U8 VPD[256]; /* 04h */ 380 } CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1, 381 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t; 382 383 #define MPI_MANUFACTURING1_PAGEVERSION (0x00) 384 385 386 typedef struct _MPI_CHIP_REVISION_ID 387 { 388 U16 DeviceID; /* 00h */ 389 U8 PCIRevisionID; /* 02h */ 390 U8 Reserved; /* 03h */ 391 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID, 392 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t; 393 394 395 /* 396 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 397 * one and check Header.PageLength at runtime. 398 */ 399 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS 400 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 401 #endif 402 403 typedef struct _CONFIG_PAGE_MANUFACTURING_2 404 { 405 CONFIG_PAGE_HEADER Header; /* 00h */ 406 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 407 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */ 408 } CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2, 409 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t; 410 411 #define MPI_MANUFACTURING2_PAGEVERSION (0x00) 412 413 414 /* 415 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 416 * one and check Header.PageLength at runtime. 417 */ 418 #ifndef MPI_MAN_PAGE_3_INFO_WORDS 419 #define MPI_MAN_PAGE_3_INFO_WORDS (1) 420 #endif 421 422 typedef struct _CONFIG_PAGE_MANUFACTURING_3 423 { 424 CONFIG_PAGE_HEADER Header; /* 00h */ 425 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 426 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */ 427 } CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3, 428 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t; 429 430 #define MPI_MANUFACTURING3_PAGEVERSION (0x00) 431 432 433 typedef struct _CONFIG_PAGE_MANUFACTURING_4 434 { 435 CONFIG_PAGE_HEADER Header; /* 00h */ 436 U32 Reserved1; /* 04h */ 437 U8 InfoOffset0; /* 08h */ 438 U8 InfoSize0; /* 09h */ 439 U8 InfoOffset1; /* 0Ah */ 440 U8 InfoSize1; /* 0Bh */ 441 U8 InquirySize; /* 0Ch */ 442 U8 Reserved2; /* 0Dh */ 443 U16 Reserved3; /* 0Eh */ 444 U8 InquiryData[56]; /* 10h */ 445 U32 ISVolumeSettings; /* 48h */ 446 U32 IMEVolumeSettings; /* 4Ch */ 447 U32 IMVolumeSettings; /* 50h */ 448 } CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4, 449 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t; 450 451 #define MPI_MANUFACTURING4_PAGEVERSION (0x00) 452 453 454 /**************************************************************************** 455 * IO Unit Config Pages 456 ****************************************************************************/ 457 458 typedef struct _CONFIG_PAGE_IO_UNIT_0 459 { 460 CONFIG_PAGE_HEADER Header; /* 00h */ 461 U64 UniqueValue; /* 04h */ 462 } CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0, 463 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t; 464 465 #define MPI_IOUNITPAGE0_PAGEVERSION (0x00) 466 467 468 typedef struct _CONFIG_PAGE_IO_UNIT_1 469 { 470 CONFIG_PAGE_HEADER Header; /* 00h */ 471 U32 Flags; /* 04h */ 472 } CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1, 473 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t; 474 475 #define MPI_IOUNITPAGE1_PAGEVERSION (0x00) 476 477 /* IO Unit Page 1 Flags defines */ 478 479 #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000) 480 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001) 481 #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002) 482 #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000) 483 #define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 484 #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040) 485 #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080) 486 487 488 typedef struct _MPI_ADAPTER_INFO 489 { 490 U8 PciBusNumber; /* 00h */ 491 U8 PciDeviceAndFunctionNumber; /* 01h */ 492 U16 AdapterFlags; /* 02h */ 493 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO, 494 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t; 495 496 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 497 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 498 499 typedef struct _CONFIG_PAGE_IO_UNIT_2 500 { 501 CONFIG_PAGE_HEADER Header; /* 00h */ 502 U32 Flags; /* 04h */ 503 U32 BiosVersion; /* 08h */ 504 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */ 505 } CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2, 506 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t; 507 508 #define MPI_IOUNITPAGE2_PAGEVERSION (0x00) 509 510 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002) 511 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004) 512 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008) 513 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010) 514 515 516 /* 517 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 518 * one and check Header.PageLength at runtime. 519 */ 520 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX 521 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 522 #endif 523 524 typedef struct _CONFIG_PAGE_IO_UNIT_3 525 { 526 CONFIG_PAGE_HEADER Header; /* 00h */ 527 U8 GPIOCount; /* 04h */ 528 U8 Reserved1; /* 05h */ 529 U16 Reserved2; /* 06h */ 530 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */ 531 } CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3, 532 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t; 533 534 #define MPI_IOUNITPAGE3_PAGEVERSION (0x01) 535 536 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC) 537 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 538 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00) 539 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01) 540 541 542 /**************************************************************************** 543 * IOC Config Pages 544 ****************************************************************************/ 545 546 typedef struct _CONFIG_PAGE_IOC_0 547 { 548 CONFIG_PAGE_HEADER Header; /* 00h */ 549 U32 TotalNVStore; /* 04h */ 550 U32 FreeNVStore; /* 08h */ 551 U16 VendorID; /* 0Ch */ 552 U16 DeviceID; /* 0Eh */ 553 U8 RevisionID; /* 10h */ 554 U8 Reserved[3]; /* 11h */ 555 U32 ClassCode; /* 14h */ 556 U16 SubsystemVendorID; /* 18h */ 557 U16 SubsystemID; /* 1Ah */ 558 } CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0, 559 IOCPage0_t, MPI_POINTER pIOCPage0_t; 560 561 #define MPI_IOCPAGE0_PAGEVERSION (0x01) 562 563 564 typedef struct _CONFIG_PAGE_IOC_1 565 { 566 CONFIG_PAGE_HEADER Header; /* 00h */ 567 U32 Flags; /* 04h */ 568 U32 CoalescingTimeout; /* 08h */ 569 U8 CoalescingDepth; /* 0Ch */ 570 U8 PCISlotNum; /* 0Dh */ 571 U8 Reserved[2]; /* 0Eh */ 572 } CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1, 573 IOCPage1_t, MPI_POINTER pIOCPage1_t; 574 575 #define MPI_IOCPAGE1_PAGEVERSION (0x01) 576 577 #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001) 578 579 #define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 580 581 582 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL 583 { 584 U8 VolumeID; /* 00h */ 585 U8 VolumeBus; /* 01h */ 586 U8 VolumeIOC; /* 02h */ 587 U8 VolumePageNumber; /* 03h */ 588 U8 VolumeType; /* 04h */ 589 U8 Flags; /* 05h */ 590 U16 Reserved3; /* 06h */ 591 } CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL, 592 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t; 593 594 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */ 595 596 #define MPI_RAID_VOL_TYPE_IS (0x00) 597 #define MPI_RAID_VOL_TYPE_IME (0x01) 598 #define MPI_RAID_VOL_TYPE_IM (0x02) 599 600 /* IOC Page 2 Volume Flags values */ 601 602 #define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08) 603 604 /* 605 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 606 * one and check Header.PageLength at runtime. 607 */ 608 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX 609 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1) 610 #endif 611 612 typedef struct _CONFIG_PAGE_IOC_2 613 { 614 CONFIG_PAGE_HEADER Header; /* 00h */ 615 U32 CapabilitiesFlags; /* 04h */ 616 U8 NumActiveVolumes; /* 08h */ 617 U8 MaxVolumes; /* 09h */ 618 U8 NumActivePhysDisks; /* 0Ah */ 619 U8 MaxPhysDisks; /* 0Bh */ 620 CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */ 621 } CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2, 622 IOCPage2_t, MPI_POINTER pIOCPage2_t; 623 624 #define MPI_IOCPAGE2_PAGEVERSION (0x02) 625 626 /* IOC Page 2 Capabilities flags */ 627 628 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001) 629 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002) 630 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004) 631 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000) 632 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000) 633 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000) 634 635 636 typedef struct _IOC_3_PHYS_DISK 637 { 638 U8 PhysDiskID; /* 00h */ 639 U8 PhysDiskBus; /* 01h */ 640 U8 PhysDiskIOC; /* 02h */ 641 U8 PhysDiskNum; /* 03h */ 642 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK, 643 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t; 644 645 /* 646 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 647 * one and check Header.PageLength at runtime. 648 */ 649 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX 650 #define MPI_IOC_PAGE_3_PHYSDISK_MAX (1) 651 #endif 652 653 typedef struct _CONFIG_PAGE_IOC_3 654 { 655 CONFIG_PAGE_HEADER Header; /* 00h */ 656 U8 NumPhysDisks; /* 04h */ 657 U8 Reserved1; /* 05h */ 658 U16 Reserved2; /* 06h */ 659 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */ 660 } CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3, 661 IOCPage3_t, MPI_POINTER pIOCPage3_t; 662 663 #define MPI_IOCPAGE3_PAGEVERSION (0x00) 664 665 666 typedef struct _IOC_4_SEP 667 { 668 U8 SEPTargetID; /* 00h */ 669 U8 SEPBus; /* 01h */ 670 U16 Reserved; /* 02h */ 671 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP, 672 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t; 673 674 /* 675 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 676 * one and check Header.PageLength at runtime. 677 */ 678 #ifndef MPI_IOC_PAGE_4_SEP_MAX 679 #define MPI_IOC_PAGE_4_SEP_MAX (1) 680 #endif 681 682 typedef struct _CONFIG_PAGE_IOC_4 683 { 684 CONFIG_PAGE_HEADER Header; /* 00h */ 685 U8 ActiveSEP; /* 04h */ 686 U8 MaxSEP; /* 05h */ 687 U16 Reserved1; /* 06h */ 688 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */ 689 } CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4, 690 IOCPage4_t, MPI_POINTER pIOCPage4_t; 691 692 #define MPI_IOCPAGE4_PAGEVERSION (0x00) 693 694 695 typedef struct _IOC_5_HOT_SPARE 696 { 697 U8 PhysDiskNum; /* 00h */ 698 U8 Reserved; /* 01h */ 699 U8 HotSparePool; /* 02h */ 700 U8 Flags; /* 03h */ 701 } IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE, 702 Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t; 703 704 /* IOC Page 5 HotSpare Flags */ 705 #define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01) 706 707 /* 708 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 709 * one and check Header.PageLength at runtime. 710 */ 711 #ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX 712 #define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1) 713 #endif 714 715 typedef struct _CONFIG_PAGE_IOC_5 716 { 717 CONFIG_PAGE_HEADER Header; /* 00h */ 718 U32 Reserved1; /* 04h */ 719 U8 NumHotSpares; /* 08h */ 720 U8 Reserved2; /* 09h */ 721 U16 Reserved3; /* 0Ah */ 722 IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */ 723 } CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5, 724 IOCPage5_t, MPI_POINTER pIOCPage5_t; 725 726 #define MPI_IOCPAGE5_PAGEVERSION (0x00) 727 728 729 730 /**************************************************************************** 731 * SCSI Port Config Pages 732 ****************************************************************************/ 733 734 typedef struct _CONFIG_PAGE_SCSI_PORT_0 735 { 736 CONFIG_PAGE_HEADER Header; /* 00h */ 737 U32 Capabilities; /* 04h */ 738 U32 PhysicalInterface; /* 08h */ 739 } CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0, 740 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t; 741 742 #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x01) 743 744 #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001) 745 #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002) 746 #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004) 747 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 748 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 749 #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000) 750 #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000) 751 752 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003) 753 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01) 754 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02) 755 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03) 756 #define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000) 757 #define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24) 758 #define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE) 759 #define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF) 760 761 762 typedef struct _CONFIG_PAGE_SCSI_PORT_1 763 { 764 CONFIG_PAGE_HEADER Header; /* 00h */ 765 U32 Configuration; /* 04h */ 766 U32 OnBusTimerValue; /* 08h */ 767 U8 TargetConfig; /* 0Ch */ 768 U8 Reserved1; /* 0Dh */ 769 U16 IDConfig; /* 0Eh */ 770 } CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1, 771 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t; 772 773 #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03) 774 775 /* Configuration values */ 776 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF) 777 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000) 778 779 /* TargetConfig values */ 780 #define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01) 781 #define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG (0x02) 782 783 784 typedef struct _MPI_DEVICE_INFO 785 { 786 U8 Timeout; /* 00h */ 787 U8 SyncFactor; /* 01h */ 788 U16 DeviceFlags; /* 02h */ 789 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO, 790 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t; 791 792 typedef struct _CONFIG_PAGE_SCSI_PORT_2 793 { 794 CONFIG_PAGE_HEADER Header; /* 00h */ 795 U32 PortFlags; /* 04h */ 796 U32 PortSettings; /* 08h */ 797 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */ 798 } CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2, 799 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t; 800 801 #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x02) 802 803 /* PortFlags values */ 804 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001) 805 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004) 806 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 807 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010) 808 809 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK (0x00000060) 810 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV (0x00000000) 811 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020) 812 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060) 813 814 /* PortSettings values */ 815 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F) 816 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030) 817 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000) 818 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010) 819 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020) 820 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030) 821 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0) 822 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00) 823 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000) 824 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000) 825 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000) 826 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000) 827 828 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001) 829 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002) 830 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004) 831 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008) 832 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010) 833 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020) 834 835 836 /**************************************************************************** 837 * SCSI Target Device Config Pages 838 ****************************************************************************/ 839 840 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0 841 { 842 CONFIG_PAGE_HEADER Header; /* 00h */ 843 U32 NegotiatedParameters; /* 04h */ 844 U32 Information; /* 08h */ 845 } CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0, 846 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t; 847 848 #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x03) 849 850 #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001) 851 #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002) 852 #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004) 853 #define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008) 854 #define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010) 855 #define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020) 856 #define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040) 857 #define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080) 858 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00) 859 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000) 860 #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000) 861 #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000) 862 863 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001) 864 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002) 865 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004) 866 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008) 867 868 869 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1 870 { 871 CONFIG_PAGE_HEADER Header; /* 00h */ 872 U32 RequestedParameters; /* 04h */ 873 U32 Reserved; /* 08h */ 874 U32 Configuration; /* 0Ch */ 875 } CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1, 876 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t; 877 878 #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x04) 879 880 #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001) 881 #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002) 882 #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004) 883 #define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008) 884 #define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010) 885 #define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020) 886 #define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040) 887 #define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080) 888 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 889 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 890 #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000) 891 #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000) 892 893 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002) 894 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004) 895 #define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008) 896 #define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010) 897 898 899 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2 900 { 901 CONFIG_PAGE_HEADER Header; /* 00h */ 902 U32 DomainValidation; /* 04h */ 903 U32 ParityPipeSelect; /* 08h */ 904 U32 DataPipeSelect; /* 0Ch */ 905 } CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2, 906 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t; 907 908 #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01) 909 910 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010) 911 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020) 912 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380) 913 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00) 914 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000) 915 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000) 916 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000) 917 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000) 918 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000) 919 920 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003) 921 922 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003) 923 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C) 924 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030) 925 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0) 926 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300) 927 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00) 928 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000) 929 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000) 930 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000) 931 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000) 932 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000) 933 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000) 934 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000) 935 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000) 936 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000) 937 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000) 938 939 940 typedef struct _CONFIG_PAGE_SCSI_DEVICE_3 941 { 942 CONFIG_PAGE_HEADER Header; /* 00h */ 943 U16 MsgRejectCount; /* 04h */ 944 U16 PhaseErrorCount; /* 06h */ 945 U16 ParityErrorCount; /* 08h */ 946 U16 Reserved; /* 0Ah */ 947 } CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3, 948 SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t; 949 950 #define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00) 951 952 #define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE) 953 #define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF) 954 955 956 /**************************************************************************** 957 * FC Port Config Pages 958 ****************************************************************************/ 959 960 typedef struct _CONFIG_PAGE_FC_PORT_0 961 { 962 CONFIG_PAGE_HEADER Header; /* 00h */ 963 U32 Flags; /* 04h */ 964 U8 MPIPortNumber; /* 08h */ 965 U8 LinkType; /* 09h */ 966 U8 PortState; /* 0Ah */ 967 U8 Reserved; /* 0Bh */ 968 U32 PortIdentifier; /* 0Ch */ 969 U64 WWNN; /* 10h */ 970 U64 WWPN; /* 18h */ 971 U32 SupportedServiceClass; /* 20h */ 972 U32 SupportedSpeeds; /* 24h */ 973 U32 CurrentSpeed; /* 28h */ 974 U32 MaxFrameSize; /* 2Ch */ 975 U64 FabricWWNN; /* 30h */ 976 U64 FabricWWPN; /* 38h */ 977 U32 DiscoveredPortsCount; /* 40h */ 978 U32 MaxInitiators; /* 44h */ 979 U8 MaxAliasesSupported; /* 48h */ 980 U8 MaxHardAliasesSupported; /* 49h */ 981 U8 NumCurrentAliases; /* 4Ah */ 982 U8 Reserved1; /* 4Bh */ 983 } CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0, 984 FCPortPage0_t, MPI_POINTER pFCPortPage0_t; 985 986 #define MPI_FCPORTPAGE0_PAGEVERSION (0x02) 987 988 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F) 989 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR) 990 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET) 991 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN) 992 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR) 993 994 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010) 995 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020) 996 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040) 997 998 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00) 999 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000) 1000 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100) 1001 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200) 1002 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400) 1003 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800) 1004 1005 #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00) 1006 #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01) 1007 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02) 1008 #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03) 1009 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04) 1010 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05) 1011 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06) 1012 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07) 1013 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08) 1014 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09) 1015 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A) 1016 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B) 1017 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C) 1018 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D) 1019 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E) 1020 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F) 1021 1022 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */ 1023 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */ 1024 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */ 1025 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */ 1026 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */ 1027 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */ 1028 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */ 1029 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */ 1030 1031 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001) 1032 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002) 1033 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004) 1034 1035 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */ 1036 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */ 1037 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */ 1038 1039 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED 1040 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED 1041 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED 1042 1043 1044 typedef struct _CONFIG_PAGE_FC_PORT_1 1045 { 1046 CONFIG_PAGE_HEADER Header; /* 00h */ 1047 U32 Flags; /* 04h */ 1048 U64 NoSEEPROMWWNN; /* 08h */ 1049 U64 NoSEEPROMWWPN; /* 10h */ 1050 U8 HardALPA; /* 18h */ 1051 U8 LinkConfig; /* 19h */ 1052 U8 TopologyConfig; /* 1Ah */ 1053 U8 AltConnector; /* 1Bh */ 1054 U8 NumRequestedAliases; /* 1Ch */ 1055 U8 RR_TOV; /* 1Dh */ 1056 U8 InitiatorDeviceTimeout; /* 1Eh */ 1057 U8 InitiatorIoPendTimeout; /* 1Fh */ 1058 } CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1, 1059 FCPortPage1_t, MPI_POINTER pFCPortPage1_t; 1060 1061 #define MPI_FCPORTPAGE1_PAGEVERSION (0x06) 1062 1063 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000) 1064 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000) 1065 #define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000) 1066 #define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000) 1067 #define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000) 1068 #define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE (0x00400000) 1069 #define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK (0x00200000) 1070 #define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070) 1071 #define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG (0x00000008) 1072 #define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO (0x00000004) 1073 #define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002) 1074 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001) 1075 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000) 1076 1077 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000) 1078 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28) 1079 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1080 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1081 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1082 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1083 1084 #define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000) 1085 #define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010) 1086 #define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030) 1087 #define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050) 1088 1089 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF) 1090 1091 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F) 1092 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00) 1093 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01) 1094 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02) 1095 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03) 1096 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F) 1097 1098 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F) 1099 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01) 1100 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02) 1101 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F) 1102 1103 #define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00) 1104 1105 #define MPI_FCPORTPAGE1_INITIATOR_DEV_TIMEOUT_MASK (0x7F) 1106 #define MPI_FCPORTPAGE1_INITIATOR_DEV_UNIT_16 (0x80) 1107 1108 1109 typedef struct _CONFIG_PAGE_FC_PORT_2 1110 { 1111 CONFIG_PAGE_HEADER Header; /* 00h */ 1112 U8 NumberActive; /* 04h */ 1113 U8 ALPA[127]; /* 05h */ 1114 } CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2, 1115 FCPortPage2_t, MPI_POINTER pFCPortPage2_t; 1116 1117 #define MPI_FCPORTPAGE2_PAGEVERSION (0x01) 1118 1119 1120 typedef struct _WWN_FORMAT 1121 { 1122 U64 WWNN; /* 00h */ 1123 U64 WWPN; /* 08h */ 1124 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT, 1125 WWNFormat, MPI_POINTER pWWNFormat; 1126 1127 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID 1128 { 1129 WWN_FORMAT WWN; 1130 U32 Did; 1131 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID, 1132 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t; 1133 1134 typedef struct _FC_PORT_PERSISTENT 1135 { 1136 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */ 1137 U8 TargetID; /* 10h */ 1138 U8 Bus; /* 11h */ 1139 U16 Flags; /* 12h */ 1140 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT, 1141 PersistentData_t, MPI_POINTER pPersistentData_t; 1142 1143 #define MPI_PERSISTENT_FLAGS_SHIFT (16) 1144 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001) 1145 #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002) 1146 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004) 1147 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008) 1148 #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080) 1149 1150 /* 1151 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1152 * one and check Header.PageLength at runtime. 1153 */ 1154 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX 1155 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1) 1156 #endif 1157 1158 typedef struct _CONFIG_PAGE_FC_PORT_3 1159 { 1160 CONFIG_PAGE_HEADER Header; /* 00h */ 1161 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */ 1162 } CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3, 1163 FCPortPage3_t, MPI_POINTER pFCPortPage3_t; 1164 1165 #define MPI_FCPORTPAGE3_PAGEVERSION (0x01) 1166 1167 1168 typedef struct _CONFIG_PAGE_FC_PORT_4 1169 { 1170 CONFIG_PAGE_HEADER Header; /* 00h */ 1171 U32 PortFlags; /* 04h */ 1172 U32 PortSettings; /* 08h */ 1173 } CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4, 1174 FCPortPage4_t, MPI_POINTER pFCPortPage4_t; 1175 1176 #define MPI_FCPORTPAGE4_PAGEVERSION (0x00) 1177 1178 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1179 1180 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030) 1181 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000) 1182 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010) 1183 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020) 1184 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030) 1185 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0) 1186 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00) 1187 1188 1189 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO 1190 { 1191 U8 Flags; /* 00h */ 1192 U8 AliasAlpa; /* 01h */ 1193 U16 Reserved; /* 02h */ 1194 U64 AliasWWNN; /* 04h */ 1195 U64 AliasWWPN; /* 0Ch */ 1196 } CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1197 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1198 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t; 1199 1200 typedef struct _CONFIG_PAGE_FC_PORT_5 1201 { 1202 CONFIG_PAGE_HEADER Header; /* 00h */ 1203 CONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */ 1204 } CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5, 1205 FCPortPage5_t, MPI_POINTER pFCPortPage5_t; 1206 1207 #define MPI_FCPORTPAGE5_PAGEVERSION (0x02) 1208 1209 #define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01) 1210 #define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02) 1211 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04) 1212 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08) 1213 #define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10) 1214 1215 typedef struct _CONFIG_PAGE_FC_PORT_6 1216 { 1217 CONFIG_PAGE_HEADER Header; /* 00h */ 1218 U32 Reserved; /* 04h */ 1219 U64 TimeSinceReset; /* 08h */ 1220 U64 TxFrames; /* 10h */ 1221 U64 RxFrames; /* 18h */ 1222 U64 TxWords; /* 20h */ 1223 U64 RxWords; /* 28h */ 1224 U64 LipCount; /* 30h */ 1225 U64 NosCount; /* 38h */ 1226 U64 ErrorFrames; /* 40h */ 1227 U64 DumpedFrames; /* 48h */ 1228 U64 LinkFailureCount; /* 50h */ 1229 U64 LossOfSyncCount; /* 58h */ 1230 U64 LossOfSignalCount; /* 60h */ 1231 U64 PrimativeSeqErrCount; /* 68h */ 1232 U64 InvalidTxWordCount; /* 70h */ 1233 U64 InvalidCrcCount; /* 78h */ 1234 U64 FcpInitiatorIoCount; /* 80h */ 1235 } CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6, 1236 FCPortPage6_t, MPI_POINTER pFCPortPage6_t; 1237 1238 #define MPI_FCPORTPAGE6_PAGEVERSION (0x00) 1239 1240 1241 typedef struct _CONFIG_PAGE_FC_PORT_7 1242 { 1243 CONFIG_PAGE_HEADER Header; /* 00h */ 1244 U32 Reserved; /* 04h */ 1245 U8 PortSymbolicName[256]; /* 08h */ 1246 } CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7, 1247 FCPortPage7_t, MPI_POINTER pFCPortPage7_t; 1248 1249 #define MPI_FCPORTPAGE7_PAGEVERSION (0x00) 1250 1251 1252 typedef struct _CONFIG_PAGE_FC_PORT_8 1253 { 1254 CONFIG_PAGE_HEADER Header; /* 00h */ 1255 U32 BitVector[8]; /* 04h */ 1256 } CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8, 1257 FCPortPage8_t, MPI_POINTER pFCPortPage8_t; 1258 1259 #define MPI_FCPORTPAGE8_PAGEVERSION (0x00) 1260 1261 1262 typedef struct _CONFIG_PAGE_FC_PORT_9 1263 { 1264 CONFIG_PAGE_HEADER Header; /* 00h */ 1265 U32 Reserved; /* 04h */ 1266 U64 GlobalWWPN; /* 08h */ 1267 U64 GlobalWWNN; /* 10h */ 1268 U32 UnitType; /* 18h */ 1269 U32 PhysicalPortNumber; /* 1Ch */ 1270 U32 NumAttachedNodes; /* 20h */ 1271 U16 IPVersion; /* 24h */ 1272 U16 UDPPortNumber; /* 26h */ 1273 U8 IPAddress[16]; /* 28h */ 1274 U16 Reserved1; /* 38h */ 1275 U16 TopologyDiscoveryFlags; /* 3Ah */ 1276 } CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9, 1277 FCPortPage9_t, MPI_POINTER pFCPortPage9_t; 1278 1279 #define MPI_FCPORTPAGE9_PAGEVERSION (0x00) 1280 1281 1282 typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA 1283 { 1284 U8 Id; /* 10h */ 1285 U8 ExtId; /* 11h */ 1286 U8 Connector; /* 12h */ 1287 U8 Transceiver[8]; /* 13h */ 1288 U8 Encoding; /* 1Bh */ 1289 U8 BitRate_100mbs; /* 1Ch */ 1290 U8 Reserved1; /* 1Dh */ 1291 U8 Length9u_km; /* 1Eh */ 1292 U8 Length9u_100m; /* 1Fh */ 1293 U8 Length50u_10m; /* 20h */ 1294 U8 Length62p5u_10m; /* 21h */ 1295 U8 LengthCopper_m; /* 22h */ 1296 U8 Reseverved2; /* 22h */ 1297 U8 VendorName[16]; /* 24h */ 1298 U8 Reserved3; /* 34h */ 1299 U8 VendorOUI[3]; /* 35h */ 1300 U8 VendorPN[16]; /* 38h */ 1301 U8 VendorRev[4]; /* 48h */ 1302 U16 Wavelength; /* 4Ch */ 1303 U8 Reserved4; /* 4Eh */ 1304 U8 CC_BASE; /* 4Fh */ 1305 } CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA, 1306 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA, 1307 FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t; 1308 1309 #define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00) 1310 #define MPI_FCPORT10_BASE_ID_GBIC (0x01) 1311 #define MPI_FCPORT10_BASE_ID_FIXED (0x02) 1312 #define MPI_FCPORT10_BASE_ID_SFP (0x03) 1313 #define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04) 1314 #define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F) 1315 #define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80) 1316 1317 #define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00) 1318 #define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01) 1319 #define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02) 1320 #define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03) 1321 #define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04) 1322 #define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05) 1323 #define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06) 1324 #define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07) 1325 #define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80) 1326 1327 #define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00) 1328 #define MPI_FCPORT10_BASE_CONN_SC (0x01) 1329 #define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02) 1330 #define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03) 1331 #define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04) 1332 #define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05) 1333 #define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06) 1334 #define MPI_FCPORT10_BASE_CONN_LC (0x07) 1335 #define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08) 1336 #define MPI_FCPORT10_BASE_CONN_MU (0x09) 1337 #define MPI_FCPORT10_BASE_CONN_SG (0x0A) 1338 #define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B) 1339 #define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C) 1340 #define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F) 1341 #define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20) 1342 #define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21) 1343 #define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22) 1344 #define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F) 1345 #define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80) 1346 1347 #define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00) 1348 #define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01) 1349 #define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02) 1350 #define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03) 1351 #define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04) 1352 1353 1354 typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA 1355 { 1356 U8 Options[2]; /* 50h */ 1357 U8 BitRateMax; /* 52h */ 1358 U8 BitRateMin; /* 53h */ 1359 U8 VendorSN[16]; /* 54h */ 1360 U8 DateCode[8]; /* 64h */ 1361 U8 DiagMonitoringType; /* 6Ch */ 1362 U8 EnhancedOptions; /* 6Dh */ 1363 U8 SFF8472Compliance; /* 6Eh */ 1364 U8 CC_EXT; /* 6Fh */ 1365 } CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA, 1366 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA, 1367 FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t; 1368 1369 #define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20) 1370 #define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10) 1371 #define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08) 1372 #define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04) 1373 #define MPI_FCPORT10_EXT_OPTION1_LOS (0x02) 1374 1375 1376 typedef struct _CONFIG_PAGE_FC_PORT_10 1377 { 1378 CONFIG_PAGE_HEADER Header; /* 00h */ 1379 U8 Flags; /* 04h */ 1380 U8 Reserved1; /* 05h */ 1381 U16 Reserved2; /* 06h */ 1382 U32 HwConfig1; /* 08h */ 1383 U32 HwConfig2; /* 0Ch */ 1384 CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */ 1385 CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */ 1386 U8 VendorSpecific[32]; /* 70h */ 1387 } CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10, 1388 FCPortPage10_t, MPI_POINTER pFCPortPage10_t; 1389 1390 #define MPI_FCPORTPAGE10_PAGEVERSION (0x01) 1391 1392 /* standard MODDEF pin definitions (from GBIC spec.) */ 1393 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007) 1394 #define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001) 1395 #define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002) 1396 #define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004) 1397 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007) 1398 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006) 1399 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005) 1400 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004) 1401 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003) 1402 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002) 1403 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001) 1404 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000) 1405 1406 #define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010) 1407 #define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020) 1408 1409 1410 /**************************************************************************** 1411 * FC Device Config Pages 1412 ****************************************************************************/ 1413 1414 typedef struct _CONFIG_PAGE_FC_DEVICE_0 1415 { 1416 CONFIG_PAGE_HEADER Header; /* 00h */ 1417 U64 WWNN; /* 04h */ 1418 U64 WWPN; /* 0Ch */ 1419 U32 PortIdentifier; /* 14h */ 1420 U8 Protocol; /* 18h */ 1421 U8 Flags; /* 19h */ 1422 U16 BBCredit; /* 1Ah */ 1423 U16 MaxRxFrameSize; /* 1Ch */ 1424 U8 ADISCHardALPA; /* 1Eh */ 1425 U8 PortNumber; /* 1Fh */ 1426 U8 FcPhLowestVersion; /* 20h */ 1427 U8 FcPhHighestVersion; /* 21h */ 1428 U8 CurrentTargetID; /* 22h */ 1429 U8 CurrentBus; /* 23h */ 1430 } CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0, 1431 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t; 1432 1433 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x03) 1434 1435 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01) 1436 #define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02) 1437 #define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04) 1438 1439 #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01) 1440 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02) 1441 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04) 1442 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY (0x08) 1443 1444 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK) 1445 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK) 1446 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) 1447 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID) 1448 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK) 1449 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK) 1450 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT) 1451 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK) 1452 1453 #define MPI_FC_DEVICE_PAGE0_HARD_ALPA_UNKNOWN (0xFF) 1454 1455 /**************************************************************************** 1456 * RAID Volume Config Pages 1457 ****************************************************************************/ 1458 1459 typedef struct _RAID_VOL0_PHYS_DISK 1460 { 1461 U16 Reserved; /* 00h */ 1462 U8 PhysDiskMap; /* 02h */ 1463 U8 PhysDiskNum; /* 03h */ 1464 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK, 1465 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t; 1466 1467 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1468 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1469 1470 typedef struct _RAID_VOL0_STATUS 1471 { 1472 U8 Flags; /* 00h */ 1473 U8 State; /* 01h */ 1474 U16 Reserved; /* 02h */ 1475 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS, 1476 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t; 1477 1478 /* RAID Volume Page 0 VolumeStatus defines */ 1479 1480 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01) 1481 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02) 1482 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04) 1483 #define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08) 1484 1485 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00) 1486 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01) 1487 #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02) 1488 1489 typedef struct _RAID_VOL0_SETTINGS 1490 { 1491 U16 Settings; /* 00h */ 1492 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 1493 U8 Reserved; /* 02h */ 1494 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS, 1495 RaidVol0Settings, MPI_POINTER pRaidVol0Settings; 1496 1497 /* RAID Volume Page 0 VolumeSettings defines */ 1498 1499 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001) 1500 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002) 1501 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004) 1502 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008) 1503 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010) 1504 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000) 1505 1506 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1507 #define MPI_RAID_HOT_SPARE_POOL_0 (0x01) 1508 #define MPI_RAID_HOT_SPARE_POOL_1 (0x02) 1509 #define MPI_RAID_HOT_SPARE_POOL_2 (0x04) 1510 #define MPI_RAID_HOT_SPARE_POOL_3 (0x08) 1511 #define MPI_RAID_HOT_SPARE_POOL_4 (0x10) 1512 #define MPI_RAID_HOT_SPARE_POOL_5 (0x20) 1513 #define MPI_RAID_HOT_SPARE_POOL_6 (0x40) 1514 #define MPI_RAID_HOT_SPARE_POOL_7 (0x80) 1515 1516 /* 1517 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1518 * one and check Header.PageLength at runtime. 1519 */ 1520 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX 1521 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1522 #endif 1523 1524 typedef struct _CONFIG_PAGE_RAID_VOL_0 1525 { 1526 CONFIG_PAGE_HEADER Header; /* 00h */ 1527 U8 VolumeID; /* 04h */ 1528 U8 VolumeBus; /* 05h */ 1529 U8 VolumeIOC; /* 06h */ 1530 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */ 1531 RAID_VOL0_STATUS VolumeStatus; /* 08h */ 1532 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */ 1533 U32 MaxLBA; /* 10h */ 1534 U32 Reserved1; /* 14h */ 1535 U32 StripeSize; /* 18h */ 1536 U32 Reserved2; /* 1Ch */ 1537 U32 Reserved3; /* 20h */ 1538 U8 NumPhysDisks; /* 24h */ 1539 U8 DataScrubRate; /* 25h */ 1540 U8 ResyncRate; /* 26h */ 1541 U8 InactiveStatus; /* 27h */ 1542 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */ 1543 } CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0, 1544 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t; 1545 1546 #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x01) 1547 1548 1549 /**************************************************************************** 1550 * RAID Physical Disk Config Pages 1551 ****************************************************************************/ 1552 1553 typedef struct _RAID_PHYS_DISK0_ERROR_DATA 1554 { 1555 U8 ErrorCdbByte; /* 00h */ 1556 U8 ErrorSenseKey; /* 01h */ 1557 U16 Reserved; /* 02h */ 1558 U16 ErrorCount; /* 04h */ 1559 U8 ErrorASC; /* 06h */ 1560 U8 ErrorASCQ; /* 07h */ 1561 U16 SmartCount; /* 08h */ 1562 U8 SmartASC; /* 0Ah */ 1563 U8 SmartASCQ; /* 0Bh */ 1564 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA, 1565 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t; 1566 1567 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA 1568 { 1569 U8 VendorID[8]; /* 00h */ 1570 U8 ProductID[16]; /* 08h */ 1571 U8 ProductRevLevel[4]; /* 18h */ 1572 U8 Info[32]; /* 1Ch */ 1573 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA, 1574 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData; 1575 1576 typedef struct _RAID_PHYS_DISK0_SETTINGS 1577 { 1578 U8 SepID; /* 00h */ 1579 U8 SepBus; /* 01h */ 1580 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 1581 U8 PhysDiskSettings; /* 03h */ 1582 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS, 1583 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t; 1584 1585 typedef struct _RAID_PHYS_DISK0_STATUS 1586 { 1587 U8 Flags; /* 00h */ 1588 U8 State; /* 01h */ 1589 U16 Reserved; /* 02h */ 1590 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS, 1591 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t; 1592 1593 /* RAID Volume 2 IM Physical Disk DiskStatus flags */ 1594 1595 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01) 1596 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02) 1597 1598 #define MPI_PHYSDISK0_STATUS_ONLINE (0x00) 1599 #define MPI_PHYSDISK0_STATUS_MISSING (0x01) 1600 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02) 1601 #define MPI_PHYSDISK0_STATUS_FAILED (0x03) 1602 #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04) 1603 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05) 1604 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06) 1605 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF) 1606 1607 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0 1608 { 1609 CONFIG_PAGE_HEADER Header; /* 00h */ 1610 U8 PhysDiskID; /* 04h */ 1611 U8 PhysDiskBus; /* 05h */ 1612 U8 PhysDiskIOC; /* 06h */ 1613 U8 PhysDiskNum; /* 07h */ 1614 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */ 1615 U32 Reserved1; /* 0Ch */ 1616 U32 Reserved2; /* 10h */ 1617 U32 Reserved3; /* 14h */ 1618 U8 DiskIdentifier[16]; /* 18h */ 1619 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */ 1620 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */ 1621 U32 MaxLBA; /* 68h */ 1622 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */ 1623 } CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0, 1624 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t; 1625 1626 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x00) 1627 1628 1629 /**************************************************************************** 1630 * LAN Config Pages 1631 ****************************************************************************/ 1632 1633 typedef struct _CONFIG_PAGE_LAN_0 1634 { 1635 ConfigPageHeader_t Header; /* 00h */ 1636 U16 TxRxModes; /* 04h */ 1637 U16 Reserved; /* 06h */ 1638 U32 PacketPrePad; /* 08h */ 1639 } CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0, 1640 LANPage0_t, MPI_POINTER pLANPage0_t; 1641 1642 #define MPI_LAN_PAGE0_PAGEVERSION (0x01) 1643 1644 #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000) 1645 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001) 1646 #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001) 1647 1648 typedef struct _CONFIG_PAGE_LAN_1 1649 { 1650 ConfigPageHeader_t Header; /* 00h */ 1651 U16 Reserved; /* 04h */ 1652 U8 CurrentDeviceState; /* 06h */ 1653 U8 Reserved1; /* 07h */ 1654 U32 MinPacketSize; /* 08h */ 1655 U32 MaxPacketSize; /* 0Ch */ 1656 U32 HardwareAddressLow; /* 10h */ 1657 U32 HardwareAddressHigh; /* 14h */ 1658 U32 MaxWireSpeedLow; /* 18h */ 1659 U32 MaxWireSpeedHigh; /* 1Ch */ 1660 U32 BucketsRemaining; /* 20h */ 1661 U32 MaxReplySize; /* 24h */ 1662 U32 NegWireSpeedLow; /* 28h */ 1663 U32 NegWireSpeedHigh; /* 2Ch */ 1664 } CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1, 1665 LANPage1_t, MPI_POINTER pLANPage1_t; 1666 1667 #define MPI_LAN_PAGE1_PAGEVERSION (0x03) 1668 1669 #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00) 1670 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01) 1671 1672 #endif 1673 1674