1 /* $FreeBSD$ */ 2 /*- 3 * Copyright (c) 2000-2010, LSI Logic Corporation and its contributors. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * substantially similar to the "NO WARRANTY" disclaimer below 13 * ("Disclaimer") and any redistribution must be conditioned upon including 14 * a substantially similar Disclaimer requirement for further binary 15 * redistribution. 16 * 3. Neither the name of the LSI Logic Corporation nor the names of its 17 * contributors may be used to endorse or promote products derived from 18 * this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT 30 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * Name: mpi_cnfg.h 33 * Title: MPI Config message, structures, and Pages 34 * Creation Date: July 27, 2000 35 * 36 * mpi_cnfg.h Version: 01.05.19 37 * 38 * Version History 39 * --------------- 40 * 41 * Date Version Description 42 * -------- -------- ------------------------------------------------------ 43 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 44 * 06-06-00 01.00.01 Update version number for 1.0 release. 45 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages. 46 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2 47 * fields to FC_DEVICE_0 page, updated the page version. 48 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in 49 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages 50 * and updated the page versions. 51 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1 52 * page and updated the page version. 53 * Added Information field and _INFO_PARAMS_NEGOTIATED 54 * definitionto SCSI_DEVICE_0 page. 55 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the 56 * page version. 57 * Added BucketsRemaining to LAN_1 page, redefined the 58 * state values, and updated the page version. 59 * Revised bus width definitions in SCSI_PORT_0, 60 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages. 61 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page 62 * version. 63 * Moved FC_DEVICE_0 PageAddress description to spec. 64 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field 65 * widths in IOC_0 page and updated the page version. 66 * 11-02-00 01.01.01 Original release for post 1.0 work 67 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI 68 * Port Page 2, FC Port Page 4, FC Port Page 5 69 * 11-15-00 01.01.02 Interim changes to match proposals 70 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01. 71 * 12-05-00 01.01.04 Modified config page actions. 72 * 01-09-01 01.01.05 Added defines for page address formats. 73 * Data size for Manufacturing pages 2 and 3 no longer 74 * defined here. 75 * Io Unit Page 2 size is fixed at 4 adapters and some 76 * flags were changed. 77 * SCSI Port Page 2 Device Settings modified. 78 * New fields added to FC Port Page 0 and some flags 79 * cleaned up. 80 * Removed impedance flash from FC Port Page 1. 81 * Added FC Port pages 6 and 7. 82 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0. 83 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique. 84 * Added some LinkType defines for FcPortPage0. 85 * 02-20-01 01.01.08 Started using MPI_POINTER. 86 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with 87 * MPI_CONFIG_PAGETYPE_RAID_VOLUME. 88 * Added definitions and structures for IOC Page 2 and 89 * RAID Volume Page 2. 90 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9. 91 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID. 92 * Added VendorId and ProductRevLevel fields to 93 * RAIDVOL2_IM_PHYS_ID struct. 94 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_ 95 * defines to make them compatible to MPI version 1.0. 96 * Added structure offset comments. 97 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and 98 * removed some obsolete ones. 99 * Added IO Unit Page 3. 100 * Modified defines for Scsi Port Page 2. 101 * Modified RAID Volume Pages. 102 * 08-08-01 01.02.01 Original release for v1.2 work. 103 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct. 104 * Added defines for the SEP bits in RVP2 VolumeSettings. 105 * Modified the DeviceSettings field in RVP2 to use the 106 * proper structure. 107 * Added defines for SES, SAF-TE, and cross channel for 108 * IOCPage2 CapabilitiesFlags. 109 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE. 110 * Removed define for 111 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE. 112 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT. 113 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035. 114 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY 115 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY. 116 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS, 117 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and 118 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and 119 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED. 120 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED 121 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED. 122 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1. 123 * Added rejected bits to SCSI Device Page 0 Information. 124 * Increased size of ALPA array in FC Port Page 2 by one 125 * and removed a one byte reserved field. 126 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in 127 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering. 128 * Added structures for Manufacturing Page 4, IO Unit 129 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and 130 * RAID PhysDisk Page 0. 131 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK. 132 * Modified some of the new defines to make them 32 133 * character unique. 134 * Modified how variable length pages (arrays) are defined. 135 * Added generic defines for hot spare pools and RAID 136 * volume types. 137 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR. 138 * 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with 139 * related define, and bumped the page version define. 140 * 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a 141 * reserved byte and added a define. 142 * Added define for 143 * MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE. 144 * Added new config page: CONFIG_PAGE_IOC_5. 145 * Added MaxAliases, MaxHardAliases, and NumCurrentAliases 146 * fields to CONFIG_PAGE_FC_PORT_0. 147 * Added AltConnector and NumRequestedAliases fields to 148 * CONFIG_PAGE_FC_PORT_1. 149 * Added new config page: CONFIG_PAGE_FC_PORT_10. 150 * 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines. 151 * Added additional MPI_SCSIDEVPAGE0_NP_ defines. 152 * Added more MPI_SCSIDEVPAGE1_RP_ defines. 153 * Added define for 154 * MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE. 155 * Added new config page: CONFIG_PAGE_SCSI_DEVICE_3. 156 * Modified MPI_FCPORTPAGE5_FLAGS_ defines. 157 * 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define. 158 * 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0. 159 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1. 160 * Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0. 161 * 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for 162 * CONFIG_PAGE_FC_PORT_1. 163 * Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable 164 * an alias. 165 * Added more device id defines. 166 * 06-26-03 01.02.12 Added MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID define. 167 * Added TargetConfig and IDConfig fields to 168 * CONFIG_PAGE_SCSI_PORT_1. 169 * Added more PortFlags defines for CONFIG_PAGE_SCSI_PORT_2 170 * to control DV. 171 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1. 172 * In CONFIG_PAGE_FC_DEVICE_0, replaced Reserved1 field 173 * with ADISCHardALPA. 174 * Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define. 175 * 01-16-04 01.02.13 Added InitiatorDeviceTimeout and InitiatorIoPendTimeout 176 * fields and related defines to CONFIG_PAGE_FC_PORT_1. 177 * Added define for 178 * MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK. 179 * Added new fields to the substructures of 180 * CONFIG_PAGE_FC_PORT_10. 181 * 04-29-04 01.02.14 Added define for IDP bit for CONFIG_PAGE_SCSI_PORT_0, 182 * CONFIG_PAGE_SCSI_DEVICE_0, and 183 * CONFIG_PAGE_SCSI_DEVICE_1. Also bumped Page Version for 184 * these pages. 185 * 05-11-04 01.03.01 Added structure for CONFIG_PAGE_INBAND_0. 186 * 08-19-04 01.05.01 Modified MSG_CONFIG request to support extended config 187 * pages. 188 * Added a new structure for extended config page header. 189 * Added new extended config pages types and structures for 190 * SAS IO Unit, SAS Expander, SAS Device, and SAS PHY. 191 * Replaced a reserved byte in CONFIG_PAGE_MANUFACTURING_4 192 * to add a Flags field. 193 * Two new Manufacturing config pages (5 and 6). 194 * Two new bits defined for IO Unit Page 1 Flags field. 195 * Modified CONFIG_PAGE_IO_UNIT_2 to add three new fields 196 * to specify the BIOS boot device. 197 * Four new Flags bits defined for IO Unit Page 2. 198 * Added IO Unit Page 4. 199 * Added EEDP Flags settings to IOC Page 1. 200 * Added new BIOS Page 1 config page. 201 * 10-05-04 01.05.02 Added define for 202 * MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE. 203 * Added new Flags field to CONFIG_PAGE_MANUFACTURING_5 and 204 * associated defines. 205 * Added more defines for SAS IO Unit Page 0 206 * DiscoveryStatus field. 207 * Added define for MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK 208 * and MPI_SAS_IOUNIT0_DS_TABLE_LINK. 209 * Added defines for Physical Mapping Modes to SAS IO Unit 210 * Page 2. 211 * Added define for 212 * MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH. 213 * 10-27-04 01.05.03 Added defines for new SAS PHY page addressing mode. 214 * Added defines for MaxTargetSpinUp to BIOS Page 1. 215 * Added 5 new ControlFlags defines for SAS IO Unit 216 * Page 1. 217 * Added MaxNumPhysicalMappedIDs field to SAS IO Unit 218 * Page 2. 219 * Added AccessStatus field to SAS Device Page 0 and added 220 * new Flags bits for supported SATA features. 221 * 12-07-04 01.05.04 Added config page structures for BIOS Page 2, RAID 222 * Volume Page 1, and RAID Physical Disk Page 1. 223 * Replaced IO Unit Page 1 BootTargetID,BootBus, and 224 * BootAdapterNum with reserved field. 225 * Added DataScrubRate and ResyncRate to RAID Volume 226 * Page 0. 227 * Added MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT 228 * define. 229 * 12-09-04 01.05.05 Added Target Mode Large CDB Enable to FC Port Page 1 230 * Flags field. 231 * Added Auto Port Config flag define for SAS IOUNIT 232 * Page 1 ControlFlags. 233 * Added Disabled bad Phy define to Expander Page 1 234 * Discovery Info field. 235 * Added SAS/SATA device support to SAS IOUnit Page 1 236 * ControlFlags. 237 * Added Unsupported device to SAS Dev Page 0 Flags field 238 * Added disable use SATA Hash Address for SAS IOUNIT 239 * page 1 in ControlFields. 240 * 01-15-05 01.05.06 Added defaults for data scrub rate and resync rate to 241 * Manufacturing Page 4. 242 * Added new defines for BIOS Page 1 IOCSettings field. 243 * Added ExtDiskIdentifier field to RAID Physical Disk 244 * Page 0. 245 * Added new defines for SAS IO Unit Page 1 ControlFlags 246 * and to SAS Device Page 0 Flags to control SATA devices. 247 * Added defines and structures for the new Log Page 0, a 248 * new type of configuration page. 249 * 02-09-05 01.05.07 Added InactiveStatus field to RAID Volume Page 0. 250 * Added WWID field to RAID Volume Page 1. 251 * Added PhysicalPort field to SAS Expander pages 0 and 1. 252 * 03-11-05 01.05.08 Removed the EEDP flags from IOC Page 1. 253 * Added Enclosure/Slot boot device format to BIOS Page 2. 254 * New status value for RAID Volume Page 0 VolumeStatus 255 * (VolumeState subfield). 256 * New value for RAID Physical Page 0 InactiveStatus. 257 * Added Inactive Volume Member flag RAID Physical Disk 258 * Page 0 PhysDiskStatus field. 259 * New physical mapping mode in SAS IO Unit Page 2. 260 * Added CONFIG_PAGE_SAS_ENCLOSURE_0. 261 * Added Slot and Enclosure fields to SAS Device Page 0. 262 * 06-24-05 01.05.09 Added EEDP defines to IOC Page 1. 263 * Added more RAID type defines to IOC Page 2. 264 * Added Port Enable Delay settings to BIOS Page 1. 265 * Added Bad Block Table Full define to RAID Volume Page 0. 266 * Added Previous State defines to RAID Physical Disk 267 * Page 0. 268 * Added Max Sata Targets define for DiscoveryStatus field 269 * of SAS IO Unit Page 0. 270 * Added Device Self Test to Control Flags of SAS IO Unit 271 * Page 1. 272 * Added Direct Attach Starting Slot Number define for SAS 273 * IO Unit Page 2. 274 * Added new fields in SAS Device Page 2 for enclosure 275 * mapping. 276 * Added OwnerDevHandle and Flags field to SAS PHY Page 0. 277 * Added IOC GPIO Flags define to SAS Enclosure Page 0. 278 * Fixed the value for MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT. 279 * 08-03-05 01.05.10 Removed ISDataScrubRate and ISResyncRate from 280 * Manufacturing Page 4. 281 * Added MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE bit. 282 * Added NumDevsPerEnclosure field to SAS IO Unit page 2. 283 * Added MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP 284 * define. 285 * Added EnclosureHandle field to SAS Expander page 0. 286 * Removed redundant NumTableEntriesProg field from SAS 287 * Expander Page 1. 288 * 08-30-05 01.05.11 Added DeviceID for FC949E and changed the DeviceID for 289 * SAS1078. 290 * Added more defines for Manufacturing Page 4 Flags field. 291 * Added more defines for IOCSettings and added 292 * ExpanderSpinup field to Bios Page 1. 293 * Added postpone SATA Init bit to SAS IO Unit Page 1 294 * ControlFlags. 295 * Changed LogEntry format for Log Page 0. 296 * 03-27-06 01.05.12 Added two new Flags defines for Manufacturing Page 4. 297 * Added Manufacturing Page 7. 298 * Added MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING. 299 * Added IOC Page 6. 300 * Added PrevBootDeviceForm field to CONFIG_PAGE_BIOS_2. 301 * Added MaxLBAHigh field to RAID Volume Page 0. 302 * Added Nvdata version fields to SAS IO Unit Page 0. 303 * Added AdditionalControlFlags, MaxTargetPortConnectTime, 304 * ReportDeviceMissingDelay, and IODeviceMissingDelay 305 * fields to SAS IO Unit Page 1. 306 * 10-11-06 01.05.13 Added NumForceWWID field and ForceWWID array to 307 * Manufacturing Page 5. 308 * Added Manufacturing pages 8 through 10. 309 * Added defines for supported metadata size bits in 310 * CapabilitiesFlags field of IOC Page 6. 311 * Added defines for metadata size bits in VolumeSettings 312 * field of RAID Volume Page 0. 313 * Added SATA Link Reset settings, Enable SATA Asynchronous 314 * Notification bit, and HideNonZeroAttachedPhyIdentifiers 315 * bit to AdditionalControlFlags field of SAS IO Unit 316 * Page 1. 317 * Added defines for Enclosure Devices Unmapped and 318 * Device Limit Exceeded bits in Status field of SAS IO 319 * Unit Page 2. 320 * Added more AccessStatus values for SAS Device Page 0. 321 * Added bit for SATA Asynchronous Notification Support in 322 * Flags field of SAS Device Page 0. 323 * 02-28-07 01.05.14 Added ExtFlags field to Manufacturing Page 4. 324 * Added Disable SMART Polling for CapabilitiesFlags of 325 * IOC Page 6. 326 * Added Disable SMART Polling to DeviceSettings of BIOS 327 * Page 1. 328 * Added Multi-Port Domain bit for DiscoveryStatus field 329 * of SAS IO Unit Page. 330 * Added Multi-Port Domain Illegal flag for SAS IO Unit 331 * Page 1 AdditionalControlFlags field. 332 * 05-24-07 01.05.15 Added Hide Physical Disks with Non-Integrated RAID 333 * Metadata bit to Manufacturing Page 4 ExtFlags field. 334 * Added Internal Connector to End Device Present bit to 335 * Expander Page 0 Flags field. 336 * Fixed define for 337 * MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED. 338 * 08-07-07 01.05.16 Added MPI_IOCPAGE6_CAP_FLAGS_MULTIPORT_DRIVE_SUPPORT 339 * define. 340 * Added BIOS Page 4 structure. 341 * Added MPI_RAID_PHYS_DISK1_PATH_MAX define for RAID 342 * Physical Disk Page 1. 343 * 01-15-07 01.05.17 Added additional bit defines for ExtFlags field of 344 * Manufacturing Page 4. 345 * Added Solid State Drives Supported bit to IOC Page 6 346 * Capabilities Flags. 347 * Added new value for AccessStatus field of SAS Device 348 * Page 0 (_SATA_NEEDS_INITIALIZATION). 349 * 03-28-08 01.05.18 Defined new bits in Manufacturing Page 4 ExtFlags field 350 * to control coercion size and the mixing of SAS and SATA 351 * SSD drives. 352 * 07-11-08 01.05.19 Added defines MPI_MANPAGE4_EXTFLAGS_RAID0_SINGLE_DRIVE 353 * and MPI_MANPAGE4_EXTFLAGS_SSD_SCRUB_DISABLE for ExtFlags 354 * field of Manufacturing Page 4. 355 * Added defines for a new bit in BIOS Page 1 BiosOptions 356 * field to control adapter scan order. 357 * Added BootDeviceWaitTime field to SAS IO Unit Page 2. 358 * Added MPI_SAS_PHY0_PHYINFO_PHY_VACANT for use in PhyInfo 359 * field of SAS Expander Page 1. 360 * -------------------------------------------------------------------------- 361 */ 362 363 #ifndef MPI_CNFG_H 364 #define MPI_CNFG_H 365 366 367 /***************************************************************************** 368 * 369 * C o n f i g M e s s a g e a n d S t r u c t u r e s 370 * 371 *****************************************************************************/ 372 373 typedef struct _CONFIG_PAGE_HEADER 374 { 375 U8 PageVersion; /* 00h */ 376 U8 PageLength; /* 01h */ 377 U8 PageNumber; /* 02h */ 378 U8 PageType; /* 03h */ 379 } CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER, 380 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t; 381 382 typedef union _CONFIG_PAGE_HEADER_UNION 383 { 384 ConfigPageHeader_t Struct; 385 U8 Bytes[4]; 386 U16 Word16[2]; 387 U32 Word32; 388 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion, 389 CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION; 390 391 typedef struct _CONFIG_EXTENDED_PAGE_HEADER 392 { 393 U8 PageVersion; /* 00h */ 394 U8 Reserved1; /* 01h */ 395 U8 PageNumber; /* 02h */ 396 U8 PageType; /* 03h */ 397 U16 ExtPageLength; /* 04h */ 398 U8 ExtPageType; /* 06h */ 399 U8 Reserved2; /* 07h */ 400 } CONFIG_EXTENDED_PAGE_HEADER, MPI_POINTER PTR_CONFIG_EXTENDED_PAGE_HEADER, 401 ConfigExtendedPageHeader_t, MPI_POINTER pConfigExtendedPageHeader_t; 402 403 404 405 /**************************************************************************** 406 * PageType field values 407 ****************************************************************************/ 408 #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00) 409 #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10) 410 #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20) 411 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30) 412 #define MPI_CONFIG_PAGEATTR_MASK (0xF0) 413 414 #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00) 415 #define MPI_CONFIG_PAGETYPE_IOC (0x01) 416 #define MPI_CONFIG_PAGETYPE_BIOS (0x02) 417 #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03) 418 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04) 419 #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05) 420 #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06) 421 #define MPI_CONFIG_PAGETYPE_LAN (0x07) 422 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 423 #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09) 424 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 425 #define MPI_CONFIG_PAGETYPE_INBAND (0x0B) 426 #define MPI_CONFIG_PAGETYPE_EXTENDED (0x0F) 427 #define MPI_CONFIG_PAGETYPE_MASK (0x0F) 428 429 #define MPI_CONFIG_TYPENUM_MASK (0x0FFF) 430 431 432 /**************************************************************************** 433 * ExtPageType field values 434 ****************************************************************************/ 435 #define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 436 #define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 437 #define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 438 #define MPI_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 439 #define MPI_CONFIG_EXTPAGETYPE_LOG (0x14) 440 #define MPI_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 441 442 443 /**************************************************************************** 444 * PageAddress field values 445 ****************************************************************************/ 446 #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF) 447 448 #define MPI_SCSI_DEVICE_FORM_MASK (0xF0000000) 449 #define MPI_SCSI_DEVICE_FORM_BUS_TID (0x00000000) 450 #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF) 451 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0) 452 #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00) 453 #define MPI_SCSI_DEVICE_BUS_SHIFT (8) 454 #define MPI_SCSI_DEVICE_FORM_TARGET_MODE (0x10000000) 455 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_MASK (0x000000FF) 456 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_SHIFT (0) 457 #define MPI_SCSI_DEVICE_TM_BUS_MASK (0x0000FF00) 458 #define MPI_SCSI_DEVICE_TM_BUS_SHIFT (8) 459 #define MPI_SCSI_DEVICE_TM_INIT_ID_MASK (0x00FF0000) 460 #define MPI_SCSI_DEVICE_TM_INIT_ID_SHIFT (16) 461 462 #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000) 463 #define MPI_FC_PORT_PGAD_PORT_SHIFT (28) 464 #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000) 465 #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000) 466 #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF) 467 #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0) 468 469 #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000) 470 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28) 471 #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000) 472 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000) 473 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000) 474 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28) 475 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF) 476 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0) 477 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000) 478 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 479 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8) 480 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 481 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0) 482 483 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 484 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0) 485 486 #define MPI_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 487 #define MPI_SAS_EXPAND_PGAD_FORM_SHIFT (28) 488 #define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 489 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x00000001) 490 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE (0x00000002) 491 #define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE (0x0000FFFF) 492 #define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE (0) 493 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY (0x00FF0000) 494 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY (16) 495 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE (0x0000FFFF) 496 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE (0) 497 #define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE (0x0000FFFF) 498 #define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE (0) 499 500 #define MPI_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 501 #define MPI_SAS_DEVICE_PGAD_FORM_SHIFT (28) 502 #define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 503 #define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID (0x00000001) 504 #define MPI_SAS_DEVICE_PGAD_FORM_HANDLE (0x00000002) 505 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK (0x0000FFFF) 506 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT (0) 507 #define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 508 #define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT (8) 509 #define MPI_SAS_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 510 #define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT (0) 511 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK (0x0000FFFF) 512 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT (0) 513 514 #define MPI_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 515 #define MPI_SAS_PHY_PGAD_FORM_SHIFT (28) 516 #define MPI_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x0) 517 #define MPI_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x1) 518 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 519 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (0) 520 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 521 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_SHIFT (0) 522 523 #define MPI_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 524 #define MPI_SAS_ENCLOS_PGAD_FORM_SHIFT (28) 525 #define MPI_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 526 #define MPI_SAS_ENCLOS_PGAD_FORM_HANDLE (0x00000001) 527 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_MASK (0x0000FFFF) 528 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_SHIFT (0) 529 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_MASK (0x0000FFFF) 530 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_SHIFT (0) 531 532 533 534 /**************************************************************************** 535 * Config Request Message 536 ****************************************************************************/ 537 typedef struct _MSG_CONFIG 538 { 539 U8 Action; /* 00h */ 540 U8 Reserved; /* 01h */ 541 U8 ChainOffset; /* 02h */ 542 U8 Function; /* 03h */ 543 U16 ExtPageLength; /* 04h */ 544 U8 ExtPageType; /* 06h */ 545 U8 MsgFlags; /* 07h */ 546 U32 MsgContext; /* 08h */ 547 U8 Reserved2[8]; /* 0Ch */ 548 CONFIG_PAGE_HEADER Header; /* 14h */ 549 U32 PageAddress; /* 18h */ 550 SGE_IO_UNION PageBufferSGE; /* 1Ch */ 551 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG, 552 Config_t, MPI_POINTER pConfig_t; 553 554 555 /**************************************************************************** 556 * Action field values 557 ****************************************************************************/ 558 #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00) 559 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 560 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 561 #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03) 562 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 563 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 564 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 565 566 567 /* Config Reply Message */ 568 typedef struct _MSG_CONFIG_REPLY 569 { 570 U8 Action; /* 00h */ 571 U8 Reserved; /* 01h */ 572 U8 MsgLength; /* 02h */ 573 U8 Function; /* 03h */ 574 U16 ExtPageLength; /* 04h */ 575 U8 ExtPageType; /* 06h */ 576 U8 MsgFlags; /* 07h */ 577 U32 MsgContext; /* 08h */ 578 U8 Reserved2[2]; /* 0Ch */ 579 U16 IOCStatus; /* 0Eh */ 580 U32 IOCLogInfo; /* 10h */ 581 CONFIG_PAGE_HEADER Header; /* 14h */ 582 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY, 583 ConfigReply_t, MPI_POINTER pConfigReply_t; 584 585 586 587 /***************************************************************************** 588 * 589 * C o n f i g u r a t i o n P a g e s 590 * 591 *****************************************************************************/ 592 593 /**************************************************************************** 594 * Manufacturing Config pages 595 ****************************************************************************/ 596 #define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000) 597 /* Fibre Channel */ 598 #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621) 599 #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624) 600 #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622) 601 #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628) 602 #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626) 603 #define MPI_MANUFACTPAGE_DEVICEID_FC939X (0x0642) 604 #define MPI_MANUFACTPAGE_DEVICEID_FC949X (0x0640) 605 #define MPI_MANUFACTPAGE_DEVICEID_FC949E (0x0646) 606 /* SCSI */ 607 #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030) 608 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031) 609 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032) 610 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033) 611 #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040) 612 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041) 613 /* SAS */ 614 #define MPI_MANUFACTPAGE_DEVID_SAS1064 (0x0050) 615 #define MPI_MANUFACTPAGE_DEVID_SAS1064A (0x005C) 616 #define MPI_MANUFACTPAGE_DEVID_SAS1064E (0x0056) 617 #define MPI_MANUFACTPAGE_DEVID_SAS1066 (0x005E) 618 #define MPI_MANUFACTPAGE_DEVID_SAS1066E (0x005A) 619 #define MPI_MANUFACTPAGE_DEVID_SAS1068 (0x0054) 620 #define MPI_MANUFACTPAGE_DEVID_SAS1068E (0x0058) 621 #define MPI_MANUFACTPAGE_DEVID_SAS1078 (0x0062) 622 623 624 typedef struct _CONFIG_PAGE_MANUFACTURING_0 625 { 626 CONFIG_PAGE_HEADER Header; /* 00h */ 627 U8 ChipName[16]; /* 04h */ 628 U8 ChipRevision[8]; /* 14h */ 629 U8 BoardName[16]; /* 1Ch */ 630 U8 BoardAssembly[16]; /* 2Ch */ 631 U8 BoardTracerNumber[16]; /* 3Ch */ 632 633 } CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0, 634 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t; 635 636 #define MPI_MANUFACTURING0_PAGEVERSION (0x00) 637 638 639 typedef struct _CONFIG_PAGE_MANUFACTURING_1 640 { 641 CONFIG_PAGE_HEADER Header; /* 00h */ 642 U8 VPD[256]; /* 04h */ 643 } CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1, 644 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t; 645 646 #define MPI_MANUFACTURING1_PAGEVERSION (0x00) 647 648 649 typedef struct _MPI_CHIP_REVISION_ID 650 { 651 U16 DeviceID; /* 00h */ 652 U8 PCIRevisionID; /* 02h */ 653 U8 Reserved; /* 03h */ 654 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID, 655 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t; 656 657 658 /* 659 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 660 * one and check Header.PageLength at runtime. 661 */ 662 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS 663 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 664 #endif 665 666 typedef struct _CONFIG_PAGE_MANUFACTURING_2 667 { 668 CONFIG_PAGE_HEADER Header; /* 00h */ 669 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 670 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */ 671 } CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2, 672 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t; 673 674 #define MPI_MANUFACTURING2_PAGEVERSION (0x00) 675 676 677 /* 678 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 679 * one and check Header.PageLength at runtime. 680 */ 681 #ifndef MPI_MAN_PAGE_3_INFO_WORDS 682 #define MPI_MAN_PAGE_3_INFO_WORDS (1) 683 #endif 684 685 typedef struct _CONFIG_PAGE_MANUFACTURING_3 686 { 687 CONFIG_PAGE_HEADER Header; /* 00h */ 688 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 689 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */ 690 } CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3, 691 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t; 692 693 #define MPI_MANUFACTURING3_PAGEVERSION (0x00) 694 695 696 typedef struct _CONFIG_PAGE_MANUFACTURING_4 697 { 698 CONFIG_PAGE_HEADER Header; /* 00h */ 699 U32 Reserved1; /* 04h */ 700 U8 InfoOffset0; /* 08h */ 701 U8 InfoSize0; /* 09h */ 702 U8 InfoOffset1; /* 0Ah */ 703 U8 InfoSize1; /* 0Bh */ 704 U8 InquirySize; /* 0Ch */ 705 U8 Flags; /* 0Dh */ 706 U16 ExtFlags; /* 0Eh */ 707 U8 InquiryData[56]; /* 10h */ 708 U32 ISVolumeSettings; /* 48h */ 709 U32 IMEVolumeSettings; /* 4Ch */ 710 U32 IMVolumeSettings; /* 50h */ 711 U32 Reserved3; /* 54h */ 712 U32 Reserved4; /* 58h */ 713 U32 Reserved5; /* 5Ch */ 714 U8 IMEDataScrubRate; /* 60h */ 715 U8 IMEResyncRate; /* 61h */ 716 U16 Reserved6; /* 62h */ 717 U8 IMDataScrubRate; /* 64h */ 718 U8 IMResyncRate; /* 65h */ 719 U16 Reserved7; /* 66h */ 720 U32 Reserved8; /* 68h */ 721 U32 Reserved9; /* 6Ch */ 722 } CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4, 723 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t; 724 725 #define MPI_MANUFACTURING4_PAGEVERSION (0x05) 726 727 /* defines for the Flags field */ 728 #define MPI_MANPAGE4_FORCE_BAD_BLOCK_TABLE (0x80) 729 #define MPI_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x40) 730 #define MPI_MANPAGE4_IME_DISABLE (0x20) 731 #define MPI_MANPAGE4_IM_DISABLE (0x10) 732 #define MPI_MANPAGE4_IS_DISABLE (0x08) 733 #define MPI_MANPAGE4_IR_MODEPAGE8_DISABLE (0x04) 734 #define MPI_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x02) 735 #define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA (0x01) 736 737 /* defines for the ExtFlags field */ 738 #define MPI_MANPAGE4_EXTFLAGS_RAID0_SINGLE_DRIVE (0x0400) 739 #define MPI_MANPAGE4_EXTFLAGS_SSD_SCRUB_DISABLE (0x0200) 740 #define MPI_MANPAGE4_EXTFLAGS_MASK_COERCION_SIZE (0x0180) 741 #define MPI_MANPAGE4_EXTFLAGS_SHIFT_COERCION_SIZE (7) 742 #define MPI_MANPAGE4_EXTFLAGS_1GB_COERCION_SIZE (0) 743 #define MPI_MANPAGE4_EXTFLAGS_128MB_COERCION_SIZE (1) 744 745 #define MPI_MANPAGE4_EXTFLAGS_NO_MIX_SSD_SAS_SATA (0x0040) 746 #define MPI_MANPAGE4_EXTFLAGS_MIX_SSD_AND_NON_SSD (0x0020) 747 #define MPI_MANPAGE4_EXTFLAGS_DUAL_PORT_SUPPORT (0x0010) 748 #define MPI_MANPAGE4_EXTFLAGS_HIDE_NON_IR_METADATA (0x0008) 749 #define MPI_MANPAGE4_EXTFLAGS_SAS_CACHE_DISABLE (0x0004) 750 #define MPI_MANPAGE4_EXTFLAGS_SATA_CACHE_DISABLE (0x0002) 751 #define MPI_MANPAGE4_EXTFLAGS_LEGACY_MODE (0x0001) 752 753 754 #ifndef MPI_MANPAGE5_NUM_FORCEWWID 755 #define MPI_MANPAGE5_NUM_FORCEWWID (1) 756 #endif 757 758 typedef struct _CONFIG_PAGE_MANUFACTURING_5 759 { 760 CONFIG_PAGE_HEADER Header; /* 00h */ 761 U64 BaseWWID; /* 04h */ 762 U8 Flags; /* 0Ch */ 763 U8 NumForceWWID; /* 0Dh */ 764 U16 Reserved2; /* 0Eh */ 765 U32 Reserved3; /* 10h */ 766 U32 Reserved4; /* 14h */ 767 U64 ForceWWID[MPI_MANPAGE5_NUM_FORCEWWID]; /* 18h */ 768 } CONFIG_PAGE_MANUFACTURING_5, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_5, 769 ManufacturingPage5_t, MPI_POINTER pManufacturingPage5_t; 770 771 #define MPI_MANUFACTURING5_PAGEVERSION (0x02) 772 773 /* defines for the Flags field */ 774 #define MPI_MANPAGE5_TWO_WWID_PER_PHY (0x01) 775 776 777 typedef struct _CONFIG_PAGE_MANUFACTURING_6 778 { 779 CONFIG_PAGE_HEADER Header; /* 00h */ 780 U32 ProductSpecificInfo;/* 04h */ 781 } CONFIG_PAGE_MANUFACTURING_6, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_6, 782 ManufacturingPage6_t, MPI_POINTER pManufacturingPage6_t; 783 784 #define MPI_MANUFACTURING6_PAGEVERSION (0x00) 785 786 787 typedef struct _MPI_MANPAGE7_CONNECTOR_INFO 788 { 789 U32 Pinout; /* 00h */ 790 U8 Connector[16]; /* 04h */ 791 U8 Location; /* 14h */ 792 U8 Reserved1; /* 15h */ 793 U16 Slot; /* 16h */ 794 U32 Reserved2; /* 18h */ 795 } MPI_MANPAGE7_CONNECTOR_INFO, MPI_POINTER PTR_MPI_MANPAGE7_CONNECTOR_INFO, 796 MpiManPage7ConnectorInfo_t, MPI_POINTER pMpiManPage7ConnectorInfo_t; 797 798 /* defines for the Pinout field */ 799 #define MPI_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000) 800 #define MPI_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000) 801 #define MPI_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000) 802 #define MPI_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000) 803 #define MPI_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800) 804 #define MPI_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400) 805 #define MPI_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200) 806 #define MPI_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100) 807 #define MPI_MANPAGE7_PINOUT_SFF_8482 (0x00000002) 808 #define MPI_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001) 809 810 /* defines for the Location field */ 811 #define MPI_MANPAGE7_LOCATION_UNKNOWN (0x01) 812 #define MPI_MANPAGE7_LOCATION_INTERNAL (0x02) 813 #define MPI_MANPAGE7_LOCATION_EXTERNAL (0x04) 814 #define MPI_MANPAGE7_LOCATION_SWITCHABLE (0x08) 815 #define MPI_MANPAGE7_LOCATION_AUTO (0x10) 816 #define MPI_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 817 #define MPI_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 818 819 /* 820 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 821 * one and check NumPhys at runtime. 822 */ 823 #ifndef MPI_MANPAGE7_CONNECTOR_INFO_MAX 824 #define MPI_MANPAGE7_CONNECTOR_INFO_MAX (1) 825 #endif 826 827 typedef struct _CONFIG_PAGE_MANUFACTURING_7 828 { 829 CONFIG_PAGE_HEADER Header; /* 00h */ 830 U32 Reserved1; /* 04h */ 831 U32 Reserved2; /* 08h */ 832 U32 Flags; /* 0Ch */ 833 U8 EnclosureName[16]; /* 10h */ 834 U8 NumPhys; /* 20h */ 835 U8 Reserved3; /* 21h */ 836 U16 Reserved4; /* 22h */ 837 MPI_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI_MANPAGE7_CONNECTOR_INFO_MAX]; /* 24h */ 838 } CONFIG_PAGE_MANUFACTURING_7, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_7, 839 ManufacturingPage7_t, MPI_POINTER pManufacturingPage7_t; 840 841 #define MPI_MANUFACTURING7_PAGEVERSION (0x00) 842 843 /* defines for the Flags field */ 844 #define MPI_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 845 846 847 typedef struct _CONFIG_PAGE_MANUFACTURING_8 848 { 849 CONFIG_PAGE_HEADER Header; /* 00h */ 850 U32 ProductSpecificInfo;/* 04h */ 851 } CONFIG_PAGE_MANUFACTURING_8, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_8, 852 ManufacturingPage8_t, MPI_POINTER pManufacturingPage8_t; 853 854 #define MPI_MANUFACTURING8_PAGEVERSION (0x00) 855 856 857 typedef struct _CONFIG_PAGE_MANUFACTURING_9 858 { 859 CONFIG_PAGE_HEADER Header; /* 00h */ 860 U32 ProductSpecificInfo;/* 04h */ 861 } CONFIG_PAGE_MANUFACTURING_9, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_9, 862 ManufacturingPage9_t, MPI_POINTER pManufacturingPage9_t; 863 864 #define MPI_MANUFACTURING9_PAGEVERSION (0x00) 865 866 867 typedef struct _CONFIG_PAGE_MANUFACTURING_10 868 { 869 CONFIG_PAGE_HEADER Header; /* 00h */ 870 U32 ProductSpecificInfo;/* 04h */ 871 } CONFIG_PAGE_MANUFACTURING_10, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_10, 872 ManufacturingPage10_t, MPI_POINTER pManufacturingPage10_t; 873 874 #define MPI_MANUFACTURING10_PAGEVERSION (0x00) 875 876 877 /**************************************************************************** 878 * IO Unit Config Pages 879 ****************************************************************************/ 880 881 typedef struct _CONFIG_PAGE_IO_UNIT_0 882 { 883 CONFIG_PAGE_HEADER Header; /* 00h */ 884 U64 UniqueValue; /* 04h */ 885 } CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0, 886 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t; 887 888 #define MPI_IOUNITPAGE0_PAGEVERSION (0x00) 889 890 891 typedef struct _CONFIG_PAGE_IO_UNIT_1 892 { 893 CONFIG_PAGE_HEADER Header; /* 00h */ 894 U32 Flags; /* 04h */ 895 } CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1, 896 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t; 897 898 #define MPI_IOUNITPAGE1_PAGEVERSION (0x02) 899 900 /* IO Unit Page 1 Flags defines */ 901 #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000) 902 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001) 903 #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002) 904 #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000) 905 #define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 906 #define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING (0x00000020) 907 #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040) 908 #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080) 909 #define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 910 #define MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE (0x00000200) 911 912 typedef struct _MPI_ADAPTER_INFO 913 { 914 U8 PciBusNumber; /* 00h */ 915 U8 PciDeviceAndFunctionNumber; /* 01h */ 916 U16 AdapterFlags; /* 02h */ 917 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO, 918 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t; 919 920 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 921 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 922 923 typedef struct _CONFIG_PAGE_IO_UNIT_2 924 { 925 CONFIG_PAGE_HEADER Header; /* 00h */ 926 U32 Flags; /* 04h */ 927 U32 BiosVersion; /* 08h */ 928 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */ 929 U32 Reserved1; /* 1Ch */ 930 } CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2, 931 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t; 932 933 #define MPI_IOUNITPAGE2_PAGEVERSION (0x02) 934 935 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002) 936 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004) 937 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008) 938 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010) 939 940 #define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 941 #define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 942 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY (0x00000020) 943 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 944 945 946 /* 947 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 948 * one and check Header.PageLength at runtime. 949 */ 950 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX 951 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 952 #endif 953 954 typedef struct _CONFIG_PAGE_IO_UNIT_3 955 { 956 CONFIG_PAGE_HEADER Header; /* 00h */ 957 U8 GPIOCount; /* 04h */ 958 U8 Reserved1; /* 05h */ 959 U16 Reserved2; /* 06h */ 960 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */ 961 } CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3, 962 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t; 963 964 #define MPI_IOUNITPAGE3_PAGEVERSION (0x01) 965 966 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC) 967 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 968 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00) 969 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01) 970 971 972 typedef struct _CONFIG_PAGE_IO_UNIT_4 973 { 974 CONFIG_PAGE_HEADER Header; /* 00h */ 975 U32 Reserved1; /* 04h */ 976 SGE_SIMPLE_UNION FWImageSGE; /* 08h */ 977 } CONFIG_PAGE_IO_UNIT_4, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_4, 978 IOUnitPage4_t, MPI_POINTER pIOUnitPage4_t; 979 980 #define MPI_IOUNITPAGE4_PAGEVERSION (0x00) 981 982 983 /**************************************************************************** 984 * IOC Config Pages 985 ****************************************************************************/ 986 987 typedef struct _CONFIG_PAGE_IOC_0 988 { 989 CONFIG_PAGE_HEADER Header; /* 00h */ 990 U32 TotalNVStore; /* 04h */ 991 U32 FreeNVStore; /* 08h */ 992 U16 VendorID; /* 0Ch */ 993 U16 DeviceID; /* 0Eh */ 994 U8 RevisionID; /* 10h */ 995 U8 Reserved[3]; /* 11h */ 996 U32 ClassCode; /* 14h */ 997 U16 SubsystemVendorID; /* 18h */ 998 U16 SubsystemID; /* 1Ah */ 999 } CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0, 1000 IOCPage0_t, MPI_POINTER pIOCPage0_t; 1001 1002 #define MPI_IOCPAGE0_PAGEVERSION (0x01) 1003 1004 1005 typedef struct _CONFIG_PAGE_IOC_1 1006 { 1007 CONFIG_PAGE_HEADER Header; /* 00h */ 1008 U32 Flags; /* 04h */ 1009 U32 CoalescingTimeout; /* 08h */ 1010 U8 CoalescingDepth; /* 0Ch */ 1011 U8 PCISlotNum; /* 0Dh */ 1012 U8 Reserved[2]; /* 0Eh */ 1013 } CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1, 1014 IOCPage1_t, MPI_POINTER pIOCPage1_t; 1015 1016 #define MPI_IOCPAGE1_PAGEVERSION (0x03) 1017 1018 /* defines for the Flags field */ 1019 #define MPI_IOCPAGE1_EEDP_MODE_MASK (0x07000000) 1020 #define MPI_IOCPAGE1_EEDP_MODE_OFF (0x00000000) 1021 #define MPI_IOCPAGE1_EEDP_MODE_T10 (0x01000000) 1022 #define MPI_IOCPAGE1_EEDP_MODE_LSI_1 (0x02000000) 1023 #define MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE (0x00000010) 1024 #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001) 1025 1026 #define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1027 1028 1029 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL 1030 { 1031 U8 VolumeID; /* 00h */ 1032 U8 VolumeBus; /* 01h */ 1033 U8 VolumeIOC; /* 02h */ 1034 U8 VolumePageNumber; /* 03h */ 1035 U8 VolumeType; /* 04h */ 1036 U8 Flags; /* 05h */ 1037 U16 Reserved3; /* 06h */ 1038 } CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL, 1039 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t; 1040 1041 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */ 1042 1043 #define MPI_RAID_VOL_TYPE_IS (0x00) 1044 #define MPI_RAID_VOL_TYPE_IME (0x01) 1045 #define MPI_RAID_VOL_TYPE_IM (0x02) 1046 #define MPI_RAID_VOL_TYPE_RAID_5 (0x03) 1047 #define MPI_RAID_VOL_TYPE_RAID_6 (0x04) 1048 #define MPI_RAID_VOL_TYPE_RAID_10 (0x05) 1049 #define MPI_RAID_VOL_TYPE_RAID_50 (0x06) 1050 #define MPI_RAID_VOL_TYPE_UNKNOWN (0xFF) 1051 1052 /* IOC Page 2 Volume Flags values */ 1053 1054 #define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08) 1055 1056 /* 1057 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1058 * one and check Header.PageLength at runtime. 1059 */ 1060 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX 1061 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1) 1062 #endif 1063 1064 typedef struct _CONFIG_PAGE_IOC_2 1065 { 1066 CONFIG_PAGE_HEADER Header; /* 00h */ 1067 U32 CapabilitiesFlags; /* 04h */ 1068 U8 NumActiveVolumes; /* 08h */ 1069 U8 MaxVolumes; /* 09h */ 1070 U8 NumActivePhysDisks; /* 0Ah */ 1071 U8 MaxPhysDisks; /* 0Bh */ 1072 CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */ 1073 } CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2, 1074 IOCPage2_t, MPI_POINTER pIOCPage2_t; 1075 1076 #define MPI_IOCPAGE2_PAGEVERSION (0x04) 1077 1078 /* IOC Page 2 Capabilities flags */ 1079 1080 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001) 1081 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002) 1082 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004) 1083 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_5_SUPPORT (0x00000008) 1084 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_6_SUPPORT (0x00000010) 1085 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_10_SUPPORT (0x00000020) 1086 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_50_SUPPORT (0x00000040) 1087 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING (0x10000000) 1088 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000) 1089 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000) 1090 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000) 1091 1092 1093 typedef struct _IOC_3_PHYS_DISK 1094 { 1095 U8 PhysDiskID; /* 00h */ 1096 U8 PhysDiskBus; /* 01h */ 1097 U8 PhysDiskIOC; /* 02h */ 1098 U8 PhysDiskNum; /* 03h */ 1099 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK, 1100 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t; 1101 1102 /* 1103 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1104 * one and check Header.PageLength at runtime. 1105 */ 1106 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX 1107 #define MPI_IOC_PAGE_3_PHYSDISK_MAX (1) 1108 #endif 1109 1110 typedef struct _CONFIG_PAGE_IOC_3 1111 { 1112 CONFIG_PAGE_HEADER Header; /* 00h */ 1113 U8 NumPhysDisks; /* 04h */ 1114 U8 Reserved1; /* 05h */ 1115 U16 Reserved2; /* 06h */ 1116 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */ 1117 } CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3, 1118 IOCPage3_t, MPI_POINTER pIOCPage3_t; 1119 1120 #define MPI_IOCPAGE3_PAGEVERSION (0x00) 1121 1122 1123 typedef struct _IOC_4_SEP 1124 { 1125 U8 SEPTargetID; /* 00h */ 1126 U8 SEPBus; /* 01h */ 1127 U16 Reserved; /* 02h */ 1128 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP, 1129 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t; 1130 1131 /* 1132 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1133 * one and check Header.PageLength at runtime. 1134 */ 1135 #ifndef MPI_IOC_PAGE_4_SEP_MAX 1136 #define MPI_IOC_PAGE_4_SEP_MAX (1) 1137 #endif 1138 1139 typedef struct _CONFIG_PAGE_IOC_4 1140 { 1141 CONFIG_PAGE_HEADER Header; /* 00h */ 1142 U8 ActiveSEP; /* 04h */ 1143 U8 MaxSEP; /* 05h */ 1144 U16 Reserved1; /* 06h */ 1145 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */ 1146 } CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4, 1147 IOCPage4_t, MPI_POINTER pIOCPage4_t; 1148 1149 #define MPI_IOCPAGE4_PAGEVERSION (0x00) 1150 1151 1152 typedef struct _IOC_5_HOT_SPARE 1153 { 1154 U8 PhysDiskNum; /* 00h */ 1155 U8 Reserved; /* 01h */ 1156 U8 HotSparePool; /* 02h */ 1157 U8 Flags; /* 03h */ 1158 } IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE, 1159 Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t; 1160 1161 /* IOC Page 5 HotSpare Flags */ 1162 #define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01) 1163 1164 /* 1165 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1166 * one and check Header.PageLength at runtime. 1167 */ 1168 #ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX 1169 #define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1) 1170 #endif 1171 1172 typedef struct _CONFIG_PAGE_IOC_5 1173 { 1174 CONFIG_PAGE_HEADER Header; /* 00h */ 1175 U32 Reserved1; /* 04h */ 1176 U8 NumHotSpares; /* 08h */ 1177 U8 Reserved2; /* 09h */ 1178 U16 Reserved3; /* 0Ah */ 1179 IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */ 1180 } CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5, 1181 IOCPage5_t, MPI_POINTER pIOCPage5_t; 1182 1183 #define MPI_IOCPAGE5_PAGEVERSION (0x00) 1184 1185 typedef struct _CONFIG_PAGE_IOC_6 1186 { 1187 CONFIG_PAGE_HEADER Header; /* 00h */ 1188 U32 CapabilitiesFlags; /* 04h */ 1189 U8 MaxDrivesIS; /* 08h */ 1190 U8 MaxDrivesIM; /* 09h */ 1191 U8 MaxDrivesIME; /* 0Ah */ 1192 U8 Reserved1; /* 0Bh */ 1193 U8 MinDrivesIS; /* 0Ch */ 1194 U8 MinDrivesIM; /* 0Dh */ 1195 U8 MinDrivesIME; /* 0Eh */ 1196 U8 Reserved2; /* 0Fh */ 1197 U8 MaxGlobalHotSpares; /* 10h */ 1198 U8 Reserved3; /* 11h */ 1199 U16 Reserved4; /* 12h */ 1200 U32 Reserved5; /* 14h */ 1201 U32 SupportedStripeSizeMapIS; /* 18h */ 1202 U32 SupportedStripeSizeMapIME; /* 1Ch */ 1203 U32 Reserved6; /* 20h */ 1204 U8 MetadataSize; /* 24h */ 1205 U8 Reserved7; /* 25h */ 1206 U16 Reserved8; /* 26h */ 1207 U16 MaxBadBlockTableEntries; /* 28h */ 1208 U16 Reserved9; /* 2Ah */ 1209 U16 IRNvsramUsage; /* 2Ch */ 1210 U16 Reserved10; /* 2Eh */ 1211 U32 IRNvsramVersion; /* 30h */ 1212 U32 Reserved11; /* 34h */ 1213 U32 Reserved12; /* 38h */ 1214 } CONFIG_PAGE_IOC_6, MPI_POINTER PTR_CONFIG_PAGE_IOC_6, 1215 IOCPage6_t, MPI_POINTER pIOCPage6_t; 1216 1217 #define MPI_IOCPAGE6_PAGEVERSION (0x01) 1218 1219 /* IOC Page 6 Capabilities Flags */ 1220 1221 #define MPI_IOCPAGE6_CAP_FLAGS_SSD_SUPPORT (0x00000020) 1222 #define MPI_IOCPAGE6_CAP_FLAGS_MULTIPORT_DRIVE_SUPPORT (0x00000010) 1223 #define MPI_IOCPAGE6_CAP_FLAGS_DISABLE_SMART_POLLING (0x00000008) 1224 1225 #define MPI_IOCPAGE6_CAP_FLAGS_MASK_METADATA_SIZE (0x00000006) 1226 #define MPI_IOCPAGE6_CAP_FLAGS_64MB_METADATA_SIZE (0x00000000) 1227 #define MPI_IOCPAGE6_CAP_FLAGS_512MB_METADATA_SIZE (0x00000002) 1228 1229 #define MPI_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1230 1231 1232 /**************************************************************************** 1233 * BIOS Config Pages 1234 ****************************************************************************/ 1235 1236 typedef struct _CONFIG_PAGE_BIOS_1 1237 { 1238 CONFIG_PAGE_HEADER Header; /* 00h */ 1239 U32 BiosOptions; /* 04h */ 1240 U32 IOCSettings; /* 08h */ 1241 U32 Reserved1; /* 0Ch */ 1242 U32 DeviceSettings; /* 10h */ 1243 U16 NumberOfDevices; /* 14h */ 1244 U8 ExpanderSpinup; /* 16h */ 1245 U8 Reserved2; /* 17h */ 1246 U16 IOTimeoutBlockDevicesNonRM; /* 18h */ 1247 U16 IOTimeoutSequential; /* 1Ah */ 1248 U16 IOTimeoutOther; /* 1Ch */ 1249 U16 IOTimeoutBlockDevicesRM; /* 1Eh */ 1250 } CONFIG_PAGE_BIOS_1, MPI_POINTER PTR_CONFIG_PAGE_BIOS_1, 1251 BIOSPage1_t, MPI_POINTER pBIOSPage1_t; 1252 1253 #define MPI_BIOSPAGE1_PAGEVERSION (0x03) 1254 1255 /* values for the BiosOptions field */ 1256 #define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE (0x00000400) 1257 #define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE (0x00000200) 1258 #define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE (0x00000100) 1259 1260 #define MPI_BIOSPAGE1_OPTIONS_SCAN_HIGH_TO_LOW (0x00000002) 1261 #define MPI_BIOSPAGE1_OPTIONS_SCAN_LOW_TO_HIGH (0x00000000) 1262 1263 #define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1264 1265 /* values for the IOCSettings field */ 1266 #define MPI_BIOSPAGE1_IOCSET_MASK_INITIAL_SPINUP_DELAY (0x0F000000) 1267 #define MPI_BIOSPAGE1_IOCSET_SHIFT_INITIAL_SPINUP_DELAY (24) 1268 1269 #define MPI_BIOSPAGE1_IOCSET_MASK_PORT_ENABLE_DELAY (0x00F00000) 1270 #define MPI_BIOSPAGE1_IOCSET_SHIFT_PORT_ENABLE_DELAY (20) 1271 1272 #define MPI_BIOSPAGE1_IOCSET_AUTO_PORT_ENABLE (0x00080000) 1273 #define MPI_BIOSPAGE1_IOCSET_DIRECT_ATTACH_SPINUP_MODE (0x00040000) 1274 1275 #define MPI_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1276 #define MPI_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1277 #define MPI_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1278 1279 #define MPI_BIOSPAGE1_IOCSET_MASK_MAX_TARGET_SPIN_UP (0x0000F000) 1280 #define MPI_BIOSPAGE1_IOCSET_SHIFT_MAX_TARGET_SPIN_UP (12) 1281 1282 #define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY (0x00000F00) 1283 #define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY (8) 1284 1285 #define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1286 #define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1287 #define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1288 #define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1289 1290 #define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1291 #define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1292 #define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1293 #define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1294 #define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1295 1296 #define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1297 1298 /* values for the DeviceSettings field */ 1299 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1300 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1301 #define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1302 #define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1303 #define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1304 1305 /* defines for the ExpanderSpinup field */ 1306 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_MAX_TARGET (0xF0) 1307 #define MPI_BIOSPAGE1_EXPSPINUP_SHIFT_MAX_TARGET (4) 1308 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_DELAY (0x0F) 1309 1310 typedef struct _MPI_BOOT_DEVICE_ADAPTER_ORDER 1311 { 1312 U32 Reserved1; /* 00h */ 1313 U32 Reserved2; /* 04h */ 1314 U32 Reserved3; /* 08h */ 1315 U32 Reserved4; /* 0Ch */ 1316 U32 Reserved5; /* 10h */ 1317 U32 Reserved6; /* 14h */ 1318 U32 Reserved7; /* 18h */ 1319 U32 Reserved8; /* 1Ch */ 1320 U32 Reserved9; /* 20h */ 1321 U32 Reserved10; /* 24h */ 1322 U32 Reserved11; /* 28h */ 1323 U32 Reserved12; /* 2Ch */ 1324 U32 Reserved13; /* 30h */ 1325 U32 Reserved14; /* 34h */ 1326 U32 Reserved15; /* 38h */ 1327 U32 Reserved16; /* 3Ch */ 1328 U32 Reserved17; /* 40h */ 1329 } MPI_BOOT_DEVICE_ADAPTER_ORDER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_ORDER; 1330 1331 typedef struct _MPI_BOOT_DEVICE_ADAPTER_NUMBER 1332 { 1333 U8 TargetID; /* 00h */ 1334 U8 Bus; /* 01h */ 1335 U8 AdapterNumber; /* 02h */ 1336 U8 Reserved1; /* 03h */ 1337 U32 Reserved2; /* 04h */ 1338 U32 Reserved3; /* 08h */ 1339 U32 Reserved4; /* 0Ch */ 1340 U8 LUN[8]; /* 10h */ 1341 U32 Reserved5; /* 18h */ 1342 U32 Reserved6; /* 1Ch */ 1343 U32 Reserved7; /* 20h */ 1344 U32 Reserved8; /* 24h */ 1345 U32 Reserved9; /* 28h */ 1346 U32 Reserved10; /* 2Ch */ 1347 U32 Reserved11; /* 30h */ 1348 U32 Reserved12; /* 34h */ 1349 U32 Reserved13; /* 38h */ 1350 U32 Reserved14; /* 3Ch */ 1351 U32 Reserved15; /* 40h */ 1352 } MPI_BOOT_DEVICE_ADAPTER_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_NUMBER; 1353 1354 typedef struct _MPI_BOOT_DEVICE_PCI_ADDRESS 1355 { 1356 U8 TargetID; /* 00h */ 1357 U8 Bus; /* 01h */ 1358 U16 PCIAddress; /* 02h */ 1359 U32 Reserved1; /* 04h */ 1360 U32 Reserved2; /* 08h */ 1361 U32 Reserved3; /* 0Ch */ 1362 U8 LUN[8]; /* 10h */ 1363 U32 Reserved4; /* 18h */ 1364 U32 Reserved5; /* 1Ch */ 1365 U32 Reserved6; /* 20h */ 1366 U32 Reserved7; /* 24h */ 1367 U32 Reserved8; /* 28h */ 1368 U32 Reserved9; /* 2Ch */ 1369 U32 Reserved10; /* 30h */ 1370 U32 Reserved11; /* 34h */ 1371 U32 Reserved12; /* 38h */ 1372 U32 Reserved13; /* 3Ch */ 1373 U32 Reserved14; /* 40h */ 1374 } MPI_BOOT_DEVICE_PCI_ADDRESS, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_ADDRESS; 1375 1376 typedef struct _MPI_BOOT_DEVICE_SLOT_NUMBER 1377 { 1378 U8 TargetID; /* 00h */ 1379 U8 Bus; /* 01h */ 1380 U8 PCISlotNumber; /* 02h */ 1381 U8 Reserved1; /* 03h */ 1382 U32 Reserved2; /* 04h */ 1383 U32 Reserved3; /* 08h */ 1384 U32 Reserved4; /* 0Ch */ 1385 U8 LUN[8]; /* 10h */ 1386 U32 Reserved5; /* 18h */ 1387 U32 Reserved6; /* 1Ch */ 1388 U32 Reserved7; /* 20h */ 1389 U32 Reserved8; /* 24h */ 1390 U32 Reserved9; /* 28h */ 1391 U32 Reserved10; /* 2Ch */ 1392 U32 Reserved11; /* 30h */ 1393 U32 Reserved12; /* 34h */ 1394 U32 Reserved13; /* 38h */ 1395 U32 Reserved14; /* 3Ch */ 1396 U32 Reserved15; /* 40h */ 1397 } MPI_BOOT_DEVICE_PCI_SLOT_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_SLOT_NUMBER; 1398 1399 typedef struct _MPI_BOOT_DEVICE_FC_WWN 1400 { 1401 U64 WWPN; /* 00h */ 1402 U32 Reserved1; /* 08h */ 1403 U32 Reserved2; /* 0Ch */ 1404 U8 LUN[8]; /* 10h */ 1405 U32 Reserved3; /* 18h */ 1406 U32 Reserved4; /* 1Ch */ 1407 U32 Reserved5; /* 20h */ 1408 U32 Reserved6; /* 24h */ 1409 U32 Reserved7; /* 28h */ 1410 U32 Reserved8; /* 2Ch */ 1411 U32 Reserved9; /* 30h */ 1412 U32 Reserved10; /* 34h */ 1413 U32 Reserved11; /* 38h */ 1414 U32 Reserved12; /* 3Ch */ 1415 U32 Reserved13; /* 40h */ 1416 } MPI_BOOT_DEVICE_FC_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_FC_WWN; 1417 1418 typedef struct _MPI_BOOT_DEVICE_SAS_WWN 1419 { 1420 U64 SASAddress; /* 00h */ 1421 U32 Reserved1; /* 08h */ 1422 U32 Reserved2; /* 0Ch */ 1423 U8 LUN[8]; /* 10h */ 1424 U32 Reserved3; /* 18h */ 1425 U32 Reserved4; /* 1Ch */ 1426 U32 Reserved5; /* 20h */ 1427 U32 Reserved6; /* 24h */ 1428 U32 Reserved7; /* 28h */ 1429 U32 Reserved8; /* 2Ch */ 1430 U32 Reserved9; /* 30h */ 1431 U32 Reserved10; /* 34h */ 1432 U32 Reserved11; /* 38h */ 1433 U32 Reserved12; /* 3Ch */ 1434 U32 Reserved13; /* 40h */ 1435 } MPI_BOOT_DEVICE_SAS_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_SAS_WWN; 1436 1437 typedef struct _MPI_BOOT_DEVICE_ENCLOSURE_SLOT 1438 { 1439 U64 EnclosureLogicalID; /* 00h */ 1440 U32 Reserved1; /* 08h */ 1441 U32 Reserved2; /* 0Ch */ 1442 U8 LUN[8]; /* 10h */ 1443 U16 SlotNumber; /* 18h */ 1444 U16 Reserved3; /* 1Ah */ 1445 U32 Reserved4; /* 1Ch */ 1446 U32 Reserved5; /* 20h */ 1447 U32 Reserved6; /* 24h */ 1448 U32 Reserved7; /* 28h */ 1449 U32 Reserved8; /* 2Ch */ 1450 U32 Reserved9; /* 30h */ 1451 U32 Reserved10; /* 34h */ 1452 U32 Reserved11; /* 38h */ 1453 U32 Reserved12; /* 3Ch */ 1454 U32 Reserved13; /* 40h */ 1455 } MPI_BOOT_DEVICE_ENCLOSURE_SLOT, 1456 MPI_POINTER PTR_MPI_BOOT_DEVICE_ENCLOSURE_SLOT; 1457 1458 typedef union _MPI_BIOSPAGE2_BOOT_DEVICE 1459 { 1460 MPI_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1461 MPI_BOOT_DEVICE_ADAPTER_NUMBER AdapterNumber; 1462 MPI_BOOT_DEVICE_PCI_ADDRESS PCIAddress; 1463 MPI_BOOT_DEVICE_PCI_SLOT_NUMBER PCISlotNumber; 1464 MPI_BOOT_DEVICE_FC_WWN FcWwn; 1465 MPI_BOOT_DEVICE_SAS_WWN SasWwn; 1466 MPI_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1467 } MPI_BIOSPAGE2_BOOT_DEVICE, MPI_POINTER PTR_MPI_BIOSPAGE2_BOOT_DEVICE; 1468 1469 typedef struct _CONFIG_PAGE_BIOS_2 1470 { 1471 CONFIG_PAGE_HEADER Header; /* 00h */ 1472 U32 Reserved1; /* 04h */ 1473 U32 Reserved2; /* 08h */ 1474 U32 Reserved3; /* 0Ch */ 1475 U32 Reserved4; /* 10h */ 1476 U32 Reserved5; /* 14h */ 1477 U32 Reserved6; /* 18h */ 1478 U8 BootDeviceForm; /* 1Ch */ 1479 U8 PrevBootDeviceForm; /* 1Ch */ 1480 U16 Reserved8; /* 1Eh */ 1481 MPI_BIOSPAGE2_BOOT_DEVICE BootDevice; /* 20h */ 1482 } CONFIG_PAGE_BIOS_2, MPI_POINTER PTR_CONFIG_PAGE_BIOS_2, 1483 BIOSPage2_t, MPI_POINTER pBIOSPage2_t; 1484 1485 #define MPI_BIOSPAGE2_PAGEVERSION (0x02) 1486 1487 #define MPI_BIOSPAGE2_FORM_MASK (0x0F) 1488 #define MPI_BIOSPAGE2_FORM_ADAPTER_ORDER (0x00) 1489 #define MPI_BIOSPAGE2_FORM_ADAPTER_NUMBER (0x01) 1490 #define MPI_BIOSPAGE2_FORM_PCI_ADDRESS (0x02) 1491 #define MPI_BIOSPAGE2_FORM_PCI_SLOT_NUMBER (0x03) 1492 #define MPI_BIOSPAGE2_FORM_FC_WWN (0x04) 1493 #define MPI_BIOSPAGE2_FORM_SAS_WWN (0x05) 1494 #define MPI_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1495 1496 typedef struct _CONFIG_PAGE_BIOS_4 1497 { 1498 CONFIG_PAGE_HEADER Header; /* 00h */ 1499 U64 ReassignmentBaseWWID; /* 04h */ 1500 } CONFIG_PAGE_BIOS_4, MPI_POINTER PTR_CONFIG_PAGE_BIOS_4, 1501 BIOSPage4_t, MPI_POINTER pBIOSPage4_t; 1502 1503 #define MPI_BIOSPAGE4_PAGEVERSION (0x00) 1504 1505 1506 /**************************************************************************** 1507 * SCSI Port Config Pages 1508 ****************************************************************************/ 1509 1510 typedef struct _CONFIG_PAGE_SCSI_PORT_0 1511 { 1512 CONFIG_PAGE_HEADER Header; /* 00h */ 1513 U32 Capabilities; /* 04h */ 1514 U32 PhysicalInterface; /* 08h */ 1515 } CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0, 1516 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t; 1517 1518 #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x02) 1519 1520 #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001) 1521 #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002) 1522 #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004) 1523 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 1524 #define MPI_SCSIPORTPAGE0_SYNC_ASYNC (0x00) 1525 #define MPI_SCSIPORTPAGE0_SYNC_5 (0x32) 1526 #define MPI_SCSIPORTPAGE0_SYNC_10 (0x19) 1527 #define MPI_SCSIPORTPAGE0_SYNC_20 (0x0C) 1528 #define MPI_SCSIPORTPAGE0_SYNC_33_33 (0x0B) 1529 #define MPI_SCSIPORTPAGE0_SYNC_40 (0x0A) 1530 #define MPI_SCSIPORTPAGE0_SYNC_80 (0x09) 1531 #define MPI_SCSIPORTPAGE0_SYNC_160 (0x08) 1532 #define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN (0xFF) 1533 1534 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD (8) 1535 #define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap) \ 1536 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK) \ 1537 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD \ 1538 ) 1539 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 1540 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET (16) 1541 #define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap) \ 1542 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK) \ 1543 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET \ 1544 ) 1545 #define MPI_SCSIPORTPAGE0_CAP_IDP (0x08000000) 1546 #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000) 1547 #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000) 1548 1549 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003) 1550 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01) 1551 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02) 1552 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03) 1553 #define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000) 1554 #define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24) 1555 #define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE) 1556 #define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF) 1557 1558 1559 typedef struct _CONFIG_PAGE_SCSI_PORT_1 1560 { 1561 CONFIG_PAGE_HEADER Header; /* 00h */ 1562 U32 Configuration; /* 04h */ 1563 U32 OnBusTimerValue; /* 08h */ 1564 U8 TargetConfig; /* 0Ch */ 1565 U8 Reserved1; /* 0Dh */ 1566 U16 IDConfig; /* 0Eh */ 1567 } CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1, 1568 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t; 1569 1570 #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03) 1571 1572 /* Configuration values */ 1573 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF) 1574 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000) 1575 #define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID (16) 1576 1577 /* TargetConfig values */ 1578 #define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01) 1579 #define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG (0x02) 1580 1581 1582 typedef struct _MPI_DEVICE_INFO 1583 { 1584 U8 Timeout; /* 00h */ 1585 U8 SyncFactor; /* 01h */ 1586 U16 DeviceFlags; /* 02h */ 1587 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO, 1588 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t; 1589 1590 typedef struct _CONFIG_PAGE_SCSI_PORT_2 1591 { 1592 CONFIG_PAGE_HEADER Header; /* 00h */ 1593 U32 PortFlags; /* 04h */ 1594 U32 PortSettings; /* 08h */ 1595 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */ 1596 } CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2, 1597 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t; 1598 1599 #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x02) 1600 1601 /* PortFlags values */ 1602 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001) 1603 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004) 1604 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1605 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010) 1606 1607 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK (0x00000060) 1608 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV (0x00000000) 1609 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020) 1610 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060) 1611 1612 1613 /* PortSettings values */ 1614 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F) 1615 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030) 1616 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000) 1617 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010) 1618 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020) 1619 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030) 1620 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0) 1621 #define MPI_SCSIPORTPAGE2_PORT_RM_NONE (0x00000000) 1622 #define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY (0x00000040) 1623 #define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA (0x00000080) 1624 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00) 1625 #define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY (8) 1626 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000) 1627 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000) 1628 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000) 1629 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000) 1630 1631 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001) 1632 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002) 1633 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004) 1634 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008) 1635 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010) 1636 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020) 1637 1638 1639 /**************************************************************************** 1640 * SCSI Target Device Config Pages 1641 ****************************************************************************/ 1642 1643 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0 1644 { 1645 CONFIG_PAGE_HEADER Header; /* 00h */ 1646 U32 NegotiatedParameters; /* 04h */ 1647 U32 Information; /* 08h */ 1648 } CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0, 1649 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t; 1650 1651 #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x04) 1652 1653 #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001) 1654 #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002) 1655 #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004) 1656 #define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008) 1657 #define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010) 1658 #define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020) 1659 #define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040) 1660 #define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080) 1661 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00) 1662 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD (8) 1663 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000) 1664 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET (16) 1665 #define MPI_SCSIDEVPAGE0_NP_IDP (0x08000000) 1666 #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000) 1667 #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000) 1668 1669 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001) 1670 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002) 1671 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004) 1672 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008) 1673 1674 1675 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1 1676 { 1677 CONFIG_PAGE_HEADER Header; /* 00h */ 1678 U32 RequestedParameters; /* 04h */ 1679 U32 Reserved; /* 08h */ 1680 U32 Configuration; /* 0Ch */ 1681 } CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1, 1682 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t; 1683 1684 #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x05) 1685 1686 #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001) 1687 #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002) 1688 #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004) 1689 #define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008) 1690 #define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010) 1691 #define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020) 1692 #define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040) 1693 #define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080) 1694 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 1695 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD (8) 1696 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 1697 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET (16) 1698 #define MPI_SCSIDEVPAGE1_RP_IDP (0x08000000) 1699 #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000) 1700 #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000) 1701 1702 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002) 1703 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004) 1704 #define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008) 1705 #define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010) 1706 1707 1708 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2 1709 { 1710 CONFIG_PAGE_HEADER Header; /* 00h */ 1711 U32 DomainValidation; /* 04h */ 1712 U32 ParityPipeSelect; /* 08h */ 1713 U32 DataPipeSelect; /* 0Ch */ 1714 } CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2, 1715 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t; 1716 1717 #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01) 1718 1719 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010) 1720 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020) 1721 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380) 1722 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00) 1723 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000) 1724 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000) 1725 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000) 1726 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000) 1727 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000) 1728 1729 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003) 1730 1731 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003) 1732 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C) 1733 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030) 1734 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0) 1735 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300) 1736 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00) 1737 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000) 1738 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000) 1739 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000) 1740 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000) 1741 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000) 1742 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000) 1743 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000) 1744 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000) 1745 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000) 1746 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000) 1747 1748 1749 typedef struct _CONFIG_PAGE_SCSI_DEVICE_3 1750 { 1751 CONFIG_PAGE_HEADER Header; /* 00h */ 1752 U16 MsgRejectCount; /* 04h */ 1753 U16 PhaseErrorCount; /* 06h */ 1754 U16 ParityErrorCount; /* 08h */ 1755 U16 Reserved; /* 0Ah */ 1756 } CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3, 1757 SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t; 1758 1759 #define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00) 1760 1761 #define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE) 1762 #define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF) 1763 1764 1765 /**************************************************************************** 1766 * FC Port Config Pages 1767 ****************************************************************************/ 1768 1769 typedef struct _CONFIG_PAGE_FC_PORT_0 1770 { 1771 CONFIG_PAGE_HEADER Header; /* 00h */ 1772 U32 Flags; /* 04h */ 1773 U8 MPIPortNumber; /* 08h */ 1774 U8 LinkType; /* 09h */ 1775 U8 PortState; /* 0Ah */ 1776 U8 Reserved; /* 0Bh */ 1777 U32 PortIdentifier; /* 0Ch */ 1778 U64 WWNN; /* 10h */ 1779 U64 WWPN; /* 18h */ 1780 U32 SupportedServiceClass; /* 20h */ 1781 U32 SupportedSpeeds; /* 24h */ 1782 U32 CurrentSpeed; /* 28h */ 1783 U32 MaxFrameSize; /* 2Ch */ 1784 U64 FabricWWNN; /* 30h */ 1785 U64 FabricWWPN; /* 38h */ 1786 U32 DiscoveredPortsCount; /* 40h */ 1787 U32 MaxInitiators; /* 44h */ 1788 U8 MaxAliasesSupported; /* 48h */ 1789 U8 MaxHardAliasesSupported; /* 49h */ 1790 U8 NumCurrentAliases; /* 4Ah */ 1791 U8 Reserved1; /* 4Bh */ 1792 } CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0, 1793 FCPortPage0_t, MPI_POINTER pFCPortPage0_t; 1794 1795 #define MPI_FCPORTPAGE0_PAGEVERSION (0x02) 1796 1797 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F) 1798 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR) 1799 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET) 1800 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN) 1801 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR) 1802 1803 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010) 1804 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020) 1805 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040) 1806 1807 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00) 1808 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000) 1809 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100) 1810 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200) 1811 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400) 1812 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800) 1813 1814 #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00) 1815 #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01) 1816 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02) 1817 #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03) 1818 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04) 1819 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05) 1820 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06) 1821 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07) 1822 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08) 1823 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09) 1824 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A) 1825 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B) 1826 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C) 1827 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D) 1828 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E) 1829 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F) 1830 1831 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */ 1832 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */ 1833 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */ 1834 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */ 1835 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */ 1836 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */ 1837 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */ 1838 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */ 1839 1840 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001) 1841 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002) 1842 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004) 1843 1844 #define MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN (0x00000000) /* (SNIA)HBA_PORTSPEED_UNKNOWN 0 Unknown - transceiver incapable of reporting */ 1845 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */ 1846 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */ 1847 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */ 1848 #define MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED (0x00000008) /* (SNIA)HBA_PORTSPEED_4GBIT 8 4 GBit/sec */ 1849 1850 #define MPI_FCPORTPAGE0_CURRENT_SPEED_UKNOWN MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN 1851 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED 1852 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED 1853 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED 1854 #define MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED 1855 #define MPI_FCPORTPAGE0_CURRENT_SPEED_NOT_NEGOTIATED (0x00008000) /* (SNIA)HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) Speed not established */ 1856 1857 1858 typedef struct _CONFIG_PAGE_FC_PORT_1 1859 { 1860 CONFIG_PAGE_HEADER Header; /* 00h */ 1861 U32 Flags; /* 04h */ 1862 U64 NoSEEPROMWWNN; /* 08h */ 1863 U64 NoSEEPROMWWPN; /* 10h */ 1864 U8 HardALPA; /* 18h */ 1865 U8 LinkConfig; /* 19h */ 1866 U8 TopologyConfig; /* 1Ah */ 1867 U8 AltConnector; /* 1Bh */ 1868 U8 NumRequestedAliases; /* 1Ch */ 1869 U8 RR_TOV; /* 1Dh */ 1870 U8 InitiatorDeviceTimeout; /* 1Eh */ 1871 U8 InitiatorIoPendTimeout; /* 1Fh */ 1872 } CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1, 1873 FCPortPage1_t, MPI_POINTER pFCPortPage1_t; 1874 1875 #define MPI_FCPORTPAGE1_PAGEVERSION (0x06) 1876 1877 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000) 1878 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000) 1879 #define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000) 1880 #define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000) 1881 #define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000) 1882 #define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE (0x00400000) 1883 #define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK (0x00200000) 1884 #define MPI_FCPORTPAGE1_FLAGS_TARGET_LARGE_CDB_ENABLE (0x00000080) 1885 #define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070) 1886 #define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG (0x00000008) 1887 #define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO (0x00000004) 1888 #define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002) 1889 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001) 1890 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000) 1891 1892 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000) 1893 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28) 1894 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1895 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1896 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1897 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1898 1899 #define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000) 1900 #define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010) 1901 #define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030) 1902 #define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050) 1903 1904 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF) 1905 1906 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F) 1907 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00) 1908 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01) 1909 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02) 1910 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03) 1911 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F) 1912 1913 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F) 1914 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01) 1915 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02) 1916 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F) 1917 1918 #define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00) 1919 1920 #define MPI_FCPORTPAGE1_INITIATOR_DEV_TIMEOUT_MASK (0x7F) 1921 #define MPI_FCPORTPAGE1_INITIATOR_DEV_UNIT_16 (0x80) 1922 1923 1924 typedef struct _CONFIG_PAGE_FC_PORT_2 1925 { 1926 CONFIG_PAGE_HEADER Header; /* 00h */ 1927 U8 NumberActive; /* 04h */ 1928 U8 ALPA[127]; /* 05h */ 1929 } CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2, 1930 FCPortPage2_t, MPI_POINTER pFCPortPage2_t; 1931 1932 #define MPI_FCPORTPAGE2_PAGEVERSION (0x01) 1933 1934 1935 typedef struct _WWN_FORMAT 1936 { 1937 U64 WWNN; /* 00h */ 1938 U64 WWPN; /* 08h */ 1939 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT, 1940 WWNFormat, MPI_POINTER pWWNFormat; 1941 1942 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID 1943 { 1944 WWN_FORMAT WWN; 1945 U32 Did; 1946 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID, 1947 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t; 1948 1949 typedef struct _FC_PORT_PERSISTENT 1950 { 1951 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */ 1952 U8 TargetID; /* 10h */ 1953 U8 Bus; /* 11h */ 1954 U16 Flags; /* 12h */ 1955 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT, 1956 PersistentData_t, MPI_POINTER pPersistentData_t; 1957 1958 #define MPI_PERSISTENT_FLAGS_SHIFT (16) 1959 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001) 1960 #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002) 1961 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004) 1962 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008) 1963 #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080) 1964 1965 /* 1966 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1967 * one and check Header.PageLength at runtime. 1968 */ 1969 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX 1970 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1) 1971 #endif 1972 1973 typedef struct _CONFIG_PAGE_FC_PORT_3 1974 { 1975 CONFIG_PAGE_HEADER Header; /* 00h */ 1976 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */ 1977 } CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3, 1978 FCPortPage3_t, MPI_POINTER pFCPortPage3_t; 1979 1980 #define MPI_FCPORTPAGE3_PAGEVERSION (0x01) 1981 1982 1983 typedef struct _CONFIG_PAGE_FC_PORT_4 1984 { 1985 CONFIG_PAGE_HEADER Header; /* 00h */ 1986 U32 PortFlags; /* 04h */ 1987 U32 PortSettings; /* 08h */ 1988 } CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4, 1989 FCPortPage4_t, MPI_POINTER pFCPortPage4_t; 1990 1991 #define MPI_FCPORTPAGE4_PAGEVERSION (0x00) 1992 1993 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1994 1995 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030) 1996 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000) 1997 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010) 1998 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020) 1999 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030) 2000 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0) 2001 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00) 2002 2003 2004 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO 2005 { 2006 U8 Flags; /* 00h */ 2007 U8 AliasAlpa; /* 01h */ 2008 U16 Reserved; /* 02h */ 2009 U64 AliasWWNN; /* 04h */ 2010 U64 AliasWWPN; /* 0Ch */ 2011 } CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 2012 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 2013 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t; 2014 2015 typedef struct _CONFIG_PAGE_FC_PORT_5 2016 { 2017 CONFIG_PAGE_HEADER Header; /* 00h */ 2018 CONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */ 2019 } CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5, 2020 FCPortPage5_t, MPI_POINTER pFCPortPage5_t; 2021 2022 #define MPI_FCPORTPAGE5_PAGEVERSION (0x02) 2023 2024 #define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01) 2025 #define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02) 2026 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04) 2027 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08) 2028 #define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10) 2029 2030 typedef struct _CONFIG_PAGE_FC_PORT_6 2031 { 2032 CONFIG_PAGE_HEADER Header; /* 00h */ 2033 U32 Reserved; /* 04h */ 2034 U64 TimeSinceReset; /* 08h */ 2035 U64 TxFrames; /* 10h */ 2036 U64 RxFrames; /* 18h */ 2037 U64 TxWords; /* 20h */ 2038 U64 RxWords; /* 28h */ 2039 U64 LipCount; /* 30h */ 2040 U64 NosCount; /* 38h */ 2041 U64 ErrorFrames; /* 40h */ 2042 U64 DumpedFrames; /* 48h */ 2043 U64 LinkFailureCount; /* 50h */ 2044 U64 LossOfSyncCount; /* 58h */ 2045 U64 LossOfSignalCount; /* 60h */ 2046 U64 PrimativeSeqErrCount; /* 68h */ 2047 U64 InvalidTxWordCount; /* 70h */ 2048 U64 InvalidCrcCount; /* 78h */ 2049 U64 FcpInitiatorIoCount; /* 80h */ 2050 } CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6, 2051 FCPortPage6_t, MPI_POINTER pFCPortPage6_t; 2052 2053 #define MPI_FCPORTPAGE6_PAGEVERSION (0x00) 2054 2055 2056 typedef struct _CONFIG_PAGE_FC_PORT_7 2057 { 2058 CONFIG_PAGE_HEADER Header; /* 00h */ 2059 U32 Reserved; /* 04h */ 2060 U8 PortSymbolicName[256]; /* 08h */ 2061 } CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7, 2062 FCPortPage7_t, MPI_POINTER pFCPortPage7_t; 2063 2064 #define MPI_FCPORTPAGE7_PAGEVERSION (0x00) 2065 2066 2067 typedef struct _CONFIG_PAGE_FC_PORT_8 2068 { 2069 CONFIG_PAGE_HEADER Header; /* 00h */ 2070 U32 BitVector[8]; /* 04h */ 2071 } CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8, 2072 FCPortPage8_t, MPI_POINTER pFCPortPage8_t; 2073 2074 #define MPI_FCPORTPAGE8_PAGEVERSION (0x00) 2075 2076 2077 typedef struct _CONFIG_PAGE_FC_PORT_9 2078 { 2079 CONFIG_PAGE_HEADER Header; /* 00h */ 2080 U32 Reserved; /* 04h */ 2081 U64 GlobalWWPN; /* 08h */ 2082 U64 GlobalWWNN; /* 10h */ 2083 U32 UnitType; /* 18h */ 2084 U32 PhysicalPortNumber; /* 1Ch */ 2085 U32 NumAttachedNodes; /* 20h */ 2086 U16 IPVersion; /* 24h */ 2087 U16 UDPPortNumber; /* 26h */ 2088 U8 IPAddress[16]; /* 28h */ 2089 U16 Reserved1; /* 38h */ 2090 U16 TopologyDiscoveryFlags; /* 3Ah */ 2091 } CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9, 2092 FCPortPage9_t, MPI_POINTER pFCPortPage9_t; 2093 2094 #define MPI_FCPORTPAGE9_PAGEVERSION (0x00) 2095 2096 2097 typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA 2098 { 2099 U8 Id; /* 10h */ 2100 U8 ExtId; /* 11h */ 2101 U8 Connector; /* 12h */ 2102 U8 Transceiver[8]; /* 13h */ 2103 U8 Encoding; /* 1Bh */ 2104 U8 BitRate_100mbs; /* 1Ch */ 2105 U8 Reserved1; /* 1Dh */ 2106 U8 Length9u_km; /* 1Eh */ 2107 U8 Length9u_100m; /* 1Fh */ 2108 U8 Length50u_10m; /* 20h */ 2109 U8 Length62p5u_10m; /* 21h */ 2110 U8 LengthCopper_m; /* 22h */ 2111 U8 Reseverved2; /* 22h */ 2112 U8 VendorName[16]; /* 24h */ 2113 U8 Reserved3; /* 34h */ 2114 U8 VendorOUI[3]; /* 35h */ 2115 U8 VendorPN[16]; /* 38h */ 2116 U8 VendorRev[4]; /* 48h */ 2117 U16 Wavelength; /* 4Ch */ 2118 U8 Reserved4; /* 4Eh */ 2119 U8 CC_BASE; /* 4Fh */ 2120 } CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA, 2121 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA, 2122 FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t; 2123 2124 #define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00) 2125 #define MPI_FCPORT10_BASE_ID_GBIC (0x01) 2126 #define MPI_FCPORT10_BASE_ID_FIXED (0x02) 2127 #define MPI_FCPORT10_BASE_ID_SFP (0x03) 2128 #define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04) 2129 #define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F) 2130 #define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80) 2131 2132 #define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00) 2133 #define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01) 2134 #define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02) 2135 #define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03) 2136 #define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04) 2137 #define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05) 2138 #define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06) 2139 #define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07) 2140 #define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80) 2141 2142 #define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00) 2143 #define MPI_FCPORT10_BASE_CONN_SC (0x01) 2144 #define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02) 2145 #define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03) 2146 #define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04) 2147 #define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05) 2148 #define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06) 2149 #define MPI_FCPORT10_BASE_CONN_LC (0x07) 2150 #define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08) 2151 #define MPI_FCPORT10_BASE_CONN_MU (0x09) 2152 #define MPI_FCPORT10_BASE_CONN_SG (0x0A) 2153 #define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B) 2154 #define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C) 2155 #define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F) 2156 #define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20) 2157 #define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21) 2158 #define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22) 2159 #define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F) 2160 #define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80) 2161 2162 #define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00) 2163 #define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01) 2164 #define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02) 2165 #define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03) 2166 #define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04) 2167 2168 2169 typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA 2170 { 2171 U8 Options[2]; /* 50h */ 2172 U8 BitRateMax; /* 52h */ 2173 U8 BitRateMin; /* 53h */ 2174 U8 VendorSN[16]; /* 54h */ 2175 U8 DateCode[8]; /* 64h */ 2176 U8 DiagMonitoringType; /* 6Ch */ 2177 U8 EnhancedOptions; /* 6Dh */ 2178 U8 SFF8472Compliance; /* 6Eh */ 2179 U8 CC_EXT; /* 6Fh */ 2180 } CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA, 2181 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA, 2182 FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t; 2183 2184 #define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20) 2185 #define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10) 2186 #define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08) 2187 #define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04) 2188 #define MPI_FCPORT10_EXT_OPTION1_LOS (0x02) 2189 2190 2191 typedef struct _CONFIG_PAGE_FC_PORT_10 2192 { 2193 CONFIG_PAGE_HEADER Header; /* 00h */ 2194 U8 Flags; /* 04h */ 2195 U8 Reserved1; /* 05h */ 2196 U16 Reserved2; /* 06h */ 2197 U32 HwConfig1; /* 08h */ 2198 U32 HwConfig2; /* 0Ch */ 2199 CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */ 2200 CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */ 2201 U8 VendorSpecific[32]; /* 70h */ 2202 } CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10, 2203 FCPortPage10_t, MPI_POINTER pFCPortPage10_t; 2204 2205 #define MPI_FCPORTPAGE10_PAGEVERSION (0x01) 2206 2207 /* standard MODDEF pin definitions (from GBIC spec.) */ 2208 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007) 2209 #define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001) 2210 #define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002) 2211 #define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004) 2212 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007) 2213 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006) 2214 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005) 2215 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004) 2216 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003) 2217 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002) 2218 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001) 2219 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000) 2220 2221 #define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010) 2222 #define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020) 2223 2224 2225 /**************************************************************************** 2226 * FC Device Config Pages 2227 ****************************************************************************/ 2228 2229 typedef struct _CONFIG_PAGE_FC_DEVICE_0 2230 { 2231 CONFIG_PAGE_HEADER Header; /* 00h */ 2232 U64 WWNN; /* 04h */ 2233 U64 WWPN; /* 0Ch */ 2234 U32 PortIdentifier; /* 14h */ 2235 U8 Protocol; /* 18h */ 2236 U8 Flags; /* 19h */ 2237 U16 BBCredit; /* 1Ah */ 2238 U16 MaxRxFrameSize; /* 1Ch */ 2239 U8 ADISCHardALPA; /* 1Eh */ 2240 U8 PortNumber; /* 1Fh */ 2241 U8 FcPhLowestVersion; /* 20h */ 2242 U8 FcPhHighestVersion; /* 21h */ 2243 U8 CurrentTargetID; /* 22h */ 2244 U8 CurrentBus; /* 23h */ 2245 } CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0, 2246 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t; 2247 2248 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x03) 2249 2250 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01) 2251 #define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02) 2252 #define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04) 2253 2254 #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01) 2255 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02) 2256 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04) 2257 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY (0x08) 2258 2259 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK) 2260 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK) 2261 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) 2262 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID) 2263 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK) 2264 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK) 2265 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT) 2266 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK) 2267 2268 #define MPI_FC_DEVICE_PAGE0_HARD_ALPA_UNKNOWN (0xFF) 2269 2270 /**************************************************************************** 2271 * RAID Volume Config Pages 2272 ****************************************************************************/ 2273 2274 typedef struct _RAID_VOL0_PHYS_DISK 2275 { 2276 U16 Reserved; /* 00h */ 2277 U8 PhysDiskMap; /* 02h */ 2278 U8 PhysDiskNum; /* 03h */ 2279 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK, 2280 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t; 2281 2282 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 2283 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 2284 2285 typedef struct _RAID_VOL0_STATUS 2286 { 2287 U8 Flags; /* 00h */ 2288 U8 State; /* 01h */ 2289 U16 Reserved; /* 02h */ 2290 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS, 2291 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t; 2292 2293 /* RAID Volume Page 0 VolumeStatus defines */ 2294 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01) 2295 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02) 2296 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04) 2297 #define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08) 2298 #define MPI_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x10) 2299 2300 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00) 2301 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01) 2302 #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02) 2303 #define MPI_RAIDVOL0_STATUS_STATE_MISSING (0x03) 2304 2305 typedef struct _RAID_VOL0_SETTINGS 2306 { 2307 U16 Settings; /* 00h */ 2308 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 2309 U8 Reserved; /* 02h */ 2310 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS, 2311 RaidVol0Settings, MPI_POINTER pRaidVol0Settings; 2312 2313 /* RAID Volume Page 0 VolumeSettings defines */ 2314 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001) 2315 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002) 2316 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004) 2317 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008) 2318 #define MPI_RAIDVOL0_SETTING_FAST_DATA_SCRUBBING_0102 (0x0020) /* obsolete */ 2319 2320 #define MPI_RAIDVOL0_SETTING_MASK_METADATA_SIZE (0x00C0) 2321 #define MPI_RAIDVOL0_SETTING_64MB_METADATA_SIZE (0x0000) 2322 #define MPI_RAIDVOL0_SETTING_512MB_METADATA_SIZE (0x0040) 2323 2324 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010) 2325 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000) 2326 2327 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 2328 #define MPI_RAID_HOT_SPARE_POOL_0 (0x01) 2329 #define MPI_RAID_HOT_SPARE_POOL_1 (0x02) 2330 #define MPI_RAID_HOT_SPARE_POOL_2 (0x04) 2331 #define MPI_RAID_HOT_SPARE_POOL_3 (0x08) 2332 #define MPI_RAID_HOT_SPARE_POOL_4 (0x10) 2333 #define MPI_RAID_HOT_SPARE_POOL_5 (0x20) 2334 #define MPI_RAID_HOT_SPARE_POOL_6 (0x40) 2335 #define MPI_RAID_HOT_SPARE_POOL_7 (0x80) 2336 2337 /* 2338 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2339 * one and check Header.PageLength at runtime. 2340 */ 2341 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX 2342 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 2343 #endif 2344 2345 typedef struct _CONFIG_PAGE_RAID_VOL_0 2346 { 2347 CONFIG_PAGE_HEADER Header; /* 00h */ 2348 U8 VolumeID; /* 04h */ 2349 U8 VolumeBus; /* 05h */ 2350 U8 VolumeIOC; /* 06h */ 2351 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */ 2352 RAID_VOL0_STATUS VolumeStatus; /* 08h */ 2353 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */ 2354 U32 MaxLBA; /* 10h */ 2355 U32 MaxLBAHigh; /* 14h */ 2356 U32 StripeSize; /* 18h */ 2357 U32 Reserved2; /* 1Ch */ 2358 U32 Reserved3; /* 20h */ 2359 U8 NumPhysDisks; /* 24h */ 2360 U8 DataScrubRate; /* 25h */ 2361 U8 ResyncRate; /* 26h */ 2362 U8 InactiveStatus; /* 27h */ 2363 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */ 2364 } CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0, 2365 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t; 2366 2367 #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x07) 2368 2369 /* values for RAID Volume Page 0 InactiveStatus field */ 2370 #define MPI_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 2371 #define MPI_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 2372 #define MPI_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 2373 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 2374 #define MPI_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 2375 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 2376 #define MPI_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 2377 2378 2379 typedef struct _CONFIG_PAGE_RAID_VOL_1 2380 { 2381 CONFIG_PAGE_HEADER Header; /* 00h */ 2382 U8 VolumeID; /* 04h */ 2383 U8 VolumeBus; /* 05h */ 2384 U8 VolumeIOC; /* 06h */ 2385 U8 Reserved0; /* 07h */ 2386 U8 GUID[24]; /* 08h */ 2387 U8 Name[32]; /* 20h */ 2388 U64 WWID; /* 40h */ 2389 U32 Reserved1; /* 48h */ 2390 U32 Reserved2; /* 4Ch */ 2391 } CONFIG_PAGE_RAID_VOL_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_1, 2392 RaidVolumePage1_t, MPI_POINTER pRaidVolumePage1_t; 2393 2394 #define MPI_RAIDVOLPAGE1_PAGEVERSION (0x01) 2395 2396 2397 /**************************************************************************** 2398 * RAID Physical Disk Config Pages 2399 ****************************************************************************/ 2400 2401 typedef struct _RAID_PHYS_DISK0_ERROR_DATA 2402 { 2403 U8 ErrorCdbByte; /* 00h */ 2404 U8 ErrorSenseKey; /* 01h */ 2405 U16 Reserved; /* 02h */ 2406 U16 ErrorCount; /* 04h */ 2407 U8 ErrorASC; /* 06h */ 2408 U8 ErrorASCQ; /* 07h */ 2409 U16 SmartCount; /* 08h */ 2410 U8 SmartASC; /* 0Ah */ 2411 U8 SmartASCQ; /* 0Bh */ 2412 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA, 2413 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t; 2414 2415 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA 2416 { 2417 U8 VendorID[8]; /* 00h */ 2418 U8 ProductID[16]; /* 08h */ 2419 U8 ProductRevLevel[4]; /* 18h */ 2420 U8 Info[32]; /* 1Ch */ 2421 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA, 2422 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData; 2423 2424 typedef struct _RAID_PHYS_DISK0_SETTINGS 2425 { 2426 U8 SepID; /* 00h */ 2427 U8 SepBus; /* 01h */ 2428 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 2429 U8 PhysDiskSettings; /* 03h */ 2430 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS, 2431 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t; 2432 2433 typedef struct _RAID_PHYS_DISK0_STATUS 2434 { 2435 U8 Flags; /* 00h */ 2436 U8 State; /* 01h */ 2437 U16 Reserved; /* 02h */ 2438 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS, 2439 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t; 2440 2441 /* RAID Physical Disk PhysDiskStatus flags */ 2442 2443 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01) 2444 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02) 2445 #define MPI_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x04) 2446 #define MPI_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00) 2447 #define MPI_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x08) 2448 2449 #define MPI_PHYSDISK0_STATUS_ONLINE (0x00) 2450 #define MPI_PHYSDISK0_STATUS_MISSING (0x01) 2451 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02) 2452 #define MPI_PHYSDISK0_STATUS_FAILED (0x03) 2453 #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04) 2454 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05) 2455 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06) 2456 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF) 2457 2458 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0 2459 { 2460 CONFIG_PAGE_HEADER Header; /* 00h */ 2461 U8 PhysDiskID; /* 04h */ 2462 U8 PhysDiskBus; /* 05h */ 2463 U8 PhysDiskIOC; /* 06h */ 2464 U8 PhysDiskNum; /* 07h */ 2465 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */ 2466 U32 Reserved1; /* 0Ch */ 2467 U8 ExtDiskIdentifier[8]; /* 10h */ 2468 U8 DiskIdentifier[16]; /* 18h */ 2469 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */ 2470 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */ 2471 U32 MaxLBA; /* 68h */ 2472 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */ 2473 } CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0, 2474 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t; 2475 2476 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x02) 2477 2478 2479 typedef struct _RAID_PHYS_DISK1_PATH 2480 { 2481 U8 PhysDiskID; /* 00h */ 2482 U8 PhysDiskBus; /* 01h */ 2483 U16 Reserved1; /* 02h */ 2484 U64 WWID; /* 04h */ 2485 U64 OwnerWWID; /* 0Ch */ 2486 U8 OwnerIdentifier; /* 14h */ 2487 U8 Reserved2; /* 15h */ 2488 U16 Flags; /* 16h */ 2489 } RAID_PHYS_DISK1_PATH, MPI_POINTER PTR_RAID_PHYS_DISK1_PATH, 2490 RaidPhysDisk1Path_t, MPI_POINTER pRaidPhysDisk1Path_t; 2491 2492 /* RAID Physical Disk Page 1 Flags field defines */ 2493 #define MPI_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 2494 #define MPI_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 2495 2496 2497 /* 2498 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2499 * one and check Header.PageLength or NumPhysDiskPaths at runtime. 2500 */ 2501 #ifndef MPI_RAID_PHYS_DISK1_PATH_MAX 2502 #define MPI_RAID_PHYS_DISK1_PATH_MAX (1) 2503 #endif 2504 2505 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_1 2506 { 2507 CONFIG_PAGE_HEADER Header; /* 00h */ 2508 U8 NumPhysDiskPaths; /* 04h */ 2509 U8 PhysDiskNum; /* 05h */ 2510 U16 Reserved2; /* 06h */ 2511 U32 Reserved1; /* 08h */ 2512 RAID_PHYS_DISK1_PATH Path[MPI_RAID_PHYS_DISK1_PATH_MAX];/* 0Ch */ 2513 } CONFIG_PAGE_RAID_PHYS_DISK_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_1, 2514 RaidPhysDiskPage1_t, MPI_POINTER pRaidPhysDiskPage1_t; 2515 2516 #define MPI_RAIDPHYSDISKPAGE1_PAGEVERSION (0x00) 2517 2518 2519 /**************************************************************************** 2520 * LAN Config Pages 2521 ****************************************************************************/ 2522 2523 typedef struct _CONFIG_PAGE_LAN_0 2524 { 2525 ConfigPageHeader_t Header; /* 00h */ 2526 U16 TxRxModes; /* 04h */ 2527 U16 Reserved; /* 06h */ 2528 U32 PacketPrePad; /* 08h */ 2529 } CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0, 2530 LANPage0_t, MPI_POINTER pLANPage0_t; 2531 2532 #define MPI_LAN_PAGE0_PAGEVERSION (0x01) 2533 2534 #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000) 2535 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001) 2536 #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001) 2537 2538 typedef struct _CONFIG_PAGE_LAN_1 2539 { 2540 ConfigPageHeader_t Header; /* 00h */ 2541 U16 Reserved; /* 04h */ 2542 U8 CurrentDeviceState; /* 06h */ 2543 U8 Reserved1; /* 07h */ 2544 U32 MinPacketSize; /* 08h */ 2545 U32 MaxPacketSize; /* 0Ch */ 2546 U32 HardwareAddressLow; /* 10h */ 2547 U32 HardwareAddressHigh; /* 14h */ 2548 U32 MaxWireSpeedLow; /* 18h */ 2549 U32 MaxWireSpeedHigh; /* 1Ch */ 2550 U32 BucketsRemaining; /* 20h */ 2551 U32 MaxReplySize; /* 24h */ 2552 U32 NegWireSpeedLow; /* 28h */ 2553 U32 NegWireSpeedHigh; /* 2Ch */ 2554 } CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1, 2555 LANPage1_t, MPI_POINTER pLANPage1_t; 2556 2557 #define MPI_LAN_PAGE1_PAGEVERSION (0x03) 2558 2559 #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00) 2560 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01) 2561 2562 2563 /**************************************************************************** 2564 * Inband Config Pages 2565 ****************************************************************************/ 2566 2567 typedef struct _CONFIG_PAGE_INBAND_0 2568 { 2569 CONFIG_PAGE_HEADER Header; /* 00h */ 2570 MPI_VERSION_FORMAT InbandVersion; /* 04h */ 2571 U16 MaximumBuffers; /* 08h */ 2572 U16 Reserved1; /* 0Ah */ 2573 } CONFIG_PAGE_INBAND_0, MPI_POINTER PTR_CONFIG_PAGE_INBAND_0, 2574 InbandPage0_t, MPI_POINTER pInbandPage0_t; 2575 2576 #define MPI_INBAND_PAGEVERSION (0x00) 2577 2578 2579 2580 /**************************************************************************** 2581 * SAS IO Unit Config Pages 2582 ****************************************************************************/ 2583 2584 typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA 2585 { 2586 U8 Port; /* 00h */ 2587 U8 PortFlags; /* 01h */ 2588 U8 PhyFlags; /* 02h */ 2589 U8 NegotiatedLinkRate; /* 03h */ 2590 U32 ControllerPhyDeviceInfo;/* 04h */ 2591 U16 AttachedDeviceHandle; /* 08h */ 2592 U16 ControllerDevHandle; /* 0Ah */ 2593 U32 DiscoveryStatus; /* 0Ch */ 2594 } MPI_SAS_IO_UNIT0_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT0_PHY_DATA, 2595 SasIOUnit0PhyData, MPI_POINTER pSasIOUnit0PhyData; 2596 2597 /* 2598 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2599 * one and check Header.PageLength at runtime. 2600 */ 2601 #ifndef MPI_SAS_IOUNIT0_PHY_MAX 2602 #define MPI_SAS_IOUNIT0_PHY_MAX (1) 2603 #endif 2604 2605 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_0 2606 { 2607 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2608 U16 NvdataVersionDefault; /* 08h */ 2609 U16 NvdataVersionPersistent; /* 0Ah */ 2610 U8 NumPhys; /* 0Ch */ 2611 U8 Reserved2; /* 0Dh */ 2612 U16 Reserved3; /* 0Eh */ 2613 MPI_SAS_IO_UNIT0_PHY_DATA PhyData[MPI_SAS_IOUNIT0_PHY_MAX]; /* 10h */ 2614 } CONFIG_PAGE_SAS_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_0, 2615 SasIOUnitPage0_t, MPI_POINTER pSasIOUnitPage0_t; 2616 2617 #define MPI_SASIOUNITPAGE0_PAGEVERSION (0x04) 2618 2619 /* values for SAS IO Unit Page 0 PortFlags */ 2620 #define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS (0x08) 2621 #define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM (0x00) 2622 #define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM (0x04) 2623 #define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2624 2625 /* values for SAS IO Unit Page 0 PhyFlags */ 2626 #define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED (0x04) 2627 #define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT (0x02) 2628 #define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT (0x01) 2629 2630 /* values for SAS IO Unit Page 0 NegotiatedLinkRate */ 2631 #define MPI_SAS_IOUNIT0_RATE_UNKNOWN (0x00) 2632 #define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED (0x01) 2633 #define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION (0x02) 2634 #define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE (0x03) 2635 #define MPI_SAS_IOUNIT0_RATE_1_5 (0x08) 2636 #define MPI_SAS_IOUNIT0_RATE_3_0 (0x09) 2637 #define MPI_SAS_IOUNIT0_RATE_6_0 (0x0A) 2638 2639 /* see mpi_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 2640 2641 /* values for SAS IO Unit Page 0 DiscoveryStatus */ 2642 #define MPI_SAS_IOUNIT0_DS_LOOP_DETECTED (0x00000001) 2643 #define MPI_SAS_IOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2644 #define MPI_SAS_IOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2645 #define MPI_SAS_IOUNIT0_DS_EXPANDER_ERR (0x00000008) 2646 #define MPI_SAS_IOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2647 #define MPI_SAS_IOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2648 #define MPI_SAS_IOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2649 #define MPI_SAS_IOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2650 #define MPI_SAS_IOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2651 #define MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2652 #define MPI_SAS_IOUNIT0_DS_TABLE_LINK (0x00000400) 2653 #define MPI_SAS_IOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2654 #define MPI_SAS_IOUNIT0_DS_MAX_SATA_TARGETS (0x00001000) 2655 #define MPI_SAS_IOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 2656 2657 2658 typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA 2659 { 2660 U8 Port; /* 00h */ 2661 U8 PortFlags; /* 01h */ 2662 U8 PhyFlags; /* 02h */ 2663 U8 MaxMinLinkRate; /* 03h */ 2664 U32 ControllerPhyDeviceInfo; /* 04h */ 2665 U16 MaxTargetPortConnectTime; /* 08h */ 2666 U16 Reserved1; /* 0Ah */ 2667 } MPI_SAS_IO_UNIT1_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT1_PHY_DATA, 2668 SasIOUnit1PhyData, MPI_POINTER pSasIOUnit1PhyData; 2669 2670 /* 2671 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2672 * one and check Header.PageLength at runtime. 2673 */ 2674 #ifndef MPI_SAS_IOUNIT1_PHY_MAX 2675 #define MPI_SAS_IOUNIT1_PHY_MAX (1) 2676 #endif 2677 2678 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_1 2679 { 2680 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2681 U16 ControlFlags; /* 08h */ 2682 U16 MaxNumSATATargets; /* 0Ah */ 2683 U16 AdditionalControlFlags; /* 0Ch */ 2684 U16 Reserved1; /* 0Eh */ 2685 U8 NumPhys; /* 10h */ 2686 U8 SATAMaxQDepth; /* 11h */ 2687 U8 ReportDeviceMissingDelay; /* 12h */ 2688 U8 IODeviceMissingDelay; /* 13h */ 2689 MPI_SAS_IO_UNIT1_PHY_DATA PhyData[MPI_SAS_IOUNIT1_PHY_MAX]; /* 14h */ 2690 } CONFIG_PAGE_SAS_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_1, 2691 SasIOUnitPage1_t, MPI_POINTER pSasIOUnitPage1_t; 2692 2693 #define MPI_SASIOUNITPAGE1_PAGEVERSION (0x07) 2694 2695 /* values for SAS IO Unit Page 1 ControlFlags */ 2696 #define MPI_SAS_IOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2697 #define MPI_SAS_IOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2698 #define MPI_SAS_IOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 2699 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2700 #define MPI_SAS_IOUNIT1_CONTROL_DISABLE_SAS_HASH (0x0800) 2701 2702 #define MPI_SAS_IOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2703 #define MPI_SAS_IOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2704 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x00) 2705 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x01) 2706 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x02) 2707 2708 #define MPI_SAS_IOUNIT1_CONTROL_POSTPONE_SATA_INIT (0x0100) 2709 #define MPI_SAS_IOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2710 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2711 #define MPI_SAS_IOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2712 #define MPI_SAS_IOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2713 #define MPI_SAS_IOUNIT1_CONTROL_PHY_ENABLE_ORDER_HIGH (0x0008) 2714 #define MPI_SAS_IOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2715 #define MPI_SAS_IOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2716 #define MPI_SAS_IOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 2717 2718 /* values for SAS IO Unit Page 1 AdditionalControlFlags */ 2719 #define MPI_SAS_IOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2720 #define MPI_SAS_IOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2721 #define MPI_SAS_IOUNIT1_ACONTROL_HIDE_NONZERO_ATTACHED_PHY_IDENT (0x0020) 2722 #define MPI_SAS_IOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2723 #define MPI_SAS_IOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2724 #define MPI_SAS_IOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2725 #define MPI_SAS_IOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2726 #define MPI_SAS_IOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2727 2728 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2729 #define MPI_SAS_IOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2730 #define MPI_SAS_IOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2731 2732 /* values for SAS IO Unit Page 1 PortFlags */ 2733 #define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM (0x00) 2734 #define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM (0x04) 2735 #define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2736 2737 /* values for SAS IO Unit Page 0 PhyFlags */ 2738 #define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE (0x04) 2739 #define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT (0x02) 2740 #define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT (0x01) 2741 2742 /* values for SAS IO Unit Page 0 MaxMinLinkRate */ 2743 #define MPI_SAS_IOUNIT1_MAX_RATE_MASK (0xF0) 2744 #define MPI_SAS_IOUNIT1_MAX_RATE_1_5 (0x80) 2745 #define MPI_SAS_IOUNIT1_MAX_RATE_3_0 (0x90) 2746 #define MPI_SAS_IOUNIT1_MIN_RATE_MASK (0x0F) 2747 #define MPI_SAS_IOUNIT1_MIN_RATE_1_5 (0x08) 2748 #define MPI_SAS_IOUNIT1_MIN_RATE_3_0 (0x09) 2749 2750 /* see mpi_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2751 2752 2753 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_2 2754 { 2755 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2756 U8 NumDevsPerEnclosure; /* 08h */ 2757 U8 BootDeviceWaitTime; /* 09h */ 2758 U16 Reserved2; /* 0Ah */ 2759 U16 MaxPersistentIDs; /* 0Ch */ 2760 U16 NumPersistentIDsUsed; /* 0Eh */ 2761 U8 Status; /* 10h */ 2762 U8 Flags; /* 11h */ 2763 U16 MaxNumPhysicalMappedIDs;/* 12h */ 2764 } CONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2, 2765 SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t; 2766 2767 #define MPI_SASIOUNITPAGE2_PAGEVERSION (0x07) 2768 2769 /* values for SAS IO Unit Page 2 Status field */ 2770 #define MPI_SAS_IOUNIT2_STATUS_DEVICE_LIMIT_EXCEEDED (0x08) 2771 #define MPI_SAS_IOUNIT2_STATUS_ENCLOSURE_DEVICES_UNMAPPED (0x04) 2772 #define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS (0x02) 2773 #define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS (0x01) 2774 2775 /* values for SAS IO Unit Page 2 Flags field */ 2776 #define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS (0x01) 2777 /* Physical Mapping Modes */ 2778 #define MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE (0x0E) 2779 #define MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE (1) 2780 #define MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP (0x00) 2781 #define MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP (0x01) 2782 #define MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP (0x02) 2783 #define MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP (0x07) 2784 2785 #define MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT (0x10) 2786 #define MPI_SAS_IOUNIT2_FLAGS_DA_STARTING_SLOT (0x20) 2787 2788 2789 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_3 2790 { 2791 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2792 U32 Reserved1; /* 08h */ 2793 U32 MaxInvalidDwordCount; /* 0Ch */ 2794 U32 InvalidDwordCountTime; /* 10h */ 2795 U32 MaxRunningDisparityErrorCount; /* 14h */ 2796 U32 RunningDisparityErrorTime; /* 18h */ 2797 U32 MaxLossDwordSynchCount; /* 1Ch */ 2798 U32 LossDwordSynchCountTime; /* 20h */ 2799 U32 MaxPhyResetProblemCount; /* 24h */ 2800 U32 PhyResetProblemTime; /* 28h */ 2801 } CONFIG_PAGE_SAS_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_3, 2802 SasIOUnitPage3_t, MPI_POINTER pSasIOUnitPage3_t; 2803 2804 #define MPI_SASIOUNITPAGE3_PAGEVERSION (0x00) 2805 2806 2807 /**************************************************************************** 2808 * SAS Expander Config Pages 2809 ****************************************************************************/ 2810 2811 typedef struct _CONFIG_PAGE_SAS_EXPANDER_0 2812 { 2813 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2814 U8 PhysicalPort; /* 08h */ 2815 U8 Reserved1; /* 09h */ 2816 U16 EnclosureHandle; /* 0Ah */ 2817 U64 SASAddress; /* 0Ch */ 2818 U32 DiscoveryStatus; /* 14h */ 2819 U16 DevHandle; /* 18h */ 2820 U16 ParentDevHandle; /* 1Ah */ 2821 U16 ExpanderChangeCount; /* 1Ch */ 2822 U16 ExpanderRouteIndexes; /* 1Eh */ 2823 U8 NumPhys; /* 20h */ 2824 U8 SASLevel; /* 21h */ 2825 U8 Flags; /* 22h */ 2826 U8 Reserved3; /* 23h */ 2827 } CONFIG_PAGE_SAS_EXPANDER_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_0, 2828 SasExpanderPage0_t, MPI_POINTER pSasExpanderPage0_t; 2829 2830 #define MPI_SASEXPANDER0_PAGEVERSION (0x03) 2831 2832 /* values for SAS Expander Page 0 DiscoveryStatus field */ 2833 #define MPI_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2834 #define MPI_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2835 #define MPI_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2836 #define MPI_SAS_EXPANDER0_DS_EXPANDER_ERR (0x00000008) 2837 #define MPI_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2838 #define MPI_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2839 #define MPI_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2840 #define MPI_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2841 #define MPI_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2842 #define MPI_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2843 #define MPI_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2844 #define MPI_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2845 2846 /* values for SAS Expander Page 0 Flags field */ 2847 #define MPI_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x04) 2848 #define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x02) 2849 #define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x01) 2850 2851 2852 typedef struct _CONFIG_PAGE_SAS_EXPANDER_1 2853 { 2854 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2855 U8 PhysicalPort; /* 08h */ 2856 U8 Reserved1; /* 09h */ 2857 U16 Reserved2; /* 0Ah */ 2858 U8 NumPhys; /* 0Ch */ 2859 U8 Phy; /* 0Dh */ 2860 U16 NumTableEntriesProgrammed; /* 0Eh */ 2861 U8 ProgrammedLinkRate; /* 10h */ 2862 U8 HwLinkRate; /* 11h */ 2863 U16 AttachedDevHandle; /* 12h */ 2864 U32 PhyInfo; /* 14h */ 2865 U32 AttachedDeviceInfo; /* 18h */ 2866 U16 OwnerDevHandle; /* 1Ch */ 2867 U8 ChangeCount; /* 1Eh */ 2868 U8 NegotiatedLinkRate; /* 1Fh */ 2869 U8 PhyIdentifier; /* 20h */ 2870 U8 AttachedPhyIdentifier; /* 21h */ 2871 U8 Reserved3; /* 22h */ 2872 U8 DiscoveryInfo; /* 23h */ 2873 U32 Reserved4; /* 24h */ 2874 } CONFIG_PAGE_SAS_EXPANDER_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_1, 2875 SasExpanderPage1_t, MPI_POINTER pSasExpanderPage1_t; 2876 2877 #define MPI_SASEXPANDER1_PAGEVERSION (0x01) 2878 2879 /* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */ 2880 2881 /* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */ 2882 2883 /* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */ 2884 2885 /* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */ 2886 2887 /* values for SAS Expander Page 1 DiscoveryInfo field */ 2888 #define MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2889 #define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2890 #define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2891 2892 /* values for SAS Expander Page 1 NegotiatedLinkRate field */ 2893 #define MPI_SAS_EXPANDER1_NEG_RATE_UNKNOWN (0x00) 2894 #define MPI_SAS_EXPANDER1_NEG_RATE_PHY_DISABLED (0x01) 2895 #define MPI_SAS_EXPANDER1_NEG_RATE_FAILED_NEGOTIATION (0x02) 2896 #define MPI_SAS_EXPANDER1_NEG_RATE_SATA_OOB_COMPLETE (0x03) 2897 #define MPI_SAS_EXPANDER1_NEG_RATE_1_5 (0x08) 2898 #define MPI_SAS_EXPANDER1_NEG_RATE_3_0 (0x09) 2899 2900 2901 /**************************************************************************** 2902 * SAS Device Config Pages 2903 ****************************************************************************/ 2904 2905 typedef struct _CONFIG_PAGE_SAS_DEVICE_0 2906 { 2907 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2908 U16 Slot; /* 08h */ 2909 U16 EnclosureHandle; /* 0Ah */ 2910 U64 SASAddress; /* 0Ch */ 2911 U16 ParentDevHandle; /* 14h */ 2912 U8 PhyNum; /* 16h */ 2913 U8 AccessStatus; /* 17h */ 2914 U16 DevHandle; /* 18h */ 2915 U8 TargetID; /* 1Ah */ 2916 U8 Bus; /* 1Bh */ 2917 U32 DeviceInfo; /* 1Ch */ 2918 U16 Flags; /* 20h */ 2919 U8 PhysicalPort; /* 22h */ 2920 U8 Reserved2; /* 23h */ 2921 } CONFIG_PAGE_SAS_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_0, 2922 SasDevicePage0_t, MPI_POINTER pSasDevicePage0_t; 2923 2924 #define MPI_SASDEVICE0_PAGEVERSION (0x05) 2925 2926 /* values for SAS Device Page 0 AccessStatus field */ 2927 #define MPI_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2928 #define MPI_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2929 #define MPI_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2930 #define MPI_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2931 #define MPI_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2932 /* specific values for SATA Init failures */ 2933 #define MPI_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2934 #define MPI_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2935 #define MPI_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2936 #define MPI_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2937 #define MPI_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2938 #define MPI_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2939 #define MPI_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2940 #define MPI_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2941 #define MPI_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2942 #define MPI_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2943 #define MPI_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2944 2945 /* values for SAS Device Page 0 Flags field */ 2946 #define MPI_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2947 #define MPI_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2948 #define MPI_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2949 #define MPI_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2950 #define MPI_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2951 #define MPI_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2952 #define MPI_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2953 #define MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2954 #define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT (0x0004) 2955 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED (0x0002) 2956 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2957 2958 /* see mpi_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2959 2960 2961 typedef struct _CONFIG_PAGE_SAS_DEVICE_1 2962 { 2963 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2964 U32 Reserved1; /* 08h */ 2965 U64 SASAddress; /* 0Ch */ 2966 U32 Reserved2; /* 14h */ 2967 U16 DevHandle; /* 18h */ 2968 U8 TargetID; /* 1Ah */ 2969 U8 Bus; /* 1Bh */ 2970 U8 InitialRegDeviceFIS[20];/* 1Ch */ 2971 } CONFIG_PAGE_SAS_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_1, 2972 SasDevicePage1_t, MPI_POINTER pSasDevicePage1_t; 2973 2974 #define MPI_SASDEVICE1_PAGEVERSION (0x00) 2975 2976 2977 typedef struct _CONFIG_PAGE_SAS_DEVICE_2 2978 { 2979 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2980 U64 PhysicalIdentifier; /* 08h */ 2981 U32 EnclosureMapping; /* 10h */ 2982 } CONFIG_PAGE_SAS_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_2, 2983 SasDevicePage2_t, MPI_POINTER pSasDevicePage2_t; 2984 2985 #define MPI_SASDEVICE2_PAGEVERSION (0x01) 2986 2987 /* defines for SAS Device Page 2 EnclosureMapping field */ 2988 #define MPI_SASDEVICE2_ENC_MAP_MASK_MISSING_COUNT (0x0000000F) 2989 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_MISSING_COUNT (0) 2990 #define MPI_SASDEVICE2_ENC_MAP_MASK_NUM_SLOTS (0x000007F0) 2991 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_NUM_SLOTS (4) 2992 #define MPI_SASDEVICE2_ENC_MAP_MASK_START_INDEX (0x001FF800) 2993 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_START_INDEX (11) 2994 2995 2996 /**************************************************************************** 2997 * SAS PHY Config Pages 2998 ****************************************************************************/ 2999 3000 typedef struct _CONFIG_PAGE_SAS_PHY_0 3001 { 3002 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 3003 U16 OwnerDevHandle; /* 08h */ 3004 U16 Reserved1; /* 0Ah */ 3005 U64 SASAddress; /* 0Ch */ 3006 U16 AttachedDevHandle; /* 14h */ 3007 U8 AttachedPhyIdentifier; /* 16h */ 3008 U8 Reserved2; /* 17h */ 3009 U32 AttachedDeviceInfo; /* 18h */ 3010 U8 ProgrammedLinkRate; /* 1Ch */ 3011 U8 HwLinkRate; /* 1Dh */ 3012 U8 ChangeCount; /* 1Eh */ 3013 U8 Flags; /* 1Fh */ 3014 U32 PhyInfo; /* 20h */ 3015 } CONFIG_PAGE_SAS_PHY_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_0, 3016 SasPhyPage0_t, MPI_POINTER pSasPhyPage0_t; 3017 3018 #define MPI_SASPHY0_PAGEVERSION (0x01) 3019 3020 /* values for SAS PHY Page 0 ProgrammedLinkRate field */ 3021 #define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK (0xF0) 3022 #define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 3023 #define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5 (0x80) 3024 #define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0 (0x90) 3025 #define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK (0x0F) 3026 #define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 3027 #define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5 (0x08) 3028 #define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0 (0x09) 3029 3030 /* values for SAS PHY Page 0 HwLinkRate field */ 3031 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK (0xF0) 3032 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5 (0x80) 3033 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0 (0x90) 3034 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK (0x0F) 3035 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5 (0x08) 3036 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0 (0x09) 3037 3038 /* values for SAS PHY Page 0 Flags field */ 3039 #define MPI_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 3040 3041 /* values for SAS PHY Page 0 PhyInfo field */ 3042 #define MPI_SAS_PHY0_PHYINFO_PHY_VACANT (0x80000000) 3043 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 3044 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR (0x00002000) 3045 #define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY (0x00001000) 3046 3047 #define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 3048 #define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 3049 3050 #define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 3051 #define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING (0x00000000) 3052 #define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 3053 #define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING (0x00000020) 3054 3055 #define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE (0x0000000F) 3056 #define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE (0x00000000) 3057 #define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED (0x00000001) 3058 #define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED (0x00000002) 3059 #define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE (0x00000003) 3060 #define MPI_SAS_PHY0_PHYINFO_RATE_1_5 (0x00000008) 3061 #define MPI_SAS_PHY0_PHYINFO_RATE_3_0 (0x00000009) 3062 3063 3064 typedef struct _CONFIG_PAGE_SAS_PHY_1 3065 { 3066 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 3067 U32 Reserved1; /* 08h */ 3068 U32 InvalidDwordCount; /* 0Ch */ 3069 U32 RunningDisparityErrorCount; /* 10h */ 3070 U32 LossDwordSynchCount; /* 14h */ 3071 U32 PhyResetProblemCount; /* 18h */ 3072 } CONFIG_PAGE_SAS_PHY_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_1, 3073 SasPhyPage1_t, MPI_POINTER pSasPhyPage1_t; 3074 3075 #define MPI_SASPHY1_PAGEVERSION (0x00) 3076 3077 3078 /**************************************************************************** 3079 * SAS Enclosure Config Pages 3080 ****************************************************************************/ 3081 3082 typedef struct _CONFIG_PAGE_SAS_ENCLOSURE_0 3083 { 3084 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 3085 U32 Reserved1; /* 08h */ 3086 U64 EnclosureLogicalID; /* 0Ch */ 3087 U16 Flags; /* 14h */ 3088 U16 EnclosureHandle; /* 16h */ 3089 U16 NumSlots; /* 18h */ 3090 U16 StartSlot; /* 1Ah */ 3091 U8 StartTargetID; /* 1Ch */ 3092 U8 StartBus; /* 1Dh */ 3093 U8 SEPTargetID; /* 1Eh */ 3094 U8 SEPBus; /* 1Fh */ 3095 U32 Reserved2; /* 20h */ 3096 U32 Reserved3; /* 24h */ 3097 } CONFIG_PAGE_SAS_ENCLOSURE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_ENCLOSURE_0, 3098 SasEnclosurePage0_t, MPI_POINTER pSasEnclosurePage0_t; 3099 3100 #define MPI_SASENCLOSURE0_PAGEVERSION (0x01) 3101 3102 /* values for SAS Enclosure Page 0 Flags field */ 3103 #define MPI_SAS_ENCLS0_FLAGS_SEP_BUS_ID_VALID (0x0020) 3104 #define MPI_SAS_ENCLS0_FLAGS_START_BUS_ID_VALID (0x0010) 3105 3106 #define MPI_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3107 #define MPI_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3108 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3109 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3110 #define MPI_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3111 #define MPI_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3112 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3113 3114 3115 /**************************************************************************** 3116 * Log Config Pages 3117 ****************************************************************************/ 3118 /* 3119 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3120 * one and check NumLogEntries at runtime. 3121 */ 3122 #ifndef MPI_LOG_0_NUM_LOG_ENTRIES 3123 #define MPI_LOG_0_NUM_LOG_ENTRIES (1) 3124 #endif 3125 3126 #define MPI_LOG_0_LOG_DATA_LENGTH (0x1C) 3127 3128 typedef struct _MPI_LOG_0_ENTRY 3129 { 3130 U32 TimeStamp; /* 00h */ 3131 U32 Reserved1; /* 04h */ 3132 U16 LogSequence; /* 08h */ 3133 U16 LogEntryQualifier; /* 0Ah */ 3134 U8 LogData[MPI_LOG_0_LOG_DATA_LENGTH]; /* 0Ch */ 3135 } MPI_LOG_0_ENTRY, MPI_POINTER PTR_MPI_LOG_0_ENTRY, 3136 MpiLog0Entry_t, MPI_POINTER pMpiLog0Entry_t; 3137 3138 /* values for Log Page 0 LogEntry LogEntryQualifier field */ 3139 #define MPI_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3140 #define MPI_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3141 3142 typedef struct _CONFIG_PAGE_LOG_0 3143 { 3144 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 3145 U32 Reserved1; /* 08h */ 3146 U32 Reserved2; /* 0Ch */ 3147 U16 NumLogEntries; /* 10h */ 3148 U16 Reserved3; /* 12h */ 3149 MPI_LOG_0_ENTRY LogEntry[MPI_LOG_0_NUM_LOG_ENTRIES]; /* 14h */ 3150 } CONFIG_PAGE_LOG_0, MPI_POINTER PTR_CONFIG_PAGE_LOG_0, 3151 LogPage0_t, MPI_POINTER pLogPage0_t; 3152 3153 #define MPI_LOG_0_PAGEVERSION (0x01) 3154 3155 3156 #endif 3157 3158