1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2000-2010, LSI Logic Corporation and its contributors. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are 9 * met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13 * substantially similar to the "NO WARRANTY" disclaimer below 14 * ("Disclaimer") and any redistribution must be conditioned upon including 15 * a substantially similar Disclaimer requirement for further binary 16 * redistribution. 17 * 3. Neither the name of the LSI Logic Corporation nor the names of its 18 * contributors may be used to endorse or promote products derived from 19 * this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF THE COPYRIGHT 31 * OWNER OR CONTRIBUTOR IS ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * Name: mpi_cnfg.h 34 * Title: MPI Config message, structures, and Pages 35 * Creation Date: July 27, 2000 36 * 37 * mpi_cnfg.h Version: 01.05.19 38 * 39 * Version History 40 * --------------- 41 * 42 * Date Version Description 43 * -------- -------- ------------------------------------------------------ 44 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000. 45 * 06-06-00 01.00.01 Update version number for 1.0 release. 46 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages. 47 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2 48 * fields to FC_DEVICE_0 page, updated the page version. 49 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in 50 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages 51 * and updated the page versions. 52 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1 53 * page and updated the page version. 54 * Added Information field and _INFO_PARAMS_NEGOTIATED 55 * definitionto SCSI_DEVICE_0 page. 56 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the 57 * page version. 58 * Added BucketsRemaining to LAN_1 page, redefined the 59 * state values, and updated the page version. 60 * Revised bus width definitions in SCSI_PORT_0, 61 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages. 62 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page 63 * version. 64 * Moved FC_DEVICE_0 PageAddress description to spec. 65 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field 66 * widths in IOC_0 page and updated the page version. 67 * 11-02-00 01.01.01 Original release for post 1.0 work 68 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI 69 * Port Page 2, FC Port Page 4, FC Port Page 5 70 * 11-15-00 01.01.02 Interim changes to match proposals 71 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01. 72 * 12-05-00 01.01.04 Modified config page actions. 73 * 01-09-01 01.01.05 Added defines for page address formats. 74 * Data size for Manufacturing pages 2 and 3 no longer 75 * defined here. 76 * Io Unit Page 2 size is fixed at 4 adapters and some 77 * flags were changed. 78 * SCSI Port Page 2 Device Settings modified. 79 * New fields added to FC Port Page 0 and some flags 80 * cleaned up. 81 * Removed impedance flash from FC Port Page 1. 82 * Added FC Port pages 6 and 7. 83 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0. 84 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique. 85 * Added some LinkType defines for FcPortPage0. 86 * 02-20-01 01.01.08 Started using MPI_POINTER. 87 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with 88 * MPI_CONFIG_PAGETYPE_RAID_VOLUME. 89 * Added definitions and structures for IOC Page 2 and 90 * RAID Volume Page 2. 91 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9. 92 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID. 93 * Added VendorId and ProductRevLevel fields to 94 * RAIDVOL2_IM_PHYS_ID struct. 95 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_ 96 * defines to make them compatible to MPI version 1.0. 97 * Added structure offset comments. 98 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and 99 * removed some obsolete ones. 100 * Added IO Unit Page 3. 101 * Modified defines for Scsi Port Page 2. 102 * Modified RAID Volume Pages. 103 * 08-08-01 01.02.01 Original release for v1.2 work. 104 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct. 105 * Added defines for the SEP bits in RVP2 VolumeSettings. 106 * Modified the DeviceSettings field in RVP2 to use the 107 * proper structure. 108 * Added defines for SES, SAF-TE, and cross channel for 109 * IOCPage2 CapabilitiesFlags. 110 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE. 111 * Removed define for 112 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE. 113 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT. 114 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035. 115 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY 116 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY. 117 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS, 118 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and 119 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and 120 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED. 121 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED 122 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED. 123 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1. 124 * Added rejected bits to SCSI Device Page 0 Information. 125 * Increased size of ALPA array in FC Port Page 2 by one 126 * and removed a one byte reserved field. 127 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in 128 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering. 129 * Added structures for Manufacturing Page 4, IO Unit 130 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and 131 * RAID PhysDisk Page 0. 132 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK. 133 * Modified some of the new defines to make them 32 134 * character unique. 135 * Modified how variable length pages (arrays) are defined. 136 * Added generic defines for hot spare pools and RAID 137 * volume types. 138 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR. 139 * 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with 140 * related define, and bumped the page version define. 141 * 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a 142 * reserved byte and added a define. 143 * Added define for 144 * MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE. 145 * Added new config page: CONFIG_PAGE_IOC_5. 146 * Added MaxAliases, MaxHardAliases, and NumCurrentAliases 147 * fields to CONFIG_PAGE_FC_PORT_0. 148 * Added AltConnector and NumRequestedAliases fields to 149 * CONFIG_PAGE_FC_PORT_1. 150 * Added new config page: CONFIG_PAGE_FC_PORT_10. 151 * 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines. 152 * Added additional MPI_SCSIDEVPAGE0_NP_ defines. 153 * Added more MPI_SCSIDEVPAGE1_RP_ defines. 154 * Added define for 155 * MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE. 156 * Added new config page: CONFIG_PAGE_SCSI_DEVICE_3. 157 * Modified MPI_FCPORTPAGE5_FLAGS_ defines. 158 * 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define. 159 * 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0. 160 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1. 161 * Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0. 162 * 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for 163 * CONFIG_PAGE_FC_PORT_1. 164 * Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable 165 * an alias. 166 * Added more device id defines. 167 * 06-26-03 01.02.12 Added MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID define. 168 * Added TargetConfig and IDConfig fields to 169 * CONFIG_PAGE_SCSI_PORT_1. 170 * Added more PortFlags defines for CONFIG_PAGE_SCSI_PORT_2 171 * to control DV. 172 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1. 173 * In CONFIG_PAGE_FC_DEVICE_0, replaced Reserved1 field 174 * with ADISCHardALPA. 175 * Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define. 176 * 01-16-04 01.02.13 Added InitiatorDeviceTimeout and InitiatorIoPendTimeout 177 * fields and related defines to CONFIG_PAGE_FC_PORT_1. 178 * Added define for 179 * MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK. 180 * Added new fields to the substructures of 181 * CONFIG_PAGE_FC_PORT_10. 182 * 04-29-04 01.02.14 Added define for IDP bit for CONFIG_PAGE_SCSI_PORT_0, 183 * CONFIG_PAGE_SCSI_DEVICE_0, and 184 * CONFIG_PAGE_SCSI_DEVICE_1. Also bumped Page Version for 185 * these pages. 186 * 05-11-04 01.03.01 Added structure for CONFIG_PAGE_INBAND_0. 187 * 08-19-04 01.05.01 Modified MSG_CONFIG request to support extended config 188 * pages. 189 * Added a new structure for extended config page header. 190 * Added new extended config pages types and structures for 191 * SAS IO Unit, SAS Expander, SAS Device, and SAS PHY. 192 * Replaced a reserved byte in CONFIG_PAGE_MANUFACTURING_4 193 * to add a Flags field. 194 * Two new Manufacturing config pages (5 and 6). 195 * Two new bits defined for IO Unit Page 1 Flags field. 196 * Modified CONFIG_PAGE_IO_UNIT_2 to add three new fields 197 * to specify the BIOS boot device. 198 * Four new Flags bits defined for IO Unit Page 2. 199 * Added IO Unit Page 4. 200 * Added EEDP Flags settings to IOC Page 1. 201 * Added new BIOS Page 1 config page. 202 * 10-05-04 01.05.02 Added define for 203 * MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE. 204 * Added new Flags field to CONFIG_PAGE_MANUFACTURING_5 and 205 * associated defines. 206 * Added more defines for SAS IO Unit Page 0 207 * DiscoveryStatus field. 208 * Added define for MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK 209 * and MPI_SAS_IOUNIT0_DS_TABLE_LINK. 210 * Added defines for Physical Mapping Modes to SAS IO Unit 211 * Page 2. 212 * Added define for 213 * MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH. 214 * 10-27-04 01.05.03 Added defines for new SAS PHY page addressing mode. 215 * Added defines for MaxTargetSpinUp to BIOS Page 1. 216 * Added 5 new ControlFlags defines for SAS IO Unit 217 * Page 1. 218 * Added MaxNumPhysicalMappedIDs field to SAS IO Unit 219 * Page 2. 220 * Added AccessStatus field to SAS Device Page 0 and added 221 * new Flags bits for supported SATA features. 222 * 12-07-04 01.05.04 Added config page structures for BIOS Page 2, RAID 223 * Volume Page 1, and RAID Physical Disk Page 1. 224 * Replaced IO Unit Page 1 BootTargetID,BootBus, and 225 * BootAdapterNum with reserved field. 226 * Added DataScrubRate and ResyncRate to RAID Volume 227 * Page 0. 228 * Added MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT 229 * define. 230 * 12-09-04 01.05.05 Added Target Mode Large CDB Enable to FC Port Page 1 231 * Flags field. 232 * Added Auto Port Config flag define for SAS IOUNIT 233 * Page 1 ControlFlags. 234 * Added Disabled bad Phy define to Expander Page 1 235 * Discovery Info field. 236 * Added SAS/SATA device support to SAS IOUnit Page 1 237 * ControlFlags. 238 * Added Unsupported device to SAS Dev Page 0 Flags field 239 * Added disable use SATA Hash Address for SAS IOUNIT 240 * page 1 in ControlFields. 241 * 01-15-05 01.05.06 Added defaults for data scrub rate and resync rate to 242 * Manufacturing Page 4. 243 * Added new defines for BIOS Page 1 IOCSettings field. 244 * Added ExtDiskIdentifier field to RAID Physical Disk 245 * Page 0. 246 * Added new defines for SAS IO Unit Page 1 ControlFlags 247 * and to SAS Device Page 0 Flags to control SATA devices. 248 * Added defines and structures for the new Log Page 0, a 249 * new type of configuration page. 250 * 02-09-05 01.05.07 Added InactiveStatus field to RAID Volume Page 0. 251 * Added WWID field to RAID Volume Page 1. 252 * Added PhysicalPort field to SAS Expander pages 0 and 1. 253 * 03-11-05 01.05.08 Removed the EEDP flags from IOC Page 1. 254 * Added Enclosure/Slot boot device format to BIOS Page 2. 255 * New status value for RAID Volume Page 0 VolumeStatus 256 * (VolumeState subfield). 257 * New value for RAID Physical Page 0 InactiveStatus. 258 * Added Inactive Volume Member flag RAID Physical Disk 259 * Page 0 PhysDiskStatus field. 260 * New physical mapping mode in SAS IO Unit Page 2. 261 * Added CONFIG_PAGE_SAS_ENCLOSURE_0. 262 * Added Slot and Enclosure fields to SAS Device Page 0. 263 * 06-24-05 01.05.09 Added EEDP defines to IOC Page 1. 264 * Added more RAID type defines to IOC Page 2. 265 * Added Port Enable Delay settings to BIOS Page 1. 266 * Added Bad Block Table Full define to RAID Volume Page 0. 267 * Added Previous State defines to RAID Physical Disk 268 * Page 0. 269 * Added Max Sata Targets define for DiscoveryStatus field 270 * of SAS IO Unit Page 0. 271 * Added Device Self Test to Control Flags of SAS IO Unit 272 * Page 1. 273 * Added Direct Attach Starting Slot Number define for SAS 274 * IO Unit Page 2. 275 * Added new fields in SAS Device Page 2 for enclosure 276 * mapping. 277 * Added OwnerDevHandle and Flags field to SAS PHY Page 0. 278 * Added IOC GPIO Flags define to SAS Enclosure Page 0. 279 * Fixed the value for MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT. 280 * 08-03-05 01.05.10 Removed ISDataScrubRate and ISResyncRate from 281 * Manufacturing Page 4. 282 * Added MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE bit. 283 * Added NumDevsPerEnclosure field to SAS IO Unit page 2. 284 * Added MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP 285 * define. 286 * Added EnclosureHandle field to SAS Expander page 0. 287 * Removed redundant NumTableEntriesProg field from SAS 288 * Expander Page 1. 289 * 08-30-05 01.05.11 Added DeviceID for FC949E and changed the DeviceID for 290 * SAS1078. 291 * Added more defines for Manufacturing Page 4 Flags field. 292 * Added more defines for IOCSettings and added 293 * ExpanderSpinup field to Bios Page 1. 294 * Added postpone SATA Init bit to SAS IO Unit Page 1 295 * ControlFlags. 296 * Changed LogEntry format for Log Page 0. 297 * 03-27-06 01.05.12 Added two new Flags defines for Manufacturing Page 4. 298 * Added Manufacturing Page 7. 299 * Added MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING. 300 * Added IOC Page 6. 301 * Added PrevBootDeviceForm field to CONFIG_PAGE_BIOS_2. 302 * Added MaxLBAHigh field to RAID Volume Page 0. 303 * Added Nvdata version fields to SAS IO Unit Page 0. 304 * Added AdditionalControlFlags, MaxTargetPortConnectTime, 305 * ReportDeviceMissingDelay, and IODeviceMissingDelay 306 * fields to SAS IO Unit Page 1. 307 * 10-11-06 01.05.13 Added NumForceWWID field and ForceWWID array to 308 * Manufacturing Page 5. 309 * Added Manufacturing pages 8 through 10. 310 * Added defines for supported metadata size bits in 311 * CapabilitiesFlags field of IOC Page 6. 312 * Added defines for metadata size bits in VolumeSettings 313 * field of RAID Volume Page 0. 314 * Added SATA Link Reset settings, Enable SATA Asynchronous 315 * Notification bit, and HideNonZeroAttachedPhyIdentifiers 316 * bit to AdditionalControlFlags field of SAS IO Unit 317 * Page 1. 318 * Added defines for Enclosure Devices Unmapped and 319 * Device Limit Exceeded bits in Status field of SAS IO 320 * Unit Page 2. 321 * Added more AccessStatus values for SAS Device Page 0. 322 * Added bit for SATA Asynchronous Notification Support in 323 * Flags field of SAS Device Page 0. 324 * 02-28-07 01.05.14 Added ExtFlags field to Manufacturing Page 4. 325 * Added Disable SMART Polling for CapabilitiesFlags of 326 * IOC Page 6. 327 * Added Disable SMART Polling to DeviceSettings of BIOS 328 * Page 1. 329 * Added Multi-Port Domain bit for DiscoveryStatus field 330 * of SAS IO Unit Page. 331 * Added Multi-Port Domain Illegal flag for SAS IO Unit 332 * Page 1 AdditionalControlFlags field. 333 * 05-24-07 01.05.15 Added Hide Physical Disks with Non-Integrated RAID 334 * Metadata bit to Manufacturing Page 4 ExtFlags field. 335 * Added Internal Connector to End Device Present bit to 336 * Expander Page 0 Flags field. 337 * Fixed define for 338 * MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED. 339 * 08-07-07 01.05.16 Added MPI_IOCPAGE6_CAP_FLAGS_MULTIPORT_DRIVE_SUPPORT 340 * define. 341 * Added BIOS Page 4 structure. 342 * Added MPI_RAID_PHYS_DISK1_PATH_MAX define for RAID 343 * Physical Disk Page 1. 344 * 01-15-07 01.05.17 Added additional bit defines for ExtFlags field of 345 * Manufacturing Page 4. 346 * Added Solid State Drives Supported bit to IOC Page 6 347 * Capabilities Flags. 348 * Added new value for AccessStatus field of SAS Device 349 * Page 0 (_SATA_NEEDS_INITIALIZATION). 350 * 03-28-08 01.05.18 Defined new bits in Manufacturing Page 4 ExtFlags field 351 * to control coercion size and the mixing of SAS and SATA 352 * SSD drives. 353 * 07-11-08 01.05.19 Added defines MPI_MANPAGE4_EXTFLAGS_RAID0_SINGLE_DRIVE 354 * and MPI_MANPAGE4_EXTFLAGS_SSD_SCRUB_DISABLE for ExtFlags 355 * field of Manufacturing Page 4. 356 * Added defines for a new bit in BIOS Page 1 BiosOptions 357 * field to control adapter scan order. 358 * Added BootDeviceWaitTime field to SAS IO Unit Page 2. 359 * Added MPI_SAS_PHY0_PHYINFO_PHY_VACANT for use in PhyInfo 360 * field of SAS Expander Page 1. 361 * -------------------------------------------------------------------------- 362 */ 363 364 #ifndef MPI_CNFG_H 365 #define MPI_CNFG_H 366 367 /***************************************************************************** 368 * 369 * C o n f i g M e s s a g e a n d S t r u c t u r e s 370 * 371 *****************************************************************************/ 372 373 typedef struct _CONFIG_PAGE_HEADER 374 { 375 U8 PageVersion; /* 00h */ 376 U8 PageLength; /* 01h */ 377 U8 PageNumber; /* 02h */ 378 U8 PageType; /* 03h */ 379 } CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER, 380 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t; 381 382 typedef union _CONFIG_PAGE_HEADER_UNION 383 { 384 ConfigPageHeader_t Struct; 385 U8 Bytes[4]; 386 U16 Word16[2]; 387 U32 Word32; 388 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion, 389 CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION; 390 391 typedef struct _CONFIG_EXTENDED_PAGE_HEADER 392 { 393 U8 PageVersion; /* 00h */ 394 U8 Reserved1; /* 01h */ 395 U8 PageNumber; /* 02h */ 396 U8 PageType; /* 03h */ 397 U16 ExtPageLength; /* 04h */ 398 U8 ExtPageType; /* 06h */ 399 U8 Reserved2; /* 07h */ 400 } CONFIG_EXTENDED_PAGE_HEADER, MPI_POINTER PTR_CONFIG_EXTENDED_PAGE_HEADER, 401 ConfigExtendedPageHeader_t, MPI_POINTER pConfigExtendedPageHeader_t; 402 403 /**************************************************************************** 404 * PageType field values 405 ****************************************************************************/ 406 #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00) 407 #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10) 408 #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20) 409 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30) 410 #define MPI_CONFIG_PAGEATTR_MASK (0xF0) 411 412 #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00) 413 #define MPI_CONFIG_PAGETYPE_IOC (0x01) 414 #define MPI_CONFIG_PAGETYPE_BIOS (0x02) 415 #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03) 416 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04) 417 #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05) 418 #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06) 419 #define MPI_CONFIG_PAGETYPE_LAN (0x07) 420 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 421 #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09) 422 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 423 #define MPI_CONFIG_PAGETYPE_INBAND (0x0B) 424 #define MPI_CONFIG_PAGETYPE_EXTENDED (0x0F) 425 #define MPI_CONFIG_PAGETYPE_MASK (0x0F) 426 427 #define MPI_CONFIG_TYPENUM_MASK (0x0FFF) 428 429 /**************************************************************************** 430 * ExtPageType field values 431 ****************************************************************************/ 432 #define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 433 #define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 434 #define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 435 #define MPI_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 436 #define MPI_CONFIG_EXTPAGETYPE_LOG (0x14) 437 #define MPI_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 438 439 /**************************************************************************** 440 * PageAddress field values 441 ****************************************************************************/ 442 #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF) 443 444 #define MPI_SCSI_DEVICE_FORM_MASK (0xF0000000) 445 #define MPI_SCSI_DEVICE_FORM_BUS_TID (0x00000000) 446 #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF) 447 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0) 448 #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00) 449 #define MPI_SCSI_DEVICE_BUS_SHIFT (8) 450 #define MPI_SCSI_DEVICE_FORM_TARGET_MODE (0x10000000) 451 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_MASK (0x000000FF) 452 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_SHIFT (0) 453 #define MPI_SCSI_DEVICE_TM_BUS_MASK (0x0000FF00) 454 #define MPI_SCSI_DEVICE_TM_BUS_SHIFT (8) 455 #define MPI_SCSI_DEVICE_TM_INIT_ID_MASK (0x00FF0000) 456 #define MPI_SCSI_DEVICE_TM_INIT_ID_SHIFT (16) 457 458 #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000) 459 #define MPI_FC_PORT_PGAD_PORT_SHIFT (28) 460 #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000) 461 #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000) 462 #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF) 463 #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0) 464 465 #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000) 466 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28) 467 #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000) 468 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000) 469 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000) 470 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28) 471 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF) 472 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0) 473 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000) 474 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 475 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8) 476 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 477 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0) 478 479 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 480 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0) 481 482 #define MPI_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 483 #define MPI_SAS_EXPAND_PGAD_FORM_SHIFT (28) 484 #define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 485 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x00000001) 486 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE (0x00000002) 487 #define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE (0x0000FFFF) 488 #define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE (0) 489 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY (0x00FF0000) 490 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY (16) 491 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE (0x0000FFFF) 492 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE (0) 493 #define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE (0x0000FFFF) 494 #define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE (0) 495 496 #define MPI_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 497 #define MPI_SAS_DEVICE_PGAD_FORM_SHIFT (28) 498 #define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 499 #define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID (0x00000001) 500 #define MPI_SAS_DEVICE_PGAD_FORM_HANDLE (0x00000002) 501 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK (0x0000FFFF) 502 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT (0) 503 #define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00) 504 #define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT (8) 505 #define MPI_SAS_DEVICE_PGAD_BT_TID_MASK (0x000000FF) 506 #define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT (0) 507 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK (0x0000FFFF) 508 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT (0) 509 510 #define MPI_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 511 #define MPI_SAS_PHY_PGAD_FORM_SHIFT (28) 512 #define MPI_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x0) 513 #define MPI_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x1) 514 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 515 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (0) 516 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 517 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_SHIFT (0) 518 519 #define MPI_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 520 #define MPI_SAS_ENCLOS_PGAD_FORM_SHIFT (28) 521 #define MPI_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 522 #define MPI_SAS_ENCLOS_PGAD_FORM_HANDLE (0x00000001) 523 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_MASK (0x0000FFFF) 524 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_SHIFT (0) 525 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_MASK (0x0000FFFF) 526 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_SHIFT (0) 527 528 /**************************************************************************** 529 * Config Request Message 530 ****************************************************************************/ 531 typedef struct _MSG_CONFIG 532 { 533 U8 Action; /* 00h */ 534 U8 Reserved; /* 01h */ 535 U8 ChainOffset; /* 02h */ 536 U8 Function; /* 03h */ 537 U16 ExtPageLength; /* 04h */ 538 U8 ExtPageType; /* 06h */ 539 U8 MsgFlags; /* 07h */ 540 U32 MsgContext; /* 08h */ 541 U8 Reserved2[8]; /* 0Ch */ 542 CONFIG_PAGE_HEADER Header; /* 14h */ 543 U32 PageAddress; /* 18h */ 544 SGE_IO_UNION PageBufferSGE; /* 1Ch */ 545 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG, 546 Config_t, MPI_POINTER pConfig_t; 547 548 /**************************************************************************** 549 * Action field values 550 ****************************************************************************/ 551 #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00) 552 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 553 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 554 #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03) 555 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 556 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 557 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 558 559 /* Config Reply Message */ 560 typedef struct _MSG_CONFIG_REPLY 561 { 562 U8 Action; /* 00h */ 563 U8 Reserved; /* 01h */ 564 U8 MsgLength; /* 02h */ 565 U8 Function; /* 03h */ 566 U16 ExtPageLength; /* 04h */ 567 U8 ExtPageType; /* 06h */ 568 U8 MsgFlags; /* 07h */ 569 U32 MsgContext; /* 08h */ 570 U8 Reserved2[2]; /* 0Ch */ 571 U16 IOCStatus; /* 0Eh */ 572 U32 IOCLogInfo; /* 10h */ 573 CONFIG_PAGE_HEADER Header; /* 14h */ 574 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY, 575 ConfigReply_t, MPI_POINTER pConfigReply_t; 576 577 /***************************************************************************** 578 * 579 * C o n f i g u r a t i o n P a g e s 580 * 581 *****************************************************************************/ 582 583 /**************************************************************************** 584 * Manufacturing Config pages 585 ****************************************************************************/ 586 #define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000) 587 /* Fibre Channel */ 588 #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621) 589 #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624) 590 #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622) 591 #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628) 592 #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626) 593 #define MPI_MANUFACTPAGE_DEVICEID_FC939X (0x0642) 594 #define MPI_MANUFACTPAGE_DEVICEID_FC949X (0x0640) 595 #define MPI_MANUFACTPAGE_DEVICEID_FC949E (0x0646) 596 /* SCSI */ 597 #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030) 598 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031) 599 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032) 600 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033) 601 #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040) 602 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041) 603 /* SAS */ 604 #define MPI_MANUFACTPAGE_DEVID_SAS1064 (0x0050) 605 #define MPI_MANUFACTPAGE_DEVID_SAS1064A (0x005C) 606 #define MPI_MANUFACTPAGE_DEVID_SAS1064E (0x0056) 607 #define MPI_MANUFACTPAGE_DEVID_SAS1066 (0x005E) 608 #define MPI_MANUFACTPAGE_DEVID_SAS1066E (0x005A) 609 #define MPI_MANUFACTPAGE_DEVID_SAS1068 (0x0054) 610 #define MPI_MANUFACTPAGE_DEVID_SAS1068E (0x0058) 611 #define MPI_MANUFACTPAGE_DEVID_SAS1078 (0x0062) 612 613 typedef struct _CONFIG_PAGE_MANUFACTURING_0 614 { 615 CONFIG_PAGE_HEADER Header; /* 00h */ 616 U8 ChipName[16]; /* 04h */ 617 U8 ChipRevision[8]; /* 14h */ 618 U8 BoardName[16]; /* 1Ch */ 619 U8 BoardAssembly[16]; /* 2Ch */ 620 U8 BoardTracerNumber[16]; /* 3Ch */ 621 622 } CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0, 623 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t; 624 625 #define MPI_MANUFACTURING0_PAGEVERSION (0x00) 626 627 typedef struct _CONFIG_PAGE_MANUFACTURING_1 628 { 629 CONFIG_PAGE_HEADER Header; /* 00h */ 630 U8 VPD[256]; /* 04h */ 631 } CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1, 632 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t; 633 634 #define MPI_MANUFACTURING1_PAGEVERSION (0x00) 635 636 typedef struct _MPI_CHIP_REVISION_ID 637 { 638 U16 DeviceID; /* 00h */ 639 U8 PCIRevisionID; /* 02h */ 640 U8 Reserved; /* 03h */ 641 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID, 642 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t; 643 644 /* 645 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 646 * one and check Header.PageLength at runtime. 647 */ 648 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS 649 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 650 #endif 651 652 typedef struct _CONFIG_PAGE_MANUFACTURING_2 653 { 654 CONFIG_PAGE_HEADER Header; /* 00h */ 655 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 656 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */ 657 } CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2, 658 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t; 659 660 #define MPI_MANUFACTURING2_PAGEVERSION (0x00) 661 662 /* 663 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 664 * one and check Header.PageLength at runtime. 665 */ 666 #ifndef MPI_MAN_PAGE_3_INFO_WORDS 667 #define MPI_MAN_PAGE_3_INFO_WORDS (1) 668 #endif 669 670 typedef struct _CONFIG_PAGE_MANUFACTURING_3 671 { 672 CONFIG_PAGE_HEADER Header; /* 00h */ 673 MPI_CHIP_REVISION_ID ChipId; /* 04h */ 674 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */ 675 } CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3, 676 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t; 677 678 #define MPI_MANUFACTURING3_PAGEVERSION (0x00) 679 680 typedef struct _CONFIG_PAGE_MANUFACTURING_4 681 { 682 CONFIG_PAGE_HEADER Header; /* 00h */ 683 U32 Reserved1; /* 04h */ 684 U8 InfoOffset0; /* 08h */ 685 U8 InfoSize0; /* 09h */ 686 U8 InfoOffset1; /* 0Ah */ 687 U8 InfoSize1; /* 0Bh */ 688 U8 InquirySize; /* 0Ch */ 689 U8 Flags; /* 0Dh */ 690 U16 ExtFlags; /* 0Eh */ 691 U8 InquiryData[56]; /* 10h */ 692 U32 ISVolumeSettings; /* 48h */ 693 U32 IMEVolumeSettings; /* 4Ch */ 694 U32 IMVolumeSettings; /* 50h */ 695 U32 Reserved3; /* 54h */ 696 U32 Reserved4; /* 58h */ 697 U32 Reserved5; /* 5Ch */ 698 U8 IMEDataScrubRate; /* 60h */ 699 U8 IMEResyncRate; /* 61h */ 700 U16 Reserved6; /* 62h */ 701 U8 IMDataScrubRate; /* 64h */ 702 U8 IMResyncRate; /* 65h */ 703 U16 Reserved7; /* 66h */ 704 U32 Reserved8; /* 68h */ 705 U32 Reserved9; /* 6Ch */ 706 } CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4, 707 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t; 708 709 #define MPI_MANUFACTURING4_PAGEVERSION (0x05) 710 711 /* defines for the Flags field */ 712 #define MPI_MANPAGE4_FORCE_BAD_BLOCK_TABLE (0x80) 713 #define MPI_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x40) 714 #define MPI_MANPAGE4_IME_DISABLE (0x20) 715 #define MPI_MANPAGE4_IM_DISABLE (0x10) 716 #define MPI_MANPAGE4_IS_DISABLE (0x08) 717 #define MPI_MANPAGE4_IR_MODEPAGE8_DISABLE (0x04) 718 #define MPI_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x02) 719 #define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA (0x01) 720 721 /* defines for the ExtFlags field */ 722 #define MPI_MANPAGE4_EXTFLAGS_RAID0_SINGLE_DRIVE (0x0400) 723 #define MPI_MANPAGE4_EXTFLAGS_SSD_SCRUB_DISABLE (0x0200) 724 #define MPI_MANPAGE4_EXTFLAGS_MASK_COERCION_SIZE (0x0180) 725 #define MPI_MANPAGE4_EXTFLAGS_SHIFT_COERCION_SIZE (7) 726 #define MPI_MANPAGE4_EXTFLAGS_1GB_COERCION_SIZE (0) 727 #define MPI_MANPAGE4_EXTFLAGS_128MB_COERCION_SIZE (1) 728 729 #define MPI_MANPAGE4_EXTFLAGS_NO_MIX_SSD_SAS_SATA (0x0040) 730 #define MPI_MANPAGE4_EXTFLAGS_MIX_SSD_AND_NON_SSD (0x0020) 731 #define MPI_MANPAGE4_EXTFLAGS_DUAL_PORT_SUPPORT (0x0010) 732 #define MPI_MANPAGE4_EXTFLAGS_HIDE_NON_IR_METADATA (0x0008) 733 #define MPI_MANPAGE4_EXTFLAGS_SAS_CACHE_DISABLE (0x0004) 734 #define MPI_MANPAGE4_EXTFLAGS_SATA_CACHE_DISABLE (0x0002) 735 #define MPI_MANPAGE4_EXTFLAGS_LEGACY_MODE (0x0001) 736 737 #ifndef MPI_MANPAGE5_NUM_FORCEWWID 738 #define MPI_MANPAGE5_NUM_FORCEWWID (1) 739 #endif 740 741 typedef struct _CONFIG_PAGE_MANUFACTURING_5 742 { 743 CONFIG_PAGE_HEADER Header; /* 00h */ 744 U64 BaseWWID; /* 04h */ 745 U8 Flags; /* 0Ch */ 746 U8 NumForceWWID; /* 0Dh */ 747 U16 Reserved2; /* 0Eh */ 748 U32 Reserved3; /* 10h */ 749 U32 Reserved4; /* 14h */ 750 U64 ForceWWID[MPI_MANPAGE5_NUM_FORCEWWID]; /* 18h */ 751 } CONFIG_PAGE_MANUFACTURING_5, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_5, 752 ManufacturingPage5_t, MPI_POINTER pManufacturingPage5_t; 753 754 #define MPI_MANUFACTURING5_PAGEVERSION (0x02) 755 756 /* defines for the Flags field */ 757 #define MPI_MANPAGE5_TWO_WWID_PER_PHY (0x01) 758 759 typedef struct _CONFIG_PAGE_MANUFACTURING_6 760 { 761 CONFIG_PAGE_HEADER Header; /* 00h */ 762 U32 ProductSpecificInfo;/* 04h */ 763 } CONFIG_PAGE_MANUFACTURING_6, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_6, 764 ManufacturingPage6_t, MPI_POINTER pManufacturingPage6_t; 765 766 #define MPI_MANUFACTURING6_PAGEVERSION (0x00) 767 768 typedef struct _MPI_MANPAGE7_CONNECTOR_INFO 769 { 770 U32 Pinout; /* 00h */ 771 U8 Connector[16]; /* 04h */ 772 U8 Location; /* 14h */ 773 U8 Reserved1; /* 15h */ 774 U16 Slot; /* 16h */ 775 U32 Reserved2; /* 18h */ 776 } MPI_MANPAGE7_CONNECTOR_INFO, MPI_POINTER PTR_MPI_MANPAGE7_CONNECTOR_INFO, 777 MpiManPage7ConnectorInfo_t, MPI_POINTER pMpiManPage7ConnectorInfo_t; 778 779 /* defines for the Pinout field */ 780 #define MPI_MANPAGE7_PINOUT_SFF_8484_L4 (0x00080000) 781 #define MPI_MANPAGE7_PINOUT_SFF_8484_L3 (0x00040000) 782 #define MPI_MANPAGE7_PINOUT_SFF_8484_L2 (0x00020000) 783 #define MPI_MANPAGE7_PINOUT_SFF_8484_L1 (0x00010000) 784 #define MPI_MANPAGE7_PINOUT_SFF_8470_L4 (0x00000800) 785 #define MPI_MANPAGE7_PINOUT_SFF_8470_L3 (0x00000400) 786 #define MPI_MANPAGE7_PINOUT_SFF_8470_L2 (0x00000200) 787 #define MPI_MANPAGE7_PINOUT_SFF_8470_L1 (0x00000100) 788 #define MPI_MANPAGE7_PINOUT_SFF_8482 (0x00000002) 789 #define MPI_MANPAGE7_PINOUT_CONNECTION_UNKNOWN (0x00000001) 790 791 /* defines for the Location field */ 792 #define MPI_MANPAGE7_LOCATION_UNKNOWN (0x01) 793 #define MPI_MANPAGE7_LOCATION_INTERNAL (0x02) 794 #define MPI_MANPAGE7_LOCATION_EXTERNAL (0x04) 795 #define MPI_MANPAGE7_LOCATION_SWITCHABLE (0x08) 796 #define MPI_MANPAGE7_LOCATION_AUTO (0x10) 797 #define MPI_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 798 #define MPI_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 799 800 /* 801 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 802 * one and check NumPhys at runtime. 803 */ 804 #ifndef MPI_MANPAGE7_CONNECTOR_INFO_MAX 805 #define MPI_MANPAGE7_CONNECTOR_INFO_MAX (1) 806 #endif 807 808 typedef struct _CONFIG_PAGE_MANUFACTURING_7 809 { 810 CONFIG_PAGE_HEADER Header; /* 00h */ 811 U32 Reserved1; /* 04h */ 812 U32 Reserved2; /* 08h */ 813 U32 Flags; /* 0Ch */ 814 U8 EnclosureName[16]; /* 10h */ 815 U8 NumPhys; /* 20h */ 816 U8 Reserved3; /* 21h */ 817 U16 Reserved4; /* 22h */ 818 MPI_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI_MANPAGE7_CONNECTOR_INFO_MAX]; /* 24h */ 819 } CONFIG_PAGE_MANUFACTURING_7, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_7, 820 ManufacturingPage7_t, MPI_POINTER pManufacturingPage7_t; 821 822 #define MPI_MANUFACTURING7_PAGEVERSION (0x00) 823 824 /* defines for the Flags field */ 825 #define MPI_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 826 827 typedef struct _CONFIG_PAGE_MANUFACTURING_8 828 { 829 CONFIG_PAGE_HEADER Header; /* 00h */ 830 U32 ProductSpecificInfo;/* 04h */ 831 } CONFIG_PAGE_MANUFACTURING_8, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_8, 832 ManufacturingPage8_t, MPI_POINTER pManufacturingPage8_t; 833 834 #define MPI_MANUFACTURING8_PAGEVERSION (0x00) 835 836 typedef struct _CONFIG_PAGE_MANUFACTURING_9 837 { 838 CONFIG_PAGE_HEADER Header; /* 00h */ 839 U32 ProductSpecificInfo;/* 04h */ 840 } CONFIG_PAGE_MANUFACTURING_9, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_9, 841 ManufacturingPage9_t, MPI_POINTER pManufacturingPage9_t; 842 843 #define MPI_MANUFACTURING9_PAGEVERSION (0x00) 844 845 typedef struct _CONFIG_PAGE_MANUFACTURING_10 846 { 847 CONFIG_PAGE_HEADER Header; /* 00h */ 848 U32 ProductSpecificInfo;/* 04h */ 849 } CONFIG_PAGE_MANUFACTURING_10, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_10, 850 ManufacturingPage10_t, MPI_POINTER pManufacturingPage10_t; 851 852 #define MPI_MANUFACTURING10_PAGEVERSION (0x00) 853 854 /**************************************************************************** 855 * IO Unit Config Pages 856 ****************************************************************************/ 857 858 typedef struct _CONFIG_PAGE_IO_UNIT_0 859 { 860 CONFIG_PAGE_HEADER Header; /* 00h */ 861 U64 UniqueValue; /* 04h */ 862 } CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0, 863 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t; 864 865 #define MPI_IOUNITPAGE0_PAGEVERSION (0x00) 866 867 typedef struct _CONFIG_PAGE_IO_UNIT_1 868 { 869 CONFIG_PAGE_HEADER Header; /* 00h */ 870 U32 Flags; /* 04h */ 871 } CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1, 872 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t; 873 874 #define MPI_IOUNITPAGE1_PAGEVERSION (0x02) 875 876 /* IO Unit Page 1 Flags defines */ 877 #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000) 878 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001) 879 #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002) 880 #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000) 881 #define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 882 #define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING (0x00000020) 883 #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040) 884 #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080) 885 #define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 886 #define MPI_IOUNITPAGE1_SATA_WRITE_CACHE_DISABLE (0x00000200) 887 888 typedef struct _MPI_ADAPTER_INFO 889 { 890 U8 PciBusNumber; /* 00h */ 891 U8 PciDeviceAndFunctionNumber; /* 01h */ 892 U16 AdapterFlags; /* 02h */ 893 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO, 894 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t; 895 896 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 897 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 898 899 typedef struct _CONFIG_PAGE_IO_UNIT_2 900 { 901 CONFIG_PAGE_HEADER Header; /* 00h */ 902 U32 Flags; /* 04h */ 903 U32 BiosVersion; /* 08h */ 904 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */ 905 U32 Reserved1; /* 1Ch */ 906 } CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2, 907 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t; 908 909 #define MPI_IOUNITPAGE2_PAGEVERSION (0x02) 910 911 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002) 912 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004) 913 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008) 914 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010) 915 916 #define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 917 #define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 918 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY (0x00000020) 919 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 920 921 /* 922 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 923 * one and check Header.PageLength at runtime. 924 */ 925 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX 926 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 927 #endif 928 929 typedef struct _CONFIG_PAGE_IO_UNIT_3 930 { 931 CONFIG_PAGE_HEADER Header; /* 00h */ 932 U8 GPIOCount; /* 04h */ 933 U8 Reserved1; /* 05h */ 934 U16 Reserved2; /* 06h */ 935 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */ 936 } CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3, 937 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t; 938 939 #define MPI_IOUNITPAGE3_PAGEVERSION (0x01) 940 941 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC) 942 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 943 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00) 944 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01) 945 946 typedef struct _CONFIG_PAGE_IO_UNIT_4 947 { 948 CONFIG_PAGE_HEADER Header; /* 00h */ 949 U32 Reserved1; /* 04h */ 950 SGE_SIMPLE_UNION FWImageSGE; /* 08h */ 951 } CONFIG_PAGE_IO_UNIT_4, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_4, 952 IOUnitPage4_t, MPI_POINTER pIOUnitPage4_t; 953 954 #define MPI_IOUNITPAGE4_PAGEVERSION (0x00) 955 956 /**************************************************************************** 957 * IOC Config Pages 958 ****************************************************************************/ 959 960 typedef struct _CONFIG_PAGE_IOC_0 961 { 962 CONFIG_PAGE_HEADER Header; /* 00h */ 963 U32 TotalNVStore; /* 04h */ 964 U32 FreeNVStore; /* 08h */ 965 U16 VendorID; /* 0Ch */ 966 U16 DeviceID; /* 0Eh */ 967 U8 RevisionID; /* 10h */ 968 U8 Reserved[3]; /* 11h */ 969 U32 ClassCode; /* 14h */ 970 U16 SubsystemVendorID; /* 18h */ 971 U16 SubsystemID; /* 1Ah */ 972 } CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0, 973 IOCPage0_t, MPI_POINTER pIOCPage0_t; 974 975 #define MPI_IOCPAGE0_PAGEVERSION (0x01) 976 977 typedef struct _CONFIG_PAGE_IOC_1 978 { 979 CONFIG_PAGE_HEADER Header; /* 00h */ 980 U32 Flags; /* 04h */ 981 U32 CoalescingTimeout; /* 08h */ 982 U8 CoalescingDepth; /* 0Ch */ 983 U8 PCISlotNum; /* 0Dh */ 984 U8 Reserved[2]; /* 0Eh */ 985 } CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1, 986 IOCPage1_t, MPI_POINTER pIOCPage1_t; 987 988 #define MPI_IOCPAGE1_PAGEVERSION (0x03) 989 990 /* defines for the Flags field */ 991 #define MPI_IOCPAGE1_EEDP_MODE_MASK (0x07000000) 992 #define MPI_IOCPAGE1_EEDP_MODE_OFF (0x00000000) 993 #define MPI_IOCPAGE1_EEDP_MODE_T10 (0x01000000) 994 #define MPI_IOCPAGE1_EEDP_MODE_LSI_1 (0x02000000) 995 #define MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE (0x00000010) 996 #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001) 997 998 #define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 999 1000 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL 1001 { 1002 U8 VolumeID; /* 00h */ 1003 U8 VolumeBus; /* 01h */ 1004 U8 VolumeIOC; /* 02h */ 1005 U8 VolumePageNumber; /* 03h */ 1006 U8 VolumeType; /* 04h */ 1007 U8 Flags; /* 05h */ 1008 U16 Reserved3; /* 06h */ 1009 } CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL, 1010 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t; 1011 1012 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */ 1013 1014 #define MPI_RAID_VOL_TYPE_IS (0x00) 1015 #define MPI_RAID_VOL_TYPE_IME (0x01) 1016 #define MPI_RAID_VOL_TYPE_IM (0x02) 1017 #define MPI_RAID_VOL_TYPE_RAID_5 (0x03) 1018 #define MPI_RAID_VOL_TYPE_RAID_6 (0x04) 1019 #define MPI_RAID_VOL_TYPE_RAID_10 (0x05) 1020 #define MPI_RAID_VOL_TYPE_RAID_50 (0x06) 1021 #define MPI_RAID_VOL_TYPE_UNKNOWN (0xFF) 1022 1023 /* IOC Page 2 Volume Flags values */ 1024 1025 #define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08) 1026 1027 /* 1028 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1029 * one and check Header.PageLength at runtime. 1030 */ 1031 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX 1032 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1) 1033 #endif 1034 1035 typedef struct _CONFIG_PAGE_IOC_2 1036 { 1037 CONFIG_PAGE_HEADER Header; /* 00h */ 1038 U32 CapabilitiesFlags; /* 04h */ 1039 U8 NumActiveVolumes; /* 08h */ 1040 U8 MaxVolumes; /* 09h */ 1041 U8 NumActivePhysDisks; /* 0Ah */ 1042 U8 MaxPhysDisks; /* 0Bh */ 1043 CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */ 1044 } CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2, 1045 IOCPage2_t, MPI_POINTER pIOCPage2_t; 1046 1047 #define MPI_IOCPAGE2_PAGEVERSION (0x04) 1048 1049 /* IOC Page 2 Capabilities flags */ 1050 1051 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001) 1052 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002) 1053 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004) 1054 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_5_SUPPORT (0x00000008) 1055 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_6_SUPPORT (0x00000010) 1056 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_10_SUPPORT (0x00000020) 1057 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_50_SUPPORT (0x00000040) 1058 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_64_BIT_ADDRESSING (0x10000000) 1059 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000) 1060 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000) 1061 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000) 1062 1063 typedef struct _IOC_3_PHYS_DISK 1064 { 1065 U8 PhysDiskID; /* 00h */ 1066 U8 PhysDiskBus; /* 01h */ 1067 U8 PhysDiskIOC; /* 02h */ 1068 U8 PhysDiskNum; /* 03h */ 1069 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK, 1070 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t; 1071 1072 /* 1073 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1074 * one and check Header.PageLength at runtime. 1075 */ 1076 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX 1077 #define MPI_IOC_PAGE_3_PHYSDISK_MAX (1) 1078 #endif 1079 1080 typedef struct _CONFIG_PAGE_IOC_3 1081 { 1082 CONFIG_PAGE_HEADER Header; /* 00h */ 1083 U8 NumPhysDisks; /* 04h */ 1084 U8 Reserved1; /* 05h */ 1085 U16 Reserved2; /* 06h */ 1086 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */ 1087 } CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3, 1088 IOCPage3_t, MPI_POINTER pIOCPage3_t; 1089 1090 #define MPI_IOCPAGE3_PAGEVERSION (0x00) 1091 1092 typedef struct _IOC_4_SEP 1093 { 1094 U8 SEPTargetID; /* 00h */ 1095 U8 SEPBus; /* 01h */ 1096 U16 Reserved; /* 02h */ 1097 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP, 1098 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t; 1099 1100 /* 1101 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1102 * one and check Header.PageLength at runtime. 1103 */ 1104 #ifndef MPI_IOC_PAGE_4_SEP_MAX 1105 #define MPI_IOC_PAGE_4_SEP_MAX (1) 1106 #endif 1107 1108 typedef struct _CONFIG_PAGE_IOC_4 1109 { 1110 CONFIG_PAGE_HEADER Header; /* 00h */ 1111 U8 ActiveSEP; /* 04h */ 1112 U8 MaxSEP; /* 05h */ 1113 U16 Reserved1; /* 06h */ 1114 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */ 1115 } CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4, 1116 IOCPage4_t, MPI_POINTER pIOCPage4_t; 1117 1118 #define MPI_IOCPAGE4_PAGEVERSION (0x00) 1119 1120 typedef struct _IOC_5_HOT_SPARE 1121 { 1122 U8 PhysDiskNum; /* 00h */ 1123 U8 Reserved; /* 01h */ 1124 U8 HotSparePool; /* 02h */ 1125 U8 Flags; /* 03h */ 1126 } IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE, 1127 Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t; 1128 1129 /* IOC Page 5 HotSpare Flags */ 1130 #define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01) 1131 1132 /* 1133 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1134 * one and check Header.PageLength at runtime. 1135 */ 1136 #ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX 1137 #define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1) 1138 #endif 1139 1140 typedef struct _CONFIG_PAGE_IOC_5 1141 { 1142 CONFIG_PAGE_HEADER Header; /* 00h */ 1143 U32 Reserved1; /* 04h */ 1144 U8 NumHotSpares; /* 08h */ 1145 U8 Reserved2; /* 09h */ 1146 U16 Reserved3; /* 0Ah */ 1147 IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */ 1148 } CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5, 1149 IOCPage5_t, MPI_POINTER pIOCPage5_t; 1150 1151 #define MPI_IOCPAGE5_PAGEVERSION (0x00) 1152 1153 typedef struct _CONFIG_PAGE_IOC_6 1154 { 1155 CONFIG_PAGE_HEADER Header; /* 00h */ 1156 U32 CapabilitiesFlags; /* 04h */ 1157 U8 MaxDrivesIS; /* 08h */ 1158 U8 MaxDrivesIM; /* 09h */ 1159 U8 MaxDrivesIME; /* 0Ah */ 1160 U8 Reserved1; /* 0Bh */ 1161 U8 MinDrivesIS; /* 0Ch */ 1162 U8 MinDrivesIM; /* 0Dh */ 1163 U8 MinDrivesIME; /* 0Eh */ 1164 U8 Reserved2; /* 0Fh */ 1165 U8 MaxGlobalHotSpares; /* 10h */ 1166 U8 Reserved3; /* 11h */ 1167 U16 Reserved4; /* 12h */ 1168 U32 Reserved5; /* 14h */ 1169 U32 SupportedStripeSizeMapIS; /* 18h */ 1170 U32 SupportedStripeSizeMapIME; /* 1Ch */ 1171 U32 Reserved6; /* 20h */ 1172 U8 MetadataSize; /* 24h */ 1173 U8 Reserved7; /* 25h */ 1174 U16 Reserved8; /* 26h */ 1175 U16 MaxBadBlockTableEntries; /* 28h */ 1176 U16 Reserved9; /* 2Ah */ 1177 U16 IRNvsramUsage; /* 2Ch */ 1178 U16 Reserved10; /* 2Eh */ 1179 U32 IRNvsramVersion; /* 30h */ 1180 U32 Reserved11; /* 34h */ 1181 U32 Reserved12; /* 38h */ 1182 } CONFIG_PAGE_IOC_6, MPI_POINTER PTR_CONFIG_PAGE_IOC_6, 1183 IOCPage6_t, MPI_POINTER pIOCPage6_t; 1184 1185 #define MPI_IOCPAGE6_PAGEVERSION (0x01) 1186 1187 /* IOC Page 6 Capabilities Flags */ 1188 1189 #define MPI_IOCPAGE6_CAP_FLAGS_SSD_SUPPORT (0x00000020) 1190 #define MPI_IOCPAGE6_CAP_FLAGS_MULTIPORT_DRIVE_SUPPORT (0x00000010) 1191 #define MPI_IOCPAGE6_CAP_FLAGS_DISABLE_SMART_POLLING (0x00000008) 1192 1193 #define MPI_IOCPAGE6_CAP_FLAGS_MASK_METADATA_SIZE (0x00000006) 1194 #define MPI_IOCPAGE6_CAP_FLAGS_64MB_METADATA_SIZE (0x00000000) 1195 #define MPI_IOCPAGE6_CAP_FLAGS_512MB_METADATA_SIZE (0x00000002) 1196 1197 #define MPI_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1198 1199 /**************************************************************************** 1200 * BIOS Config Pages 1201 ****************************************************************************/ 1202 1203 typedef struct _CONFIG_PAGE_BIOS_1 1204 { 1205 CONFIG_PAGE_HEADER Header; /* 00h */ 1206 U32 BiosOptions; /* 04h */ 1207 U32 IOCSettings; /* 08h */ 1208 U32 Reserved1; /* 0Ch */ 1209 U32 DeviceSettings; /* 10h */ 1210 U16 NumberOfDevices; /* 14h */ 1211 U8 ExpanderSpinup; /* 16h */ 1212 U8 Reserved2; /* 17h */ 1213 U16 IOTimeoutBlockDevicesNonRM; /* 18h */ 1214 U16 IOTimeoutSequential; /* 1Ah */ 1215 U16 IOTimeoutOther; /* 1Ch */ 1216 U16 IOTimeoutBlockDevicesRM; /* 1Eh */ 1217 } CONFIG_PAGE_BIOS_1, MPI_POINTER PTR_CONFIG_PAGE_BIOS_1, 1218 BIOSPage1_t, MPI_POINTER pBIOSPage1_t; 1219 1220 #define MPI_BIOSPAGE1_PAGEVERSION (0x03) 1221 1222 /* values for the BiosOptions field */ 1223 #define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE (0x00000400) 1224 #define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE (0x00000200) 1225 #define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE (0x00000100) 1226 1227 #define MPI_BIOSPAGE1_OPTIONS_SCAN_HIGH_TO_LOW (0x00000002) 1228 #define MPI_BIOSPAGE1_OPTIONS_SCAN_LOW_TO_HIGH (0x00000000) 1229 1230 #define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1231 1232 /* values for the IOCSettings field */ 1233 #define MPI_BIOSPAGE1_IOCSET_MASK_INITIAL_SPINUP_DELAY (0x0F000000) 1234 #define MPI_BIOSPAGE1_IOCSET_SHIFT_INITIAL_SPINUP_DELAY (24) 1235 1236 #define MPI_BIOSPAGE1_IOCSET_MASK_PORT_ENABLE_DELAY (0x00F00000) 1237 #define MPI_BIOSPAGE1_IOCSET_SHIFT_PORT_ENABLE_DELAY (20) 1238 1239 #define MPI_BIOSPAGE1_IOCSET_AUTO_PORT_ENABLE (0x00080000) 1240 #define MPI_BIOSPAGE1_IOCSET_DIRECT_ATTACH_SPINUP_MODE (0x00040000) 1241 1242 #define MPI_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1243 #define MPI_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1244 #define MPI_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1245 1246 #define MPI_BIOSPAGE1_IOCSET_MASK_MAX_TARGET_SPIN_UP (0x0000F000) 1247 #define MPI_BIOSPAGE1_IOCSET_SHIFT_MAX_TARGET_SPIN_UP (12) 1248 1249 #define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY (0x00000F00) 1250 #define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY (8) 1251 1252 #define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1253 #define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1254 #define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1255 #define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1256 1257 #define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1258 #define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1259 #define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1260 #define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1261 #define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1262 1263 #define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1264 1265 /* values for the DeviceSettings field */ 1266 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1267 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1268 #define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1269 #define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1270 #define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1271 1272 /* defines for the ExpanderSpinup field */ 1273 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_MAX_TARGET (0xF0) 1274 #define MPI_BIOSPAGE1_EXPSPINUP_SHIFT_MAX_TARGET (4) 1275 #define MPI_BIOSPAGE1_EXPSPINUP_MASK_DELAY (0x0F) 1276 1277 typedef struct _MPI_BOOT_DEVICE_ADAPTER_ORDER 1278 { 1279 U32 Reserved1; /* 00h */ 1280 U32 Reserved2; /* 04h */ 1281 U32 Reserved3; /* 08h */ 1282 U32 Reserved4; /* 0Ch */ 1283 U32 Reserved5; /* 10h */ 1284 U32 Reserved6; /* 14h */ 1285 U32 Reserved7; /* 18h */ 1286 U32 Reserved8; /* 1Ch */ 1287 U32 Reserved9; /* 20h */ 1288 U32 Reserved10; /* 24h */ 1289 U32 Reserved11; /* 28h */ 1290 U32 Reserved12; /* 2Ch */ 1291 U32 Reserved13; /* 30h */ 1292 U32 Reserved14; /* 34h */ 1293 U32 Reserved15; /* 38h */ 1294 U32 Reserved16; /* 3Ch */ 1295 U32 Reserved17; /* 40h */ 1296 } MPI_BOOT_DEVICE_ADAPTER_ORDER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_ORDER; 1297 1298 typedef struct _MPI_BOOT_DEVICE_ADAPTER_NUMBER 1299 { 1300 U8 TargetID; /* 00h */ 1301 U8 Bus; /* 01h */ 1302 U8 AdapterNumber; /* 02h */ 1303 U8 Reserved1; /* 03h */ 1304 U32 Reserved2; /* 04h */ 1305 U32 Reserved3; /* 08h */ 1306 U32 Reserved4; /* 0Ch */ 1307 U8 LUN[8]; /* 10h */ 1308 U32 Reserved5; /* 18h */ 1309 U32 Reserved6; /* 1Ch */ 1310 U32 Reserved7; /* 20h */ 1311 U32 Reserved8; /* 24h */ 1312 U32 Reserved9; /* 28h */ 1313 U32 Reserved10; /* 2Ch */ 1314 U32 Reserved11; /* 30h */ 1315 U32 Reserved12; /* 34h */ 1316 U32 Reserved13; /* 38h */ 1317 U32 Reserved14; /* 3Ch */ 1318 U32 Reserved15; /* 40h */ 1319 } MPI_BOOT_DEVICE_ADAPTER_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_NUMBER; 1320 1321 typedef struct _MPI_BOOT_DEVICE_PCI_ADDRESS 1322 { 1323 U8 TargetID; /* 00h */ 1324 U8 Bus; /* 01h */ 1325 U16 PCIAddress; /* 02h */ 1326 U32 Reserved1; /* 04h */ 1327 U32 Reserved2; /* 08h */ 1328 U32 Reserved3; /* 0Ch */ 1329 U8 LUN[8]; /* 10h */ 1330 U32 Reserved4; /* 18h */ 1331 U32 Reserved5; /* 1Ch */ 1332 U32 Reserved6; /* 20h */ 1333 U32 Reserved7; /* 24h */ 1334 U32 Reserved8; /* 28h */ 1335 U32 Reserved9; /* 2Ch */ 1336 U32 Reserved10; /* 30h */ 1337 U32 Reserved11; /* 34h */ 1338 U32 Reserved12; /* 38h */ 1339 U32 Reserved13; /* 3Ch */ 1340 U32 Reserved14; /* 40h */ 1341 } MPI_BOOT_DEVICE_PCI_ADDRESS, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_ADDRESS; 1342 1343 typedef struct _MPI_BOOT_DEVICE_SLOT_NUMBER 1344 { 1345 U8 TargetID; /* 00h */ 1346 U8 Bus; /* 01h */ 1347 U8 PCISlotNumber; /* 02h */ 1348 U8 Reserved1; /* 03h */ 1349 U32 Reserved2; /* 04h */ 1350 U32 Reserved3; /* 08h */ 1351 U32 Reserved4; /* 0Ch */ 1352 U8 LUN[8]; /* 10h */ 1353 U32 Reserved5; /* 18h */ 1354 U32 Reserved6; /* 1Ch */ 1355 U32 Reserved7; /* 20h */ 1356 U32 Reserved8; /* 24h */ 1357 U32 Reserved9; /* 28h */ 1358 U32 Reserved10; /* 2Ch */ 1359 U32 Reserved11; /* 30h */ 1360 U32 Reserved12; /* 34h */ 1361 U32 Reserved13; /* 38h */ 1362 U32 Reserved14; /* 3Ch */ 1363 U32 Reserved15; /* 40h */ 1364 } MPI_BOOT_DEVICE_PCI_SLOT_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_SLOT_NUMBER; 1365 1366 typedef struct _MPI_BOOT_DEVICE_FC_WWN 1367 { 1368 U64 WWPN; /* 00h */ 1369 U32 Reserved1; /* 08h */ 1370 U32 Reserved2; /* 0Ch */ 1371 U8 LUN[8]; /* 10h */ 1372 U32 Reserved3; /* 18h */ 1373 U32 Reserved4; /* 1Ch */ 1374 U32 Reserved5; /* 20h */ 1375 U32 Reserved6; /* 24h */ 1376 U32 Reserved7; /* 28h */ 1377 U32 Reserved8; /* 2Ch */ 1378 U32 Reserved9; /* 30h */ 1379 U32 Reserved10; /* 34h */ 1380 U32 Reserved11; /* 38h */ 1381 U32 Reserved12; /* 3Ch */ 1382 U32 Reserved13; /* 40h */ 1383 } MPI_BOOT_DEVICE_FC_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_FC_WWN; 1384 1385 typedef struct _MPI_BOOT_DEVICE_SAS_WWN 1386 { 1387 U64 SASAddress; /* 00h */ 1388 U32 Reserved1; /* 08h */ 1389 U32 Reserved2; /* 0Ch */ 1390 U8 LUN[8]; /* 10h */ 1391 U32 Reserved3; /* 18h */ 1392 U32 Reserved4; /* 1Ch */ 1393 U32 Reserved5; /* 20h */ 1394 U32 Reserved6; /* 24h */ 1395 U32 Reserved7; /* 28h */ 1396 U32 Reserved8; /* 2Ch */ 1397 U32 Reserved9; /* 30h */ 1398 U32 Reserved10; /* 34h */ 1399 U32 Reserved11; /* 38h */ 1400 U32 Reserved12; /* 3Ch */ 1401 U32 Reserved13; /* 40h */ 1402 } MPI_BOOT_DEVICE_SAS_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_SAS_WWN; 1403 1404 typedef struct _MPI_BOOT_DEVICE_ENCLOSURE_SLOT 1405 { 1406 U64 EnclosureLogicalID; /* 00h */ 1407 U32 Reserved1; /* 08h */ 1408 U32 Reserved2; /* 0Ch */ 1409 U8 LUN[8]; /* 10h */ 1410 U16 SlotNumber; /* 18h */ 1411 U16 Reserved3; /* 1Ah */ 1412 U32 Reserved4; /* 1Ch */ 1413 U32 Reserved5; /* 20h */ 1414 U32 Reserved6; /* 24h */ 1415 U32 Reserved7; /* 28h */ 1416 U32 Reserved8; /* 2Ch */ 1417 U32 Reserved9; /* 30h */ 1418 U32 Reserved10; /* 34h */ 1419 U32 Reserved11; /* 38h */ 1420 U32 Reserved12; /* 3Ch */ 1421 U32 Reserved13; /* 40h */ 1422 } MPI_BOOT_DEVICE_ENCLOSURE_SLOT, 1423 MPI_POINTER PTR_MPI_BOOT_DEVICE_ENCLOSURE_SLOT; 1424 1425 typedef union _MPI_BIOSPAGE2_BOOT_DEVICE 1426 { 1427 MPI_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1428 MPI_BOOT_DEVICE_ADAPTER_NUMBER AdapterNumber; 1429 MPI_BOOT_DEVICE_PCI_ADDRESS PCIAddress; 1430 MPI_BOOT_DEVICE_PCI_SLOT_NUMBER PCISlotNumber; 1431 MPI_BOOT_DEVICE_FC_WWN FcWwn; 1432 MPI_BOOT_DEVICE_SAS_WWN SasWwn; 1433 MPI_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1434 } MPI_BIOSPAGE2_BOOT_DEVICE, MPI_POINTER PTR_MPI_BIOSPAGE2_BOOT_DEVICE; 1435 1436 typedef struct _CONFIG_PAGE_BIOS_2 1437 { 1438 CONFIG_PAGE_HEADER Header; /* 00h */ 1439 U32 Reserved1; /* 04h */ 1440 U32 Reserved2; /* 08h */ 1441 U32 Reserved3; /* 0Ch */ 1442 U32 Reserved4; /* 10h */ 1443 U32 Reserved5; /* 14h */ 1444 U32 Reserved6; /* 18h */ 1445 U8 BootDeviceForm; /* 1Ch */ 1446 U8 PrevBootDeviceForm; /* 1Ch */ 1447 U16 Reserved8; /* 1Eh */ 1448 MPI_BIOSPAGE2_BOOT_DEVICE BootDevice; /* 20h */ 1449 } CONFIG_PAGE_BIOS_2, MPI_POINTER PTR_CONFIG_PAGE_BIOS_2, 1450 BIOSPage2_t, MPI_POINTER pBIOSPage2_t; 1451 1452 #define MPI_BIOSPAGE2_PAGEVERSION (0x02) 1453 1454 #define MPI_BIOSPAGE2_FORM_MASK (0x0F) 1455 #define MPI_BIOSPAGE2_FORM_ADAPTER_ORDER (0x00) 1456 #define MPI_BIOSPAGE2_FORM_ADAPTER_NUMBER (0x01) 1457 #define MPI_BIOSPAGE2_FORM_PCI_ADDRESS (0x02) 1458 #define MPI_BIOSPAGE2_FORM_PCI_SLOT_NUMBER (0x03) 1459 #define MPI_BIOSPAGE2_FORM_FC_WWN (0x04) 1460 #define MPI_BIOSPAGE2_FORM_SAS_WWN (0x05) 1461 #define MPI_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1462 1463 typedef struct _CONFIG_PAGE_BIOS_4 1464 { 1465 CONFIG_PAGE_HEADER Header; /* 00h */ 1466 U64 ReassignmentBaseWWID; /* 04h */ 1467 } CONFIG_PAGE_BIOS_4, MPI_POINTER PTR_CONFIG_PAGE_BIOS_4, 1468 BIOSPage4_t, MPI_POINTER pBIOSPage4_t; 1469 1470 #define MPI_BIOSPAGE4_PAGEVERSION (0x00) 1471 1472 /**************************************************************************** 1473 * SCSI Port Config Pages 1474 ****************************************************************************/ 1475 1476 typedef struct _CONFIG_PAGE_SCSI_PORT_0 1477 { 1478 CONFIG_PAGE_HEADER Header; /* 00h */ 1479 U32 Capabilities; /* 04h */ 1480 U32 PhysicalInterface; /* 08h */ 1481 } CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0, 1482 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t; 1483 1484 #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x02) 1485 1486 #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001) 1487 #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002) 1488 #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004) 1489 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 1490 #define MPI_SCSIPORTPAGE0_SYNC_ASYNC (0x00) 1491 #define MPI_SCSIPORTPAGE0_SYNC_5 (0x32) 1492 #define MPI_SCSIPORTPAGE0_SYNC_10 (0x19) 1493 #define MPI_SCSIPORTPAGE0_SYNC_20 (0x0C) 1494 #define MPI_SCSIPORTPAGE0_SYNC_33_33 (0x0B) 1495 #define MPI_SCSIPORTPAGE0_SYNC_40 (0x0A) 1496 #define MPI_SCSIPORTPAGE0_SYNC_80 (0x09) 1497 #define MPI_SCSIPORTPAGE0_SYNC_160 (0x08) 1498 #define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN (0xFF) 1499 1500 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD (8) 1501 #define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap) \ 1502 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK) \ 1503 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD \ 1504 ) 1505 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 1506 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET (16) 1507 #define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap) \ 1508 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK) \ 1509 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET \ 1510 ) 1511 #define MPI_SCSIPORTPAGE0_CAP_IDP (0x08000000) 1512 #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000) 1513 #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000) 1514 1515 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003) 1516 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01) 1517 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02) 1518 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03) 1519 #define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000) 1520 #define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24) 1521 #define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE) 1522 #define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF) 1523 1524 typedef struct _CONFIG_PAGE_SCSI_PORT_1 1525 { 1526 CONFIG_PAGE_HEADER Header; /* 00h */ 1527 U32 Configuration; /* 04h */ 1528 U32 OnBusTimerValue; /* 08h */ 1529 U8 TargetConfig; /* 0Ch */ 1530 U8 Reserved1; /* 0Dh */ 1531 U16 IDConfig; /* 0Eh */ 1532 } CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1, 1533 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t; 1534 1535 #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03) 1536 1537 /* Configuration values */ 1538 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF) 1539 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000) 1540 #define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID (16) 1541 1542 /* TargetConfig values */ 1543 #define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01) 1544 #define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG (0x02) 1545 1546 typedef struct _MPI_DEVICE_INFO 1547 { 1548 U8 Timeout; /* 00h */ 1549 U8 SyncFactor; /* 01h */ 1550 U16 DeviceFlags; /* 02h */ 1551 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO, 1552 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t; 1553 1554 typedef struct _CONFIG_PAGE_SCSI_PORT_2 1555 { 1556 CONFIG_PAGE_HEADER Header; /* 00h */ 1557 U32 PortFlags; /* 04h */ 1558 U32 PortSettings; /* 08h */ 1559 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */ 1560 } CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2, 1561 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t; 1562 1563 #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x02) 1564 1565 /* PortFlags values */ 1566 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001) 1567 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004) 1568 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1569 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010) 1570 1571 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK (0x00000060) 1572 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV (0x00000000) 1573 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020) 1574 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060) 1575 1576 /* PortSettings values */ 1577 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F) 1578 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030) 1579 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000) 1580 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010) 1581 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020) 1582 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030) 1583 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0) 1584 #define MPI_SCSIPORTPAGE2_PORT_RM_NONE (0x00000000) 1585 #define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY (0x00000040) 1586 #define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA (0x00000080) 1587 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00) 1588 #define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY (8) 1589 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000) 1590 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000) 1591 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000) 1592 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000) 1593 1594 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001) 1595 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002) 1596 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004) 1597 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008) 1598 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010) 1599 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020) 1600 1601 /**************************************************************************** 1602 * SCSI Target Device Config Pages 1603 ****************************************************************************/ 1604 1605 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0 1606 { 1607 CONFIG_PAGE_HEADER Header; /* 00h */ 1608 U32 NegotiatedParameters; /* 04h */ 1609 U32 Information; /* 08h */ 1610 } CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0, 1611 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t; 1612 1613 #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x04) 1614 1615 #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001) 1616 #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002) 1617 #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004) 1618 #define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008) 1619 #define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010) 1620 #define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020) 1621 #define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040) 1622 #define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080) 1623 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00) 1624 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD (8) 1625 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000) 1626 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET (16) 1627 #define MPI_SCSIDEVPAGE0_NP_IDP (0x08000000) 1628 #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000) 1629 #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000) 1630 1631 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001) 1632 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002) 1633 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004) 1634 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008) 1635 1636 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1 1637 { 1638 CONFIG_PAGE_HEADER Header; /* 00h */ 1639 U32 RequestedParameters; /* 04h */ 1640 U32 Reserved; /* 08h */ 1641 U32 Configuration; /* 0Ch */ 1642 } CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1, 1643 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t; 1644 1645 #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x05) 1646 1647 #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001) 1648 #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002) 1649 #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004) 1650 #define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008) 1651 #define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010) 1652 #define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020) 1653 #define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040) 1654 #define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080) 1655 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00) 1656 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD (8) 1657 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000) 1658 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET (16) 1659 #define MPI_SCSIDEVPAGE1_RP_IDP (0x08000000) 1660 #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000) 1661 #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000) 1662 1663 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002) 1664 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004) 1665 #define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008) 1666 #define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010) 1667 1668 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2 1669 { 1670 CONFIG_PAGE_HEADER Header; /* 00h */ 1671 U32 DomainValidation; /* 04h */ 1672 U32 ParityPipeSelect; /* 08h */ 1673 U32 DataPipeSelect; /* 0Ch */ 1674 } CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2, 1675 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t; 1676 1677 #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01) 1678 1679 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010) 1680 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020) 1681 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380) 1682 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00) 1683 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000) 1684 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000) 1685 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000) 1686 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000) 1687 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000) 1688 1689 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003) 1690 1691 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003) 1692 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C) 1693 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030) 1694 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0) 1695 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300) 1696 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00) 1697 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000) 1698 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000) 1699 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000) 1700 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000) 1701 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000) 1702 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000) 1703 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000) 1704 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000) 1705 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000) 1706 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000) 1707 1708 typedef struct _CONFIG_PAGE_SCSI_DEVICE_3 1709 { 1710 CONFIG_PAGE_HEADER Header; /* 00h */ 1711 U16 MsgRejectCount; /* 04h */ 1712 U16 PhaseErrorCount; /* 06h */ 1713 U16 ParityErrorCount; /* 08h */ 1714 U16 Reserved; /* 0Ah */ 1715 } CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3, 1716 SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t; 1717 1718 #define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00) 1719 1720 #define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE) 1721 #define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF) 1722 1723 /**************************************************************************** 1724 * FC Port Config Pages 1725 ****************************************************************************/ 1726 1727 typedef struct _CONFIG_PAGE_FC_PORT_0 1728 { 1729 CONFIG_PAGE_HEADER Header; /* 00h */ 1730 U32 Flags; /* 04h */ 1731 U8 MPIPortNumber; /* 08h */ 1732 U8 LinkType; /* 09h */ 1733 U8 PortState; /* 0Ah */ 1734 U8 Reserved; /* 0Bh */ 1735 U32 PortIdentifier; /* 0Ch */ 1736 U64 WWNN; /* 10h */ 1737 U64 WWPN; /* 18h */ 1738 U32 SupportedServiceClass; /* 20h */ 1739 U32 SupportedSpeeds; /* 24h */ 1740 U32 CurrentSpeed; /* 28h */ 1741 U32 MaxFrameSize; /* 2Ch */ 1742 U64 FabricWWNN; /* 30h */ 1743 U64 FabricWWPN; /* 38h */ 1744 U32 DiscoveredPortsCount; /* 40h */ 1745 U32 MaxInitiators; /* 44h */ 1746 U8 MaxAliasesSupported; /* 48h */ 1747 U8 MaxHardAliasesSupported; /* 49h */ 1748 U8 NumCurrentAliases; /* 4Ah */ 1749 U8 Reserved1; /* 4Bh */ 1750 } CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0, 1751 FCPortPage0_t, MPI_POINTER pFCPortPage0_t; 1752 1753 #define MPI_FCPORTPAGE0_PAGEVERSION (0x02) 1754 1755 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F) 1756 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR) 1757 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET) 1758 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN) 1759 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR) 1760 1761 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010) 1762 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020) 1763 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040) 1764 1765 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00) 1766 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000) 1767 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100) 1768 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200) 1769 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400) 1770 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800) 1771 1772 #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00) 1773 #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01) 1774 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02) 1775 #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03) 1776 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04) 1777 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05) 1778 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06) 1779 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07) 1780 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08) 1781 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09) 1782 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A) 1783 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B) 1784 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C) 1785 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D) 1786 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E) 1787 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F) 1788 1789 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */ 1790 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */ 1791 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */ 1792 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */ 1793 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */ 1794 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */ 1795 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */ 1796 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */ 1797 1798 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001) 1799 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002) 1800 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004) 1801 1802 #define MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN (0x00000000) /* (SNIA)HBA_PORTSPEED_UNKNOWN 0 Unknown - transceiver incapable of reporting */ 1803 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */ 1804 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */ 1805 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */ 1806 #define MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED (0x00000008) /* (SNIA)HBA_PORTSPEED_4GBIT 8 4 GBit/sec */ 1807 1808 #define MPI_FCPORTPAGE0_CURRENT_SPEED_UKNOWN MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN 1809 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED 1810 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED 1811 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED 1812 #define MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED 1813 #define MPI_FCPORTPAGE0_CURRENT_SPEED_NOT_NEGOTIATED (0x00008000) /* (SNIA)HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) Speed not established */ 1814 1815 typedef struct _CONFIG_PAGE_FC_PORT_1 1816 { 1817 CONFIG_PAGE_HEADER Header; /* 00h */ 1818 U32 Flags; /* 04h */ 1819 U64 NoSEEPROMWWNN; /* 08h */ 1820 U64 NoSEEPROMWWPN; /* 10h */ 1821 U8 HardALPA; /* 18h */ 1822 U8 LinkConfig; /* 19h */ 1823 U8 TopologyConfig; /* 1Ah */ 1824 U8 AltConnector; /* 1Bh */ 1825 U8 NumRequestedAliases; /* 1Ch */ 1826 U8 RR_TOV; /* 1Dh */ 1827 U8 InitiatorDeviceTimeout; /* 1Eh */ 1828 U8 InitiatorIoPendTimeout; /* 1Fh */ 1829 } CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1, 1830 FCPortPage1_t, MPI_POINTER pFCPortPage1_t; 1831 1832 #define MPI_FCPORTPAGE1_PAGEVERSION (0x06) 1833 1834 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000) 1835 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000) 1836 #define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000) 1837 #define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000) 1838 #define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000) 1839 #define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE (0x00400000) 1840 #define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK (0x00200000) 1841 #define MPI_FCPORTPAGE1_FLAGS_TARGET_LARGE_CDB_ENABLE (0x00000080) 1842 #define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070) 1843 #define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG (0x00000008) 1844 #define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO (0x00000004) 1845 #define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002) 1846 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001) 1847 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000) 1848 1849 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000) 1850 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28) 1851 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1852 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1853 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1854 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT) 1855 1856 #define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000) 1857 #define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010) 1858 #define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030) 1859 #define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050) 1860 1861 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF) 1862 1863 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F) 1864 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00) 1865 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01) 1866 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02) 1867 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03) 1868 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F) 1869 1870 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F) 1871 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01) 1872 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02) 1873 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F) 1874 1875 #define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00) 1876 1877 #define MPI_FCPORTPAGE1_INITIATOR_DEV_TIMEOUT_MASK (0x7F) 1878 #define MPI_FCPORTPAGE1_INITIATOR_DEV_UNIT_16 (0x80) 1879 1880 typedef struct _CONFIG_PAGE_FC_PORT_2 1881 { 1882 CONFIG_PAGE_HEADER Header; /* 00h */ 1883 U8 NumberActive; /* 04h */ 1884 U8 ALPA[127]; /* 05h */ 1885 } CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2, 1886 FCPortPage2_t, MPI_POINTER pFCPortPage2_t; 1887 1888 #define MPI_FCPORTPAGE2_PAGEVERSION (0x01) 1889 1890 typedef struct _WWN_FORMAT 1891 { 1892 U64 WWNN; /* 00h */ 1893 U64 WWPN; /* 08h */ 1894 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT, 1895 WWNFormat, MPI_POINTER pWWNFormat; 1896 1897 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID 1898 { 1899 WWN_FORMAT WWN; 1900 U32 Did; 1901 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID, 1902 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t; 1903 1904 typedef struct _FC_PORT_PERSISTENT 1905 { 1906 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */ 1907 U8 TargetID; /* 10h */ 1908 U8 Bus; /* 11h */ 1909 U16 Flags; /* 12h */ 1910 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT, 1911 PersistentData_t, MPI_POINTER pPersistentData_t; 1912 1913 #define MPI_PERSISTENT_FLAGS_SHIFT (16) 1914 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001) 1915 #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002) 1916 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004) 1917 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008) 1918 #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080) 1919 1920 /* 1921 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1922 * one and check Header.PageLength at runtime. 1923 */ 1924 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX 1925 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1) 1926 #endif 1927 1928 typedef struct _CONFIG_PAGE_FC_PORT_3 1929 { 1930 CONFIG_PAGE_HEADER Header; /* 00h */ 1931 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */ 1932 } CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3, 1933 FCPortPage3_t, MPI_POINTER pFCPortPage3_t; 1934 1935 #define MPI_FCPORTPAGE3_PAGEVERSION (0x01) 1936 1937 typedef struct _CONFIG_PAGE_FC_PORT_4 1938 { 1939 CONFIG_PAGE_HEADER Header; /* 00h */ 1940 U32 PortFlags; /* 04h */ 1941 U32 PortSettings; /* 08h */ 1942 } CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4, 1943 FCPortPage4_t, MPI_POINTER pFCPortPage4_t; 1944 1945 #define MPI_FCPORTPAGE4_PAGEVERSION (0x00) 1946 1947 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008) 1948 1949 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030) 1950 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000) 1951 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010) 1952 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020) 1953 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030) 1954 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0) 1955 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00) 1956 1957 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO 1958 { 1959 U8 Flags; /* 00h */ 1960 U8 AliasAlpa; /* 01h */ 1961 U16 Reserved; /* 02h */ 1962 U64 AliasWWNN; /* 04h */ 1963 U64 AliasWWPN; /* 0Ch */ 1964 } CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1965 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO, 1966 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t; 1967 1968 typedef struct _CONFIG_PAGE_FC_PORT_5 1969 { 1970 CONFIG_PAGE_HEADER Header; /* 00h */ 1971 CONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */ 1972 } CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5, 1973 FCPortPage5_t, MPI_POINTER pFCPortPage5_t; 1974 1975 #define MPI_FCPORTPAGE5_PAGEVERSION (0x02) 1976 1977 #define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01) 1978 #define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02) 1979 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04) 1980 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08) 1981 #define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10) 1982 1983 typedef struct _CONFIG_PAGE_FC_PORT_6 1984 { 1985 CONFIG_PAGE_HEADER Header; /* 00h */ 1986 U32 Reserved; /* 04h */ 1987 U64 TimeSinceReset; /* 08h */ 1988 U64 TxFrames; /* 10h */ 1989 U64 RxFrames; /* 18h */ 1990 U64 TxWords; /* 20h */ 1991 U64 RxWords; /* 28h */ 1992 U64 LipCount; /* 30h */ 1993 U64 NosCount; /* 38h */ 1994 U64 ErrorFrames; /* 40h */ 1995 U64 DumpedFrames; /* 48h */ 1996 U64 LinkFailureCount; /* 50h */ 1997 U64 LossOfSyncCount; /* 58h */ 1998 U64 LossOfSignalCount; /* 60h */ 1999 U64 PrimativeSeqErrCount; /* 68h */ 2000 U64 InvalidTxWordCount; /* 70h */ 2001 U64 InvalidCrcCount; /* 78h */ 2002 U64 FcpInitiatorIoCount; /* 80h */ 2003 } CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6, 2004 FCPortPage6_t, MPI_POINTER pFCPortPage6_t; 2005 2006 #define MPI_FCPORTPAGE6_PAGEVERSION (0x00) 2007 2008 typedef struct _CONFIG_PAGE_FC_PORT_7 2009 { 2010 CONFIG_PAGE_HEADER Header; /* 00h */ 2011 U32 Reserved; /* 04h */ 2012 U8 PortSymbolicName[256]; /* 08h */ 2013 } CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7, 2014 FCPortPage7_t, MPI_POINTER pFCPortPage7_t; 2015 2016 #define MPI_FCPORTPAGE7_PAGEVERSION (0x00) 2017 2018 typedef struct _CONFIG_PAGE_FC_PORT_8 2019 { 2020 CONFIG_PAGE_HEADER Header; /* 00h */ 2021 U32 BitVector[8]; /* 04h */ 2022 } CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8, 2023 FCPortPage8_t, MPI_POINTER pFCPortPage8_t; 2024 2025 #define MPI_FCPORTPAGE8_PAGEVERSION (0x00) 2026 2027 typedef struct _CONFIG_PAGE_FC_PORT_9 2028 { 2029 CONFIG_PAGE_HEADER Header; /* 00h */ 2030 U32 Reserved; /* 04h */ 2031 U64 GlobalWWPN; /* 08h */ 2032 U64 GlobalWWNN; /* 10h */ 2033 U32 UnitType; /* 18h */ 2034 U32 PhysicalPortNumber; /* 1Ch */ 2035 U32 NumAttachedNodes; /* 20h */ 2036 U16 IPVersion; /* 24h */ 2037 U16 UDPPortNumber; /* 26h */ 2038 U8 IPAddress[16]; /* 28h */ 2039 U16 Reserved1; /* 38h */ 2040 U16 TopologyDiscoveryFlags; /* 3Ah */ 2041 } CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9, 2042 FCPortPage9_t, MPI_POINTER pFCPortPage9_t; 2043 2044 #define MPI_FCPORTPAGE9_PAGEVERSION (0x00) 2045 2046 typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA 2047 { 2048 U8 Id; /* 10h */ 2049 U8 ExtId; /* 11h */ 2050 U8 Connector; /* 12h */ 2051 U8 Transceiver[8]; /* 13h */ 2052 U8 Encoding; /* 1Bh */ 2053 U8 BitRate_100mbs; /* 1Ch */ 2054 U8 Reserved1; /* 1Dh */ 2055 U8 Length9u_km; /* 1Eh */ 2056 U8 Length9u_100m; /* 1Fh */ 2057 U8 Length50u_10m; /* 20h */ 2058 U8 Length62p5u_10m; /* 21h */ 2059 U8 LengthCopper_m; /* 22h */ 2060 U8 Reseverved2; /* 22h */ 2061 U8 VendorName[16]; /* 24h */ 2062 U8 Reserved3; /* 34h */ 2063 U8 VendorOUI[3]; /* 35h */ 2064 U8 VendorPN[16]; /* 38h */ 2065 U8 VendorRev[4]; /* 48h */ 2066 U16 Wavelength; /* 4Ch */ 2067 U8 Reserved4; /* 4Eh */ 2068 U8 CC_BASE; /* 4Fh */ 2069 } CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA, 2070 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA, 2071 FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t; 2072 2073 #define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00) 2074 #define MPI_FCPORT10_BASE_ID_GBIC (0x01) 2075 #define MPI_FCPORT10_BASE_ID_FIXED (0x02) 2076 #define MPI_FCPORT10_BASE_ID_SFP (0x03) 2077 #define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04) 2078 #define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F) 2079 #define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80) 2080 2081 #define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00) 2082 #define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01) 2083 #define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02) 2084 #define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03) 2085 #define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04) 2086 #define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05) 2087 #define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06) 2088 #define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07) 2089 #define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80) 2090 2091 #define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00) 2092 #define MPI_FCPORT10_BASE_CONN_SC (0x01) 2093 #define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02) 2094 #define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03) 2095 #define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04) 2096 #define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05) 2097 #define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06) 2098 #define MPI_FCPORT10_BASE_CONN_LC (0x07) 2099 #define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08) 2100 #define MPI_FCPORT10_BASE_CONN_MU (0x09) 2101 #define MPI_FCPORT10_BASE_CONN_SG (0x0A) 2102 #define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B) 2103 #define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C) 2104 #define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F) 2105 #define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20) 2106 #define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21) 2107 #define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22) 2108 #define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F) 2109 #define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80) 2110 2111 #define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00) 2112 #define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01) 2113 #define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02) 2114 #define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03) 2115 #define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04) 2116 2117 typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA 2118 { 2119 U8 Options[2]; /* 50h */ 2120 U8 BitRateMax; /* 52h */ 2121 U8 BitRateMin; /* 53h */ 2122 U8 VendorSN[16]; /* 54h */ 2123 U8 DateCode[8]; /* 64h */ 2124 U8 DiagMonitoringType; /* 6Ch */ 2125 U8 EnhancedOptions; /* 6Dh */ 2126 U8 SFF8472Compliance; /* 6Eh */ 2127 U8 CC_EXT; /* 6Fh */ 2128 } CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA, 2129 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA, 2130 FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t; 2131 2132 #define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20) 2133 #define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10) 2134 #define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08) 2135 #define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04) 2136 #define MPI_FCPORT10_EXT_OPTION1_LOS (0x02) 2137 2138 typedef struct _CONFIG_PAGE_FC_PORT_10 2139 { 2140 CONFIG_PAGE_HEADER Header; /* 00h */ 2141 U8 Flags; /* 04h */ 2142 U8 Reserved1; /* 05h */ 2143 U16 Reserved2; /* 06h */ 2144 U32 HwConfig1; /* 08h */ 2145 U32 HwConfig2; /* 0Ch */ 2146 CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */ 2147 CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */ 2148 U8 VendorSpecific[32]; /* 70h */ 2149 } CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10, 2150 FCPortPage10_t, MPI_POINTER pFCPortPage10_t; 2151 2152 #define MPI_FCPORTPAGE10_PAGEVERSION (0x01) 2153 2154 /* standard MODDEF pin definitions (from GBIC spec.) */ 2155 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007) 2156 #define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001) 2157 #define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002) 2158 #define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004) 2159 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007) 2160 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006) 2161 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005) 2162 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004) 2163 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003) 2164 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002) 2165 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001) 2166 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000) 2167 2168 #define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010) 2169 #define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020) 2170 2171 /**************************************************************************** 2172 * FC Device Config Pages 2173 ****************************************************************************/ 2174 2175 typedef struct _CONFIG_PAGE_FC_DEVICE_0 2176 { 2177 CONFIG_PAGE_HEADER Header; /* 00h */ 2178 U64 WWNN; /* 04h */ 2179 U64 WWPN; /* 0Ch */ 2180 U32 PortIdentifier; /* 14h */ 2181 U8 Protocol; /* 18h */ 2182 U8 Flags; /* 19h */ 2183 U16 BBCredit; /* 1Ah */ 2184 U16 MaxRxFrameSize; /* 1Ch */ 2185 U8 ADISCHardALPA; /* 1Eh */ 2186 U8 PortNumber; /* 1Fh */ 2187 U8 FcPhLowestVersion; /* 20h */ 2188 U8 FcPhHighestVersion; /* 21h */ 2189 U8 CurrentTargetID; /* 22h */ 2190 U8 CurrentBus; /* 23h */ 2191 } CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0, 2192 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t; 2193 2194 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x03) 2195 2196 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01) 2197 #define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02) 2198 #define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04) 2199 2200 #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01) 2201 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02) 2202 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04) 2203 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY (0x08) 2204 2205 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK) 2206 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK) 2207 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID) 2208 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID) 2209 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK) 2210 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK) 2211 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT) 2212 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK) 2213 2214 #define MPI_FC_DEVICE_PAGE0_HARD_ALPA_UNKNOWN (0xFF) 2215 2216 /**************************************************************************** 2217 * RAID Volume Config Pages 2218 ****************************************************************************/ 2219 2220 typedef struct _RAID_VOL0_PHYS_DISK 2221 { 2222 U16 Reserved; /* 00h */ 2223 U8 PhysDiskMap; /* 02h */ 2224 U8 PhysDiskNum; /* 03h */ 2225 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK, 2226 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t; 2227 2228 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 2229 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 2230 2231 typedef struct _RAID_VOL0_STATUS 2232 { 2233 U8 Flags; /* 00h */ 2234 U8 State; /* 01h */ 2235 U16 Reserved; /* 02h */ 2236 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS, 2237 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t; 2238 2239 /* RAID Volume Page 0 VolumeStatus defines */ 2240 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01) 2241 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02) 2242 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04) 2243 #define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08) 2244 #define MPI_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x10) 2245 2246 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00) 2247 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01) 2248 #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02) 2249 #define MPI_RAIDVOL0_STATUS_STATE_MISSING (0x03) 2250 2251 typedef struct _RAID_VOL0_SETTINGS 2252 { 2253 U16 Settings; /* 00h */ 2254 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 2255 U8 Reserved; /* 02h */ 2256 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS, 2257 RaidVol0Settings, MPI_POINTER pRaidVol0Settings; 2258 2259 /* RAID Volume Page 0 VolumeSettings defines */ 2260 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001) 2261 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002) 2262 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004) 2263 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008) 2264 #define MPI_RAIDVOL0_SETTING_FAST_DATA_SCRUBBING_0102 (0x0020) /* obsolete */ 2265 2266 #define MPI_RAIDVOL0_SETTING_MASK_METADATA_SIZE (0x00C0) 2267 #define MPI_RAIDVOL0_SETTING_64MB_METADATA_SIZE (0x0000) 2268 #define MPI_RAIDVOL0_SETTING_512MB_METADATA_SIZE (0x0040) 2269 2270 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010) 2271 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000) 2272 2273 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 2274 #define MPI_RAID_HOT_SPARE_POOL_0 (0x01) 2275 #define MPI_RAID_HOT_SPARE_POOL_1 (0x02) 2276 #define MPI_RAID_HOT_SPARE_POOL_2 (0x04) 2277 #define MPI_RAID_HOT_SPARE_POOL_3 (0x08) 2278 #define MPI_RAID_HOT_SPARE_POOL_4 (0x10) 2279 #define MPI_RAID_HOT_SPARE_POOL_5 (0x20) 2280 #define MPI_RAID_HOT_SPARE_POOL_6 (0x40) 2281 #define MPI_RAID_HOT_SPARE_POOL_7 (0x80) 2282 2283 /* 2284 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2285 * one and check Header.PageLength at runtime. 2286 */ 2287 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX 2288 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 2289 #endif 2290 2291 typedef struct _CONFIG_PAGE_RAID_VOL_0 2292 { 2293 CONFIG_PAGE_HEADER Header; /* 00h */ 2294 U8 VolumeID; /* 04h */ 2295 U8 VolumeBus; /* 05h */ 2296 U8 VolumeIOC; /* 06h */ 2297 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */ 2298 RAID_VOL0_STATUS VolumeStatus; /* 08h */ 2299 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */ 2300 U32 MaxLBA; /* 10h */ 2301 U32 MaxLBAHigh; /* 14h */ 2302 U32 StripeSize; /* 18h */ 2303 U32 Reserved2; /* 1Ch */ 2304 U32 Reserved3; /* 20h */ 2305 U8 NumPhysDisks; /* 24h */ 2306 U8 DataScrubRate; /* 25h */ 2307 U8 ResyncRate; /* 26h */ 2308 U8 InactiveStatus; /* 27h */ 2309 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */ 2310 } CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0, 2311 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t; 2312 2313 #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x07) 2314 2315 /* values for RAID Volume Page 0 InactiveStatus field */ 2316 #define MPI_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 2317 #define MPI_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 2318 #define MPI_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 2319 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 2320 #define MPI_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 2321 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 2322 #define MPI_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 2323 2324 typedef struct _CONFIG_PAGE_RAID_VOL_1 2325 { 2326 CONFIG_PAGE_HEADER Header; /* 00h */ 2327 U8 VolumeID; /* 04h */ 2328 U8 VolumeBus; /* 05h */ 2329 U8 VolumeIOC; /* 06h */ 2330 U8 Reserved0; /* 07h */ 2331 U8 GUID[24]; /* 08h */ 2332 U8 Name[32]; /* 20h */ 2333 U64 WWID; /* 40h */ 2334 U32 Reserved1; /* 48h */ 2335 U32 Reserved2; /* 4Ch */ 2336 } CONFIG_PAGE_RAID_VOL_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_1, 2337 RaidVolumePage1_t, MPI_POINTER pRaidVolumePage1_t; 2338 2339 #define MPI_RAIDVOLPAGE1_PAGEVERSION (0x01) 2340 2341 /**************************************************************************** 2342 * RAID Physical Disk Config Pages 2343 ****************************************************************************/ 2344 2345 typedef struct _RAID_PHYS_DISK0_ERROR_DATA 2346 { 2347 U8 ErrorCdbByte; /* 00h */ 2348 U8 ErrorSenseKey; /* 01h */ 2349 U16 Reserved; /* 02h */ 2350 U16 ErrorCount; /* 04h */ 2351 U8 ErrorASC; /* 06h */ 2352 U8 ErrorASCQ; /* 07h */ 2353 U16 SmartCount; /* 08h */ 2354 U8 SmartASC; /* 0Ah */ 2355 U8 SmartASCQ; /* 0Bh */ 2356 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA, 2357 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t; 2358 2359 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA 2360 { 2361 U8 VendorID[8]; /* 00h */ 2362 U8 ProductID[16]; /* 08h */ 2363 U8 ProductRevLevel[4]; /* 18h */ 2364 U8 Info[32]; /* 1Ch */ 2365 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA, 2366 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData; 2367 2368 typedef struct _RAID_PHYS_DISK0_SETTINGS 2369 { 2370 U8 SepID; /* 00h */ 2371 U8 SepBus; /* 01h */ 2372 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */ 2373 U8 PhysDiskSettings; /* 03h */ 2374 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS, 2375 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t; 2376 2377 typedef struct _RAID_PHYS_DISK0_STATUS 2378 { 2379 U8 Flags; /* 00h */ 2380 U8 State; /* 01h */ 2381 U16 Reserved; /* 02h */ 2382 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS, 2383 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t; 2384 2385 /* RAID Physical Disk PhysDiskStatus flags */ 2386 2387 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01) 2388 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02) 2389 #define MPI_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x04) 2390 #define MPI_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00) 2391 #define MPI_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x08) 2392 2393 #define MPI_PHYSDISK0_STATUS_ONLINE (0x00) 2394 #define MPI_PHYSDISK0_STATUS_MISSING (0x01) 2395 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02) 2396 #define MPI_PHYSDISK0_STATUS_FAILED (0x03) 2397 #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04) 2398 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05) 2399 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06) 2400 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF) 2401 2402 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0 2403 { 2404 CONFIG_PAGE_HEADER Header; /* 00h */ 2405 U8 PhysDiskID; /* 04h */ 2406 U8 PhysDiskBus; /* 05h */ 2407 U8 PhysDiskIOC; /* 06h */ 2408 U8 PhysDiskNum; /* 07h */ 2409 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */ 2410 U32 Reserved1; /* 0Ch */ 2411 U8 ExtDiskIdentifier[8]; /* 10h */ 2412 U8 DiskIdentifier[16]; /* 18h */ 2413 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */ 2414 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */ 2415 U32 MaxLBA; /* 68h */ 2416 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */ 2417 } CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0, 2418 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t; 2419 2420 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x02) 2421 2422 typedef struct _RAID_PHYS_DISK1_PATH 2423 { 2424 U8 PhysDiskID; /* 00h */ 2425 U8 PhysDiskBus; /* 01h */ 2426 U16 Reserved1; /* 02h */ 2427 U64 WWID; /* 04h */ 2428 U64 OwnerWWID; /* 0Ch */ 2429 U8 OwnerIdentifier; /* 14h */ 2430 U8 Reserved2; /* 15h */ 2431 U16 Flags; /* 16h */ 2432 } RAID_PHYS_DISK1_PATH, MPI_POINTER PTR_RAID_PHYS_DISK1_PATH, 2433 RaidPhysDisk1Path_t, MPI_POINTER pRaidPhysDisk1Path_t; 2434 2435 /* RAID Physical Disk Page 1 Flags field defines */ 2436 #define MPI_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 2437 #define MPI_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 2438 2439 /* 2440 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2441 * one and check Header.PageLength or NumPhysDiskPaths at runtime. 2442 */ 2443 #ifndef MPI_RAID_PHYS_DISK1_PATH_MAX 2444 #define MPI_RAID_PHYS_DISK1_PATH_MAX (1) 2445 #endif 2446 2447 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_1 2448 { 2449 CONFIG_PAGE_HEADER Header; /* 00h */ 2450 U8 NumPhysDiskPaths; /* 04h */ 2451 U8 PhysDiskNum; /* 05h */ 2452 U16 Reserved2; /* 06h */ 2453 U32 Reserved1; /* 08h */ 2454 RAID_PHYS_DISK1_PATH Path[MPI_RAID_PHYS_DISK1_PATH_MAX];/* 0Ch */ 2455 } CONFIG_PAGE_RAID_PHYS_DISK_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_1, 2456 RaidPhysDiskPage1_t, MPI_POINTER pRaidPhysDiskPage1_t; 2457 2458 #define MPI_RAIDPHYSDISKPAGE1_PAGEVERSION (0x00) 2459 2460 /**************************************************************************** 2461 * LAN Config Pages 2462 ****************************************************************************/ 2463 2464 typedef struct _CONFIG_PAGE_LAN_0 2465 { 2466 ConfigPageHeader_t Header; /* 00h */ 2467 U16 TxRxModes; /* 04h */ 2468 U16 Reserved; /* 06h */ 2469 U32 PacketPrePad; /* 08h */ 2470 } CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0, 2471 LANPage0_t, MPI_POINTER pLANPage0_t; 2472 2473 #define MPI_LAN_PAGE0_PAGEVERSION (0x01) 2474 2475 #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000) 2476 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001) 2477 #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001) 2478 2479 typedef struct _CONFIG_PAGE_LAN_1 2480 { 2481 ConfigPageHeader_t Header; /* 00h */ 2482 U16 Reserved; /* 04h */ 2483 U8 CurrentDeviceState; /* 06h */ 2484 U8 Reserved1; /* 07h */ 2485 U32 MinPacketSize; /* 08h */ 2486 U32 MaxPacketSize; /* 0Ch */ 2487 U32 HardwareAddressLow; /* 10h */ 2488 U32 HardwareAddressHigh; /* 14h */ 2489 U32 MaxWireSpeedLow; /* 18h */ 2490 U32 MaxWireSpeedHigh; /* 1Ch */ 2491 U32 BucketsRemaining; /* 20h */ 2492 U32 MaxReplySize; /* 24h */ 2493 U32 NegWireSpeedLow; /* 28h */ 2494 U32 NegWireSpeedHigh; /* 2Ch */ 2495 } CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1, 2496 LANPage1_t, MPI_POINTER pLANPage1_t; 2497 2498 #define MPI_LAN_PAGE1_PAGEVERSION (0x03) 2499 2500 #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00) 2501 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01) 2502 2503 /**************************************************************************** 2504 * Inband Config Pages 2505 ****************************************************************************/ 2506 2507 typedef struct _CONFIG_PAGE_INBAND_0 2508 { 2509 CONFIG_PAGE_HEADER Header; /* 00h */ 2510 MPI_VERSION_FORMAT InbandVersion; /* 04h */ 2511 U16 MaximumBuffers; /* 08h */ 2512 U16 Reserved1; /* 0Ah */ 2513 } CONFIG_PAGE_INBAND_0, MPI_POINTER PTR_CONFIG_PAGE_INBAND_0, 2514 InbandPage0_t, MPI_POINTER pInbandPage0_t; 2515 2516 #define MPI_INBAND_PAGEVERSION (0x00) 2517 2518 /**************************************************************************** 2519 * SAS IO Unit Config Pages 2520 ****************************************************************************/ 2521 2522 typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA 2523 { 2524 U8 Port; /* 00h */ 2525 U8 PortFlags; /* 01h */ 2526 U8 PhyFlags; /* 02h */ 2527 U8 NegotiatedLinkRate; /* 03h */ 2528 U32 ControllerPhyDeviceInfo;/* 04h */ 2529 U16 AttachedDeviceHandle; /* 08h */ 2530 U16 ControllerDevHandle; /* 0Ah */ 2531 U32 DiscoveryStatus; /* 0Ch */ 2532 } MPI_SAS_IO_UNIT0_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT0_PHY_DATA, 2533 SasIOUnit0PhyData, MPI_POINTER pSasIOUnit0PhyData; 2534 2535 /* 2536 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2537 * one and check Header.PageLength at runtime. 2538 */ 2539 #ifndef MPI_SAS_IOUNIT0_PHY_MAX 2540 #define MPI_SAS_IOUNIT0_PHY_MAX (1) 2541 #endif 2542 2543 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_0 2544 { 2545 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2546 U16 NvdataVersionDefault; /* 08h */ 2547 U16 NvdataVersionPersistent; /* 0Ah */ 2548 U8 NumPhys; /* 0Ch */ 2549 U8 Reserved2; /* 0Dh */ 2550 U16 Reserved3; /* 0Eh */ 2551 MPI_SAS_IO_UNIT0_PHY_DATA PhyData[MPI_SAS_IOUNIT0_PHY_MAX]; /* 10h */ 2552 } CONFIG_PAGE_SAS_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_0, 2553 SasIOUnitPage0_t, MPI_POINTER pSasIOUnitPage0_t; 2554 2555 #define MPI_SASIOUNITPAGE0_PAGEVERSION (0x04) 2556 2557 /* values for SAS IO Unit Page 0 PortFlags */ 2558 #define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS (0x08) 2559 #define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM (0x00) 2560 #define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM (0x04) 2561 #define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2562 2563 /* values for SAS IO Unit Page 0 PhyFlags */ 2564 #define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED (0x04) 2565 #define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT (0x02) 2566 #define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT (0x01) 2567 2568 /* values for SAS IO Unit Page 0 NegotiatedLinkRate */ 2569 #define MPI_SAS_IOUNIT0_RATE_UNKNOWN (0x00) 2570 #define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED (0x01) 2571 #define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION (0x02) 2572 #define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE (0x03) 2573 #define MPI_SAS_IOUNIT0_RATE_1_5 (0x08) 2574 #define MPI_SAS_IOUNIT0_RATE_3_0 (0x09) 2575 #define MPI_SAS_IOUNIT0_RATE_6_0 (0x0A) 2576 2577 /* see mpi_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 2578 2579 /* values for SAS IO Unit Page 0 DiscoveryStatus */ 2580 #define MPI_SAS_IOUNIT0_DS_LOOP_DETECTED (0x00000001) 2581 #define MPI_SAS_IOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2582 #define MPI_SAS_IOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2583 #define MPI_SAS_IOUNIT0_DS_EXPANDER_ERR (0x00000008) 2584 #define MPI_SAS_IOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2585 #define MPI_SAS_IOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2586 #define MPI_SAS_IOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2587 #define MPI_SAS_IOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2588 #define MPI_SAS_IOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2589 #define MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2590 #define MPI_SAS_IOUNIT0_DS_TABLE_LINK (0x00000400) 2591 #define MPI_SAS_IOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2592 #define MPI_SAS_IOUNIT0_DS_MAX_SATA_TARGETS (0x00001000) 2593 #define MPI_SAS_IOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 2594 2595 typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA 2596 { 2597 U8 Port; /* 00h */ 2598 U8 PortFlags; /* 01h */ 2599 U8 PhyFlags; /* 02h */ 2600 U8 MaxMinLinkRate; /* 03h */ 2601 U32 ControllerPhyDeviceInfo; /* 04h */ 2602 U16 MaxTargetPortConnectTime; /* 08h */ 2603 U16 Reserved1; /* 0Ah */ 2604 } MPI_SAS_IO_UNIT1_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT1_PHY_DATA, 2605 SasIOUnit1PhyData, MPI_POINTER pSasIOUnit1PhyData; 2606 2607 /* 2608 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2609 * one and check Header.PageLength at runtime. 2610 */ 2611 #ifndef MPI_SAS_IOUNIT1_PHY_MAX 2612 #define MPI_SAS_IOUNIT1_PHY_MAX (1) 2613 #endif 2614 2615 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_1 2616 { 2617 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2618 U16 ControlFlags; /* 08h */ 2619 U16 MaxNumSATATargets; /* 0Ah */ 2620 U16 AdditionalControlFlags; /* 0Ch */ 2621 U16 Reserved1; /* 0Eh */ 2622 U8 NumPhys; /* 10h */ 2623 U8 SATAMaxQDepth; /* 11h */ 2624 U8 ReportDeviceMissingDelay; /* 12h */ 2625 U8 IODeviceMissingDelay; /* 13h */ 2626 MPI_SAS_IO_UNIT1_PHY_DATA PhyData[MPI_SAS_IOUNIT1_PHY_MAX]; /* 14h */ 2627 } CONFIG_PAGE_SAS_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_1, 2628 SasIOUnitPage1_t, MPI_POINTER pSasIOUnitPage1_t; 2629 2630 #define MPI_SASIOUNITPAGE1_PAGEVERSION (0x07) 2631 2632 /* values for SAS IO Unit Page 1 ControlFlags */ 2633 #define MPI_SAS_IOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2634 #define MPI_SAS_IOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2635 #define MPI_SAS_IOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 2636 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2637 #define MPI_SAS_IOUNIT1_CONTROL_DISABLE_SAS_HASH (0x0800) 2638 2639 #define MPI_SAS_IOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2640 #define MPI_SAS_IOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2641 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x00) 2642 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x01) 2643 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x02) 2644 2645 #define MPI_SAS_IOUNIT1_CONTROL_POSTPONE_SATA_INIT (0x0100) 2646 #define MPI_SAS_IOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2647 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2648 #define MPI_SAS_IOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2649 #define MPI_SAS_IOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2650 #define MPI_SAS_IOUNIT1_CONTROL_PHY_ENABLE_ORDER_HIGH (0x0008) 2651 #define MPI_SAS_IOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2652 #define MPI_SAS_IOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2653 #define MPI_SAS_IOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 2654 2655 /* values for SAS IO Unit Page 1 AdditionalControlFlags */ 2656 #define MPI_SAS_IOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2657 #define MPI_SAS_IOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2658 #define MPI_SAS_IOUNIT1_ACONTROL_HIDE_NONZERO_ATTACHED_PHY_IDENT (0x0020) 2659 #define MPI_SAS_IOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2660 #define MPI_SAS_IOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2661 #define MPI_SAS_IOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2662 #define MPI_SAS_IOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2663 #define MPI_SAS_IOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2664 2665 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2666 #define MPI_SAS_IOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2667 #define MPI_SAS_IOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2668 2669 /* values for SAS IO Unit Page 1 PortFlags */ 2670 #define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM (0x00) 2671 #define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM (0x04) 2672 #define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2673 2674 /* values for SAS IO Unit Page 0 PhyFlags */ 2675 #define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE (0x04) 2676 #define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT (0x02) 2677 #define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT (0x01) 2678 2679 /* values for SAS IO Unit Page 0 MaxMinLinkRate */ 2680 #define MPI_SAS_IOUNIT1_MAX_RATE_MASK (0xF0) 2681 #define MPI_SAS_IOUNIT1_MAX_RATE_1_5 (0x80) 2682 #define MPI_SAS_IOUNIT1_MAX_RATE_3_0 (0x90) 2683 #define MPI_SAS_IOUNIT1_MIN_RATE_MASK (0x0F) 2684 #define MPI_SAS_IOUNIT1_MIN_RATE_1_5 (0x08) 2685 #define MPI_SAS_IOUNIT1_MIN_RATE_3_0 (0x09) 2686 2687 /* see mpi_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2688 2689 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_2 2690 { 2691 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2692 U8 NumDevsPerEnclosure; /* 08h */ 2693 U8 BootDeviceWaitTime; /* 09h */ 2694 U16 Reserved2; /* 0Ah */ 2695 U16 MaxPersistentIDs; /* 0Ch */ 2696 U16 NumPersistentIDsUsed; /* 0Eh */ 2697 U8 Status; /* 10h */ 2698 U8 Flags; /* 11h */ 2699 U16 MaxNumPhysicalMappedIDs;/* 12h */ 2700 } CONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2, 2701 SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t; 2702 2703 #define MPI_SASIOUNITPAGE2_PAGEVERSION (0x07) 2704 2705 /* values for SAS IO Unit Page 2 Status field */ 2706 #define MPI_SAS_IOUNIT2_STATUS_DEVICE_LIMIT_EXCEEDED (0x08) 2707 #define MPI_SAS_IOUNIT2_STATUS_ENCLOSURE_DEVICES_UNMAPPED (0x04) 2708 #define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS (0x02) 2709 #define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS (0x01) 2710 2711 /* values for SAS IO Unit Page 2 Flags field */ 2712 #define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS (0x01) 2713 /* Physical Mapping Modes */ 2714 #define MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE (0x0E) 2715 #define MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE (1) 2716 #define MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP (0x00) 2717 #define MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP (0x01) 2718 #define MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP (0x02) 2719 #define MPI_SAS_IOUNIT2_FLAGS_HOST_ASSIGNED_PHYS_MAP (0x07) 2720 2721 #define MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT (0x10) 2722 #define MPI_SAS_IOUNIT2_FLAGS_DA_STARTING_SLOT (0x20) 2723 2724 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_3 2725 { 2726 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2727 U32 Reserved1; /* 08h */ 2728 U32 MaxInvalidDwordCount; /* 0Ch */ 2729 U32 InvalidDwordCountTime; /* 10h */ 2730 U32 MaxRunningDisparityErrorCount; /* 14h */ 2731 U32 RunningDisparityErrorTime; /* 18h */ 2732 U32 MaxLossDwordSynchCount; /* 1Ch */ 2733 U32 LossDwordSynchCountTime; /* 20h */ 2734 U32 MaxPhyResetProblemCount; /* 24h */ 2735 U32 PhyResetProblemTime; /* 28h */ 2736 } CONFIG_PAGE_SAS_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_3, 2737 SasIOUnitPage3_t, MPI_POINTER pSasIOUnitPage3_t; 2738 2739 #define MPI_SASIOUNITPAGE3_PAGEVERSION (0x00) 2740 2741 /**************************************************************************** 2742 * SAS Expander Config Pages 2743 ****************************************************************************/ 2744 2745 typedef struct _CONFIG_PAGE_SAS_EXPANDER_0 2746 { 2747 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2748 U8 PhysicalPort; /* 08h */ 2749 U8 Reserved1; /* 09h */ 2750 U16 EnclosureHandle; /* 0Ah */ 2751 U64 SASAddress; /* 0Ch */ 2752 U32 DiscoveryStatus; /* 14h */ 2753 U16 DevHandle; /* 18h */ 2754 U16 ParentDevHandle; /* 1Ah */ 2755 U16 ExpanderChangeCount; /* 1Ch */ 2756 U16 ExpanderRouteIndexes; /* 1Eh */ 2757 U8 NumPhys; /* 20h */ 2758 U8 SASLevel; /* 21h */ 2759 U8 Flags; /* 22h */ 2760 U8 Reserved3; /* 23h */ 2761 } CONFIG_PAGE_SAS_EXPANDER_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_0, 2762 SasExpanderPage0_t, MPI_POINTER pSasExpanderPage0_t; 2763 2764 #define MPI_SASEXPANDER0_PAGEVERSION (0x03) 2765 2766 /* values for SAS Expander Page 0 DiscoveryStatus field */ 2767 #define MPI_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2768 #define MPI_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2769 #define MPI_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2770 #define MPI_SAS_EXPANDER0_DS_EXPANDER_ERR (0x00000008) 2771 #define MPI_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2772 #define MPI_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2773 #define MPI_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2774 #define MPI_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2775 #define MPI_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2776 #define MPI_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2777 #define MPI_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2778 #define MPI_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2779 2780 /* values for SAS Expander Page 0 Flags field */ 2781 #define MPI_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x04) 2782 #define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x02) 2783 #define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x01) 2784 2785 typedef struct _CONFIG_PAGE_SAS_EXPANDER_1 2786 { 2787 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2788 U8 PhysicalPort; /* 08h */ 2789 U8 Reserved1; /* 09h */ 2790 U16 Reserved2; /* 0Ah */ 2791 U8 NumPhys; /* 0Ch */ 2792 U8 Phy; /* 0Dh */ 2793 U16 NumTableEntriesProgrammed; /* 0Eh */ 2794 U8 ProgrammedLinkRate; /* 10h */ 2795 U8 HwLinkRate; /* 11h */ 2796 U16 AttachedDevHandle; /* 12h */ 2797 U32 PhyInfo; /* 14h */ 2798 U32 AttachedDeviceInfo; /* 18h */ 2799 U16 OwnerDevHandle; /* 1Ch */ 2800 U8 ChangeCount; /* 1Eh */ 2801 U8 NegotiatedLinkRate; /* 1Fh */ 2802 U8 PhyIdentifier; /* 20h */ 2803 U8 AttachedPhyIdentifier; /* 21h */ 2804 U8 Reserved3; /* 22h */ 2805 U8 DiscoveryInfo; /* 23h */ 2806 U32 Reserved4; /* 24h */ 2807 } CONFIG_PAGE_SAS_EXPANDER_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_1, 2808 SasExpanderPage1_t, MPI_POINTER pSasExpanderPage1_t; 2809 2810 #define MPI_SASEXPANDER1_PAGEVERSION (0x01) 2811 2812 /* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */ 2813 2814 /* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */ 2815 2816 /* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */ 2817 2818 /* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */ 2819 2820 /* values for SAS Expander Page 1 DiscoveryInfo field */ 2821 #define MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2822 #define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2823 #define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2824 2825 /* values for SAS Expander Page 1 NegotiatedLinkRate field */ 2826 #define MPI_SAS_EXPANDER1_NEG_RATE_UNKNOWN (0x00) 2827 #define MPI_SAS_EXPANDER1_NEG_RATE_PHY_DISABLED (0x01) 2828 #define MPI_SAS_EXPANDER1_NEG_RATE_FAILED_NEGOTIATION (0x02) 2829 #define MPI_SAS_EXPANDER1_NEG_RATE_SATA_OOB_COMPLETE (0x03) 2830 #define MPI_SAS_EXPANDER1_NEG_RATE_1_5 (0x08) 2831 #define MPI_SAS_EXPANDER1_NEG_RATE_3_0 (0x09) 2832 2833 /**************************************************************************** 2834 * SAS Device Config Pages 2835 ****************************************************************************/ 2836 2837 typedef struct _CONFIG_PAGE_SAS_DEVICE_0 2838 { 2839 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2840 U16 Slot; /* 08h */ 2841 U16 EnclosureHandle; /* 0Ah */ 2842 U64 SASAddress; /* 0Ch */ 2843 U16 ParentDevHandle; /* 14h */ 2844 U8 PhyNum; /* 16h */ 2845 U8 AccessStatus; /* 17h */ 2846 U16 DevHandle; /* 18h */ 2847 U8 TargetID; /* 1Ah */ 2848 U8 Bus; /* 1Bh */ 2849 U32 DeviceInfo; /* 1Ch */ 2850 U16 Flags; /* 20h */ 2851 U8 PhysicalPort; /* 22h */ 2852 U8 Reserved2; /* 23h */ 2853 } CONFIG_PAGE_SAS_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_0, 2854 SasDevicePage0_t, MPI_POINTER pSasDevicePage0_t; 2855 2856 #define MPI_SASDEVICE0_PAGEVERSION (0x05) 2857 2858 /* values for SAS Device Page 0 AccessStatus field */ 2859 #define MPI_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2860 #define MPI_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2861 #define MPI_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2862 #define MPI_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2863 #define MPI_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2864 /* specific values for SATA Init failures */ 2865 #define MPI_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2866 #define MPI_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2867 #define MPI_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2868 #define MPI_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2869 #define MPI_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2870 #define MPI_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2871 #define MPI_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2872 #define MPI_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2873 #define MPI_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2874 #define MPI_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2875 #define MPI_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2876 2877 /* values for SAS Device Page 0 Flags field */ 2878 #define MPI_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2879 #define MPI_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2880 #define MPI_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2881 #define MPI_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2882 #define MPI_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2883 #define MPI_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2884 #define MPI_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2885 #define MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2886 #define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT (0x0004) 2887 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED (0x0002) 2888 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2889 2890 /* see mpi_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2891 2892 typedef struct _CONFIG_PAGE_SAS_DEVICE_1 2893 { 2894 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2895 U32 Reserved1; /* 08h */ 2896 U64 SASAddress; /* 0Ch */ 2897 U32 Reserved2; /* 14h */ 2898 U16 DevHandle; /* 18h */ 2899 U8 TargetID; /* 1Ah */ 2900 U8 Bus; /* 1Bh */ 2901 U8 InitialRegDeviceFIS[20];/* 1Ch */ 2902 } CONFIG_PAGE_SAS_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_1, 2903 SasDevicePage1_t, MPI_POINTER pSasDevicePage1_t; 2904 2905 #define MPI_SASDEVICE1_PAGEVERSION (0x00) 2906 2907 typedef struct _CONFIG_PAGE_SAS_DEVICE_2 2908 { 2909 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2910 U64 PhysicalIdentifier; /* 08h */ 2911 U32 EnclosureMapping; /* 10h */ 2912 } CONFIG_PAGE_SAS_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_2, 2913 SasDevicePage2_t, MPI_POINTER pSasDevicePage2_t; 2914 2915 #define MPI_SASDEVICE2_PAGEVERSION (0x01) 2916 2917 /* defines for SAS Device Page 2 EnclosureMapping field */ 2918 #define MPI_SASDEVICE2_ENC_MAP_MASK_MISSING_COUNT (0x0000000F) 2919 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_MISSING_COUNT (0) 2920 #define MPI_SASDEVICE2_ENC_MAP_MASK_NUM_SLOTS (0x000007F0) 2921 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_NUM_SLOTS (4) 2922 #define MPI_SASDEVICE2_ENC_MAP_MASK_START_INDEX (0x001FF800) 2923 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_START_INDEX (11) 2924 2925 /**************************************************************************** 2926 * SAS PHY Config Pages 2927 ****************************************************************************/ 2928 2929 typedef struct _CONFIG_PAGE_SAS_PHY_0 2930 { 2931 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2932 U16 OwnerDevHandle; /* 08h */ 2933 U16 Reserved1; /* 0Ah */ 2934 U64 SASAddress; /* 0Ch */ 2935 U16 AttachedDevHandle; /* 14h */ 2936 U8 AttachedPhyIdentifier; /* 16h */ 2937 U8 Reserved2; /* 17h */ 2938 U32 AttachedDeviceInfo; /* 18h */ 2939 U8 ProgrammedLinkRate; /* 1Ch */ 2940 U8 HwLinkRate; /* 1Dh */ 2941 U8 ChangeCount; /* 1Eh */ 2942 U8 Flags; /* 1Fh */ 2943 U32 PhyInfo; /* 20h */ 2944 } CONFIG_PAGE_SAS_PHY_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_0, 2945 SasPhyPage0_t, MPI_POINTER pSasPhyPage0_t; 2946 2947 #define MPI_SASPHY0_PAGEVERSION (0x01) 2948 2949 /* values for SAS PHY Page 0 ProgrammedLinkRate field */ 2950 #define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK (0xF0) 2951 #define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 2952 #define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5 (0x80) 2953 #define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0 (0x90) 2954 #define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK (0x0F) 2955 #define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 2956 #define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5 (0x08) 2957 #define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0 (0x09) 2958 2959 /* values for SAS PHY Page 0 HwLinkRate field */ 2960 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK (0xF0) 2961 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5 (0x80) 2962 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0 (0x90) 2963 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK (0x0F) 2964 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5 (0x08) 2965 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0 (0x09) 2966 2967 /* values for SAS PHY Page 0 Flags field */ 2968 #define MPI_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2969 2970 /* values for SAS PHY Page 0 PhyInfo field */ 2971 #define MPI_SAS_PHY0_PHYINFO_PHY_VACANT (0x80000000) 2972 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 2973 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR (0x00002000) 2974 #define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY (0x00001000) 2975 2976 #define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 2977 #define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 2978 2979 #define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 2980 #define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING (0x00000000) 2981 #define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 2982 #define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING (0x00000020) 2983 2984 #define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE (0x0000000F) 2985 #define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE (0x00000000) 2986 #define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED (0x00000001) 2987 #define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED (0x00000002) 2988 #define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE (0x00000003) 2989 #define MPI_SAS_PHY0_PHYINFO_RATE_1_5 (0x00000008) 2990 #define MPI_SAS_PHY0_PHYINFO_RATE_3_0 (0x00000009) 2991 2992 typedef struct _CONFIG_PAGE_SAS_PHY_1 2993 { 2994 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 2995 U32 Reserved1; /* 08h */ 2996 U32 InvalidDwordCount; /* 0Ch */ 2997 U32 RunningDisparityErrorCount; /* 10h */ 2998 U32 LossDwordSynchCount; /* 14h */ 2999 U32 PhyResetProblemCount; /* 18h */ 3000 } CONFIG_PAGE_SAS_PHY_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_1, 3001 SasPhyPage1_t, MPI_POINTER pSasPhyPage1_t; 3002 3003 #define MPI_SASPHY1_PAGEVERSION (0x00) 3004 3005 /**************************************************************************** 3006 * SAS Enclosure Config Pages 3007 ****************************************************************************/ 3008 3009 typedef struct _CONFIG_PAGE_SAS_ENCLOSURE_0 3010 { 3011 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 3012 U32 Reserved1; /* 08h */ 3013 U64 EnclosureLogicalID; /* 0Ch */ 3014 U16 Flags; /* 14h */ 3015 U16 EnclosureHandle; /* 16h */ 3016 U16 NumSlots; /* 18h */ 3017 U16 StartSlot; /* 1Ah */ 3018 U8 StartTargetID; /* 1Ch */ 3019 U8 StartBus; /* 1Dh */ 3020 U8 SEPTargetID; /* 1Eh */ 3021 U8 SEPBus; /* 1Fh */ 3022 U32 Reserved2; /* 20h */ 3023 U32 Reserved3; /* 24h */ 3024 } CONFIG_PAGE_SAS_ENCLOSURE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_ENCLOSURE_0, 3025 SasEnclosurePage0_t, MPI_POINTER pSasEnclosurePage0_t; 3026 3027 #define MPI_SASENCLOSURE0_PAGEVERSION (0x01) 3028 3029 /* values for SAS Enclosure Page 0 Flags field */ 3030 #define MPI_SAS_ENCLS0_FLAGS_SEP_BUS_ID_VALID (0x0020) 3031 #define MPI_SAS_ENCLS0_FLAGS_START_BUS_ID_VALID (0x0010) 3032 3033 #define MPI_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3034 #define MPI_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3035 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3036 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3037 #define MPI_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3038 #define MPI_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3039 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3040 3041 /**************************************************************************** 3042 * Log Config Pages 3043 ****************************************************************************/ 3044 /* 3045 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3046 * one and check NumLogEntries at runtime. 3047 */ 3048 #ifndef MPI_LOG_0_NUM_LOG_ENTRIES 3049 #define MPI_LOG_0_NUM_LOG_ENTRIES (1) 3050 #endif 3051 3052 #define MPI_LOG_0_LOG_DATA_LENGTH (0x1C) 3053 3054 typedef struct _MPI_LOG_0_ENTRY 3055 { 3056 U32 TimeStamp; /* 00h */ 3057 U32 Reserved1; /* 04h */ 3058 U16 LogSequence; /* 08h */ 3059 U16 LogEntryQualifier; /* 0Ah */ 3060 U8 LogData[MPI_LOG_0_LOG_DATA_LENGTH]; /* 0Ch */ 3061 } MPI_LOG_0_ENTRY, MPI_POINTER PTR_MPI_LOG_0_ENTRY, 3062 MpiLog0Entry_t, MPI_POINTER pMpiLog0Entry_t; 3063 3064 /* values for Log Page 0 LogEntry LogEntryQualifier field */ 3065 #define MPI_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3066 #define MPI_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3067 3068 typedef struct _CONFIG_PAGE_LOG_0 3069 { 3070 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */ 3071 U32 Reserved1; /* 08h */ 3072 U32 Reserved2; /* 0Ch */ 3073 U16 NumLogEntries; /* 10h */ 3074 U16 Reserved3; /* 12h */ 3075 MPI_LOG_0_ENTRY LogEntry[MPI_LOG_0_NUM_LOG_ENTRIES]; /* 14h */ 3076 } CONFIG_PAGE_LOG_0, MPI_POINTER PTR_CONFIG_PAGE_LOG_0, 3077 LogPage0_t, MPI_POINTER pLogPage0_t; 3078 3079 #define MPI_LOG_0_PAGEVERSION (0x01) 3080 3081 #endif 3082