1 /*- 2 * Copyright (c) 2011, 2012 LSI Corp. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * LSI MPT-Fusion Host Adapter FreeBSD 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * Copyright (c) 2000-2012 LSI Corporation. 33 * 34 * 35 * Name: mpi2_ioc.h 36 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 37 * Creation Date: October 11, 2006 38 * 39 * mpi2_ioc.h Version: 02.00.16 40 * 41 * Version History 42 * --------------- 43 * 44 * Date Version Description 45 * -------- -------- ------------------------------------------------------ 46 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 47 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to 48 * MaxTargets. 49 * Added TotalImageSize field to FWDownload Request. 50 * Added reserved words to FWUpload Request. 51 * 06-26-07 02.00.02 Added IR Configuration Change List Event. 52 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit 53 * request and replaced it with 54 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth. 55 * Replaced the MinReplyQueueDepth field of the IOCFacts 56 * reply with MaxReplyDescriptorPostQueueDepth. 57 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum 58 * depth for the Reply Descriptor Post Queue. 59 * Added SASAddress field to Initiator Device Table 60 * Overflow Event data. 61 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING 62 * for SAS Initiator Device Status Change Event data. 63 * Modified Reason Code defines for SAS Topology Change 64 * List Event data, including adding a bit for PHY Vacant 65 * status, and adding a mask for the Reason Code. 66 * Added define for 67 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING. 68 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID. 69 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of 70 * the IOCFacts Reply. 71 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 72 * Moved MPI2_VERSION_UNION to mpi2.h. 73 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks 74 * instead of enables, and added SASBroadcastPrimitiveMasks 75 * field. 76 * Added Log Entry Added Event and related structure. 77 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID. 78 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET. 79 * Added MaxVolumes and MaxPersistentEntries fields to 80 * IOCFacts reply. 81 * Added ProtocalFlags and IOCCapabilities fields to 82 * MPI2_FW_IMAGE_HEADER. 83 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT. 84 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to 85 * a U16 (from a U32). 86 * Removed extra 's' from EventMasks name. 87 * 06-27-08 02.00.08 Fixed an offset in a comment. 88 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST. 89 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and 90 * renamed MinReplyFrameSize to ReplyFrameSize. 91 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX. 92 * Added two new RAIDOperation values for Integrated RAID 93 * Operations Status Event data. 94 * Added four new IR Configuration Change List Event data 95 * ReasonCode values. 96 * Added two new ReasonCode defines for SAS Device Status 97 * Change Event data. 98 * Added three new DiscoveryStatus bits for the SAS 99 * Discovery event data. 100 * Added Multiplexing Status Change bit to the PhyStatus 101 * field of the SAS Topology Change List event data. 102 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY. 103 * BootFlags are now product-specific. 104 * Added defines for the indivdual signature bytes 105 * for MPI2_INIT_IMAGE_FOOTER. 106 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define. 107 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR 108 * define. 109 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE 110 * define. 111 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define. 112 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define. 113 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define. 114 * Added two new reason codes for SAS Device Status Change 115 * Event. 116 * Added new event: SAS PHY Counter. 117 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure. 118 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 119 * Added new product id family for 2208. 120 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST. 121 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY. 122 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY. 123 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY. 124 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define. 125 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define. 126 * Added Host Based Discovery Phy Event data. 127 * Added defines for ProductID Product field 128 * (MPI2_FW_HEADER_PID_). 129 * Modified values for SAS ProductID Family 130 * (MPI2_FW_HEADER_PID_FAMILY_). 131 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines. 132 * Added PowerManagementControl Request structures and 133 * defines. 134 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete. 135 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define. 136 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC. 137 * -------------------------------------------------------------------------- 138 */ 139 140 #ifndef MPI2_IOC_H 141 #define MPI2_IOC_H 142 143 /***************************************************************************** 144 * 145 * IOC Messages 146 * 147 *****************************************************************************/ 148 149 /**************************************************************************** 150 * IOCInit message 151 ****************************************************************************/ 152 153 /* IOCInit Request message */ 154 typedef struct _MPI2_IOC_INIT_REQUEST 155 { 156 U8 WhoInit; /* 0x00 */ 157 U8 Reserved1; /* 0x01 */ 158 U8 ChainOffset; /* 0x02 */ 159 U8 Function; /* 0x03 */ 160 U16 Reserved2; /* 0x04 */ 161 U8 Reserved3; /* 0x06 */ 162 U8 MsgFlags; /* 0x07 */ 163 U8 VP_ID; /* 0x08 */ 164 U8 VF_ID; /* 0x09 */ 165 U16 Reserved4; /* 0x0A */ 166 U16 MsgVersion; /* 0x0C */ 167 U16 HeaderVersion; /* 0x0E */ 168 U32 Reserved5; /* 0x10 */ 169 U16 Reserved6; /* 0x14 */ 170 U8 Reserved7; /* 0x16 */ 171 U8 HostMSIxVectors; /* 0x17 */ 172 U16 Reserved8; /* 0x18 */ 173 U16 SystemRequestFrameSize; /* 0x1A */ 174 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */ 175 U16 ReplyFreeQueueDepth; /* 0x1E */ 176 U32 SenseBufferAddressHigh; /* 0x20 */ 177 U32 SystemReplyAddressHigh; /* 0x24 */ 178 U64 SystemRequestFrameBaseAddress; /* 0x28 */ 179 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */ 180 U64 ReplyFreeQueueAddress; /* 0x38 */ 181 U64 TimeStamp; /* 0x40 */ 182 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 183 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 184 185 /* WhoInit values */ 186 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 187 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 188 #define MPI2_WHOINIT_ROM_BIOS (0x02) 189 #define MPI2_WHOINIT_PCI_PEER (0x03) 190 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 191 #define MPI2_WHOINIT_MANUFACTURER (0x05) 192 193 /* MsgVersion */ 194 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00) 195 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8) 196 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF) 197 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0) 198 199 /* HeaderVersion */ 200 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00) 201 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8) 202 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF) 203 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0) 204 205 /* minimum depth for the Reply Descriptor Post Queue */ 206 #define MPI2_RDPQ_DEPTH_MIN (16) 207 208 209 /* IOCInit Reply message */ 210 typedef struct _MPI2_IOC_INIT_REPLY 211 { 212 U8 WhoInit; /* 0x00 */ 213 U8 Reserved1; /* 0x01 */ 214 U8 MsgLength; /* 0x02 */ 215 U8 Function; /* 0x03 */ 216 U16 Reserved2; /* 0x04 */ 217 U8 Reserved3; /* 0x06 */ 218 U8 MsgFlags; /* 0x07 */ 219 U8 VP_ID; /* 0x08 */ 220 U8 VF_ID; /* 0x09 */ 221 U16 Reserved4; /* 0x0A */ 222 U16 Reserved5; /* 0x0C */ 223 U16 IOCStatus; /* 0x0E */ 224 U32 IOCLogInfo; /* 0x10 */ 225 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY, 226 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t; 227 228 229 /**************************************************************************** 230 * IOCFacts message 231 ****************************************************************************/ 232 233 /* IOCFacts Request message */ 234 typedef struct _MPI2_IOC_FACTS_REQUEST 235 { 236 U16 Reserved1; /* 0x00 */ 237 U8 ChainOffset; /* 0x02 */ 238 U8 Function; /* 0x03 */ 239 U16 Reserved2; /* 0x04 */ 240 U8 Reserved3; /* 0x06 */ 241 U8 MsgFlags; /* 0x07 */ 242 U8 VP_ID; /* 0x08 */ 243 U8 VF_ID; /* 0x09 */ 244 U16 Reserved4; /* 0x0A */ 245 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST, 246 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t; 247 248 249 /* IOCFacts Reply message */ 250 typedef struct _MPI2_IOC_FACTS_REPLY 251 { 252 U16 MsgVersion; /* 0x00 */ 253 U8 MsgLength; /* 0x02 */ 254 U8 Function; /* 0x03 */ 255 U16 HeaderVersion; /* 0x04 */ 256 U8 IOCNumber; /* 0x06 */ 257 U8 MsgFlags; /* 0x07 */ 258 U8 VP_ID; /* 0x08 */ 259 U8 VF_ID; /* 0x09 */ 260 U16 Reserved1; /* 0x0A */ 261 U16 IOCExceptions; /* 0x0C */ 262 U16 IOCStatus; /* 0x0E */ 263 U32 IOCLogInfo; /* 0x10 */ 264 U8 MaxChainDepth; /* 0x14 */ 265 U8 WhoInit; /* 0x15 */ 266 U8 NumberOfPorts; /* 0x16 */ 267 U8 MaxMSIxVectors; /* 0x17 */ 268 U16 RequestCredit; /* 0x18 */ 269 U16 ProductID; /* 0x1A */ 270 U32 IOCCapabilities; /* 0x1C */ 271 MPI2_VERSION_UNION FWVersion; /* 0x20 */ 272 U16 IOCRequestFrameSize; /* 0x24 */ 273 U16 Reserved3; /* 0x26 */ 274 U16 MaxInitiators; /* 0x28 */ 275 U16 MaxTargets; /* 0x2A */ 276 U16 MaxSasExpanders; /* 0x2C */ 277 U16 MaxEnclosures; /* 0x2E */ 278 U16 ProtocolFlags; /* 0x30 */ 279 U16 HighPriorityCredit; /* 0x32 */ 280 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */ 281 U8 ReplyFrameSize; /* 0x36 */ 282 U8 MaxVolumes; /* 0x37 */ 283 U16 MaxDevHandle; /* 0x38 */ 284 U16 MaxPersistentEntries; /* 0x3A */ 285 U16 MinDevHandle; /* 0x3C */ 286 U16 Reserved4; /* 0x3E */ 287 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY, 288 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t; 289 290 /* MsgVersion */ 291 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) 292 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8) 293 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) 294 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0) 295 296 /* HeaderVersion */ 297 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00) 298 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8) 299 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF) 300 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0) 301 302 /* IOCExceptions */ 303 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100) 304 305 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0) 306 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000) 307 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020) 308 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040) 309 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060) 310 311 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010) 312 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008) 313 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004) 314 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002) 315 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) 316 317 /* defines for WhoInit field are after the IOCInit Request */ 318 319 /* ProductID field uses MPI2_FW_HEADER_PID_ */ 320 321 /* IOCCapabilities */ 322 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000) 323 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000) 324 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000) 325 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000) 326 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000) 327 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800) 328 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100) 329 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080) 330 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040) 331 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020) 332 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010) 333 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008) 334 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004) 335 336 /* ProtocolFlags */ 337 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) 338 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) 339 340 341 /**************************************************************************** 342 * PortFacts message 343 ****************************************************************************/ 344 345 /* PortFacts Request message */ 346 typedef struct _MPI2_PORT_FACTS_REQUEST 347 { 348 U16 Reserved1; /* 0x00 */ 349 U8 ChainOffset; /* 0x02 */ 350 U8 Function; /* 0x03 */ 351 U16 Reserved2; /* 0x04 */ 352 U8 PortNumber; /* 0x06 */ 353 U8 MsgFlags; /* 0x07 */ 354 U8 VP_ID; /* 0x08 */ 355 U8 VF_ID; /* 0x09 */ 356 U16 Reserved3; /* 0x0A */ 357 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST, 358 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t; 359 360 /* PortFacts Reply message */ 361 typedef struct _MPI2_PORT_FACTS_REPLY 362 { 363 U16 Reserved1; /* 0x00 */ 364 U8 MsgLength; /* 0x02 */ 365 U8 Function; /* 0x03 */ 366 U16 Reserved2; /* 0x04 */ 367 U8 PortNumber; /* 0x06 */ 368 U8 MsgFlags; /* 0x07 */ 369 U8 VP_ID; /* 0x08 */ 370 U8 VF_ID; /* 0x09 */ 371 U16 Reserved3; /* 0x0A */ 372 U16 Reserved4; /* 0x0C */ 373 U16 IOCStatus; /* 0x0E */ 374 U32 IOCLogInfo; /* 0x10 */ 375 U8 Reserved5; /* 0x14 */ 376 U8 PortType; /* 0x15 */ 377 U16 Reserved6; /* 0x16 */ 378 U16 MaxPostedCmdBuffers; /* 0x18 */ 379 U16 Reserved7; /* 0x1A */ 380 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY, 381 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t; 382 383 /* PortType values */ 384 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00) 385 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10) 386 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20) 387 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) 388 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) 389 390 391 /**************************************************************************** 392 * PortEnable message 393 ****************************************************************************/ 394 395 /* PortEnable Request message */ 396 typedef struct _MPI2_PORT_ENABLE_REQUEST 397 { 398 U16 Reserved1; /* 0x00 */ 399 U8 ChainOffset; /* 0x02 */ 400 U8 Function; /* 0x03 */ 401 U8 Reserved2; /* 0x04 */ 402 U8 PortFlags; /* 0x05 */ 403 U8 Reserved3; /* 0x06 */ 404 U8 MsgFlags; /* 0x07 */ 405 U8 VP_ID; /* 0x08 */ 406 U8 VF_ID; /* 0x09 */ 407 U16 Reserved4; /* 0x0A */ 408 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST, 409 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t; 410 411 412 /* PortEnable Reply message */ 413 typedef struct _MPI2_PORT_ENABLE_REPLY 414 { 415 U16 Reserved1; /* 0x00 */ 416 U8 MsgLength; /* 0x02 */ 417 U8 Function; /* 0x03 */ 418 U8 Reserved2; /* 0x04 */ 419 U8 PortFlags; /* 0x05 */ 420 U8 Reserved3; /* 0x06 */ 421 U8 MsgFlags; /* 0x07 */ 422 U8 VP_ID; /* 0x08 */ 423 U8 VF_ID; /* 0x09 */ 424 U16 Reserved4; /* 0x0A */ 425 U16 Reserved5; /* 0x0C */ 426 U16 IOCStatus; /* 0x0E */ 427 U32 IOCLogInfo; /* 0x10 */ 428 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY, 429 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t; 430 431 432 /**************************************************************************** 433 * EventNotification message 434 ****************************************************************************/ 435 436 /* EventNotification Request message */ 437 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4) 438 439 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST 440 { 441 U16 Reserved1; /* 0x00 */ 442 U8 ChainOffset; /* 0x02 */ 443 U8 Function; /* 0x03 */ 444 U16 Reserved2; /* 0x04 */ 445 U8 Reserved3; /* 0x06 */ 446 U8 MsgFlags; /* 0x07 */ 447 U8 VP_ID; /* 0x08 */ 448 U8 VF_ID; /* 0x09 */ 449 U16 Reserved4; /* 0x0A */ 450 U32 Reserved5; /* 0x0C */ 451 U32 Reserved6; /* 0x10 */ 452 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */ 453 U16 SASBroadcastPrimitiveMasks; /* 0x24 */ 454 U16 Reserved7; /* 0x26 */ 455 U32 Reserved8; /* 0x28 */ 456 } MPI2_EVENT_NOTIFICATION_REQUEST, 457 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST, 458 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t; 459 460 461 /* EventNotification Reply message */ 462 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY 463 { 464 U16 EventDataLength; /* 0x00 */ 465 U8 MsgLength; /* 0x02 */ 466 U8 Function; /* 0x03 */ 467 U16 Reserved1; /* 0x04 */ 468 U8 AckRequired; /* 0x06 */ 469 U8 MsgFlags; /* 0x07 */ 470 U8 VP_ID; /* 0x08 */ 471 U8 VF_ID; /* 0x09 */ 472 U16 Reserved2; /* 0x0A */ 473 U16 Reserved3; /* 0x0C */ 474 U16 IOCStatus; /* 0x0E */ 475 U32 IOCLogInfo; /* 0x10 */ 476 U16 Event; /* 0x14 */ 477 U16 Reserved4; /* 0x16 */ 478 U32 EventContext; /* 0x18 */ 479 U32 EventData[1]; /* 0x1C */ 480 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY, 481 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t; 482 483 /* AckRequired */ 484 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) 485 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) 486 487 /* Event */ 488 #define MPI2_EVENT_LOG_DATA (0x0001) 489 #define MPI2_EVENT_STATE_CHANGE (0x0002) 490 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005) 491 #define MPI2_EVENT_EVENT_CHANGE (0x000A) 492 #define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */ 493 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F) 494 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014) 495 #define MPI2_EVENT_SAS_DISCOVERY (0x0016) 496 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017) 497 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018) 498 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019) 499 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C) 500 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D) 501 #define MPI2_EVENT_IR_VOLUME (0x001E) 502 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F) 503 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020) 504 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021) 505 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022) 506 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023) 507 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024) 508 #define MPI2_EVENT_SAS_QUIESCE (0x0025) 509 510 511 /* Log Entry Added Event data */ 512 513 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */ 514 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C) 515 516 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED 517 { 518 U64 TimeStamp; /* 0x00 */ 519 U32 Reserved1; /* 0x08 */ 520 U16 LogSequence; /* 0x0C */ 521 U16 LogEntryQualifier; /* 0x0E */ 522 U8 VP_ID; /* 0x10 */ 523 U8 VF_ID; /* 0x11 */ 524 U16 Reserved2; /* 0x12 */ 525 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */ 526 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 527 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 528 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t; 529 530 /* GPIO Interrupt Event data */ 531 532 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT 533 { 534 U8 GPIONum; /* 0x00 */ 535 U8 Reserved1; /* 0x01 */ 536 U16 Reserved2; /* 0x02 */ 537 } MPI2_EVENT_DATA_GPIO_INTERRUPT, 538 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT, 539 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t; 540 541 /* Hard Reset Received Event data */ 542 543 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED 544 { 545 U8 Reserved1; /* 0x00 */ 546 U8 Port; /* 0x01 */ 547 U16 Reserved2; /* 0x02 */ 548 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 549 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 550 Mpi2EventDataHardResetReceived_t, 551 MPI2_POINTER pMpi2EventDataHardResetReceived_t; 552 553 /* Task Set Full Event data */ 554 /* this event is obsolete */ 555 556 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL 557 { 558 U16 DevHandle; /* 0x00 */ 559 U16 CurrentDepth; /* 0x02 */ 560 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL, 561 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t; 562 563 564 /* SAS Device Status Change Event data */ 565 566 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE 567 { 568 U16 TaskTag; /* 0x00 */ 569 U8 ReasonCode; /* 0x02 */ 570 U8 Reserved1; /* 0x03 */ 571 U8 ASC; /* 0x04 */ 572 U8 ASCQ; /* 0x05 */ 573 U16 DevHandle; /* 0x06 */ 574 U32 Reserved2; /* 0x08 */ 575 U64 SASAddress; /* 0x0C */ 576 U8 LUN[8]; /* 0x14 */ 577 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 578 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 579 Mpi2EventDataSasDeviceStatusChange_t, 580 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t; 581 582 /* SAS Device Status Change Event data ReasonCode values */ 583 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05) 584 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07) 585 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 586 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 587 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 588 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 589 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 590 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 591 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) 592 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) 593 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10) 594 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11) 595 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12) 596 597 598 /* Integrated RAID Operation Status Event data */ 599 600 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS 601 { 602 U16 VolDevHandle; /* 0x00 */ 603 U16 Reserved1; /* 0x02 */ 604 U8 RAIDOperation; /* 0x04 */ 605 U8 PercentComplete; /* 0x05 */ 606 U16 Reserved2; /* 0x06 */ 607 U32 Resereved3; /* 0x08 */ 608 } MPI2_EVENT_DATA_IR_OPERATION_STATUS, 609 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS, 610 Mpi2EventDataIrOperationStatus_t, 611 MPI2_POINTER pMpi2EventDataIrOperationStatus_t; 612 613 /* Integrated RAID Operation Status Event data RAIDOperation values */ 614 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00) 615 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01) 616 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02) 617 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03) 618 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04) 619 620 621 /* Integrated RAID Volume Event data */ 622 623 typedef struct _MPI2_EVENT_DATA_IR_VOLUME 624 { 625 U16 VolDevHandle; /* 0x00 */ 626 U8 ReasonCode; /* 0x02 */ 627 U8 Reserved1; /* 0x03 */ 628 U32 NewValue; /* 0x04 */ 629 U32 PreviousValue; /* 0x08 */ 630 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME, 631 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t; 632 633 /* Integrated RAID Volume Event data ReasonCode values */ 634 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01) 635 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02) 636 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03) 637 638 639 /* Integrated RAID Physical Disk Event data */ 640 641 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK 642 { 643 U16 Reserved1; /* 0x00 */ 644 U8 ReasonCode; /* 0x02 */ 645 U8 PhysDiskNum; /* 0x03 */ 646 U16 PhysDiskDevHandle; /* 0x04 */ 647 U16 Reserved2; /* 0x06 */ 648 U16 Slot; /* 0x08 */ 649 U16 EnclosureHandle; /* 0x0A */ 650 U32 NewValue; /* 0x0C */ 651 U32 PreviousValue; /* 0x10 */ 652 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 653 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 654 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t; 655 656 /* Integrated RAID Physical Disk Event data ReasonCode values */ 657 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01) 658 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02) 659 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03) 660 661 662 /* Integrated RAID Configuration Change List Event data */ 663 664 /* 665 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 666 * one and check NumElements at runtime. 667 */ 668 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT 669 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1) 670 #endif 671 672 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT 673 { 674 U16 ElementFlags; /* 0x00 */ 675 U16 VolDevHandle; /* 0x02 */ 676 U8 ReasonCode; /* 0x04 */ 677 U8 PhysDiskNum; /* 0x05 */ 678 U16 PhysDiskDevHandle; /* 0x06 */ 679 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT, 680 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t; 681 682 /* IR Configuration Change List Event data ElementFlags values */ 683 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F) 684 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000) 685 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001) 686 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002) 687 688 /* IR Configuration Change List Event data ReasonCode values */ 689 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01) 690 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02) 691 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03) 692 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04) 693 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05) 694 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06) 695 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07) 696 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08) 697 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09) 698 699 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST 700 { 701 U8 NumElements; /* 0x00 */ 702 U8 Reserved1; /* 0x01 */ 703 U8 Reserved2; /* 0x02 */ 704 U8 ConfigNum; /* 0x03 */ 705 U32 Flags; /* 0x04 */ 706 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */ 707 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 708 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 709 Mpi2EventDataIrConfigChangeList_t, 710 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t; 711 712 /* IR Configuration Change List Event data Flags values */ 713 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001) 714 715 716 /* SAS Discovery Event data */ 717 718 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY 719 { 720 U8 Flags; /* 0x00 */ 721 U8 ReasonCode; /* 0x01 */ 722 U8 PhysicalPort; /* 0x02 */ 723 U8 Reserved1; /* 0x03 */ 724 U32 DiscoveryStatus; /* 0x04 */ 725 } MPI2_EVENT_DATA_SAS_DISCOVERY, 726 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY, 727 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t; 728 729 /* SAS Discovery Event data Flags values */ 730 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02) 731 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01) 732 733 /* SAS Discovery Event data ReasonCode values */ 734 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01) 735 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02) 736 737 /* SAS Discovery Event data DiscoveryStatus values */ 738 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 739 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000) 740 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000) 741 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 742 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000) 743 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 744 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 745 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000) 746 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 747 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800) 748 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400) 749 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200) 750 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100) 751 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080) 752 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040) 753 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020) 754 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010) 755 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004) 756 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002) 757 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001) 758 759 760 /* SAS Broadcast Primitive Event data */ 761 762 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE 763 { 764 U8 PhyNum; /* 0x00 */ 765 U8 Port; /* 0x01 */ 766 U8 PortWidth; /* 0x02 */ 767 U8 Primitive; /* 0x03 */ 768 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 769 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 770 Mpi2EventDataSasBroadcastPrimitive_t, 771 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t; 772 773 /* defines for the Primitive field */ 774 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01) 775 #define MPI2_EVENT_PRIMITIVE_SES (0x02) 776 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03) 777 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 778 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05) 779 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06) 780 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07) 781 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08) 782 783 784 /* SAS Initiator Device Status Change Event data */ 785 786 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE 787 { 788 U8 ReasonCode; /* 0x00 */ 789 U8 PhysicalPort; /* 0x01 */ 790 U16 DevHandle; /* 0x02 */ 791 U64 SASAddress; /* 0x04 */ 792 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 793 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 794 Mpi2EventDataSasInitDevStatusChange_t, 795 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t; 796 797 /* SAS Initiator Device Status Change event ReasonCode values */ 798 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01) 799 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) 800 801 802 /* SAS Initiator Device Table Overflow Event data */ 803 804 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW 805 { 806 U16 MaxInit; /* 0x00 */ 807 U16 CurrentInit; /* 0x02 */ 808 U64 SASAddress; /* 0x04 */ 809 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 810 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 811 Mpi2EventDataSasInitTableOverflow_t, 812 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t; 813 814 815 /* SAS Topology Change List Event data */ 816 817 /* 818 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 819 * one and check NumEntries at runtime. 820 */ 821 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT 822 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1) 823 #endif 824 825 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY 826 { 827 U16 AttachedDevHandle; /* 0x00 */ 828 U8 LinkRate; /* 0x02 */ 829 U8 PhyStatus; /* 0x03 */ 830 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY, 831 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t; 832 833 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST 834 { 835 U16 EnclosureHandle; /* 0x00 */ 836 U16 ExpanderDevHandle; /* 0x02 */ 837 U8 NumPhys; /* 0x04 */ 838 U8 Reserved1; /* 0x05 */ 839 U16 Reserved2; /* 0x06 */ 840 U8 NumEntries; /* 0x08 */ 841 U8 StartPhyNum; /* 0x09 */ 842 U8 ExpStatus; /* 0x0A */ 843 U8 PhysicalPort; /* 0x0B */ 844 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/ 845 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 846 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 847 Mpi2EventDataSasTopologyChangeList_t, 848 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t; 849 850 /* values for the ExpStatus field */ 851 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) 852 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01) 853 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 854 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 855 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 856 857 /* defines for the LinkRate field */ 858 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0) 859 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) 860 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F) 861 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) 862 863 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) 864 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) 865 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) 866 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) 867 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) 868 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) 869 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) 870 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08) 871 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09) 872 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A) 873 874 /* values for the PhyStatus field */ 875 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80) 876 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10) 877 /* values for the PhyStatus ReasonCode sub-field */ 878 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F) 879 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01) 880 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02) 881 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03) 882 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04) 883 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05) 884 885 886 /* SAS Enclosure Device Status Change Event data */ 887 888 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE 889 { 890 U16 EnclosureHandle; /* 0x00 */ 891 U8 ReasonCode; /* 0x02 */ 892 U8 PhysicalPort; /* 0x03 */ 893 U64 EnclosureLogicalID; /* 0x04 */ 894 U16 NumSlots; /* 0x0C */ 895 U16 StartSlot; /* 0x0E */ 896 U32 PhyBits; /* 0x10 */ 897 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 898 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 899 Mpi2EventDataSasEnclDevStatusChange_t, 900 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t; 901 902 /* SAS Enclosure Device Status Change event ReasonCode values */ 903 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01) 904 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02) 905 906 907 /* SAS PHY Counter Event data */ 908 909 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER 910 { 911 U64 TimeStamp; /* 0x00 */ 912 U32 Reserved1; /* 0x08 */ 913 U8 PhyEventCode; /* 0x0C */ 914 U8 PhyNum; /* 0x0D */ 915 U16 Reserved2; /* 0x0E */ 916 U32 PhyEventInfo; /* 0x10 */ 917 U8 CounterType; /* 0x14 */ 918 U8 ThresholdWindow; /* 0x15 */ 919 U8 TimeUnits; /* 0x16 */ 920 U8 Reserved3; /* 0x17 */ 921 U32 EventThreshold; /* 0x18 */ 922 U16 ThresholdFlags; /* 0x1C */ 923 U16 Reserved4; /* 0x1E */ 924 } MPI2_EVENT_DATA_SAS_PHY_COUNTER, 925 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER, 926 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t; 927 928 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */ 929 930 /* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */ 931 932 /* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */ 933 934 /* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */ 935 936 937 /* SAS Quiesce Event data */ 938 939 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE 940 { 941 U8 ReasonCode; /* 0x00 */ 942 U8 Reserved1; /* 0x01 */ 943 U16 Reserved2; /* 0x02 */ 944 U32 Reserved3; /* 0x04 */ 945 } MPI2_EVENT_DATA_SAS_QUIESCE, 946 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE, 947 Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t; 948 949 /* SAS Quiesce Event data ReasonCode values */ 950 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01) 951 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02) 952 953 954 /* Host Based Discovery Phy Event data */ 955 956 typedef struct _MPI2_EVENT_HBD_PHY_SAS 957 { 958 U8 Flags; /* 0x00 */ 959 U8 NegotiatedLinkRate; /* 0x01 */ 960 U8 PhyNum; /* 0x02 */ 961 U8 PhysicalPort; /* 0x03 */ 962 U32 Reserved1; /* 0x04 */ 963 U8 InitialFrame[28]; /* 0x08 */ 964 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS, 965 Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t; 966 967 /* values for the Flags field */ 968 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02) 969 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01) 970 971 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for the NegotiatedLinkRate field */ 972 973 typedef union _MPI2_EVENT_HBD_DESCRIPTOR 974 { 975 MPI2_EVENT_HBD_PHY_SAS Sas; 976 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR, 977 Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t; 978 979 typedef struct _MPI2_EVENT_DATA_HBD_PHY 980 { 981 U8 DescriptorType; /* 0x00 */ 982 U8 Reserved1; /* 0x01 */ 983 U16 Reserved2; /* 0x02 */ 984 U32 Reserved3; /* 0x04 */ 985 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */ 986 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY, 987 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t; 988 989 /* values for the DescriptorType field */ 990 #define MPI2_EVENT_HBD_DT_SAS (0x01) 991 992 993 994 /**************************************************************************** 995 * EventAck message 996 ****************************************************************************/ 997 998 /* EventAck Request message */ 999 typedef struct _MPI2_EVENT_ACK_REQUEST 1000 { 1001 U16 Reserved1; /* 0x00 */ 1002 U8 ChainOffset; /* 0x02 */ 1003 U8 Function; /* 0x03 */ 1004 U16 Reserved2; /* 0x04 */ 1005 U8 Reserved3; /* 0x06 */ 1006 U8 MsgFlags; /* 0x07 */ 1007 U8 VP_ID; /* 0x08 */ 1008 U8 VF_ID; /* 0x09 */ 1009 U16 Reserved4; /* 0x0A */ 1010 U16 Event; /* 0x0C */ 1011 U16 Reserved5; /* 0x0E */ 1012 U32 EventContext; /* 0x10 */ 1013 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST, 1014 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t; 1015 1016 1017 /* EventAck Reply message */ 1018 typedef struct _MPI2_EVENT_ACK_REPLY 1019 { 1020 U16 Reserved1; /* 0x00 */ 1021 U8 MsgLength; /* 0x02 */ 1022 U8 Function; /* 0x03 */ 1023 U16 Reserved2; /* 0x04 */ 1024 U8 Reserved3; /* 0x06 */ 1025 U8 MsgFlags; /* 0x07 */ 1026 U8 VP_ID; /* 0x08 */ 1027 U8 VF_ID; /* 0x09 */ 1028 U16 Reserved4; /* 0x0A */ 1029 U16 Reserved5; /* 0x0C */ 1030 U16 IOCStatus; /* 0x0E */ 1031 U32 IOCLogInfo; /* 0x10 */ 1032 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY, 1033 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t; 1034 1035 1036 /**************************************************************************** 1037 * FWDownload message 1038 ****************************************************************************/ 1039 1040 /* FWDownload Request message */ 1041 typedef struct _MPI2_FW_DOWNLOAD_REQUEST 1042 { 1043 U8 ImageType; /* 0x00 */ 1044 U8 Reserved1; /* 0x01 */ 1045 U8 ChainOffset; /* 0x02 */ 1046 U8 Function; /* 0x03 */ 1047 U16 Reserved2; /* 0x04 */ 1048 U8 Reserved3; /* 0x06 */ 1049 U8 MsgFlags; /* 0x07 */ 1050 U8 VP_ID; /* 0x08 */ 1051 U8 VF_ID; /* 0x09 */ 1052 U16 Reserved4; /* 0x0A */ 1053 U32 TotalImageSize; /* 0x0C */ 1054 U32 Reserved5; /* 0x10 */ 1055 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1056 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST, 1057 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest; 1058 1059 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01) 1060 1061 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01) 1062 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02) 1063 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06) 1064 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07) 1065 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08) 1066 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09) 1067 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A) 1068 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1069 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0) 1070 1071 /* FWDownload TransactionContext Element */ 1072 typedef struct _MPI2_FW_DOWNLOAD_TCSGE 1073 { 1074 U8 Reserved1; /* 0x00 */ 1075 U8 ContextSize; /* 0x01 */ 1076 U8 DetailsLength; /* 0x02 */ 1077 U8 Flags; /* 0x03 */ 1078 U32 Reserved2; /* 0x04 */ 1079 U32 ImageOffset; /* 0x08 */ 1080 U32 ImageSize; /* 0x0C */ 1081 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE, 1082 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t; 1083 1084 /* FWDownload Reply message */ 1085 typedef struct _MPI2_FW_DOWNLOAD_REPLY 1086 { 1087 U8 ImageType; /* 0x00 */ 1088 U8 Reserved1; /* 0x01 */ 1089 U8 MsgLength; /* 0x02 */ 1090 U8 Function; /* 0x03 */ 1091 U16 Reserved2; /* 0x04 */ 1092 U8 Reserved3; /* 0x06 */ 1093 U8 MsgFlags; /* 0x07 */ 1094 U8 VP_ID; /* 0x08 */ 1095 U8 VF_ID; /* 0x09 */ 1096 U16 Reserved4; /* 0x0A */ 1097 U16 Reserved5; /* 0x0C */ 1098 U16 IOCStatus; /* 0x0E */ 1099 U32 IOCLogInfo; /* 0x10 */ 1100 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY, 1101 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t; 1102 1103 1104 /**************************************************************************** 1105 * FWUpload message 1106 ****************************************************************************/ 1107 1108 /* FWUpload Request message */ 1109 typedef struct _MPI2_FW_UPLOAD_REQUEST 1110 { 1111 U8 ImageType; /* 0x00 */ 1112 U8 Reserved1; /* 0x01 */ 1113 U8 ChainOffset; /* 0x02 */ 1114 U8 Function; /* 0x03 */ 1115 U16 Reserved2; /* 0x04 */ 1116 U8 Reserved3; /* 0x06 */ 1117 U8 MsgFlags; /* 0x07 */ 1118 U8 VP_ID; /* 0x08 */ 1119 U8 VF_ID; /* 0x09 */ 1120 U16 Reserved4; /* 0x0A */ 1121 U32 Reserved5; /* 0x0C */ 1122 U32 Reserved6; /* 0x10 */ 1123 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1124 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST, 1125 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t; 1126 1127 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00) 1128 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01) 1129 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) 1130 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05) 1131 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06) 1132 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07) 1133 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08) 1134 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09) 1135 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A) 1136 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1137 1138 typedef struct _MPI2_FW_UPLOAD_TCSGE 1139 { 1140 U8 Reserved1; /* 0x00 */ 1141 U8 ContextSize; /* 0x01 */ 1142 U8 DetailsLength; /* 0x02 */ 1143 U8 Flags; /* 0x03 */ 1144 U32 Reserved2; /* 0x04 */ 1145 U32 ImageOffset; /* 0x08 */ 1146 U32 ImageSize; /* 0x0C */ 1147 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE, 1148 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t; 1149 1150 /* FWUpload Reply message */ 1151 typedef struct _MPI2_FW_UPLOAD_REPLY 1152 { 1153 U8 ImageType; /* 0x00 */ 1154 U8 Reserved1; /* 0x01 */ 1155 U8 MsgLength; /* 0x02 */ 1156 U8 Function; /* 0x03 */ 1157 U16 Reserved2; /* 0x04 */ 1158 U8 Reserved3; /* 0x06 */ 1159 U8 MsgFlags; /* 0x07 */ 1160 U8 VP_ID; /* 0x08 */ 1161 U8 VF_ID; /* 0x09 */ 1162 U16 Reserved4; /* 0x0A */ 1163 U16 Reserved5; /* 0x0C */ 1164 U16 IOCStatus; /* 0x0E */ 1165 U32 IOCLogInfo; /* 0x10 */ 1166 U32 ActualImageSize; /* 0x14 */ 1167 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY, 1168 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t; 1169 1170 1171 /* FW Image Header */ 1172 typedef struct _MPI2_FW_IMAGE_HEADER 1173 { 1174 U32 Signature; /* 0x00 */ 1175 U32 Signature0; /* 0x04 */ 1176 U32 Signature1; /* 0x08 */ 1177 U32 Signature2; /* 0x0C */ 1178 MPI2_VERSION_UNION MPIVersion; /* 0x10 */ 1179 MPI2_VERSION_UNION FWVersion; /* 0x14 */ 1180 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */ 1181 MPI2_VERSION_UNION PackageVersion; /* 0x1C */ 1182 U16 VendorID; /* 0x20 */ 1183 U16 ProductID; /* 0x22 */ 1184 U16 ProtocolFlags; /* 0x24 */ 1185 U16 Reserved26; /* 0x26 */ 1186 U32 IOCCapabilities; /* 0x28 */ 1187 U32 ImageSize; /* 0x2C */ 1188 U32 NextImageHeaderOffset; /* 0x30 */ 1189 U32 Checksum; /* 0x34 */ 1190 U32 Reserved38; /* 0x38 */ 1191 U32 Reserved3C; /* 0x3C */ 1192 U32 Reserved40; /* 0x40 */ 1193 U32 Reserved44; /* 0x44 */ 1194 U32 Reserved48; /* 0x48 */ 1195 U32 Reserved4C; /* 0x4C */ 1196 U32 Reserved50; /* 0x50 */ 1197 U32 Reserved54; /* 0x54 */ 1198 U32 Reserved58; /* 0x58 */ 1199 U32 Reserved5C; /* 0x5C */ 1200 U32 Reserved60; /* 0x60 */ 1201 U32 FirmwareVersionNameWhat; /* 0x64 */ 1202 U8 FirmwareVersionName[32]; /* 0x68 */ 1203 U32 VendorNameWhat; /* 0x88 */ 1204 U8 VendorName[32]; /* 0x8C */ 1205 U32 PackageNameWhat; /* 0x88 */ 1206 U8 PackageName[32]; /* 0x8C */ 1207 U32 ReservedD0; /* 0xD0 */ 1208 U32 ReservedD4; /* 0xD4 */ 1209 U32 ReservedD8; /* 0xD8 */ 1210 U32 ReservedDC; /* 0xDC */ 1211 U32 ReservedE0; /* 0xE0 */ 1212 U32 ReservedE4; /* 0xE4 */ 1213 U32 ReservedE8; /* 0xE8 */ 1214 U32 ReservedEC; /* 0xEC */ 1215 U32 ReservedF0; /* 0xF0 */ 1216 U32 ReservedF4; /* 0xF4 */ 1217 U32 ReservedF8; /* 0xF8 */ 1218 U32 ReservedFC; /* 0xFC */ 1219 } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER, 1220 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t; 1221 1222 /* Signature field */ 1223 #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00) 1224 #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000) 1225 #define MPI2_FW_HEADER_SIGNATURE (0xEA000000) 1226 1227 /* Signature0 field */ 1228 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04) 1229 #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A) 1230 1231 /* Signature1 field */ 1232 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08) 1233 #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5) 1234 1235 /* Signature2 field */ 1236 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C) 1237 #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA) 1238 1239 1240 /* defines for using the ProductID field */ 1241 #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000) 1242 #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000) 1243 1244 #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00) 1245 #define MPI2_FW_HEADER_PID_PROD_A (0x0000) 1246 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) 1247 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700) 1248 1249 1250 #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF) 1251 /* SAS */ 1252 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013) 1253 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014) 1254 1255 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */ 1256 1257 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */ 1258 1259 1260 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C) 1261 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30) 1262 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64) 1263 1264 #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840) 1265 1266 #define MPI2_FW_HEADER_SIZE (0x100) 1267 1268 1269 /* Extended Image Header */ 1270 typedef struct _MPI2_EXT_IMAGE_HEADER 1271 1272 { 1273 U8 ImageType; /* 0x00 */ 1274 U8 Reserved1; /* 0x01 */ 1275 U16 Reserved2; /* 0x02 */ 1276 U32 Checksum; /* 0x04 */ 1277 U32 ImageSize; /* 0x08 */ 1278 U32 NextImageHeaderOffset; /* 0x0C */ 1279 U32 PackageVersion; /* 0x10 */ 1280 U32 Reserved3; /* 0x14 */ 1281 U32 Reserved4; /* 0x18 */ 1282 U32 Reserved5; /* 0x1C */ 1283 U8 IdentifyString[32]; /* 0x20 */ 1284 } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER, 1285 Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t; 1286 1287 /* useful offsets */ 1288 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00) 1289 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08) 1290 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C) 1291 1292 #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40) 1293 1294 /* defines for the ImageType field */ 1295 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) 1296 #define MPI2_EXT_IMAGE_TYPE_FW (0x01) 1297 #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03) 1298 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04) 1299 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05) 1300 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06) 1301 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07) 1302 #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08) 1303 1304 #define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MEGARAID) 1305 1306 1307 1308 /* FLASH Layout Extended Image Data */ 1309 1310 /* 1311 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1312 * one and check RegionsPerLayout at runtime. 1313 */ 1314 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS 1315 #define MPI2_FLASH_NUMBER_OF_REGIONS (1) 1316 #endif 1317 1318 /* 1319 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1320 * one and check NumberOfLayouts at runtime. 1321 */ 1322 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS 1323 #define MPI2_FLASH_NUMBER_OF_LAYOUTS (1) 1324 #endif 1325 1326 typedef struct _MPI2_FLASH_REGION 1327 { 1328 U8 RegionType; /* 0x00 */ 1329 U8 Reserved1; /* 0x01 */ 1330 U16 Reserved2; /* 0x02 */ 1331 U32 RegionOffset; /* 0x04 */ 1332 U32 RegionSize; /* 0x08 */ 1333 U32 Reserved3; /* 0x0C */ 1334 } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION, 1335 Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t; 1336 1337 typedef struct _MPI2_FLASH_LAYOUT 1338 { 1339 U32 FlashSize; /* 0x00 */ 1340 U32 Reserved1; /* 0x04 */ 1341 U32 Reserved2; /* 0x08 */ 1342 U32 Reserved3; /* 0x0C */ 1343 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */ 1344 } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT, 1345 Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t; 1346 1347 typedef struct _MPI2_FLASH_LAYOUT_DATA 1348 { 1349 U8 ImageRevision; /* 0x00 */ 1350 U8 Reserved1; /* 0x01 */ 1351 U8 SizeOfRegion; /* 0x02 */ 1352 U8 Reserved2; /* 0x03 */ 1353 U16 NumberOfLayouts; /* 0x04 */ 1354 U16 RegionsPerLayout; /* 0x06 */ 1355 U16 MinimumSectorAlignment; /* 0x08 */ 1356 U16 Reserved3; /* 0x0A */ 1357 U32 Reserved4; /* 0x0C */ 1358 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */ 1359 } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA, 1360 Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t; 1361 1362 /* defines for the RegionType field */ 1363 #define MPI2_FLASH_REGION_UNUSED (0x00) 1364 #define MPI2_FLASH_REGION_FIRMWARE (0x01) 1365 #define MPI2_FLASH_REGION_BIOS (0x02) 1366 #define MPI2_FLASH_REGION_NVDATA (0x03) 1367 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05) 1368 #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06) 1369 #define MPI2_FLASH_REGION_CONFIG_1 (0x07) 1370 #define MPI2_FLASH_REGION_CONFIG_2 (0x08) 1371 #define MPI2_FLASH_REGION_MEGARAID (0x09) 1372 #define MPI2_FLASH_REGION_INIT (0x0A) 1373 1374 /* ImageRevision */ 1375 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00) 1376 1377 1378 1379 /* Supported Devices Extended Image Data */ 1380 1381 /* 1382 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1383 * one and check NumberOfDevices at runtime. 1384 */ 1385 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES 1386 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1) 1387 #endif 1388 1389 typedef struct _MPI2_SUPPORTED_DEVICE 1390 { 1391 U16 DeviceID; /* 0x00 */ 1392 U16 VendorID; /* 0x02 */ 1393 U16 DeviceIDMask; /* 0x04 */ 1394 U16 Reserved1; /* 0x06 */ 1395 U8 LowPCIRev; /* 0x08 */ 1396 U8 HighPCIRev; /* 0x09 */ 1397 U16 Reserved2; /* 0x0A */ 1398 U32 Reserved3; /* 0x0C */ 1399 } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE, 1400 Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t; 1401 1402 typedef struct _MPI2_SUPPORTED_DEVICES_DATA 1403 { 1404 U8 ImageRevision; /* 0x00 */ 1405 U8 Reserved1; /* 0x01 */ 1406 U8 NumberOfDevices; /* 0x02 */ 1407 U8 Reserved2; /* 0x03 */ 1408 U32 Reserved3; /* 0x04 */ 1409 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */ 1410 } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA, 1411 Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t; 1412 1413 /* ImageRevision */ 1414 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00) 1415 1416 1417 /* Init Extended Image Data */ 1418 1419 typedef struct _MPI2_INIT_IMAGE_FOOTER 1420 1421 { 1422 U32 BootFlags; /* 0x00 */ 1423 U32 ImageSize; /* 0x04 */ 1424 U32 Signature0; /* 0x08 */ 1425 U32 Signature1; /* 0x0C */ 1426 U32 Signature2; /* 0x10 */ 1427 U32 ResetVector; /* 0x14 */ 1428 } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER, 1429 Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t; 1430 1431 /* defines for the BootFlags field */ 1432 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00) 1433 1434 /* defines for the ImageSize field */ 1435 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04) 1436 1437 /* defines for the Signature0 field */ 1438 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08) 1439 #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA) 1440 1441 /* defines for the Signature1 field */ 1442 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C) 1443 #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5) 1444 1445 /* defines for the Signature2 field */ 1446 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10) 1447 #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A) 1448 1449 /* Signature fields as individual bytes */ 1450 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA) 1451 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A) 1452 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5) 1453 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A) 1454 1455 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5) 1456 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA) 1457 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A) 1458 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5) 1459 1460 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A) 1461 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5) 1462 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA) 1463 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A) 1464 1465 /* defines for the ResetVector field */ 1466 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14) 1467 1468 1469 /**************************************************************************** 1470 * PowerManagementControl message 1471 ****************************************************************************/ 1472 1473 /* PowerManagementControl Request message */ 1474 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST 1475 { 1476 U8 Feature; /* 0x00 */ 1477 U8 Reserved1; /* 0x01 */ 1478 U8 ChainOffset; /* 0x02 */ 1479 U8 Function; /* 0x03 */ 1480 U16 Reserved2; /* 0x04 */ 1481 U8 Reserved3; /* 0x06 */ 1482 U8 MsgFlags; /* 0x07 */ 1483 U8 VP_ID; /* 0x08 */ 1484 U8 VF_ID; /* 0x09 */ 1485 U16 Reserved4; /* 0x0A */ 1486 U8 Parameter1; /* 0x0C */ 1487 U8 Parameter2; /* 0x0D */ 1488 U8 Parameter3; /* 0x0E */ 1489 U8 Parameter4; /* 0x0F */ 1490 U32 Reserved5; /* 0x10 */ 1491 U32 Reserved6; /* 0x14 */ 1492 } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST, 1493 Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t; 1494 1495 /* defines for the Feature field */ 1496 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01) 1497 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02) 1498 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) 1499 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04) 1500 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80) 1501 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF) 1502 1503 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */ 1504 /* Parameter1 contains a PHY number */ 1505 /* Parameter2 indicates power condition action using these defines */ 1506 #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01) 1507 #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02) 1508 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03) 1509 /* Parameter3 and Parameter4 are reserved */ 1510 1511 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION Feature */ 1512 /* Parameter1 contains SAS port width modulation group number */ 1513 /* Parameter2 indicates IOC action using these defines */ 1514 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01) 1515 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02) 1516 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03) 1517 /* Parameter3 indicates desired modulation level using these defines */ 1518 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00) 1519 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01) 1520 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02) 1521 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03) 1522 /* Parameter4 is reserved */ 1523 1524 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */ 1525 /* Parameter1 indicates desired PCIe link speed using these defines */ 1526 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) 1527 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) 1528 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) 1529 /* Parameter2 indicates desired PCIe link width using these defines */ 1530 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) 1531 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) 1532 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) 1533 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) 1534 /* Parameter3 and Parameter4 are reserved */ 1535 1536 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */ 1537 /* Parameter1 indicates desired IOC hardware clock speed using these defines */ 1538 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01) 1539 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02) 1540 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04) 1541 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08) 1542 /* Parameter2, Parameter3, and Parameter4 are reserved */ 1543 1544 1545 /* PowerManagementControl Reply message */ 1546 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY 1547 { 1548 U8 Feature; /* 0x00 */ 1549 U8 Reserved1; /* 0x01 */ 1550 U8 MsgLength; /* 0x02 */ 1551 U8 Function; /* 0x03 */ 1552 U16 Reserved2; /* 0x04 */ 1553 U8 Reserved3; /* 0x06 */ 1554 U8 MsgFlags; /* 0x07 */ 1555 U8 VP_ID; /* 0x08 */ 1556 U8 VF_ID; /* 0x09 */ 1557 U16 Reserved4; /* 0x0A */ 1558 U16 Reserved5; /* 0x0C */ 1559 U16 IOCStatus; /* 0x0E */ 1560 U32 IOCLogInfo; /* 0x10 */ 1561 } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY, 1562 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t; 1563 1564 1565 #endif 1566 1567