1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006-2015 LSI Corp. 5 * Copyright (c) 2013-2015 Avago Technologies 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD 30 */ 31 32 /* 33 * Copyright (c) 2006-2015 LSI Corporation. 34 * Copyright (c) 2013-2015 Avago Technologies 35 * 36 * 37 * Name: mpi2_ioc.h 38 * Title: MPI IOC, Port, Event, FW Download, and FW Upload messages 39 * Creation Date: October 11, 2006 40 * 41 * mpi2_ioc.h Version: 02.00.16 42 * 43 * Version History 44 * --------------- 45 * 46 * Date Version Description 47 * -------- -------- ------------------------------------------------------ 48 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 49 * 06-04-07 02.00.01 In IOCFacts Reply structure, renamed MaxDevices to 50 * MaxTargets. 51 * Added TotalImageSize field to FWDownload Request. 52 * Added reserved words to FWUpload Request. 53 * 06-26-07 02.00.02 Added IR Configuration Change List Event. 54 * 08-31-07 02.00.03 Removed SystemReplyQueueDepth field from the IOCInit 55 * request and replaced it with 56 * ReplyDescriptorPostQueueDepth and ReplyFreeQueueDepth. 57 * Replaced the MinReplyQueueDepth field of the IOCFacts 58 * reply with MaxReplyDescriptorPostQueueDepth. 59 * Added MPI2_RDPQ_DEPTH_MIN define to specify the minimum 60 * depth for the Reply Descriptor Post Queue. 61 * Added SASAddress field to Initiator Device Table 62 * Overflow Event data. 63 * 10-31-07 02.00.04 Added ReasonCode MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING 64 * for SAS Initiator Device Status Change Event data. 65 * Modified Reason Code defines for SAS Topology Change 66 * List Event data, including adding a bit for PHY Vacant 67 * status, and adding a mask for the Reason Code. 68 * Added define for 69 * MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING. 70 * Added define for MPI2_EXT_IMAGE_TYPE_MEGARAID. 71 * 12-18-07 02.00.05 Added Boot Status defines for the IOCExceptions field of 72 * the IOCFacts Reply. 73 * Removed MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 74 * Moved MPI2_VERSION_UNION to mpi2.h. 75 * Changed MPI2_EVENT_NOTIFICATION_REQUEST to use masks 76 * instead of enables, and added SASBroadcastPrimitiveMasks 77 * field. 78 * Added Log Entry Added Event and related structure. 79 * 02-29-08 02.00.06 Added define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID. 80 * Removed define MPI2_IOCFACTS_PROTOCOL_SMP_TARGET. 81 * Added MaxVolumes and MaxPersistentEntries fields to 82 * IOCFacts reply. 83 * Added ProtocalFlags and IOCCapabilities fields to 84 * MPI2_FW_IMAGE_HEADER. 85 * Removed MPI2_PORTENABLE_FLAGS_ENABLE_SINGLE_PORT. 86 * 03-03-08 02.00.07 Fixed MPI2_FW_IMAGE_HEADER by changing Reserved26 to 87 * a U16 (from a U32). 88 * Removed extra 's' from EventMasks name. 89 * 06-27-08 02.00.08 Fixed an offset in a comment. 90 * 10-02-08 02.00.09 Removed SystemReplyFrameSize from MPI2_IOC_INIT_REQUEST. 91 * Removed CurReplyFrameSize from MPI2_IOC_FACTS_REPLY and 92 * renamed MinReplyFrameSize to ReplyFrameSize. 93 * Added MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX. 94 * Added two new RAIDOperation values for Integrated RAID 95 * Operations Status Event data. 96 * Added four new IR Configuration Change List Event data 97 * ReasonCode values. 98 * Added two new ReasonCode defines for SAS Device Status 99 * Change Event data. 100 * Added three new DiscoveryStatus bits for the SAS 101 * Discovery event data. 102 * Added Multiplexing Status Change bit to the PhyStatus 103 * field of the SAS Topology Change List event data. 104 * Removed define for MPI2_INIT_IMAGE_BOOTFLAGS_XMEMCOPY. 105 * BootFlags are now product-specific. 106 * Added defines for the indivdual signature bytes 107 * for MPI2_INIT_IMAGE_FOOTER. 108 * 01-19-09 02.00.10 Added MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY define. 109 * Added MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR 110 * define. 111 * Added MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE 112 * define. 113 * Removed MPI2_EVENT_SAS_DISC_DS_SATA_INIT_FAILURE define. 114 * 05-06-09 02.00.11 Added MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR define. 115 * Added MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX define. 116 * Added two new reason codes for SAS Device Status Change 117 * Event. 118 * Added new event: SAS PHY Counter. 119 * 07-30-09 02.00.12 Added GPIO Interrupt event define and structure. 120 * Added MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER define. 121 * Added new product id family for 2208. 122 * 10-28-09 02.00.13 Added HostMSIxVectors field to MPI2_IOC_INIT_REQUEST. 123 * Added MaxMSIxVectors field to MPI2_IOC_FACTS_REPLY. 124 * Added MinDevHandle field to MPI2_IOC_FACTS_REPLY. 125 * Added MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY. 126 * Added MPI2_EVENT_HOST_BASED_DISCOVERY_PHY define. 127 * Added MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER define. 128 * Added Host Based Discovery Phy Event data. 129 * Added defines for ProductID Product field 130 * (MPI2_FW_HEADER_PID_). 131 * Modified values for SAS ProductID Family 132 * (MPI2_FW_HEADER_PID_FAMILY_). 133 * 02-10-10 02.00.14 Added SAS Quiesce Event structure and defines. 134 * Added PowerManagementControl Request structures and 135 * defines. 136 * 05-12-10 02.00.15 Marked Task Set Full Event as obsolete. 137 * Added MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY define. 138 * 11-10-10 02.00.16 Added MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC. 139 * -------------------------------------------------------------------------- 140 */ 141 142 #ifndef MPI2_IOC_H 143 #define MPI2_IOC_H 144 145 /***************************************************************************** 146 * 147 * IOC Messages 148 * 149 *****************************************************************************/ 150 151 /**************************************************************************** 152 * IOCInit message 153 ****************************************************************************/ 154 155 /* IOCInit Request message */ 156 typedef struct _MPI2_IOC_INIT_REQUEST 157 { 158 U8 WhoInit; /* 0x00 */ 159 U8 Reserved1; /* 0x01 */ 160 U8 ChainOffset; /* 0x02 */ 161 U8 Function; /* 0x03 */ 162 U16 Reserved2; /* 0x04 */ 163 U8 Reserved3; /* 0x06 */ 164 U8 MsgFlags; /* 0x07 */ 165 U8 VP_ID; /* 0x08 */ 166 U8 VF_ID; /* 0x09 */ 167 U16 Reserved4; /* 0x0A */ 168 U16 MsgVersion; /* 0x0C */ 169 U16 HeaderVersion; /* 0x0E */ 170 U32 Reserved5; /* 0x10 */ 171 U16 Reserved6; /* 0x14 */ 172 U8 Reserved7; /* 0x16 */ 173 U8 HostMSIxVectors; /* 0x17 */ 174 U16 Reserved8; /* 0x18 */ 175 U16 SystemRequestFrameSize; /* 0x1A */ 176 U16 ReplyDescriptorPostQueueDepth; /* 0x1C */ 177 U16 ReplyFreeQueueDepth; /* 0x1E */ 178 U32 SenseBufferAddressHigh; /* 0x20 */ 179 U32 SystemReplyAddressHigh; /* 0x24 */ 180 U64 SystemRequestFrameBaseAddress; /* 0x28 */ 181 U64 ReplyDescriptorPostQueueAddress;/* 0x30 */ 182 U64 ReplyFreeQueueAddress; /* 0x38 */ 183 U64 TimeStamp; /* 0x40 */ 184 } MPI2_IOC_INIT_REQUEST, MPI2_POINTER PTR_MPI2_IOC_INIT_REQUEST, 185 Mpi2IOCInitRequest_t, MPI2_POINTER pMpi2IOCInitRequest_t; 186 187 /* WhoInit values */ 188 #define MPI2_WHOINIT_NOT_INITIALIZED (0x00) 189 #define MPI2_WHOINIT_SYSTEM_BIOS (0x01) 190 #define MPI2_WHOINIT_ROM_BIOS (0x02) 191 #define MPI2_WHOINIT_PCI_PEER (0x03) 192 #define MPI2_WHOINIT_HOST_DRIVER (0x04) 193 #define MPI2_WHOINIT_MANUFACTURER (0x05) 194 195 /* MsgVersion */ 196 #define MPI2_IOCINIT_MSGVERSION_MAJOR_MASK (0xFF00) 197 #define MPI2_IOCINIT_MSGVERSION_MAJOR_SHIFT (8) 198 #define MPI2_IOCINIT_MSGVERSION_MINOR_MASK (0x00FF) 199 #define MPI2_IOCINIT_MSGVERSION_MINOR_SHIFT (0) 200 201 /* HeaderVersion */ 202 #define MPI2_IOCINIT_HDRVERSION_UNIT_MASK (0xFF00) 203 #define MPI2_IOCINIT_HDRVERSION_UNIT_SHIFT (8) 204 #define MPI2_IOCINIT_HDRVERSION_DEV_MASK (0x00FF) 205 #define MPI2_IOCINIT_HDRVERSION_DEV_SHIFT (0) 206 207 /* minimum depth for the Reply Descriptor Post Queue */ 208 #define MPI2_RDPQ_DEPTH_MIN (16) 209 210 /* IOCInit Reply message */ 211 typedef struct _MPI2_IOC_INIT_REPLY 212 { 213 U8 WhoInit; /* 0x00 */ 214 U8 Reserved1; /* 0x01 */ 215 U8 MsgLength; /* 0x02 */ 216 U8 Function; /* 0x03 */ 217 U16 Reserved2; /* 0x04 */ 218 U8 Reserved3; /* 0x06 */ 219 U8 MsgFlags; /* 0x07 */ 220 U8 VP_ID; /* 0x08 */ 221 U8 VF_ID; /* 0x09 */ 222 U16 Reserved4; /* 0x0A */ 223 U16 Reserved5; /* 0x0C */ 224 U16 IOCStatus; /* 0x0E */ 225 U32 IOCLogInfo; /* 0x10 */ 226 } MPI2_IOC_INIT_REPLY, MPI2_POINTER PTR_MPI2_IOC_INIT_REPLY, 227 Mpi2IOCInitReply_t, MPI2_POINTER pMpi2IOCInitReply_t; 228 229 /**************************************************************************** 230 * IOCFacts message 231 ****************************************************************************/ 232 233 /* IOCFacts Request message */ 234 typedef struct _MPI2_IOC_FACTS_REQUEST 235 { 236 U16 Reserved1; /* 0x00 */ 237 U8 ChainOffset; /* 0x02 */ 238 U8 Function; /* 0x03 */ 239 U16 Reserved2; /* 0x04 */ 240 U8 Reserved3; /* 0x06 */ 241 U8 MsgFlags; /* 0x07 */ 242 U8 VP_ID; /* 0x08 */ 243 U8 VF_ID; /* 0x09 */ 244 U16 Reserved4; /* 0x0A */ 245 } MPI2_IOC_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_IOC_FACTS_REQUEST, 246 Mpi2IOCFactsRequest_t, MPI2_POINTER pMpi2IOCFactsRequest_t; 247 248 /* IOCFacts Reply message */ 249 typedef struct _MPI2_IOC_FACTS_REPLY 250 { 251 U16 MsgVersion; /* 0x00 */ 252 U8 MsgLength; /* 0x02 */ 253 U8 Function; /* 0x03 */ 254 U16 HeaderVersion; /* 0x04 */ 255 U8 IOCNumber; /* 0x06 */ 256 U8 MsgFlags; /* 0x07 */ 257 U8 VP_ID; /* 0x08 */ 258 U8 VF_ID; /* 0x09 */ 259 U16 Reserved1; /* 0x0A */ 260 U16 IOCExceptions; /* 0x0C */ 261 U16 IOCStatus; /* 0x0E */ 262 U32 IOCLogInfo; /* 0x10 */ 263 U8 MaxChainDepth; /* 0x14 */ 264 U8 WhoInit; /* 0x15 */ 265 U8 NumberOfPorts; /* 0x16 */ 266 U8 MaxMSIxVectors; /* 0x17 */ 267 U16 RequestCredit; /* 0x18 */ 268 U16 ProductID; /* 0x1A */ 269 U32 IOCCapabilities; /* 0x1C */ 270 MPI2_VERSION_UNION FWVersion; /* 0x20 */ 271 U16 IOCRequestFrameSize; /* 0x24 */ 272 U16 Reserved3; /* 0x26 */ 273 U16 MaxInitiators; /* 0x28 */ 274 U16 MaxTargets; /* 0x2A */ 275 U16 MaxSasExpanders; /* 0x2C */ 276 U16 MaxEnclosures; /* 0x2E */ 277 U16 ProtocolFlags; /* 0x30 */ 278 U16 HighPriorityCredit; /* 0x32 */ 279 U16 MaxReplyDescriptorPostQueueDepth; /* 0x34 */ 280 U8 ReplyFrameSize; /* 0x36 */ 281 U8 MaxVolumes; /* 0x37 */ 282 U16 MaxDevHandle; /* 0x38 */ 283 U16 MaxPersistentEntries; /* 0x3A */ 284 U16 MinDevHandle; /* 0x3C */ 285 U16 Reserved4; /* 0x3E */ 286 } MPI2_IOC_FACTS_REPLY, MPI2_POINTER PTR_MPI2_IOC_FACTS_REPLY, 287 Mpi2IOCFactsReply_t, MPI2_POINTER pMpi2IOCFactsReply_t; 288 289 /* MsgVersion */ 290 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK (0xFF00) 291 #define MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT (8) 292 #define MPI2_IOCFACTS_MSGVERSION_MINOR_MASK (0x00FF) 293 #define MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT (0) 294 295 /* HeaderVersion */ 296 #define MPI2_IOCFACTS_HDRVERSION_UNIT_MASK (0xFF00) 297 #define MPI2_IOCFACTS_HDRVERSION_UNIT_SHIFT (8) 298 #define MPI2_IOCFACTS_HDRVERSION_DEV_MASK (0x00FF) 299 #define MPI2_IOCFACTS_HDRVERSION_DEV_SHIFT (0) 300 301 /* IOCExceptions */ 302 #define MPI2_IOCFACTS_EXCEPT_IR_FOREIGN_CONFIG_MAX (0x0100) 303 304 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_MASK (0x00E0) 305 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_GOOD (0x0000) 306 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_BACKUP (0x0020) 307 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_RESTORED (0x0040) 308 #define MPI2_IOCFACTS_EXCEPT_BOOTSTAT_CORRUPT_BACKUP (0x0060) 309 310 #define MPI2_IOCFACTS_EXCEPT_METADATA_UNSUPPORTED (0x0010) 311 #define MPI2_IOCFACTS_EXCEPT_MANUFACT_CHECKSUM_FAIL (0x0008) 312 #define MPI2_IOCFACTS_EXCEPT_FW_CHECKSUM_FAIL (0x0004) 313 #define MPI2_IOCFACTS_EXCEPT_RAID_CONFIG_INVALID (0x0002) 314 #define MPI2_IOCFACTS_EXCEPT_CONFIG_CHECKSUM_FAIL (0x0001) 315 316 /* defines for WhoInit field are after the IOCInit Request */ 317 318 /* ProductID field uses MPI2_FW_HEADER_PID_ */ 319 320 /* IOCCapabilities */ 321 #define MPI2_IOCFACTS_CAPABILITY_HOST_BASED_DISCOVERY (0x00010000) 322 #define MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX (0x00008000) 323 #define MPI2_IOCFACTS_CAPABILITY_RAID_ACCELERATOR (0x00004000) 324 #define MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY (0x00002000) 325 #define MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID (0x00001000) 326 #define MPI2_IOCFACTS_CAPABILITY_TLR (0x00000800) 327 #define MPI2_IOCFACTS_CAPABILITY_MULTICAST (0x00000100) 328 #define MPI2_IOCFACTS_CAPABILITY_BIDIRECTIONAL_TARGET (0x00000080) 329 #define MPI2_IOCFACTS_CAPABILITY_EEDP (0x00000040) 330 #define MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER (0x00000020) 331 #define MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER (0x00000010) 332 #define MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER (0x00000008) 333 #define MPI2_IOCFACTS_CAPABILITY_TASK_SET_FULL_HANDLING (0x00000004) 334 335 /* ProtocolFlags */ 336 #define MPI2_IOCFACTS_PROTOCOL_SCSI_TARGET (0x0001) 337 #define MPI2_IOCFACTS_PROTOCOL_SCSI_INITIATOR (0x0002) 338 339 /**************************************************************************** 340 * PortFacts message 341 ****************************************************************************/ 342 343 /* PortFacts Request message */ 344 typedef struct _MPI2_PORT_FACTS_REQUEST 345 { 346 U16 Reserved1; /* 0x00 */ 347 U8 ChainOffset; /* 0x02 */ 348 U8 Function; /* 0x03 */ 349 U16 Reserved2; /* 0x04 */ 350 U8 PortNumber; /* 0x06 */ 351 U8 MsgFlags; /* 0x07 */ 352 U8 VP_ID; /* 0x08 */ 353 U8 VF_ID; /* 0x09 */ 354 U16 Reserved3; /* 0x0A */ 355 } MPI2_PORT_FACTS_REQUEST, MPI2_POINTER PTR_MPI2_PORT_FACTS_REQUEST, 356 Mpi2PortFactsRequest_t, MPI2_POINTER pMpi2PortFactsRequest_t; 357 358 /* PortFacts Reply message */ 359 typedef struct _MPI2_PORT_FACTS_REPLY 360 { 361 U16 Reserved1; /* 0x00 */ 362 U8 MsgLength; /* 0x02 */ 363 U8 Function; /* 0x03 */ 364 U16 Reserved2; /* 0x04 */ 365 U8 PortNumber; /* 0x06 */ 366 U8 MsgFlags; /* 0x07 */ 367 U8 VP_ID; /* 0x08 */ 368 U8 VF_ID; /* 0x09 */ 369 U16 Reserved3; /* 0x0A */ 370 U16 Reserved4; /* 0x0C */ 371 U16 IOCStatus; /* 0x0E */ 372 U32 IOCLogInfo; /* 0x10 */ 373 U8 Reserved5; /* 0x14 */ 374 U8 PortType; /* 0x15 */ 375 U16 Reserved6; /* 0x16 */ 376 U16 MaxPostedCmdBuffers; /* 0x18 */ 377 U16 Reserved7; /* 0x1A */ 378 } MPI2_PORT_FACTS_REPLY, MPI2_POINTER PTR_MPI2_PORT_FACTS_REPLY, 379 Mpi2PortFactsReply_t, MPI2_POINTER pMpi2PortFactsReply_t; 380 381 /* PortType values */ 382 #define MPI2_PORTFACTS_PORTTYPE_INACTIVE (0x00) 383 #define MPI2_PORTFACTS_PORTTYPE_FC (0x10) 384 #define MPI2_PORTFACTS_PORTTYPE_ISCSI (0x20) 385 #define MPI2_PORTFACTS_PORTTYPE_SAS_PHYSICAL (0x30) 386 #define MPI2_PORTFACTS_PORTTYPE_SAS_VIRTUAL (0x31) 387 388 /**************************************************************************** 389 * PortEnable message 390 ****************************************************************************/ 391 392 /* PortEnable Request message */ 393 typedef struct _MPI2_PORT_ENABLE_REQUEST 394 { 395 U16 Reserved1; /* 0x00 */ 396 U8 ChainOffset; /* 0x02 */ 397 U8 Function; /* 0x03 */ 398 U8 Reserved2; /* 0x04 */ 399 U8 PortFlags; /* 0x05 */ 400 U8 Reserved3; /* 0x06 */ 401 U8 MsgFlags; /* 0x07 */ 402 U8 VP_ID; /* 0x08 */ 403 U8 VF_ID; /* 0x09 */ 404 U16 Reserved4; /* 0x0A */ 405 } MPI2_PORT_ENABLE_REQUEST, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REQUEST, 406 Mpi2PortEnableRequest_t, MPI2_POINTER pMpi2PortEnableRequest_t; 407 408 /* PortEnable Reply message */ 409 typedef struct _MPI2_PORT_ENABLE_REPLY 410 { 411 U16 Reserved1; /* 0x00 */ 412 U8 MsgLength; /* 0x02 */ 413 U8 Function; /* 0x03 */ 414 U8 Reserved2; /* 0x04 */ 415 U8 PortFlags; /* 0x05 */ 416 U8 Reserved3; /* 0x06 */ 417 U8 MsgFlags; /* 0x07 */ 418 U8 VP_ID; /* 0x08 */ 419 U8 VF_ID; /* 0x09 */ 420 U16 Reserved4; /* 0x0A */ 421 U16 Reserved5; /* 0x0C */ 422 U16 IOCStatus; /* 0x0E */ 423 U32 IOCLogInfo; /* 0x10 */ 424 } MPI2_PORT_ENABLE_REPLY, MPI2_POINTER PTR_MPI2_PORT_ENABLE_REPLY, 425 Mpi2PortEnableReply_t, MPI2_POINTER pMpi2PortEnableReply_t; 426 427 /**************************************************************************** 428 * EventNotification message 429 ****************************************************************************/ 430 431 /* EventNotification Request message */ 432 #define MPI2_EVENT_NOTIFY_EVENTMASK_WORDS (4) 433 434 typedef struct _MPI2_EVENT_NOTIFICATION_REQUEST 435 { 436 U16 Reserved1; /* 0x00 */ 437 U8 ChainOffset; /* 0x02 */ 438 U8 Function; /* 0x03 */ 439 U16 Reserved2; /* 0x04 */ 440 U8 Reserved3; /* 0x06 */ 441 U8 MsgFlags; /* 0x07 */ 442 U8 VP_ID; /* 0x08 */ 443 U8 VF_ID; /* 0x09 */ 444 U16 Reserved4; /* 0x0A */ 445 U32 Reserved5; /* 0x0C */ 446 U32 Reserved6; /* 0x10 */ 447 U32 EventMasks[MPI2_EVENT_NOTIFY_EVENTMASK_WORDS];/* 0x14 */ 448 U16 SASBroadcastPrimitiveMasks; /* 0x24 */ 449 U16 Reserved7; /* 0x26 */ 450 U32 Reserved8; /* 0x28 */ 451 } MPI2_EVENT_NOTIFICATION_REQUEST, 452 MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REQUEST, 453 Mpi2EventNotificationRequest_t, MPI2_POINTER pMpi2EventNotificationRequest_t; 454 455 /* EventNotification Reply message */ 456 typedef struct _MPI2_EVENT_NOTIFICATION_REPLY 457 { 458 U16 EventDataLength; /* 0x00 */ 459 U8 MsgLength; /* 0x02 */ 460 U8 Function; /* 0x03 */ 461 U16 Reserved1; /* 0x04 */ 462 U8 AckRequired; /* 0x06 */ 463 U8 MsgFlags; /* 0x07 */ 464 U8 VP_ID; /* 0x08 */ 465 U8 VF_ID; /* 0x09 */ 466 U16 Reserved2; /* 0x0A */ 467 U16 Reserved3; /* 0x0C */ 468 U16 IOCStatus; /* 0x0E */ 469 U32 IOCLogInfo; /* 0x10 */ 470 U16 Event; /* 0x14 */ 471 U16 Reserved4; /* 0x16 */ 472 U32 EventContext; /* 0x18 */ 473 U32 EventData[1]; /* 0x1C */ 474 } MPI2_EVENT_NOTIFICATION_REPLY, MPI2_POINTER PTR_MPI2_EVENT_NOTIFICATION_REPLY, 475 Mpi2EventNotificationReply_t, MPI2_POINTER pMpi2EventNotificationReply_t; 476 477 /* AckRequired */ 478 #define MPI2_EVENT_NOTIFICATION_ACK_NOT_REQUIRED (0x00) 479 #define MPI2_EVENT_NOTIFICATION_ACK_REQUIRED (0x01) 480 481 /* Event */ 482 #define MPI2_EVENT_LOG_DATA (0x0001) 483 #define MPI2_EVENT_STATE_CHANGE (0x0002) 484 #define MPI2_EVENT_HARD_RESET_RECEIVED (0x0005) 485 #define MPI2_EVENT_EVENT_CHANGE (0x000A) 486 #define MPI2_EVENT_TASK_SET_FULL (0x000E) /* obsolete */ 487 #define MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE (0x000F) 488 #define MPI2_EVENT_IR_OPERATION_STATUS (0x0014) 489 #define MPI2_EVENT_SAS_DISCOVERY (0x0016) 490 #define MPI2_EVENT_SAS_BROADCAST_PRIMITIVE (0x0017) 491 #define MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE (0x0018) 492 #define MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW (0x0019) 493 #define MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST (0x001C) 494 #define MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE (0x001D) 495 #define MPI2_EVENT_IR_VOLUME (0x001E) 496 #define MPI2_EVENT_IR_PHYSICAL_DISK (0x001F) 497 #define MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST (0x0020) 498 #define MPI2_EVENT_LOG_ENTRY_ADDED (0x0021) 499 #define MPI2_EVENT_SAS_PHY_COUNTER (0x0022) 500 #define MPI2_EVENT_GPIO_INTERRUPT (0x0023) 501 #define MPI2_EVENT_HOST_BASED_DISCOVERY_PHY (0x0024) 502 #define MPI2_EVENT_SAS_QUIESCE (0x0025) 503 504 /* Log Entry Added Event data */ 505 506 /* the following structure matches MPI2_LOG_0_ENTRY in mpi2_cnfg.h */ 507 #define MPI2_EVENT_DATA_LOG_DATA_LENGTH (0x1C) 508 509 typedef struct _MPI2_EVENT_DATA_LOG_ENTRY_ADDED 510 { 511 U64 TimeStamp; /* 0x00 */ 512 U32 Reserved1; /* 0x08 */ 513 U16 LogSequence; /* 0x0C */ 514 U16 LogEntryQualifier; /* 0x0E */ 515 U8 VP_ID; /* 0x10 */ 516 U8 VF_ID; /* 0x11 */ 517 U16 Reserved2; /* 0x12 */ 518 U8 LogData[MPI2_EVENT_DATA_LOG_DATA_LENGTH];/* 0x14 */ 519 } MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 520 MPI2_POINTER PTR_MPI2_EVENT_DATA_LOG_ENTRY_ADDED, 521 Mpi2EventDataLogEntryAdded_t, MPI2_POINTER pMpi2EventDataLogEntryAdded_t; 522 523 /* GPIO Interrupt Event data */ 524 525 typedef struct _MPI2_EVENT_DATA_GPIO_INTERRUPT 526 { 527 U8 GPIONum; /* 0x00 */ 528 U8 Reserved1; /* 0x01 */ 529 U16 Reserved2; /* 0x02 */ 530 } MPI2_EVENT_DATA_GPIO_INTERRUPT, 531 MPI2_POINTER PTR_MPI2_EVENT_DATA_GPIO_INTERRUPT, 532 Mpi2EventDataGpioInterrupt_t, MPI2_POINTER pMpi2EventDataGpioInterrupt_t; 533 534 /* Hard Reset Received Event data */ 535 536 typedef struct _MPI2_EVENT_DATA_HARD_RESET_RECEIVED 537 { 538 U8 Reserved1; /* 0x00 */ 539 U8 Port; /* 0x01 */ 540 U16 Reserved2; /* 0x02 */ 541 } MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 542 MPI2_POINTER PTR_MPI2_EVENT_DATA_HARD_RESET_RECEIVED, 543 Mpi2EventDataHardResetReceived_t, 544 MPI2_POINTER pMpi2EventDataHardResetReceived_t; 545 546 /* Task Set Full Event data */ 547 /* this event is obsolete */ 548 549 typedef struct _MPI2_EVENT_DATA_TASK_SET_FULL 550 { 551 U16 DevHandle; /* 0x00 */ 552 U16 CurrentDepth; /* 0x02 */ 553 } MPI2_EVENT_DATA_TASK_SET_FULL, MPI2_POINTER PTR_MPI2_EVENT_DATA_TASK_SET_FULL, 554 Mpi2EventDataTaskSetFull_t, MPI2_POINTER pMpi2EventDataTaskSetFull_t; 555 556 /* SAS Device Status Change Event data */ 557 558 typedef struct _MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE 559 { 560 U16 TaskTag; /* 0x00 */ 561 U8 ReasonCode; /* 0x02 */ 562 U8 Reserved1; /* 0x03 */ 563 U8 ASC; /* 0x04 */ 564 U8 ASCQ; /* 0x05 */ 565 U16 DevHandle; /* 0x06 */ 566 U32 Reserved2; /* 0x08 */ 567 U64 SASAddress; /* 0x0C */ 568 U8 LUN[8]; /* 0x14 */ 569 } MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 570 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DEVICE_STATUS_CHANGE, 571 Mpi2EventDataSasDeviceStatusChange_t, 572 MPI2_POINTER pMpi2EventDataSasDeviceStatusChange_t; 573 574 /* SAS Device Status Change Event data ReasonCode values */ 575 #define MPI2_EVENT_SAS_DEV_STAT_RC_SMART_DATA (0x05) 576 #define MPI2_EVENT_SAS_DEV_STAT_RC_UNSUPPORTED (0x07) 577 #define MPI2_EVENT_SAS_DEV_STAT_RC_INTERNAL_DEVICE_RESET (0x08) 578 #define MPI2_EVENT_SAS_DEV_STAT_RC_TASK_ABORT_INTERNAL (0x09) 579 #define MPI2_EVENT_SAS_DEV_STAT_RC_ABORT_TASK_SET_INTERNAL (0x0A) 580 #define MPI2_EVENT_SAS_DEV_STAT_RC_CLEAR_TASK_SET_INTERNAL (0x0B) 581 #define MPI2_EVENT_SAS_DEV_STAT_RC_QUERY_TASK_INTERNAL (0x0C) 582 #define MPI2_EVENT_SAS_DEV_STAT_RC_ASYNC_NOTIFICATION (0x0D) 583 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_INTERNAL_DEV_RESET (0x0E) 584 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_TASK_ABORT_INTERNAL (0x0F) 585 #define MPI2_EVENT_SAS_DEV_STAT_RC_SATA_INIT_FAILURE (0x10) 586 #define MPI2_EVENT_SAS_DEV_STAT_RC_EXPANDER_REDUCED_FUNCTIONALITY (0x11) 587 #define MPI2_EVENT_SAS_DEV_STAT_RC_CMP_EXPANDER_REDUCED_FUNCTIONALITY (0x12) 588 589 /* Integrated RAID Operation Status Event data */ 590 591 typedef struct _MPI2_EVENT_DATA_IR_OPERATION_STATUS 592 { 593 U16 VolDevHandle; /* 0x00 */ 594 U16 Reserved1; /* 0x02 */ 595 U8 RAIDOperation; /* 0x04 */ 596 U8 PercentComplete; /* 0x05 */ 597 U16 Reserved2; /* 0x06 */ 598 U32 Resereved3; /* 0x08 */ 599 } MPI2_EVENT_DATA_IR_OPERATION_STATUS, 600 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_OPERATION_STATUS, 601 Mpi2EventDataIrOperationStatus_t, 602 MPI2_POINTER pMpi2EventDataIrOperationStatus_t; 603 604 /* Integrated RAID Operation Status Event data RAIDOperation values */ 605 #define MPI2_EVENT_IR_RAIDOP_RESYNC (0x00) 606 #define MPI2_EVENT_IR_RAIDOP_ONLINE_CAP_EXPANSION (0x01) 607 #define MPI2_EVENT_IR_RAIDOP_CONSISTENCY_CHECK (0x02) 608 #define MPI2_EVENT_IR_RAIDOP_BACKGROUND_INIT (0x03) 609 #define MPI2_EVENT_IR_RAIDOP_MAKE_DATA_CONSISTENT (0x04) 610 611 /* Integrated RAID Volume Event data */ 612 613 typedef struct _MPI2_EVENT_DATA_IR_VOLUME 614 { 615 U16 VolDevHandle; /* 0x00 */ 616 U8 ReasonCode; /* 0x02 */ 617 U8 Reserved1; /* 0x03 */ 618 U32 NewValue; /* 0x04 */ 619 U32 PreviousValue; /* 0x08 */ 620 } MPI2_EVENT_DATA_IR_VOLUME, MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_VOLUME, 621 Mpi2EventDataIrVolume_t, MPI2_POINTER pMpi2EventDataIrVolume_t; 622 623 /* Integrated RAID Volume Event data ReasonCode values */ 624 #define MPI2_EVENT_IR_VOLUME_RC_SETTINGS_CHANGED (0x01) 625 #define MPI2_EVENT_IR_VOLUME_RC_STATUS_FLAGS_CHANGED (0x02) 626 #define MPI2_EVENT_IR_VOLUME_RC_STATE_CHANGED (0x03) 627 628 /* Integrated RAID Physical Disk Event data */ 629 630 typedef struct _MPI2_EVENT_DATA_IR_PHYSICAL_DISK 631 { 632 U16 Reserved1; /* 0x00 */ 633 U8 ReasonCode; /* 0x02 */ 634 U8 PhysDiskNum; /* 0x03 */ 635 U16 PhysDiskDevHandle; /* 0x04 */ 636 U16 Reserved2; /* 0x06 */ 637 U16 Slot; /* 0x08 */ 638 U16 EnclosureHandle; /* 0x0A */ 639 U32 NewValue; /* 0x0C */ 640 U32 PreviousValue; /* 0x10 */ 641 } MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 642 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_PHYSICAL_DISK, 643 Mpi2EventDataIrPhysicalDisk_t, MPI2_POINTER pMpi2EventDataIrPhysicalDisk_t; 644 645 /* Integrated RAID Physical Disk Event data ReasonCode values */ 646 #define MPI2_EVENT_IR_PHYSDISK_RC_SETTINGS_CHANGED (0x01) 647 #define MPI2_EVENT_IR_PHYSDISK_RC_STATUS_FLAGS_CHANGED (0x02) 648 #define MPI2_EVENT_IR_PHYSDISK_RC_STATE_CHANGED (0x03) 649 650 /* Integrated RAID Configuration Change List Event data */ 651 652 /* 653 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 654 * one and check NumElements at runtime. 655 */ 656 #ifndef MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT 657 #define MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT (1) 658 #endif 659 660 typedef struct _MPI2_EVENT_IR_CONFIG_ELEMENT 661 { 662 U16 ElementFlags; /* 0x00 */ 663 U16 VolDevHandle; /* 0x02 */ 664 U8 ReasonCode; /* 0x04 */ 665 U8 PhysDiskNum; /* 0x05 */ 666 U16 PhysDiskDevHandle; /* 0x06 */ 667 } MPI2_EVENT_IR_CONFIG_ELEMENT, MPI2_POINTER PTR_MPI2_EVENT_IR_CONFIG_ELEMENT, 668 Mpi2EventIrConfigElement_t, MPI2_POINTER pMpi2EventIrConfigElement_t; 669 670 /* IR Configuration Change List Event data ElementFlags values */ 671 #define MPI2_EVENT_IR_CHANGE_EFLAGS_ELEMENT_TYPE_MASK (0x000F) 672 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLUME_ELEMENT (0x0000) 673 #define MPI2_EVENT_IR_CHANGE_EFLAGS_VOLPHYSDISK_ELEMENT (0x0001) 674 #define MPI2_EVENT_IR_CHANGE_EFLAGS_HOTSPARE_ELEMENT (0x0002) 675 676 /* IR Configuration Change List Event data ReasonCode values */ 677 #define MPI2_EVENT_IR_CHANGE_RC_ADDED (0x01) 678 #define MPI2_EVENT_IR_CHANGE_RC_REMOVED (0x02) 679 #define MPI2_EVENT_IR_CHANGE_RC_NO_CHANGE (0x03) 680 #define MPI2_EVENT_IR_CHANGE_RC_HIDE (0x04) 681 #define MPI2_EVENT_IR_CHANGE_RC_UNHIDE (0x05) 682 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_CREATED (0x06) 683 #define MPI2_EVENT_IR_CHANGE_RC_VOLUME_DELETED (0x07) 684 #define MPI2_EVENT_IR_CHANGE_RC_PD_CREATED (0x08) 685 #define MPI2_EVENT_IR_CHANGE_RC_PD_DELETED (0x09) 686 687 typedef struct _MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST 688 { 689 U8 NumElements; /* 0x00 */ 690 U8 Reserved1; /* 0x01 */ 691 U8 Reserved2; /* 0x02 */ 692 U8 ConfigNum; /* 0x03 */ 693 U32 Flags; /* 0x04 */ 694 MPI2_EVENT_IR_CONFIG_ELEMENT ConfigElement[MPI2_EVENT_IR_CONFIG_ELEMENT_COUNT]; /* 0x08 */ 695 } MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 696 MPI2_POINTER PTR_MPI2_EVENT_DATA_IR_CONFIG_CHANGE_LIST, 697 Mpi2EventDataIrConfigChangeList_t, 698 MPI2_POINTER pMpi2EventDataIrConfigChangeList_t; 699 700 /* IR Configuration Change List Event data Flags values */ 701 #define MPI2_EVENT_IR_CHANGE_FLAGS_FOREIGN_CONFIG (0x00000001) 702 703 /* SAS Discovery Event data */ 704 705 typedef struct _MPI2_EVENT_DATA_SAS_DISCOVERY 706 { 707 U8 Flags; /* 0x00 */ 708 U8 ReasonCode; /* 0x01 */ 709 U8 PhysicalPort; /* 0x02 */ 710 U8 Reserved1; /* 0x03 */ 711 U32 DiscoveryStatus; /* 0x04 */ 712 } MPI2_EVENT_DATA_SAS_DISCOVERY, 713 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_DISCOVERY, 714 Mpi2EventDataSasDiscovery_t, MPI2_POINTER pMpi2EventDataSasDiscovery_t; 715 716 /* SAS Discovery Event data Flags values */ 717 #define MPI2_EVENT_SAS_DISC_DEVICE_CHANGE (0x02) 718 #define MPI2_EVENT_SAS_DISC_IN_PROGRESS (0x01) 719 720 /* SAS Discovery Event data ReasonCode values */ 721 #define MPI2_EVENT_SAS_DISC_RC_STARTED (0x01) 722 #define MPI2_EVENT_SAS_DISC_RC_COMPLETED (0x02) 723 724 /* SAS Discovery Event data DiscoveryStatus values */ 725 #define MPI2_EVENT_SAS_DISC_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 726 #define MPI2_EVENT_SAS_DISC_DS_MAX_EXPANDERS_EXCEED (0x40000000) 727 #define MPI2_EVENT_SAS_DISC_DS_MAX_DEVICES_EXCEED (0x20000000) 728 #define MPI2_EVENT_SAS_DISC_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 729 #define MPI2_EVENT_SAS_DISC_DS_DOWNSTREAM_INITIATOR (0x08000000) 730 #define MPI2_EVENT_SAS_DISC_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 731 #define MPI2_EVENT_SAS_DISC_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 732 #define MPI2_EVENT_SAS_DISC_DS_MULTI_PORT_DOMAIN (0x00002000) 733 #define MPI2_EVENT_SAS_DISC_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 734 #define MPI2_EVENT_SAS_DISC_DS_UNSUPPORTED_DEVICE (0x00000800) 735 #define MPI2_EVENT_SAS_DISC_DS_TABLE_LINK (0x00000400) 736 #define MPI2_EVENT_SAS_DISC_DS_SUBTRACTIVE_LINK (0x00000200) 737 #define MPI2_EVENT_SAS_DISC_DS_SMP_CRC_ERROR (0x00000100) 738 #define MPI2_EVENT_SAS_DISC_DS_SMP_FUNCTION_FAILED (0x00000080) 739 #define MPI2_EVENT_SAS_DISC_DS_INDEX_NOT_EXIST (0x00000040) 740 #define MPI2_EVENT_SAS_DISC_DS_OUT_ROUTE_ENTRIES (0x00000020) 741 #define MPI2_EVENT_SAS_DISC_DS_SMP_TIMEOUT (0x00000010) 742 #define MPI2_EVENT_SAS_DISC_DS_MULTIPLE_PORTS (0x00000004) 743 #define MPI2_EVENT_SAS_DISC_DS_UNADDRESSABLE_DEVICE (0x00000002) 744 #define MPI2_EVENT_SAS_DISC_DS_LOOP_DETECTED (0x00000001) 745 746 /* SAS Broadcast Primitive Event data */ 747 748 typedef struct _MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE 749 { 750 U8 PhyNum; /* 0x00 */ 751 U8 Port; /* 0x01 */ 752 U8 PortWidth; /* 0x02 */ 753 U8 Primitive; /* 0x03 */ 754 } MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 755 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_BROADCAST_PRIMITIVE, 756 Mpi2EventDataSasBroadcastPrimitive_t, 757 MPI2_POINTER pMpi2EventDataSasBroadcastPrimitive_t; 758 759 /* defines for the Primitive field */ 760 #define MPI2_EVENT_PRIMITIVE_CHANGE (0x01) 761 #define MPI2_EVENT_PRIMITIVE_SES (0x02) 762 #define MPI2_EVENT_PRIMITIVE_EXPANDER (0x03) 763 #define MPI2_EVENT_PRIMITIVE_ASYNCHRONOUS_EVENT (0x04) 764 #define MPI2_EVENT_PRIMITIVE_RESERVED3 (0x05) 765 #define MPI2_EVENT_PRIMITIVE_RESERVED4 (0x06) 766 #define MPI2_EVENT_PRIMITIVE_CHANGE0_RESERVED (0x07) 767 #define MPI2_EVENT_PRIMITIVE_CHANGE1_RESERVED (0x08) 768 769 /* SAS Initiator Device Status Change Event data */ 770 771 typedef struct _MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE 772 { 773 U8 ReasonCode; /* 0x00 */ 774 U8 PhysicalPort; /* 0x01 */ 775 U16 DevHandle; /* 0x02 */ 776 U64 SASAddress; /* 0x04 */ 777 } MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 778 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_DEV_STATUS_CHANGE, 779 Mpi2EventDataSasInitDevStatusChange_t, 780 MPI2_POINTER pMpi2EventDataSasInitDevStatusChange_t; 781 782 /* SAS Initiator Device Status Change event ReasonCode values */ 783 #define MPI2_EVENT_SAS_INIT_RC_ADDED (0x01) 784 #define MPI2_EVENT_SAS_INIT_RC_NOT_RESPONDING (0x02) 785 786 /* SAS Initiator Device Table Overflow Event data */ 787 788 typedef struct _MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW 789 { 790 U16 MaxInit; /* 0x00 */ 791 U16 CurrentInit; /* 0x02 */ 792 U64 SASAddress; /* 0x04 */ 793 } MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 794 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_INIT_TABLE_OVERFLOW, 795 Mpi2EventDataSasInitTableOverflow_t, 796 MPI2_POINTER pMpi2EventDataSasInitTableOverflow_t; 797 798 /* SAS Topology Change List Event data */ 799 800 /* 801 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 802 * one and check NumEntries at runtime. 803 */ 804 #ifndef MPI2_EVENT_SAS_TOPO_PHY_COUNT 805 #define MPI2_EVENT_SAS_TOPO_PHY_COUNT (1) 806 #endif 807 808 typedef struct _MPI2_EVENT_SAS_TOPO_PHY_ENTRY 809 { 810 U16 AttachedDevHandle; /* 0x00 */ 811 U8 LinkRate; /* 0x02 */ 812 U8 PhyStatus; /* 0x03 */ 813 } MPI2_EVENT_SAS_TOPO_PHY_ENTRY, MPI2_POINTER PTR_MPI2_EVENT_SAS_TOPO_PHY_ENTRY, 814 Mpi2EventSasTopoPhyEntry_t, MPI2_POINTER pMpi2EventSasTopoPhyEntry_t; 815 816 typedef struct _MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST 817 { 818 U16 EnclosureHandle; /* 0x00 */ 819 U16 ExpanderDevHandle; /* 0x02 */ 820 U8 NumPhys; /* 0x04 */ 821 U8 Reserved1; /* 0x05 */ 822 U16 Reserved2; /* 0x06 */ 823 U8 NumEntries; /* 0x08 */ 824 U8 StartPhyNum; /* 0x09 */ 825 U8 ExpStatus; /* 0x0A */ 826 U8 PhysicalPort; /* 0x0B */ 827 MPI2_EVENT_SAS_TOPO_PHY_ENTRY PHY[MPI2_EVENT_SAS_TOPO_PHY_COUNT]; /* 0x0C*/ 828 } MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 829 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_TOPOLOGY_CHANGE_LIST, 830 Mpi2EventDataSasTopologyChangeList_t, 831 MPI2_POINTER pMpi2EventDataSasTopologyChangeList_t; 832 833 /* values for the ExpStatus field */ 834 #define MPI2_EVENT_SAS_TOPO_ES_NO_EXPANDER (0x00) 835 #define MPI2_EVENT_SAS_TOPO_ES_ADDED (0x01) 836 #define MPI2_EVENT_SAS_TOPO_ES_NOT_RESPONDING (0x02) 837 #define MPI2_EVENT_SAS_TOPO_ES_RESPONDING (0x03) 838 #define MPI2_EVENT_SAS_TOPO_ES_DELAY_NOT_RESPONDING (0x04) 839 840 /* defines for the LinkRate field */ 841 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_MASK (0xF0) 842 #define MPI2_EVENT_SAS_TOPO_LR_CURRENT_SHIFT (4) 843 #define MPI2_EVENT_SAS_TOPO_LR_PREV_MASK (0x0F) 844 #define MPI2_EVENT_SAS_TOPO_LR_PREV_SHIFT (0) 845 846 #define MPI2_EVENT_SAS_TOPO_LR_UNKNOWN_LINK_RATE (0x00) 847 #define MPI2_EVENT_SAS_TOPO_LR_PHY_DISABLED (0x01) 848 #define MPI2_EVENT_SAS_TOPO_LR_NEGOTIATION_FAILED (0x02) 849 #define MPI2_EVENT_SAS_TOPO_LR_SATA_OOB_COMPLETE (0x03) 850 #define MPI2_EVENT_SAS_TOPO_LR_PORT_SELECTOR (0x04) 851 #define MPI2_EVENT_SAS_TOPO_LR_SMP_RESET_IN_PROGRESS (0x05) 852 #define MPI2_EVENT_SAS_TOPO_LR_UNSUPPORTED_PHY (0x06) 853 #define MPI2_EVENT_SAS_TOPO_LR_RATE_1_5 (0x08) 854 #define MPI2_EVENT_SAS_TOPO_LR_RATE_3_0 (0x09) 855 #define MPI2_EVENT_SAS_TOPO_LR_RATE_6_0 (0x0A) 856 857 /* values for the PhyStatus field */ 858 #define MPI2_EVENT_SAS_TOPO_PHYSTATUS_VACANT (0x80) 859 #define MPI2_EVENT_SAS_TOPO_PS_MULTIPLEX_CHANGE (0x10) 860 /* values for the PhyStatus ReasonCode sub-field */ 861 #define MPI2_EVENT_SAS_TOPO_RC_MASK (0x0F) 862 #define MPI2_EVENT_SAS_TOPO_RC_TARG_ADDED (0x01) 863 #define MPI2_EVENT_SAS_TOPO_RC_TARG_NOT_RESPONDING (0x02) 864 #define MPI2_EVENT_SAS_TOPO_RC_PHY_CHANGED (0x03) 865 #define MPI2_EVENT_SAS_TOPO_RC_NO_CHANGE (0x04) 866 #define MPI2_EVENT_SAS_TOPO_RC_DELAY_NOT_RESPONDING (0x05) 867 868 /* SAS Enclosure Device Status Change Event data */ 869 870 typedef struct _MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE 871 { 872 U16 EnclosureHandle; /* 0x00 */ 873 U8 ReasonCode; /* 0x02 */ 874 U8 PhysicalPort; /* 0x03 */ 875 U64 EnclosureLogicalID; /* 0x04 */ 876 U16 NumSlots; /* 0x0C */ 877 U16 StartSlot; /* 0x0E */ 878 U32 PhyBits; /* 0x10 */ 879 } MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 880 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_ENCL_DEV_STATUS_CHANGE, 881 Mpi2EventDataSasEnclDevStatusChange_t, 882 MPI2_POINTER pMpi2EventDataSasEnclDevStatusChange_t; 883 884 /* SAS Enclosure Device Status Change event ReasonCode values */ 885 #define MPI2_EVENT_SAS_ENCL_RC_ADDED (0x01) 886 #define MPI2_EVENT_SAS_ENCL_RC_NOT_RESPONDING (0x02) 887 888 /* SAS PHY Counter Event data */ 889 890 typedef struct _MPI2_EVENT_DATA_SAS_PHY_COUNTER 891 { 892 U64 TimeStamp; /* 0x00 */ 893 U32 Reserved1; /* 0x08 */ 894 U8 PhyEventCode; /* 0x0C */ 895 U8 PhyNum; /* 0x0D */ 896 U16 Reserved2; /* 0x0E */ 897 U32 PhyEventInfo; /* 0x10 */ 898 U8 CounterType; /* 0x14 */ 899 U8 ThresholdWindow; /* 0x15 */ 900 U8 TimeUnits; /* 0x16 */ 901 U8 Reserved3; /* 0x17 */ 902 U32 EventThreshold; /* 0x18 */ 903 U16 ThresholdFlags; /* 0x1C */ 904 U16 Reserved4; /* 0x1E */ 905 } MPI2_EVENT_DATA_SAS_PHY_COUNTER, 906 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_PHY_COUNTER, 907 Mpi2EventDataSasPhyCounter_t, MPI2_POINTER pMpi2EventDataSasPhyCounter_t; 908 909 /* use MPI2_SASPHY3_EVENT_CODE_ values from mpi2_cnfg.h for the PhyEventCode field */ 910 911 /* use MPI2_SASPHY3_COUNTER_TYPE_ values from mpi2_cnfg.h for the CounterType field */ 912 913 /* use MPI2_SASPHY3_TIME_UNITS_ values from mpi2_cnfg.h for the TimeUnits field */ 914 915 /* use MPI2_SASPHY3_TFLAGS_ values from mpi2_cnfg.h for the ThresholdFlags field */ 916 917 /* SAS Quiesce Event data */ 918 919 typedef struct _MPI2_EVENT_DATA_SAS_QUIESCE 920 { 921 U8 ReasonCode; /* 0x00 */ 922 U8 Reserved1; /* 0x01 */ 923 U16 Reserved2; /* 0x02 */ 924 U32 Reserved3; /* 0x04 */ 925 } MPI2_EVENT_DATA_SAS_QUIESCE, 926 MPI2_POINTER PTR_MPI2_EVENT_DATA_SAS_QUIESCE, 927 Mpi2EventDataSasQuiesce_t, MPI2_POINTER pMpi2EventDataSasQuiesce_t; 928 929 /* SAS Quiesce Event data ReasonCode values */ 930 #define MPI2_EVENT_SAS_QUIESCE_RC_STARTED (0x01) 931 #define MPI2_EVENT_SAS_QUIESCE_RC_COMPLETED (0x02) 932 933 /* Host Based Discovery Phy Event data */ 934 935 typedef struct _MPI2_EVENT_HBD_PHY_SAS 936 { 937 U8 Flags; /* 0x00 */ 938 U8 NegotiatedLinkRate; /* 0x01 */ 939 U8 PhyNum; /* 0x02 */ 940 U8 PhysicalPort; /* 0x03 */ 941 U32 Reserved1; /* 0x04 */ 942 U8 InitialFrame[28]; /* 0x08 */ 943 } MPI2_EVENT_HBD_PHY_SAS, MPI2_POINTER PTR_MPI2_EVENT_HBD_PHY_SAS, 944 Mpi2EventHbdPhySas_t, MPI2_POINTER pMpi2EventHbdPhySas_t; 945 946 /* values for the Flags field */ 947 #define MPI2_EVENT_HBD_SAS_FLAGS_FRAME_VALID (0x02) 948 #define MPI2_EVENT_HBD_SAS_FLAGS_SATA_FRAME (0x01) 949 950 /* use MPI2_SAS_NEG_LINK_RATE_ defines from mpi2_cnfg.h for the NegotiatedLinkRate field */ 951 952 typedef union _MPI2_EVENT_HBD_DESCRIPTOR 953 { 954 MPI2_EVENT_HBD_PHY_SAS Sas; 955 } MPI2_EVENT_HBD_DESCRIPTOR, MPI2_POINTER PTR_MPI2_EVENT_HBD_DESCRIPTOR, 956 Mpi2EventHbdDescriptor_t, MPI2_POINTER pMpi2EventHbdDescriptor_t; 957 958 typedef struct _MPI2_EVENT_DATA_HBD_PHY 959 { 960 U8 DescriptorType; /* 0x00 */ 961 U8 Reserved1; /* 0x01 */ 962 U16 Reserved2; /* 0x02 */ 963 U32 Reserved3; /* 0x04 */ 964 MPI2_EVENT_HBD_DESCRIPTOR Descriptor; /* 0x08 */ 965 } MPI2_EVENT_DATA_HBD_PHY, MPI2_POINTER PTR_MPI2_EVENT_DATA_HBD_PHY, 966 Mpi2EventDataHbdPhy_t, MPI2_POINTER pMpi2EventDataMpi2EventDataHbdPhy_t; 967 968 /* values for the DescriptorType field */ 969 #define MPI2_EVENT_HBD_DT_SAS (0x01) 970 971 /**************************************************************************** 972 * EventAck message 973 ****************************************************************************/ 974 975 /* EventAck Request message */ 976 typedef struct _MPI2_EVENT_ACK_REQUEST 977 { 978 U16 Reserved1; /* 0x00 */ 979 U8 ChainOffset; /* 0x02 */ 980 U8 Function; /* 0x03 */ 981 U16 Reserved2; /* 0x04 */ 982 U8 Reserved3; /* 0x06 */ 983 U8 MsgFlags; /* 0x07 */ 984 U8 VP_ID; /* 0x08 */ 985 U8 VF_ID; /* 0x09 */ 986 U16 Reserved4; /* 0x0A */ 987 U16 Event; /* 0x0C */ 988 U16 Reserved5; /* 0x0E */ 989 U32 EventContext; /* 0x10 */ 990 } MPI2_EVENT_ACK_REQUEST, MPI2_POINTER PTR_MPI2_EVENT_ACK_REQUEST, 991 Mpi2EventAckRequest_t, MPI2_POINTER pMpi2EventAckRequest_t; 992 993 /* EventAck Reply message */ 994 typedef struct _MPI2_EVENT_ACK_REPLY 995 { 996 U16 Reserved1; /* 0x00 */ 997 U8 MsgLength; /* 0x02 */ 998 U8 Function; /* 0x03 */ 999 U16 Reserved2; /* 0x04 */ 1000 U8 Reserved3; /* 0x06 */ 1001 U8 MsgFlags; /* 0x07 */ 1002 U8 VP_ID; /* 0x08 */ 1003 U8 VF_ID; /* 0x09 */ 1004 U16 Reserved4; /* 0x0A */ 1005 U16 Reserved5; /* 0x0C */ 1006 U16 IOCStatus; /* 0x0E */ 1007 U32 IOCLogInfo; /* 0x10 */ 1008 } MPI2_EVENT_ACK_REPLY, MPI2_POINTER PTR_MPI2_EVENT_ACK_REPLY, 1009 Mpi2EventAckReply_t, MPI2_POINTER pMpi2EventAckReply_t; 1010 1011 /**************************************************************************** 1012 * FWDownload message 1013 ****************************************************************************/ 1014 1015 /* FWDownload Request message */ 1016 typedef struct _MPI2_FW_DOWNLOAD_REQUEST 1017 { 1018 U8 ImageType; /* 0x00 */ 1019 U8 Reserved1; /* 0x01 */ 1020 U8 ChainOffset; /* 0x02 */ 1021 U8 Function; /* 0x03 */ 1022 U16 Reserved2; /* 0x04 */ 1023 U8 Reserved3; /* 0x06 */ 1024 U8 MsgFlags; /* 0x07 */ 1025 U8 VP_ID; /* 0x08 */ 1026 U8 VF_ID; /* 0x09 */ 1027 U16 Reserved4; /* 0x0A */ 1028 U32 TotalImageSize; /* 0x0C */ 1029 U32 Reserved5; /* 0x10 */ 1030 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1031 } MPI2_FW_DOWNLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REQUEST, 1032 Mpi2FWDownloadRequest, MPI2_POINTER pMpi2FWDownloadRequest; 1033 1034 #define MPI2_FW_DOWNLOAD_MSGFLGS_LAST_SEGMENT (0x01) 1035 1036 #define MPI2_FW_DOWNLOAD_ITYPE_FW (0x01) 1037 #define MPI2_FW_DOWNLOAD_ITYPE_BIOS (0x02) 1038 #define MPI2_FW_DOWNLOAD_ITYPE_MANUFACTURING (0x06) 1039 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_1 (0x07) 1040 #define MPI2_FW_DOWNLOAD_ITYPE_CONFIG_2 (0x08) 1041 #define MPI2_FW_DOWNLOAD_ITYPE_MEGARAID (0x09) 1042 #define MPI2_FW_DOWNLOAD_ITYPE_COMPLETE (0x0A) 1043 #define MPI2_FW_DOWNLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1044 #define MPI2_FW_DOWNLOAD_ITYPE_MIN_PRODUCT_SPECIFIC (0xF0) 1045 1046 /* FWDownload TransactionContext Element */ 1047 typedef struct _MPI2_FW_DOWNLOAD_TCSGE 1048 { 1049 U8 Reserved1; /* 0x00 */ 1050 U8 ContextSize; /* 0x01 */ 1051 U8 DetailsLength; /* 0x02 */ 1052 U8 Flags; /* 0x03 */ 1053 U32 Reserved2; /* 0x04 */ 1054 U32 ImageOffset; /* 0x08 */ 1055 U32 ImageSize; /* 0x0C */ 1056 } MPI2_FW_DOWNLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_TCSGE, 1057 Mpi2FWDownloadTCSGE_t, MPI2_POINTER pMpi2FWDownloadTCSGE_t; 1058 1059 /* FWDownload Reply message */ 1060 typedef struct _MPI2_FW_DOWNLOAD_REPLY 1061 { 1062 U8 ImageType; /* 0x00 */ 1063 U8 Reserved1; /* 0x01 */ 1064 U8 MsgLength; /* 0x02 */ 1065 U8 Function; /* 0x03 */ 1066 U16 Reserved2; /* 0x04 */ 1067 U8 Reserved3; /* 0x06 */ 1068 U8 MsgFlags; /* 0x07 */ 1069 U8 VP_ID; /* 0x08 */ 1070 U8 VF_ID; /* 0x09 */ 1071 U16 Reserved4; /* 0x0A */ 1072 U16 Reserved5; /* 0x0C */ 1073 U16 IOCStatus; /* 0x0E */ 1074 U32 IOCLogInfo; /* 0x10 */ 1075 } MPI2_FW_DOWNLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_DOWNLOAD_REPLY, 1076 Mpi2FWDownloadReply_t, MPI2_POINTER pMpi2FWDownloadReply_t; 1077 1078 /**************************************************************************** 1079 * FWUpload message 1080 ****************************************************************************/ 1081 1082 /* FWUpload Request message */ 1083 typedef struct _MPI2_FW_UPLOAD_REQUEST 1084 { 1085 U8 ImageType; /* 0x00 */ 1086 U8 Reserved1; /* 0x01 */ 1087 U8 ChainOffset; /* 0x02 */ 1088 U8 Function; /* 0x03 */ 1089 U16 Reserved2; /* 0x04 */ 1090 U8 Reserved3; /* 0x06 */ 1091 U8 MsgFlags; /* 0x07 */ 1092 U8 VP_ID; /* 0x08 */ 1093 U8 VF_ID; /* 0x09 */ 1094 U16 Reserved4; /* 0x0A */ 1095 U32 Reserved5; /* 0x0C */ 1096 U32 Reserved6; /* 0x10 */ 1097 MPI2_MPI_SGE_UNION SGL; /* 0x14 */ 1098 } MPI2_FW_UPLOAD_REQUEST, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REQUEST, 1099 Mpi2FWUploadRequest_t, MPI2_POINTER pMpi2FWUploadRequest_t; 1100 1101 #define MPI2_FW_UPLOAD_ITYPE_FW_CURRENT (0x00) 1102 #define MPI2_FW_UPLOAD_ITYPE_FW_FLASH (0x01) 1103 #define MPI2_FW_UPLOAD_ITYPE_BIOS_FLASH (0x02) 1104 #define MPI2_FW_UPLOAD_ITYPE_FW_BACKUP (0x05) 1105 #define MPI2_FW_UPLOAD_ITYPE_MANUFACTURING (0x06) 1106 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_1 (0x07) 1107 #define MPI2_FW_UPLOAD_ITYPE_CONFIG_2 (0x08) 1108 #define MPI2_FW_UPLOAD_ITYPE_MEGARAID (0x09) 1109 #define MPI2_FW_UPLOAD_ITYPE_COMPLETE (0x0A) 1110 #define MPI2_FW_UPLOAD_ITYPE_COMMON_BOOT_BLOCK (0x0B) 1111 1112 typedef struct _MPI2_FW_UPLOAD_TCSGE 1113 { 1114 U8 Reserved1; /* 0x00 */ 1115 U8 ContextSize; /* 0x01 */ 1116 U8 DetailsLength; /* 0x02 */ 1117 U8 Flags; /* 0x03 */ 1118 U32 Reserved2; /* 0x04 */ 1119 U32 ImageOffset; /* 0x08 */ 1120 U32 ImageSize; /* 0x0C */ 1121 } MPI2_FW_UPLOAD_TCSGE, MPI2_POINTER PTR_MPI2_FW_UPLOAD_TCSGE, 1122 Mpi2FWUploadTCSGE_t, MPI2_POINTER pMpi2FWUploadTCSGE_t; 1123 1124 /* FWUpload Reply message */ 1125 typedef struct _MPI2_FW_UPLOAD_REPLY 1126 { 1127 U8 ImageType; /* 0x00 */ 1128 U8 Reserved1; /* 0x01 */ 1129 U8 MsgLength; /* 0x02 */ 1130 U8 Function; /* 0x03 */ 1131 U16 Reserved2; /* 0x04 */ 1132 U8 Reserved3; /* 0x06 */ 1133 U8 MsgFlags; /* 0x07 */ 1134 U8 VP_ID; /* 0x08 */ 1135 U8 VF_ID; /* 0x09 */ 1136 U16 Reserved4; /* 0x0A */ 1137 U16 Reserved5; /* 0x0C */ 1138 U16 IOCStatus; /* 0x0E */ 1139 U32 IOCLogInfo; /* 0x10 */ 1140 U32 ActualImageSize; /* 0x14 */ 1141 } MPI2_FW_UPLOAD_REPLY, MPI2_POINTER PTR_MPI2_FW_UPLOAD_REPLY, 1142 Mpi2FWUploadReply_t, MPI2_POINTER pMPi2FWUploadReply_t; 1143 1144 /* FW Image Header */ 1145 typedef struct _MPI2_FW_IMAGE_HEADER 1146 { 1147 U32 Signature; /* 0x00 */ 1148 U32 Signature0; /* 0x04 */ 1149 U32 Signature1; /* 0x08 */ 1150 U32 Signature2; /* 0x0C */ 1151 MPI2_VERSION_UNION MPIVersion; /* 0x10 */ 1152 MPI2_VERSION_UNION FWVersion; /* 0x14 */ 1153 MPI2_VERSION_UNION NVDATAVersion; /* 0x18 */ 1154 MPI2_VERSION_UNION PackageVersion; /* 0x1C */ 1155 U16 VendorID; /* 0x20 */ 1156 U16 ProductID; /* 0x22 */ 1157 U16 ProtocolFlags; /* 0x24 */ 1158 U16 Reserved26; /* 0x26 */ 1159 U32 IOCCapabilities; /* 0x28 */ 1160 U32 ImageSize; /* 0x2C */ 1161 U32 NextImageHeaderOffset; /* 0x30 */ 1162 U32 Checksum; /* 0x34 */ 1163 U32 Reserved38; /* 0x38 */ 1164 U32 Reserved3C; /* 0x3C */ 1165 U32 Reserved40; /* 0x40 */ 1166 U32 Reserved44; /* 0x44 */ 1167 U32 Reserved48; /* 0x48 */ 1168 U32 Reserved4C; /* 0x4C */ 1169 U32 Reserved50; /* 0x50 */ 1170 U32 Reserved54; /* 0x54 */ 1171 U32 Reserved58; /* 0x58 */ 1172 U32 Reserved5C; /* 0x5C */ 1173 U32 Reserved60; /* 0x60 */ 1174 U32 FirmwareVersionNameWhat; /* 0x64 */ 1175 U8 FirmwareVersionName[32]; /* 0x68 */ 1176 U32 VendorNameWhat; /* 0x88 */ 1177 U8 VendorName[32]; /* 0x8C */ 1178 U32 PackageNameWhat; /* 0x88 */ 1179 U8 PackageName[32]; /* 0x8C */ 1180 U32 ReservedD0; /* 0xD0 */ 1181 U32 ReservedD4; /* 0xD4 */ 1182 U32 ReservedD8; /* 0xD8 */ 1183 U32 ReservedDC; /* 0xDC */ 1184 U32 ReservedE0; /* 0xE0 */ 1185 U32 ReservedE4; /* 0xE4 */ 1186 U32 ReservedE8; /* 0xE8 */ 1187 U32 ReservedEC; /* 0xEC */ 1188 U32 ReservedF0; /* 0xF0 */ 1189 U32 ReservedF4; /* 0xF4 */ 1190 U32 ReservedF8; /* 0xF8 */ 1191 U32 ReservedFC; /* 0xFC */ 1192 } MPI2_FW_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_FW_IMAGE_HEADER, 1193 Mpi2FWImageHeader_t, MPI2_POINTER pMpi2FWImageHeader_t; 1194 1195 /* Signature field */ 1196 #define MPI2_FW_HEADER_SIGNATURE_OFFSET (0x00) 1197 #define MPI2_FW_HEADER_SIGNATURE_MASK (0xFF000000) 1198 #define MPI2_FW_HEADER_SIGNATURE (0xEA000000) 1199 1200 /* Signature0 field */ 1201 #define MPI2_FW_HEADER_SIGNATURE0_OFFSET (0x04) 1202 #define MPI2_FW_HEADER_SIGNATURE0 (0x5AFAA55A) 1203 1204 /* Signature1 field */ 1205 #define MPI2_FW_HEADER_SIGNATURE1_OFFSET (0x08) 1206 #define MPI2_FW_HEADER_SIGNATURE1 (0xA55AFAA5) 1207 1208 /* Signature2 field */ 1209 #define MPI2_FW_HEADER_SIGNATURE2_OFFSET (0x0C) 1210 #define MPI2_FW_HEADER_SIGNATURE2 (0x5AA55AFA) 1211 1212 /* defines for using the ProductID field */ 1213 #define MPI2_FW_HEADER_PID_TYPE_MASK (0xF000) 1214 #define MPI2_FW_HEADER_PID_TYPE_SAS (0x2000) 1215 1216 #define MPI2_FW_HEADER_PID_PROD_MASK (0x0F00) 1217 #define MPI2_FW_HEADER_PID_PROD_A (0x0000) 1218 #define MPI2_FW_HEADER_PID_PROD_TARGET_INITIATOR_SCSI (0x0200) 1219 #define MPI2_FW_HEADER_PID_PROD_IR_SCSI (0x0700) 1220 1221 #define MPI2_FW_HEADER_PID_FAMILY_MASK (0x00FF) 1222 /* SAS */ 1223 #define MPI2_FW_HEADER_PID_FAMILY_2108_SAS (0x0013) 1224 #define MPI2_FW_HEADER_PID_FAMILY_2208_SAS (0x0014) 1225 1226 /* use MPI2_IOCFACTS_PROTOCOL_ defines for ProtocolFlags field */ 1227 1228 /* use MPI2_IOCFACTS_CAPABILITY_ defines for IOCCapabilities field */ 1229 1230 #define MPI2_FW_HEADER_IMAGESIZE_OFFSET (0x2C) 1231 #define MPI2_FW_HEADER_NEXTIMAGE_OFFSET (0x30) 1232 #define MPI2_FW_HEADER_VERNMHWAT_OFFSET (0x64) 1233 1234 #define MPI2_FW_HEADER_WHAT_SIGNATURE (0x29232840) 1235 1236 #define MPI2_FW_HEADER_SIZE (0x100) 1237 1238 /* Extended Image Header */ 1239 typedef struct _MPI2_EXT_IMAGE_HEADER 1240 1241 { 1242 U8 ImageType; /* 0x00 */ 1243 U8 Reserved1; /* 0x01 */ 1244 U16 Reserved2; /* 0x02 */ 1245 U32 Checksum; /* 0x04 */ 1246 U32 ImageSize; /* 0x08 */ 1247 U32 NextImageHeaderOffset; /* 0x0C */ 1248 U32 PackageVersion; /* 0x10 */ 1249 U32 Reserved3; /* 0x14 */ 1250 U32 Reserved4; /* 0x18 */ 1251 U32 Reserved5; /* 0x1C */ 1252 U8 IdentifyString[32]; /* 0x20 */ 1253 } MPI2_EXT_IMAGE_HEADER, MPI2_POINTER PTR_MPI2_EXT_IMAGE_HEADER, 1254 Mpi2ExtImageHeader_t, MPI2_POINTER pMpi2ExtImageHeader_t; 1255 1256 /* useful offsets */ 1257 #define MPI2_EXT_IMAGE_IMAGETYPE_OFFSET (0x00) 1258 #define MPI2_EXT_IMAGE_IMAGESIZE_OFFSET (0x08) 1259 #define MPI2_EXT_IMAGE_NEXTIMAGE_OFFSET (0x0C) 1260 1261 #define MPI2_EXT_IMAGE_HEADER_SIZE (0x40) 1262 1263 /* defines for the ImageType field */ 1264 #define MPI2_EXT_IMAGE_TYPE_UNSPECIFIED (0x00) 1265 #define MPI2_EXT_IMAGE_TYPE_FW (0x01) 1266 #define MPI2_EXT_IMAGE_TYPE_NVDATA (0x03) 1267 #define MPI2_EXT_IMAGE_TYPE_BOOTLOADER (0x04) 1268 #define MPI2_EXT_IMAGE_TYPE_INITIALIZATION (0x05) 1269 #define MPI2_EXT_IMAGE_TYPE_FLASH_LAYOUT (0x06) 1270 #define MPI2_EXT_IMAGE_TYPE_SUPPORTED_DEVICES (0x07) 1271 #define MPI2_EXT_IMAGE_TYPE_MEGARAID (0x08) 1272 1273 #define MPI2_EXT_IMAGE_TYPE_MAX (MPI2_EXT_IMAGE_TYPE_MEGARAID) 1274 1275 /* FLASH Layout Extended Image Data */ 1276 1277 /* 1278 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1279 * one and check RegionsPerLayout at runtime. 1280 */ 1281 #ifndef MPI2_FLASH_NUMBER_OF_REGIONS 1282 #define MPI2_FLASH_NUMBER_OF_REGIONS (1) 1283 #endif 1284 1285 /* 1286 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1287 * one and check NumberOfLayouts at runtime. 1288 */ 1289 #ifndef MPI2_FLASH_NUMBER_OF_LAYOUTS 1290 #define MPI2_FLASH_NUMBER_OF_LAYOUTS (1) 1291 #endif 1292 1293 typedef struct _MPI2_FLASH_REGION 1294 { 1295 U8 RegionType; /* 0x00 */ 1296 U8 Reserved1; /* 0x01 */ 1297 U16 Reserved2; /* 0x02 */ 1298 U32 RegionOffset; /* 0x04 */ 1299 U32 RegionSize; /* 0x08 */ 1300 U32 Reserved3; /* 0x0C */ 1301 } MPI2_FLASH_REGION, MPI2_POINTER PTR_MPI2_FLASH_REGION, 1302 Mpi2FlashRegion_t, MPI2_POINTER pMpi2FlashRegion_t; 1303 1304 typedef struct _MPI2_FLASH_LAYOUT 1305 { 1306 U32 FlashSize; /* 0x00 */ 1307 U32 Reserved1; /* 0x04 */ 1308 U32 Reserved2; /* 0x08 */ 1309 U32 Reserved3; /* 0x0C */ 1310 MPI2_FLASH_REGION Region[MPI2_FLASH_NUMBER_OF_REGIONS];/* 0x10 */ 1311 } MPI2_FLASH_LAYOUT, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT, 1312 Mpi2FlashLayout_t, MPI2_POINTER pMpi2FlashLayout_t; 1313 1314 typedef struct _MPI2_FLASH_LAYOUT_DATA 1315 { 1316 U8 ImageRevision; /* 0x00 */ 1317 U8 Reserved1; /* 0x01 */ 1318 U8 SizeOfRegion; /* 0x02 */ 1319 U8 Reserved2; /* 0x03 */ 1320 U16 NumberOfLayouts; /* 0x04 */ 1321 U16 RegionsPerLayout; /* 0x06 */ 1322 U16 MinimumSectorAlignment; /* 0x08 */ 1323 U16 Reserved3; /* 0x0A */ 1324 U32 Reserved4; /* 0x0C */ 1325 MPI2_FLASH_LAYOUT Layout[MPI2_FLASH_NUMBER_OF_LAYOUTS];/* 0x10 */ 1326 } MPI2_FLASH_LAYOUT_DATA, MPI2_POINTER PTR_MPI2_FLASH_LAYOUT_DATA, 1327 Mpi2FlashLayoutData_t, MPI2_POINTER pMpi2FlashLayoutData_t; 1328 1329 /* defines for the RegionType field */ 1330 #define MPI2_FLASH_REGION_UNUSED (0x00) 1331 #define MPI2_FLASH_REGION_FIRMWARE (0x01) 1332 #define MPI2_FLASH_REGION_BIOS (0x02) 1333 #define MPI2_FLASH_REGION_NVDATA (0x03) 1334 #define MPI2_FLASH_REGION_FIRMWARE_BACKUP (0x05) 1335 #define MPI2_FLASH_REGION_MFG_INFORMATION (0x06) 1336 #define MPI2_FLASH_REGION_CONFIG_1 (0x07) 1337 #define MPI2_FLASH_REGION_CONFIG_2 (0x08) 1338 #define MPI2_FLASH_REGION_MEGARAID (0x09) 1339 #define MPI2_FLASH_REGION_INIT (0x0A) 1340 1341 /* ImageRevision */ 1342 #define MPI2_FLASH_LAYOUT_IMAGE_REVISION (0x00) 1343 1344 /* Supported Devices Extended Image Data */ 1345 1346 /* 1347 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1348 * one and check NumberOfDevices at runtime. 1349 */ 1350 #ifndef MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES 1351 #define MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES (1) 1352 #endif 1353 1354 typedef struct _MPI2_SUPPORTED_DEVICE 1355 { 1356 U16 DeviceID; /* 0x00 */ 1357 U16 VendorID; /* 0x02 */ 1358 U16 DeviceIDMask; /* 0x04 */ 1359 U16 Reserved1; /* 0x06 */ 1360 U8 LowPCIRev; /* 0x08 */ 1361 U8 HighPCIRev; /* 0x09 */ 1362 U16 Reserved2; /* 0x0A */ 1363 U32 Reserved3; /* 0x0C */ 1364 } MPI2_SUPPORTED_DEVICE, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICE, 1365 Mpi2SupportedDevice_t, MPI2_POINTER pMpi2SupportedDevice_t; 1366 1367 typedef struct _MPI2_SUPPORTED_DEVICES_DATA 1368 { 1369 U8 ImageRevision; /* 0x00 */ 1370 U8 Reserved1; /* 0x01 */ 1371 U8 NumberOfDevices; /* 0x02 */ 1372 U8 Reserved2; /* 0x03 */ 1373 U32 Reserved3; /* 0x04 */ 1374 MPI2_SUPPORTED_DEVICE SupportedDevice[MPI2_SUPPORTED_DEVICES_IMAGE_NUM_DEVICES]; /* 0x08 */ 1375 } MPI2_SUPPORTED_DEVICES_DATA, MPI2_POINTER PTR_MPI2_SUPPORTED_DEVICES_DATA, 1376 Mpi2SupportedDevicesData_t, MPI2_POINTER pMpi2SupportedDevicesData_t; 1377 1378 /* ImageRevision */ 1379 #define MPI2_SUPPORTED_DEVICES_IMAGE_REVISION (0x00) 1380 1381 /* Init Extended Image Data */ 1382 1383 typedef struct _MPI2_INIT_IMAGE_FOOTER 1384 1385 { 1386 U32 BootFlags; /* 0x00 */ 1387 U32 ImageSize; /* 0x04 */ 1388 U32 Signature0; /* 0x08 */ 1389 U32 Signature1; /* 0x0C */ 1390 U32 Signature2; /* 0x10 */ 1391 U32 ResetVector; /* 0x14 */ 1392 } MPI2_INIT_IMAGE_FOOTER, MPI2_POINTER PTR_MPI2_INIT_IMAGE_FOOTER, 1393 Mpi2InitImageFooter_t, MPI2_POINTER pMpi2InitImageFooter_t; 1394 1395 /* defines for the BootFlags field */ 1396 #define MPI2_INIT_IMAGE_BOOTFLAGS_OFFSET (0x00) 1397 1398 /* defines for the ImageSize field */ 1399 #define MPI2_INIT_IMAGE_IMAGESIZE_OFFSET (0x04) 1400 1401 /* defines for the Signature0 field */ 1402 #define MPI2_INIT_IMAGE_SIGNATURE0_OFFSET (0x08) 1403 #define MPI2_INIT_IMAGE_SIGNATURE0 (0x5AA55AEA) 1404 1405 /* defines for the Signature1 field */ 1406 #define MPI2_INIT_IMAGE_SIGNATURE1_OFFSET (0x0C) 1407 #define MPI2_INIT_IMAGE_SIGNATURE1 (0xA55AEAA5) 1408 1409 /* defines for the Signature2 field */ 1410 #define MPI2_INIT_IMAGE_SIGNATURE2_OFFSET (0x10) 1411 #define MPI2_INIT_IMAGE_SIGNATURE2 (0x5AEAA55A) 1412 1413 /* Signature fields as individual bytes */ 1414 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_0 (0xEA) 1415 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_1 (0x5A) 1416 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_2 (0xA5) 1417 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_3 (0x5A) 1418 1419 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_4 (0xA5) 1420 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_5 (0xEA) 1421 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_6 (0x5A) 1422 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_7 (0xA5) 1423 1424 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_8 (0x5A) 1425 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_9 (0xA5) 1426 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_A (0xEA) 1427 #define MPI2_INIT_IMAGE_SIGNATURE_BYTE_B (0x5A) 1428 1429 /* defines for the ResetVector field */ 1430 #define MPI2_INIT_IMAGE_RESETVECTOR_OFFSET (0x14) 1431 1432 /**************************************************************************** 1433 * PowerManagementControl message 1434 ****************************************************************************/ 1435 1436 /* PowerManagementControl Request message */ 1437 typedef struct _MPI2_PWR_MGMT_CONTROL_REQUEST 1438 { 1439 U8 Feature; /* 0x00 */ 1440 U8 Reserved1; /* 0x01 */ 1441 U8 ChainOffset; /* 0x02 */ 1442 U8 Function; /* 0x03 */ 1443 U16 Reserved2; /* 0x04 */ 1444 U8 Reserved3; /* 0x06 */ 1445 U8 MsgFlags; /* 0x07 */ 1446 U8 VP_ID; /* 0x08 */ 1447 U8 VF_ID; /* 0x09 */ 1448 U16 Reserved4; /* 0x0A */ 1449 U8 Parameter1; /* 0x0C */ 1450 U8 Parameter2; /* 0x0D */ 1451 U8 Parameter3; /* 0x0E */ 1452 U8 Parameter4; /* 0x0F */ 1453 U32 Reserved5; /* 0x10 */ 1454 U32 Reserved6; /* 0x14 */ 1455 } MPI2_PWR_MGMT_CONTROL_REQUEST, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REQUEST, 1456 Mpi2PwrMgmtControlRequest_t, MPI2_POINTER pMpi2PwrMgmtControlRequest_t; 1457 1458 /* defines for the Feature field */ 1459 #define MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND (0x01) 1460 #define MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION (0x02) 1461 #define MPI2_PM_CONTROL_FEATURE_PCIE_LINK (0x03) 1462 #define MPI2_PM_CONTROL_FEATURE_IOC_SPEED (0x04) 1463 #define MPI2_PM_CONTROL_FEATURE_MIN_PRODUCT_SPECIFIC (0x80) 1464 #define MPI2_PM_CONTROL_FEATURE_MAX_PRODUCT_SPECIFIC (0xFF) 1465 1466 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_DA_PHY_POWER_COND Feature */ 1467 /* Parameter1 contains a PHY number */ 1468 /* Parameter2 indicates power condition action using these defines */ 1469 #define MPI2_PM_CONTROL_PARAM2_PARTIAL (0x01) 1470 #define MPI2_PM_CONTROL_PARAM2_SLUMBER (0x02) 1471 #define MPI2_PM_CONTROL_PARAM2_EXIT_PWR_MGMT (0x03) 1472 /* Parameter3 and Parameter4 are reserved */ 1473 1474 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PORT_WIDTH_MODULATION Feature */ 1475 /* Parameter1 contains SAS port width modulation group number */ 1476 /* Parameter2 indicates IOC action using these defines */ 1477 #define MPI2_PM_CONTROL_PARAM2_REQUEST_OWNERSHIP (0x01) 1478 #define MPI2_PM_CONTROL_PARAM2_CHANGE_MODULATION (0x02) 1479 #define MPI2_PM_CONTROL_PARAM2_RELINQUISH_OWNERSHIP (0x03) 1480 /* Parameter3 indicates desired modulation level using these defines */ 1481 #define MPI2_PM_CONTROL_PARAM3_25_PERCENT (0x00) 1482 #define MPI2_PM_CONTROL_PARAM3_50_PERCENT (0x01) 1483 #define MPI2_PM_CONTROL_PARAM3_75_PERCENT (0x02) 1484 #define MPI2_PM_CONTROL_PARAM3_100_PERCENT (0x03) 1485 /* Parameter4 is reserved */ 1486 1487 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_PCIE_LINK Feature */ 1488 /* Parameter1 indicates desired PCIe link speed using these defines */ 1489 #define MPI2_PM_CONTROL_PARAM1_PCIE_2_5_GBPS (0x00) 1490 #define MPI2_PM_CONTROL_PARAM1_PCIE_5_0_GBPS (0x01) 1491 #define MPI2_PM_CONTROL_PARAM1_PCIE_8_0_GBPS (0x02) 1492 /* Parameter2 indicates desired PCIe link width using these defines */ 1493 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X1 (0x01) 1494 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X2 (0x02) 1495 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X4 (0x04) 1496 #define MPI2_PM_CONTROL_PARAM2_WIDTH_X8 (0x08) 1497 /* Parameter3 and Parameter4 are reserved */ 1498 1499 /* parameter usage for the MPI2_PM_CONTROL_FEATURE_IOC_SPEED Feature */ 1500 /* Parameter1 indicates desired IOC hardware clock speed using these defines */ 1501 #define MPI2_PM_CONTROL_PARAM1_FULL_IOC_SPEED (0x01) 1502 #define MPI2_PM_CONTROL_PARAM1_HALF_IOC_SPEED (0x02) 1503 #define MPI2_PM_CONTROL_PARAM1_QUARTER_IOC_SPEED (0x04) 1504 #define MPI2_PM_CONTROL_PARAM1_EIGHTH_IOC_SPEED (0x08) 1505 /* Parameter2, Parameter3, and Parameter4 are reserved */ 1506 1507 /* PowerManagementControl Reply message */ 1508 typedef struct _MPI2_PWR_MGMT_CONTROL_REPLY 1509 { 1510 U8 Feature; /* 0x00 */ 1511 U8 Reserved1; /* 0x01 */ 1512 U8 MsgLength; /* 0x02 */ 1513 U8 Function; /* 0x03 */ 1514 U16 Reserved2; /* 0x04 */ 1515 U8 Reserved3; /* 0x06 */ 1516 U8 MsgFlags; /* 0x07 */ 1517 U8 VP_ID; /* 0x08 */ 1518 U8 VF_ID; /* 0x09 */ 1519 U16 Reserved4; /* 0x0A */ 1520 U16 Reserved5; /* 0x0C */ 1521 U16 IOCStatus; /* 0x0E */ 1522 U32 IOCLogInfo; /* 0x10 */ 1523 } MPI2_PWR_MGMT_CONTROL_REPLY, MPI2_POINTER PTR_MPI2_PWR_MGMT_CONTROL_REPLY, 1524 Mpi2PwrMgmtControlReply_t, MPI2_POINTER pMpi2PwrMgmtControlReply_t; 1525 1526 #endif 1527