1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006-2015 LSI Corp. 5 * Copyright (c) 2013-2015 Avago Technologies 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD 30 * 31 * $FreeBSD$ 32 */ 33 34 /* 35 * Copyright (c) 2006-2015 LSI Corporation. 36 * Copyright (c) 2013-2015 Avago Technologies 37 * 38 * 39 * Name: mpi2_cnfg.h 40 * Title: MPI Configuration messages and pages 41 * Creation Date: November 10, 2006 42 * 43 * mpi2_cnfg.h Version: 02.00.17 44 * 45 * Version History 46 * --------------- 47 * 48 * Date Version Description 49 * -------- -------- ------------------------------------------------------ 50 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 51 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 52 * Added Manufacturing Page 11. 53 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 54 * define. 55 * 06-26-07 02.00.02 Adding generic structure for product-specific 56 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 57 * Rework of BIOS Page 2 configuration page. 58 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 59 * forms. 60 * Added configuration pages IOC Page 8 and Driver 61 * Persistent Mapping Page 0. 62 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 63 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 64 * RAID Physical Disk Pages 0 and 1, RAID Configuration 65 * Page 0). 66 * Added new value for AccessStatus field of SAS Device 67 * Page 0 (_SATA_NEEDS_INITIALIZATION). 68 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 69 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 70 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 71 * NVDATA. 72 * Modified IOC Page 7 to use masks and added field for 73 * SASBroadcastPrimitiveMasks. 74 * Added MPI2_CONFIG_PAGE_BIOS_4. 75 * Added MPI2_CONFIG_PAGE_LOG_0. 76 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 77 * Added SAS Device IDs. 78 * Updated Integrated RAID configuration pages including 79 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 80 * Page 0. 81 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 82 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 83 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 84 * Added missing MaxNumRoutedSasAddresses field to 85 * MPI2_CONFIG_PAGE_EXPANDER_0. 86 * Added SAS Port Page 0. 87 * Modified structure layout for 88 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 89 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 90 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 91 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 92 * to 0x000000FF. 93 * Added two new values for the Physical Disk Coercion Size 94 * bits in the Flags field of Manufacturing Page 4. 95 * Added product-specific Manufacturing pages 16 to 31. 96 * Modified Flags bits for controlling write cache on SATA 97 * drives in IO Unit Page 1. 98 * Added new bit to AdditionalControlFlags of SAS IO Unit 99 * Page 1 to control Invalid Topology Correction. 100 * Added additional defines for RAID Volume Page 0 101 * VolumeStatusFlags field. 102 * Modified meaning of RAID Volume Page 0 VolumeSettings 103 * define for auto-configure of hot-swap drives. 104 * Added SupportedPhysDisks field to RAID Volume Page 1 and 105 * added related defines. 106 * Added PhysDiskAttributes field (and related defines) to 107 * RAID Physical Disk Page 0. 108 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 109 * Added three new DiscoveryStatus bits for SAS IO Unit 110 * Page 0 and SAS Expander Page 0. 111 * Removed multiplexing information from SAS IO Unit pages. 112 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 113 * Removed Zone Address Resolved bit from PhyInfo and from 114 * Expander Page 0 Flags field. 115 * Added two new AccessStatus values to SAS Device Page 0 116 * for indicating routing problems. Added 3 reserved words 117 * to this page. 118 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 119 * Inserted missing reserved field into structure for IOC 120 * Page 6. 121 * Added more pending task bits to RAID Volume Page 0 122 * VolumeStatusFlags defines. 123 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 124 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 125 * and SAS Expander Page 0 to flag a downstream initiator 126 * when in simplified routing mode. 127 * Removed SATA Init Failure defines for DiscoveryStatus 128 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 129 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 130 * Added PortGroups, DmaGroup, and ControlGroup fields to 131 * SAS Device Page 0. 132 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 133 * Unit Page 6. 134 * Added expander reduced functionality data to SAS 135 * Expander Page 0. 136 * Added SAS PHY Page 2 and SAS PHY Page 3. 137 * 07-30-09 02.00.12 Added IO Unit Page 7. 138 * Added new device ids. 139 * Added SAS IO Unit Page 5. 140 * Added partial and slumber power management capable flags 141 * to SAS Device Page 0 Flags field. 142 * Added PhyInfo defines for power condition. 143 * Added Ethernet configuration pages. 144 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 145 * Added SAS PHY Page 4 structure and defines. 146 * 02-10-10 02.00.14 Modified the comments for the configuration page 147 * structures that contain an array of data. The host 148 * should use the "count" field in the page data (e.g. the 149 * NumPhys field) to determine the number of valid elements 150 * in the array. 151 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 152 * Added PowerManagementCapabilities to IO Unit Page 7. 153 * Added PortWidthModGroup field to 154 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 155 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 156 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 157 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 158 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 159 * define. 160 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 161 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 162 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 163 * defines. 164 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 165 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 166 * the Pinout field. 167 * Added BoardTemperature and BoardTemperatureUnits fields 168 * to MPI2_CONFIG_PAGE_IO_UNIT_7. 169 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 170 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 171 * -------------------------------------------------------------------------- 172 */ 173 174 #ifndef MPI2_CNFG_H 175 #define MPI2_CNFG_H 176 177 /***************************************************************************** 178 * Configuration Page Header and defines 179 *****************************************************************************/ 180 181 /* Config Page Header */ 182 typedef struct _MPI2_CONFIG_PAGE_HEADER 183 { 184 U8 PageVersion; /* 0x00 */ 185 U8 PageLength; /* 0x01 */ 186 U8 PageNumber; /* 0x02 */ 187 U8 PageType; /* 0x03 */ 188 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER, 189 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t; 190 191 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION 192 { 193 MPI2_CONFIG_PAGE_HEADER Struct; 194 U8 Bytes[4]; 195 U16 Word16[2]; 196 U32 Word32; 197 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 198 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion; 199 200 /* Extended Config Page Header */ 201 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER 202 { 203 U8 PageVersion; /* 0x00 */ 204 U8 Reserved1; /* 0x01 */ 205 U8 PageNumber; /* 0x02 */ 206 U8 PageType; /* 0x03 */ 207 U16 ExtPageLength; /* 0x04 */ 208 U8 ExtPageType; /* 0x06 */ 209 U8 Reserved2; /* 0x07 */ 210 } MPI2_CONFIG_EXTENDED_PAGE_HEADER, 211 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 212 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t; 213 214 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION 215 { 216 MPI2_CONFIG_PAGE_HEADER Struct; 217 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 218 U8 Bytes[8]; 219 U16 Word16[4]; 220 U32 Word32[2]; 221 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 222 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion; 223 224 /* PageType field values */ 225 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 226 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 227 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 228 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 229 230 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 231 #define MPI2_CONFIG_PAGETYPE_IOC (0x01) 232 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 233 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 234 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 235 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 236 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 237 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 238 239 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 240 241 /* ExtPageType field values */ 242 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 243 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 244 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 245 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 246 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 247 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 248 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 249 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 250 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 251 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 252 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 253 254 /***************************************************************************** 255 * PageAddress defines 256 *****************************************************************************/ 257 258 /* RAID Volume PageAddress format */ 259 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 260 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 261 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 262 263 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 264 265 /* RAID Physical Disk PageAddress format */ 266 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 267 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 268 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 269 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 270 271 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 272 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 273 274 /* SAS Expander PageAddress format */ 275 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 276 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 277 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 278 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 279 280 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 281 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 282 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 283 284 /* SAS Device PageAddress format */ 285 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 286 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 287 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 288 289 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 290 291 /* SAS PHY PageAddress format */ 292 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 293 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 294 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 295 296 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 297 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 298 299 /* SAS Port PageAddress format */ 300 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 301 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 302 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 303 304 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 305 306 /* SAS Enclosure PageAddress format */ 307 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 308 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 309 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 310 311 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 312 313 /* RAID Configuration PageAddress format */ 314 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 315 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 316 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 317 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 318 319 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 320 321 /* Driver Persistent Mapping PageAddress format */ 322 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 323 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 324 325 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 326 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 327 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 328 329 /* Ethernet PageAddress format */ 330 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 331 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 332 333 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 334 335 /**************************************************************************** 336 * Configuration messages 337 ****************************************************************************/ 338 339 /* Configuration Request Message */ 340 typedef struct _MPI2_CONFIG_REQUEST 341 { 342 U8 Action; /* 0x00 */ 343 U8 SGLFlags; /* 0x01 */ 344 U8 ChainOffset; /* 0x02 */ 345 U8 Function; /* 0x03 */ 346 U16 ExtPageLength; /* 0x04 */ 347 U8 ExtPageType; /* 0x06 */ 348 U8 MsgFlags; /* 0x07 */ 349 U8 VP_ID; /* 0x08 */ 350 U8 VF_ID; /* 0x09 */ 351 U16 Reserved1; /* 0x0A */ 352 U32 Reserved2; /* 0x0C */ 353 U32 Reserved3; /* 0x10 */ 354 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 355 U32 PageAddress; /* 0x18 */ 356 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */ 357 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST, 358 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t; 359 360 /* values for the Action field */ 361 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 362 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 363 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 364 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 365 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 366 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 367 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 368 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 369 370 /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 371 372 /* Config Reply Message */ 373 typedef struct _MPI2_CONFIG_REPLY 374 { 375 U8 Action; /* 0x00 */ 376 U8 SGLFlags; /* 0x01 */ 377 U8 MsgLength; /* 0x02 */ 378 U8 Function; /* 0x03 */ 379 U16 ExtPageLength; /* 0x04 */ 380 U8 ExtPageType; /* 0x06 */ 381 U8 MsgFlags; /* 0x07 */ 382 U8 VP_ID; /* 0x08 */ 383 U8 VF_ID; /* 0x09 */ 384 U16 Reserved1; /* 0x0A */ 385 U16 Reserved2; /* 0x0C */ 386 U16 IOCStatus; /* 0x0E */ 387 U32 IOCLogInfo; /* 0x10 */ 388 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 389 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY, 390 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t; 391 392 /***************************************************************************** 393 * 394 * C o n f i g u r a t i o n P a g e s 395 * 396 *****************************************************************************/ 397 398 /**************************************************************************** 399 * Manufacturing Config pages 400 ****************************************************************************/ 401 402 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 403 404 /* SAS */ 405 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 406 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 407 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 408 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 409 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 410 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 411 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 412 413 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 414 415 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 416 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 417 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 418 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 419 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 420 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 421 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 422 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 423 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 424 425 /* Manufacturing Page 0 */ 426 427 typedef struct _MPI2_CONFIG_PAGE_MAN_0 428 { 429 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 430 U8 ChipName[16]; /* 0x04 */ 431 U8 ChipRevision[8]; /* 0x14 */ 432 U8 BoardName[16]; /* 0x1C */ 433 U8 BoardAssembly[16]; /* 0x2C */ 434 U8 BoardTracerNumber[16]; /* 0x3C */ 435 } MPI2_CONFIG_PAGE_MAN_0, 436 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0, 437 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t; 438 439 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 440 441 /* Manufacturing Page 1 */ 442 443 typedef struct _MPI2_CONFIG_PAGE_MAN_1 444 { 445 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 446 U8 VPD[256]; /* 0x04 */ 447 } MPI2_CONFIG_PAGE_MAN_1, 448 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1, 449 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t; 450 451 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 452 453 typedef struct _MPI2_CHIP_REVISION_ID 454 { 455 U16 DeviceID; /* 0x00 */ 456 U8 PCIRevisionID; /* 0x02 */ 457 U8 Reserved; /* 0x03 */ 458 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID, 459 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t; 460 461 /* Manufacturing Page 2 */ 462 463 /* 464 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 465 * one and check Header.PageLength at runtime. 466 */ 467 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 468 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 469 #endif 470 471 typedef struct _MPI2_CONFIG_PAGE_MAN_2 472 { 473 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 474 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 475 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */ 476 } MPI2_CONFIG_PAGE_MAN_2, 477 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2, 478 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t; 479 480 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 481 482 /* Manufacturing Page 3 */ 483 484 /* 485 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 486 * one and check Header.PageLength at runtime. 487 */ 488 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS 489 #define MPI2_MAN_PAGE_3_INFO_WORDS (1) 490 #endif 491 492 typedef struct _MPI2_CONFIG_PAGE_MAN_3 493 { 494 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 495 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 496 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */ 497 } MPI2_CONFIG_PAGE_MAN_3, 498 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3, 499 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t; 500 501 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 502 503 /* Manufacturing Page 4 */ 504 505 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS 506 { 507 U8 PowerSaveFlags; /* 0x00 */ 508 U8 InternalOperationsSleepTime; /* 0x01 */ 509 U8 InternalOperationsRunTime; /* 0x02 */ 510 U8 HostIdleTime; /* 0x03 */ 511 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 512 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 513 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t; 514 515 /* defines for the PowerSaveFlags field */ 516 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 517 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 518 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 519 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 520 521 typedef struct _MPI2_CONFIG_PAGE_MAN_4 522 { 523 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 524 U32 Reserved1; /* 0x04 */ 525 U32 Flags; /* 0x08 */ 526 U8 InquirySize; /* 0x0C */ 527 U8 Reserved2; /* 0x0D */ 528 U16 Reserved3; /* 0x0E */ 529 U8 InquiryData[56]; /* 0x10 */ 530 U32 RAID0VolumeSettings; /* 0x48 */ 531 U32 RAID1EVolumeSettings; /* 0x4C */ 532 U32 RAID1VolumeSettings; /* 0x50 */ 533 U32 RAID10VolumeSettings; /* 0x54 */ 534 U32 Reserved4; /* 0x58 */ 535 U32 Reserved5; /* 0x5C */ 536 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */ 537 U8 MaxOCEDisks; /* 0x64 */ 538 U8 ResyncRate; /* 0x65 */ 539 U16 DataScrubDuration; /* 0x66 */ 540 U8 MaxHotSpares; /* 0x68 */ 541 U8 MaxPhysDisksPerVol; /* 0x69 */ 542 U8 MaxPhysDisks; /* 0x6A */ 543 U8 MaxVolumes; /* 0x6B */ 544 } MPI2_CONFIG_PAGE_MAN_4, 545 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4, 546 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t; 547 548 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 549 550 /* Manufacturing Page 4 Flags field */ 551 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 552 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 553 554 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 555 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 556 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 557 558 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 559 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 560 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 561 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 562 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 563 564 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 565 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 566 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 567 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 568 569 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 570 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 571 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 572 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 573 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 574 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 575 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 576 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 577 578 /* Manufacturing Page 5 */ 579 580 /* 581 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 582 * one and check the value returned for NumPhys at runtime. 583 */ 584 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 585 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 586 #endif 587 588 typedef struct _MPI2_MANUFACTURING5_ENTRY 589 { 590 U64 WWID; /* 0x00 */ 591 U64 DeviceName; /* 0x08 */ 592 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY, 593 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t; 594 595 typedef struct _MPI2_CONFIG_PAGE_MAN_5 596 { 597 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 598 U8 NumPhys; /* 0x04 */ 599 U8 Reserved1; /* 0x05 */ 600 U16 Reserved2; /* 0x06 */ 601 U32 Reserved3; /* 0x08 */ 602 U32 Reserved4; /* 0x0C */ 603 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */ 604 } MPI2_CONFIG_PAGE_MAN_5, 605 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5, 606 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t; 607 608 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 609 610 /* Manufacturing Page 6 */ 611 612 typedef struct _MPI2_CONFIG_PAGE_MAN_6 613 { 614 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 615 U32 ProductSpecificInfo;/* 0x04 */ 616 } MPI2_CONFIG_PAGE_MAN_6, 617 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6, 618 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t; 619 620 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 621 622 /* Manufacturing Page 7 */ 623 624 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO 625 { 626 U32 Pinout; /* 0x00 */ 627 U8 Connector[16]; /* 0x04 */ 628 U8 Location; /* 0x14 */ 629 U8 ReceptacleID; /* 0x15 */ 630 U16 Slot; /* 0x16 */ 631 U32 Reserved2; /* 0x18 */ 632 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 633 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t; 634 635 /* defines for the Pinout field */ 636 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 637 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 638 639 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 640 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 641 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 642 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 643 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 644 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 645 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 646 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 647 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 648 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 649 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 650 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 651 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 652 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 653 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 654 655 /* defines for the Location field */ 656 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 657 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 658 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 659 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 660 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 661 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 662 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 663 664 /* 665 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 666 * one and check the value returned for NumPhys at runtime. 667 */ 668 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 669 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 670 #endif 671 672 typedef struct _MPI2_CONFIG_PAGE_MAN_7 673 { 674 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 675 U32 Reserved1; /* 0x04 */ 676 U32 Reserved2; /* 0x08 */ 677 U32 Flags; /* 0x0C */ 678 U8 EnclosureName[16]; /* 0x10 */ 679 U8 NumPhys; /* 0x20 */ 680 U8 Reserved3; /* 0x21 */ 681 U16 Reserved4; /* 0x22 */ 682 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */ 683 } MPI2_CONFIG_PAGE_MAN_7, 684 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7, 685 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t; 686 687 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 688 689 /* defines for the Flags field */ 690 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 691 692 /* 693 * Generic structure to use for product-specific manufacturing pages 694 * (currently Manufacturing Page 8 through Manufacturing Page 31). 695 */ 696 697 typedef struct _MPI2_CONFIG_PAGE_MAN_PS 698 { 699 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 700 U32 ProductSpecificInfo;/* 0x04 */ 701 } MPI2_CONFIG_PAGE_MAN_PS, 702 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS, 703 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t; 704 705 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 706 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 707 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 708 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 709 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 710 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 711 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 712 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 713 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 714 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 715 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 716 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 717 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 718 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 719 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 720 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 721 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 722 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 723 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 724 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 725 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 726 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 727 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 728 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 729 730 /**************************************************************************** 731 * IO Unit Config Pages 732 ****************************************************************************/ 733 734 /* IO Unit Page 0 */ 735 736 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 737 { 738 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 739 U64 UniqueValue; /* 0x04 */ 740 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */ 741 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */ 742 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 743 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t; 744 745 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 746 747 /* IO Unit Page 1 */ 748 749 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 750 { 751 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 752 U32 Flags; /* 0x04 */ 753 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 754 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t; 755 756 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 757 758 /* IO Unit Page 1 Flags defines */ 759 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 760 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 761 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 762 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 763 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 764 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 765 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 766 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 767 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 768 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 769 770 /* IO Unit Page 3 */ 771 772 /* 773 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 774 * one and check the value returned for GPIOCount at runtime. 775 */ 776 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 777 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 778 #endif 779 780 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 781 { 782 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 783 U8 GPIOCount; /* 0x04 */ 784 U8 Reserved1; /* 0x05 */ 785 U16 Reserved2; /* 0x06 */ 786 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */ 787 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 788 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t; 789 790 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 791 792 /* defines for IO Unit Page 3 GPIOVal field */ 793 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 794 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 795 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 796 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 797 798 /* IO Unit Page 5 */ 799 800 /* 801 * Upper layer code (drivers, utilities, etc.) should leave this define set to 802 * one and check the value returned for NumDmaEngines at runtime. 803 */ 804 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 805 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 806 #endif 807 808 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 809 { 810 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 811 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */ 812 U64 RaidAcceleratorBufferSize; /* 0x0C */ 813 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */ 814 U8 RAControlSize; /* 0x1C */ 815 U8 NumDmaEngines; /* 0x1D */ 816 U8 RAMinControlSize; /* 0x1E */ 817 U8 RAMaxControlSize; /* 0x1F */ 818 U32 Reserved1; /* 0x20 */ 819 U32 Reserved2; /* 0x24 */ 820 U32 Reserved3; /* 0x28 */ 821 U32 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */ 822 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 823 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t; 824 825 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 826 827 /* defines for IO Unit Page 5 DmaEngineCapabilities field */ 828 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00) 829 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 830 831 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 832 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 833 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 834 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 835 836 /* IO Unit Page 6 */ 837 838 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 839 { 840 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 841 U16 Flags; /* 0x04 */ 842 U8 RAHostControlSize; /* 0x06 */ 843 U8 Reserved0; /* 0x07 */ 844 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */ 845 U32 Reserved1; /* 0x10 */ 846 U32 Reserved2; /* 0x14 */ 847 U32 Reserved3; /* 0x18 */ 848 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 849 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t; 850 851 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 852 853 /* defines for IO Unit Page 6 Flags field */ 854 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 855 856 /* IO Unit Page 7 */ 857 858 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 859 { 860 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 861 U16 Reserved1; /* 0x04 */ 862 U8 PCIeWidth; /* 0x06 */ 863 U8 PCIeSpeed; /* 0x07 */ 864 U32 ProcessorState; /* 0x08 */ 865 U32 PowerManagementCapabilities; /* 0x0C */ 866 U16 IOCTemperature; /* 0x10 */ 867 U8 IOCTemperatureUnits; /* 0x12 */ 868 U8 IOCSpeed; /* 0x13 */ 869 U16 BoardTemperature; /* 0x14 */ 870 U8 BoardTemperatureUnits; /* 0x16 */ 871 U8 Reserved3; /* 0x17 */ 872 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 873 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t; 874 875 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x02) 876 877 /* defines for IO Unit Page 7 PCIeWidth field */ 878 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 879 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 880 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 881 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 882 883 /* defines for IO Unit Page 7 PCIeSpeed field */ 884 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 885 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 886 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 887 888 /* defines for IO Unit Page 7 ProcessorState field */ 889 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 890 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 891 892 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 893 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 894 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 895 896 /* defines for IO Unit Page 7 PowerManagementCapabilities field */ 897 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 898 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 899 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 900 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) 901 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) 902 903 /* defines for IO Unit Page 7 IOCTemperatureUnits field */ 904 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 905 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 906 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 907 908 /* defines for IO Unit Page 7 IOCSpeed field */ 909 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 910 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 911 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 912 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 913 914 /* defines for IO Unit Page 7 BoardTemperatureUnits field */ 915 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 916 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 917 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 918 919 /**************************************************************************** 920 * IOC Config Pages 921 ****************************************************************************/ 922 923 /* IOC Page 0 */ 924 925 typedef struct _MPI2_CONFIG_PAGE_IOC_0 926 { 927 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 928 U32 Reserved1; /* 0x04 */ 929 U32 Reserved2; /* 0x08 */ 930 U16 VendorID; /* 0x0C */ 931 U16 DeviceID; /* 0x0E */ 932 U8 RevisionID; /* 0x10 */ 933 U8 Reserved3; /* 0x11 */ 934 U16 Reserved4; /* 0x12 */ 935 U32 ClassCode; /* 0x14 */ 936 U16 SubsystemVendorID; /* 0x18 */ 937 U16 SubsystemID; /* 0x1A */ 938 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0, 939 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t; 940 941 #define MPI2_IOCPAGE0_PAGEVERSION (0x02) 942 943 /* IOC Page 1 */ 944 945 typedef struct _MPI2_CONFIG_PAGE_IOC_1 946 { 947 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 948 U32 Flags; /* 0x04 */ 949 U32 CoalescingTimeout; /* 0x08 */ 950 U8 CoalescingDepth; /* 0x0C */ 951 U8 PCISlotNum; /* 0x0D */ 952 U8 PCIBusNum; /* 0x0E */ 953 U8 PCIDomainSegment; /* 0x0F */ 954 U32 Reserved1; /* 0x10 */ 955 U32 Reserved2; /* 0x14 */ 956 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1, 957 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t; 958 959 #define MPI2_IOCPAGE1_PAGEVERSION (0x05) 960 961 /* defines for IOC Page 1 Flags field */ 962 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 963 964 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 965 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 966 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 967 968 /* IOC Page 6 */ 969 970 typedef struct _MPI2_CONFIG_PAGE_IOC_6 971 { 972 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 973 U32 CapabilitiesFlags; /* 0x04 */ 974 U8 MaxDrivesRAID0; /* 0x08 */ 975 U8 MaxDrivesRAID1; /* 0x09 */ 976 U8 MaxDrivesRAID1E; /* 0x0A */ 977 U8 MaxDrivesRAID10; /* 0x0B */ 978 U8 MinDrivesRAID0; /* 0x0C */ 979 U8 MinDrivesRAID1; /* 0x0D */ 980 U8 MinDrivesRAID1E; /* 0x0E */ 981 U8 MinDrivesRAID10; /* 0x0F */ 982 U32 Reserved1; /* 0x10 */ 983 U8 MaxGlobalHotSpares; /* 0x14 */ 984 U8 MaxPhysDisks; /* 0x15 */ 985 U8 MaxVolumes; /* 0x16 */ 986 U8 MaxConfigs; /* 0x17 */ 987 U8 MaxOCEDisks; /* 0x18 */ 988 U8 Reserved2; /* 0x19 */ 989 U16 Reserved3; /* 0x1A */ 990 U32 SupportedStripeSizeMapRAID0; /* 0x1C */ 991 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */ 992 U32 SupportedStripeSizeMapRAID10; /* 0x24 */ 993 U32 Reserved4; /* 0x28 */ 994 U32 Reserved5; /* 0x2C */ 995 U16 DefaultMetadataSize; /* 0x30 */ 996 U16 Reserved6; /* 0x32 */ 997 U16 MaxBadBlockTableEntries; /* 0x34 */ 998 U16 Reserved7; /* 0x36 */ 999 U32 IRNvsramVersion; /* 0x38 */ 1000 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6, 1001 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t; 1002 1003 #define MPI2_IOCPAGE6_PAGEVERSION (0x04) 1004 1005 /* defines for IOC Page 6 CapabilitiesFlags */ 1006 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1007 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1008 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1009 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1010 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1011 1012 /* IOC Page 7 */ 1013 1014 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1015 1016 typedef struct _MPI2_CONFIG_PAGE_IOC_7 1017 { 1018 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1019 U32 Reserved1; /* 0x04 */ 1020 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */ 1021 U16 SASBroadcastPrimitiveMasks; /* 0x18 */ 1022 U16 Reserved2; /* 0x1A */ 1023 U32 Reserved3; /* 0x1C */ 1024 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7, 1025 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t; 1026 1027 #define MPI2_IOCPAGE7_PAGEVERSION (0x01) 1028 1029 /* IOC Page 8 */ 1030 1031 typedef struct _MPI2_CONFIG_PAGE_IOC_8 1032 { 1033 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1034 U8 NumDevsPerEnclosure; /* 0x04 */ 1035 U8 Reserved1; /* 0x05 */ 1036 U16 Reserved2; /* 0x06 */ 1037 U16 MaxPersistentEntries; /* 0x08 */ 1038 U16 MaxNumPhysicalMappedIDs; /* 0x0A */ 1039 U16 Flags; /* 0x0C */ 1040 U16 Reserved3; /* 0x0E */ 1041 U16 IRVolumeMappingFlags; /* 0x10 */ 1042 U16 Reserved4; /* 0x12 */ 1043 U32 Reserved5; /* 0x14 */ 1044 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8, 1045 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t; 1046 1047 #define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1048 1049 /* defines for IOC Page 8 Flags field */ 1050 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1051 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1052 1053 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1054 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1055 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1056 1057 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1058 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1059 1060 /* defines for IOC Page 8 IRVolumeMappingFlags */ 1061 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1062 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1063 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1064 1065 /**************************************************************************** 1066 * BIOS Config Pages 1067 ****************************************************************************/ 1068 1069 /* BIOS Page 1 */ 1070 1071 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 1072 { 1073 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1074 U32 BiosOptions; /* 0x04 */ 1075 U32 IOCSettings; /* 0x08 */ 1076 U32 Reserved1; /* 0x0C */ 1077 U32 DeviceSettings; /* 0x10 */ 1078 U16 NumberOfDevices; /* 0x14 */ 1079 U16 Reserved2; /* 0x16 */ 1080 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */ 1081 U16 IOTimeoutSequential; /* 0x1A */ 1082 U16 IOTimeoutOther; /* 0x1C */ 1083 U16 IOTimeoutBlockDevicesRM; /* 0x1E */ 1084 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1, 1085 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t; 1086 1087 #define MPI2_BIOSPAGE1_PAGEVERSION (0x04) 1088 1089 /* values for BIOS Page 1 BiosOptions field */ 1090 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1091 1092 /* values for BIOS Page 1 IOCSettings field */ 1093 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1094 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1095 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1096 1097 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1098 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1099 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1100 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1101 1102 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1103 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1104 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1105 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1106 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1107 1108 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1109 1110 /* values for BIOS Page 1 DeviceSettings field */ 1111 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1112 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1113 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1114 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1115 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1116 1117 /* BIOS Page 2 */ 1118 1119 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER 1120 { 1121 U32 Reserved1; /* 0x00 */ 1122 U32 Reserved2; /* 0x04 */ 1123 U32 Reserved3; /* 0x08 */ 1124 U32 Reserved4; /* 0x0C */ 1125 U32 Reserved5; /* 0x10 */ 1126 U32 Reserved6; /* 0x14 */ 1127 } MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1128 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1129 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t; 1130 1131 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID 1132 { 1133 U64 SASAddress; /* 0x00 */ 1134 U8 LUN[8]; /* 0x08 */ 1135 U32 Reserved1; /* 0x10 */ 1136 U32 Reserved2; /* 0x14 */ 1137 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1138 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t; 1139 1140 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT 1141 { 1142 U64 EnclosureLogicalID; /* 0x00 */ 1143 U32 Reserved1; /* 0x08 */ 1144 U32 Reserved2; /* 0x0C */ 1145 U16 SlotNumber; /* 0x10 */ 1146 U16 Reserved3; /* 0x12 */ 1147 U32 Reserved4; /* 0x14 */ 1148 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1149 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1150 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t; 1151 1152 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME 1153 { 1154 U64 DeviceName; /* 0x00 */ 1155 U8 LUN[8]; /* 0x08 */ 1156 U32 Reserved1; /* 0x10 */ 1157 U32 Reserved2; /* 0x14 */ 1158 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1159 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t; 1160 1161 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE 1162 { 1163 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1164 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1165 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1166 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1167 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1168 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t; 1169 1170 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 1171 { 1172 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1173 U32 Reserved1; /* 0x04 */ 1174 U32 Reserved2; /* 0x08 */ 1175 U32 Reserved3; /* 0x0C */ 1176 U32 Reserved4; /* 0x10 */ 1177 U32 Reserved5; /* 0x14 */ 1178 U32 Reserved6; /* 0x18 */ 1179 U8 ReqBootDeviceForm; /* 0x1C */ 1180 U8 Reserved7; /* 0x1D */ 1181 U16 Reserved8; /* 0x1E */ 1182 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */ 1183 U8 ReqAltBootDeviceForm; /* 0x38 */ 1184 U8 Reserved9; /* 0x39 */ 1185 U16 Reserved10; /* 0x3A */ 1186 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */ 1187 U8 CurrentBootDeviceForm; /* 0x58 */ 1188 U8 Reserved11; /* 0x59 */ 1189 U16 Reserved12; /* 0x5A */ 1190 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */ 1191 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2, 1192 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t; 1193 1194 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1195 1196 /* values for BIOS Page 2 BootDeviceForm fields */ 1197 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1198 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1199 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1200 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1201 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1202 1203 /* BIOS Page 3 */ 1204 1205 typedef struct _MPI2_ADAPTER_INFO 1206 { 1207 U8 PciBusNumber; /* 0x00 */ 1208 U8 PciDeviceAndFunctionNumber; /* 0x01 */ 1209 U16 AdapterFlags; /* 0x02 */ 1210 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO, 1211 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t; 1212 1213 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1214 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1215 1216 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 1217 { 1218 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1219 U32 GlobalFlags; /* 0x04 */ 1220 U32 BiosVersion; /* 0x08 */ 1221 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */ 1222 U32 Reserved1; /* 0x1C */ 1223 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3, 1224 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t; 1225 1226 #define MPI2_BIOSPAGE3_PAGEVERSION (0x00) 1227 1228 /* values for BIOS Page 3 GlobalFlags */ 1229 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1230 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1231 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1232 1233 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1234 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1235 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1236 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1237 1238 /* BIOS Page 4 */ 1239 1240 /* 1241 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1242 * one and check the value returned for NumPhys at runtime. 1243 */ 1244 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1245 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1246 #endif 1247 1248 typedef struct _MPI2_BIOS4_ENTRY 1249 { 1250 U64 ReassignmentWWID; /* 0x00 */ 1251 U64 ReassignmentDeviceName; /* 0x08 */ 1252 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY, 1253 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t; 1254 1255 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 1256 { 1257 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1258 U8 NumPhys; /* 0x04 */ 1259 U8 Reserved1; /* 0x05 */ 1260 U16 Reserved2; /* 0x06 */ 1261 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */ 1262 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4, 1263 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t; 1264 1265 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1266 1267 /**************************************************************************** 1268 * RAID Volume Config Pages 1269 ****************************************************************************/ 1270 1271 /* RAID Volume Page 0 */ 1272 1273 typedef struct _MPI2_RAIDVOL0_PHYS_DISK 1274 { 1275 U8 RAIDSetNum; /* 0x00 */ 1276 U8 PhysDiskMap; /* 0x01 */ 1277 U8 PhysDiskNum; /* 0x02 */ 1278 U8 Reserved; /* 0x03 */ 1279 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK, 1280 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t; 1281 1282 /* defines for the PhysDiskMap field */ 1283 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1284 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1285 1286 typedef struct _MPI2_RAIDVOL0_SETTINGS 1287 { 1288 U16 Settings; /* 0x00 */ 1289 U8 HotSparePool; /* 0x01 */ 1290 U8 Reserved; /* 0x02 */ 1291 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS, 1292 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t; 1293 1294 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1295 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1296 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1297 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1298 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1299 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1300 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1301 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1302 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1303 1304 /* RAID Volume Page 0 VolumeSettings defines */ 1305 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1306 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1307 1308 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1309 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1310 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1311 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1312 1313 /* 1314 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1315 * one and check the value returned for NumPhysDisks at runtime. 1316 */ 1317 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1318 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1319 #endif 1320 1321 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 1322 { 1323 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1324 U16 DevHandle; /* 0x04 */ 1325 U8 VolumeState; /* 0x06 */ 1326 U8 VolumeType; /* 0x07 */ 1327 U32 VolumeStatusFlags; /* 0x08 */ 1328 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */ 1329 U64 MaxLBA; /* 0x10 */ 1330 U32 StripeSize; /* 0x18 */ 1331 U16 BlockSize; /* 0x1C */ 1332 U16 Reserved1; /* 0x1E */ 1333 U8 SupportedPhysDisks; /* 0x20 */ 1334 U8 ResyncRate; /* 0x21 */ 1335 U16 DataScrubDuration; /* 0x22 */ 1336 U8 NumPhysDisks; /* 0x24 */ 1337 U8 Reserved2; /* 0x25 */ 1338 U8 Reserved3; /* 0x26 */ 1339 U8 InactiveStatus; /* 0x27 */ 1340 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */ 1341 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1342 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t; 1343 1344 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1345 1346 /* values for RAID VolumeState */ 1347 #define MPI2_RAID_VOL_STATE_MISSING (0x00) 1348 #define MPI2_RAID_VOL_STATE_FAILED (0x01) 1349 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1350 #define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1351 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1352 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1353 1354 /* values for RAID VolumeType */ 1355 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1356 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1357 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1358 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1359 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1360 1361 /* values for RAID Volume Page 0 VolumeStatusFlags field */ 1362 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1363 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1364 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1365 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1366 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1367 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1368 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1369 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1370 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1371 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1372 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1373 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1374 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1375 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1376 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1377 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1378 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1379 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1380 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1381 1382 /* values for RAID Volume Page 0 SupportedPhysDisks field */ 1383 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1384 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1385 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1386 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1387 1388 /* values for RAID Volume Page 0 InactiveStatus field */ 1389 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1390 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1391 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1392 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1393 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1394 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1395 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1396 1397 /* RAID Volume Page 1 */ 1398 1399 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 1400 { 1401 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1402 U16 DevHandle; /* 0x04 */ 1403 U16 Reserved0; /* 0x06 */ 1404 U8 GUID[24]; /* 0x08 */ 1405 U8 Name[16]; /* 0x20 */ 1406 U64 WWID; /* 0x30 */ 1407 U32 Reserved1; /* 0x38 */ 1408 U32 Reserved2; /* 0x3C */ 1409 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1410 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t; 1411 1412 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1413 1414 /**************************************************************************** 1415 * RAID Physical Disk Config Pages 1416 ****************************************************************************/ 1417 1418 /* RAID Physical Disk Page 0 */ 1419 1420 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS 1421 { 1422 U16 Reserved1; /* 0x00 */ 1423 U8 HotSparePool; /* 0x02 */ 1424 U8 Reserved2; /* 0x03 */ 1425 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1426 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t; 1427 1428 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1429 1430 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA 1431 { 1432 U8 VendorID[8]; /* 0x00 */ 1433 U8 ProductID[16]; /* 0x08 */ 1434 U8 ProductRevLevel[4]; /* 0x18 */ 1435 U8 SerialNum[32]; /* 0x1C */ 1436 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1437 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1438 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t; 1439 1440 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 1441 { 1442 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1443 U16 DevHandle; /* 0x04 */ 1444 U8 Reserved1; /* 0x06 */ 1445 U8 PhysDiskNum; /* 0x07 */ 1446 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */ 1447 U32 Reserved2; /* 0x0C */ 1448 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */ 1449 U32 Reserved3; /* 0x4C */ 1450 U8 PhysDiskState; /* 0x50 */ 1451 U8 OfflineReason; /* 0x51 */ 1452 U8 IncompatibleReason; /* 0x52 */ 1453 U8 PhysDiskAttributes; /* 0x53 */ 1454 U32 PhysDiskStatusFlags; /* 0x54 */ 1455 U64 DeviceMaxLBA; /* 0x58 */ 1456 U64 HostMaxLBA; /* 0x60 */ 1457 U64 CoercedMaxLBA; /* 0x68 */ 1458 U16 BlockSize; /* 0x70 */ 1459 U16 Reserved5; /* 0x72 */ 1460 U32 Reserved6; /* 0x74 */ 1461 } MPI2_CONFIG_PAGE_RD_PDISK_0, 1462 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1463 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t; 1464 1465 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1466 1467 /* PhysDiskState defines */ 1468 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1469 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1470 #define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1471 #define MPI2_RAID_PD_STATE_ONLINE (0x03) 1472 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1473 #define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1474 #define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1475 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1476 1477 /* OfflineReason defines */ 1478 #define MPI2_PHYSDISK0_ONLINE (0x00) 1479 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1480 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1481 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1482 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1483 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1484 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1485 1486 /* IncompatibleReason defines */ 1487 #define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1488 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1489 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1490 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1491 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1492 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1493 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 1494 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1495 1496 /* PhysDiskAttributes defines */ 1497 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 1498 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1499 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1500 1501 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 1502 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1503 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1504 1505 /* PhysDiskStatusFlags defines */ 1506 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1507 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1508 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1509 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1510 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1511 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 1512 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 1513 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 1514 1515 /* RAID Physical Disk Page 1 */ 1516 1517 /* 1518 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1519 * one and check the value returned for NumPhysDiskPaths at runtime. 1520 */ 1521 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 1522 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 1523 #endif 1524 1525 typedef struct _MPI2_RAIDPHYSDISK1_PATH 1526 { 1527 U16 DevHandle; /* 0x00 */ 1528 U16 Reserved1; /* 0x02 */ 1529 U64 WWID; /* 0x04 */ 1530 U64 OwnerWWID; /* 0x0C */ 1531 U8 OwnerIdentifier; /* 0x14 */ 1532 U8 Reserved2; /* 0x15 */ 1533 U16 Flags; /* 0x16 */ 1534 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH, 1535 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t; 1536 1537 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 1538 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 1539 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 1540 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 1541 1542 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 1543 { 1544 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1545 U8 NumPhysDiskPaths; /* 0x04 */ 1546 U8 PhysDiskNum; /* 0x05 */ 1547 U16 Reserved1; /* 0x06 */ 1548 U32 Reserved2; /* 0x08 */ 1549 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */ 1550 } MPI2_CONFIG_PAGE_RD_PDISK_1, 1551 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 1552 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t; 1553 1554 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 1555 1556 /**************************************************************************** 1557 * values for fields used by several types of SAS Config Pages 1558 ****************************************************************************/ 1559 1560 /* values for NegotiatedLinkRates fields */ 1561 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 1562 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 1563 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 1564 /* link rates used for Negotiated Physical and Logical Link Rate */ 1565 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 1566 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 1567 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 1568 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 1569 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 1570 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 1571 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 1572 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 1573 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 1574 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 1575 1576 /* values for AttachedPhyInfo fields */ 1577 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 1578 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 1579 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 1580 1581 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 1582 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 1583 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 1584 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 1585 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 1586 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 1587 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 1588 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 1589 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 1590 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 1591 1592 /* values for PhyInfo fields */ 1593 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 1594 1595 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 1596 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 1597 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 1598 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 1599 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 1600 1601 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 1602 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 1603 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 1604 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 1605 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 1606 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 1607 1608 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 1609 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 1610 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 1611 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 1612 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 1613 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 1614 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 1615 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 1616 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 1617 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 1618 1619 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 1620 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 1621 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 1622 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 1623 1624 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 1625 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 1626 1627 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 1628 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 1629 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 1630 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 1631 1632 /* values for SAS ProgrammedLinkRate fields */ 1633 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 1634 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 1635 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 1636 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 1637 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 1638 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 1639 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 1640 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 1641 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 1642 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 1643 1644 /* values for SAS HwLinkRate fields */ 1645 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 1646 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 1647 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 1648 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 1649 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 1650 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 1651 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 1652 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 1653 1654 /**************************************************************************** 1655 * SAS IO Unit Config Pages 1656 ****************************************************************************/ 1657 1658 /* SAS IO Unit Page 0 */ 1659 1660 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA 1661 { 1662 U8 Port; /* 0x00 */ 1663 U8 PortFlags; /* 0x01 */ 1664 U8 PhyFlags; /* 0x02 */ 1665 U8 NegotiatedLinkRate; /* 0x03 */ 1666 U32 ControllerPhyDeviceInfo;/* 0x04 */ 1667 U16 AttachedDevHandle; /* 0x08 */ 1668 U16 ControllerDevHandle; /* 0x0A */ 1669 U32 DiscoveryStatus; /* 0x0C */ 1670 U32 Reserved; /* 0x10 */ 1671 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 1672 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t; 1673 1674 /* 1675 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1676 * one and check the value returned for NumPhys at runtime. 1677 */ 1678 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX 1679 #define MPI2_SAS_IOUNIT0_PHY_MAX (1) 1680 #endif 1681 1682 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 1683 { 1684 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1685 U32 Reserved1; /* 0x08 */ 1686 U8 NumPhys; /* 0x0C */ 1687 U8 Reserved2; /* 0x0D */ 1688 U16 Reserved3; /* 0x0E */ 1689 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */ 1690 } MPI2_CONFIG_PAGE_SASIOUNIT_0, 1691 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 1692 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t; 1693 1694 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 1695 1696 /* values for SAS IO Unit Page 0 PortFlags */ 1697 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 1698 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 1699 1700 /* values for SAS IO Unit Page 0 PhyFlags */ 1701 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 1702 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 1703 1704 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 1705 1706 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 1707 1708 /* values for SAS IO Unit Page 0 DiscoveryStatus */ 1709 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 1710 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 1711 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 1712 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 1713 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 1714 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 1715 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 1716 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 1717 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 1718 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 1719 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 1720 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 1721 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 1722 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 1723 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 1724 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 1725 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 1726 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 1727 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 1728 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 1729 1730 /* SAS IO Unit Page 1 */ 1731 1732 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA 1733 { 1734 U8 Port; /* 0x00 */ 1735 U8 PortFlags; /* 0x01 */ 1736 U8 PhyFlags; /* 0x02 */ 1737 U8 MaxMinLinkRate; /* 0x03 */ 1738 U32 ControllerPhyDeviceInfo; /* 0x04 */ 1739 U16 MaxTargetPortConnectTime; /* 0x08 */ 1740 U16 Reserved1; /* 0x0A */ 1741 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 1742 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t; 1743 1744 /* 1745 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1746 * one and check the value returned for NumPhys at runtime. 1747 */ 1748 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX 1749 #define MPI2_SAS_IOUNIT1_PHY_MAX (1) 1750 #endif 1751 1752 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 1753 { 1754 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1755 U16 ControlFlags; /* 0x08 */ 1756 U16 SASNarrowMaxQueueDepth; /* 0x0A */ 1757 U16 AdditionalControlFlags; /* 0x0C */ 1758 U16 SASWideMaxQueueDepth; /* 0x0E */ 1759 U8 NumPhys; /* 0x10 */ 1760 U8 SATAMaxQDepth; /* 0x11 */ 1761 U8 ReportDeviceMissingDelay; /* 0x12 */ 1762 U8 IODeviceMissingDelay; /* 0x13 */ 1763 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */ 1764 } MPI2_CONFIG_PAGE_SASIOUNIT_1, 1765 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 1766 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t; 1767 1768 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 1769 1770 /* values for SAS IO Unit Page 1 ControlFlags */ 1771 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 1772 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 1773 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 1774 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 1775 1776 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 1777 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 1778 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 1779 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 1780 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 1781 1782 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 1783 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 1784 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 1785 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 1786 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 1787 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 1788 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 1789 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 1790 1791 /* values for SAS IO Unit Page 1 AdditionalControlFlags */ 1792 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 1793 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 1794 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 1795 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 1796 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 1797 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 1798 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 1799 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 1800 1801 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 1802 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 1803 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 1804 1805 /* values for SAS IO Unit Page 1 PortFlags */ 1806 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 1807 1808 /* values for SAS IO Unit Page 1 PhyFlags */ 1809 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 1810 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 1811 1812 /* values for SAS IO Unit Page 1 MaxMinLinkRate */ 1813 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 1814 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 1815 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 1816 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 1817 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 1818 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 1819 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 1820 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 1821 1822 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 1823 1824 /* SAS IO Unit Page 4 */ 1825 1826 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP 1827 { 1828 U8 MaxTargetSpinup; /* 0x00 */ 1829 U8 SpinupDelay; /* 0x01 */ 1830 U16 Reserved1; /* 0x02 */ 1831 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 1832 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t; 1833 1834 /* 1835 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1836 * one and check the value returned for NumPhys at runtime. 1837 */ 1838 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX 1839 #define MPI2_SAS_IOUNIT4_PHY_MAX (4) 1840 #endif 1841 1842 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 1843 { 1844 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1845 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 1846 U32 Reserved1; /* 0x18 */ 1847 U32 Reserved2; /* 0x1C */ 1848 U32 Reserved3; /* 0x20 */ 1849 U8 BootDeviceWaitTime; /* 0x24 */ 1850 U8 Reserved4; /* 0x25 */ 1851 U16 Reserved5; /* 0x26 */ 1852 U8 NumPhys; /* 0x28 */ 1853 U8 PEInitialSpinupDelay; /* 0x29 */ 1854 U8 PEReplyDelay; /* 0x2A */ 1855 U8 Flags; /* 0x2B */ 1856 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */ 1857 } MPI2_CONFIG_PAGE_SASIOUNIT_4, 1858 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 1859 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t; 1860 1861 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 1862 1863 /* defines for Flags field */ 1864 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 1865 1866 /* defines for PHY field */ 1867 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 1868 1869 /* SAS IO Unit Page 5 */ 1870 1871 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 1872 { 1873 U8 ControlFlags; /* 0x00 */ 1874 U8 PortWidthModGroup; /* 0x01 */ 1875 U16 InactivityTimerExponent; /* 0x02 */ 1876 U8 SATAPartialTimeout; /* 0x04 */ 1877 U8 Reserved2; /* 0x05 */ 1878 U8 SATASlumberTimeout; /* 0x06 */ 1879 U8 Reserved3; /* 0x07 */ 1880 U8 SASPartialTimeout; /* 0x08 */ 1881 U8 Reserved4; /* 0x09 */ 1882 U8 SASSlumberTimeout; /* 0x0A */ 1883 U8 Reserved5; /* 0x0B */ 1884 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 1885 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 1886 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t; 1887 1888 /* defines for ControlFlags field */ 1889 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 1890 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 1891 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 1892 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 1893 1894 /* defines for PortWidthModeGroup field */ 1895 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 1896 1897 /* defines for InactivityTimerExponent field */ 1898 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 1899 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 1900 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 1901 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 1902 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 1903 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 1904 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 1905 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 1906 1907 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 1908 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 1909 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 1910 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 1911 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 1912 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 1913 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 1914 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 1915 1916 /* 1917 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1918 * one and check the value returned for NumPhys at runtime. 1919 */ 1920 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX 1921 #define MPI2_SAS_IOUNIT5_PHY_MAX (1) 1922 #endif 1923 1924 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 1925 { 1926 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1927 U8 NumPhys; /* 0x08 */ 1928 U8 Reserved1; /* 0x09 */ 1929 U16 Reserved2; /* 0x0A */ 1930 U32 Reserved3; /* 0x0C */ 1931 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */ 1932 } MPI2_CONFIG_PAGE_SASIOUNIT_5, 1933 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 1934 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t; 1935 1936 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 1937 1938 /* SAS IO Unit Page 6 */ 1939 1940 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 1941 { 1942 U8 CurrentStatus; /* 0x00 */ 1943 U8 CurrentModulation; /* 0x01 */ 1944 U8 CurrentUtilization; /* 0x02 */ 1945 U8 Reserved1; /* 0x03 */ 1946 U32 Reserved2; /* 0x04 */ 1947 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 1948 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 1949 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 1950 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t; 1951 1952 /* defines for CurrentStatus field */ 1953 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 1954 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 1955 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 1956 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 1957 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 1958 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 1959 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 1960 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 1961 1962 /* defines for CurrentModulation field */ 1963 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 1964 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 1965 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 1966 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 1967 1968 /* 1969 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1970 * one and check the value returned for NumGroups at runtime. 1971 */ 1972 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 1973 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 1974 #endif 1975 1976 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 1977 { 1978 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1979 U32 Reserved1; /* 0x08 */ 1980 U32 Reserved2; /* 0x0C */ 1981 U8 NumGroups; /* 0x10 */ 1982 U8 Reserved3; /* 0x11 */ 1983 U16 Reserved4; /* 0x12 */ 1984 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 1985 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */ 1986 } MPI2_CONFIG_PAGE_SASIOUNIT_6, 1987 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 1988 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t; 1989 1990 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 1991 1992 /* SAS IO Unit Page 7 */ 1993 1994 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 1995 { 1996 U8 Flags; /* 0x00 */ 1997 U8 Reserved1; /* 0x01 */ 1998 U16 Reserved2; /* 0x02 */ 1999 U8 Threshold75Pct; /* 0x04 */ 2000 U8 Threshold50Pct; /* 0x05 */ 2001 U8 Threshold25Pct; /* 0x06 */ 2002 U8 Reserved3; /* 0x07 */ 2003 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2004 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2005 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2006 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2007 2008 /* defines for Flags field */ 2009 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2010 2011 /* 2012 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2013 * one and check the value returned for NumGroups at runtime. 2014 */ 2015 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2016 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2017 #endif 2018 2019 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 2020 { 2021 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2022 U8 SamplingInterval; /* 0x08 */ 2023 U8 WindowLength; /* 0x09 */ 2024 U16 Reserved1; /* 0x0A */ 2025 U32 Reserved2; /* 0x0C */ 2026 U32 Reserved3; /* 0x10 */ 2027 U8 NumGroups; /* 0x14 */ 2028 U8 Reserved4; /* 0x15 */ 2029 U16 Reserved5; /* 0x16 */ 2030 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2031 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */ 2032 } MPI2_CONFIG_PAGE_SASIOUNIT_7, 2033 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2034 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t; 2035 2036 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2037 2038 /* SAS IO Unit Page 8 */ 2039 2040 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 2041 { 2042 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2043 U32 Reserved1; /* 0x08 */ 2044 U32 PowerManagementCapabilities; /* 0x0C */ 2045 U32 Reserved2; /* 0x10 */ 2046 } MPI2_CONFIG_PAGE_SASIOUNIT_8, 2047 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2048 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t; 2049 2050 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2051 2052 /* defines for PowerManagementCapabilities field */ 2053 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x000001000) 2054 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x000000800) 2055 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x000000400) 2056 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x000000200) 2057 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x000000100) 2058 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x000000010) 2059 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x000000008) 2060 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x000000004) 2061 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x000000002) 2062 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x000000001) 2063 2064 /**************************************************************************** 2065 * SAS Expander Config Pages 2066 ****************************************************************************/ 2067 2068 /* SAS Expander Page 0 */ 2069 2070 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 2071 { 2072 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2073 U8 PhysicalPort; /* 0x08 */ 2074 U8 ReportGenLength; /* 0x09 */ 2075 U16 EnclosureHandle; /* 0x0A */ 2076 U64 SASAddress; /* 0x0C */ 2077 U32 DiscoveryStatus; /* 0x14 */ 2078 U16 DevHandle; /* 0x18 */ 2079 U16 ParentDevHandle; /* 0x1A */ 2080 U16 ExpanderChangeCount; /* 0x1C */ 2081 U16 ExpanderRouteIndexes; /* 0x1E */ 2082 U8 NumPhys; /* 0x20 */ 2083 U8 SASLevel; /* 0x21 */ 2084 U16 Flags; /* 0x22 */ 2085 U16 STPBusInactivityTimeLimit; /* 0x24 */ 2086 U16 STPMaxConnectTimeLimit; /* 0x26 */ 2087 U16 STP_SMP_NexusLossTime; /* 0x28 */ 2088 U16 MaxNumRoutedSasAddresses; /* 0x2A */ 2089 U64 ActiveZoneManagerSASAddress;/* 0x2C */ 2090 U16 ZoneLockInactivityLimit; /* 0x34 */ 2091 U16 Reserved1; /* 0x36 */ 2092 U8 TimeToReducedFunc; /* 0x38 */ 2093 U8 InitialTimeToReducedFunc; /* 0x39 */ 2094 U8 MaxReducedFuncTime; /* 0x3A */ 2095 U8 Reserved2; /* 0x3B */ 2096 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2097 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t; 2098 2099 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2100 2101 /* values for SAS Expander Page 0 DiscoveryStatus field */ 2102 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2103 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2104 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2105 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2106 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2107 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2108 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2109 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2110 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2111 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2112 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2113 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2114 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2115 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2116 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2117 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2118 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2119 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2120 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2121 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2122 2123 /* values for SAS Expander Page 0 Flags field */ 2124 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2125 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2126 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2127 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2128 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2129 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2130 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2131 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2132 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2133 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2134 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2135 2136 /* SAS Expander Page 1 */ 2137 2138 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 2139 { 2140 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2141 U8 PhysicalPort; /* 0x08 */ 2142 U8 Reserved1; /* 0x09 */ 2143 U16 Reserved2; /* 0x0A */ 2144 U8 NumPhys; /* 0x0C */ 2145 U8 Phy; /* 0x0D */ 2146 U16 NumTableEntriesProgrammed; /* 0x0E */ 2147 U8 ProgrammedLinkRate; /* 0x10 */ 2148 U8 HwLinkRate; /* 0x11 */ 2149 U16 AttachedDevHandle; /* 0x12 */ 2150 U32 PhyInfo; /* 0x14 */ 2151 U32 AttachedDeviceInfo; /* 0x18 */ 2152 U16 ExpanderDevHandle; /* 0x1C */ 2153 U8 ChangeCount; /* 0x1E */ 2154 U8 NegotiatedLinkRate; /* 0x1F */ 2155 U8 PhyIdentifier; /* 0x20 */ 2156 U8 AttachedPhyIdentifier; /* 0x21 */ 2157 U8 Reserved3; /* 0x22 */ 2158 U8 DiscoveryInfo; /* 0x23 */ 2159 U32 AttachedPhyInfo; /* 0x24 */ 2160 U8 ZoneGroup; /* 0x28 */ 2161 U8 SelfConfigStatus; /* 0x29 */ 2162 U16 Reserved4; /* 0x2A */ 2163 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2164 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t; 2165 2166 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2167 2168 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2169 2170 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2171 2172 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2173 2174 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */ 2175 2176 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2177 2178 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2179 2180 /* values for SAS Expander Page 1 DiscoveryInfo field */ 2181 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2182 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2183 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2184 2185 /**************************************************************************** 2186 * SAS Device Config Pages 2187 ****************************************************************************/ 2188 2189 /* SAS Device Page 0 */ 2190 2191 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 2192 { 2193 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2194 U16 Slot; /* 0x08 */ 2195 U16 EnclosureHandle; /* 0x0A */ 2196 U64 SASAddress; /* 0x0C */ 2197 U16 ParentDevHandle; /* 0x14 */ 2198 U8 PhyNum; /* 0x16 */ 2199 U8 AccessStatus; /* 0x17 */ 2200 U16 DevHandle; /* 0x18 */ 2201 U8 AttachedPhyIdentifier; /* 0x1A */ 2202 U8 ZoneGroup; /* 0x1B */ 2203 U32 DeviceInfo; /* 0x1C */ 2204 U16 Flags; /* 0x20 */ 2205 U8 PhysicalPort; /* 0x22 */ 2206 U8 MaxPortConnections; /* 0x23 */ 2207 U64 DeviceName; /* 0x24 */ 2208 U8 PortGroups; /* 0x2C */ 2209 U8 DmaGroup; /* 0x2D */ 2210 U8 ControlGroup; /* 0x2E */ 2211 U8 Reserved1; /* 0x2F */ 2212 U32 Reserved2; /* 0x30 */ 2213 U32 Reserved3; /* 0x34 */ 2214 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2215 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t; 2216 2217 #define MPI2_SASDEVICE0_PAGEVERSION (0x08) 2218 2219 /* values for SAS Device Page 0 AccessStatus field */ 2220 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2221 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2222 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2223 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2224 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2225 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2226 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2227 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2228 /* specific values for SATA Init failures */ 2229 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2230 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2231 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2232 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2233 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2234 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2235 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2236 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2237 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2238 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2239 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2240 2241 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2242 2243 /* values for SAS Device Page 0 Flags field */ 2244 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2245 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2246 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2247 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2248 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2249 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2250 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2251 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2252 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2253 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2254 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2255 2256 /* SAS Device Page 1 */ 2257 2258 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 2259 { 2260 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2261 U32 Reserved1; /* 0x08 */ 2262 U64 SASAddress; /* 0x0C */ 2263 U32 Reserved2; /* 0x14 */ 2264 U16 DevHandle; /* 0x18 */ 2265 U16 Reserved3; /* 0x1A */ 2266 U8 InitialRegDeviceFIS[20];/* 0x1C */ 2267 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2268 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t; 2269 2270 #define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2271 2272 /**************************************************************************** 2273 * SAS PHY Config Pages 2274 ****************************************************************************/ 2275 2276 /* SAS PHY Page 0 */ 2277 2278 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 2279 { 2280 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2281 U16 OwnerDevHandle; /* 0x08 */ 2282 U16 Reserved1; /* 0x0A */ 2283 U16 AttachedDevHandle; /* 0x0C */ 2284 U8 AttachedPhyIdentifier; /* 0x0E */ 2285 U8 Reserved2; /* 0x0F */ 2286 U32 AttachedPhyInfo; /* 0x10 */ 2287 U8 ProgrammedLinkRate; /* 0x14 */ 2288 U8 HwLinkRate; /* 0x15 */ 2289 U8 ChangeCount; /* 0x16 */ 2290 U8 Flags; /* 0x17 */ 2291 U32 PhyInfo; /* 0x18 */ 2292 U8 NegotiatedLinkRate; /* 0x1C */ 2293 U8 Reserved3; /* 0x1D */ 2294 U16 Reserved4; /* 0x1E */ 2295 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2296 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t; 2297 2298 #define MPI2_SASPHY0_PAGEVERSION (0x03) 2299 2300 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2301 2302 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2303 2304 /* values for SAS PHY Page 0 Flags field */ 2305 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2306 2307 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2308 2309 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2310 2311 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2312 2313 /* SAS PHY Page 1 */ 2314 2315 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 2316 { 2317 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2318 U32 Reserved1; /* 0x08 */ 2319 U32 InvalidDwordCount; /* 0x0C */ 2320 U32 RunningDisparityErrorCount; /* 0x10 */ 2321 U32 LossDwordSynchCount; /* 0x14 */ 2322 U32 PhyResetProblemCount; /* 0x18 */ 2323 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 2324 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t; 2325 2326 #define MPI2_SASPHY1_PAGEVERSION (0x01) 2327 2328 /* SAS PHY Page 2 */ 2329 2330 typedef struct _MPI2_SASPHY2_PHY_EVENT 2331 { 2332 U8 PhyEventCode; /* 0x00 */ 2333 U8 Reserved1; /* 0x01 */ 2334 U16 Reserved2; /* 0x02 */ 2335 U32 PhyEventInfo; /* 0x04 */ 2336 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT, 2337 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t; 2338 2339 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 2340 2341 /* 2342 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2343 * one and check the value returned for NumPhyEvents at runtime. 2344 */ 2345 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX 2346 #define MPI2_SASPHY2_PHY_EVENT_MAX (1) 2347 #endif 2348 2349 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 2350 { 2351 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2352 U32 Reserved1; /* 0x08 */ 2353 U8 NumPhyEvents; /* 0x0C */ 2354 U8 Reserved2; /* 0x0D */ 2355 U16 Reserved3; /* 0x0E */ 2356 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */ 2357 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 2358 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t; 2359 2360 #define MPI2_SASPHY2_PAGEVERSION (0x00) 2361 2362 /* SAS PHY Page 3 */ 2363 2364 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG 2365 { 2366 U8 PhyEventCode; /* 0x00 */ 2367 U8 Reserved1; /* 0x01 */ 2368 U16 Reserved2; /* 0x02 */ 2369 U8 CounterType; /* 0x04 */ 2370 U8 ThresholdWindow; /* 0x05 */ 2371 U8 TimeUnits; /* 0x06 */ 2372 U8 Reserved3; /* 0x07 */ 2373 U32 EventThreshold; /* 0x08 */ 2374 U16 ThresholdFlags; /* 0x0C */ 2375 U16 Reserved4; /* 0x0E */ 2376 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 2377 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t; 2378 2379 /* values for PhyEventCode field */ 2380 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2381 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2382 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2383 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2384 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2385 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 2386 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 2387 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 2388 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 2389 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 2390 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 2391 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 2392 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 2393 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 2394 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 2395 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 2396 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 2397 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 2398 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 2399 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 2400 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 2401 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 2402 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 2403 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 2404 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 2405 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 2406 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 2407 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 2408 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 2409 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 2410 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 2411 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 2412 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 2413 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 2414 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 2415 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 2416 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 2417 2418 /* values for the CounterType field */ 2419 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 2420 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 2421 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 2422 2423 /* values for the TimeUnits field */ 2424 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 2425 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 2426 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 2427 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 2428 2429 /* values for the ThresholdFlags field */ 2430 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 2431 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 2432 2433 /* 2434 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2435 * one and check the value returned for NumPhyEvents at runtime. 2436 */ 2437 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX 2438 #define MPI2_SASPHY3_PHY_EVENT_MAX (1) 2439 #endif 2440 2441 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 2442 { 2443 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2444 U32 Reserved1; /* 0x08 */ 2445 U8 NumPhyEvents; /* 0x0C */ 2446 U8 Reserved2; /* 0x0D */ 2447 U16 Reserved3; /* 0x0E */ 2448 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */ 2449 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 2450 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t; 2451 2452 #define MPI2_SASPHY3_PAGEVERSION (0x00) 2453 2454 /* SAS PHY Page 4 */ 2455 2456 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 2457 { 2458 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2459 U16 Reserved1; /* 0x08 */ 2460 U8 Reserved2; /* 0x0A */ 2461 U8 Flags; /* 0x0B */ 2462 U8 InitialFrame[28]; /* 0x0C */ 2463 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 2464 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t; 2465 2466 #define MPI2_SASPHY4_PAGEVERSION (0x00) 2467 2468 /* values for the Flags field */ 2469 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 2470 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 2471 2472 /**************************************************************************** 2473 * SAS Port Config Pages 2474 ****************************************************************************/ 2475 2476 /* SAS Port Page 0 */ 2477 2478 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 2479 { 2480 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2481 U8 PortNumber; /* 0x08 */ 2482 U8 PhysicalPort; /* 0x09 */ 2483 U8 PortWidth; /* 0x0A */ 2484 U8 PhysicalPortWidth; /* 0x0B */ 2485 U8 ZoneGroup; /* 0x0C */ 2486 U8 Reserved1; /* 0x0D */ 2487 U16 Reserved2; /* 0x0E */ 2488 U64 SASAddress; /* 0x10 */ 2489 U32 DeviceInfo; /* 0x18 */ 2490 U32 Reserved3; /* 0x1C */ 2491 U32 Reserved4; /* 0x20 */ 2492 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 2493 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t; 2494 2495 #define MPI2_SASPORT0_PAGEVERSION (0x00) 2496 2497 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 2498 2499 /**************************************************************************** 2500 * SAS Enclosure Config Pages 2501 ****************************************************************************/ 2502 2503 /* SAS Enclosure Page 0 */ 2504 2505 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 2506 { 2507 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2508 U32 Reserved1; /* 0x08 */ 2509 U64 EnclosureLogicalID; /* 0x0C */ 2510 U16 Flags; /* 0x14 */ 2511 U16 EnclosureHandle; /* 0x16 */ 2512 U16 NumSlots; /* 0x18 */ 2513 U16 StartSlot; /* 0x1A */ 2514 U16 Reserved2; /* 0x1C */ 2515 U16 SEPDevHandle; /* 0x1E */ 2516 U32 Reserved3; /* 0x20 */ 2517 U32 Reserved4; /* 0x24 */ 2518 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 2519 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 2520 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t; 2521 2522 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x03) 2523 2524 /* values for SAS Enclosure Page 0 Flags field */ 2525 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 2526 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 2527 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 2528 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 2529 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 2530 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 2531 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 2532 2533 /**************************************************************************** 2534 * Log Config Page 2535 ****************************************************************************/ 2536 2537 /* Log Page 0 */ 2538 2539 /* 2540 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2541 * one and check the value returned for NumLogEntries at runtime. 2542 */ 2543 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 2544 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 2545 #endif 2546 2547 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 2548 2549 typedef struct _MPI2_LOG_0_ENTRY 2550 { 2551 U64 TimeStamp; /* 0x00 */ 2552 U32 Reserved1; /* 0x08 */ 2553 U16 LogSequence; /* 0x0C */ 2554 U16 LogEntryQualifier; /* 0x0E */ 2555 U8 VP_ID; /* 0x10 */ 2556 U8 VF_ID; /* 0x11 */ 2557 U16 Reserved2; /* 0x12 */ 2558 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */ 2559 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY, 2560 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t; 2561 2562 /* values for Log Page 0 LogEntry LogEntryQualifier field */ 2563 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 2564 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 2565 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 2566 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 2567 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 2568 2569 typedef struct _MPI2_CONFIG_PAGE_LOG_0 2570 { 2571 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2572 U32 Reserved1; /* 0x08 */ 2573 U32 Reserved2; /* 0x0C */ 2574 U16 NumLogEntries; /* 0x10 */ 2575 U16 Reserved3; /* 0x12 */ 2576 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */ 2577 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0, 2578 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t; 2579 2580 #define MPI2_LOG_0_PAGEVERSION (0x02) 2581 2582 /**************************************************************************** 2583 * RAID Config Page 2584 ****************************************************************************/ 2585 2586 /* RAID Page 0 */ 2587 2588 /* 2589 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2590 * one and check the value returned for NumElements at runtime. 2591 */ 2592 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 2593 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 2594 #endif 2595 2596 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT 2597 { 2598 U16 ElementFlags; /* 0x00 */ 2599 U16 VolDevHandle; /* 0x02 */ 2600 U8 HotSparePool; /* 0x04 */ 2601 U8 PhysDiskNum; /* 0x05 */ 2602 U16 PhysDiskDevHandle; /* 0x06 */ 2603 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 2604 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 2605 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t; 2606 2607 /* values for the ElementFlags field */ 2608 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 2609 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 2610 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 2611 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 2612 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 2613 2614 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 2615 { 2616 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2617 U8 NumHotSpares; /* 0x08 */ 2618 U8 NumPhysDisks; /* 0x09 */ 2619 U8 NumVolumes; /* 0x0A */ 2620 U8 ConfigNum; /* 0x0B */ 2621 U32 Flags; /* 0x0C */ 2622 U8 ConfigGUID[24]; /* 0x10 */ 2623 U32 Reserved1; /* 0x28 */ 2624 U8 NumElements; /* 0x2C */ 2625 U8 Reserved2; /* 0x2D */ 2626 U16 Reserved3; /* 0x2E */ 2627 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */ 2628 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 2629 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 2630 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t; 2631 2632 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 2633 2634 /* values for RAID Configuration Page 0 Flags field */ 2635 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 2636 2637 /**************************************************************************** 2638 * Driver Persistent Mapping Config Pages 2639 ****************************************************************************/ 2640 2641 /* Driver Persistent Mapping Page 0 */ 2642 2643 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY 2644 { 2645 U64 PhysicalIdentifier; /* 0x00 */ 2646 U16 MappingInformation; /* 0x08 */ 2647 U16 DeviceIndex; /* 0x0A */ 2648 U32 PhysicalBitsMapping; /* 0x0C */ 2649 U32 Reserved1; /* 0x10 */ 2650 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 2651 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 2652 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t; 2653 2654 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 2655 { 2656 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2657 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */ 2658 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 2659 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 2660 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t; 2661 2662 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 2663 2664 /* values for Driver Persistent Mapping Page 0 MappingInformation field */ 2665 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 2666 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 2667 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 2668 2669 /**************************************************************************** 2670 * Ethernet Config Pages 2671 ****************************************************************************/ 2672 2673 /* Ethernet Page 0 */ 2674 2675 /* IP address (union of IPv4 and IPv6) */ 2676 typedef union _MPI2_ETHERNET_IP_ADDR 2677 { 2678 U32 IPv4Addr; 2679 U32 IPv6Addr[4]; 2680 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR, 2681 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t; 2682 2683 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 2684 2685 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 2686 { 2687 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2688 U8 NumInterfaces; /* 0x08 */ 2689 U8 Reserved0; /* 0x09 */ 2690 U16 Reserved1; /* 0x0A */ 2691 U32 Status; /* 0x0C */ 2692 U8 MediaState; /* 0x10 */ 2693 U8 Reserved2; /* 0x11 */ 2694 U16 Reserved3; /* 0x12 */ 2695 U8 MacAddress[6]; /* 0x14 */ 2696 U8 Reserved4; /* 0x1A */ 2697 U8 Reserved5; /* 0x1B */ 2698 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */ 2699 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */ 2700 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */ 2701 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */ 2702 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */ 2703 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */ 2704 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 2705 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 2706 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t; 2707 2708 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 2709 2710 /* values for Ethernet Page 0 Status field */ 2711 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 2712 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 2713 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 2714 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 2715 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 2716 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 2717 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 2718 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 2719 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 2720 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 2721 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 2722 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 2723 2724 /* values for Ethernet Page 0 MediaState field */ 2725 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 2726 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 2727 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 2728 2729 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 2730 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 2731 #define MPI2_ETHPG0_MS_10MBIT (0x01) 2732 #define MPI2_ETHPG0_MS_100MBIT (0x02) 2733 #define MPI2_ETHPG0_MS_1GBIT (0x03) 2734 2735 /* Ethernet Page 1 */ 2736 2737 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 2738 { 2739 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2740 U32 Reserved0; /* 0x08 */ 2741 U32 Flags; /* 0x0C */ 2742 U8 MediaState; /* 0x10 */ 2743 U8 Reserved1; /* 0x11 */ 2744 U16 Reserved2; /* 0x12 */ 2745 U8 MacAddress[6]; /* 0x14 */ 2746 U8 Reserved3; /* 0x1A */ 2747 U8 Reserved4; /* 0x1B */ 2748 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */ 2749 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */ 2750 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */ 2751 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */ 2752 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */ 2753 U32 Reserved5; /* 0x6C */ 2754 U32 Reserved6; /* 0x70 */ 2755 U32 Reserved7; /* 0x74 */ 2756 U32 Reserved8; /* 0x78 */ 2757 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 2758 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 2759 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t; 2760 2761 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 2762 2763 /* values for Ethernet Page 1 Flags field */ 2764 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 2765 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 2766 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 2767 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 2768 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 2769 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 2770 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 2771 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 2772 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 2773 2774 /* values for Ethernet Page 1 MediaState field */ 2775 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 2776 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 2777 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 2778 2779 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 2780 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 2781 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 2782 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 2783 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 2784 2785 /**************************************************************************** 2786 * Extended Manufacturing Config Pages 2787 ****************************************************************************/ 2788 2789 /* 2790 * Generic structure to use for product-specific extended manufacturing pages 2791 * (currently Extended Manufacturing Page 40 through Extended Manufacturing 2792 * Page 60). 2793 */ 2794 2795 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS 2796 { 2797 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2798 U32 ProductSpecificInfo; /* 0x08 */ 2799 } MPI2_CONFIG_PAGE_EXT_MAN_PS, 2800 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 2801 Mpi2ExtManufacturingPagePS_t, MPI2_POINTER pMpi2ExtManufacturingPagePS_t; 2802 2803 /* PageVersion should be provided by product-specific code */ 2804 2805 #endif 2806