1 /*- 2 * Copyright (c) 2011, 2012 LSI Corp. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * LSI MPT-Fusion Host Adapter FreeBSD 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * Copyright (c) 2000-2012 LSI Corporation. 33 * 34 * 35 * Name: mpi2_cnfg.h 36 * Title: MPI Configuration messages and pages 37 * Creation Date: November 10, 2006 38 * 39 * mpi2_cnfg.h Version: 02.00.17 40 * 41 * Version History 42 * --------------- 43 * 44 * Date Version Description 45 * -------- -------- ------------------------------------------------------ 46 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 47 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 48 * Added Manufacturing Page 11. 49 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 50 * define. 51 * 06-26-07 02.00.02 Adding generic structure for product-specific 52 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 53 * Rework of BIOS Page 2 configuration page. 54 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 55 * forms. 56 * Added configuration pages IOC Page 8 and Driver 57 * Persistent Mapping Page 0. 58 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 59 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 60 * RAID Physical Disk Pages 0 and 1, RAID Configuration 61 * Page 0). 62 * Added new value for AccessStatus field of SAS Device 63 * Page 0 (_SATA_NEEDS_INITIALIZATION). 64 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 65 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 66 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 67 * NVDATA. 68 * Modified IOC Page 7 to use masks and added field for 69 * SASBroadcastPrimitiveMasks. 70 * Added MPI2_CONFIG_PAGE_BIOS_4. 71 * Added MPI2_CONFIG_PAGE_LOG_0. 72 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 73 * Added SAS Device IDs. 74 * Updated Integrated RAID configuration pages including 75 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 76 * Page 0. 77 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 78 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 79 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 80 * Added missing MaxNumRoutedSasAddresses field to 81 * MPI2_CONFIG_PAGE_EXPANDER_0. 82 * Added SAS Port Page 0. 83 * Modified structure layout for 84 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 85 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 86 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 87 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 88 * to 0x000000FF. 89 * Added two new values for the Physical Disk Coercion Size 90 * bits in the Flags field of Manufacturing Page 4. 91 * Added product-specific Manufacturing pages 16 to 31. 92 * Modified Flags bits for controlling write cache on SATA 93 * drives in IO Unit Page 1. 94 * Added new bit to AdditionalControlFlags of SAS IO Unit 95 * Page 1 to control Invalid Topology Correction. 96 * Added additional defines for RAID Volume Page 0 97 * VolumeStatusFlags field. 98 * Modified meaning of RAID Volume Page 0 VolumeSettings 99 * define for auto-configure of hot-swap drives. 100 * Added SupportedPhysDisks field to RAID Volume Page 1 and 101 * added related defines. 102 * Added PhysDiskAttributes field (and related defines) to 103 * RAID Physical Disk Page 0. 104 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 105 * Added three new DiscoveryStatus bits for SAS IO Unit 106 * Page 0 and SAS Expander Page 0. 107 * Removed multiplexing information from SAS IO Unit pages. 108 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 109 * Removed Zone Address Resolved bit from PhyInfo and from 110 * Expander Page 0 Flags field. 111 * Added two new AccessStatus values to SAS Device Page 0 112 * for indicating routing problems. Added 3 reserved words 113 * to this page. 114 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 115 * Inserted missing reserved field into structure for IOC 116 * Page 6. 117 * Added more pending task bits to RAID Volume Page 0 118 * VolumeStatusFlags defines. 119 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 120 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 121 * and SAS Expander Page 0 to flag a downstream initiator 122 * when in simplified routing mode. 123 * Removed SATA Init Failure defines for DiscoveryStatus 124 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 125 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 126 * Added PortGroups, DmaGroup, and ControlGroup fields to 127 * SAS Device Page 0. 128 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 129 * Unit Page 6. 130 * Added expander reduced functionality data to SAS 131 * Expander Page 0. 132 * Added SAS PHY Page 2 and SAS PHY Page 3. 133 * 07-30-09 02.00.12 Added IO Unit Page 7. 134 * Added new device ids. 135 * Added SAS IO Unit Page 5. 136 * Added partial and slumber power management capable flags 137 * to SAS Device Page 0 Flags field. 138 * Added PhyInfo defines for power condition. 139 * Added Ethernet configuration pages. 140 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 141 * Added SAS PHY Page 4 structure and defines. 142 * 02-10-10 02.00.14 Modified the comments for the configuration page 143 * structures that contain an array of data. The host 144 * should use the "count" field in the page data (e.g. the 145 * NumPhys field) to determine the number of valid elements 146 * in the array. 147 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 148 * Added PowerManagementCapabilities to IO Unit Page 7. 149 * Added PortWidthModGroup field to 150 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 151 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 152 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 153 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 154 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 155 * define. 156 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 157 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 158 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 159 * defines. 160 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 161 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 162 * the Pinout field. 163 * Added BoardTemperature and BoardTemperatureUnits fields 164 * to MPI2_CONFIG_PAGE_IO_UNIT_7. 165 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 166 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 167 * -------------------------------------------------------------------------- 168 */ 169 170 #ifndef MPI2_CNFG_H 171 #define MPI2_CNFG_H 172 173 /***************************************************************************** 174 * Configuration Page Header and defines 175 *****************************************************************************/ 176 177 /* Config Page Header */ 178 typedef struct _MPI2_CONFIG_PAGE_HEADER 179 { 180 U8 PageVersion; /* 0x00 */ 181 U8 PageLength; /* 0x01 */ 182 U8 PageNumber; /* 0x02 */ 183 U8 PageType; /* 0x03 */ 184 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER, 185 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t; 186 187 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION 188 { 189 MPI2_CONFIG_PAGE_HEADER Struct; 190 U8 Bytes[4]; 191 U16 Word16[2]; 192 U32 Word32; 193 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 194 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion; 195 196 /* Extended Config Page Header */ 197 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER 198 { 199 U8 PageVersion; /* 0x00 */ 200 U8 Reserved1; /* 0x01 */ 201 U8 PageNumber; /* 0x02 */ 202 U8 PageType; /* 0x03 */ 203 U16 ExtPageLength; /* 0x04 */ 204 U8 ExtPageType; /* 0x06 */ 205 U8 Reserved2; /* 0x07 */ 206 } MPI2_CONFIG_EXTENDED_PAGE_HEADER, 207 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 208 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t; 209 210 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION 211 { 212 MPI2_CONFIG_PAGE_HEADER Struct; 213 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 214 U8 Bytes[8]; 215 U16 Word16[4]; 216 U32 Word32[2]; 217 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 218 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion; 219 220 221 /* PageType field values */ 222 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 223 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 224 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 225 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 226 227 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 228 #define MPI2_CONFIG_PAGETYPE_IOC (0x01) 229 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 230 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 231 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 232 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 233 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 234 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 235 236 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 237 238 239 /* ExtPageType field values */ 240 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 241 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 242 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 243 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 244 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 245 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 246 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 247 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 248 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 249 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 250 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 251 252 253 /***************************************************************************** 254 * PageAddress defines 255 *****************************************************************************/ 256 257 /* RAID Volume PageAddress format */ 258 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 259 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 260 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 261 262 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 263 264 265 /* RAID Physical Disk PageAddress format */ 266 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 267 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 268 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 269 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 270 271 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 272 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 273 274 275 /* SAS Expander PageAddress format */ 276 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 277 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 278 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 279 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 280 281 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 282 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 283 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 284 285 286 /* SAS Device PageAddress format */ 287 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 288 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 289 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 290 291 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 292 293 294 /* SAS PHY PageAddress format */ 295 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 296 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 297 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 298 299 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 300 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 301 302 303 /* SAS Port PageAddress format */ 304 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 305 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 306 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 307 308 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 309 310 311 /* SAS Enclosure PageAddress format */ 312 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 313 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 314 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 315 316 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 317 318 319 /* RAID Configuration PageAddress format */ 320 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 321 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 322 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 323 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 324 325 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 326 327 328 /* Driver Persistent Mapping PageAddress format */ 329 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 330 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 331 332 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 333 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 334 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 335 336 337 /* Ethernet PageAddress format */ 338 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 339 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 340 341 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 342 343 344 345 /**************************************************************************** 346 * Configuration messages 347 ****************************************************************************/ 348 349 /* Configuration Request Message */ 350 typedef struct _MPI2_CONFIG_REQUEST 351 { 352 U8 Action; /* 0x00 */ 353 U8 SGLFlags; /* 0x01 */ 354 U8 ChainOffset; /* 0x02 */ 355 U8 Function; /* 0x03 */ 356 U16 ExtPageLength; /* 0x04 */ 357 U8 ExtPageType; /* 0x06 */ 358 U8 MsgFlags; /* 0x07 */ 359 U8 VP_ID; /* 0x08 */ 360 U8 VF_ID; /* 0x09 */ 361 U16 Reserved1; /* 0x0A */ 362 U32 Reserved2; /* 0x0C */ 363 U32 Reserved3; /* 0x10 */ 364 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 365 U32 PageAddress; /* 0x18 */ 366 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */ 367 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST, 368 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t; 369 370 /* values for the Action field */ 371 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 372 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 373 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 374 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 375 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 376 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 377 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 378 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 379 380 /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 381 382 383 /* Config Reply Message */ 384 typedef struct _MPI2_CONFIG_REPLY 385 { 386 U8 Action; /* 0x00 */ 387 U8 SGLFlags; /* 0x01 */ 388 U8 MsgLength; /* 0x02 */ 389 U8 Function; /* 0x03 */ 390 U16 ExtPageLength; /* 0x04 */ 391 U8 ExtPageType; /* 0x06 */ 392 U8 MsgFlags; /* 0x07 */ 393 U8 VP_ID; /* 0x08 */ 394 U8 VF_ID; /* 0x09 */ 395 U16 Reserved1; /* 0x0A */ 396 U16 Reserved2; /* 0x0C */ 397 U16 IOCStatus; /* 0x0E */ 398 U32 IOCLogInfo; /* 0x10 */ 399 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 400 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY, 401 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t; 402 403 404 405 /***************************************************************************** 406 * 407 * C o n f i g u r a t i o n P a g e s 408 * 409 *****************************************************************************/ 410 411 /**************************************************************************** 412 * Manufacturing Config pages 413 ****************************************************************************/ 414 415 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 416 417 /* SAS */ 418 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 419 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 420 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 421 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 422 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 423 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 424 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 425 426 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 427 428 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 429 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 430 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 431 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 432 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 433 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 434 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 435 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 436 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 437 438 439 440 441 /* Manufacturing Page 0 */ 442 443 typedef struct _MPI2_CONFIG_PAGE_MAN_0 444 { 445 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 446 U8 ChipName[16]; /* 0x04 */ 447 U8 ChipRevision[8]; /* 0x14 */ 448 U8 BoardName[16]; /* 0x1C */ 449 U8 BoardAssembly[16]; /* 0x2C */ 450 U8 BoardTracerNumber[16]; /* 0x3C */ 451 } MPI2_CONFIG_PAGE_MAN_0, 452 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0, 453 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t; 454 455 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 456 457 458 /* Manufacturing Page 1 */ 459 460 typedef struct _MPI2_CONFIG_PAGE_MAN_1 461 { 462 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 463 U8 VPD[256]; /* 0x04 */ 464 } MPI2_CONFIG_PAGE_MAN_1, 465 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1, 466 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t; 467 468 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 469 470 471 typedef struct _MPI2_CHIP_REVISION_ID 472 { 473 U16 DeviceID; /* 0x00 */ 474 U8 PCIRevisionID; /* 0x02 */ 475 U8 Reserved; /* 0x03 */ 476 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID, 477 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t; 478 479 480 /* Manufacturing Page 2 */ 481 482 /* 483 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 484 * one and check Header.PageLength at runtime. 485 */ 486 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 487 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 488 #endif 489 490 typedef struct _MPI2_CONFIG_PAGE_MAN_2 491 { 492 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 493 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 494 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */ 495 } MPI2_CONFIG_PAGE_MAN_2, 496 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2, 497 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t; 498 499 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 500 501 502 /* Manufacturing Page 3 */ 503 504 /* 505 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 506 * one and check Header.PageLength at runtime. 507 */ 508 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS 509 #define MPI2_MAN_PAGE_3_INFO_WORDS (1) 510 #endif 511 512 typedef struct _MPI2_CONFIG_PAGE_MAN_3 513 { 514 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 515 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 516 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */ 517 } MPI2_CONFIG_PAGE_MAN_3, 518 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3, 519 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t; 520 521 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 522 523 524 /* Manufacturing Page 4 */ 525 526 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS 527 { 528 U8 PowerSaveFlags; /* 0x00 */ 529 U8 InternalOperationsSleepTime; /* 0x01 */ 530 U8 InternalOperationsRunTime; /* 0x02 */ 531 U8 HostIdleTime; /* 0x03 */ 532 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 533 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 534 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t; 535 536 /* defines for the PowerSaveFlags field */ 537 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 538 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 539 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 540 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 541 542 typedef struct _MPI2_CONFIG_PAGE_MAN_4 543 { 544 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 545 U32 Reserved1; /* 0x04 */ 546 U32 Flags; /* 0x08 */ 547 U8 InquirySize; /* 0x0C */ 548 U8 Reserved2; /* 0x0D */ 549 U16 Reserved3; /* 0x0E */ 550 U8 InquiryData[56]; /* 0x10 */ 551 U32 RAID0VolumeSettings; /* 0x48 */ 552 U32 RAID1EVolumeSettings; /* 0x4C */ 553 U32 RAID1VolumeSettings; /* 0x50 */ 554 U32 RAID10VolumeSettings; /* 0x54 */ 555 U32 Reserved4; /* 0x58 */ 556 U32 Reserved5; /* 0x5C */ 557 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */ 558 U8 MaxOCEDisks; /* 0x64 */ 559 U8 ResyncRate; /* 0x65 */ 560 U16 DataScrubDuration; /* 0x66 */ 561 U8 MaxHotSpares; /* 0x68 */ 562 U8 MaxPhysDisksPerVol; /* 0x69 */ 563 U8 MaxPhysDisks; /* 0x6A */ 564 U8 MaxVolumes; /* 0x6B */ 565 } MPI2_CONFIG_PAGE_MAN_4, 566 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4, 567 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t; 568 569 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 570 571 /* Manufacturing Page 4 Flags field */ 572 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 573 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 574 575 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 576 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 577 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 578 579 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 580 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 581 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 582 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 583 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 584 585 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 586 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 587 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 588 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 589 590 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 591 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 592 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 593 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 594 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 595 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 596 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 597 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 598 599 600 /* Manufacturing Page 5 */ 601 602 /* 603 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 604 * one and check the value returned for NumPhys at runtime. 605 */ 606 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 607 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 608 #endif 609 610 typedef struct _MPI2_MANUFACTURING5_ENTRY 611 { 612 U64 WWID; /* 0x00 */ 613 U64 DeviceName; /* 0x08 */ 614 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY, 615 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t; 616 617 typedef struct _MPI2_CONFIG_PAGE_MAN_5 618 { 619 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 620 U8 NumPhys; /* 0x04 */ 621 U8 Reserved1; /* 0x05 */ 622 U16 Reserved2; /* 0x06 */ 623 U32 Reserved3; /* 0x08 */ 624 U32 Reserved4; /* 0x0C */ 625 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */ 626 } MPI2_CONFIG_PAGE_MAN_5, 627 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5, 628 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t; 629 630 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 631 632 633 /* Manufacturing Page 6 */ 634 635 typedef struct _MPI2_CONFIG_PAGE_MAN_6 636 { 637 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 638 U32 ProductSpecificInfo;/* 0x04 */ 639 } MPI2_CONFIG_PAGE_MAN_6, 640 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6, 641 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t; 642 643 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 644 645 646 /* Manufacturing Page 7 */ 647 648 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO 649 { 650 U32 Pinout; /* 0x00 */ 651 U8 Connector[16]; /* 0x04 */ 652 U8 Location; /* 0x14 */ 653 U8 ReceptacleID; /* 0x15 */ 654 U16 Slot; /* 0x16 */ 655 U32 Reserved2; /* 0x18 */ 656 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 657 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t; 658 659 /* defines for the Pinout field */ 660 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 661 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 662 663 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 664 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 665 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 666 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 667 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 668 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 669 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 670 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 671 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 672 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 673 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 674 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 675 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 676 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 677 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 678 679 /* defines for the Location field */ 680 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 681 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 682 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 683 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 684 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 685 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 686 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 687 688 /* 689 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 690 * one and check the value returned for NumPhys at runtime. 691 */ 692 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 693 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 694 #endif 695 696 typedef struct _MPI2_CONFIG_PAGE_MAN_7 697 { 698 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 699 U32 Reserved1; /* 0x04 */ 700 U32 Reserved2; /* 0x08 */ 701 U32 Flags; /* 0x0C */ 702 U8 EnclosureName[16]; /* 0x10 */ 703 U8 NumPhys; /* 0x20 */ 704 U8 Reserved3; /* 0x21 */ 705 U16 Reserved4; /* 0x22 */ 706 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */ 707 } MPI2_CONFIG_PAGE_MAN_7, 708 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7, 709 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t; 710 711 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 712 713 /* defines for the Flags field */ 714 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 715 716 717 /* 718 * Generic structure to use for product-specific manufacturing pages 719 * (currently Manufacturing Page 8 through Manufacturing Page 31). 720 */ 721 722 typedef struct _MPI2_CONFIG_PAGE_MAN_PS 723 { 724 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 725 U32 ProductSpecificInfo;/* 0x04 */ 726 } MPI2_CONFIG_PAGE_MAN_PS, 727 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS, 728 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t; 729 730 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 731 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 732 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 733 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 734 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 735 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 736 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 737 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 738 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 739 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 740 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 741 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 742 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 743 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 744 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 745 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 746 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 747 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 748 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 749 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 750 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 751 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 752 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 753 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 754 755 756 /**************************************************************************** 757 * IO Unit Config Pages 758 ****************************************************************************/ 759 760 /* IO Unit Page 0 */ 761 762 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 763 { 764 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 765 U64 UniqueValue; /* 0x04 */ 766 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */ 767 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */ 768 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 769 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t; 770 771 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 772 773 774 /* IO Unit Page 1 */ 775 776 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 777 { 778 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 779 U32 Flags; /* 0x04 */ 780 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 781 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t; 782 783 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 784 785 /* IO Unit Page 1 Flags defines */ 786 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 787 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 788 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 789 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 790 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 791 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 792 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 793 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 794 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 795 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 796 797 798 /* IO Unit Page 3 */ 799 800 /* 801 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 802 * one and check the value returned for GPIOCount at runtime. 803 */ 804 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 805 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 806 #endif 807 808 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 809 { 810 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 811 U8 GPIOCount; /* 0x04 */ 812 U8 Reserved1; /* 0x05 */ 813 U16 Reserved2; /* 0x06 */ 814 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */ 815 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 816 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t; 817 818 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 819 820 /* defines for IO Unit Page 3 GPIOVal field */ 821 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 822 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 823 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 824 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 825 826 827 /* IO Unit Page 5 */ 828 829 /* 830 * Upper layer code (drivers, utilities, etc.) should leave this define set to 831 * one and check the value returned for NumDmaEngines at runtime. 832 */ 833 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 834 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 835 #endif 836 837 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 838 { 839 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 840 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */ 841 U64 RaidAcceleratorBufferSize; /* 0x0C */ 842 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */ 843 U8 RAControlSize; /* 0x1C */ 844 U8 NumDmaEngines; /* 0x1D */ 845 U8 RAMinControlSize; /* 0x1E */ 846 U8 RAMaxControlSize; /* 0x1F */ 847 U32 Reserved1; /* 0x20 */ 848 U32 Reserved2; /* 0x24 */ 849 U32 Reserved3; /* 0x28 */ 850 U32 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */ 851 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 852 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t; 853 854 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 855 856 /* defines for IO Unit Page 5 DmaEngineCapabilities field */ 857 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00) 858 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 859 860 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 861 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 862 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 863 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 864 865 866 /* IO Unit Page 6 */ 867 868 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 869 { 870 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 871 U16 Flags; /* 0x04 */ 872 U8 RAHostControlSize; /* 0x06 */ 873 U8 Reserved0; /* 0x07 */ 874 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */ 875 U32 Reserved1; /* 0x10 */ 876 U32 Reserved2; /* 0x14 */ 877 U32 Reserved3; /* 0x18 */ 878 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 879 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t; 880 881 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 882 883 /* defines for IO Unit Page 6 Flags field */ 884 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 885 886 887 /* IO Unit Page 7 */ 888 889 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 890 { 891 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 892 U16 Reserved1; /* 0x04 */ 893 U8 PCIeWidth; /* 0x06 */ 894 U8 PCIeSpeed; /* 0x07 */ 895 U32 ProcessorState; /* 0x08 */ 896 U32 PowerManagementCapabilities; /* 0x0C */ 897 U16 IOCTemperature; /* 0x10 */ 898 U8 IOCTemperatureUnits; /* 0x12 */ 899 U8 IOCSpeed; /* 0x13 */ 900 U16 BoardTemperature; /* 0x14 */ 901 U8 BoardTemperatureUnits; /* 0x16 */ 902 U8 Reserved3; /* 0x17 */ 903 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 904 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t; 905 906 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x02) 907 908 /* defines for IO Unit Page 7 PCIeWidth field */ 909 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 910 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 911 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 912 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 913 914 /* defines for IO Unit Page 7 PCIeSpeed field */ 915 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 916 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 917 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 918 919 /* defines for IO Unit Page 7 ProcessorState field */ 920 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 921 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 922 923 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 924 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 925 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 926 927 /* defines for IO Unit Page 7 PowerManagementCapabilities field */ 928 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 929 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 930 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 931 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) 932 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) 933 934 /* defines for IO Unit Page 7 IOCTemperatureUnits field */ 935 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 936 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 937 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 938 939 /* defines for IO Unit Page 7 IOCSpeed field */ 940 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 941 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 942 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 943 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 944 945 /* defines for IO Unit Page 7 BoardTemperatureUnits field */ 946 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 947 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 948 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 949 950 951 952 /**************************************************************************** 953 * IOC Config Pages 954 ****************************************************************************/ 955 956 /* IOC Page 0 */ 957 958 typedef struct _MPI2_CONFIG_PAGE_IOC_0 959 { 960 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 961 U32 Reserved1; /* 0x04 */ 962 U32 Reserved2; /* 0x08 */ 963 U16 VendorID; /* 0x0C */ 964 U16 DeviceID; /* 0x0E */ 965 U8 RevisionID; /* 0x10 */ 966 U8 Reserved3; /* 0x11 */ 967 U16 Reserved4; /* 0x12 */ 968 U32 ClassCode; /* 0x14 */ 969 U16 SubsystemVendorID; /* 0x18 */ 970 U16 SubsystemID; /* 0x1A */ 971 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0, 972 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t; 973 974 #define MPI2_IOCPAGE0_PAGEVERSION (0x02) 975 976 977 /* IOC Page 1 */ 978 979 typedef struct _MPI2_CONFIG_PAGE_IOC_1 980 { 981 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 982 U32 Flags; /* 0x04 */ 983 U32 CoalescingTimeout; /* 0x08 */ 984 U8 CoalescingDepth; /* 0x0C */ 985 U8 PCISlotNum; /* 0x0D */ 986 U8 PCIBusNum; /* 0x0E */ 987 U8 PCIDomainSegment; /* 0x0F */ 988 U32 Reserved1; /* 0x10 */ 989 U32 Reserved2; /* 0x14 */ 990 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1, 991 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t; 992 993 #define MPI2_IOCPAGE1_PAGEVERSION (0x05) 994 995 /* defines for IOC Page 1 Flags field */ 996 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 997 998 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 999 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 1000 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 1001 1002 /* IOC Page 6 */ 1003 1004 typedef struct _MPI2_CONFIG_PAGE_IOC_6 1005 { 1006 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1007 U32 CapabilitiesFlags; /* 0x04 */ 1008 U8 MaxDrivesRAID0; /* 0x08 */ 1009 U8 MaxDrivesRAID1; /* 0x09 */ 1010 U8 MaxDrivesRAID1E; /* 0x0A */ 1011 U8 MaxDrivesRAID10; /* 0x0B */ 1012 U8 MinDrivesRAID0; /* 0x0C */ 1013 U8 MinDrivesRAID1; /* 0x0D */ 1014 U8 MinDrivesRAID1E; /* 0x0E */ 1015 U8 MinDrivesRAID10; /* 0x0F */ 1016 U32 Reserved1; /* 0x10 */ 1017 U8 MaxGlobalHotSpares; /* 0x14 */ 1018 U8 MaxPhysDisks; /* 0x15 */ 1019 U8 MaxVolumes; /* 0x16 */ 1020 U8 MaxConfigs; /* 0x17 */ 1021 U8 MaxOCEDisks; /* 0x18 */ 1022 U8 Reserved2; /* 0x19 */ 1023 U16 Reserved3; /* 0x1A */ 1024 U32 SupportedStripeSizeMapRAID0; /* 0x1C */ 1025 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */ 1026 U32 SupportedStripeSizeMapRAID10; /* 0x24 */ 1027 U32 Reserved4; /* 0x28 */ 1028 U32 Reserved5; /* 0x2C */ 1029 U16 DefaultMetadataSize; /* 0x30 */ 1030 U16 Reserved6; /* 0x32 */ 1031 U16 MaxBadBlockTableEntries; /* 0x34 */ 1032 U16 Reserved7; /* 0x36 */ 1033 U32 IRNvsramVersion; /* 0x38 */ 1034 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6, 1035 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t; 1036 1037 #define MPI2_IOCPAGE6_PAGEVERSION (0x04) 1038 1039 /* defines for IOC Page 6 CapabilitiesFlags */ 1040 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1041 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1042 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1043 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1044 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1045 1046 1047 /* IOC Page 7 */ 1048 1049 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1050 1051 typedef struct _MPI2_CONFIG_PAGE_IOC_7 1052 { 1053 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1054 U32 Reserved1; /* 0x04 */ 1055 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */ 1056 U16 SASBroadcastPrimitiveMasks; /* 0x18 */ 1057 U16 Reserved2; /* 0x1A */ 1058 U32 Reserved3; /* 0x1C */ 1059 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7, 1060 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t; 1061 1062 #define MPI2_IOCPAGE7_PAGEVERSION (0x01) 1063 1064 1065 /* IOC Page 8 */ 1066 1067 typedef struct _MPI2_CONFIG_PAGE_IOC_8 1068 { 1069 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1070 U8 NumDevsPerEnclosure; /* 0x04 */ 1071 U8 Reserved1; /* 0x05 */ 1072 U16 Reserved2; /* 0x06 */ 1073 U16 MaxPersistentEntries; /* 0x08 */ 1074 U16 MaxNumPhysicalMappedIDs; /* 0x0A */ 1075 U16 Flags; /* 0x0C */ 1076 U16 Reserved3; /* 0x0E */ 1077 U16 IRVolumeMappingFlags; /* 0x10 */ 1078 U16 Reserved4; /* 0x12 */ 1079 U32 Reserved5; /* 0x14 */ 1080 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8, 1081 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t; 1082 1083 #define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1084 1085 /* defines for IOC Page 8 Flags field */ 1086 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1087 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1088 1089 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1090 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1091 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1092 1093 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1094 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1095 1096 /* defines for IOC Page 8 IRVolumeMappingFlags */ 1097 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1098 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1099 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1100 1101 1102 /**************************************************************************** 1103 * BIOS Config Pages 1104 ****************************************************************************/ 1105 1106 /* BIOS Page 1 */ 1107 1108 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 1109 { 1110 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1111 U32 BiosOptions; /* 0x04 */ 1112 U32 IOCSettings; /* 0x08 */ 1113 U32 Reserved1; /* 0x0C */ 1114 U32 DeviceSettings; /* 0x10 */ 1115 U16 NumberOfDevices; /* 0x14 */ 1116 U16 Reserved2; /* 0x16 */ 1117 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */ 1118 U16 IOTimeoutSequential; /* 0x1A */ 1119 U16 IOTimeoutOther; /* 0x1C */ 1120 U16 IOTimeoutBlockDevicesRM; /* 0x1E */ 1121 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1, 1122 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t; 1123 1124 #define MPI2_BIOSPAGE1_PAGEVERSION (0x04) 1125 1126 /* values for BIOS Page 1 BiosOptions field */ 1127 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1128 1129 /* values for BIOS Page 1 IOCSettings field */ 1130 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1131 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1132 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1133 1134 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1135 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1136 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1137 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1138 1139 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1140 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1141 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1142 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1143 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1144 1145 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1146 1147 /* values for BIOS Page 1 DeviceSettings field */ 1148 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1149 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1150 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1151 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1152 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1153 1154 1155 /* BIOS Page 2 */ 1156 1157 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER 1158 { 1159 U32 Reserved1; /* 0x00 */ 1160 U32 Reserved2; /* 0x04 */ 1161 U32 Reserved3; /* 0x08 */ 1162 U32 Reserved4; /* 0x0C */ 1163 U32 Reserved5; /* 0x10 */ 1164 U32 Reserved6; /* 0x14 */ 1165 } MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1166 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1167 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t; 1168 1169 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID 1170 { 1171 U64 SASAddress; /* 0x00 */ 1172 U8 LUN[8]; /* 0x08 */ 1173 U32 Reserved1; /* 0x10 */ 1174 U32 Reserved2; /* 0x14 */ 1175 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1176 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t; 1177 1178 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT 1179 { 1180 U64 EnclosureLogicalID; /* 0x00 */ 1181 U32 Reserved1; /* 0x08 */ 1182 U32 Reserved2; /* 0x0C */ 1183 U16 SlotNumber; /* 0x10 */ 1184 U16 Reserved3; /* 0x12 */ 1185 U32 Reserved4; /* 0x14 */ 1186 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1187 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1188 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t; 1189 1190 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME 1191 { 1192 U64 DeviceName; /* 0x00 */ 1193 U8 LUN[8]; /* 0x08 */ 1194 U32 Reserved1; /* 0x10 */ 1195 U32 Reserved2; /* 0x14 */ 1196 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1197 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t; 1198 1199 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE 1200 { 1201 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1202 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1203 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1204 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1205 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1206 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t; 1207 1208 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 1209 { 1210 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1211 U32 Reserved1; /* 0x04 */ 1212 U32 Reserved2; /* 0x08 */ 1213 U32 Reserved3; /* 0x0C */ 1214 U32 Reserved4; /* 0x10 */ 1215 U32 Reserved5; /* 0x14 */ 1216 U32 Reserved6; /* 0x18 */ 1217 U8 ReqBootDeviceForm; /* 0x1C */ 1218 U8 Reserved7; /* 0x1D */ 1219 U16 Reserved8; /* 0x1E */ 1220 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */ 1221 U8 ReqAltBootDeviceForm; /* 0x38 */ 1222 U8 Reserved9; /* 0x39 */ 1223 U16 Reserved10; /* 0x3A */ 1224 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */ 1225 U8 CurrentBootDeviceForm; /* 0x58 */ 1226 U8 Reserved11; /* 0x59 */ 1227 U16 Reserved12; /* 0x5A */ 1228 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */ 1229 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2, 1230 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t; 1231 1232 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1233 1234 /* values for BIOS Page 2 BootDeviceForm fields */ 1235 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1236 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1237 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1238 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1239 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1240 1241 1242 /* BIOS Page 3 */ 1243 1244 typedef struct _MPI2_ADAPTER_INFO 1245 { 1246 U8 PciBusNumber; /* 0x00 */ 1247 U8 PciDeviceAndFunctionNumber; /* 0x01 */ 1248 U16 AdapterFlags; /* 0x02 */ 1249 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO, 1250 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t; 1251 1252 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1253 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1254 1255 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 1256 { 1257 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1258 U32 GlobalFlags; /* 0x04 */ 1259 U32 BiosVersion; /* 0x08 */ 1260 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */ 1261 U32 Reserved1; /* 0x1C */ 1262 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3, 1263 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t; 1264 1265 #define MPI2_BIOSPAGE3_PAGEVERSION (0x00) 1266 1267 /* values for BIOS Page 3 GlobalFlags */ 1268 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1269 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1270 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1271 1272 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1273 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1274 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1275 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1276 1277 1278 /* BIOS Page 4 */ 1279 1280 /* 1281 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1282 * one and check the value returned for NumPhys at runtime. 1283 */ 1284 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1285 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1286 #endif 1287 1288 typedef struct _MPI2_BIOS4_ENTRY 1289 { 1290 U64 ReassignmentWWID; /* 0x00 */ 1291 U64 ReassignmentDeviceName; /* 0x08 */ 1292 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY, 1293 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t; 1294 1295 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 1296 { 1297 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1298 U8 NumPhys; /* 0x04 */ 1299 U8 Reserved1; /* 0x05 */ 1300 U16 Reserved2; /* 0x06 */ 1301 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */ 1302 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4, 1303 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t; 1304 1305 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1306 1307 1308 /**************************************************************************** 1309 * RAID Volume Config Pages 1310 ****************************************************************************/ 1311 1312 /* RAID Volume Page 0 */ 1313 1314 typedef struct _MPI2_RAIDVOL0_PHYS_DISK 1315 { 1316 U8 RAIDSetNum; /* 0x00 */ 1317 U8 PhysDiskMap; /* 0x01 */ 1318 U8 PhysDiskNum; /* 0x02 */ 1319 U8 Reserved; /* 0x03 */ 1320 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK, 1321 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t; 1322 1323 /* defines for the PhysDiskMap field */ 1324 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1325 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1326 1327 typedef struct _MPI2_RAIDVOL0_SETTINGS 1328 { 1329 U16 Settings; /* 0x00 */ 1330 U8 HotSparePool; /* 0x01 */ 1331 U8 Reserved; /* 0x02 */ 1332 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS, 1333 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t; 1334 1335 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1336 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1337 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1338 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1339 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1340 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1341 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1342 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1343 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1344 1345 /* RAID Volume Page 0 VolumeSettings defines */ 1346 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1347 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1348 1349 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1350 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1351 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1352 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1353 1354 /* 1355 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1356 * one and check the value returned for NumPhysDisks at runtime. 1357 */ 1358 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1359 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1360 #endif 1361 1362 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 1363 { 1364 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1365 U16 DevHandle; /* 0x04 */ 1366 U8 VolumeState; /* 0x06 */ 1367 U8 VolumeType; /* 0x07 */ 1368 U32 VolumeStatusFlags; /* 0x08 */ 1369 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */ 1370 U64 MaxLBA; /* 0x10 */ 1371 U32 StripeSize; /* 0x18 */ 1372 U16 BlockSize; /* 0x1C */ 1373 U16 Reserved1; /* 0x1E */ 1374 U8 SupportedPhysDisks; /* 0x20 */ 1375 U8 ResyncRate; /* 0x21 */ 1376 U16 DataScrubDuration; /* 0x22 */ 1377 U8 NumPhysDisks; /* 0x24 */ 1378 U8 Reserved2; /* 0x25 */ 1379 U8 Reserved3; /* 0x26 */ 1380 U8 InactiveStatus; /* 0x27 */ 1381 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */ 1382 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1383 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t; 1384 1385 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1386 1387 /* values for RAID VolumeState */ 1388 #define MPI2_RAID_VOL_STATE_MISSING (0x00) 1389 #define MPI2_RAID_VOL_STATE_FAILED (0x01) 1390 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1391 #define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1392 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1393 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1394 1395 /* values for RAID VolumeType */ 1396 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1397 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1398 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1399 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1400 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1401 1402 /* values for RAID Volume Page 0 VolumeStatusFlags field */ 1403 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1404 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1405 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1406 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1407 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1408 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1409 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1410 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1411 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1412 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1413 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1414 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1415 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1416 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1417 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1418 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1419 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1420 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1421 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1422 1423 /* values for RAID Volume Page 0 SupportedPhysDisks field */ 1424 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1425 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1426 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1427 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1428 1429 /* values for RAID Volume Page 0 InactiveStatus field */ 1430 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1431 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1432 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1433 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1434 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1435 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1436 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1437 1438 1439 /* RAID Volume Page 1 */ 1440 1441 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 1442 { 1443 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1444 U16 DevHandle; /* 0x04 */ 1445 U16 Reserved0; /* 0x06 */ 1446 U8 GUID[24]; /* 0x08 */ 1447 U8 Name[16]; /* 0x20 */ 1448 U64 WWID; /* 0x30 */ 1449 U32 Reserved1; /* 0x38 */ 1450 U32 Reserved2; /* 0x3C */ 1451 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1452 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t; 1453 1454 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1455 1456 1457 /**************************************************************************** 1458 * RAID Physical Disk Config Pages 1459 ****************************************************************************/ 1460 1461 /* RAID Physical Disk Page 0 */ 1462 1463 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS 1464 { 1465 U16 Reserved1; /* 0x00 */ 1466 U8 HotSparePool; /* 0x02 */ 1467 U8 Reserved2; /* 0x03 */ 1468 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1469 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t; 1470 1471 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1472 1473 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA 1474 { 1475 U8 VendorID[8]; /* 0x00 */ 1476 U8 ProductID[16]; /* 0x08 */ 1477 U8 ProductRevLevel[4]; /* 0x18 */ 1478 U8 SerialNum[32]; /* 0x1C */ 1479 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1480 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1481 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t; 1482 1483 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 1484 { 1485 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1486 U16 DevHandle; /* 0x04 */ 1487 U8 Reserved1; /* 0x06 */ 1488 U8 PhysDiskNum; /* 0x07 */ 1489 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */ 1490 U32 Reserved2; /* 0x0C */ 1491 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */ 1492 U32 Reserved3; /* 0x4C */ 1493 U8 PhysDiskState; /* 0x50 */ 1494 U8 OfflineReason; /* 0x51 */ 1495 U8 IncompatibleReason; /* 0x52 */ 1496 U8 PhysDiskAttributes; /* 0x53 */ 1497 U32 PhysDiskStatusFlags; /* 0x54 */ 1498 U64 DeviceMaxLBA; /* 0x58 */ 1499 U64 HostMaxLBA; /* 0x60 */ 1500 U64 CoercedMaxLBA; /* 0x68 */ 1501 U16 BlockSize; /* 0x70 */ 1502 U16 Reserved5; /* 0x72 */ 1503 U32 Reserved6; /* 0x74 */ 1504 } MPI2_CONFIG_PAGE_RD_PDISK_0, 1505 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1506 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t; 1507 1508 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1509 1510 /* PhysDiskState defines */ 1511 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1512 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1513 #define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1514 #define MPI2_RAID_PD_STATE_ONLINE (0x03) 1515 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1516 #define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1517 #define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1518 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1519 1520 /* OfflineReason defines */ 1521 #define MPI2_PHYSDISK0_ONLINE (0x00) 1522 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1523 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1524 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1525 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1526 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1527 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1528 1529 /* IncompatibleReason defines */ 1530 #define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1531 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1532 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1533 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1534 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1535 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1536 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 1537 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1538 1539 /* PhysDiskAttributes defines */ 1540 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 1541 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1542 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1543 1544 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 1545 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1546 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1547 1548 /* PhysDiskStatusFlags defines */ 1549 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1550 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1551 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1552 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1553 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1554 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 1555 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 1556 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 1557 1558 1559 /* RAID Physical Disk Page 1 */ 1560 1561 /* 1562 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1563 * one and check the value returned for NumPhysDiskPaths at runtime. 1564 */ 1565 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 1566 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 1567 #endif 1568 1569 typedef struct _MPI2_RAIDPHYSDISK1_PATH 1570 { 1571 U16 DevHandle; /* 0x00 */ 1572 U16 Reserved1; /* 0x02 */ 1573 U64 WWID; /* 0x04 */ 1574 U64 OwnerWWID; /* 0x0C */ 1575 U8 OwnerIdentifier; /* 0x14 */ 1576 U8 Reserved2; /* 0x15 */ 1577 U16 Flags; /* 0x16 */ 1578 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH, 1579 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t; 1580 1581 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 1582 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 1583 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 1584 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 1585 1586 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 1587 { 1588 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1589 U8 NumPhysDiskPaths; /* 0x04 */ 1590 U8 PhysDiskNum; /* 0x05 */ 1591 U16 Reserved1; /* 0x06 */ 1592 U32 Reserved2; /* 0x08 */ 1593 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */ 1594 } MPI2_CONFIG_PAGE_RD_PDISK_1, 1595 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 1596 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t; 1597 1598 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 1599 1600 1601 /**************************************************************************** 1602 * values for fields used by several types of SAS Config Pages 1603 ****************************************************************************/ 1604 1605 /* values for NegotiatedLinkRates fields */ 1606 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 1607 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 1608 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 1609 /* link rates used for Negotiated Physical and Logical Link Rate */ 1610 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 1611 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 1612 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 1613 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 1614 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 1615 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 1616 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 1617 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 1618 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 1619 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 1620 1621 1622 /* values for AttachedPhyInfo fields */ 1623 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 1624 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 1625 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 1626 1627 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 1628 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 1629 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 1630 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 1631 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 1632 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 1633 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 1634 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 1635 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 1636 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 1637 1638 1639 /* values for PhyInfo fields */ 1640 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 1641 1642 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 1643 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 1644 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 1645 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 1646 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 1647 1648 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 1649 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 1650 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 1651 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 1652 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 1653 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 1654 1655 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 1656 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 1657 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 1658 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 1659 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 1660 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 1661 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 1662 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 1663 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 1664 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 1665 1666 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 1667 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 1668 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 1669 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 1670 1671 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 1672 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 1673 1674 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 1675 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 1676 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 1677 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 1678 1679 1680 /* values for SAS ProgrammedLinkRate fields */ 1681 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 1682 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 1683 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 1684 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 1685 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 1686 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 1687 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 1688 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 1689 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 1690 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 1691 1692 1693 /* values for SAS HwLinkRate fields */ 1694 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 1695 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 1696 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 1697 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 1698 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 1699 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 1700 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 1701 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 1702 1703 1704 1705 /**************************************************************************** 1706 * SAS IO Unit Config Pages 1707 ****************************************************************************/ 1708 1709 /* SAS IO Unit Page 0 */ 1710 1711 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA 1712 { 1713 U8 Port; /* 0x00 */ 1714 U8 PortFlags; /* 0x01 */ 1715 U8 PhyFlags; /* 0x02 */ 1716 U8 NegotiatedLinkRate; /* 0x03 */ 1717 U32 ControllerPhyDeviceInfo;/* 0x04 */ 1718 U16 AttachedDevHandle; /* 0x08 */ 1719 U16 ControllerDevHandle; /* 0x0A */ 1720 U32 DiscoveryStatus; /* 0x0C */ 1721 U32 Reserved; /* 0x10 */ 1722 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 1723 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t; 1724 1725 /* 1726 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1727 * one and check the value returned for NumPhys at runtime. 1728 */ 1729 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX 1730 #define MPI2_SAS_IOUNIT0_PHY_MAX (1) 1731 #endif 1732 1733 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 1734 { 1735 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1736 U32 Reserved1; /* 0x08 */ 1737 U8 NumPhys; /* 0x0C */ 1738 U8 Reserved2; /* 0x0D */ 1739 U16 Reserved3; /* 0x0E */ 1740 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */ 1741 } MPI2_CONFIG_PAGE_SASIOUNIT_0, 1742 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 1743 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t; 1744 1745 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 1746 1747 /* values for SAS IO Unit Page 0 PortFlags */ 1748 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 1749 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 1750 1751 /* values for SAS IO Unit Page 0 PhyFlags */ 1752 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 1753 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 1754 1755 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 1756 1757 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 1758 1759 /* values for SAS IO Unit Page 0 DiscoveryStatus */ 1760 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 1761 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 1762 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 1763 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 1764 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 1765 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 1766 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 1767 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 1768 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 1769 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 1770 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 1771 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 1772 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 1773 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 1774 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 1775 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 1776 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 1777 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 1778 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 1779 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 1780 1781 1782 /* SAS IO Unit Page 1 */ 1783 1784 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA 1785 { 1786 U8 Port; /* 0x00 */ 1787 U8 PortFlags; /* 0x01 */ 1788 U8 PhyFlags; /* 0x02 */ 1789 U8 MaxMinLinkRate; /* 0x03 */ 1790 U32 ControllerPhyDeviceInfo; /* 0x04 */ 1791 U16 MaxTargetPortConnectTime; /* 0x08 */ 1792 U16 Reserved1; /* 0x0A */ 1793 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 1794 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t; 1795 1796 /* 1797 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1798 * one and check the value returned for NumPhys at runtime. 1799 */ 1800 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX 1801 #define MPI2_SAS_IOUNIT1_PHY_MAX (1) 1802 #endif 1803 1804 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 1805 { 1806 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1807 U16 ControlFlags; /* 0x08 */ 1808 U16 SASNarrowMaxQueueDepth; /* 0x0A */ 1809 U16 AdditionalControlFlags; /* 0x0C */ 1810 U16 SASWideMaxQueueDepth; /* 0x0E */ 1811 U8 NumPhys; /* 0x10 */ 1812 U8 SATAMaxQDepth; /* 0x11 */ 1813 U8 ReportDeviceMissingDelay; /* 0x12 */ 1814 U8 IODeviceMissingDelay; /* 0x13 */ 1815 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */ 1816 } MPI2_CONFIG_PAGE_SASIOUNIT_1, 1817 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 1818 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t; 1819 1820 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 1821 1822 /* values for SAS IO Unit Page 1 ControlFlags */ 1823 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 1824 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 1825 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 1826 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 1827 1828 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 1829 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 1830 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 1831 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 1832 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 1833 1834 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 1835 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 1836 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 1837 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 1838 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 1839 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 1840 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 1841 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 1842 1843 /* values for SAS IO Unit Page 1 AdditionalControlFlags */ 1844 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 1845 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 1846 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 1847 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 1848 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 1849 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 1850 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 1851 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 1852 1853 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 1854 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 1855 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 1856 1857 /* values for SAS IO Unit Page 1 PortFlags */ 1858 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 1859 1860 /* values for SAS IO Unit Page 1 PhyFlags */ 1861 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 1862 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 1863 1864 /* values for SAS IO Unit Page 1 MaxMinLinkRate */ 1865 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 1866 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 1867 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 1868 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 1869 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 1870 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 1871 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 1872 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 1873 1874 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 1875 1876 1877 /* SAS IO Unit Page 4 */ 1878 1879 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP 1880 { 1881 U8 MaxTargetSpinup; /* 0x00 */ 1882 U8 SpinupDelay; /* 0x01 */ 1883 U16 Reserved1; /* 0x02 */ 1884 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 1885 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t; 1886 1887 /* 1888 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1889 * one and check the value returned for NumPhys at runtime. 1890 */ 1891 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX 1892 #define MPI2_SAS_IOUNIT4_PHY_MAX (4) 1893 #endif 1894 1895 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 1896 { 1897 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1898 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 1899 U32 Reserved1; /* 0x18 */ 1900 U32 Reserved2; /* 0x1C */ 1901 U32 Reserved3; /* 0x20 */ 1902 U8 BootDeviceWaitTime; /* 0x24 */ 1903 U8 Reserved4; /* 0x25 */ 1904 U16 Reserved5; /* 0x26 */ 1905 U8 NumPhys; /* 0x28 */ 1906 U8 PEInitialSpinupDelay; /* 0x29 */ 1907 U8 PEReplyDelay; /* 0x2A */ 1908 U8 Flags; /* 0x2B */ 1909 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */ 1910 } MPI2_CONFIG_PAGE_SASIOUNIT_4, 1911 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 1912 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t; 1913 1914 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 1915 1916 /* defines for Flags field */ 1917 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 1918 1919 /* defines for PHY field */ 1920 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 1921 1922 1923 /* SAS IO Unit Page 5 */ 1924 1925 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 1926 { 1927 U8 ControlFlags; /* 0x00 */ 1928 U8 PortWidthModGroup; /* 0x01 */ 1929 U16 InactivityTimerExponent; /* 0x02 */ 1930 U8 SATAPartialTimeout; /* 0x04 */ 1931 U8 Reserved2; /* 0x05 */ 1932 U8 SATASlumberTimeout; /* 0x06 */ 1933 U8 Reserved3; /* 0x07 */ 1934 U8 SASPartialTimeout; /* 0x08 */ 1935 U8 Reserved4; /* 0x09 */ 1936 U8 SASSlumberTimeout; /* 0x0A */ 1937 U8 Reserved5; /* 0x0B */ 1938 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 1939 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 1940 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t; 1941 1942 /* defines for ControlFlags field */ 1943 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 1944 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 1945 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 1946 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 1947 1948 /* defines for PortWidthModeGroup field */ 1949 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 1950 1951 /* defines for InactivityTimerExponent field */ 1952 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 1953 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 1954 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 1955 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 1956 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 1957 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 1958 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 1959 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 1960 1961 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 1962 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 1963 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 1964 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 1965 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 1966 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 1967 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 1968 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 1969 1970 /* 1971 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1972 * one and check the value returned for NumPhys at runtime. 1973 */ 1974 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX 1975 #define MPI2_SAS_IOUNIT5_PHY_MAX (1) 1976 #endif 1977 1978 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 1979 { 1980 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1981 U8 NumPhys; /* 0x08 */ 1982 U8 Reserved1; /* 0x09 */ 1983 U16 Reserved2; /* 0x0A */ 1984 U32 Reserved3; /* 0x0C */ 1985 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */ 1986 } MPI2_CONFIG_PAGE_SASIOUNIT_5, 1987 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 1988 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t; 1989 1990 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 1991 1992 1993 /* SAS IO Unit Page 6 */ 1994 1995 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 1996 { 1997 U8 CurrentStatus; /* 0x00 */ 1998 U8 CurrentModulation; /* 0x01 */ 1999 U8 CurrentUtilization; /* 0x02 */ 2000 U8 Reserved1; /* 0x03 */ 2001 U32 Reserved2; /* 0x04 */ 2002 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2003 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2004 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 2005 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t; 2006 2007 /* defines for CurrentStatus field */ 2008 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 2009 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 2010 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 2011 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 2012 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 2013 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 2014 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 2015 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 2016 2017 /* defines for CurrentModulation field */ 2018 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 2019 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 2020 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 2021 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 2022 2023 /* 2024 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2025 * one and check the value returned for NumGroups at runtime. 2026 */ 2027 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 2028 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 2029 #endif 2030 2031 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 2032 { 2033 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2034 U32 Reserved1; /* 0x08 */ 2035 U32 Reserved2; /* 0x0C */ 2036 U8 NumGroups; /* 0x10 */ 2037 U8 Reserved3; /* 0x11 */ 2038 U16 Reserved4; /* 0x12 */ 2039 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2040 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */ 2041 } MPI2_CONFIG_PAGE_SASIOUNIT_6, 2042 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 2043 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t; 2044 2045 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 2046 2047 2048 /* SAS IO Unit Page 7 */ 2049 2050 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2051 { 2052 U8 Flags; /* 0x00 */ 2053 U8 Reserved1; /* 0x01 */ 2054 U16 Reserved2; /* 0x02 */ 2055 U8 Threshold75Pct; /* 0x04 */ 2056 U8 Threshold50Pct; /* 0x05 */ 2057 U8 Threshold25Pct; /* 0x06 */ 2058 U8 Reserved3; /* 0x07 */ 2059 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2060 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2061 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2062 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2063 2064 /* defines for Flags field */ 2065 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2066 2067 2068 /* 2069 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2070 * one and check the value returned for NumGroups at runtime. 2071 */ 2072 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2073 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2074 #endif 2075 2076 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 2077 { 2078 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2079 U8 SamplingInterval; /* 0x08 */ 2080 U8 WindowLength; /* 0x09 */ 2081 U16 Reserved1; /* 0x0A */ 2082 U32 Reserved2; /* 0x0C */ 2083 U32 Reserved3; /* 0x10 */ 2084 U8 NumGroups; /* 0x14 */ 2085 U8 Reserved4; /* 0x15 */ 2086 U16 Reserved5; /* 0x16 */ 2087 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2088 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */ 2089 } MPI2_CONFIG_PAGE_SASIOUNIT_7, 2090 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2091 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t; 2092 2093 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2094 2095 2096 /* SAS IO Unit Page 8 */ 2097 2098 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 2099 { 2100 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2101 U32 Reserved1; /* 0x08 */ 2102 U32 PowerManagementCapabilities; /* 0x0C */ 2103 U32 Reserved2; /* 0x10 */ 2104 } MPI2_CONFIG_PAGE_SASIOUNIT_8, 2105 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2106 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t; 2107 2108 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2109 2110 /* defines for PowerManagementCapabilities field */ 2111 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x000001000) 2112 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x000000800) 2113 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x000000400) 2114 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x000000200) 2115 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x000000100) 2116 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x000000010) 2117 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x000000008) 2118 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x000000004) 2119 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x000000002) 2120 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x000000001) 2121 2122 2123 2124 2125 /**************************************************************************** 2126 * SAS Expander Config Pages 2127 ****************************************************************************/ 2128 2129 /* SAS Expander Page 0 */ 2130 2131 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 2132 { 2133 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2134 U8 PhysicalPort; /* 0x08 */ 2135 U8 ReportGenLength; /* 0x09 */ 2136 U16 EnclosureHandle; /* 0x0A */ 2137 U64 SASAddress; /* 0x0C */ 2138 U32 DiscoveryStatus; /* 0x14 */ 2139 U16 DevHandle; /* 0x18 */ 2140 U16 ParentDevHandle; /* 0x1A */ 2141 U16 ExpanderChangeCount; /* 0x1C */ 2142 U16 ExpanderRouteIndexes; /* 0x1E */ 2143 U8 NumPhys; /* 0x20 */ 2144 U8 SASLevel; /* 0x21 */ 2145 U16 Flags; /* 0x22 */ 2146 U16 STPBusInactivityTimeLimit; /* 0x24 */ 2147 U16 STPMaxConnectTimeLimit; /* 0x26 */ 2148 U16 STP_SMP_NexusLossTime; /* 0x28 */ 2149 U16 MaxNumRoutedSasAddresses; /* 0x2A */ 2150 U64 ActiveZoneManagerSASAddress;/* 0x2C */ 2151 U16 ZoneLockInactivityLimit; /* 0x34 */ 2152 U16 Reserved1; /* 0x36 */ 2153 U8 TimeToReducedFunc; /* 0x38 */ 2154 U8 InitialTimeToReducedFunc; /* 0x39 */ 2155 U8 MaxReducedFuncTime; /* 0x3A */ 2156 U8 Reserved2; /* 0x3B */ 2157 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2158 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t; 2159 2160 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2161 2162 /* values for SAS Expander Page 0 DiscoveryStatus field */ 2163 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2164 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2165 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2166 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2167 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2168 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2169 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2170 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2171 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2172 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2173 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2174 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2175 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2176 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2177 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2178 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2179 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2180 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2181 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2182 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2183 2184 /* values for SAS Expander Page 0 Flags field */ 2185 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2186 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2187 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2188 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2189 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2190 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2191 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2192 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2193 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2194 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2195 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2196 2197 2198 /* SAS Expander Page 1 */ 2199 2200 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 2201 { 2202 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2203 U8 PhysicalPort; /* 0x08 */ 2204 U8 Reserved1; /* 0x09 */ 2205 U16 Reserved2; /* 0x0A */ 2206 U8 NumPhys; /* 0x0C */ 2207 U8 Phy; /* 0x0D */ 2208 U16 NumTableEntriesProgrammed; /* 0x0E */ 2209 U8 ProgrammedLinkRate; /* 0x10 */ 2210 U8 HwLinkRate; /* 0x11 */ 2211 U16 AttachedDevHandle; /* 0x12 */ 2212 U32 PhyInfo; /* 0x14 */ 2213 U32 AttachedDeviceInfo; /* 0x18 */ 2214 U16 ExpanderDevHandle; /* 0x1C */ 2215 U8 ChangeCount; /* 0x1E */ 2216 U8 NegotiatedLinkRate; /* 0x1F */ 2217 U8 PhyIdentifier; /* 0x20 */ 2218 U8 AttachedPhyIdentifier; /* 0x21 */ 2219 U8 Reserved3; /* 0x22 */ 2220 U8 DiscoveryInfo; /* 0x23 */ 2221 U32 AttachedPhyInfo; /* 0x24 */ 2222 U8 ZoneGroup; /* 0x28 */ 2223 U8 SelfConfigStatus; /* 0x29 */ 2224 U16 Reserved4; /* 0x2A */ 2225 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2226 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t; 2227 2228 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2229 2230 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2231 2232 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2233 2234 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2235 2236 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */ 2237 2238 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2239 2240 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2241 2242 /* values for SAS Expander Page 1 DiscoveryInfo field */ 2243 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2244 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2245 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2246 2247 2248 /**************************************************************************** 2249 * SAS Device Config Pages 2250 ****************************************************************************/ 2251 2252 /* SAS Device Page 0 */ 2253 2254 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 2255 { 2256 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2257 U16 Slot; /* 0x08 */ 2258 U16 EnclosureHandle; /* 0x0A */ 2259 U64 SASAddress; /* 0x0C */ 2260 U16 ParentDevHandle; /* 0x14 */ 2261 U8 PhyNum; /* 0x16 */ 2262 U8 AccessStatus; /* 0x17 */ 2263 U16 DevHandle; /* 0x18 */ 2264 U8 AttachedPhyIdentifier; /* 0x1A */ 2265 U8 ZoneGroup; /* 0x1B */ 2266 U32 DeviceInfo; /* 0x1C */ 2267 U16 Flags; /* 0x20 */ 2268 U8 PhysicalPort; /* 0x22 */ 2269 U8 MaxPortConnections; /* 0x23 */ 2270 U64 DeviceName; /* 0x24 */ 2271 U8 PortGroups; /* 0x2C */ 2272 U8 DmaGroup; /* 0x2D */ 2273 U8 ControlGroup; /* 0x2E */ 2274 U8 Reserved1; /* 0x2F */ 2275 U32 Reserved2; /* 0x30 */ 2276 U32 Reserved3; /* 0x34 */ 2277 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2278 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t; 2279 2280 #define MPI2_SASDEVICE0_PAGEVERSION (0x08) 2281 2282 /* values for SAS Device Page 0 AccessStatus field */ 2283 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2284 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2285 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2286 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2287 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2288 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2289 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2290 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2291 /* specific values for SATA Init failures */ 2292 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2293 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2294 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2295 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2296 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2297 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2298 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2299 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2300 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2301 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2302 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2303 2304 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2305 2306 /* values for SAS Device Page 0 Flags field */ 2307 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2308 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2309 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2310 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2311 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2312 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2313 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2314 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2315 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2316 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2317 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2318 2319 2320 /* SAS Device Page 1 */ 2321 2322 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 2323 { 2324 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2325 U32 Reserved1; /* 0x08 */ 2326 U64 SASAddress; /* 0x0C */ 2327 U32 Reserved2; /* 0x14 */ 2328 U16 DevHandle; /* 0x18 */ 2329 U16 Reserved3; /* 0x1A */ 2330 U8 InitialRegDeviceFIS[20];/* 0x1C */ 2331 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2332 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t; 2333 2334 #define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2335 2336 2337 /**************************************************************************** 2338 * SAS PHY Config Pages 2339 ****************************************************************************/ 2340 2341 /* SAS PHY Page 0 */ 2342 2343 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 2344 { 2345 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2346 U16 OwnerDevHandle; /* 0x08 */ 2347 U16 Reserved1; /* 0x0A */ 2348 U16 AttachedDevHandle; /* 0x0C */ 2349 U8 AttachedPhyIdentifier; /* 0x0E */ 2350 U8 Reserved2; /* 0x0F */ 2351 U32 AttachedPhyInfo; /* 0x10 */ 2352 U8 ProgrammedLinkRate; /* 0x14 */ 2353 U8 HwLinkRate; /* 0x15 */ 2354 U8 ChangeCount; /* 0x16 */ 2355 U8 Flags; /* 0x17 */ 2356 U32 PhyInfo; /* 0x18 */ 2357 U8 NegotiatedLinkRate; /* 0x1C */ 2358 U8 Reserved3; /* 0x1D */ 2359 U16 Reserved4; /* 0x1E */ 2360 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2361 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t; 2362 2363 #define MPI2_SASPHY0_PAGEVERSION (0x03) 2364 2365 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2366 2367 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2368 2369 /* values for SAS PHY Page 0 Flags field */ 2370 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2371 2372 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2373 2374 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2375 2376 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2377 2378 2379 /* SAS PHY Page 1 */ 2380 2381 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 2382 { 2383 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2384 U32 Reserved1; /* 0x08 */ 2385 U32 InvalidDwordCount; /* 0x0C */ 2386 U32 RunningDisparityErrorCount; /* 0x10 */ 2387 U32 LossDwordSynchCount; /* 0x14 */ 2388 U32 PhyResetProblemCount; /* 0x18 */ 2389 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 2390 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t; 2391 2392 #define MPI2_SASPHY1_PAGEVERSION (0x01) 2393 2394 2395 /* SAS PHY Page 2 */ 2396 2397 typedef struct _MPI2_SASPHY2_PHY_EVENT 2398 { 2399 U8 PhyEventCode; /* 0x00 */ 2400 U8 Reserved1; /* 0x01 */ 2401 U16 Reserved2; /* 0x02 */ 2402 U32 PhyEventInfo; /* 0x04 */ 2403 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT, 2404 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t; 2405 2406 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 2407 2408 2409 /* 2410 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2411 * one and check the value returned for NumPhyEvents at runtime. 2412 */ 2413 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX 2414 #define MPI2_SASPHY2_PHY_EVENT_MAX (1) 2415 #endif 2416 2417 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 2418 { 2419 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2420 U32 Reserved1; /* 0x08 */ 2421 U8 NumPhyEvents; /* 0x0C */ 2422 U8 Reserved2; /* 0x0D */ 2423 U16 Reserved3; /* 0x0E */ 2424 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */ 2425 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 2426 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t; 2427 2428 #define MPI2_SASPHY2_PAGEVERSION (0x00) 2429 2430 2431 /* SAS PHY Page 3 */ 2432 2433 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG 2434 { 2435 U8 PhyEventCode; /* 0x00 */ 2436 U8 Reserved1; /* 0x01 */ 2437 U16 Reserved2; /* 0x02 */ 2438 U8 CounterType; /* 0x04 */ 2439 U8 ThresholdWindow; /* 0x05 */ 2440 U8 TimeUnits; /* 0x06 */ 2441 U8 Reserved3; /* 0x07 */ 2442 U32 EventThreshold; /* 0x08 */ 2443 U16 ThresholdFlags; /* 0x0C */ 2444 U16 Reserved4; /* 0x0E */ 2445 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 2446 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t; 2447 2448 /* values for PhyEventCode field */ 2449 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2450 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2451 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2452 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2453 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2454 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 2455 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 2456 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 2457 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 2458 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 2459 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 2460 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 2461 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 2462 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 2463 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 2464 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 2465 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 2466 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 2467 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 2468 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 2469 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 2470 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 2471 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 2472 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 2473 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 2474 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 2475 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 2476 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 2477 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 2478 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 2479 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 2480 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 2481 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 2482 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 2483 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 2484 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 2485 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 2486 2487 /* values for the CounterType field */ 2488 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 2489 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 2490 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 2491 2492 /* values for the TimeUnits field */ 2493 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 2494 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 2495 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 2496 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 2497 2498 /* values for the ThresholdFlags field */ 2499 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 2500 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 2501 2502 /* 2503 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2504 * one and check the value returned for NumPhyEvents at runtime. 2505 */ 2506 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX 2507 #define MPI2_SASPHY3_PHY_EVENT_MAX (1) 2508 #endif 2509 2510 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 2511 { 2512 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2513 U32 Reserved1; /* 0x08 */ 2514 U8 NumPhyEvents; /* 0x0C */ 2515 U8 Reserved2; /* 0x0D */ 2516 U16 Reserved3; /* 0x0E */ 2517 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */ 2518 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 2519 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t; 2520 2521 #define MPI2_SASPHY3_PAGEVERSION (0x00) 2522 2523 2524 /* SAS PHY Page 4 */ 2525 2526 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 2527 { 2528 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2529 U16 Reserved1; /* 0x08 */ 2530 U8 Reserved2; /* 0x0A */ 2531 U8 Flags; /* 0x0B */ 2532 U8 InitialFrame[28]; /* 0x0C */ 2533 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 2534 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t; 2535 2536 #define MPI2_SASPHY4_PAGEVERSION (0x00) 2537 2538 /* values for the Flags field */ 2539 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 2540 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 2541 2542 2543 2544 2545 /**************************************************************************** 2546 * SAS Port Config Pages 2547 ****************************************************************************/ 2548 2549 /* SAS Port Page 0 */ 2550 2551 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 2552 { 2553 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2554 U8 PortNumber; /* 0x08 */ 2555 U8 PhysicalPort; /* 0x09 */ 2556 U8 PortWidth; /* 0x0A */ 2557 U8 PhysicalPortWidth; /* 0x0B */ 2558 U8 ZoneGroup; /* 0x0C */ 2559 U8 Reserved1; /* 0x0D */ 2560 U16 Reserved2; /* 0x0E */ 2561 U64 SASAddress; /* 0x10 */ 2562 U32 DeviceInfo; /* 0x18 */ 2563 U32 Reserved3; /* 0x1C */ 2564 U32 Reserved4; /* 0x20 */ 2565 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 2566 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t; 2567 2568 #define MPI2_SASPORT0_PAGEVERSION (0x00) 2569 2570 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 2571 2572 2573 /**************************************************************************** 2574 * SAS Enclosure Config Pages 2575 ****************************************************************************/ 2576 2577 /* SAS Enclosure Page 0 */ 2578 2579 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 2580 { 2581 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2582 U32 Reserved1; /* 0x08 */ 2583 U64 EnclosureLogicalID; /* 0x0C */ 2584 U16 Flags; /* 0x14 */ 2585 U16 EnclosureHandle; /* 0x16 */ 2586 U16 NumSlots; /* 0x18 */ 2587 U16 StartSlot; /* 0x1A */ 2588 U16 Reserved2; /* 0x1C */ 2589 U16 SEPDevHandle; /* 0x1E */ 2590 U32 Reserved3; /* 0x20 */ 2591 U32 Reserved4; /* 0x24 */ 2592 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 2593 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 2594 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t; 2595 2596 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x03) 2597 2598 /* values for SAS Enclosure Page 0 Flags field */ 2599 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 2600 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 2601 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 2602 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 2603 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 2604 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 2605 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 2606 2607 2608 /**************************************************************************** 2609 * Log Config Page 2610 ****************************************************************************/ 2611 2612 /* Log Page 0 */ 2613 2614 /* 2615 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2616 * one and check the value returned for NumLogEntries at runtime. 2617 */ 2618 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 2619 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 2620 #endif 2621 2622 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 2623 2624 typedef struct _MPI2_LOG_0_ENTRY 2625 { 2626 U64 TimeStamp; /* 0x00 */ 2627 U32 Reserved1; /* 0x08 */ 2628 U16 LogSequence; /* 0x0C */ 2629 U16 LogEntryQualifier; /* 0x0E */ 2630 U8 VP_ID; /* 0x10 */ 2631 U8 VF_ID; /* 0x11 */ 2632 U16 Reserved2; /* 0x12 */ 2633 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */ 2634 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY, 2635 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t; 2636 2637 /* values for Log Page 0 LogEntry LogEntryQualifier field */ 2638 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 2639 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 2640 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 2641 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 2642 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 2643 2644 typedef struct _MPI2_CONFIG_PAGE_LOG_0 2645 { 2646 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2647 U32 Reserved1; /* 0x08 */ 2648 U32 Reserved2; /* 0x0C */ 2649 U16 NumLogEntries; /* 0x10 */ 2650 U16 Reserved3; /* 0x12 */ 2651 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */ 2652 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0, 2653 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t; 2654 2655 #define MPI2_LOG_0_PAGEVERSION (0x02) 2656 2657 2658 /**************************************************************************** 2659 * RAID Config Page 2660 ****************************************************************************/ 2661 2662 /* RAID Page 0 */ 2663 2664 /* 2665 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2666 * one and check the value returned for NumElements at runtime. 2667 */ 2668 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 2669 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 2670 #endif 2671 2672 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT 2673 { 2674 U16 ElementFlags; /* 0x00 */ 2675 U16 VolDevHandle; /* 0x02 */ 2676 U8 HotSparePool; /* 0x04 */ 2677 U8 PhysDiskNum; /* 0x05 */ 2678 U16 PhysDiskDevHandle; /* 0x06 */ 2679 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 2680 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 2681 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t; 2682 2683 /* values for the ElementFlags field */ 2684 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 2685 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 2686 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 2687 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 2688 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 2689 2690 2691 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 2692 { 2693 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2694 U8 NumHotSpares; /* 0x08 */ 2695 U8 NumPhysDisks; /* 0x09 */ 2696 U8 NumVolumes; /* 0x0A */ 2697 U8 ConfigNum; /* 0x0B */ 2698 U32 Flags; /* 0x0C */ 2699 U8 ConfigGUID[24]; /* 0x10 */ 2700 U32 Reserved1; /* 0x28 */ 2701 U8 NumElements; /* 0x2C */ 2702 U8 Reserved2; /* 0x2D */ 2703 U16 Reserved3; /* 0x2E */ 2704 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */ 2705 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 2706 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 2707 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t; 2708 2709 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 2710 2711 /* values for RAID Configuration Page 0 Flags field */ 2712 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 2713 2714 2715 /**************************************************************************** 2716 * Driver Persistent Mapping Config Pages 2717 ****************************************************************************/ 2718 2719 /* Driver Persistent Mapping Page 0 */ 2720 2721 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY 2722 { 2723 U64 PhysicalIdentifier; /* 0x00 */ 2724 U16 MappingInformation; /* 0x08 */ 2725 U16 DeviceIndex; /* 0x0A */ 2726 U32 PhysicalBitsMapping; /* 0x0C */ 2727 U32 Reserved1; /* 0x10 */ 2728 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 2729 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 2730 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t; 2731 2732 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 2733 { 2734 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2735 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */ 2736 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 2737 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 2738 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t; 2739 2740 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 2741 2742 /* values for Driver Persistent Mapping Page 0 MappingInformation field */ 2743 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 2744 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 2745 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 2746 2747 2748 /**************************************************************************** 2749 * Ethernet Config Pages 2750 ****************************************************************************/ 2751 2752 /* Ethernet Page 0 */ 2753 2754 /* IP address (union of IPv4 and IPv6) */ 2755 typedef union _MPI2_ETHERNET_IP_ADDR 2756 { 2757 U32 IPv4Addr; 2758 U32 IPv6Addr[4]; 2759 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR, 2760 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t; 2761 2762 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 2763 2764 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 2765 { 2766 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2767 U8 NumInterfaces; /* 0x08 */ 2768 U8 Reserved0; /* 0x09 */ 2769 U16 Reserved1; /* 0x0A */ 2770 U32 Status; /* 0x0C */ 2771 U8 MediaState; /* 0x10 */ 2772 U8 Reserved2; /* 0x11 */ 2773 U16 Reserved3; /* 0x12 */ 2774 U8 MacAddress[6]; /* 0x14 */ 2775 U8 Reserved4; /* 0x1A */ 2776 U8 Reserved5; /* 0x1B */ 2777 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */ 2778 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */ 2779 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */ 2780 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */ 2781 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */ 2782 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */ 2783 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 2784 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 2785 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t; 2786 2787 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 2788 2789 /* values for Ethernet Page 0 Status field */ 2790 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 2791 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 2792 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 2793 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 2794 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 2795 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 2796 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 2797 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 2798 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 2799 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 2800 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 2801 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 2802 2803 /* values for Ethernet Page 0 MediaState field */ 2804 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 2805 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 2806 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 2807 2808 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 2809 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 2810 #define MPI2_ETHPG0_MS_10MBIT (0x01) 2811 #define MPI2_ETHPG0_MS_100MBIT (0x02) 2812 #define MPI2_ETHPG0_MS_1GBIT (0x03) 2813 2814 2815 /* Ethernet Page 1 */ 2816 2817 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 2818 { 2819 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2820 U32 Reserved0; /* 0x08 */ 2821 U32 Flags; /* 0x0C */ 2822 U8 MediaState; /* 0x10 */ 2823 U8 Reserved1; /* 0x11 */ 2824 U16 Reserved2; /* 0x12 */ 2825 U8 MacAddress[6]; /* 0x14 */ 2826 U8 Reserved3; /* 0x1A */ 2827 U8 Reserved4; /* 0x1B */ 2828 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */ 2829 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */ 2830 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */ 2831 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */ 2832 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */ 2833 U32 Reserved5; /* 0x6C */ 2834 U32 Reserved6; /* 0x70 */ 2835 U32 Reserved7; /* 0x74 */ 2836 U32 Reserved8; /* 0x78 */ 2837 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 2838 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 2839 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t; 2840 2841 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 2842 2843 /* values for Ethernet Page 1 Flags field */ 2844 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 2845 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 2846 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 2847 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 2848 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 2849 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 2850 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 2851 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 2852 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 2853 2854 /* values for Ethernet Page 1 MediaState field */ 2855 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 2856 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 2857 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 2858 2859 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 2860 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 2861 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 2862 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 2863 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 2864 2865 2866 /**************************************************************************** 2867 * Extended Manufacturing Config Pages 2868 ****************************************************************************/ 2869 2870 /* 2871 * Generic structure to use for product-specific extended manufacturing pages 2872 * (currently Extended Manufacturing Page 40 through Extended Manufacturing 2873 * Page 60). 2874 */ 2875 2876 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS 2877 { 2878 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2879 U32 ProductSpecificInfo; /* 0x08 */ 2880 } MPI2_CONFIG_PAGE_EXT_MAN_PS, 2881 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 2882 Mpi2ExtManufacturingPagePS_t, MPI2_POINTER pMpi2ExtManufacturingPagePS_t; 2883 2884 /* PageVersion should be provided by product-specific code */ 2885 2886 #endif 2887 2888