1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2006-2015 LSI Corp. 5 * Copyright (c) 2013-2015 Avago Technologies 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD 30 */ 31 32 /* 33 * Copyright (c) 2006-2015 LSI Corporation. 34 * Copyright (c) 2013-2015 Avago Technologies 35 * 36 * 37 * Name: mpi2_cnfg.h 38 * Title: MPI Configuration messages and pages 39 * Creation Date: November 10, 2006 40 * 41 * mpi2_cnfg.h Version: 02.00.17 42 * 43 * Version History 44 * --------------- 45 * 46 * Date Version Description 47 * -------- -------- ------------------------------------------------------ 48 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 49 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 50 * Added Manufacturing Page 11. 51 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 52 * define. 53 * 06-26-07 02.00.02 Adding generic structure for product-specific 54 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 55 * Rework of BIOS Page 2 configuration page. 56 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 57 * forms. 58 * Added configuration pages IOC Page 8 and Driver 59 * Persistent Mapping Page 0. 60 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 61 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 62 * RAID Physical Disk Pages 0 and 1, RAID Configuration 63 * Page 0). 64 * Added new value for AccessStatus field of SAS Device 65 * Page 0 (_SATA_NEEDS_INITIALIZATION). 66 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 67 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 68 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 69 * NVDATA. 70 * Modified IOC Page 7 to use masks and added field for 71 * SASBroadcastPrimitiveMasks. 72 * Added MPI2_CONFIG_PAGE_BIOS_4. 73 * Added MPI2_CONFIG_PAGE_LOG_0. 74 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 75 * Added SAS Device IDs. 76 * Updated Integrated RAID configuration pages including 77 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 78 * Page 0. 79 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 80 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 81 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 82 * Added missing MaxNumRoutedSasAddresses field to 83 * MPI2_CONFIG_PAGE_EXPANDER_0. 84 * Added SAS Port Page 0. 85 * Modified structure layout for 86 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 87 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 88 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 89 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 90 * to 0x000000FF. 91 * Added two new values for the Physical Disk Coercion Size 92 * bits in the Flags field of Manufacturing Page 4. 93 * Added product-specific Manufacturing pages 16 to 31. 94 * Modified Flags bits for controlling write cache on SATA 95 * drives in IO Unit Page 1. 96 * Added new bit to AdditionalControlFlags of SAS IO Unit 97 * Page 1 to control Invalid Topology Correction. 98 * Added additional defines for RAID Volume Page 0 99 * VolumeStatusFlags field. 100 * Modified meaning of RAID Volume Page 0 VolumeSettings 101 * define for auto-configure of hot-swap drives. 102 * Added SupportedPhysDisks field to RAID Volume Page 1 and 103 * added related defines. 104 * Added PhysDiskAttributes field (and related defines) to 105 * RAID Physical Disk Page 0. 106 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 107 * Added three new DiscoveryStatus bits for SAS IO Unit 108 * Page 0 and SAS Expander Page 0. 109 * Removed multiplexing information from SAS IO Unit pages. 110 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 111 * Removed Zone Address Resolved bit from PhyInfo and from 112 * Expander Page 0 Flags field. 113 * Added two new AccessStatus values to SAS Device Page 0 114 * for indicating routing problems. Added 3 reserved words 115 * to this page. 116 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 117 * Inserted missing reserved field into structure for IOC 118 * Page 6. 119 * Added more pending task bits to RAID Volume Page 0 120 * VolumeStatusFlags defines. 121 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 122 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 123 * and SAS Expander Page 0 to flag a downstream initiator 124 * when in simplified routing mode. 125 * Removed SATA Init Failure defines for DiscoveryStatus 126 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 127 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 128 * Added PortGroups, DmaGroup, and ControlGroup fields to 129 * SAS Device Page 0. 130 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 131 * Unit Page 6. 132 * Added expander reduced functionality data to SAS 133 * Expander Page 0. 134 * Added SAS PHY Page 2 and SAS PHY Page 3. 135 * 07-30-09 02.00.12 Added IO Unit Page 7. 136 * Added new device ids. 137 * Added SAS IO Unit Page 5. 138 * Added partial and slumber power management capable flags 139 * to SAS Device Page 0 Flags field. 140 * Added PhyInfo defines for power condition. 141 * Added Ethernet configuration pages. 142 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 143 * Added SAS PHY Page 4 structure and defines. 144 * 02-10-10 02.00.14 Modified the comments for the configuration page 145 * structures that contain an array of data. The host 146 * should use the "count" field in the page data (e.g. the 147 * NumPhys field) to determine the number of valid elements 148 * in the array. 149 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 150 * Added PowerManagementCapabilities to IO Unit Page 7. 151 * Added PortWidthModGroup field to 152 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 153 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 154 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 155 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 156 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 157 * define. 158 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 159 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 160 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 161 * defines. 162 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 163 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 164 * the Pinout field. 165 * Added BoardTemperature and BoardTemperatureUnits fields 166 * to MPI2_CONFIG_PAGE_IO_UNIT_7. 167 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 168 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 169 * -------------------------------------------------------------------------- 170 */ 171 172 #ifndef MPI2_CNFG_H 173 #define MPI2_CNFG_H 174 175 /***************************************************************************** 176 * Configuration Page Header and defines 177 *****************************************************************************/ 178 179 /* Config Page Header */ 180 typedef struct _MPI2_CONFIG_PAGE_HEADER 181 { 182 U8 PageVersion; /* 0x00 */ 183 U8 PageLength; /* 0x01 */ 184 U8 PageNumber; /* 0x02 */ 185 U8 PageType; /* 0x03 */ 186 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER, 187 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t; 188 189 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION 190 { 191 MPI2_CONFIG_PAGE_HEADER Struct; 192 U8 Bytes[4]; 193 U16 Word16[2]; 194 U32 Word32; 195 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 196 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion; 197 198 /* Extended Config Page Header */ 199 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER 200 { 201 U8 PageVersion; /* 0x00 */ 202 U8 Reserved1; /* 0x01 */ 203 U8 PageNumber; /* 0x02 */ 204 U8 PageType; /* 0x03 */ 205 U16 ExtPageLength; /* 0x04 */ 206 U8 ExtPageType; /* 0x06 */ 207 U8 Reserved2; /* 0x07 */ 208 } MPI2_CONFIG_EXTENDED_PAGE_HEADER, 209 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 210 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t; 211 212 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION 213 { 214 MPI2_CONFIG_PAGE_HEADER Struct; 215 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 216 U8 Bytes[8]; 217 U16 Word16[4]; 218 U32 Word32[2]; 219 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 220 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion; 221 222 /* PageType field values */ 223 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 224 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 225 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 226 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 227 228 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 229 #define MPI2_CONFIG_PAGETYPE_IOC (0x01) 230 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 231 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 232 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 233 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 234 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 235 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 236 237 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 238 239 /* ExtPageType field values */ 240 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 241 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 242 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 243 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 244 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 245 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 246 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 247 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 248 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 249 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 250 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 251 252 /***************************************************************************** 253 * PageAddress defines 254 *****************************************************************************/ 255 256 /* RAID Volume PageAddress format */ 257 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 258 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 259 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 260 261 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 262 263 /* RAID Physical Disk PageAddress format */ 264 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 265 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 266 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 267 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 268 269 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 270 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 271 272 /* SAS Expander PageAddress format */ 273 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 274 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 275 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 276 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 277 278 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 279 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 280 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 281 282 /* SAS Device PageAddress format */ 283 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 284 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 285 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 286 287 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 288 289 /* SAS PHY PageAddress format */ 290 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 291 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 292 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 293 294 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 295 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 296 297 /* SAS Port PageAddress format */ 298 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 299 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 300 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 301 302 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 303 304 /* SAS Enclosure PageAddress format */ 305 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 306 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 307 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 308 309 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 310 311 /* RAID Configuration PageAddress format */ 312 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 313 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 314 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 315 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 316 317 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 318 319 /* Driver Persistent Mapping PageAddress format */ 320 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 321 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 322 323 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 324 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 325 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 326 327 /* Ethernet PageAddress format */ 328 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 329 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 330 331 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 332 333 /**************************************************************************** 334 * Configuration messages 335 ****************************************************************************/ 336 337 /* Configuration Request Message */ 338 typedef struct _MPI2_CONFIG_REQUEST 339 { 340 U8 Action; /* 0x00 */ 341 U8 SGLFlags; /* 0x01 */ 342 U8 ChainOffset; /* 0x02 */ 343 U8 Function; /* 0x03 */ 344 U16 ExtPageLength; /* 0x04 */ 345 U8 ExtPageType; /* 0x06 */ 346 U8 MsgFlags; /* 0x07 */ 347 U8 VP_ID; /* 0x08 */ 348 U8 VF_ID; /* 0x09 */ 349 U16 Reserved1; /* 0x0A */ 350 U32 Reserved2; /* 0x0C */ 351 U32 Reserved3; /* 0x10 */ 352 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 353 U32 PageAddress; /* 0x18 */ 354 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */ 355 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST, 356 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t; 357 358 /* values for the Action field */ 359 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 360 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 361 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 362 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 363 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 364 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 365 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 366 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 367 368 /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 369 370 /* Config Reply Message */ 371 typedef struct _MPI2_CONFIG_REPLY 372 { 373 U8 Action; /* 0x00 */ 374 U8 SGLFlags; /* 0x01 */ 375 U8 MsgLength; /* 0x02 */ 376 U8 Function; /* 0x03 */ 377 U16 ExtPageLength; /* 0x04 */ 378 U8 ExtPageType; /* 0x06 */ 379 U8 MsgFlags; /* 0x07 */ 380 U8 VP_ID; /* 0x08 */ 381 U8 VF_ID; /* 0x09 */ 382 U16 Reserved1; /* 0x0A */ 383 U16 Reserved2; /* 0x0C */ 384 U16 IOCStatus; /* 0x0E */ 385 U32 IOCLogInfo; /* 0x10 */ 386 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 387 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY, 388 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t; 389 390 /***************************************************************************** 391 * 392 * C o n f i g u r a t i o n P a g e s 393 * 394 *****************************************************************************/ 395 396 /**************************************************************************** 397 * Manufacturing Config pages 398 ****************************************************************************/ 399 400 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 401 402 /* SAS */ 403 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 404 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 405 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 406 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 407 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 408 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 409 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 410 411 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 412 413 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 414 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 415 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 416 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 417 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 418 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 419 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 420 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 421 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 422 423 /* Manufacturing Page 0 */ 424 425 typedef struct _MPI2_CONFIG_PAGE_MAN_0 426 { 427 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 428 U8 ChipName[16]; /* 0x04 */ 429 U8 ChipRevision[8]; /* 0x14 */ 430 U8 BoardName[16]; /* 0x1C */ 431 U8 BoardAssembly[16]; /* 0x2C */ 432 U8 BoardTracerNumber[16]; /* 0x3C */ 433 } MPI2_CONFIG_PAGE_MAN_0, 434 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0, 435 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t; 436 437 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 438 439 /* Manufacturing Page 1 */ 440 441 typedef struct _MPI2_CONFIG_PAGE_MAN_1 442 { 443 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 444 U8 VPD[256]; /* 0x04 */ 445 } MPI2_CONFIG_PAGE_MAN_1, 446 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1, 447 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t; 448 449 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 450 451 typedef struct _MPI2_CHIP_REVISION_ID 452 { 453 U16 DeviceID; /* 0x00 */ 454 U8 PCIRevisionID; /* 0x02 */ 455 U8 Reserved; /* 0x03 */ 456 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID, 457 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t; 458 459 /* Manufacturing Page 2 */ 460 461 /* 462 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 463 * one and check Header.PageLength at runtime. 464 */ 465 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 466 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 467 #endif 468 469 typedef struct _MPI2_CONFIG_PAGE_MAN_2 470 { 471 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 472 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 473 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */ 474 } MPI2_CONFIG_PAGE_MAN_2, 475 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2, 476 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t; 477 478 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 479 480 /* Manufacturing Page 3 */ 481 482 /* 483 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 484 * one and check Header.PageLength at runtime. 485 */ 486 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS 487 #define MPI2_MAN_PAGE_3_INFO_WORDS (1) 488 #endif 489 490 typedef struct _MPI2_CONFIG_PAGE_MAN_3 491 { 492 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 493 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 494 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */ 495 } MPI2_CONFIG_PAGE_MAN_3, 496 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3, 497 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t; 498 499 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 500 501 /* Manufacturing Page 4 */ 502 503 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS 504 { 505 U8 PowerSaveFlags; /* 0x00 */ 506 U8 InternalOperationsSleepTime; /* 0x01 */ 507 U8 InternalOperationsRunTime; /* 0x02 */ 508 U8 HostIdleTime; /* 0x03 */ 509 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 510 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 511 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t; 512 513 /* defines for the PowerSaveFlags field */ 514 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 515 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 516 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 517 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 518 519 typedef struct _MPI2_CONFIG_PAGE_MAN_4 520 { 521 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 522 U32 Reserved1; /* 0x04 */ 523 U32 Flags; /* 0x08 */ 524 U8 InquirySize; /* 0x0C */ 525 U8 Reserved2; /* 0x0D */ 526 U16 Reserved3; /* 0x0E */ 527 U8 InquiryData[56]; /* 0x10 */ 528 U32 RAID0VolumeSettings; /* 0x48 */ 529 U32 RAID1EVolumeSettings; /* 0x4C */ 530 U32 RAID1VolumeSettings; /* 0x50 */ 531 U32 RAID10VolumeSettings; /* 0x54 */ 532 U32 Reserved4; /* 0x58 */ 533 U32 Reserved5; /* 0x5C */ 534 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */ 535 U8 MaxOCEDisks; /* 0x64 */ 536 U8 ResyncRate; /* 0x65 */ 537 U16 DataScrubDuration; /* 0x66 */ 538 U8 MaxHotSpares; /* 0x68 */ 539 U8 MaxPhysDisksPerVol; /* 0x69 */ 540 U8 MaxPhysDisks; /* 0x6A */ 541 U8 MaxVolumes; /* 0x6B */ 542 } MPI2_CONFIG_PAGE_MAN_4, 543 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4, 544 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t; 545 546 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 547 548 /* Manufacturing Page 4 Flags field */ 549 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 550 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 551 552 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 553 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 554 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 555 556 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 557 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 558 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 559 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 560 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 561 562 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 563 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 564 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 565 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 566 567 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 568 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 569 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 570 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 571 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 572 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 573 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 574 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 575 576 /* Manufacturing Page 5 */ 577 578 /* 579 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 580 * one and check the value returned for NumPhys at runtime. 581 */ 582 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 583 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 584 #endif 585 586 typedef struct _MPI2_MANUFACTURING5_ENTRY 587 { 588 U64 WWID; /* 0x00 */ 589 U64 DeviceName; /* 0x08 */ 590 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY, 591 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t; 592 593 typedef struct _MPI2_CONFIG_PAGE_MAN_5 594 { 595 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 596 U8 NumPhys; /* 0x04 */ 597 U8 Reserved1; /* 0x05 */ 598 U16 Reserved2; /* 0x06 */ 599 U32 Reserved3; /* 0x08 */ 600 U32 Reserved4; /* 0x0C */ 601 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */ 602 } MPI2_CONFIG_PAGE_MAN_5, 603 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5, 604 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t; 605 606 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 607 608 /* Manufacturing Page 6 */ 609 610 typedef struct _MPI2_CONFIG_PAGE_MAN_6 611 { 612 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 613 U32 ProductSpecificInfo;/* 0x04 */ 614 } MPI2_CONFIG_PAGE_MAN_6, 615 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6, 616 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t; 617 618 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 619 620 /* Manufacturing Page 7 */ 621 622 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO 623 { 624 U32 Pinout; /* 0x00 */ 625 U8 Connector[16]; /* 0x04 */ 626 U8 Location; /* 0x14 */ 627 U8 ReceptacleID; /* 0x15 */ 628 U16 Slot; /* 0x16 */ 629 U32 Reserved2; /* 0x18 */ 630 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 631 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t; 632 633 /* defines for the Pinout field */ 634 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 635 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 636 637 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 638 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 639 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 640 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 641 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 642 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 643 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 644 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 645 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 646 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 647 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 648 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 649 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 650 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 651 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 652 653 /* defines for the Location field */ 654 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 655 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 656 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 657 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 658 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 659 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 660 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 661 662 /* 663 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 664 * one and check the value returned for NumPhys at runtime. 665 */ 666 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 667 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 668 #endif 669 670 typedef struct _MPI2_CONFIG_PAGE_MAN_7 671 { 672 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 673 U32 Reserved1; /* 0x04 */ 674 U32 Reserved2; /* 0x08 */ 675 U32 Flags; /* 0x0C */ 676 U8 EnclosureName[16]; /* 0x10 */ 677 U8 NumPhys; /* 0x20 */ 678 U8 Reserved3; /* 0x21 */ 679 U16 Reserved4; /* 0x22 */ 680 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */ 681 } MPI2_CONFIG_PAGE_MAN_7, 682 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7, 683 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t; 684 685 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 686 687 /* defines for the Flags field */ 688 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 689 690 /* 691 * Generic structure to use for product-specific manufacturing pages 692 * (currently Manufacturing Page 8 through Manufacturing Page 31). 693 */ 694 695 typedef struct _MPI2_CONFIG_PAGE_MAN_PS 696 { 697 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 698 U32 ProductSpecificInfo;/* 0x04 */ 699 } MPI2_CONFIG_PAGE_MAN_PS, 700 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS, 701 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t; 702 703 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 704 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 705 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 706 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 707 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 708 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 709 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 710 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 711 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 712 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 713 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 714 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 715 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 716 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 717 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 718 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 719 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 720 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 721 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 722 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 723 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 724 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 725 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 726 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 727 728 /**************************************************************************** 729 * IO Unit Config Pages 730 ****************************************************************************/ 731 732 /* IO Unit Page 0 */ 733 734 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 735 { 736 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 737 U64 UniqueValue; /* 0x04 */ 738 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */ 739 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */ 740 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 741 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t; 742 743 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 744 745 /* IO Unit Page 1 */ 746 747 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 748 { 749 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 750 U32 Flags; /* 0x04 */ 751 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 752 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t; 753 754 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 755 756 /* IO Unit Page 1 Flags defines */ 757 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 758 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 759 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 760 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 761 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 762 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 763 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 764 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 765 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 766 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 767 768 /* IO Unit Page 3 */ 769 770 /* 771 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 772 * one and check the value returned for GPIOCount at runtime. 773 */ 774 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 775 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 776 #endif 777 778 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 779 { 780 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 781 U8 GPIOCount; /* 0x04 */ 782 U8 Reserved1; /* 0x05 */ 783 U16 Reserved2; /* 0x06 */ 784 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */ 785 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 786 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t; 787 788 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 789 790 /* defines for IO Unit Page 3 GPIOVal field */ 791 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 792 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 793 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 794 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 795 796 /* IO Unit Page 5 */ 797 798 /* 799 * Upper layer code (drivers, utilities, etc.) should leave this define set to 800 * one and check the value returned for NumDmaEngines at runtime. 801 */ 802 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 803 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 804 #endif 805 806 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 807 { 808 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 809 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */ 810 U64 RaidAcceleratorBufferSize; /* 0x0C */ 811 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */ 812 U8 RAControlSize; /* 0x1C */ 813 U8 NumDmaEngines; /* 0x1D */ 814 U8 RAMinControlSize; /* 0x1E */ 815 U8 RAMaxControlSize; /* 0x1F */ 816 U32 Reserved1; /* 0x20 */ 817 U32 Reserved2; /* 0x24 */ 818 U32 Reserved3; /* 0x28 */ 819 U32 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */ 820 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 821 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t; 822 823 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 824 825 /* defines for IO Unit Page 5 DmaEngineCapabilities field */ 826 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00) 827 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 828 829 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 830 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 831 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 832 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 833 834 /* IO Unit Page 6 */ 835 836 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 837 { 838 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 839 U16 Flags; /* 0x04 */ 840 U8 RAHostControlSize; /* 0x06 */ 841 U8 Reserved0; /* 0x07 */ 842 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */ 843 U32 Reserved1; /* 0x10 */ 844 U32 Reserved2; /* 0x14 */ 845 U32 Reserved3; /* 0x18 */ 846 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 847 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t; 848 849 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 850 851 /* defines for IO Unit Page 6 Flags field */ 852 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 853 854 /* IO Unit Page 7 */ 855 856 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 857 { 858 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 859 U16 Reserved1; /* 0x04 */ 860 U8 PCIeWidth; /* 0x06 */ 861 U8 PCIeSpeed; /* 0x07 */ 862 U32 ProcessorState; /* 0x08 */ 863 U32 PowerManagementCapabilities; /* 0x0C */ 864 U16 IOCTemperature; /* 0x10 */ 865 U8 IOCTemperatureUnits; /* 0x12 */ 866 U8 IOCSpeed; /* 0x13 */ 867 U16 BoardTemperature; /* 0x14 */ 868 U8 BoardTemperatureUnits; /* 0x16 */ 869 U8 Reserved3; /* 0x17 */ 870 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 871 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t; 872 873 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x02) 874 875 /* defines for IO Unit Page 7 PCIeWidth field */ 876 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 877 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 878 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 879 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 880 881 /* defines for IO Unit Page 7 PCIeSpeed field */ 882 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 883 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 884 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 885 886 /* defines for IO Unit Page 7 ProcessorState field */ 887 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 888 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 889 890 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 891 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 892 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 893 894 /* defines for IO Unit Page 7 PowerManagementCapabilities field */ 895 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 896 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 897 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 898 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) 899 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) 900 901 /* defines for IO Unit Page 7 IOCTemperatureUnits field */ 902 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 903 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 904 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 905 906 /* defines for IO Unit Page 7 IOCSpeed field */ 907 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 908 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 909 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 910 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 911 912 /* defines for IO Unit Page 7 BoardTemperatureUnits field */ 913 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 914 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 915 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 916 917 /**************************************************************************** 918 * IOC Config Pages 919 ****************************************************************************/ 920 921 /* IOC Page 0 */ 922 923 typedef struct _MPI2_CONFIG_PAGE_IOC_0 924 { 925 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 926 U32 Reserved1; /* 0x04 */ 927 U32 Reserved2; /* 0x08 */ 928 U16 VendorID; /* 0x0C */ 929 U16 DeviceID; /* 0x0E */ 930 U8 RevisionID; /* 0x10 */ 931 U8 Reserved3; /* 0x11 */ 932 U16 Reserved4; /* 0x12 */ 933 U32 ClassCode; /* 0x14 */ 934 U16 SubsystemVendorID; /* 0x18 */ 935 U16 SubsystemID; /* 0x1A */ 936 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0, 937 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t; 938 939 #define MPI2_IOCPAGE0_PAGEVERSION (0x02) 940 941 /* IOC Page 1 */ 942 943 typedef struct _MPI2_CONFIG_PAGE_IOC_1 944 { 945 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 946 U32 Flags; /* 0x04 */ 947 U32 CoalescingTimeout; /* 0x08 */ 948 U8 CoalescingDepth; /* 0x0C */ 949 U8 PCISlotNum; /* 0x0D */ 950 U8 PCIBusNum; /* 0x0E */ 951 U8 PCIDomainSegment; /* 0x0F */ 952 U32 Reserved1; /* 0x10 */ 953 U32 Reserved2; /* 0x14 */ 954 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1, 955 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t; 956 957 #define MPI2_IOCPAGE1_PAGEVERSION (0x05) 958 959 /* defines for IOC Page 1 Flags field */ 960 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 961 962 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 963 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 964 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 965 966 /* IOC Page 6 */ 967 968 typedef struct _MPI2_CONFIG_PAGE_IOC_6 969 { 970 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 971 U32 CapabilitiesFlags; /* 0x04 */ 972 U8 MaxDrivesRAID0; /* 0x08 */ 973 U8 MaxDrivesRAID1; /* 0x09 */ 974 U8 MaxDrivesRAID1E; /* 0x0A */ 975 U8 MaxDrivesRAID10; /* 0x0B */ 976 U8 MinDrivesRAID0; /* 0x0C */ 977 U8 MinDrivesRAID1; /* 0x0D */ 978 U8 MinDrivesRAID1E; /* 0x0E */ 979 U8 MinDrivesRAID10; /* 0x0F */ 980 U32 Reserved1; /* 0x10 */ 981 U8 MaxGlobalHotSpares; /* 0x14 */ 982 U8 MaxPhysDisks; /* 0x15 */ 983 U8 MaxVolumes; /* 0x16 */ 984 U8 MaxConfigs; /* 0x17 */ 985 U8 MaxOCEDisks; /* 0x18 */ 986 U8 Reserved2; /* 0x19 */ 987 U16 Reserved3; /* 0x1A */ 988 U32 SupportedStripeSizeMapRAID0; /* 0x1C */ 989 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */ 990 U32 SupportedStripeSizeMapRAID10; /* 0x24 */ 991 U32 Reserved4; /* 0x28 */ 992 U32 Reserved5; /* 0x2C */ 993 U16 DefaultMetadataSize; /* 0x30 */ 994 U16 Reserved6; /* 0x32 */ 995 U16 MaxBadBlockTableEntries; /* 0x34 */ 996 U16 Reserved7; /* 0x36 */ 997 U32 IRNvsramVersion; /* 0x38 */ 998 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6, 999 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t; 1000 1001 #define MPI2_IOCPAGE6_PAGEVERSION (0x04) 1002 1003 /* defines for IOC Page 6 CapabilitiesFlags */ 1004 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1005 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1006 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1007 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1008 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1009 1010 /* IOC Page 7 */ 1011 1012 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1013 1014 typedef struct _MPI2_CONFIG_PAGE_IOC_7 1015 { 1016 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1017 U32 Reserved1; /* 0x04 */ 1018 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */ 1019 U16 SASBroadcastPrimitiveMasks; /* 0x18 */ 1020 U16 Reserved2; /* 0x1A */ 1021 U32 Reserved3; /* 0x1C */ 1022 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7, 1023 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t; 1024 1025 #define MPI2_IOCPAGE7_PAGEVERSION (0x01) 1026 1027 /* IOC Page 8 */ 1028 1029 typedef struct _MPI2_CONFIG_PAGE_IOC_8 1030 { 1031 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1032 U8 NumDevsPerEnclosure; /* 0x04 */ 1033 U8 Reserved1; /* 0x05 */ 1034 U16 Reserved2; /* 0x06 */ 1035 U16 MaxPersistentEntries; /* 0x08 */ 1036 U16 MaxNumPhysicalMappedIDs; /* 0x0A */ 1037 U16 Flags; /* 0x0C */ 1038 U16 Reserved3; /* 0x0E */ 1039 U16 IRVolumeMappingFlags; /* 0x10 */ 1040 U16 Reserved4; /* 0x12 */ 1041 U32 Reserved5; /* 0x14 */ 1042 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8, 1043 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t; 1044 1045 #define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1046 1047 /* defines for IOC Page 8 Flags field */ 1048 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1049 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1050 1051 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1052 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1053 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1054 1055 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1056 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1057 1058 /* defines for IOC Page 8 IRVolumeMappingFlags */ 1059 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1060 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1061 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1062 1063 /**************************************************************************** 1064 * BIOS Config Pages 1065 ****************************************************************************/ 1066 1067 /* BIOS Page 1 */ 1068 1069 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 1070 { 1071 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1072 U32 BiosOptions; /* 0x04 */ 1073 U32 IOCSettings; /* 0x08 */ 1074 U32 Reserved1; /* 0x0C */ 1075 U32 DeviceSettings; /* 0x10 */ 1076 U16 NumberOfDevices; /* 0x14 */ 1077 U16 Reserved2; /* 0x16 */ 1078 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */ 1079 U16 IOTimeoutSequential; /* 0x1A */ 1080 U16 IOTimeoutOther; /* 0x1C */ 1081 U16 IOTimeoutBlockDevicesRM; /* 0x1E */ 1082 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1, 1083 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t; 1084 1085 #define MPI2_BIOSPAGE1_PAGEVERSION (0x04) 1086 1087 /* values for BIOS Page 1 BiosOptions field */ 1088 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1089 1090 /* values for BIOS Page 1 IOCSettings field */ 1091 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1092 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1093 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1094 1095 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1096 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1097 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1098 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1099 1100 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1101 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1102 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1103 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1104 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1105 1106 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1107 1108 /* values for BIOS Page 1 DeviceSettings field */ 1109 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1110 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1111 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1112 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1113 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1114 1115 /* BIOS Page 2 */ 1116 1117 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER 1118 { 1119 U32 Reserved1; /* 0x00 */ 1120 U32 Reserved2; /* 0x04 */ 1121 U32 Reserved3; /* 0x08 */ 1122 U32 Reserved4; /* 0x0C */ 1123 U32 Reserved5; /* 0x10 */ 1124 U32 Reserved6; /* 0x14 */ 1125 } MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1126 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1127 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t; 1128 1129 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID 1130 { 1131 U64 SASAddress; /* 0x00 */ 1132 U8 LUN[8]; /* 0x08 */ 1133 U32 Reserved1; /* 0x10 */ 1134 U32 Reserved2; /* 0x14 */ 1135 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1136 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t; 1137 1138 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT 1139 { 1140 U64 EnclosureLogicalID; /* 0x00 */ 1141 U32 Reserved1; /* 0x08 */ 1142 U32 Reserved2; /* 0x0C */ 1143 U16 SlotNumber; /* 0x10 */ 1144 U16 Reserved3; /* 0x12 */ 1145 U32 Reserved4; /* 0x14 */ 1146 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1147 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1148 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t; 1149 1150 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME 1151 { 1152 U64 DeviceName; /* 0x00 */ 1153 U8 LUN[8]; /* 0x08 */ 1154 U32 Reserved1; /* 0x10 */ 1155 U32 Reserved2; /* 0x14 */ 1156 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1157 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t; 1158 1159 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE 1160 { 1161 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1162 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1163 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1164 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1165 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1166 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t; 1167 1168 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 1169 { 1170 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1171 U32 Reserved1; /* 0x04 */ 1172 U32 Reserved2; /* 0x08 */ 1173 U32 Reserved3; /* 0x0C */ 1174 U32 Reserved4; /* 0x10 */ 1175 U32 Reserved5; /* 0x14 */ 1176 U32 Reserved6; /* 0x18 */ 1177 U8 ReqBootDeviceForm; /* 0x1C */ 1178 U8 Reserved7; /* 0x1D */ 1179 U16 Reserved8; /* 0x1E */ 1180 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */ 1181 U8 ReqAltBootDeviceForm; /* 0x38 */ 1182 U8 Reserved9; /* 0x39 */ 1183 U16 Reserved10; /* 0x3A */ 1184 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */ 1185 U8 CurrentBootDeviceForm; /* 0x58 */ 1186 U8 Reserved11; /* 0x59 */ 1187 U16 Reserved12; /* 0x5A */ 1188 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */ 1189 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2, 1190 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t; 1191 1192 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1193 1194 /* values for BIOS Page 2 BootDeviceForm fields */ 1195 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1196 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1197 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1198 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1199 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1200 1201 /* BIOS Page 3 */ 1202 1203 typedef struct _MPI2_ADAPTER_INFO 1204 { 1205 U8 PciBusNumber; /* 0x00 */ 1206 U8 PciDeviceAndFunctionNumber; /* 0x01 */ 1207 U16 AdapterFlags; /* 0x02 */ 1208 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO, 1209 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t; 1210 1211 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1212 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1213 1214 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 1215 { 1216 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1217 U32 GlobalFlags; /* 0x04 */ 1218 U32 BiosVersion; /* 0x08 */ 1219 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */ 1220 U32 Reserved1; /* 0x1C */ 1221 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3, 1222 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t; 1223 1224 #define MPI2_BIOSPAGE3_PAGEVERSION (0x00) 1225 1226 /* values for BIOS Page 3 GlobalFlags */ 1227 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1228 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1229 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1230 1231 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1232 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1233 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1234 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1235 1236 /* BIOS Page 4 */ 1237 1238 /* 1239 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1240 * one and check the value returned for NumPhys at runtime. 1241 */ 1242 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1243 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1244 #endif 1245 1246 typedef struct _MPI2_BIOS4_ENTRY 1247 { 1248 U64 ReassignmentWWID; /* 0x00 */ 1249 U64 ReassignmentDeviceName; /* 0x08 */ 1250 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY, 1251 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t; 1252 1253 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 1254 { 1255 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1256 U8 NumPhys; /* 0x04 */ 1257 U8 Reserved1; /* 0x05 */ 1258 U16 Reserved2; /* 0x06 */ 1259 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */ 1260 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4, 1261 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t; 1262 1263 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1264 1265 /**************************************************************************** 1266 * RAID Volume Config Pages 1267 ****************************************************************************/ 1268 1269 /* RAID Volume Page 0 */ 1270 1271 typedef struct _MPI2_RAIDVOL0_PHYS_DISK 1272 { 1273 U8 RAIDSetNum; /* 0x00 */ 1274 U8 PhysDiskMap; /* 0x01 */ 1275 U8 PhysDiskNum; /* 0x02 */ 1276 U8 Reserved; /* 0x03 */ 1277 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK, 1278 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t; 1279 1280 /* defines for the PhysDiskMap field */ 1281 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1282 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1283 1284 typedef struct _MPI2_RAIDVOL0_SETTINGS 1285 { 1286 U16 Settings; /* 0x00 */ 1287 U8 HotSparePool; /* 0x01 */ 1288 U8 Reserved; /* 0x02 */ 1289 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS, 1290 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t; 1291 1292 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1293 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1294 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1295 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1296 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1297 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1298 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1299 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1300 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1301 1302 /* RAID Volume Page 0 VolumeSettings defines */ 1303 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1304 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1305 1306 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1307 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1308 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1309 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1310 1311 /* 1312 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1313 * one and check the value returned for NumPhysDisks at runtime. 1314 */ 1315 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1316 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1317 #endif 1318 1319 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 1320 { 1321 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1322 U16 DevHandle; /* 0x04 */ 1323 U8 VolumeState; /* 0x06 */ 1324 U8 VolumeType; /* 0x07 */ 1325 U32 VolumeStatusFlags; /* 0x08 */ 1326 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */ 1327 U64 MaxLBA; /* 0x10 */ 1328 U32 StripeSize; /* 0x18 */ 1329 U16 BlockSize; /* 0x1C */ 1330 U16 Reserved1; /* 0x1E */ 1331 U8 SupportedPhysDisks; /* 0x20 */ 1332 U8 ResyncRate; /* 0x21 */ 1333 U16 DataScrubDuration; /* 0x22 */ 1334 U8 NumPhysDisks; /* 0x24 */ 1335 U8 Reserved2; /* 0x25 */ 1336 U8 Reserved3; /* 0x26 */ 1337 U8 InactiveStatus; /* 0x27 */ 1338 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */ 1339 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1340 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t; 1341 1342 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1343 1344 /* values for RAID VolumeState */ 1345 #define MPI2_RAID_VOL_STATE_MISSING (0x00) 1346 #define MPI2_RAID_VOL_STATE_FAILED (0x01) 1347 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1348 #define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1349 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1350 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1351 1352 /* values for RAID VolumeType */ 1353 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1354 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1355 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1356 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1357 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1358 1359 /* values for RAID Volume Page 0 VolumeStatusFlags field */ 1360 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1361 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1362 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1363 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1364 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1365 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1366 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1367 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1368 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1369 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1370 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1371 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1372 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1373 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1374 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1375 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1376 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1377 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1378 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1379 1380 /* values for RAID Volume Page 0 SupportedPhysDisks field */ 1381 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1382 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1383 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1384 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1385 1386 /* values for RAID Volume Page 0 InactiveStatus field */ 1387 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1388 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1389 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1390 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1391 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1392 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1393 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1394 1395 /* RAID Volume Page 1 */ 1396 1397 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 1398 { 1399 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1400 U16 DevHandle; /* 0x04 */ 1401 U16 Reserved0; /* 0x06 */ 1402 U8 GUID[24]; /* 0x08 */ 1403 U8 Name[16]; /* 0x20 */ 1404 U64 WWID; /* 0x30 */ 1405 U32 Reserved1; /* 0x38 */ 1406 U32 Reserved2; /* 0x3C */ 1407 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1408 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t; 1409 1410 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1411 1412 /**************************************************************************** 1413 * RAID Physical Disk Config Pages 1414 ****************************************************************************/ 1415 1416 /* RAID Physical Disk Page 0 */ 1417 1418 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS 1419 { 1420 U16 Reserved1; /* 0x00 */ 1421 U8 HotSparePool; /* 0x02 */ 1422 U8 Reserved2; /* 0x03 */ 1423 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1424 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t; 1425 1426 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1427 1428 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA 1429 { 1430 U8 VendorID[8]; /* 0x00 */ 1431 U8 ProductID[16]; /* 0x08 */ 1432 U8 ProductRevLevel[4]; /* 0x18 */ 1433 U8 SerialNum[32]; /* 0x1C */ 1434 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1435 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1436 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t; 1437 1438 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 1439 { 1440 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1441 U16 DevHandle; /* 0x04 */ 1442 U8 Reserved1; /* 0x06 */ 1443 U8 PhysDiskNum; /* 0x07 */ 1444 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */ 1445 U32 Reserved2; /* 0x0C */ 1446 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */ 1447 U32 Reserved3; /* 0x4C */ 1448 U8 PhysDiskState; /* 0x50 */ 1449 U8 OfflineReason; /* 0x51 */ 1450 U8 IncompatibleReason; /* 0x52 */ 1451 U8 PhysDiskAttributes; /* 0x53 */ 1452 U32 PhysDiskStatusFlags; /* 0x54 */ 1453 U64 DeviceMaxLBA; /* 0x58 */ 1454 U64 HostMaxLBA; /* 0x60 */ 1455 U64 CoercedMaxLBA; /* 0x68 */ 1456 U16 BlockSize; /* 0x70 */ 1457 U16 Reserved5; /* 0x72 */ 1458 U32 Reserved6; /* 0x74 */ 1459 } MPI2_CONFIG_PAGE_RD_PDISK_0, 1460 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1461 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t; 1462 1463 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1464 1465 /* PhysDiskState defines */ 1466 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1467 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1468 #define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1469 #define MPI2_RAID_PD_STATE_ONLINE (0x03) 1470 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1471 #define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1472 #define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1473 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1474 1475 /* OfflineReason defines */ 1476 #define MPI2_PHYSDISK0_ONLINE (0x00) 1477 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1478 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1479 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1480 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1481 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1482 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1483 1484 /* IncompatibleReason defines */ 1485 #define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1486 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1487 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1488 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1489 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1490 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1491 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 1492 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1493 1494 /* PhysDiskAttributes defines */ 1495 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 1496 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1497 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1498 1499 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 1500 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1501 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1502 1503 /* PhysDiskStatusFlags defines */ 1504 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1505 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1506 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1507 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1508 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1509 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 1510 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 1511 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 1512 1513 /* RAID Physical Disk Page 1 */ 1514 1515 /* 1516 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1517 * one and check the value returned for NumPhysDiskPaths at runtime. 1518 */ 1519 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 1520 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 1521 #endif 1522 1523 typedef struct _MPI2_RAIDPHYSDISK1_PATH 1524 { 1525 U16 DevHandle; /* 0x00 */ 1526 U16 Reserved1; /* 0x02 */ 1527 U64 WWID; /* 0x04 */ 1528 U64 OwnerWWID; /* 0x0C */ 1529 U8 OwnerIdentifier; /* 0x14 */ 1530 U8 Reserved2; /* 0x15 */ 1531 U16 Flags; /* 0x16 */ 1532 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH, 1533 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t; 1534 1535 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 1536 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 1537 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 1538 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 1539 1540 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 1541 { 1542 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1543 U8 NumPhysDiskPaths; /* 0x04 */ 1544 U8 PhysDiskNum; /* 0x05 */ 1545 U16 Reserved1; /* 0x06 */ 1546 U32 Reserved2; /* 0x08 */ 1547 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */ 1548 } MPI2_CONFIG_PAGE_RD_PDISK_1, 1549 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 1550 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t; 1551 1552 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 1553 1554 /**************************************************************************** 1555 * values for fields used by several types of SAS Config Pages 1556 ****************************************************************************/ 1557 1558 /* values for NegotiatedLinkRates fields */ 1559 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 1560 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 1561 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 1562 /* link rates used for Negotiated Physical and Logical Link Rate */ 1563 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 1564 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 1565 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 1566 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 1567 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 1568 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 1569 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 1570 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 1571 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 1572 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 1573 1574 /* values for AttachedPhyInfo fields */ 1575 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 1576 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 1577 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 1578 1579 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 1580 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 1581 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 1582 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 1583 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 1584 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 1585 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 1586 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 1587 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 1588 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 1589 1590 /* values for PhyInfo fields */ 1591 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 1592 1593 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 1594 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 1595 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 1596 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 1597 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 1598 1599 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 1600 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 1601 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 1602 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 1603 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 1604 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 1605 1606 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 1607 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 1608 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 1609 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 1610 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 1611 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 1612 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 1613 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 1614 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 1615 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 1616 1617 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 1618 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 1619 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 1620 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 1621 1622 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 1623 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 1624 1625 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 1626 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 1627 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 1628 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 1629 1630 /* values for SAS ProgrammedLinkRate fields */ 1631 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 1632 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 1633 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 1634 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 1635 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 1636 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 1637 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 1638 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 1639 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 1640 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 1641 1642 /* values for SAS HwLinkRate fields */ 1643 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 1644 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 1645 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 1646 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 1647 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 1648 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 1649 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 1650 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 1651 1652 /**************************************************************************** 1653 * SAS IO Unit Config Pages 1654 ****************************************************************************/ 1655 1656 /* SAS IO Unit Page 0 */ 1657 1658 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA 1659 { 1660 U8 Port; /* 0x00 */ 1661 U8 PortFlags; /* 0x01 */ 1662 U8 PhyFlags; /* 0x02 */ 1663 U8 NegotiatedLinkRate; /* 0x03 */ 1664 U32 ControllerPhyDeviceInfo;/* 0x04 */ 1665 U16 AttachedDevHandle; /* 0x08 */ 1666 U16 ControllerDevHandle; /* 0x0A */ 1667 U32 DiscoveryStatus; /* 0x0C */ 1668 U32 Reserved; /* 0x10 */ 1669 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 1670 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t; 1671 1672 /* 1673 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1674 * one and check the value returned for NumPhys at runtime. 1675 */ 1676 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX 1677 #define MPI2_SAS_IOUNIT0_PHY_MAX (1) 1678 #endif 1679 1680 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 1681 { 1682 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1683 U32 Reserved1; /* 0x08 */ 1684 U8 NumPhys; /* 0x0C */ 1685 U8 Reserved2; /* 0x0D */ 1686 U16 Reserved3; /* 0x0E */ 1687 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */ 1688 } MPI2_CONFIG_PAGE_SASIOUNIT_0, 1689 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 1690 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t; 1691 1692 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 1693 1694 /* values for SAS IO Unit Page 0 PortFlags */ 1695 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 1696 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 1697 1698 /* values for SAS IO Unit Page 0 PhyFlags */ 1699 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 1700 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 1701 1702 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 1703 1704 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 1705 1706 /* values for SAS IO Unit Page 0 DiscoveryStatus */ 1707 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 1708 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 1709 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 1710 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 1711 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 1712 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 1713 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 1714 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 1715 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 1716 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 1717 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 1718 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 1719 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 1720 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 1721 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 1722 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 1723 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 1724 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 1725 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 1726 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 1727 1728 /* SAS IO Unit Page 1 */ 1729 1730 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA 1731 { 1732 U8 Port; /* 0x00 */ 1733 U8 PortFlags; /* 0x01 */ 1734 U8 PhyFlags; /* 0x02 */ 1735 U8 MaxMinLinkRate; /* 0x03 */ 1736 U32 ControllerPhyDeviceInfo; /* 0x04 */ 1737 U16 MaxTargetPortConnectTime; /* 0x08 */ 1738 U16 Reserved1; /* 0x0A */ 1739 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 1740 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t; 1741 1742 /* 1743 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1744 * one and check the value returned for NumPhys at runtime. 1745 */ 1746 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX 1747 #define MPI2_SAS_IOUNIT1_PHY_MAX (1) 1748 #endif 1749 1750 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 1751 { 1752 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1753 U16 ControlFlags; /* 0x08 */ 1754 U16 SASNarrowMaxQueueDepth; /* 0x0A */ 1755 U16 AdditionalControlFlags; /* 0x0C */ 1756 U16 SASWideMaxQueueDepth; /* 0x0E */ 1757 U8 NumPhys; /* 0x10 */ 1758 U8 SATAMaxQDepth; /* 0x11 */ 1759 U8 ReportDeviceMissingDelay; /* 0x12 */ 1760 U8 IODeviceMissingDelay; /* 0x13 */ 1761 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */ 1762 } MPI2_CONFIG_PAGE_SASIOUNIT_1, 1763 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 1764 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t; 1765 1766 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 1767 1768 /* values for SAS IO Unit Page 1 ControlFlags */ 1769 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 1770 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 1771 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 1772 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 1773 1774 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 1775 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 1776 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 1777 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 1778 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 1779 1780 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 1781 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 1782 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 1783 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 1784 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 1785 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 1786 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 1787 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 1788 1789 /* values for SAS IO Unit Page 1 AdditionalControlFlags */ 1790 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 1791 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 1792 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 1793 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 1794 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 1795 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 1796 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 1797 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 1798 1799 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 1800 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 1801 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 1802 1803 /* values for SAS IO Unit Page 1 PortFlags */ 1804 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 1805 1806 /* values for SAS IO Unit Page 1 PhyFlags */ 1807 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 1808 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 1809 1810 /* values for SAS IO Unit Page 1 MaxMinLinkRate */ 1811 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 1812 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 1813 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 1814 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 1815 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 1816 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 1817 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 1818 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 1819 1820 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 1821 1822 /* SAS IO Unit Page 4 */ 1823 1824 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP 1825 { 1826 U8 MaxTargetSpinup; /* 0x00 */ 1827 U8 SpinupDelay; /* 0x01 */ 1828 U16 Reserved1; /* 0x02 */ 1829 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 1830 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t; 1831 1832 /* 1833 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1834 * one and check the value returned for NumPhys at runtime. 1835 */ 1836 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX 1837 #define MPI2_SAS_IOUNIT4_PHY_MAX (4) 1838 #endif 1839 1840 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 1841 { 1842 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1843 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 1844 U32 Reserved1; /* 0x18 */ 1845 U32 Reserved2; /* 0x1C */ 1846 U32 Reserved3; /* 0x20 */ 1847 U8 BootDeviceWaitTime; /* 0x24 */ 1848 U8 Reserved4; /* 0x25 */ 1849 U16 Reserved5; /* 0x26 */ 1850 U8 NumPhys; /* 0x28 */ 1851 U8 PEInitialSpinupDelay; /* 0x29 */ 1852 U8 PEReplyDelay; /* 0x2A */ 1853 U8 Flags; /* 0x2B */ 1854 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */ 1855 } MPI2_CONFIG_PAGE_SASIOUNIT_4, 1856 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 1857 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t; 1858 1859 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 1860 1861 /* defines for Flags field */ 1862 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 1863 1864 /* defines for PHY field */ 1865 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 1866 1867 /* SAS IO Unit Page 5 */ 1868 1869 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 1870 { 1871 U8 ControlFlags; /* 0x00 */ 1872 U8 PortWidthModGroup; /* 0x01 */ 1873 U16 InactivityTimerExponent; /* 0x02 */ 1874 U8 SATAPartialTimeout; /* 0x04 */ 1875 U8 Reserved2; /* 0x05 */ 1876 U8 SATASlumberTimeout; /* 0x06 */ 1877 U8 Reserved3; /* 0x07 */ 1878 U8 SASPartialTimeout; /* 0x08 */ 1879 U8 Reserved4; /* 0x09 */ 1880 U8 SASSlumberTimeout; /* 0x0A */ 1881 U8 Reserved5; /* 0x0B */ 1882 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 1883 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 1884 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t; 1885 1886 /* defines for ControlFlags field */ 1887 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 1888 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 1889 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 1890 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 1891 1892 /* defines for PortWidthModeGroup field */ 1893 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 1894 1895 /* defines for InactivityTimerExponent field */ 1896 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 1897 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 1898 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 1899 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 1900 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 1901 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 1902 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 1903 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 1904 1905 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 1906 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 1907 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 1908 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 1909 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 1910 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 1911 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 1912 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 1913 1914 /* 1915 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1916 * one and check the value returned for NumPhys at runtime. 1917 */ 1918 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX 1919 #define MPI2_SAS_IOUNIT5_PHY_MAX (1) 1920 #endif 1921 1922 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 1923 { 1924 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1925 U8 NumPhys; /* 0x08 */ 1926 U8 Reserved1; /* 0x09 */ 1927 U16 Reserved2; /* 0x0A */ 1928 U32 Reserved3; /* 0x0C */ 1929 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */ 1930 } MPI2_CONFIG_PAGE_SASIOUNIT_5, 1931 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 1932 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t; 1933 1934 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 1935 1936 /* SAS IO Unit Page 6 */ 1937 1938 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 1939 { 1940 U8 CurrentStatus; /* 0x00 */ 1941 U8 CurrentModulation; /* 0x01 */ 1942 U8 CurrentUtilization; /* 0x02 */ 1943 U8 Reserved1; /* 0x03 */ 1944 U32 Reserved2; /* 0x04 */ 1945 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 1946 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 1947 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 1948 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t; 1949 1950 /* defines for CurrentStatus field */ 1951 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 1952 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 1953 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 1954 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 1955 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 1956 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 1957 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 1958 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 1959 1960 /* defines for CurrentModulation field */ 1961 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 1962 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 1963 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 1964 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 1965 1966 /* 1967 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1968 * one and check the value returned for NumGroups at runtime. 1969 */ 1970 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 1971 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 1972 #endif 1973 1974 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 1975 { 1976 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1977 U32 Reserved1; /* 0x08 */ 1978 U32 Reserved2; /* 0x0C */ 1979 U8 NumGroups; /* 0x10 */ 1980 U8 Reserved3; /* 0x11 */ 1981 U16 Reserved4; /* 0x12 */ 1982 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 1983 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */ 1984 } MPI2_CONFIG_PAGE_SASIOUNIT_6, 1985 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 1986 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t; 1987 1988 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 1989 1990 /* SAS IO Unit Page 7 */ 1991 1992 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 1993 { 1994 U8 Flags; /* 0x00 */ 1995 U8 Reserved1; /* 0x01 */ 1996 U16 Reserved2; /* 0x02 */ 1997 U8 Threshold75Pct; /* 0x04 */ 1998 U8 Threshold50Pct; /* 0x05 */ 1999 U8 Threshold25Pct; /* 0x06 */ 2000 U8 Reserved3; /* 0x07 */ 2001 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2002 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2003 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2004 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2005 2006 /* defines for Flags field */ 2007 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2008 2009 /* 2010 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2011 * one and check the value returned for NumGroups at runtime. 2012 */ 2013 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2014 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2015 #endif 2016 2017 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 2018 { 2019 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2020 U8 SamplingInterval; /* 0x08 */ 2021 U8 WindowLength; /* 0x09 */ 2022 U16 Reserved1; /* 0x0A */ 2023 U32 Reserved2; /* 0x0C */ 2024 U32 Reserved3; /* 0x10 */ 2025 U8 NumGroups; /* 0x14 */ 2026 U8 Reserved4; /* 0x15 */ 2027 U16 Reserved5; /* 0x16 */ 2028 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2029 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */ 2030 } MPI2_CONFIG_PAGE_SASIOUNIT_7, 2031 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2032 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t; 2033 2034 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2035 2036 /* SAS IO Unit Page 8 */ 2037 2038 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 2039 { 2040 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2041 U32 Reserved1; /* 0x08 */ 2042 U32 PowerManagementCapabilities; /* 0x0C */ 2043 U32 Reserved2; /* 0x10 */ 2044 } MPI2_CONFIG_PAGE_SASIOUNIT_8, 2045 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2046 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t; 2047 2048 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2049 2050 /* defines for PowerManagementCapabilities field */ 2051 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x000001000) 2052 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x000000800) 2053 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x000000400) 2054 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x000000200) 2055 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x000000100) 2056 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x000000010) 2057 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x000000008) 2058 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x000000004) 2059 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x000000002) 2060 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x000000001) 2061 2062 /**************************************************************************** 2063 * SAS Expander Config Pages 2064 ****************************************************************************/ 2065 2066 /* SAS Expander Page 0 */ 2067 2068 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 2069 { 2070 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2071 U8 PhysicalPort; /* 0x08 */ 2072 U8 ReportGenLength; /* 0x09 */ 2073 U16 EnclosureHandle; /* 0x0A */ 2074 U64 SASAddress; /* 0x0C */ 2075 U32 DiscoveryStatus; /* 0x14 */ 2076 U16 DevHandle; /* 0x18 */ 2077 U16 ParentDevHandle; /* 0x1A */ 2078 U16 ExpanderChangeCount; /* 0x1C */ 2079 U16 ExpanderRouteIndexes; /* 0x1E */ 2080 U8 NumPhys; /* 0x20 */ 2081 U8 SASLevel; /* 0x21 */ 2082 U16 Flags; /* 0x22 */ 2083 U16 STPBusInactivityTimeLimit; /* 0x24 */ 2084 U16 STPMaxConnectTimeLimit; /* 0x26 */ 2085 U16 STP_SMP_NexusLossTime; /* 0x28 */ 2086 U16 MaxNumRoutedSasAddresses; /* 0x2A */ 2087 U64 ActiveZoneManagerSASAddress;/* 0x2C */ 2088 U16 ZoneLockInactivityLimit; /* 0x34 */ 2089 U16 Reserved1; /* 0x36 */ 2090 U8 TimeToReducedFunc; /* 0x38 */ 2091 U8 InitialTimeToReducedFunc; /* 0x39 */ 2092 U8 MaxReducedFuncTime; /* 0x3A */ 2093 U8 Reserved2; /* 0x3B */ 2094 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2095 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t; 2096 2097 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2098 2099 /* values for SAS Expander Page 0 DiscoveryStatus field */ 2100 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2101 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2102 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2103 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2104 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2105 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2106 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2107 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2108 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2109 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2110 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2111 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2112 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2113 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2114 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2115 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2116 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2117 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2118 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2119 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2120 2121 /* values for SAS Expander Page 0 Flags field */ 2122 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2123 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2124 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2125 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2126 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2127 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2128 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2129 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2130 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2131 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2132 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2133 2134 /* SAS Expander Page 1 */ 2135 2136 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 2137 { 2138 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2139 U8 PhysicalPort; /* 0x08 */ 2140 U8 Reserved1; /* 0x09 */ 2141 U16 Reserved2; /* 0x0A */ 2142 U8 NumPhys; /* 0x0C */ 2143 U8 Phy; /* 0x0D */ 2144 U16 NumTableEntriesProgrammed; /* 0x0E */ 2145 U8 ProgrammedLinkRate; /* 0x10 */ 2146 U8 HwLinkRate; /* 0x11 */ 2147 U16 AttachedDevHandle; /* 0x12 */ 2148 U32 PhyInfo; /* 0x14 */ 2149 U32 AttachedDeviceInfo; /* 0x18 */ 2150 U16 ExpanderDevHandle; /* 0x1C */ 2151 U8 ChangeCount; /* 0x1E */ 2152 U8 NegotiatedLinkRate; /* 0x1F */ 2153 U8 PhyIdentifier; /* 0x20 */ 2154 U8 AttachedPhyIdentifier; /* 0x21 */ 2155 U8 Reserved3; /* 0x22 */ 2156 U8 DiscoveryInfo; /* 0x23 */ 2157 U32 AttachedPhyInfo; /* 0x24 */ 2158 U8 ZoneGroup; /* 0x28 */ 2159 U8 SelfConfigStatus; /* 0x29 */ 2160 U16 Reserved4; /* 0x2A */ 2161 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2162 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t; 2163 2164 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2165 2166 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2167 2168 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2169 2170 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2171 2172 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */ 2173 2174 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2175 2176 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2177 2178 /* values for SAS Expander Page 1 DiscoveryInfo field */ 2179 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2180 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2181 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2182 2183 /**************************************************************************** 2184 * SAS Device Config Pages 2185 ****************************************************************************/ 2186 2187 /* SAS Device Page 0 */ 2188 2189 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 2190 { 2191 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2192 U16 Slot; /* 0x08 */ 2193 U16 EnclosureHandle; /* 0x0A */ 2194 U64 SASAddress; /* 0x0C */ 2195 U16 ParentDevHandle; /* 0x14 */ 2196 U8 PhyNum; /* 0x16 */ 2197 U8 AccessStatus; /* 0x17 */ 2198 U16 DevHandle; /* 0x18 */ 2199 U8 AttachedPhyIdentifier; /* 0x1A */ 2200 U8 ZoneGroup; /* 0x1B */ 2201 U32 DeviceInfo; /* 0x1C */ 2202 U16 Flags; /* 0x20 */ 2203 U8 PhysicalPort; /* 0x22 */ 2204 U8 MaxPortConnections; /* 0x23 */ 2205 U64 DeviceName; /* 0x24 */ 2206 U8 PortGroups; /* 0x2C */ 2207 U8 DmaGroup; /* 0x2D */ 2208 U8 ControlGroup; /* 0x2E */ 2209 U8 Reserved1; /* 0x2F */ 2210 U32 Reserved2; /* 0x30 */ 2211 U32 Reserved3; /* 0x34 */ 2212 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2213 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t; 2214 2215 #define MPI2_SASDEVICE0_PAGEVERSION (0x08) 2216 2217 /* values for SAS Device Page 0 AccessStatus field */ 2218 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2219 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2220 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2221 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2222 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2223 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2224 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2225 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2226 /* specific values for SATA Init failures */ 2227 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2228 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2229 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2230 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2231 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2232 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2233 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2234 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2235 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2236 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2237 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2238 2239 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2240 2241 /* values for SAS Device Page 0 Flags field */ 2242 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2243 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2244 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2245 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2246 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2247 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2248 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2249 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2250 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2251 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2252 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2253 2254 /* SAS Device Page 1 */ 2255 2256 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 2257 { 2258 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2259 U32 Reserved1; /* 0x08 */ 2260 U64 SASAddress; /* 0x0C */ 2261 U32 Reserved2; /* 0x14 */ 2262 U16 DevHandle; /* 0x18 */ 2263 U16 Reserved3; /* 0x1A */ 2264 U8 InitialRegDeviceFIS[20];/* 0x1C */ 2265 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2266 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t; 2267 2268 #define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2269 2270 /**************************************************************************** 2271 * SAS PHY Config Pages 2272 ****************************************************************************/ 2273 2274 /* SAS PHY Page 0 */ 2275 2276 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 2277 { 2278 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2279 U16 OwnerDevHandle; /* 0x08 */ 2280 U16 Reserved1; /* 0x0A */ 2281 U16 AttachedDevHandle; /* 0x0C */ 2282 U8 AttachedPhyIdentifier; /* 0x0E */ 2283 U8 Reserved2; /* 0x0F */ 2284 U32 AttachedPhyInfo; /* 0x10 */ 2285 U8 ProgrammedLinkRate; /* 0x14 */ 2286 U8 HwLinkRate; /* 0x15 */ 2287 U8 ChangeCount; /* 0x16 */ 2288 U8 Flags; /* 0x17 */ 2289 U32 PhyInfo; /* 0x18 */ 2290 U8 NegotiatedLinkRate; /* 0x1C */ 2291 U8 Reserved3; /* 0x1D */ 2292 U16 Reserved4; /* 0x1E */ 2293 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2294 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t; 2295 2296 #define MPI2_SASPHY0_PAGEVERSION (0x03) 2297 2298 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2299 2300 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2301 2302 /* values for SAS PHY Page 0 Flags field */ 2303 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2304 2305 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2306 2307 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2308 2309 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2310 2311 /* SAS PHY Page 1 */ 2312 2313 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 2314 { 2315 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2316 U32 Reserved1; /* 0x08 */ 2317 U32 InvalidDwordCount; /* 0x0C */ 2318 U32 RunningDisparityErrorCount; /* 0x10 */ 2319 U32 LossDwordSynchCount; /* 0x14 */ 2320 U32 PhyResetProblemCount; /* 0x18 */ 2321 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 2322 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t; 2323 2324 #define MPI2_SASPHY1_PAGEVERSION (0x01) 2325 2326 /* SAS PHY Page 2 */ 2327 2328 typedef struct _MPI2_SASPHY2_PHY_EVENT 2329 { 2330 U8 PhyEventCode; /* 0x00 */ 2331 U8 Reserved1; /* 0x01 */ 2332 U16 Reserved2; /* 0x02 */ 2333 U32 PhyEventInfo; /* 0x04 */ 2334 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT, 2335 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t; 2336 2337 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 2338 2339 /* 2340 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2341 * one and check the value returned for NumPhyEvents at runtime. 2342 */ 2343 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX 2344 #define MPI2_SASPHY2_PHY_EVENT_MAX (1) 2345 #endif 2346 2347 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 2348 { 2349 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2350 U32 Reserved1; /* 0x08 */ 2351 U8 NumPhyEvents; /* 0x0C */ 2352 U8 Reserved2; /* 0x0D */ 2353 U16 Reserved3; /* 0x0E */ 2354 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */ 2355 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 2356 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t; 2357 2358 #define MPI2_SASPHY2_PAGEVERSION (0x00) 2359 2360 /* SAS PHY Page 3 */ 2361 2362 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG 2363 { 2364 U8 PhyEventCode; /* 0x00 */ 2365 U8 Reserved1; /* 0x01 */ 2366 U16 Reserved2; /* 0x02 */ 2367 U8 CounterType; /* 0x04 */ 2368 U8 ThresholdWindow; /* 0x05 */ 2369 U8 TimeUnits; /* 0x06 */ 2370 U8 Reserved3; /* 0x07 */ 2371 U32 EventThreshold; /* 0x08 */ 2372 U16 ThresholdFlags; /* 0x0C */ 2373 U16 Reserved4; /* 0x0E */ 2374 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 2375 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t; 2376 2377 /* values for PhyEventCode field */ 2378 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2379 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2380 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2381 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2382 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2383 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 2384 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 2385 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 2386 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 2387 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 2388 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 2389 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 2390 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 2391 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 2392 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 2393 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 2394 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 2395 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 2396 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 2397 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 2398 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 2399 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 2400 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 2401 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 2402 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 2403 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 2404 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 2405 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 2406 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 2407 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 2408 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 2409 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 2410 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 2411 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 2412 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 2413 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 2414 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 2415 2416 /* values for the CounterType field */ 2417 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 2418 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 2419 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 2420 2421 /* values for the TimeUnits field */ 2422 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 2423 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 2424 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 2425 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 2426 2427 /* values for the ThresholdFlags field */ 2428 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 2429 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 2430 2431 /* 2432 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2433 * one and check the value returned for NumPhyEvents at runtime. 2434 */ 2435 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX 2436 #define MPI2_SASPHY3_PHY_EVENT_MAX (1) 2437 #endif 2438 2439 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 2440 { 2441 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2442 U32 Reserved1; /* 0x08 */ 2443 U8 NumPhyEvents; /* 0x0C */ 2444 U8 Reserved2; /* 0x0D */ 2445 U16 Reserved3; /* 0x0E */ 2446 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */ 2447 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 2448 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t; 2449 2450 #define MPI2_SASPHY3_PAGEVERSION (0x00) 2451 2452 /* SAS PHY Page 4 */ 2453 2454 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 2455 { 2456 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2457 U16 Reserved1; /* 0x08 */ 2458 U8 Reserved2; /* 0x0A */ 2459 U8 Flags; /* 0x0B */ 2460 U8 InitialFrame[28]; /* 0x0C */ 2461 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 2462 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t; 2463 2464 #define MPI2_SASPHY4_PAGEVERSION (0x00) 2465 2466 /* values for the Flags field */ 2467 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 2468 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 2469 2470 /**************************************************************************** 2471 * SAS Port Config Pages 2472 ****************************************************************************/ 2473 2474 /* SAS Port Page 0 */ 2475 2476 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 2477 { 2478 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2479 U8 PortNumber; /* 0x08 */ 2480 U8 PhysicalPort; /* 0x09 */ 2481 U8 PortWidth; /* 0x0A */ 2482 U8 PhysicalPortWidth; /* 0x0B */ 2483 U8 ZoneGroup; /* 0x0C */ 2484 U8 Reserved1; /* 0x0D */ 2485 U16 Reserved2; /* 0x0E */ 2486 U64 SASAddress; /* 0x10 */ 2487 U32 DeviceInfo; /* 0x18 */ 2488 U32 Reserved3; /* 0x1C */ 2489 U32 Reserved4; /* 0x20 */ 2490 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 2491 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t; 2492 2493 #define MPI2_SASPORT0_PAGEVERSION (0x00) 2494 2495 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 2496 2497 /**************************************************************************** 2498 * SAS Enclosure Config Pages 2499 ****************************************************************************/ 2500 2501 /* SAS Enclosure Page 0 */ 2502 2503 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 2504 { 2505 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2506 U32 Reserved1; /* 0x08 */ 2507 U64 EnclosureLogicalID; /* 0x0C */ 2508 U16 Flags; /* 0x14 */ 2509 U16 EnclosureHandle; /* 0x16 */ 2510 U16 NumSlots; /* 0x18 */ 2511 U16 StartSlot; /* 0x1A */ 2512 U16 Reserved2; /* 0x1C */ 2513 U16 SEPDevHandle; /* 0x1E */ 2514 U32 Reserved3; /* 0x20 */ 2515 U32 Reserved4; /* 0x24 */ 2516 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 2517 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 2518 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t; 2519 2520 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x03) 2521 2522 /* values for SAS Enclosure Page 0 Flags field */ 2523 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 2524 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 2525 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 2526 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 2527 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 2528 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 2529 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 2530 2531 /**************************************************************************** 2532 * Log Config Page 2533 ****************************************************************************/ 2534 2535 /* Log Page 0 */ 2536 2537 /* 2538 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2539 * one and check the value returned for NumLogEntries at runtime. 2540 */ 2541 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 2542 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 2543 #endif 2544 2545 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 2546 2547 typedef struct _MPI2_LOG_0_ENTRY 2548 { 2549 U64 TimeStamp; /* 0x00 */ 2550 U32 Reserved1; /* 0x08 */ 2551 U16 LogSequence; /* 0x0C */ 2552 U16 LogEntryQualifier; /* 0x0E */ 2553 U8 VP_ID; /* 0x10 */ 2554 U8 VF_ID; /* 0x11 */ 2555 U16 Reserved2; /* 0x12 */ 2556 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */ 2557 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY, 2558 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t; 2559 2560 /* values for Log Page 0 LogEntry LogEntryQualifier field */ 2561 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 2562 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 2563 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 2564 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 2565 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 2566 2567 typedef struct _MPI2_CONFIG_PAGE_LOG_0 2568 { 2569 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2570 U32 Reserved1; /* 0x08 */ 2571 U32 Reserved2; /* 0x0C */ 2572 U16 NumLogEntries; /* 0x10 */ 2573 U16 Reserved3; /* 0x12 */ 2574 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */ 2575 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0, 2576 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t; 2577 2578 #define MPI2_LOG_0_PAGEVERSION (0x02) 2579 2580 /**************************************************************************** 2581 * RAID Config Page 2582 ****************************************************************************/ 2583 2584 /* RAID Page 0 */ 2585 2586 /* 2587 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2588 * one and check the value returned for NumElements at runtime. 2589 */ 2590 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 2591 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 2592 #endif 2593 2594 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT 2595 { 2596 U16 ElementFlags; /* 0x00 */ 2597 U16 VolDevHandle; /* 0x02 */ 2598 U8 HotSparePool; /* 0x04 */ 2599 U8 PhysDiskNum; /* 0x05 */ 2600 U16 PhysDiskDevHandle; /* 0x06 */ 2601 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 2602 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 2603 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t; 2604 2605 /* values for the ElementFlags field */ 2606 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 2607 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 2608 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 2609 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 2610 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 2611 2612 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 2613 { 2614 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2615 U8 NumHotSpares; /* 0x08 */ 2616 U8 NumPhysDisks; /* 0x09 */ 2617 U8 NumVolumes; /* 0x0A */ 2618 U8 ConfigNum; /* 0x0B */ 2619 U32 Flags; /* 0x0C */ 2620 U8 ConfigGUID[24]; /* 0x10 */ 2621 U32 Reserved1; /* 0x28 */ 2622 U8 NumElements; /* 0x2C */ 2623 U8 Reserved2; /* 0x2D */ 2624 U16 Reserved3; /* 0x2E */ 2625 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */ 2626 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 2627 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 2628 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t; 2629 2630 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 2631 2632 /* values for RAID Configuration Page 0 Flags field */ 2633 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 2634 2635 /**************************************************************************** 2636 * Driver Persistent Mapping Config Pages 2637 ****************************************************************************/ 2638 2639 /* Driver Persistent Mapping Page 0 */ 2640 2641 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY 2642 { 2643 U64 PhysicalIdentifier; /* 0x00 */ 2644 U16 MappingInformation; /* 0x08 */ 2645 U16 DeviceIndex; /* 0x0A */ 2646 U32 PhysicalBitsMapping; /* 0x0C */ 2647 U32 Reserved1; /* 0x10 */ 2648 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 2649 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 2650 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t; 2651 2652 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 2653 { 2654 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2655 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */ 2656 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 2657 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 2658 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t; 2659 2660 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 2661 2662 /* values for Driver Persistent Mapping Page 0 MappingInformation field */ 2663 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 2664 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 2665 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 2666 2667 /**************************************************************************** 2668 * Ethernet Config Pages 2669 ****************************************************************************/ 2670 2671 /* Ethernet Page 0 */ 2672 2673 /* IP address (union of IPv4 and IPv6) */ 2674 typedef union _MPI2_ETHERNET_IP_ADDR 2675 { 2676 U32 IPv4Addr; 2677 U32 IPv6Addr[4]; 2678 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR, 2679 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t; 2680 2681 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 2682 2683 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 2684 { 2685 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2686 U8 NumInterfaces; /* 0x08 */ 2687 U8 Reserved0; /* 0x09 */ 2688 U16 Reserved1; /* 0x0A */ 2689 U32 Status; /* 0x0C */ 2690 U8 MediaState; /* 0x10 */ 2691 U8 Reserved2; /* 0x11 */ 2692 U16 Reserved3; /* 0x12 */ 2693 U8 MacAddress[6]; /* 0x14 */ 2694 U8 Reserved4; /* 0x1A */ 2695 U8 Reserved5; /* 0x1B */ 2696 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */ 2697 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */ 2698 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */ 2699 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */ 2700 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */ 2701 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */ 2702 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 2703 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 2704 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t; 2705 2706 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 2707 2708 /* values for Ethernet Page 0 Status field */ 2709 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 2710 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 2711 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 2712 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 2713 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 2714 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 2715 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 2716 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 2717 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 2718 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 2719 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 2720 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 2721 2722 /* values for Ethernet Page 0 MediaState field */ 2723 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 2724 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 2725 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 2726 2727 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 2728 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 2729 #define MPI2_ETHPG0_MS_10MBIT (0x01) 2730 #define MPI2_ETHPG0_MS_100MBIT (0x02) 2731 #define MPI2_ETHPG0_MS_1GBIT (0x03) 2732 2733 /* Ethernet Page 1 */ 2734 2735 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 2736 { 2737 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2738 U32 Reserved0; /* 0x08 */ 2739 U32 Flags; /* 0x0C */ 2740 U8 MediaState; /* 0x10 */ 2741 U8 Reserved1; /* 0x11 */ 2742 U16 Reserved2; /* 0x12 */ 2743 U8 MacAddress[6]; /* 0x14 */ 2744 U8 Reserved3; /* 0x1A */ 2745 U8 Reserved4; /* 0x1B */ 2746 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */ 2747 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */ 2748 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */ 2749 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */ 2750 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */ 2751 U32 Reserved5; /* 0x6C */ 2752 U32 Reserved6; /* 0x70 */ 2753 U32 Reserved7; /* 0x74 */ 2754 U32 Reserved8; /* 0x78 */ 2755 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 2756 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 2757 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t; 2758 2759 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 2760 2761 /* values for Ethernet Page 1 Flags field */ 2762 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 2763 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 2764 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 2765 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 2766 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 2767 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 2768 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 2769 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 2770 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 2771 2772 /* values for Ethernet Page 1 MediaState field */ 2773 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 2774 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 2775 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 2776 2777 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 2778 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 2779 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 2780 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 2781 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 2782 2783 /**************************************************************************** 2784 * Extended Manufacturing Config Pages 2785 ****************************************************************************/ 2786 2787 /* 2788 * Generic structure to use for product-specific extended manufacturing pages 2789 * (currently Extended Manufacturing Page 40 through Extended Manufacturing 2790 * Page 60). 2791 */ 2792 2793 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS 2794 { 2795 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2796 U32 ProductSpecificInfo; /* 0x08 */ 2797 } MPI2_CONFIG_PAGE_EXT_MAN_PS, 2798 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 2799 Mpi2ExtManufacturingPagePS_t, MPI2_POINTER pMpi2ExtManufacturingPagePS_t; 2800 2801 /* PageVersion should be provided by product-specific code */ 2802 2803 #endif 2804