1 /*- 2 * Copyright (c) 2006-2015 LSI Corp. 3 * Copyright (c) 2013-2015 Avago Technologies 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD 28 * 29 * $FreeBSD$ 30 */ 31 32 /* 33 * Copyright (c) 2006-2015 LSI Corporation. 34 * Copyright (c) 2013-2015 Avago Technologies 35 * 36 * 37 * Name: mpi2_cnfg.h 38 * Title: MPI Configuration messages and pages 39 * Creation Date: November 10, 2006 40 * 41 * mpi2_cnfg.h Version: 02.00.17 42 * 43 * Version History 44 * --------------- 45 * 46 * Date Version Description 47 * -------- -------- ------------------------------------------------------ 48 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 49 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 50 * Added Manufacturing Page 11. 51 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 52 * define. 53 * 06-26-07 02.00.02 Adding generic structure for product-specific 54 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 55 * Rework of BIOS Page 2 configuration page. 56 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 57 * forms. 58 * Added configuration pages IOC Page 8 and Driver 59 * Persistent Mapping Page 0. 60 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 61 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 62 * RAID Physical Disk Pages 0 and 1, RAID Configuration 63 * Page 0). 64 * Added new value for AccessStatus field of SAS Device 65 * Page 0 (_SATA_NEEDS_INITIALIZATION). 66 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 67 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 68 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 69 * NVDATA. 70 * Modified IOC Page 7 to use masks and added field for 71 * SASBroadcastPrimitiveMasks. 72 * Added MPI2_CONFIG_PAGE_BIOS_4. 73 * Added MPI2_CONFIG_PAGE_LOG_0. 74 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 75 * Added SAS Device IDs. 76 * Updated Integrated RAID configuration pages including 77 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 78 * Page 0. 79 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 80 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 81 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 82 * Added missing MaxNumRoutedSasAddresses field to 83 * MPI2_CONFIG_PAGE_EXPANDER_0. 84 * Added SAS Port Page 0. 85 * Modified structure layout for 86 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 87 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 88 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 89 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 90 * to 0x000000FF. 91 * Added two new values for the Physical Disk Coercion Size 92 * bits in the Flags field of Manufacturing Page 4. 93 * Added product-specific Manufacturing pages 16 to 31. 94 * Modified Flags bits for controlling write cache on SATA 95 * drives in IO Unit Page 1. 96 * Added new bit to AdditionalControlFlags of SAS IO Unit 97 * Page 1 to control Invalid Topology Correction. 98 * Added additional defines for RAID Volume Page 0 99 * VolumeStatusFlags field. 100 * Modified meaning of RAID Volume Page 0 VolumeSettings 101 * define for auto-configure of hot-swap drives. 102 * Added SupportedPhysDisks field to RAID Volume Page 1 and 103 * added related defines. 104 * Added PhysDiskAttributes field (and related defines) to 105 * RAID Physical Disk Page 0. 106 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 107 * Added three new DiscoveryStatus bits for SAS IO Unit 108 * Page 0 and SAS Expander Page 0. 109 * Removed multiplexing information from SAS IO Unit pages. 110 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 111 * Removed Zone Address Resolved bit from PhyInfo and from 112 * Expander Page 0 Flags field. 113 * Added two new AccessStatus values to SAS Device Page 0 114 * for indicating routing problems. Added 3 reserved words 115 * to this page. 116 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 117 * Inserted missing reserved field into structure for IOC 118 * Page 6. 119 * Added more pending task bits to RAID Volume Page 0 120 * VolumeStatusFlags defines. 121 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 122 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 123 * and SAS Expander Page 0 to flag a downstream initiator 124 * when in simplified routing mode. 125 * Removed SATA Init Failure defines for DiscoveryStatus 126 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 127 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 128 * Added PortGroups, DmaGroup, and ControlGroup fields to 129 * SAS Device Page 0. 130 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 131 * Unit Page 6. 132 * Added expander reduced functionality data to SAS 133 * Expander Page 0. 134 * Added SAS PHY Page 2 and SAS PHY Page 3. 135 * 07-30-09 02.00.12 Added IO Unit Page 7. 136 * Added new device ids. 137 * Added SAS IO Unit Page 5. 138 * Added partial and slumber power management capable flags 139 * to SAS Device Page 0 Flags field. 140 * Added PhyInfo defines for power condition. 141 * Added Ethernet configuration pages. 142 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 143 * Added SAS PHY Page 4 structure and defines. 144 * 02-10-10 02.00.14 Modified the comments for the configuration page 145 * structures that contain an array of data. The host 146 * should use the "count" field in the page data (e.g. the 147 * NumPhys field) to determine the number of valid elements 148 * in the array. 149 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 150 * Added PowerManagementCapabilities to IO Unit Page 7. 151 * Added PortWidthModGroup field to 152 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 153 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 154 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 155 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 156 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 157 * define. 158 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 159 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 160 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 161 * defines. 162 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 163 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 164 * the Pinout field. 165 * Added BoardTemperature and BoardTemperatureUnits fields 166 * to MPI2_CONFIG_PAGE_IO_UNIT_7. 167 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 168 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 169 * -------------------------------------------------------------------------- 170 */ 171 172 #ifndef MPI2_CNFG_H 173 #define MPI2_CNFG_H 174 175 /***************************************************************************** 176 * Configuration Page Header and defines 177 *****************************************************************************/ 178 179 /* Config Page Header */ 180 typedef struct _MPI2_CONFIG_PAGE_HEADER 181 { 182 U8 PageVersion; /* 0x00 */ 183 U8 PageLength; /* 0x01 */ 184 U8 PageNumber; /* 0x02 */ 185 U8 PageType; /* 0x03 */ 186 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER, 187 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t; 188 189 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION 190 { 191 MPI2_CONFIG_PAGE_HEADER Struct; 192 U8 Bytes[4]; 193 U16 Word16[2]; 194 U32 Word32; 195 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 196 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion; 197 198 /* Extended Config Page Header */ 199 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER 200 { 201 U8 PageVersion; /* 0x00 */ 202 U8 Reserved1; /* 0x01 */ 203 U8 PageNumber; /* 0x02 */ 204 U8 PageType; /* 0x03 */ 205 U16 ExtPageLength; /* 0x04 */ 206 U8 ExtPageType; /* 0x06 */ 207 U8 Reserved2; /* 0x07 */ 208 } MPI2_CONFIG_EXTENDED_PAGE_HEADER, 209 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 210 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t; 211 212 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION 213 { 214 MPI2_CONFIG_PAGE_HEADER Struct; 215 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 216 U8 Bytes[8]; 217 U16 Word16[4]; 218 U32 Word32[2]; 219 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 220 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion; 221 222 223 /* PageType field values */ 224 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 225 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 226 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 227 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 228 229 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 230 #define MPI2_CONFIG_PAGETYPE_IOC (0x01) 231 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 232 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 233 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 234 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 235 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 236 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 237 238 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 239 240 241 /* ExtPageType field values */ 242 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 243 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 244 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 245 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 246 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 247 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 248 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 249 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 250 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 251 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 252 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 253 254 255 /***************************************************************************** 256 * PageAddress defines 257 *****************************************************************************/ 258 259 /* RAID Volume PageAddress format */ 260 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 261 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 262 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 263 264 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 265 266 267 /* RAID Physical Disk PageAddress format */ 268 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 269 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 270 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 271 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 272 273 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 274 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 275 276 277 /* SAS Expander PageAddress format */ 278 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 279 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 280 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 281 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 282 283 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 284 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 285 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 286 287 288 /* SAS Device PageAddress format */ 289 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 290 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 291 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 292 293 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 294 295 296 /* SAS PHY PageAddress format */ 297 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 298 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 299 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 300 301 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 302 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 303 304 305 /* SAS Port PageAddress format */ 306 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 307 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 308 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 309 310 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 311 312 313 /* SAS Enclosure PageAddress format */ 314 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 315 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 316 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 317 318 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 319 320 321 /* RAID Configuration PageAddress format */ 322 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 323 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 324 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 325 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 326 327 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 328 329 330 /* Driver Persistent Mapping PageAddress format */ 331 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 332 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 333 334 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 335 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 336 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 337 338 339 /* Ethernet PageAddress format */ 340 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 341 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 342 343 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 344 345 346 347 /**************************************************************************** 348 * Configuration messages 349 ****************************************************************************/ 350 351 /* Configuration Request Message */ 352 typedef struct _MPI2_CONFIG_REQUEST 353 { 354 U8 Action; /* 0x00 */ 355 U8 SGLFlags; /* 0x01 */ 356 U8 ChainOffset; /* 0x02 */ 357 U8 Function; /* 0x03 */ 358 U16 ExtPageLength; /* 0x04 */ 359 U8 ExtPageType; /* 0x06 */ 360 U8 MsgFlags; /* 0x07 */ 361 U8 VP_ID; /* 0x08 */ 362 U8 VF_ID; /* 0x09 */ 363 U16 Reserved1; /* 0x0A */ 364 U32 Reserved2; /* 0x0C */ 365 U32 Reserved3; /* 0x10 */ 366 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 367 U32 PageAddress; /* 0x18 */ 368 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */ 369 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST, 370 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t; 371 372 /* values for the Action field */ 373 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 374 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 375 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 376 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 377 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 378 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 379 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 380 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 381 382 /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 383 384 385 /* Config Reply Message */ 386 typedef struct _MPI2_CONFIG_REPLY 387 { 388 U8 Action; /* 0x00 */ 389 U8 SGLFlags; /* 0x01 */ 390 U8 MsgLength; /* 0x02 */ 391 U8 Function; /* 0x03 */ 392 U16 ExtPageLength; /* 0x04 */ 393 U8 ExtPageType; /* 0x06 */ 394 U8 MsgFlags; /* 0x07 */ 395 U8 VP_ID; /* 0x08 */ 396 U8 VF_ID; /* 0x09 */ 397 U16 Reserved1; /* 0x0A */ 398 U16 Reserved2; /* 0x0C */ 399 U16 IOCStatus; /* 0x0E */ 400 U32 IOCLogInfo; /* 0x10 */ 401 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 402 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY, 403 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t; 404 405 406 407 /***************************************************************************** 408 * 409 * C o n f i g u r a t i o n P a g e s 410 * 411 *****************************************************************************/ 412 413 /**************************************************************************** 414 * Manufacturing Config pages 415 ****************************************************************************/ 416 417 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 418 419 /* SAS */ 420 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 421 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 422 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 423 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 424 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 425 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 426 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 427 428 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 429 430 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 431 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 432 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 433 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 434 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 435 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 436 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 437 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 438 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 439 440 441 442 443 /* Manufacturing Page 0 */ 444 445 typedef struct _MPI2_CONFIG_PAGE_MAN_0 446 { 447 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 448 U8 ChipName[16]; /* 0x04 */ 449 U8 ChipRevision[8]; /* 0x14 */ 450 U8 BoardName[16]; /* 0x1C */ 451 U8 BoardAssembly[16]; /* 0x2C */ 452 U8 BoardTracerNumber[16]; /* 0x3C */ 453 } MPI2_CONFIG_PAGE_MAN_0, 454 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0, 455 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t; 456 457 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 458 459 460 /* Manufacturing Page 1 */ 461 462 typedef struct _MPI2_CONFIG_PAGE_MAN_1 463 { 464 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 465 U8 VPD[256]; /* 0x04 */ 466 } MPI2_CONFIG_PAGE_MAN_1, 467 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1, 468 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t; 469 470 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 471 472 473 typedef struct _MPI2_CHIP_REVISION_ID 474 { 475 U16 DeviceID; /* 0x00 */ 476 U8 PCIRevisionID; /* 0x02 */ 477 U8 Reserved; /* 0x03 */ 478 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID, 479 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t; 480 481 482 /* Manufacturing Page 2 */ 483 484 /* 485 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 486 * one and check Header.PageLength at runtime. 487 */ 488 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 489 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 490 #endif 491 492 typedef struct _MPI2_CONFIG_PAGE_MAN_2 493 { 494 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 495 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 496 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */ 497 } MPI2_CONFIG_PAGE_MAN_2, 498 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2, 499 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t; 500 501 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 502 503 504 /* Manufacturing Page 3 */ 505 506 /* 507 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 508 * one and check Header.PageLength at runtime. 509 */ 510 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS 511 #define MPI2_MAN_PAGE_3_INFO_WORDS (1) 512 #endif 513 514 typedef struct _MPI2_CONFIG_PAGE_MAN_3 515 { 516 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 517 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 518 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */ 519 } MPI2_CONFIG_PAGE_MAN_3, 520 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3, 521 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t; 522 523 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 524 525 526 /* Manufacturing Page 4 */ 527 528 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS 529 { 530 U8 PowerSaveFlags; /* 0x00 */ 531 U8 InternalOperationsSleepTime; /* 0x01 */ 532 U8 InternalOperationsRunTime; /* 0x02 */ 533 U8 HostIdleTime; /* 0x03 */ 534 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 535 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 536 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t; 537 538 /* defines for the PowerSaveFlags field */ 539 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 540 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 541 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 542 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 543 544 typedef struct _MPI2_CONFIG_PAGE_MAN_4 545 { 546 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 547 U32 Reserved1; /* 0x04 */ 548 U32 Flags; /* 0x08 */ 549 U8 InquirySize; /* 0x0C */ 550 U8 Reserved2; /* 0x0D */ 551 U16 Reserved3; /* 0x0E */ 552 U8 InquiryData[56]; /* 0x10 */ 553 U32 RAID0VolumeSettings; /* 0x48 */ 554 U32 RAID1EVolumeSettings; /* 0x4C */ 555 U32 RAID1VolumeSettings; /* 0x50 */ 556 U32 RAID10VolumeSettings; /* 0x54 */ 557 U32 Reserved4; /* 0x58 */ 558 U32 Reserved5; /* 0x5C */ 559 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */ 560 U8 MaxOCEDisks; /* 0x64 */ 561 U8 ResyncRate; /* 0x65 */ 562 U16 DataScrubDuration; /* 0x66 */ 563 U8 MaxHotSpares; /* 0x68 */ 564 U8 MaxPhysDisksPerVol; /* 0x69 */ 565 U8 MaxPhysDisks; /* 0x6A */ 566 U8 MaxVolumes; /* 0x6B */ 567 } MPI2_CONFIG_PAGE_MAN_4, 568 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4, 569 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t; 570 571 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 572 573 /* Manufacturing Page 4 Flags field */ 574 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 575 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 576 577 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 578 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 579 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 580 581 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 582 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 583 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 584 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 585 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 586 587 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 588 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 589 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 590 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 591 592 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 593 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 594 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 595 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 596 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 597 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 598 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 599 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 600 601 602 /* Manufacturing Page 5 */ 603 604 /* 605 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 606 * one and check the value returned for NumPhys at runtime. 607 */ 608 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 609 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 610 #endif 611 612 typedef struct _MPI2_MANUFACTURING5_ENTRY 613 { 614 U64 WWID; /* 0x00 */ 615 U64 DeviceName; /* 0x08 */ 616 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY, 617 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t; 618 619 typedef struct _MPI2_CONFIG_PAGE_MAN_5 620 { 621 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 622 U8 NumPhys; /* 0x04 */ 623 U8 Reserved1; /* 0x05 */ 624 U16 Reserved2; /* 0x06 */ 625 U32 Reserved3; /* 0x08 */ 626 U32 Reserved4; /* 0x0C */ 627 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */ 628 } MPI2_CONFIG_PAGE_MAN_5, 629 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5, 630 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t; 631 632 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 633 634 635 /* Manufacturing Page 6 */ 636 637 typedef struct _MPI2_CONFIG_PAGE_MAN_6 638 { 639 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 640 U32 ProductSpecificInfo;/* 0x04 */ 641 } MPI2_CONFIG_PAGE_MAN_6, 642 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6, 643 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t; 644 645 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 646 647 648 /* Manufacturing Page 7 */ 649 650 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO 651 { 652 U32 Pinout; /* 0x00 */ 653 U8 Connector[16]; /* 0x04 */ 654 U8 Location; /* 0x14 */ 655 U8 ReceptacleID; /* 0x15 */ 656 U16 Slot; /* 0x16 */ 657 U32 Reserved2; /* 0x18 */ 658 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 659 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t; 660 661 /* defines for the Pinout field */ 662 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 663 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 664 665 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 666 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 667 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 668 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 669 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 670 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 671 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 672 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 673 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 674 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 675 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 676 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 677 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 678 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 679 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 680 681 /* defines for the Location field */ 682 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 683 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 684 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 685 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 686 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 687 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 688 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 689 690 /* 691 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 692 * one and check the value returned for NumPhys at runtime. 693 */ 694 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 695 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 696 #endif 697 698 typedef struct _MPI2_CONFIG_PAGE_MAN_7 699 { 700 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 701 U32 Reserved1; /* 0x04 */ 702 U32 Reserved2; /* 0x08 */ 703 U32 Flags; /* 0x0C */ 704 U8 EnclosureName[16]; /* 0x10 */ 705 U8 NumPhys; /* 0x20 */ 706 U8 Reserved3; /* 0x21 */ 707 U16 Reserved4; /* 0x22 */ 708 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */ 709 } MPI2_CONFIG_PAGE_MAN_7, 710 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7, 711 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t; 712 713 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 714 715 /* defines for the Flags field */ 716 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 717 718 719 /* 720 * Generic structure to use for product-specific manufacturing pages 721 * (currently Manufacturing Page 8 through Manufacturing Page 31). 722 */ 723 724 typedef struct _MPI2_CONFIG_PAGE_MAN_PS 725 { 726 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 727 U32 ProductSpecificInfo;/* 0x04 */ 728 } MPI2_CONFIG_PAGE_MAN_PS, 729 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS, 730 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t; 731 732 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 733 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 734 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 735 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 736 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 737 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 738 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 739 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 740 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 741 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 742 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 743 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 744 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 745 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 746 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 747 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 748 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 749 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 750 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 751 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 752 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 753 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 754 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 755 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 756 757 758 /**************************************************************************** 759 * IO Unit Config Pages 760 ****************************************************************************/ 761 762 /* IO Unit Page 0 */ 763 764 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 765 { 766 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 767 U64 UniqueValue; /* 0x04 */ 768 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */ 769 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */ 770 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 771 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t; 772 773 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 774 775 776 /* IO Unit Page 1 */ 777 778 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 779 { 780 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 781 U32 Flags; /* 0x04 */ 782 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 783 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t; 784 785 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 786 787 /* IO Unit Page 1 Flags defines */ 788 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 789 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 790 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 791 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 792 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 793 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 794 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 795 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 796 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 797 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 798 799 800 /* IO Unit Page 3 */ 801 802 /* 803 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 804 * one and check the value returned for GPIOCount at runtime. 805 */ 806 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 807 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 808 #endif 809 810 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 811 { 812 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 813 U8 GPIOCount; /* 0x04 */ 814 U8 Reserved1; /* 0x05 */ 815 U16 Reserved2; /* 0x06 */ 816 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */ 817 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 818 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t; 819 820 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 821 822 /* defines for IO Unit Page 3 GPIOVal field */ 823 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 824 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 825 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 826 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 827 828 829 /* IO Unit Page 5 */ 830 831 /* 832 * Upper layer code (drivers, utilities, etc.) should leave this define set to 833 * one and check the value returned for NumDmaEngines at runtime. 834 */ 835 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 836 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 837 #endif 838 839 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 840 { 841 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 842 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */ 843 U64 RaidAcceleratorBufferSize; /* 0x0C */ 844 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */ 845 U8 RAControlSize; /* 0x1C */ 846 U8 NumDmaEngines; /* 0x1D */ 847 U8 RAMinControlSize; /* 0x1E */ 848 U8 RAMaxControlSize; /* 0x1F */ 849 U32 Reserved1; /* 0x20 */ 850 U32 Reserved2; /* 0x24 */ 851 U32 Reserved3; /* 0x28 */ 852 U32 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */ 853 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 854 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t; 855 856 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 857 858 /* defines for IO Unit Page 5 DmaEngineCapabilities field */ 859 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFF00) 860 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 861 862 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 863 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 864 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 865 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 866 867 868 /* IO Unit Page 6 */ 869 870 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 871 { 872 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 873 U16 Flags; /* 0x04 */ 874 U8 RAHostControlSize; /* 0x06 */ 875 U8 Reserved0; /* 0x07 */ 876 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */ 877 U32 Reserved1; /* 0x10 */ 878 U32 Reserved2; /* 0x14 */ 879 U32 Reserved3; /* 0x18 */ 880 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 881 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t; 882 883 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 884 885 /* defines for IO Unit Page 6 Flags field */ 886 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 887 888 889 /* IO Unit Page 7 */ 890 891 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 892 { 893 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 894 U16 Reserved1; /* 0x04 */ 895 U8 PCIeWidth; /* 0x06 */ 896 U8 PCIeSpeed; /* 0x07 */ 897 U32 ProcessorState; /* 0x08 */ 898 U32 PowerManagementCapabilities; /* 0x0C */ 899 U16 IOCTemperature; /* 0x10 */ 900 U8 IOCTemperatureUnits; /* 0x12 */ 901 U8 IOCSpeed; /* 0x13 */ 902 U16 BoardTemperature; /* 0x14 */ 903 U8 BoardTemperatureUnits; /* 0x16 */ 904 U8 Reserved3; /* 0x17 */ 905 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 906 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t; 907 908 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x02) 909 910 /* defines for IO Unit Page 7 PCIeWidth field */ 911 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 912 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 913 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 914 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 915 916 /* defines for IO Unit Page 7 PCIeSpeed field */ 917 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 918 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 919 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 920 921 /* defines for IO Unit Page 7 ProcessorState field */ 922 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 923 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 924 925 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 926 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 927 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 928 929 /* defines for IO Unit Page 7 PowerManagementCapabilities field */ 930 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 931 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 932 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 933 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) 934 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) 935 936 /* defines for IO Unit Page 7 IOCTemperatureUnits field */ 937 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 938 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 939 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 940 941 /* defines for IO Unit Page 7 IOCSpeed field */ 942 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 943 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 944 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 945 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 946 947 /* defines for IO Unit Page 7 BoardTemperatureUnits field */ 948 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 949 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 950 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 951 952 953 954 /**************************************************************************** 955 * IOC Config Pages 956 ****************************************************************************/ 957 958 /* IOC Page 0 */ 959 960 typedef struct _MPI2_CONFIG_PAGE_IOC_0 961 { 962 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 963 U32 Reserved1; /* 0x04 */ 964 U32 Reserved2; /* 0x08 */ 965 U16 VendorID; /* 0x0C */ 966 U16 DeviceID; /* 0x0E */ 967 U8 RevisionID; /* 0x10 */ 968 U8 Reserved3; /* 0x11 */ 969 U16 Reserved4; /* 0x12 */ 970 U32 ClassCode; /* 0x14 */ 971 U16 SubsystemVendorID; /* 0x18 */ 972 U16 SubsystemID; /* 0x1A */ 973 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0, 974 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t; 975 976 #define MPI2_IOCPAGE0_PAGEVERSION (0x02) 977 978 979 /* IOC Page 1 */ 980 981 typedef struct _MPI2_CONFIG_PAGE_IOC_1 982 { 983 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 984 U32 Flags; /* 0x04 */ 985 U32 CoalescingTimeout; /* 0x08 */ 986 U8 CoalescingDepth; /* 0x0C */ 987 U8 PCISlotNum; /* 0x0D */ 988 U8 PCIBusNum; /* 0x0E */ 989 U8 PCIDomainSegment; /* 0x0F */ 990 U32 Reserved1; /* 0x10 */ 991 U32 Reserved2; /* 0x14 */ 992 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1, 993 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t; 994 995 #define MPI2_IOCPAGE1_PAGEVERSION (0x05) 996 997 /* defines for IOC Page 1 Flags field */ 998 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 999 1000 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1001 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 1002 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 1003 1004 /* IOC Page 6 */ 1005 1006 typedef struct _MPI2_CONFIG_PAGE_IOC_6 1007 { 1008 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1009 U32 CapabilitiesFlags; /* 0x04 */ 1010 U8 MaxDrivesRAID0; /* 0x08 */ 1011 U8 MaxDrivesRAID1; /* 0x09 */ 1012 U8 MaxDrivesRAID1E; /* 0x0A */ 1013 U8 MaxDrivesRAID10; /* 0x0B */ 1014 U8 MinDrivesRAID0; /* 0x0C */ 1015 U8 MinDrivesRAID1; /* 0x0D */ 1016 U8 MinDrivesRAID1E; /* 0x0E */ 1017 U8 MinDrivesRAID10; /* 0x0F */ 1018 U32 Reserved1; /* 0x10 */ 1019 U8 MaxGlobalHotSpares; /* 0x14 */ 1020 U8 MaxPhysDisks; /* 0x15 */ 1021 U8 MaxVolumes; /* 0x16 */ 1022 U8 MaxConfigs; /* 0x17 */ 1023 U8 MaxOCEDisks; /* 0x18 */ 1024 U8 Reserved2; /* 0x19 */ 1025 U16 Reserved3; /* 0x1A */ 1026 U32 SupportedStripeSizeMapRAID0; /* 0x1C */ 1027 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */ 1028 U32 SupportedStripeSizeMapRAID10; /* 0x24 */ 1029 U32 Reserved4; /* 0x28 */ 1030 U32 Reserved5; /* 0x2C */ 1031 U16 DefaultMetadataSize; /* 0x30 */ 1032 U16 Reserved6; /* 0x32 */ 1033 U16 MaxBadBlockTableEntries; /* 0x34 */ 1034 U16 Reserved7; /* 0x36 */ 1035 U32 IRNvsramVersion; /* 0x38 */ 1036 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6, 1037 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t; 1038 1039 #define MPI2_IOCPAGE6_PAGEVERSION (0x04) 1040 1041 /* defines for IOC Page 6 CapabilitiesFlags */ 1042 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1043 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1044 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1045 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1046 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1047 1048 1049 /* IOC Page 7 */ 1050 1051 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1052 1053 typedef struct _MPI2_CONFIG_PAGE_IOC_7 1054 { 1055 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1056 U32 Reserved1; /* 0x04 */ 1057 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */ 1058 U16 SASBroadcastPrimitiveMasks; /* 0x18 */ 1059 U16 Reserved2; /* 0x1A */ 1060 U32 Reserved3; /* 0x1C */ 1061 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7, 1062 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t; 1063 1064 #define MPI2_IOCPAGE7_PAGEVERSION (0x01) 1065 1066 1067 /* IOC Page 8 */ 1068 1069 typedef struct _MPI2_CONFIG_PAGE_IOC_8 1070 { 1071 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1072 U8 NumDevsPerEnclosure; /* 0x04 */ 1073 U8 Reserved1; /* 0x05 */ 1074 U16 Reserved2; /* 0x06 */ 1075 U16 MaxPersistentEntries; /* 0x08 */ 1076 U16 MaxNumPhysicalMappedIDs; /* 0x0A */ 1077 U16 Flags; /* 0x0C */ 1078 U16 Reserved3; /* 0x0E */ 1079 U16 IRVolumeMappingFlags; /* 0x10 */ 1080 U16 Reserved4; /* 0x12 */ 1081 U32 Reserved5; /* 0x14 */ 1082 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8, 1083 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t; 1084 1085 #define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1086 1087 /* defines for IOC Page 8 Flags field */ 1088 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1089 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1090 1091 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1092 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1093 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1094 1095 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1096 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1097 1098 /* defines for IOC Page 8 IRVolumeMappingFlags */ 1099 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1100 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1101 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1102 1103 1104 /**************************************************************************** 1105 * BIOS Config Pages 1106 ****************************************************************************/ 1107 1108 /* BIOS Page 1 */ 1109 1110 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 1111 { 1112 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1113 U32 BiosOptions; /* 0x04 */ 1114 U32 IOCSettings; /* 0x08 */ 1115 U32 Reserved1; /* 0x0C */ 1116 U32 DeviceSettings; /* 0x10 */ 1117 U16 NumberOfDevices; /* 0x14 */ 1118 U16 Reserved2; /* 0x16 */ 1119 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */ 1120 U16 IOTimeoutSequential; /* 0x1A */ 1121 U16 IOTimeoutOther; /* 0x1C */ 1122 U16 IOTimeoutBlockDevicesRM; /* 0x1E */ 1123 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1, 1124 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t; 1125 1126 #define MPI2_BIOSPAGE1_PAGEVERSION (0x04) 1127 1128 /* values for BIOS Page 1 BiosOptions field */ 1129 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1130 1131 /* values for BIOS Page 1 IOCSettings field */ 1132 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1133 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1134 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1135 1136 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1137 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1138 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1139 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1140 1141 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1142 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1143 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1144 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1145 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1146 1147 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1148 1149 /* values for BIOS Page 1 DeviceSettings field */ 1150 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1151 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1152 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1153 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1154 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1155 1156 1157 /* BIOS Page 2 */ 1158 1159 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER 1160 { 1161 U32 Reserved1; /* 0x00 */ 1162 U32 Reserved2; /* 0x04 */ 1163 U32 Reserved3; /* 0x08 */ 1164 U32 Reserved4; /* 0x0C */ 1165 U32 Reserved5; /* 0x10 */ 1166 U32 Reserved6; /* 0x14 */ 1167 } MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1168 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1169 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t; 1170 1171 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID 1172 { 1173 U64 SASAddress; /* 0x00 */ 1174 U8 LUN[8]; /* 0x08 */ 1175 U32 Reserved1; /* 0x10 */ 1176 U32 Reserved2; /* 0x14 */ 1177 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1178 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t; 1179 1180 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT 1181 { 1182 U64 EnclosureLogicalID; /* 0x00 */ 1183 U32 Reserved1; /* 0x08 */ 1184 U32 Reserved2; /* 0x0C */ 1185 U16 SlotNumber; /* 0x10 */ 1186 U16 Reserved3; /* 0x12 */ 1187 U32 Reserved4; /* 0x14 */ 1188 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1189 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1190 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t; 1191 1192 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME 1193 { 1194 U64 DeviceName; /* 0x00 */ 1195 U8 LUN[8]; /* 0x08 */ 1196 U32 Reserved1; /* 0x10 */ 1197 U32 Reserved2; /* 0x14 */ 1198 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1199 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t; 1200 1201 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE 1202 { 1203 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1204 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1205 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1206 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1207 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1208 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t; 1209 1210 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 1211 { 1212 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1213 U32 Reserved1; /* 0x04 */ 1214 U32 Reserved2; /* 0x08 */ 1215 U32 Reserved3; /* 0x0C */ 1216 U32 Reserved4; /* 0x10 */ 1217 U32 Reserved5; /* 0x14 */ 1218 U32 Reserved6; /* 0x18 */ 1219 U8 ReqBootDeviceForm; /* 0x1C */ 1220 U8 Reserved7; /* 0x1D */ 1221 U16 Reserved8; /* 0x1E */ 1222 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */ 1223 U8 ReqAltBootDeviceForm; /* 0x38 */ 1224 U8 Reserved9; /* 0x39 */ 1225 U16 Reserved10; /* 0x3A */ 1226 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */ 1227 U8 CurrentBootDeviceForm; /* 0x58 */ 1228 U8 Reserved11; /* 0x59 */ 1229 U16 Reserved12; /* 0x5A */ 1230 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */ 1231 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2, 1232 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t; 1233 1234 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1235 1236 /* values for BIOS Page 2 BootDeviceForm fields */ 1237 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1238 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1239 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1240 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1241 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1242 1243 1244 /* BIOS Page 3 */ 1245 1246 typedef struct _MPI2_ADAPTER_INFO 1247 { 1248 U8 PciBusNumber; /* 0x00 */ 1249 U8 PciDeviceAndFunctionNumber; /* 0x01 */ 1250 U16 AdapterFlags; /* 0x02 */ 1251 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO, 1252 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t; 1253 1254 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1255 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1256 1257 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 1258 { 1259 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1260 U32 GlobalFlags; /* 0x04 */ 1261 U32 BiosVersion; /* 0x08 */ 1262 MPI2_ADAPTER_INFO AdapterOrder[4]; /* 0x0C */ 1263 U32 Reserved1; /* 0x1C */ 1264 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3, 1265 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t; 1266 1267 #define MPI2_BIOSPAGE3_PAGEVERSION (0x00) 1268 1269 /* values for BIOS Page 3 GlobalFlags */ 1270 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1271 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1272 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1273 1274 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1275 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1276 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1277 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1278 1279 1280 /* BIOS Page 4 */ 1281 1282 /* 1283 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1284 * one and check the value returned for NumPhys at runtime. 1285 */ 1286 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1287 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1288 #endif 1289 1290 typedef struct _MPI2_BIOS4_ENTRY 1291 { 1292 U64 ReassignmentWWID; /* 0x00 */ 1293 U64 ReassignmentDeviceName; /* 0x08 */ 1294 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY, 1295 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t; 1296 1297 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 1298 { 1299 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1300 U8 NumPhys; /* 0x04 */ 1301 U8 Reserved1; /* 0x05 */ 1302 U16 Reserved2; /* 0x06 */ 1303 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */ 1304 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4, 1305 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t; 1306 1307 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1308 1309 1310 /**************************************************************************** 1311 * RAID Volume Config Pages 1312 ****************************************************************************/ 1313 1314 /* RAID Volume Page 0 */ 1315 1316 typedef struct _MPI2_RAIDVOL0_PHYS_DISK 1317 { 1318 U8 RAIDSetNum; /* 0x00 */ 1319 U8 PhysDiskMap; /* 0x01 */ 1320 U8 PhysDiskNum; /* 0x02 */ 1321 U8 Reserved; /* 0x03 */ 1322 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK, 1323 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t; 1324 1325 /* defines for the PhysDiskMap field */ 1326 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1327 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1328 1329 typedef struct _MPI2_RAIDVOL0_SETTINGS 1330 { 1331 U16 Settings; /* 0x00 */ 1332 U8 HotSparePool; /* 0x01 */ 1333 U8 Reserved; /* 0x02 */ 1334 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS, 1335 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t; 1336 1337 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1338 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1339 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1340 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1341 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1342 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1343 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1344 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1345 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1346 1347 /* RAID Volume Page 0 VolumeSettings defines */ 1348 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1349 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1350 1351 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1352 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1353 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1354 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1355 1356 /* 1357 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1358 * one and check the value returned for NumPhysDisks at runtime. 1359 */ 1360 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1361 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1362 #endif 1363 1364 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 1365 { 1366 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1367 U16 DevHandle; /* 0x04 */ 1368 U8 VolumeState; /* 0x06 */ 1369 U8 VolumeType; /* 0x07 */ 1370 U32 VolumeStatusFlags; /* 0x08 */ 1371 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */ 1372 U64 MaxLBA; /* 0x10 */ 1373 U32 StripeSize; /* 0x18 */ 1374 U16 BlockSize; /* 0x1C */ 1375 U16 Reserved1; /* 0x1E */ 1376 U8 SupportedPhysDisks; /* 0x20 */ 1377 U8 ResyncRate; /* 0x21 */ 1378 U16 DataScrubDuration; /* 0x22 */ 1379 U8 NumPhysDisks; /* 0x24 */ 1380 U8 Reserved2; /* 0x25 */ 1381 U8 Reserved3; /* 0x26 */ 1382 U8 InactiveStatus; /* 0x27 */ 1383 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */ 1384 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1385 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t; 1386 1387 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1388 1389 /* values for RAID VolumeState */ 1390 #define MPI2_RAID_VOL_STATE_MISSING (0x00) 1391 #define MPI2_RAID_VOL_STATE_FAILED (0x01) 1392 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1393 #define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1394 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1395 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1396 1397 /* values for RAID VolumeType */ 1398 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1399 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1400 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1401 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1402 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1403 1404 /* values for RAID Volume Page 0 VolumeStatusFlags field */ 1405 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1406 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1407 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1408 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1409 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1410 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1411 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1412 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1413 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1414 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1415 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1416 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1417 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1418 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1419 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1420 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1421 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1422 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1423 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1424 1425 /* values for RAID Volume Page 0 SupportedPhysDisks field */ 1426 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1427 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1428 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1429 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1430 1431 /* values for RAID Volume Page 0 InactiveStatus field */ 1432 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1433 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1434 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1435 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1436 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1437 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1438 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1439 1440 1441 /* RAID Volume Page 1 */ 1442 1443 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 1444 { 1445 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1446 U16 DevHandle; /* 0x04 */ 1447 U16 Reserved0; /* 0x06 */ 1448 U8 GUID[24]; /* 0x08 */ 1449 U8 Name[16]; /* 0x20 */ 1450 U64 WWID; /* 0x30 */ 1451 U32 Reserved1; /* 0x38 */ 1452 U32 Reserved2; /* 0x3C */ 1453 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1454 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t; 1455 1456 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1457 1458 1459 /**************************************************************************** 1460 * RAID Physical Disk Config Pages 1461 ****************************************************************************/ 1462 1463 /* RAID Physical Disk Page 0 */ 1464 1465 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS 1466 { 1467 U16 Reserved1; /* 0x00 */ 1468 U8 HotSparePool; /* 0x02 */ 1469 U8 Reserved2; /* 0x03 */ 1470 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1471 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t; 1472 1473 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1474 1475 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA 1476 { 1477 U8 VendorID[8]; /* 0x00 */ 1478 U8 ProductID[16]; /* 0x08 */ 1479 U8 ProductRevLevel[4]; /* 0x18 */ 1480 U8 SerialNum[32]; /* 0x1C */ 1481 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1482 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1483 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t; 1484 1485 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 1486 { 1487 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1488 U16 DevHandle; /* 0x04 */ 1489 U8 Reserved1; /* 0x06 */ 1490 U8 PhysDiskNum; /* 0x07 */ 1491 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */ 1492 U32 Reserved2; /* 0x0C */ 1493 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */ 1494 U32 Reserved3; /* 0x4C */ 1495 U8 PhysDiskState; /* 0x50 */ 1496 U8 OfflineReason; /* 0x51 */ 1497 U8 IncompatibleReason; /* 0x52 */ 1498 U8 PhysDiskAttributes; /* 0x53 */ 1499 U32 PhysDiskStatusFlags; /* 0x54 */ 1500 U64 DeviceMaxLBA; /* 0x58 */ 1501 U64 HostMaxLBA; /* 0x60 */ 1502 U64 CoercedMaxLBA; /* 0x68 */ 1503 U16 BlockSize; /* 0x70 */ 1504 U16 Reserved5; /* 0x72 */ 1505 U32 Reserved6; /* 0x74 */ 1506 } MPI2_CONFIG_PAGE_RD_PDISK_0, 1507 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1508 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t; 1509 1510 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1511 1512 /* PhysDiskState defines */ 1513 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1514 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1515 #define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1516 #define MPI2_RAID_PD_STATE_ONLINE (0x03) 1517 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1518 #define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1519 #define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1520 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1521 1522 /* OfflineReason defines */ 1523 #define MPI2_PHYSDISK0_ONLINE (0x00) 1524 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1525 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1526 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1527 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1528 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1529 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1530 1531 /* IncompatibleReason defines */ 1532 #define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1533 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1534 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1535 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1536 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1537 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1538 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 1539 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1540 1541 /* PhysDiskAttributes defines */ 1542 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 1543 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1544 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1545 1546 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 1547 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1548 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1549 1550 /* PhysDiskStatusFlags defines */ 1551 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1552 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1553 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1554 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1555 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1556 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 1557 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 1558 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 1559 1560 1561 /* RAID Physical Disk Page 1 */ 1562 1563 /* 1564 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1565 * one and check the value returned for NumPhysDiskPaths at runtime. 1566 */ 1567 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 1568 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 1569 #endif 1570 1571 typedef struct _MPI2_RAIDPHYSDISK1_PATH 1572 { 1573 U16 DevHandle; /* 0x00 */ 1574 U16 Reserved1; /* 0x02 */ 1575 U64 WWID; /* 0x04 */ 1576 U64 OwnerWWID; /* 0x0C */ 1577 U8 OwnerIdentifier; /* 0x14 */ 1578 U8 Reserved2; /* 0x15 */ 1579 U16 Flags; /* 0x16 */ 1580 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH, 1581 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t; 1582 1583 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 1584 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 1585 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 1586 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 1587 1588 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 1589 { 1590 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1591 U8 NumPhysDiskPaths; /* 0x04 */ 1592 U8 PhysDiskNum; /* 0x05 */ 1593 U16 Reserved1; /* 0x06 */ 1594 U32 Reserved2; /* 0x08 */ 1595 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */ 1596 } MPI2_CONFIG_PAGE_RD_PDISK_1, 1597 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 1598 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t; 1599 1600 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 1601 1602 1603 /**************************************************************************** 1604 * values for fields used by several types of SAS Config Pages 1605 ****************************************************************************/ 1606 1607 /* values for NegotiatedLinkRates fields */ 1608 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 1609 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 1610 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 1611 /* link rates used for Negotiated Physical and Logical Link Rate */ 1612 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 1613 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 1614 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 1615 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 1616 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 1617 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 1618 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 1619 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 1620 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 1621 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 1622 1623 1624 /* values for AttachedPhyInfo fields */ 1625 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 1626 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 1627 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 1628 1629 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 1630 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 1631 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 1632 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 1633 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 1634 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 1635 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 1636 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 1637 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 1638 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 1639 1640 1641 /* values for PhyInfo fields */ 1642 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 1643 1644 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 1645 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 1646 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 1647 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 1648 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 1649 1650 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 1651 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 1652 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 1653 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 1654 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 1655 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 1656 1657 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 1658 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 1659 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 1660 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 1661 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 1662 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 1663 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 1664 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 1665 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 1666 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 1667 1668 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 1669 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 1670 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 1671 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 1672 1673 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 1674 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 1675 1676 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 1677 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 1678 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 1679 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 1680 1681 1682 /* values for SAS ProgrammedLinkRate fields */ 1683 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 1684 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 1685 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 1686 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 1687 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 1688 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 1689 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 1690 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 1691 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 1692 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 1693 1694 1695 /* values for SAS HwLinkRate fields */ 1696 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 1697 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 1698 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 1699 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 1700 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 1701 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 1702 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 1703 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 1704 1705 1706 1707 /**************************************************************************** 1708 * SAS IO Unit Config Pages 1709 ****************************************************************************/ 1710 1711 /* SAS IO Unit Page 0 */ 1712 1713 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA 1714 { 1715 U8 Port; /* 0x00 */ 1716 U8 PortFlags; /* 0x01 */ 1717 U8 PhyFlags; /* 0x02 */ 1718 U8 NegotiatedLinkRate; /* 0x03 */ 1719 U32 ControllerPhyDeviceInfo;/* 0x04 */ 1720 U16 AttachedDevHandle; /* 0x08 */ 1721 U16 ControllerDevHandle; /* 0x0A */ 1722 U32 DiscoveryStatus; /* 0x0C */ 1723 U32 Reserved; /* 0x10 */ 1724 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 1725 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t; 1726 1727 /* 1728 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1729 * one and check the value returned for NumPhys at runtime. 1730 */ 1731 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX 1732 #define MPI2_SAS_IOUNIT0_PHY_MAX (1) 1733 #endif 1734 1735 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 1736 { 1737 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1738 U32 Reserved1; /* 0x08 */ 1739 U8 NumPhys; /* 0x0C */ 1740 U8 Reserved2; /* 0x0D */ 1741 U16 Reserved3; /* 0x0E */ 1742 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */ 1743 } MPI2_CONFIG_PAGE_SASIOUNIT_0, 1744 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 1745 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t; 1746 1747 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 1748 1749 /* values for SAS IO Unit Page 0 PortFlags */ 1750 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 1751 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 1752 1753 /* values for SAS IO Unit Page 0 PhyFlags */ 1754 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 1755 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 1756 1757 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 1758 1759 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 1760 1761 /* values for SAS IO Unit Page 0 DiscoveryStatus */ 1762 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 1763 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 1764 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 1765 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 1766 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 1767 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 1768 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 1769 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 1770 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 1771 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 1772 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 1773 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 1774 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 1775 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 1776 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 1777 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 1778 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 1779 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 1780 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 1781 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 1782 1783 1784 /* SAS IO Unit Page 1 */ 1785 1786 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA 1787 { 1788 U8 Port; /* 0x00 */ 1789 U8 PortFlags; /* 0x01 */ 1790 U8 PhyFlags; /* 0x02 */ 1791 U8 MaxMinLinkRate; /* 0x03 */ 1792 U32 ControllerPhyDeviceInfo; /* 0x04 */ 1793 U16 MaxTargetPortConnectTime; /* 0x08 */ 1794 U16 Reserved1; /* 0x0A */ 1795 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 1796 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t; 1797 1798 /* 1799 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1800 * one and check the value returned for NumPhys at runtime. 1801 */ 1802 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX 1803 #define MPI2_SAS_IOUNIT1_PHY_MAX (1) 1804 #endif 1805 1806 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 1807 { 1808 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1809 U16 ControlFlags; /* 0x08 */ 1810 U16 SASNarrowMaxQueueDepth; /* 0x0A */ 1811 U16 AdditionalControlFlags; /* 0x0C */ 1812 U16 SASWideMaxQueueDepth; /* 0x0E */ 1813 U8 NumPhys; /* 0x10 */ 1814 U8 SATAMaxQDepth; /* 0x11 */ 1815 U8 ReportDeviceMissingDelay; /* 0x12 */ 1816 U8 IODeviceMissingDelay; /* 0x13 */ 1817 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */ 1818 } MPI2_CONFIG_PAGE_SASIOUNIT_1, 1819 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 1820 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t; 1821 1822 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 1823 1824 /* values for SAS IO Unit Page 1 ControlFlags */ 1825 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 1826 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 1827 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) 1828 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 1829 1830 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 1831 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 1832 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 1833 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 1834 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 1835 1836 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 1837 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 1838 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 1839 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 1840 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 1841 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 1842 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 1843 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) 1844 1845 /* values for SAS IO Unit Page 1 AdditionalControlFlags */ 1846 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 1847 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 1848 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 1849 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 1850 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 1851 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 1852 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 1853 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 1854 1855 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 1856 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 1857 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 1858 1859 /* values for SAS IO Unit Page 1 PortFlags */ 1860 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 1861 1862 /* values for SAS IO Unit Page 1 PhyFlags */ 1863 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 1864 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 1865 1866 /* values for SAS IO Unit Page 1 MaxMinLinkRate */ 1867 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 1868 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 1869 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 1870 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 1871 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 1872 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 1873 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 1874 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 1875 1876 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 1877 1878 1879 /* SAS IO Unit Page 4 */ 1880 1881 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP 1882 { 1883 U8 MaxTargetSpinup; /* 0x00 */ 1884 U8 SpinupDelay; /* 0x01 */ 1885 U16 Reserved1; /* 0x02 */ 1886 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 1887 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t; 1888 1889 /* 1890 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1891 * one and check the value returned for NumPhys at runtime. 1892 */ 1893 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX 1894 #define MPI2_SAS_IOUNIT4_PHY_MAX (4) 1895 #endif 1896 1897 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 1898 { 1899 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1900 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 1901 U32 Reserved1; /* 0x18 */ 1902 U32 Reserved2; /* 0x1C */ 1903 U32 Reserved3; /* 0x20 */ 1904 U8 BootDeviceWaitTime; /* 0x24 */ 1905 U8 Reserved4; /* 0x25 */ 1906 U16 Reserved5; /* 0x26 */ 1907 U8 NumPhys; /* 0x28 */ 1908 U8 PEInitialSpinupDelay; /* 0x29 */ 1909 U8 PEReplyDelay; /* 0x2A */ 1910 U8 Flags; /* 0x2B */ 1911 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */ 1912 } MPI2_CONFIG_PAGE_SASIOUNIT_4, 1913 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 1914 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t; 1915 1916 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 1917 1918 /* defines for Flags field */ 1919 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 1920 1921 /* defines for PHY field */ 1922 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 1923 1924 1925 /* SAS IO Unit Page 5 */ 1926 1927 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 1928 { 1929 U8 ControlFlags; /* 0x00 */ 1930 U8 PortWidthModGroup; /* 0x01 */ 1931 U16 InactivityTimerExponent; /* 0x02 */ 1932 U8 SATAPartialTimeout; /* 0x04 */ 1933 U8 Reserved2; /* 0x05 */ 1934 U8 SATASlumberTimeout; /* 0x06 */ 1935 U8 Reserved3; /* 0x07 */ 1936 U8 SASPartialTimeout; /* 0x08 */ 1937 U8 Reserved4; /* 0x09 */ 1938 U8 SASSlumberTimeout; /* 0x0A */ 1939 U8 Reserved5; /* 0x0B */ 1940 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 1941 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 1942 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t; 1943 1944 /* defines for ControlFlags field */ 1945 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 1946 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 1947 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 1948 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 1949 1950 /* defines for PortWidthModeGroup field */ 1951 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 1952 1953 /* defines for InactivityTimerExponent field */ 1954 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 1955 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 1956 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 1957 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 1958 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 1959 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 1960 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 1961 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 1962 1963 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 1964 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 1965 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 1966 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 1967 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 1968 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 1969 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 1970 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 1971 1972 /* 1973 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1974 * one and check the value returned for NumPhys at runtime. 1975 */ 1976 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX 1977 #define MPI2_SAS_IOUNIT5_PHY_MAX (1) 1978 #endif 1979 1980 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 1981 { 1982 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 1983 U8 NumPhys; /* 0x08 */ 1984 U8 Reserved1; /* 0x09 */ 1985 U16 Reserved2; /* 0x0A */ 1986 U32 Reserved3; /* 0x0C */ 1987 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */ 1988 } MPI2_CONFIG_PAGE_SASIOUNIT_5, 1989 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 1990 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t; 1991 1992 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 1993 1994 1995 /* SAS IO Unit Page 6 */ 1996 1997 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 1998 { 1999 U8 CurrentStatus; /* 0x00 */ 2000 U8 CurrentModulation; /* 0x01 */ 2001 U8 CurrentUtilization; /* 0x02 */ 2002 U8 Reserved1; /* 0x03 */ 2003 U32 Reserved2; /* 0x04 */ 2004 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2005 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2006 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 2007 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t; 2008 2009 /* defines for CurrentStatus field */ 2010 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 2011 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 2012 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 2013 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 2014 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 2015 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 2016 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 2017 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 2018 2019 /* defines for CurrentModulation field */ 2020 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 2021 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 2022 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 2023 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 2024 2025 /* 2026 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2027 * one and check the value returned for NumGroups at runtime. 2028 */ 2029 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 2030 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 2031 #endif 2032 2033 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 2034 { 2035 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2036 U32 Reserved1; /* 0x08 */ 2037 U32 Reserved2; /* 0x0C */ 2038 U8 NumGroups; /* 0x10 */ 2039 U8 Reserved3; /* 0x11 */ 2040 U16 Reserved4; /* 0x12 */ 2041 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2042 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */ 2043 } MPI2_CONFIG_PAGE_SASIOUNIT_6, 2044 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 2045 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t; 2046 2047 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 2048 2049 2050 /* SAS IO Unit Page 7 */ 2051 2052 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2053 { 2054 U8 Flags; /* 0x00 */ 2055 U8 Reserved1; /* 0x01 */ 2056 U16 Reserved2; /* 0x02 */ 2057 U8 Threshold75Pct; /* 0x04 */ 2058 U8 Threshold50Pct; /* 0x05 */ 2059 U8 Threshold25Pct; /* 0x06 */ 2060 U8 Reserved3; /* 0x07 */ 2061 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2062 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2063 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2064 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2065 2066 /* defines for Flags field */ 2067 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2068 2069 2070 /* 2071 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2072 * one and check the value returned for NumGroups at runtime. 2073 */ 2074 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2075 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2076 #endif 2077 2078 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 2079 { 2080 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2081 U8 SamplingInterval; /* 0x08 */ 2082 U8 WindowLength; /* 0x09 */ 2083 U16 Reserved1; /* 0x0A */ 2084 U32 Reserved2; /* 0x0C */ 2085 U32 Reserved3; /* 0x10 */ 2086 U8 NumGroups; /* 0x14 */ 2087 U8 Reserved4; /* 0x15 */ 2088 U16 Reserved5; /* 0x16 */ 2089 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2090 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */ 2091 } MPI2_CONFIG_PAGE_SASIOUNIT_7, 2092 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2093 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t; 2094 2095 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2096 2097 2098 /* SAS IO Unit Page 8 */ 2099 2100 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 2101 { 2102 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2103 U32 Reserved1; /* 0x08 */ 2104 U32 PowerManagementCapabilities; /* 0x0C */ 2105 U32 Reserved2; /* 0x10 */ 2106 } MPI2_CONFIG_PAGE_SASIOUNIT_8, 2107 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2108 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t; 2109 2110 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2111 2112 /* defines for PowerManagementCapabilities field */ 2113 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x000001000) 2114 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x000000800) 2115 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x000000400) 2116 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x000000200) 2117 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x000000100) 2118 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x000000010) 2119 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x000000008) 2120 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x000000004) 2121 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x000000002) 2122 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x000000001) 2123 2124 2125 2126 2127 /**************************************************************************** 2128 * SAS Expander Config Pages 2129 ****************************************************************************/ 2130 2131 /* SAS Expander Page 0 */ 2132 2133 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 2134 { 2135 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2136 U8 PhysicalPort; /* 0x08 */ 2137 U8 ReportGenLength; /* 0x09 */ 2138 U16 EnclosureHandle; /* 0x0A */ 2139 U64 SASAddress; /* 0x0C */ 2140 U32 DiscoveryStatus; /* 0x14 */ 2141 U16 DevHandle; /* 0x18 */ 2142 U16 ParentDevHandle; /* 0x1A */ 2143 U16 ExpanderChangeCount; /* 0x1C */ 2144 U16 ExpanderRouteIndexes; /* 0x1E */ 2145 U8 NumPhys; /* 0x20 */ 2146 U8 SASLevel; /* 0x21 */ 2147 U16 Flags; /* 0x22 */ 2148 U16 STPBusInactivityTimeLimit; /* 0x24 */ 2149 U16 STPMaxConnectTimeLimit; /* 0x26 */ 2150 U16 STP_SMP_NexusLossTime; /* 0x28 */ 2151 U16 MaxNumRoutedSasAddresses; /* 0x2A */ 2152 U64 ActiveZoneManagerSASAddress;/* 0x2C */ 2153 U16 ZoneLockInactivityLimit; /* 0x34 */ 2154 U16 Reserved1; /* 0x36 */ 2155 U8 TimeToReducedFunc; /* 0x38 */ 2156 U8 InitialTimeToReducedFunc; /* 0x39 */ 2157 U8 MaxReducedFuncTime; /* 0x3A */ 2158 U8 Reserved2; /* 0x3B */ 2159 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2160 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t; 2161 2162 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2163 2164 /* values for SAS Expander Page 0 DiscoveryStatus field */ 2165 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2166 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2167 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2168 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2169 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2170 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2171 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2172 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2173 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2174 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2175 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2176 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2177 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2178 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2179 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2180 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2181 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2182 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2183 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2184 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2185 2186 /* values for SAS Expander Page 0 Flags field */ 2187 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2188 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2189 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2190 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2191 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2192 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2193 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2194 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2195 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2196 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2197 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2198 2199 2200 /* SAS Expander Page 1 */ 2201 2202 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 2203 { 2204 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2205 U8 PhysicalPort; /* 0x08 */ 2206 U8 Reserved1; /* 0x09 */ 2207 U16 Reserved2; /* 0x0A */ 2208 U8 NumPhys; /* 0x0C */ 2209 U8 Phy; /* 0x0D */ 2210 U16 NumTableEntriesProgrammed; /* 0x0E */ 2211 U8 ProgrammedLinkRate; /* 0x10 */ 2212 U8 HwLinkRate; /* 0x11 */ 2213 U16 AttachedDevHandle; /* 0x12 */ 2214 U32 PhyInfo; /* 0x14 */ 2215 U32 AttachedDeviceInfo; /* 0x18 */ 2216 U16 ExpanderDevHandle; /* 0x1C */ 2217 U8 ChangeCount; /* 0x1E */ 2218 U8 NegotiatedLinkRate; /* 0x1F */ 2219 U8 PhyIdentifier; /* 0x20 */ 2220 U8 AttachedPhyIdentifier; /* 0x21 */ 2221 U8 Reserved3; /* 0x22 */ 2222 U8 DiscoveryInfo; /* 0x23 */ 2223 U32 AttachedPhyInfo; /* 0x24 */ 2224 U8 ZoneGroup; /* 0x28 */ 2225 U8 SelfConfigStatus; /* 0x29 */ 2226 U16 Reserved4; /* 0x2A */ 2227 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2228 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t; 2229 2230 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2231 2232 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2233 2234 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2235 2236 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2237 2238 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */ 2239 2240 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2241 2242 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2243 2244 /* values for SAS Expander Page 1 DiscoveryInfo field */ 2245 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2246 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2247 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2248 2249 2250 /**************************************************************************** 2251 * SAS Device Config Pages 2252 ****************************************************************************/ 2253 2254 /* SAS Device Page 0 */ 2255 2256 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 2257 { 2258 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2259 U16 Slot; /* 0x08 */ 2260 U16 EnclosureHandle; /* 0x0A */ 2261 U64 SASAddress; /* 0x0C */ 2262 U16 ParentDevHandle; /* 0x14 */ 2263 U8 PhyNum; /* 0x16 */ 2264 U8 AccessStatus; /* 0x17 */ 2265 U16 DevHandle; /* 0x18 */ 2266 U8 AttachedPhyIdentifier; /* 0x1A */ 2267 U8 ZoneGroup; /* 0x1B */ 2268 U32 DeviceInfo; /* 0x1C */ 2269 U16 Flags; /* 0x20 */ 2270 U8 PhysicalPort; /* 0x22 */ 2271 U8 MaxPortConnections; /* 0x23 */ 2272 U64 DeviceName; /* 0x24 */ 2273 U8 PortGroups; /* 0x2C */ 2274 U8 DmaGroup; /* 0x2D */ 2275 U8 ControlGroup; /* 0x2E */ 2276 U8 Reserved1; /* 0x2F */ 2277 U32 Reserved2; /* 0x30 */ 2278 U32 Reserved3; /* 0x34 */ 2279 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2280 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t; 2281 2282 #define MPI2_SASDEVICE0_PAGEVERSION (0x08) 2283 2284 /* values for SAS Device Page 0 AccessStatus field */ 2285 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2286 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2287 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2288 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2289 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2290 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2291 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2292 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2293 /* specific values for SATA Init failures */ 2294 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2295 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2296 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2297 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2298 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2299 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2300 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2301 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2302 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2303 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2304 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2305 2306 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2307 2308 /* values for SAS Device Page 0 Flags field */ 2309 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2310 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2311 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2312 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2313 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2314 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2315 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2316 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2317 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2318 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2319 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2320 2321 2322 /* SAS Device Page 1 */ 2323 2324 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 2325 { 2326 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2327 U32 Reserved1; /* 0x08 */ 2328 U64 SASAddress; /* 0x0C */ 2329 U32 Reserved2; /* 0x14 */ 2330 U16 DevHandle; /* 0x18 */ 2331 U16 Reserved3; /* 0x1A */ 2332 U8 InitialRegDeviceFIS[20];/* 0x1C */ 2333 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2334 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t; 2335 2336 #define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2337 2338 2339 /**************************************************************************** 2340 * SAS PHY Config Pages 2341 ****************************************************************************/ 2342 2343 /* SAS PHY Page 0 */ 2344 2345 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 2346 { 2347 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2348 U16 OwnerDevHandle; /* 0x08 */ 2349 U16 Reserved1; /* 0x0A */ 2350 U16 AttachedDevHandle; /* 0x0C */ 2351 U8 AttachedPhyIdentifier; /* 0x0E */ 2352 U8 Reserved2; /* 0x0F */ 2353 U32 AttachedPhyInfo; /* 0x10 */ 2354 U8 ProgrammedLinkRate; /* 0x14 */ 2355 U8 HwLinkRate; /* 0x15 */ 2356 U8 ChangeCount; /* 0x16 */ 2357 U8 Flags; /* 0x17 */ 2358 U32 PhyInfo; /* 0x18 */ 2359 U8 NegotiatedLinkRate; /* 0x1C */ 2360 U8 Reserved3; /* 0x1D */ 2361 U16 Reserved4; /* 0x1E */ 2362 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2363 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t; 2364 2365 #define MPI2_SASPHY0_PAGEVERSION (0x03) 2366 2367 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2368 2369 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2370 2371 /* values for SAS PHY Page 0 Flags field */ 2372 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2373 2374 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2375 2376 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2377 2378 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2379 2380 2381 /* SAS PHY Page 1 */ 2382 2383 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 2384 { 2385 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2386 U32 Reserved1; /* 0x08 */ 2387 U32 InvalidDwordCount; /* 0x0C */ 2388 U32 RunningDisparityErrorCount; /* 0x10 */ 2389 U32 LossDwordSynchCount; /* 0x14 */ 2390 U32 PhyResetProblemCount; /* 0x18 */ 2391 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 2392 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t; 2393 2394 #define MPI2_SASPHY1_PAGEVERSION (0x01) 2395 2396 2397 /* SAS PHY Page 2 */ 2398 2399 typedef struct _MPI2_SASPHY2_PHY_EVENT 2400 { 2401 U8 PhyEventCode; /* 0x00 */ 2402 U8 Reserved1; /* 0x01 */ 2403 U16 Reserved2; /* 0x02 */ 2404 U32 PhyEventInfo; /* 0x04 */ 2405 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT, 2406 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t; 2407 2408 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 2409 2410 2411 /* 2412 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2413 * one and check the value returned for NumPhyEvents at runtime. 2414 */ 2415 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX 2416 #define MPI2_SASPHY2_PHY_EVENT_MAX (1) 2417 #endif 2418 2419 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 2420 { 2421 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2422 U32 Reserved1; /* 0x08 */ 2423 U8 NumPhyEvents; /* 0x0C */ 2424 U8 Reserved2; /* 0x0D */ 2425 U16 Reserved3; /* 0x0E */ 2426 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */ 2427 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 2428 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t; 2429 2430 #define MPI2_SASPHY2_PAGEVERSION (0x00) 2431 2432 2433 /* SAS PHY Page 3 */ 2434 2435 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG 2436 { 2437 U8 PhyEventCode; /* 0x00 */ 2438 U8 Reserved1; /* 0x01 */ 2439 U16 Reserved2; /* 0x02 */ 2440 U8 CounterType; /* 0x04 */ 2441 U8 ThresholdWindow; /* 0x05 */ 2442 U8 TimeUnits; /* 0x06 */ 2443 U8 Reserved3; /* 0x07 */ 2444 U32 EventThreshold; /* 0x08 */ 2445 U16 ThresholdFlags; /* 0x0C */ 2446 U16 Reserved4; /* 0x0E */ 2447 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 2448 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t; 2449 2450 /* values for PhyEventCode field */ 2451 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2452 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2453 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2454 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2455 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2456 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 2457 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 2458 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 2459 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 2460 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 2461 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 2462 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 2463 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 2464 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 2465 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 2466 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 2467 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 2468 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 2469 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 2470 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 2471 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 2472 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 2473 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 2474 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 2475 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 2476 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 2477 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 2478 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 2479 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 2480 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 2481 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 2482 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 2483 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 2484 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 2485 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 2486 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 2487 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 2488 2489 /* values for the CounterType field */ 2490 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 2491 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 2492 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 2493 2494 /* values for the TimeUnits field */ 2495 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 2496 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 2497 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 2498 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 2499 2500 /* values for the ThresholdFlags field */ 2501 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 2502 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 2503 2504 /* 2505 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2506 * one and check the value returned for NumPhyEvents at runtime. 2507 */ 2508 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX 2509 #define MPI2_SASPHY3_PHY_EVENT_MAX (1) 2510 #endif 2511 2512 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 2513 { 2514 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2515 U32 Reserved1; /* 0x08 */ 2516 U8 NumPhyEvents; /* 0x0C */ 2517 U8 Reserved2; /* 0x0D */ 2518 U16 Reserved3; /* 0x0E */ 2519 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */ 2520 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 2521 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t; 2522 2523 #define MPI2_SASPHY3_PAGEVERSION (0x00) 2524 2525 2526 /* SAS PHY Page 4 */ 2527 2528 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 2529 { 2530 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2531 U16 Reserved1; /* 0x08 */ 2532 U8 Reserved2; /* 0x0A */ 2533 U8 Flags; /* 0x0B */ 2534 U8 InitialFrame[28]; /* 0x0C */ 2535 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 2536 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t; 2537 2538 #define MPI2_SASPHY4_PAGEVERSION (0x00) 2539 2540 /* values for the Flags field */ 2541 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 2542 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 2543 2544 2545 2546 2547 /**************************************************************************** 2548 * SAS Port Config Pages 2549 ****************************************************************************/ 2550 2551 /* SAS Port Page 0 */ 2552 2553 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 2554 { 2555 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2556 U8 PortNumber; /* 0x08 */ 2557 U8 PhysicalPort; /* 0x09 */ 2558 U8 PortWidth; /* 0x0A */ 2559 U8 PhysicalPortWidth; /* 0x0B */ 2560 U8 ZoneGroup; /* 0x0C */ 2561 U8 Reserved1; /* 0x0D */ 2562 U16 Reserved2; /* 0x0E */ 2563 U64 SASAddress; /* 0x10 */ 2564 U32 DeviceInfo; /* 0x18 */ 2565 U32 Reserved3; /* 0x1C */ 2566 U32 Reserved4; /* 0x20 */ 2567 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 2568 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t; 2569 2570 #define MPI2_SASPORT0_PAGEVERSION (0x00) 2571 2572 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 2573 2574 2575 /**************************************************************************** 2576 * SAS Enclosure Config Pages 2577 ****************************************************************************/ 2578 2579 /* SAS Enclosure Page 0 */ 2580 2581 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 2582 { 2583 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2584 U32 Reserved1; /* 0x08 */ 2585 U64 EnclosureLogicalID; /* 0x0C */ 2586 U16 Flags; /* 0x14 */ 2587 U16 EnclosureHandle; /* 0x16 */ 2588 U16 NumSlots; /* 0x18 */ 2589 U16 StartSlot; /* 0x1A */ 2590 U16 Reserved2; /* 0x1C */ 2591 U16 SEPDevHandle; /* 0x1E */ 2592 U32 Reserved3; /* 0x20 */ 2593 U32 Reserved4; /* 0x24 */ 2594 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 2595 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 2596 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t; 2597 2598 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x03) 2599 2600 /* values for SAS Enclosure Page 0 Flags field */ 2601 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 2602 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 2603 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 2604 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 2605 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 2606 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 2607 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 2608 2609 2610 /**************************************************************************** 2611 * Log Config Page 2612 ****************************************************************************/ 2613 2614 /* Log Page 0 */ 2615 2616 /* 2617 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2618 * one and check the value returned for NumLogEntries at runtime. 2619 */ 2620 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 2621 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 2622 #endif 2623 2624 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 2625 2626 typedef struct _MPI2_LOG_0_ENTRY 2627 { 2628 U64 TimeStamp; /* 0x00 */ 2629 U32 Reserved1; /* 0x08 */ 2630 U16 LogSequence; /* 0x0C */ 2631 U16 LogEntryQualifier; /* 0x0E */ 2632 U8 VP_ID; /* 0x10 */ 2633 U8 VF_ID; /* 0x11 */ 2634 U16 Reserved2; /* 0x12 */ 2635 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */ 2636 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY, 2637 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t; 2638 2639 /* values for Log Page 0 LogEntry LogEntryQualifier field */ 2640 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 2641 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 2642 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 2643 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 2644 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 2645 2646 typedef struct _MPI2_CONFIG_PAGE_LOG_0 2647 { 2648 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2649 U32 Reserved1; /* 0x08 */ 2650 U32 Reserved2; /* 0x0C */ 2651 U16 NumLogEntries; /* 0x10 */ 2652 U16 Reserved3; /* 0x12 */ 2653 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */ 2654 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0, 2655 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t; 2656 2657 #define MPI2_LOG_0_PAGEVERSION (0x02) 2658 2659 2660 /**************************************************************************** 2661 * RAID Config Page 2662 ****************************************************************************/ 2663 2664 /* RAID Page 0 */ 2665 2666 /* 2667 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2668 * one and check the value returned for NumElements at runtime. 2669 */ 2670 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 2671 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 2672 #endif 2673 2674 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT 2675 { 2676 U16 ElementFlags; /* 0x00 */ 2677 U16 VolDevHandle; /* 0x02 */ 2678 U8 HotSparePool; /* 0x04 */ 2679 U8 PhysDiskNum; /* 0x05 */ 2680 U16 PhysDiskDevHandle; /* 0x06 */ 2681 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 2682 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 2683 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t; 2684 2685 /* values for the ElementFlags field */ 2686 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 2687 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 2688 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 2689 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 2690 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 2691 2692 2693 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 2694 { 2695 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2696 U8 NumHotSpares; /* 0x08 */ 2697 U8 NumPhysDisks; /* 0x09 */ 2698 U8 NumVolumes; /* 0x0A */ 2699 U8 ConfigNum; /* 0x0B */ 2700 U32 Flags; /* 0x0C */ 2701 U8 ConfigGUID[24]; /* 0x10 */ 2702 U32 Reserved1; /* 0x28 */ 2703 U8 NumElements; /* 0x2C */ 2704 U8 Reserved2; /* 0x2D */ 2705 U16 Reserved3; /* 0x2E */ 2706 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */ 2707 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 2708 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 2709 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t; 2710 2711 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 2712 2713 /* values for RAID Configuration Page 0 Flags field */ 2714 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 2715 2716 2717 /**************************************************************************** 2718 * Driver Persistent Mapping Config Pages 2719 ****************************************************************************/ 2720 2721 /* Driver Persistent Mapping Page 0 */ 2722 2723 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY 2724 { 2725 U64 PhysicalIdentifier; /* 0x00 */ 2726 U16 MappingInformation; /* 0x08 */ 2727 U16 DeviceIndex; /* 0x0A */ 2728 U32 PhysicalBitsMapping; /* 0x0C */ 2729 U32 Reserved1; /* 0x10 */ 2730 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 2731 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 2732 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t; 2733 2734 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 2735 { 2736 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2737 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */ 2738 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 2739 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 2740 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t; 2741 2742 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 2743 2744 /* values for Driver Persistent Mapping Page 0 MappingInformation field */ 2745 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 2746 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 2747 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 2748 2749 2750 /**************************************************************************** 2751 * Ethernet Config Pages 2752 ****************************************************************************/ 2753 2754 /* Ethernet Page 0 */ 2755 2756 /* IP address (union of IPv4 and IPv6) */ 2757 typedef union _MPI2_ETHERNET_IP_ADDR 2758 { 2759 U32 IPv4Addr; 2760 U32 IPv6Addr[4]; 2761 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR, 2762 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t; 2763 2764 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 2765 2766 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 2767 { 2768 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2769 U8 NumInterfaces; /* 0x08 */ 2770 U8 Reserved0; /* 0x09 */ 2771 U16 Reserved1; /* 0x0A */ 2772 U32 Status; /* 0x0C */ 2773 U8 MediaState; /* 0x10 */ 2774 U8 Reserved2; /* 0x11 */ 2775 U16 Reserved3; /* 0x12 */ 2776 U8 MacAddress[6]; /* 0x14 */ 2777 U8 Reserved4; /* 0x1A */ 2778 U8 Reserved5; /* 0x1B */ 2779 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */ 2780 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */ 2781 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */ 2782 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */ 2783 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */ 2784 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */ 2785 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 2786 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 2787 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t; 2788 2789 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 2790 2791 /* values for Ethernet Page 0 Status field */ 2792 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 2793 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 2794 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 2795 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 2796 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 2797 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 2798 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 2799 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 2800 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 2801 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 2802 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 2803 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 2804 2805 /* values for Ethernet Page 0 MediaState field */ 2806 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 2807 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 2808 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 2809 2810 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 2811 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 2812 #define MPI2_ETHPG0_MS_10MBIT (0x01) 2813 #define MPI2_ETHPG0_MS_100MBIT (0x02) 2814 #define MPI2_ETHPG0_MS_1GBIT (0x03) 2815 2816 2817 /* Ethernet Page 1 */ 2818 2819 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 2820 { 2821 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2822 U32 Reserved0; /* 0x08 */ 2823 U32 Flags; /* 0x0C */ 2824 U8 MediaState; /* 0x10 */ 2825 U8 Reserved1; /* 0x11 */ 2826 U16 Reserved2; /* 0x12 */ 2827 U8 MacAddress[6]; /* 0x14 */ 2828 U8 Reserved3; /* 0x1A */ 2829 U8 Reserved4; /* 0x1B */ 2830 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */ 2831 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */ 2832 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */ 2833 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */ 2834 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */ 2835 U32 Reserved5; /* 0x6C */ 2836 U32 Reserved6; /* 0x70 */ 2837 U32 Reserved7; /* 0x74 */ 2838 U32 Reserved8; /* 0x78 */ 2839 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 2840 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 2841 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t; 2842 2843 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 2844 2845 /* values for Ethernet Page 1 Flags field */ 2846 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 2847 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 2848 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 2849 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 2850 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 2851 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 2852 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 2853 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 2854 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 2855 2856 /* values for Ethernet Page 1 MediaState field */ 2857 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 2858 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 2859 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 2860 2861 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 2862 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 2863 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 2864 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 2865 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 2866 2867 2868 /**************************************************************************** 2869 * Extended Manufacturing Config Pages 2870 ****************************************************************************/ 2871 2872 /* 2873 * Generic structure to use for product-specific extended manufacturing pages 2874 * (currently Extended Manufacturing Page 40 through Extended Manufacturing 2875 * Page 60). 2876 */ 2877 2878 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS 2879 { 2880 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2881 U32 ProductSpecificInfo; /* 0x08 */ 2882 } MPI2_CONFIG_PAGE_EXT_MAN_PS, 2883 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 2884 Mpi2ExtManufacturingPagePS_t, MPI2_POINTER pMpi2ExtManufacturingPagePS_t; 2885 2886 /* PageVersion should be provided by product-specific code */ 2887 2888 #endif 2889 2890