1 /*- 2 * Copyright (c) 2011, 2012 LSI Corp. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * LSI MPT-Fusion Host Adapter FreeBSD 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * Copyright (c) 2000-2012 LSI Corporation. 33 * 34 * 35 * Name: mpi2.h 36 * Title: MPI Message independent structures and definitions 37 * including System Interface Register Set and 38 * scatter/gather formats. 39 * Creation Date: June 21, 2006 40 * 41 * mpi2.h Version: 02.00.18 42 * 43 * Version History 44 * --------------- 45 * 46 * Date Version Description 47 * -------- -------- ------------------------------------------------------ 48 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 49 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. 50 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. 51 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. 52 * Moved ReplyPostHostIndex register to offset 0x6C of the 53 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for 54 * MPI2_REPLY_POST_HOST_INDEX_OFFSET. 55 * Added union of request descriptors. 56 * Added union of reply descriptors. 57 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. 58 * Added define for MPI2_VERSION_02_00. 59 * Fixed the size of the FunctionDependent5 field in the 60 * MPI2_DEFAULT_REPLY structure. 61 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. 62 * Removed the MPI-defined Fault Codes and extended the 63 * product specific codes up to 0xEFFF. 64 * Added a sixth key value for the WriteSequence register 65 * and changed the flush value to 0x0. 66 * Added message function codes for Diagnostic Buffer Post 67 * and Diagnsotic Release. 68 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED 69 * Moved MPI2_VERSION_UNION from mpi2_ioc.h. 70 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. 71 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. 72 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. 73 * Added #defines for marking a reply descriptor as unused. 74 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. 75 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. 76 * Moved LUN field defines from mpi2_init.h. 77 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. 78 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT. 79 * In all request and reply descriptors, replaced VF_ID 80 * field with MSIxIndex field. 81 * Removed DevHandle field from 82 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 83 * bytes reserved. 84 * Added RAID Accelerator functionality. 85 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT. 86 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT. 87 * Added MSI-x index mask and shift for Reply Post Host 88 * Index register. 89 * Added function code for Host Based Discovery Action. 90 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT. 91 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL. 92 * Added defines for product-specific range of message 93 * function codes, 0xF0 to 0xFF. 94 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT. 95 * Added alternative defines for the SGE Direction bit. 96 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT. 97 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT. 98 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define. 99 * -------------------------------------------------------------------------- 100 */ 101 102 #ifndef MPI2_H 103 #define MPI2_H 104 105 106 /***************************************************************************** 107 * 108 * MPI Version Definitions 109 * 110 *****************************************************************************/ 111 112 #define MPI2_VERSION_MAJOR (0x02) 113 #define MPI2_VERSION_MINOR (0x00) 114 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 115 #define MPI2_VERSION_MAJOR_SHIFT (8) 116 #define MPI2_VERSION_MINOR_MASK (0x00FF) 117 #define MPI2_VERSION_MINOR_SHIFT (0) 118 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 119 MPI2_VERSION_MINOR) 120 121 #define MPI2_VERSION_02_00 (0x0200) 122 123 /* versioning for this MPI header set */ 124 #define MPI2_HEADER_VERSION_UNIT (0x12) 125 #define MPI2_HEADER_VERSION_DEV (0x00) 126 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 127 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 128 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 129 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 130 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 131 132 133 /***************************************************************************** 134 * 135 * IOC State Definitions 136 * 137 *****************************************************************************/ 138 139 #define MPI2_IOC_STATE_RESET (0x00000000) 140 #define MPI2_IOC_STATE_READY (0x10000000) 141 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000) 142 #define MPI2_IOC_STATE_FAULT (0x40000000) 143 144 #define MPI2_IOC_STATE_MASK (0xF0000000) 145 #define MPI2_IOC_STATE_SHIFT (28) 146 147 /* Fault state range for prodcut specific codes */ 148 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) 149 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) 150 151 152 /***************************************************************************** 153 * 154 * System Interface Register Definitions 155 * 156 *****************************************************************************/ 157 158 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS 159 { 160 U32 Doorbell; /* 0x00 */ 161 U32 WriteSequence; /* 0x04 */ 162 U32 HostDiagnostic; /* 0x08 */ 163 U32 Reserved1; /* 0x0C */ 164 U32 DiagRWData; /* 0x10 */ 165 U32 DiagRWAddressLow; /* 0x14 */ 166 U32 DiagRWAddressHigh; /* 0x18 */ 167 U32 Reserved2[5]; /* 0x1C */ 168 U32 HostInterruptStatus; /* 0x30 */ 169 U32 HostInterruptMask; /* 0x34 */ 170 U32 DCRData; /* 0x38 */ 171 U32 DCRAddress; /* 0x3C */ 172 U32 Reserved3[2]; /* 0x40 */ 173 U32 ReplyFreeHostIndex; /* 0x48 */ 174 U32 Reserved4[8]; /* 0x4C */ 175 U32 ReplyPostHostIndex; /* 0x6C */ 176 U32 Reserved5; /* 0x70 */ 177 U32 HCBSize; /* 0x74 */ 178 U32 HCBAddressLow; /* 0x78 */ 179 U32 HCBAddressHigh; /* 0x7C */ 180 U32 Reserved6[16]; /* 0x80 */ 181 U32 RequestDescriptorPostLow; /* 0xC0 */ 182 U32 RequestDescriptorPostHigh; /* 0xC4 */ 183 U32 Reserved7[14]; /* 0xC8 */ 184 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS, 185 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t; 186 187 /* 188 * Defines for working with the Doorbell register. 189 */ 190 #define MPI2_DOORBELL_OFFSET (0x00000000) 191 192 /* IOC --> System values */ 193 #define MPI2_DOORBELL_USED (0x08000000) 194 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) 195 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24) 196 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) 197 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) 198 199 /* System --> IOC values */ 200 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) 201 #define MPI2_DOORBELL_FUNCTION_SHIFT (24) 202 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 203 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) 204 205 206 /* 207 * Defines for the WriteSequence register 208 */ 209 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 210 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) 211 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 212 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 213 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 214 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 215 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 216 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 217 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 218 219 /* 220 * Defines for the HostDiagnostic register 221 */ 222 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 223 224 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 225 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) 226 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) 227 228 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 229 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) 230 #define MPI2_DIAG_HCB_MODE (0x00000100) 231 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) 232 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) 233 #define MPI2_DIAG_RESET_HISTORY (0x00000020) 234 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) 235 #define MPI2_DIAG_RESET_ADAPTER (0x00000004) 236 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) 237 238 /* 239 * Offsets for DiagRWData and address 240 */ 241 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) 242 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) 243 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) 244 245 /* 246 * Defines for the HostInterruptStatus register 247 */ 248 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 249 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) 250 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS 251 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) 252 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) 253 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) 254 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS 255 256 /* 257 * Defines for the HostInterruptMask register 258 */ 259 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 260 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000) 261 #define MPI2_HIM_REPLY_INT_MASK (0x00000008) 262 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK 263 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) 264 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK 265 266 /* 267 * Offsets for DCRData and address 268 */ 269 #define MPI2_DCR_DATA_OFFSET (0x00000038) 270 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) 271 272 /* 273 * Offset for the Reply Free Queue 274 */ 275 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) 276 277 /* 278 * Defines for the Reply Descriptor Post Queue 279 */ 280 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 281 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) 282 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) 283 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24) 284 285 /* 286 * Defines for the HCBSize and address 287 */ 288 #define MPI2_HCB_SIZE_OFFSET (0x00000074) 289 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) 290 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) 291 292 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) 293 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) 294 295 /* 296 * Offsets for the Request Queue 297 */ 298 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) 299 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) 300 301 302 /***************************************************************************** 303 * 304 * Message Descriptors 305 * 306 *****************************************************************************/ 307 308 /* Request Descriptors */ 309 310 /* Default Request Descriptor */ 311 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR 312 { 313 U8 RequestFlags; /* 0x00 */ 314 U8 MSIxIndex; /* 0x01 */ 315 U16 SMID; /* 0x02 */ 316 U16 LMID; /* 0x04 */ 317 U16 DescriptorTypeDependent; /* 0x06 */ 318 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 319 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 320 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 321 322 /* defines for the RequestFlags field */ 323 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 324 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 325 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 326 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 327 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 328 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 329 330 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 331 332 333 /* High Priority Request Descriptor */ 334 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR 335 { 336 U8 RequestFlags; /* 0x00 */ 337 U8 MSIxIndex; /* 0x01 */ 338 U16 SMID; /* 0x02 */ 339 U16 LMID; /* 0x04 */ 340 U16 Reserved1; /* 0x06 */ 341 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 342 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 343 Mpi2HighPriorityRequestDescriptor_t, 344 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 345 346 347 /* SCSI IO Request Descriptor */ 348 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR 349 { 350 U8 RequestFlags; /* 0x00 */ 351 U8 MSIxIndex; /* 0x01 */ 352 U16 SMID; /* 0x02 */ 353 U16 LMID; /* 0x04 */ 354 U16 DevHandle; /* 0x06 */ 355 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 356 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 357 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 358 359 360 /* SCSI Target Request Descriptor */ 361 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR 362 { 363 U8 RequestFlags; /* 0x00 */ 364 U8 MSIxIndex; /* 0x01 */ 365 U16 SMID; /* 0x02 */ 366 U16 LMID; /* 0x04 */ 367 U16 IoIndex; /* 0x06 */ 368 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 369 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 370 Mpi2SCSITargetRequestDescriptor_t, 371 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 372 373 374 /* RAID Accelerator Request Descriptor */ 375 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR 376 { 377 U8 RequestFlags; /* 0x00 */ 378 U8 MSIxIndex; /* 0x01 */ 379 U16 SMID; /* 0x02 */ 380 U16 LMID; /* 0x04 */ 381 U16 Reserved; /* 0x06 */ 382 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 383 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 384 Mpi2RAIDAcceleratorRequestDescriptor_t, 385 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 386 387 388 /* union of Request Descriptors */ 389 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION 390 { 391 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 392 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 393 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 394 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 395 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 396 U64 Words; 397 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION, 398 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t; 399 400 401 /* Reply Descriptors */ 402 403 /* Default Reply Descriptor */ 404 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR 405 { 406 U8 ReplyFlags; /* 0x00 */ 407 U8 MSIxIndex; /* 0x01 */ 408 U16 DescriptorTypeDependent1; /* 0x02 */ 409 U32 DescriptorTypeDependent2; /* 0x04 */ 410 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 411 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 412 413 /* defines for the ReplyFlags field */ 414 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 415 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 416 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 417 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 418 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 419 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 420 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 421 422 /* values for marking a reply descriptor as unused */ 423 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 424 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 425 426 /* Address Reply Descriptor */ 427 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR 428 { 429 U8 ReplyFlags; /* 0x00 */ 430 U8 MSIxIndex; /* 0x01 */ 431 U16 SMID; /* 0x02 */ 432 U32 ReplyFrameAddress; /* 0x04 */ 433 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 434 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 435 436 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) 437 438 439 /* SCSI IO Success Reply Descriptor */ 440 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 441 { 442 U8 ReplyFlags; /* 0x00 */ 443 U8 MSIxIndex; /* 0x01 */ 444 U16 SMID; /* 0x02 */ 445 U16 TaskTag; /* 0x04 */ 446 U16 Reserved1; /* 0x06 */ 447 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 448 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 449 Mpi2SCSIIOSuccessReplyDescriptor_t, 450 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 451 452 453 /* TargetAssist Success Reply Descriptor */ 454 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR 455 { 456 U8 ReplyFlags; /* 0x00 */ 457 U8 MSIxIndex; /* 0x01 */ 458 U16 SMID; /* 0x02 */ 459 U8 SequenceNumber; /* 0x04 */ 460 U8 Reserved1; /* 0x05 */ 461 U16 IoIndex; /* 0x06 */ 462 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 463 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 464 Mpi2TargetAssistSuccessReplyDescriptor_t, 465 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 466 467 468 /* Target Command Buffer Reply Descriptor */ 469 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 470 { 471 U8 ReplyFlags; /* 0x00 */ 472 U8 MSIxIndex; /* 0x01 */ 473 U8 VP_ID; /* 0x02 */ 474 U8 Flags; /* 0x03 */ 475 U16 InitiatorDevHandle; /* 0x04 */ 476 U16 IoIndex; /* 0x06 */ 477 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 478 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 479 Mpi2TargetCommandBufferReplyDescriptor_t, 480 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 481 482 /* defines for Flags field */ 483 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) 484 485 486 /* RAID Accelerator Success Reply Descriptor */ 487 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 488 { 489 U8 ReplyFlags; /* 0x00 */ 490 U8 MSIxIndex; /* 0x01 */ 491 U16 SMID; /* 0x02 */ 492 U32 Reserved; /* 0x04 */ 493 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 494 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 495 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 496 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 497 498 499 /* union of Reply Descriptors */ 500 typedef union _MPI2_REPLY_DESCRIPTORS_UNION 501 { 502 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 503 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 504 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 505 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 506 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 507 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 508 U64 Words; 509 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 510 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 511 512 513 514 /***************************************************************************** 515 * 516 * Message Functions 517 * 518 *****************************************************************************/ 519 520 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 521 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 522 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 523 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 524 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 525 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 526 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 527 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 528 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 529 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 530 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 531 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 532 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 533 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 534 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 535 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 536 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 537 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 538 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 539 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 540 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 541 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 542 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 543 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 544 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 545 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 546 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 547 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 548 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 549 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 550 551 552 553 /* Doorbell functions */ 554 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 555 #define MPI2_FUNCTION_HANDSHAKE (0x42) 556 557 558 /***************************************************************************** 559 * 560 * IOC Status Values 561 * 562 *****************************************************************************/ 563 564 /* mask for IOCStatus status value */ 565 #define MPI2_IOCSTATUS_MASK (0x7FFF) 566 567 /**************************************************************************** 568 * Common IOCStatus values for all replies 569 ****************************************************************************/ 570 571 #define MPI2_IOCSTATUS_SUCCESS (0x0000) 572 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) 573 #define MPI2_IOCSTATUS_BUSY (0x0002) 574 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003) 575 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) 576 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005) 577 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 578 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 579 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 580 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 581 582 /**************************************************************************** 583 * Config IOCStatus values 584 ****************************************************************************/ 585 586 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 587 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 588 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 589 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 590 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 591 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 592 593 /**************************************************************************** 594 * SCSI IO Reply 595 ****************************************************************************/ 596 597 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 598 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 599 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 600 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 601 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 602 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 603 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 604 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 605 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 606 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 607 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 608 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 609 610 /**************************************************************************** 611 * For use by SCSI Initiator and SCSI Target end-to-end data protection 612 ****************************************************************************/ 613 614 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 615 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 616 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 617 618 /**************************************************************************** 619 * SCSI Target values 620 ****************************************************************************/ 621 622 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 623 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) 624 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 625 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 626 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 627 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 628 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 629 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 630 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 631 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 632 633 /**************************************************************************** 634 * Serial Attached SCSI values 635 ****************************************************************************/ 636 637 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 638 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 639 640 /**************************************************************************** 641 * Diagnostic Buffer Post / Diagnostic Release values 642 ****************************************************************************/ 643 644 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 645 646 /**************************************************************************** 647 * RAID Accelerator values 648 ****************************************************************************/ 649 650 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) 651 652 /**************************************************************************** 653 * IOCStatus flag to indicate that log info is available 654 ****************************************************************************/ 655 656 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 657 658 /**************************************************************************** 659 * IOCLogInfo Types 660 ****************************************************************************/ 661 662 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) 663 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28) 664 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0) 665 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) 666 #define MPI2_IOCLOGINFO_TYPE_FC (0x2) 667 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3) 668 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) 669 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 670 671 672 /***************************************************************************** 673 * 674 * Standard Message Structures 675 * 676 *****************************************************************************/ 677 678 /**************************************************************************** 679 * Request Message Header for all request messages 680 ****************************************************************************/ 681 682 typedef struct _MPI2_REQUEST_HEADER 683 { 684 U16 FunctionDependent1; /* 0x00 */ 685 U8 ChainOffset; /* 0x02 */ 686 U8 Function; /* 0x03 */ 687 U16 FunctionDependent2; /* 0x04 */ 688 U8 FunctionDependent3; /* 0x06 */ 689 U8 MsgFlags; /* 0x07 */ 690 U8 VP_ID; /* 0x08 */ 691 U8 VF_ID; /* 0x09 */ 692 U16 Reserved1; /* 0x0A */ 693 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER, 694 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t; 695 696 697 /**************************************************************************** 698 * Default Reply 699 ****************************************************************************/ 700 701 typedef struct _MPI2_DEFAULT_REPLY 702 { 703 U16 FunctionDependent1; /* 0x00 */ 704 U8 MsgLength; /* 0x02 */ 705 U8 Function; /* 0x03 */ 706 U16 FunctionDependent2; /* 0x04 */ 707 U8 FunctionDependent3; /* 0x06 */ 708 U8 MsgFlags; /* 0x07 */ 709 U8 VP_ID; /* 0x08 */ 710 U8 VF_ID; /* 0x09 */ 711 U16 Reserved1; /* 0x0A */ 712 U16 FunctionDependent5; /* 0x0C */ 713 U16 IOCStatus; /* 0x0E */ 714 U32 IOCLogInfo; /* 0x10 */ 715 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY, 716 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t; 717 718 719 /* common version structure/union used in messages and configuration pages */ 720 721 typedef struct _MPI2_VERSION_STRUCT 722 { 723 U8 Dev; /* 0x00 */ 724 U8 Unit; /* 0x01 */ 725 U8 Minor; /* 0x02 */ 726 U8 Major; /* 0x03 */ 727 } MPI2_VERSION_STRUCT; 728 729 typedef union _MPI2_VERSION_UNION 730 { 731 MPI2_VERSION_STRUCT Struct; 732 U32 Word; 733 } MPI2_VERSION_UNION; 734 735 736 /* LUN field defines, common to many structures */ 737 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 738 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 739 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 740 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 741 #define MPI2_LUN_LEVEL_1_WORD (0xFF00) 742 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) 743 744 745 /***************************************************************************** 746 * 747 * Fusion-MPT MPI Scatter Gather Elements 748 * 749 *****************************************************************************/ 750 751 /**************************************************************************** 752 * MPI Simple Element structures 753 ****************************************************************************/ 754 755 typedef struct _MPI2_SGE_SIMPLE32 756 { 757 U32 FlagsLength; 758 U32 Address; 759 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32, 760 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t; 761 762 typedef struct _MPI2_SGE_SIMPLE64 763 { 764 U32 FlagsLength; 765 U64 Address; 766 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64, 767 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t; 768 769 typedef struct _MPI2_SGE_SIMPLE_UNION 770 { 771 U32 FlagsLength; 772 union 773 { 774 U32 Address32; 775 U64 Address64; 776 } u; 777 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 778 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 779 780 781 /**************************************************************************** 782 * MPI Chain Element structures 783 ****************************************************************************/ 784 785 typedef struct _MPI2_SGE_CHAIN32 786 { 787 U16 Length; 788 U8 NextChainOffset; 789 U8 Flags; 790 U32 Address; 791 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32, 792 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t; 793 794 typedef struct _MPI2_SGE_CHAIN64 795 { 796 U16 Length; 797 U8 NextChainOffset; 798 U8 Flags; 799 U64 Address; 800 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64, 801 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t; 802 803 typedef struct _MPI2_SGE_CHAIN_UNION 804 { 805 U16 Length; 806 U8 NextChainOffset; 807 U8 Flags; 808 union 809 { 810 U32 Address32; 811 U64 Address64; 812 } u; 813 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 814 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 815 816 817 /**************************************************************************** 818 * MPI Transaction Context Element structures 819 ****************************************************************************/ 820 821 typedef struct _MPI2_SGE_TRANSACTION32 822 { 823 U8 Reserved; 824 U8 ContextSize; 825 U8 DetailsLength; 826 U8 Flags; 827 U32 TransactionContext[1]; 828 U32 TransactionDetails[1]; 829 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32, 830 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t; 831 832 typedef struct _MPI2_SGE_TRANSACTION64 833 { 834 U8 Reserved; 835 U8 ContextSize; 836 U8 DetailsLength; 837 U8 Flags; 838 U32 TransactionContext[2]; 839 U32 TransactionDetails[1]; 840 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64, 841 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t; 842 843 typedef struct _MPI2_SGE_TRANSACTION96 844 { 845 U8 Reserved; 846 U8 ContextSize; 847 U8 DetailsLength; 848 U8 Flags; 849 U32 TransactionContext[3]; 850 U32 TransactionDetails[1]; 851 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96, 852 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t; 853 854 typedef struct _MPI2_SGE_TRANSACTION128 855 { 856 U8 Reserved; 857 U8 ContextSize; 858 U8 DetailsLength; 859 U8 Flags; 860 U32 TransactionContext[4]; 861 U32 TransactionDetails[1]; 862 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128, 863 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128; 864 865 typedef struct _MPI2_SGE_TRANSACTION_UNION 866 { 867 U8 Reserved; 868 U8 ContextSize; 869 U8 DetailsLength; 870 U8 Flags; 871 union 872 { 873 U32 TransactionContext32[1]; 874 U32 TransactionContext64[2]; 875 U32 TransactionContext96[3]; 876 U32 TransactionContext128[4]; 877 } u; 878 U32 TransactionDetails[1]; 879 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION, 880 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t; 881 882 883 /**************************************************************************** 884 * MPI SGE union for IO SGL's 885 ****************************************************************************/ 886 887 typedef struct _MPI2_MPI_SGE_IO_UNION 888 { 889 union 890 { 891 MPI2_SGE_SIMPLE_UNION Simple; 892 MPI2_SGE_CHAIN_UNION Chain; 893 } u; 894 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION, 895 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t; 896 897 898 /**************************************************************************** 899 * MPI SGE union for SGL's with Simple and Transaction elements 900 ****************************************************************************/ 901 902 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION 903 { 904 union 905 { 906 MPI2_SGE_SIMPLE_UNION Simple; 907 MPI2_SGE_TRANSACTION_UNION Transaction; 908 } u; 909 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION, 910 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t; 911 912 913 /**************************************************************************** 914 * All MPI SGE types union 915 ****************************************************************************/ 916 917 typedef struct _MPI2_MPI_SGE_UNION 918 { 919 union 920 { 921 MPI2_SGE_SIMPLE_UNION Simple; 922 MPI2_SGE_CHAIN_UNION Chain; 923 MPI2_SGE_TRANSACTION_UNION Transaction; 924 } u; 925 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION, 926 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t; 927 928 929 /**************************************************************************** 930 * MPI SGE field definition and masks 931 ****************************************************************************/ 932 933 /* Flags field bit definitions */ 934 935 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) 936 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) 937 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 938 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) 939 #define MPI2_SGE_FLAGS_DIRECTION (0x04) 940 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) 941 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01) 942 943 #define MPI2_SGE_FLAGS_SHIFT (24) 944 945 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) 946 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 947 948 /* Element Type */ 949 950 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) 951 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 952 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) 953 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) 954 955 /* Address location */ 956 957 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 958 959 /* Direction */ 960 961 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) 962 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) 963 964 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST) 965 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC) 966 967 /* Address Size */ 968 969 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 970 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 971 972 /* Context Size */ 973 974 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) 975 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) 976 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) 977 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) 978 979 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 980 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) 981 982 /**************************************************************************** 983 * MPI SGE operation Macros 984 ****************************************************************************/ 985 986 /* SIMPLE FlagsLength manipulations... */ 987 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) 988 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT) 989 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) 990 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) 991 992 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l)) 993 994 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) 995 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) 996 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l) 997 998 /* CAUTION - The following are READ-MODIFY-WRITE! */ 999 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f) 1000 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l) 1001 1002 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT) 1003 1004 1005 /***************************************************************************** 1006 * 1007 * Fusion-MPT IEEE Scatter Gather Elements 1008 * 1009 *****************************************************************************/ 1010 1011 /**************************************************************************** 1012 * IEEE Simple Element structures 1013 ****************************************************************************/ 1014 1015 typedef struct _MPI2_IEEE_SGE_SIMPLE32 1016 { 1017 U32 Address; 1018 U32 FlagsLength; 1019 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 1020 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 1021 1022 typedef struct _MPI2_IEEE_SGE_SIMPLE64 1023 { 1024 U64 Address; 1025 U32 Length; 1026 U16 Reserved1; 1027 U8 Reserved2; 1028 U8 Flags; 1029 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 1030 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 1031 1032 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION 1033 { 1034 MPI2_IEEE_SGE_SIMPLE32 Simple32; 1035 MPI2_IEEE_SGE_SIMPLE64 Simple64; 1036 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 1037 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 1038 1039 1040 /**************************************************************************** 1041 * IEEE Chain Element structures 1042 ****************************************************************************/ 1043 1044 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 1045 1046 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 1047 1048 typedef union _MPI2_IEEE_SGE_CHAIN_UNION 1049 { 1050 MPI2_IEEE_SGE_CHAIN32 Chain32; 1051 MPI2_IEEE_SGE_CHAIN64 Chain64; 1052 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 1053 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 1054 1055 1056 /**************************************************************************** 1057 * All IEEE SGE types union 1058 ****************************************************************************/ 1059 1060 typedef struct _MPI2_IEEE_SGE_UNION 1061 { 1062 union 1063 { 1064 MPI2_IEEE_SGE_SIMPLE_UNION Simple; 1065 MPI2_IEEE_SGE_CHAIN_UNION Chain; 1066 } u; 1067 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION, 1068 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t; 1069 1070 1071 /**************************************************************************** 1072 * IEEE SGE field definitions and masks 1073 ****************************************************************************/ 1074 1075 /* Flags field bit definitions */ 1076 1077 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1078 1079 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1080 1081 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1082 1083 /* Element Type */ 1084 1085 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1086 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1087 1088 /* Data Location Address Space */ 1089 1090 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1091 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* IEEE Simple Element only */ 1092 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* IEEE Simple Element only */ 1093 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1094 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* IEEE Simple Element only */ 1095 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (0x03) /* IEEE Chain Element only */ 1096 1097 /**************************************************************************** 1098 * IEEE SGE operation Macros 1099 ****************************************************************************/ 1100 1101 /* SIMPLE FlagsLength manipulations... */ 1102 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) 1103 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT) 1104 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) 1105 1106 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l)) 1107 1108 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) 1109 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) 1110 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l) 1111 1112 /* CAUTION - The following are READ-MODIFY-WRITE! */ 1113 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f) 1114 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l) 1115 1116 1117 1118 1119 /***************************************************************************** 1120 * 1121 * Fusion-MPT MPI/IEEE Scatter Gather Unions 1122 * 1123 *****************************************************************************/ 1124 1125 typedef union _MPI2_SIMPLE_SGE_UNION 1126 { 1127 MPI2_SGE_SIMPLE_UNION MpiSimple; 1128 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1129 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION, 1130 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t; 1131 1132 1133 typedef union _MPI2_SGE_IO_UNION 1134 { 1135 MPI2_SGE_SIMPLE_UNION MpiSimple; 1136 MPI2_SGE_CHAIN_UNION MpiChain; 1137 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1138 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1139 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 1140 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 1141 1142 1143 /**************************************************************************** 1144 * 1145 * Values for SGLFlags field, used in many request messages with an SGL 1146 * 1147 ****************************************************************************/ 1148 1149 /* values for MPI SGL Data Location Address Space subfield */ 1150 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) 1151 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) 1152 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) 1153 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) 1154 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) 1155 /* values for SGL Type subfield */ 1156 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) 1157 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) 1158 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) 1159 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) 1160 1161 1162 #endif 1163 1164