1 /* $FreeBSD$ */ 2 /* 3 * Copyright (c) 2000-2009 LSI Corporation. 4 * 5 * 6 * Name: mpi2.h 7 * Title: MPI Message independent structures and definitions 8 * including System Interface Register Set and 9 * scatter/gather formats. 10 * Creation Date: June 21, 2006 11 * 12 * mpi2.h Version: 02.00.14 13 * 14 * Version History 15 * --------------- 16 * 17 * Date Version Description 18 * -------- -------- ------------------------------------------------------ 19 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 20 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. 21 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. 22 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. 23 * Moved ReplyPostHostIndex register to offset 0x6C of the 24 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for 25 * MPI2_REPLY_POST_HOST_INDEX_OFFSET. 26 * Added union of request descriptors. 27 * Added union of reply descriptors. 28 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. 29 * Added define for MPI2_VERSION_02_00. 30 * Fixed the size of the FunctionDependent5 field in the 31 * MPI2_DEFAULT_REPLY structure. 32 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. 33 * Removed the MPI-defined Fault Codes and extended the 34 * product specific codes up to 0xEFFF. 35 * Added a sixth key value for the WriteSequence register 36 * and changed the flush value to 0x0. 37 * Added message function codes for Diagnostic Buffer Post 38 * and Diagnsotic Release. 39 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED 40 * Moved MPI2_VERSION_UNION from mpi2_ioc.h. 41 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. 42 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. 43 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. 44 * Added #defines for marking a reply descriptor as unused. 45 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. 46 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. 47 * Moved LUN field defines from mpi2_init.h. 48 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. 49 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT. 50 * In all request and reply descriptors, replaced VF_ID 51 * field with MSIxIndex field. 52 * Removed DevHandle field from 53 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 54 * bytes reserved. 55 * Added RAID Accelerator functionality. 56 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT. 57 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT. 58 * Added MSI-x index mask and shift for Reply Post Host 59 * Index register. 60 * Added function code for Host Based Discovery Action. 61 * -------------------------------------------------------------------------- 62 */ 63 64 #ifndef MPI2_H 65 #define MPI2_H 66 67 68 /***************************************************************************** 69 * 70 * MPI Version Definitions 71 * 72 *****************************************************************************/ 73 74 #define MPI2_VERSION_MAJOR (0x02) 75 #define MPI2_VERSION_MINOR (0x00) 76 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 77 #define MPI2_VERSION_MAJOR_SHIFT (8) 78 #define MPI2_VERSION_MINOR_MASK (0x00FF) 79 #define MPI2_VERSION_MINOR_SHIFT (0) 80 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 81 MPI2_VERSION_MINOR) 82 83 #define MPI2_VERSION_02_00 (0x0200) 84 85 /* versioning for this MPI header set */ 86 #define MPI2_HEADER_VERSION_UNIT (0x0E) 87 #define MPI2_HEADER_VERSION_DEV (0x00) 88 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 89 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 90 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 91 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 92 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 93 94 95 /***************************************************************************** 96 * 97 * IOC State Definitions 98 * 99 *****************************************************************************/ 100 101 #define MPI2_IOC_STATE_RESET (0x00000000) 102 #define MPI2_IOC_STATE_READY (0x10000000) 103 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000) 104 #define MPI2_IOC_STATE_FAULT (0x40000000) 105 106 #define MPI2_IOC_STATE_MASK (0xF0000000) 107 #define MPI2_IOC_STATE_SHIFT (28) 108 109 /* Fault state range for prodcut specific codes */ 110 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) 111 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) 112 113 114 /***************************************************************************** 115 * 116 * System Interface Register Definitions 117 * 118 *****************************************************************************/ 119 120 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS 121 { 122 U32 Doorbell; /* 0x00 */ 123 U32 WriteSequence; /* 0x04 */ 124 U32 HostDiagnostic; /* 0x08 */ 125 U32 Reserved1; /* 0x0C */ 126 U32 DiagRWData; /* 0x10 */ 127 U32 DiagRWAddressLow; /* 0x14 */ 128 U32 DiagRWAddressHigh; /* 0x18 */ 129 U32 Reserved2[5]; /* 0x1C */ 130 U32 HostInterruptStatus; /* 0x30 */ 131 U32 HostInterruptMask; /* 0x34 */ 132 U32 DCRData; /* 0x38 */ 133 U32 DCRAddress; /* 0x3C */ 134 U32 Reserved3[2]; /* 0x40 */ 135 U32 ReplyFreeHostIndex; /* 0x48 */ 136 U32 Reserved4[8]; /* 0x4C */ 137 U32 ReplyPostHostIndex; /* 0x6C */ 138 U32 Reserved5; /* 0x70 */ 139 U32 HCBSize; /* 0x74 */ 140 U32 HCBAddressLow; /* 0x78 */ 141 U32 HCBAddressHigh; /* 0x7C */ 142 U32 Reserved6[16]; /* 0x80 */ 143 U32 RequestDescriptorPostLow; /* 0xC0 */ 144 U32 RequestDescriptorPostHigh; /* 0xC4 */ 145 U32 Reserved7[14]; /* 0xC8 */ 146 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS, 147 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t; 148 149 /* 150 * Defines for working with the Doorbell register. 151 */ 152 #define MPI2_DOORBELL_OFFSET (0x00000000) 153 154 /* IOC --> System values */ 155 #define MPI2_DOORBELL_USED (0x08000000) 156 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) 157 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24) 158 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) 159 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) 160 161 /* System --> IOC values */ 162 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) 163 #define MPI2_DOORBELL_FUNCTION_SHIFT (24) 164 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 165 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) 166 167 168 /* 169 * Defines for the WriteSequence register 170 */ 171 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 172 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) 173 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 174 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 175 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 176 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 177 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 178 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 179 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 180 181 /* 182 * Defines for the HostDiagnostic register 183 */ 184 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 185 186 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 187 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) 188 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) 189 190 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 191 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) 192 #define MPI2_DIAG_HCB_MODE (0x00000100) 193 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) 194 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) 195 #define MPI2_DIAG_RESET_HISTORY (0x00000020) 196 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) 197 #define MPI2_DIAG_RESET_ADAPTER (0x00000004) 198 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) 199 200 /* 201 * Offsets for DiagRWData and address 202 */ 203 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) 204 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) 205 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) 206 207 /* 208 * Defines for the HostInterruptStatus register 209 */ 210 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 211 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) 212 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS 213 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) 214 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) 215 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) 216 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS 217 218 /* 219 * Defines for the HostInterruptMask register 220 */ 221 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 222 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000) 223 #define MPI2_HIM_REPLY_INT_MASK (0x00000008) 224 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK 225 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) 226 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK 227 228 /* 229 * Offsets for DCRData and address 230 */ 231 #define MPI2_DCR_DATA_OFFSET (0x00000038) 232 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) 233 234 /* 235 * Offset for the Reply Free Queue 236 */ 237 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) 238 239 /* 240 * Defines for the Reply Descriptor Post Queue 241 */ 242 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 243 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) 244 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) 245 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24) 246 247 /* 248 * Defines for the HCBSize and address 249 */ 250 #define MPI2_HCB_SIZE_OFFSET (0x00000074) 251 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) 252 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) 253 254 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) 255 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) 256 257 /* 258 * Offsets for the Request Queue 259 */ 260 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) 261 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) 262 263 264 /***************************************************************************** 265 * 266 * Message Descriptors 267 * 268 *****************************************************************************/ 269 270 /* Request Descriptors */ 271 272 /* Default Request Descriptor */ 273 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR 274 { 275 U8 RequestFlags; /* 0x00 */ 276 U8 MSIxIndex; /* 0x01 */ 277 U16 SMID; /* 0x02 */ 278 U16 LMID; /* 0x04 */ 279 U16 DescriptorTypeDependent; /* 0x06 */ 280 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 281 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 282 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 283 284 /* defines for the RequestFlags field */ 285 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 286 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 287 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 288 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 289 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 290 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 291 292 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 293 294 295 /* High Priority Request Descriptor */ 296 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR 297 { 298 U8 RequestFlags; /* 0x00 */ 299 U8 MSIxIndex; /* 0x01 */ 300 U16 SMID; /* 0x02 */ 301 U16 LMID; /* 0x04 */ 302 U16 Reserved1; /* 0x06 */ 303 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 304 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 305 Mpi2HighPriorityRequestDescriptor_t, 306 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 307 308 309 /* SCSI IO Request Descriptor */ 310 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR 311 { 312 U8 RequestFlags; /* 0x00 */ 313 U8 MSIxIndex; /* 0x01 */ 314 U16 SMID; /* 0x02 */ 315 U16 LMID; /* 0x04 */ 316 U16 DevHandle; /* 0x06 */ 317 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 318 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 319 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 320 321 322 /* SCSI Target Request Descriptor */ 323 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR 324 { 325 U8 RequestFlags; /* 0x00 */ 326 U8 MSIxIndex; /* 0x01 */ 327 U16 SMID; /* 0x02 */ 328 U16 LMID; /* 0x04 */ 329 U16 IoIndex; /* 0x06 */ 330 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 331 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 332 Mpi2SCSITargetRequestDescriptor_t, 333 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 334 335 336 /* RAID Accelerator Request Descriptor */ 337 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR 338 { 339 U8 RequestFlags; /* 0x00 */ 340 U8 MSIxIndex; /* 0x01 */ 341 U16 SMID; /* 0x02 */ 342 U16 LMID; /* 0x04 */ 343 U16 Reserved; /* 0x06 */ 344 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 345 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 346 Mpi2RAIDAcceleratorRequestDescriptor_t, 347 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 348 349 350 /* union of Request Descriptors */ 351 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION 352 { 353 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 354 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 355 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 356 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 357 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 358 U64 Words; 359 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION, 360 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t; 361 362 363 /* Reply Descriptors */ 364 365 /* Default Reply Descriptor */ 366 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR 367 { 368 U8 ReplyFlags; /* 0x00 */ 369 U8 MSIxIndex; /* 0x01 */ 370 U16 DescriptorTypeDependent1; /* 0x02 */ 371 U32 DescriptorTypeDependent2; /* 0x04 */ 372 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 373 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 374 375 /* defines for the ReplyFlags field */ 376 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 377 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 378 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 379 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 380 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 381 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 382 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 383 384 /* values for marking a reply descriptor as unused */ 385 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 386 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 387 388 /* Address Reply Descriptor */ 389 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR 390 { 391 U8 ReplyFlags; /* 0x00 */ 392 U8 MSIxIndex; /* 0x01 */ 393 U16 SMID; /* 0x02 */ 394 U32 ReplyFrameAddress; /* 0x04 */ 395 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 396 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 397 398 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) 399 400 401 /* SCSI IO Success Reply Descriptor */ 402 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 403 { 404 U8 ReplyFlags; /* 0x00 */ 405 U8 MSIxIndex; /* 0x01 */ 406 U16 SMID; /* 0x02 */ 407 U16 TaskTag; /* 0x04 */ 408 U16 Reserved1; /* 0x06 */ 409 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 410 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 411 Mpi2SCSIIOSuccessReplyDescriptor_t, 412 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 413 414 415 /* TargetAssist Success Reply Descriptor */ 416 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR 417 { 418 U8 ReplyFlags; /* 0x00 */ 419 U8 MSIxIndex; /* 0x01 */ 420 U16 SMID; /* 0x02 */ 421 U8 SequenceNumber; /* 0x04 */ 422 U8 Reserved1; /* 0x05 */ 423 U16 IoIndex; /* 0x06 */ 424 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 425 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 426 Mpi2TargetAssistSuccessReplyDescriptor_t, 427 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 428 429 430 /* Target Command Buffer Reply Descriptor */ 431 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 432 { 433 U8 ReplyFlags; /* 0x00 */ 434 U8 MSIxIndex; /* 0x01 */ 435 U8 VP_ID; /* 0x02 */ 436 U8 Flags; /* 0x03 */ 437 U16 InitiatorDevHandle; /* 0x04 */ 438 U16 IoIndex; /* 0x06 */ 439 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 440 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 441 Mpi2TargetCommandBufferReplyDescriptor_t, 442 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 443 444 /* defines for Flags field */ 445 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) 446 447 448 /* RAID Accelerator Success Reply Descriptor */ 449 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 450 { 451 U8 ReplyFlags; /* 0x00 */ 452 U8 MSIxIndex; /* 0x01 */ 453 U16 SMID; /* 0x02 */ 454 U32 Reserved; /* 0x04 */ 455 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 456 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 457 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 458 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 459 460 461 /* union of Reply Descriptors */ 462 typedef union _MPI2_REPLY_DESCRIPTORS_UNION 463 { 464 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 465 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 466 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 467 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 468 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 469 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 470 U64 Words; 471 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 472 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 473 474 475 476 /***************************************************************************** 477 * 478 * Message Functions 479 * 0x80 -> 0x8F reserved for private message use per product 480 * 481 * 482 *****************************************************************************/ 483 484 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 485 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 486 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 487 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 488 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 489 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 490 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 491 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 492 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 493 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 494 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 495 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 496 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 497 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 498 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 499 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 500 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 501 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 502 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 503 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 504 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 505 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 506 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 507 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 508 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 509 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 510 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 511 512 513 514 /* Doorbell functions */ 515 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 516 #define MPI2_FUNCTION_HANDSHAKE (0x42) 517 518 519 /***************************************************************************** 520 * 521 * IOC Status Values 522 * 523 *****************************************************************************/ 524 525 /* mask for IOCStatus status value */ 526 #define MPI2_IOCSTATUS_MASK (0x7FFF) 527 528 /**************************************************************************** 529 * Common IOCStatus values for all replies 530 ****************************************************************************/ 531 532 #define MPI2_IOCSTATUS_SUCCESS (0x0000) 533 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) 534 #define MPI2_IOCSTATUS_BUSY (0x0002) 535 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003) 536 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) 537 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005) 538 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 539 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 540 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 541 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 542 543 /**************************************************************************** 544 * Config IOCStatus values 545 ****************************************************************************/ 546 547 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 548 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 549 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 550 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 551 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 552 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 553 554 /**************************************************************************** 555 * SCSI IO Reply 556 ****************************************************************************/ 557 558 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 559 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 560 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 561 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 562 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 563 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 564 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 565 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 566 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 567 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 568 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 569 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 570 571 /**************************************************************************** 572 * For use by SCSI Initiator and SCSI Target end-to-end data protection 573 ****************************************************************************/ 574 575 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 576 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 577 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 578 579 /**************************************************************************** 580 * SCSI Target values 581 ****************************************************************************/ 582 583 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 584 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) 585 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 586 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 587 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 588 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 589 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 590 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 591 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 592 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 593 594 /**************************************************************************** 595 * Serial Attached SCSI values 596 ****************************************************************************/ 597 598 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 599 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 600 601 /**************************************************************************** 602 * Diagnostic Buffer Post / Diagnostic Release values 603 ****************************************************************************/ 604 605 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 606 607 /**************************************************************************** 608 * RAID Accelerator values 609 ****************************************************************************/ 610 611 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) 612 613 /**************************************************************************** 614 * IOCStatus flag to indicate that log info is available 615 ****************************************************************************/ 616 617 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 618 619 /**************************************************************************** 620 * IOCLogInfo Types 621 ****************************************************************************/ 622 623 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) 624 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28) 625 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0) 626 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) 627 #define MPI2_IOCLOGINFO_TYPE_FC (0x2) 628 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3) 629 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) 630 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 631 632 633 /***************************************************************************** 634 * 635 * Standard Message Structures 636 * 637 *****************************************************************************/ 638 639 /**************************************************************************** 640 * Request Message Header for all request messages 641 ****************************************************************************/ 642 643 typedef struct _MPI2_REQUEST_HEADER 644 { 645 U16 FunctionDependent1; /* 0x00 */ 646 U8 ChainOffset; /* 0x02 */ 647 U8 Function; /* 0x03 */ 648 U16 FunctionDependent2; /* 0x04 */ 649 U8 FunctionDependent3; /* 0x06 */ 650 U8 MsgFlags; /* 0x07 */ 651 U8 VP_ID; /* 0x08 */ 652 U8 VF_ID; /* 0x09 */ 653 U16 Reserved1; /* 0x0A */ 654 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER, 655 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t; 656 657 658 /**************************************************************************** 659 * Default Reply 660 ****************************************************************************/ 661 662 typedef struct _MPI2_DEFAULT_REPLY 663 { 664 U16 FunctionDependent1; /* 0x00 */ 665 U8 MsgLength; /* 0x02 */ 666 U8 Function; /* 0x03 */ 667 U16 FunctionDependent2; /* 0x04 */ 668 U8 FunctionDependent3; /* 0x06 */ 669 U8 MsgFlags; /* 0x07 */ 670 U8 VP_ID; /* 0x08 */ 671 U8 VF_ID; /* 0x09 */ 672 U16 Reserved1; /* 0x0A */ 673 U16 FunctionDependent5; /* 0x0C */ 674 U16 IOCStatus; /* 0x0E */ 675 U32 IOCLogInfo; /* 0x10 */ 676 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY, 677 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t; 678 679 680 /* common version structure/union used in messages and configuration pages */ 681 682 typedef struct _MPI2_VERSION_STRUCT 683 { 684 U8 Dev; /* 0x00 */ 685 U8 Unit; /* 0x01 */ 686 U8 Minor; /* 0x02 */ 687 U8 Major; /* 0x03 */ 688 } MPI2_VERSION_STRUCT; 689 690 typedef union _MPI2_VERSION_UNION 691 { 692 MPI2_VERSION_STRUCT Struct; 693 U32 Word; 694 } MPI2_VERSION_UNION; 695 696 697 /* LUN field defines, common to many structures */ 698 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 699 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 700 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 701 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 702 #define MPI2_LUN_LEVEL_1_WORD (0xFF00) 703 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) 704 705 706 /***************************************************************************** 707 * 708 * Fusion-MPT MPI Scatter Gather Elements 709 * 710 *****************************************************************************/ 711 712 /**************************************************************************** 713 * MPI Simple Element structures 714 ****************************************************************************/ 715 716 typedef struct _MPI2_SGE_SIMPLE32 717 { 718 U32 FlagsLength; 719 U32 Address; 720 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32, 721 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t; 722 723 typedef struct _MPI2_SGE_SIMPLE64 724 { 725 U32 FlagsLength; 726 U64 Address; 727 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64, 728 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t; 729 730 typedef struct _MPI2_SGE_SIMPLE_UNION 731 { 732 U32 FlagsLength; 733 union 734 { 735 U32 Address32; 736 U64 Address64; 737 } u; 738 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 739 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 740 741 742 /**************************************************************************** 743 * MPI Chain Element structures 744 ****************************************************************************/ 745 746 typedef struct _MPI2_SGE_CHAIN32 747 { 748 U16 Length; 749 U8 NextChainOffset; 750 U8 Flags; 751 U32 Address; 752 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32, 753 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t; 754 755 typedef struct _MPI2_SGE_CHAIN64 756 { 757 U16 Length; 758 U8 NextChainOffset; 759 U8 Flags; 760 U64 Address; 761 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64, 762 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t; 763 764 typedef struct _MPI2_SGE_CHAIN_UNION 765 { 766 U16 Length; 767 U8 NextChainOffset; 768 U8 Flags; 769 union 770 { 771 U32 Address32; 772 U64 Address64; 773 } u; 774 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 775 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 776 777 778 /**************************************************************************** 779 * MPI Transaction Context Element structures 780 ****************************************************************************/ 781 782 typedef struct _MPI2_SGE_TRANSACTION32 783 { 784 U8 Reserved; 785 U8 ContextSize; 786 U8 DetailsLength; 787 U8 Flags; 788 U32 TransactionContext[1]; 789 U32 TransactionDetails[1]; 790 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32, 791 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t; 792 793 typedef struct _MPI2_SGE_TRANSACTION64 794 { 795 U8 Reserved; 796 U8 ContextSize; 797 U8 DetailsLength; 798 U8 Flags; 799 U32 TransactionContext[2]; 800 U32 TransactionDetails[1]; 801 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64, 802 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t; 803 804 typedef struct _MPI2_SGE_TRANSACTION96 805 { 806 U8 Reserved; 807 U8 ContextSize; 808 U8 DetailsLength; 809 U8 Flags; 810 U32 TransactionContext[3]; 811 U32 TransactionDetails[1]; 812 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96, 813 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t; 814 815 typedef struct _MPI2_SGE_TRANSACTION128 816 { 817 U8 Reserved; 818 U8 ContextSize; 819 U8 DetailsLength; 820 U8 Flags; 821 U32 TransactionContext[4]; 822 U32 TransactionDetails[1]; 823 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128, 824 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128; 825 826 typedef struct _MPI2_SGE_TRANSACTION_UNION 827 { 828 U8 Reserved; 829 U8 ContextSize; 830 U8 DetailsLength; 831 U8 Flags; 832 union 833 { 834 U32 TransactionContext32[1]; 835 U32 TransactionContext64[2]; 836 U32 TransactionContext96[3]; 837 U32 TransactionContext128[4]; 838 } u; 839 U32 TransactionDetails[1]; 840 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION, 841 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t; 842 843 844 /**************************************************************************** 845 * MPI SGE union for IO SGL's 846 ****************************************************************************/ 847 848 typedef struct _MPI2_MPI_SGE_IO_UNION 849 { 850 union 851 { 852 MPI2_SGE_SIMPLE_UNION Simple; 853 MPI2_SGE_CHAIN_UNION Chain; 854 } u; 855 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION, 856 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t; 857 858 859 /**************************************************************************** 860 * MPI SGE union for SGL's with Simple and Transaction elements 861 ****************************************************************************/ 862 863 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION 864 { 865 union 866 { 867 MPI2_SGE_SIMPLE_UNION Simple; 868 MPI2_SGE_TRANSACTION_UNION Transaction; 869 } u; 870 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION, 871 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t; 872 873 874 /**************************************************************************** 875 * All MPI SGE types union 876 ****************************************************************************/ 877 878 typedef struct _MPI2_MPI_SGE_UNION 879 { 880 union 881 { 882 MPI2_SGE_SIMPLE_UNION Simple; 883 MPI2_SGE_CHAIN_UNION Chain; 884 MPI2_SGE_TRANSACTION_UNION Transaction; 885 } u; 886 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION, 887 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t; 888 889 890 /**************************************************************************** 891 * MPI SGE field definition and masks 892 ****************************************************************************/ 893 894 /* Flags field bit definitions */ 895 896 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) 897 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) 898 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 899 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) 900 #define MPI2_SGE_FLAGS_DIRECTION (0x04) 901 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) 902 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01) 903 904 #define MPI2_SGE_FLAGS_SHIFT (24) 905 906 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) 907 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 908 909 /* Element Type */ 910 911 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) 912 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 913 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) 914 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) 915 916 /* Address location */ 917 918 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 919 920 /* Direction */ 921 922 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) 923 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) 924 925 /* Address Size */ 926 927 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 928 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 929 930 /* Context Size */ 931 932 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) 933 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) 934 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) 935 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) 936 937 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 938 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) 939 940 /**************************************************************************** 941 * MPI SGE operation Macros 942 ****************************************************************************/ 943 944 /* SIMPLE FlagsLength manipulations... */ 945 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) 946 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT) 947 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) 948 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) 949 950 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l)) 951 952 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) 953 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) 954 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l) 955 956 /* CAUTION - The following are READ-MODIFY-WRITE! */ 957 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f) 958 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l) 959 960 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT) 961 962 963 /***************************************************************************** 964 * 965 * Fusion-MPT IEEE Scatter Gather Elements 966 * 967 *****************************************************************************/ 968 969 /**************************************************************************** 970 * IEEE Simple Element structures 971 ****************************************************************************/ 972 973 typedef struct _MPI2_IEEE_SGE_SIMPLE32 974 { 975 U32 Address; 976 U32 FlagsLength; 977 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 978 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 979 980 typedef struct _MPI2_IEEE_SGE_SIMPLE64 981 { 982 U64 Address; 983 U32 Length; 984 U16 Reserved1; 985 U8 Reserved2; 986 U8 Flags; 987 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 988 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 989 990 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION 991 { 992 MPI2_IEEE_SGE_SIMPLE32 Simple32; 993 MPI2_IEEE_SGE_SIMPLE64 Simple64; 994 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 995 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 996 997 998 /**************************************************************************** 999 * IEEE Chain Element structures 1000 ****************************************************************************/ 1001 1002 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 1003 1004 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 1005 1006 typedef union _MPI2_IEEE_SGE_CHAIN_UNION 1007 { 1008 MPI2_IEEE_SGE_CHAIN32 Chain32; 1009 MPI2_IEEE_SGE_CHAIN64 Chain64; 1010 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 1011 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 1012 1013 1014 /**************************************************************************** 1015 * All IEEE SGE types union 1016 ****************************************************************************/ 1017 1018 typedef struct _MPI2_IEEE_SGE_UNION 1019 { 1020 union 1021 { 1022 MPI2_IEEE_SGE_SIMPLE_UNION Simple; 1023 MPI2_IEEE_SGE_CHAIN_UNION Chain; 1024 } u; 1025 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION, 1026 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t; 1027 1028 1029 /**************************************************************************** 1030 * IEEE SGE field definitions and masks 1031 ****************************************************************************/ 1032 1033 /* Flags field bit definitions */ 1034 1035 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1036 1037 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1038 1039 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1040 1041 /* Element Type */ 1042 1043 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1044 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1045 1046 /* Data Location Address Space */ 1047 1048 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1049 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) 1050 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) 1051 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1052 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) 1053 1054 1055 /**************************************************************************** 1056 * IEEE SGE operation Macros 1057 ****************************************************************************/ 1058 1059 /* SIMPLE FlagsLength manipulations... */ 1060 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) 1061 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT) 1062 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) 1063 1064 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l)) 1065 1066 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) 1067 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) 1068 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l) 1069 1070 /* CAUTION - The following are READ-MODIFY-WRITE! */ 1071 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f) 1072 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l) 1073 1074 1075 1076 1077 /***************************************************************************** 1078 * 1079 * Fusion-MPT MPI/IEEE Scatter Gather Unions 1080 * 1081 *****************************************************************************/ 1082 1083 typedef union _MPI2_SIMPLE_SGE_UNION 1084 { 1085 MPI2_SGE_SIMPLE_UNION MpiSimple; 1086 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1087 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION, 1088 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t; 1089 1090 1091 typedef union _MPI2_SGE_IO_UNION 1092 { 1093 MPI2_SGE_SIMPLE_UNION MpiSimple; 1094 MPI2_SGE_CHAIN_UNION MpiChain; 1095 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1096 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1097 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 1098 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 1099 1100 1101 /**************************************************************************** 1102 * 1103 * Values for SGLFlags field, used in many request messages with an SGL 1104 * 1105 ****************************************************************************/ 1106 1107 /* values for MPI SGL Data Location Address Space subfield */ 1108 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) 1109 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) 1110 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) 1111 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) 1112 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) 1113 /* values for SGL Type subfield */ 1114 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) 1115 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) 1116 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) 1117 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) 1118 1119 1120 #endif 1121 1122