1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2006-2015 LSI Corp. 5 * Copyright (c) 2013-2015 Avago Technologies 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD 30 * 31 * $FreeBSD$ 32 */ 33 34 /* 35 * Copyright (c) 2006-2015 LSI Corporation. 36 * Copyright (c) 2013-2015 Avago Technologies 37 * 38 * 39 * Name: mpi2.h 40 * Title: MPI Message independent structures and definitions 41 * including System Interface Register Set and 42 * scatter/gather formats. 43 * Creation Date: June 21, 2006 44 * 45 * mpi2.h Version: 02.00.18 46 * 47 * Version History 48 * --------------- 49 * 50 * Date Version Description 51 * -------- -------- ------------------------------------------------------ 52 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 53 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. 54 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. 55 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. 56 * Moved ReplyPostHostIndex register to offset 0x6C of the 57 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for 58 * MPI2_REPLY_POST_HOST_INDEX_OFFSET. 59 * Added union of request descriptors. 60 * Added union of reply descriptors. 61 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. 62 * Added define for MPI2_VERSION_02_00. 63 * Fixed the size of the FunctionDependent5 field in the 64 * MPI2_DEFAULT_REPLY structure. 65 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. 66 * Removed the MPI-defined Fault Codes and extended the 67 * product specific codes up to 0xEFFF. 68 * Added a sixth key value for the WriteSequence register 69 * and changed the flush value to 0x0. 70 * Added message function codes for Diagnostic Buffer Post 71 * and Diagnsotic Release. 72 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED 73 * Moved MPI2_VERSION_UNION from mpi2_ioc.h. 74 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. 75 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. 76 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. 77 * Added #defines for marking a reply descriptor as unused. 78 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. 79 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. 80 * Moved LUN field defines from mpi2_init.h. 81 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. 82 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT. 83 * In all request and reply descriptors, replaced VF_ID 84 * field with MSIxIndex field. 85 * Removed DevHandle field from 86 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 87 * bytes reserved. 88 * Added RAID Accelerator functionality. 89 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT. 90 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT. 91 * Added MSI-x index mask and shift for Reply Post Host 92 * Index register. 93 * Added function code for Host Based Discovery Action. 94 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT. 95 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL. 96 * Added defines for product-specific range of message 97 * function codes, 0xF0 to 0xFF. 98 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT. 99 * Added alternative defines for the SGE Direction bit. 100 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT. 101 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT. 102 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define. 103 * -------------------------------------------------------------------------- 104 */ 105 106 #ifndef MPI2_H 107 #define MPI2_H 108 109 /***************************************************************************** 110 * 111 * MPI Version Definitions 112 * 113 *****************************************************************************/ 114 115 #define MPI2_VERSION_MAJOR (0x02) 116 #define MPI2_VERSION_MINOR (0x00) 117 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 118 #define MPI2_VERSION_MAJOR_SHIFT (8) 119 #define MPI2_VERSION_MINOR_MASK (0x00FF) 120 #define MPI2_VERSION_MINOR_SHIFT (0) 121 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 122 MPI2_VERSION_MINOR) 123 124 #define MPI2_VERSION_02_00 (0x0200) 125 126 /* versioning for this MPI header set */ 127 #define MPI2_HEADER_VERSION_UNIT (0x12) 128 #define MPI2_HEADER_VERSION_DEV (0x00) 129 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 130 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 131 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 132 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 133 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 134 135 /***************************************************************************** 136 * 137 * IOC State Definitions 138 * 139 *****************************************************************************/ 140 141 #define MPI2_IOC_STATE_RESET (0x00000000) 142 #define MPI2_IOC_STATE_READY (0x10000000) 143 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000) 144 #define MPI2_IOC_STATE_FAULT (0x40000000) 145 146 #define MPI2_IOC_STATE_MASK (0xF0000000) 147 #define MPI2_IOC_STATE_SHIFT (28) 148 149 /* Fault state range for prodcut specific codes */ 150 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) 151 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) 152 153 /***************************************************************************** 154 * 155 * System Interface Register Definitions 156 * 157 *****************************************************************************/ 158 159 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS 160 { 161 U32 Doorbell; /* 0x00 */ 162 U32 WriteSequence; /* 0x04 */ 163 U32 HostDiagnostic; /* 0x08 */ 164 U32 Reserved1; /* 0x0C */ 165 U32 DiagRWData; /* 0x10 */ 166 U32 DiagRWAddressLow; /* 0x14 */ 167 U32 DiagRWAddressHigh; /* 0x18 */ 168 U32 Reserved2[5]; /* 0x1C */ 169 U32 HostInterruptStatus; /* 0x30 */ 170 U32 HostInterruptMask; /* 0x34 */ 171 U32 DCRData; /* 0x38 */ 172 U32 DCRAddress; /* 0x3C */ 173 U32 Reserved3[2]; /* 0x40 */ 174 U32 ReplyFreeHostIndex; /* 0x48 */ 175 U32 Reserved4[8]; /* 0x4C */ 176 U32 ReplyPostHostIndex; /* 0x6C */ 177 U32 Reserved5; /* 0x70 */ 178 U32 HCBSize; /* 0x74 */ 179 U32 HCBAddressLow; /* 0x78 */ 180 U32 HCBAddressHigh; /* 0x7C */ 181 U32 Reserved6[16]; /* 0x80 */ 182 U32 RequestDescriptorPostLow; /* 0xC0 */ 183 U32 RequestDescriptorPostHigh; /* 0xC4 */ 184 U32 Reserved7[14]; /* 0xC8 */ 185 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS, 186 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t; 187 188 /* 189 * Defines for working with the Doorbell register. 190 */ 191 #define MPI2_DOORBELL_OFFSET (0x00000000) 192 193 /* IOC --> System values */ 194 #define MPI2_DOORBELL_USED (0x08000000) 195 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) 196 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24) 197 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) 198 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) 199 200 /* System --> IOC values */ 201 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) 202 #define MPI2_DOORBELL_FUNCTION_SHIFT (24) 203 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 204 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) 205 206 /* 207 * Defines for the WriteSequence register 208 */ 209 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 210 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) 211 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 212 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 213 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 214 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 215 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 216 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 217 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 218 219 /* 220 * Defines for the HostDiagnostic register 221 */ 222 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 223 224 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 225 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) 226 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) 227 228 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 229 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) 230 #define MPI2_DIAG_HCB_MODE (0x00000100) 231 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) 232 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) 233 #define MPI2_DIAG_RESET_HISTORY (0x00000020) 234 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) 235 #define MPI2_DIAG_RESET_ADAPTER (0x00000004) 236 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) 237 238 /* 239 * Offsets for DiagRWData and address 240 */ 241 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) 242 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) 243 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) 244 245 /* 246 * Defines for the HostInterruptStatus register 247 */ 248 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 249 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) 250 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS 251 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) 252 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) 253 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) 254 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS 255 256 /* 257 * Defines for the HostInterruptMask register 258 */ 259 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 260 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000) 261 #define MPI2_HIM_REPLY_INT_MASK (0x00000008) 262 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK 263 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) 264 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK 265 266 /* 267 * Offsets for DCRData and address 268 */ 269 #define MPI2_DCR_DATA_OFFSET (0x00000038) 270 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) 271 272 /* 273 * Offset for the Reply Free Queue 274 */ 275 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) 276 277 /* 278 * Defines for the Reply Descriptor Post Queue 279 */ 280 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 281 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) 282 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) 283 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24) 284 285 /* 286 * Defines for the HCBSize and address 287 */ 288 #define MPI2_HCB_SIZE_OFFSET (0x00000074) 289 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) 290 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) 291 292 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) 293 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) 294 295 /* 296 * Offsets for the Request Queue 297 */ 298 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) 299 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) 300 301 /***************************************************************************** 302 * 303 * Message Descriptors 304 * 305 *****************************************************************************/ 306 307 /* Request Descriptors */ 308 309 /* Default Request Descriptor */ 310 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR 311 { 312 U8 RequestFlags; /* 0x00 */ 313 U8 MSIxIndex; /* 0x01 */ 314 U16 SMID; /* 0x02 */ 315 U16 LMID; /* 0x04 */ 316 U16 DescriptorTypeDependent; /* 0x06 */ 317 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 318 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 319 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 320 321 /* defines for the RequestFlags field */ 322 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x0E) 323 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 324 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 325 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 326 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 327 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 328 329 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 330 331 /* High Priority Request Descriptor */ 332 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR 333 { 334 U8 RequestFlags; /* 0x00 */ 335 U8 MSIxIndex; /* 0x01 */ 336 U16 SMID; /* 0x02 */ 337 U16 LMID; /* 0x04 */ 338 U16 Reserved1; /* 0x06 */ 339 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 340 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 341 Mpi2HighPriorityRequestDescriptor_t, 342 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 343 344 /* SCSI IO Request Descriptor */ 345 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR 346 { 347 U8 RequestFlags; /* 0x00 */ 348 U8 MSIxIndex; /* 0x01 */ 349 U16 SMID; /* 0x02 */ 350 U16 LMID; /* 0x04 */ 351 U16 DevHandle; /* 0x06 */ 352 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 353 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 354 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 355 356 /* SCSI Target Request Descriptor */ 357 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR 358 { 359 U8 RequestFlags; /* 0x00 */ 360 U8 MSIxIndex; /* 0x01 */ 361 U16 SMID; /* 0x02 */ 362 U16 LMID; /* 0x04 */ 363 U16 IoIndex; /* 0x06 */ 364 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 365 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 366 Mpi2SCSITargetRequestDescriptor_t, 367 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 368 369 /* RAID Accelerator Request Descriptor */ 370 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR 371 { 372 U8 RequestFlags; /* 0x00 */ 373 U8 MSIxIndex; /* 0x01 */ 374 U16 SMID; /* 0x02 */ 375 U16 LMID; /* 0x04 */ 376 U16 Reserved; /* 0x06 */ 377 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 378 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 379 Mpi2RAIDAcceleratorRequestDescriptor_t, 380 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 381 382 /* union of Request Descriptors */ 383 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION 384 { 385 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 386 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 387 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 388 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 389 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 390 U64 Words; 391 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION, 392 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t; 393 394 /* Reply Descriptors */ 395 396 /* Default Reply Descriptor */ 397 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR 398 { 399 U8 ReplyFlags; /* 0x00 */ 400 U8 MSIxIndex; /* 0x01 */ 401 U16 DescriptorTypeDependent1; /* 0x02 */ 402 U32 DescriptorTypeDependent2; /* 0x04 */ 403 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 404 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 405 406 /* defines for the ReplyFlags field */ 407 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 408 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 409 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 410 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 411 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 412 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 413 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 414 415 /* values for marking a reply descriptor as unused */ 416 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 417 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 418 419 /* Address Reply Descriptor */ 420 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR 421 { 422 U8 ReplyFlags; /* 0x00 */ 423 U8 MSIxIndex; /* 0x01 */ 424 U16 SMID; /* 0x02 */ 425 U32 ReplyFrameAddress; /* 0x04 */ 426 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 427 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 428 429 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) 430 431 /* SCSI IO Success Reply Descriptor */ 432 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 433 { 434 U8 ReplyFlags; /* 0x00 */ 435 U8 MSIxIndex; /* 0x01 */ 436 U16 SMID; /* 0x02 */ 437 U16 TaskTag; /* 0x04 */ 438 U16 Reserved1; /* 0x06 */ 439 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 440 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 441 Mpi2SCSIIOSuccessReplyDescriptor_t, 442 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 443 444 /* TargetAssist Success Reply Descriptor */ 445 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR 446 { 447 U8 ReplyFlags; /* 0x00 */ 448 U8 MSIxIndex; /* 0x01 */ 449 U16 SMID; /* 0x02 */ 450 U8 SequenceNumber; /* 0x04 */ 451 U8 Reserved1; /* 0x05 */ 452 U16 IoIndex; /* 0x06 */ 453 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 454 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 455 Mpi2TargetAssistSuccessReplyDescriptor_t, 456 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 457 458 /* Target Command Buffer Reply Descriptor */ 459 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 460 { 461 U8 ReplyFlags; /* 0x00 */ 462 U8 MSIxIndex; /* 0x01 */ 463 U8 VP_ID; /* 0x02 */ 464 U8 Flags; /* 0x03 */ 465 U16 InitiatorDevHandle; /* 0x04 */ 466 U16 IoIndex; /* 0x06 */ 467 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 468 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 469 Mpi2TargetCommandBufferReplyDescriptor_t, 470 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 471 472 /* defines for Flags field */ 473 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) 474 475 /* RAID Accelerator Success Reply Descriptor */ 476 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 477 { 478 U8 ReplyFlags; /* 0x00 */ 479 U8 MSIxIndex; /* 0x01 */ 480 U16 SMID; /* 0x02 */ 481 U32 Reserved; /* 0x04 */ 482 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 483 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 484 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 485 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 486 487 /* union of Reply Descriptors */ 488 typedef union _MPI2_REPLY_DESCRIPTORS_UNION 489 { 490 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 491 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 492 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 493 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 494 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 495 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 496 U64 Words; 497 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 498 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 499 500 /***************************************************************************** 501 * 502 * Message Functions 503 * 504 *****************************************************************************/ 505 506 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 507 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 508 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 509 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 510 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 511 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 512 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 513 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 514 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 515 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 516 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 517 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 518 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 519 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 520 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 521 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 522 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 523 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 524 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 525 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ 526 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 527 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 528 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 529 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 530 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 531 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 532 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 533 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 534 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 535 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 536 537 /* Doorbell functions */ 538 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 539 #define MPI2_FUNCTION_HANDSHAKE (0x42) 540 541 /***************************************************************************** 542 * 543 * IOC Status Values 544 * 545 *****************************************************************************/ 546 547 /* mask for IOCStatus status value */ 548 #define MPI2_IOCSTATUS_MASK (0x7FFF) 549 550 /**************************************************************************** 551 * Common IOCStatus values for all replies 552 ****************************************************************************/ 553 554 #define MPI2_IOCSTATUS_SUCCESS (0x0000) 555 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) 556 #define MPI2_IOCSTATUS_BUSY (0x0002) 557 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003) 558 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) 559 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005) 560 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 561 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 562 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 563 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 564 565 /**************************************************************************** 566 * Config IOCStatus values 567 ****************************************************************************/ 568 569 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 570 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 571 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 572 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 573 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 574 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 575 576 /**************************************************************************** 577 * SCSI IO Reply 578 ****************************************************************************/ 579 580 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 581 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 582 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 583 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 584 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 585 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 586 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 587 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 588 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 589 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 590 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 591 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 592 593 /**************************************************************************** 594 * For use by SCSI Initiator and SCSI Target end-to-end data protection 595 ****************************************************************************/ 596 597 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 598 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 599 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 600 601 /**************************************************************************** 602 * SCSI Target values 603 ****************************************************************************/ 604 605 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 606 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) 607 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 608 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 609 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 610 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 611 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 612 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 613 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 614 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 615 616 /**************************************************************************** 617 * Serial Attached SCSI values 618 ****************************************************************************/ 619 620 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 621 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 622 623 /**************************************************************************** 624 * Diagnostic Buffer Post / Diagnostic Release values 625 ****************************************************************************/ 626 627 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 628 629 /**************************************************************************** 630 * RAID Accelerator values 631 ****************************************************************************/ 632 633 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) 634 635 /**************************************************************************** 636 * IOCStatus flag to indicate that log info is available 637 ****************************************************************************/ 638 639 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 640 641 /**************************************************************************** 642 * IOCLogInfo Types 643 ****************************************************************************/ 644 645 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) 646 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28) 647 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0) 648 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) 649 #define MPI2_IOCLOGINFO_TYPE_FC (0x2) 650 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3) 651 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) 652 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 653 654 /***************************************************************************** 655 * 656 * Standard Message Structures 657 * 658 *****************************************************************************/ 659 660 /**************************************************************************** 661 * Request Message Header for all request messages 662 ****************************************************************************/ 663 664 typedef struct _MPI2_REQUEST_HEADER 665 { 666 U16 FunctionDependent1; /* 0x00 */ 667 U8 ChainOffset; /* 0x02 */ 668 U8 Function; /* 0x03 */ 669 U16 FunctionDependent2; /* 0x04 */ 670 U8 FunctionDependent3; /* 0x06 */ 671 U8 MsgFlags; /* 0x07 */ 672 U8 VP_ID; /* 0x08 */ 673 U8 VF_ID; /* 0x09 */ 674 U16 Reserved1; /* 0x0A */ 675 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER, 676 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t; 677 678 /**************************************************************************** 679 * Default Reply 680 ****************************************************************************/ 681 682 typedef struct _MPI2_DEFAULT_REPLY 683 { 684 U16 FunctionDependent1; /* 0x00 */ 685 U8 MsgLength; /* 0x02 */ 686 U8 Function; /* 0x03 */ 687 U16 FunctionDependent2; /* 0x04 */ 688 U8 FunctionDependent3; /* 0x06 */ 689 U8 MsgFlags; /* 0x07 */ 690 U8 VP_ID; /* 0x08 */ 691 U8 VF_ID; /* 0x09 */ 692 U16 Reserved1; /* 0x0A */ 693 U16 FunctionDependent5; /* 0x0C */ 694 U16 IOCStatus; /* 0x0E */ 695 U32 IOCLogInfo; /* 0x10 */ 696 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY, 697 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t; 698 699 /* common version structure/union used in messages and configuration pages */ 700 701 typedef struct _MPI2_VERSION_STRUCT 702 { 703 U8 Dev; /* 0x00 */ 704 U8 Unit; /* 0x01 */ 705 U8 Minor; /* 0x02 */ 706 U8 Major; /* 0x03 */ 707 } MPI2_VERSION_STRUCT; 708 709 typedef union _MPI2_VERSION_UNION 710 { 711 MPI2_VERSION_STRUCT Struct; 712 U32 Word; 713 } MPI2_VERSION_UNION; 714 715 /* LUN field defines, common to many structures */ 716 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 717 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 718 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 719 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 720 #define MPI2_LUN_LEVEL_1_WORD (0xFF00) 721 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) 722 723 /***************************************************************************** 724 * 725 * Fusion-MPT MPI Scatter Gather Elements 726 * 727 *****************************************************************************/ 728 729 /**************************************************************************** 730 * MPI Simple Element structures 731 ****************************************************************************/ 732 733 typedef struct _MPI2_SGE_SIMPLE32 734 { 735 U32 FlagsLength; 736 U32 Address; 737 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32, 738 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t; 739 740 typedef struct _MPI2_SGE_SIMPLE64 741 { 742 U32 FlagsLength; 743 U64 Address; 744 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64, 745 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t; 746 747 typedef struct _MPI2_SGE_SIMPLE_UNION 748 { 749 U32 FlagsLength; 750 union 751 { 752 U32 Address32; 753 U64 Address64; 754 } u; 755 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 756 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 757 758 /**************************************************************************** 759 * MPI Chain Element structures 760 ****************************************************************************/ 761 762 typedef struct _MPI2_SGE_CHAIN32 763 { 764 U16 Length; 765 U8 NextChainOffset; 766 U8 Flags; 767 U32 Address; 768 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32, 769 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t; 770 771 typedef struct _MPI2_SGE_CHAIN64 772 { 773 U16 Length; 774 U8 NextChainOffset; 775 U8 Flags; 776 U64 Address; 777 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64, 778 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t; 779 780 typedef struct _MPI2_SGE_CHAIN_UNION 781 { 782 U16 Length; 783 U8 NextChainOffset; 784 U8 Flags; 785 union 786 { 787 U32 Address32; 788 U64 Address64; 789 } u; 790 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 791 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 792 793 /**************************************************************************** 794 * MPI Transaction Context Element structures 795 ****************************************************************************/ 796 797 typedef struct _MPI2_SGE_TRANSACTION32 798 { 799 U8 Reserved; 800 U8 ContextSize; 801 U8 DetailsLength; 802 U8 Flags; 803 U32 TransactionContext[1]; 804 U32 TransactionDetails[1]; 805 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32, 806 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t; 807 808 typedef struct _MPI2_SGE_TRANSACTION64 809 { 810 U8 Reserved; 811 U8 ContextSize; 812 U8 DetailsLength; 813 U8 Flags; 814 U32 TransactionContext[2]; 815 U32 TransactionDetails[1]; 816 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64, 817 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t; 818 819 typedef struct _MPI2_SGE_TRANSACTION96 820 { 821 U8 Reserved; 822 U8 ContextSize; 823 U8 DetailsLength; 824 U8 Flags; 825 U32 TransactionContext[3]; 826 U32 TransactionDetails[1]; 827 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96, 828 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t; 829 830 typedef struct _MPI2_SGE_TRANSACTION128 831 { 832 U8 Reserved; 833 U8 ContextSize; 834 U8 DetailsLength; 835 U8 Flags; 836 U32 TransactionContext[4]; 837 U32 TransactionDetails[1]; 838 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128, 839 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128; 840 841 typedef struct _MPI2_SGE_TRANSACTION_UNION 842 { 843 U8 Reserved; 844 U8 ContextSize; 845 U8 DetailsLength; 846 U8 Flags; 847 union 848 { 849 U32 TransactionContext32[1]; 850 U32 TransactionContext64[2]; 851 U32 TransactionContext96[3]; 852 U32 TransactionContext128[4]; 853 } u; 854 U32 TransactionDetails[1]; 855 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION, 856 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t; 857 858 /**************************************************************************** 859 * MPI SGE union for IO SGL's 860 ****************************************************************************/ 861 862 typedef struct _MPI2_MPI_SGE_IO_UNION 863 { 864 union 865 { 866 MPI2_SGE_SIMPLE_UNION Simple; 867 MPI2_SGE_CHAIN_UNION Chain; 868 } u; 869 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION, 870 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t; 871 872 /**************************************************************************** 873 * MPI SGE union for SGL's with Simple and Transaction elements 874 ****************************************************************************/ 875 876 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION 877 { 878 union 879 { 880 MPI2_SGE_SIMPLE_UNION Simple; 881 MPI2_SGE_TRANSACTION_UNION Transaction; 882 } u; 883 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION, 884 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t; 885 886 /**************************************************************************** 887 * All MPI SGE types union 888 ****************************************************************************/ 889 890 typedef struct _MPI2_MPI_SGE_UNION 891 { 892 union 893 { 894 MPI2_SGE_SIMPLE_UNION Simple; 895 MPI2_SGE_CHAIN_UNION Chain; 896 MPI2_SGE_TRANSACTION_UNION Transaction; 897 } u; 898 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION, 899 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t; 900 901 /**************************************************************************** 902 * MPI SGE field definition and masks 903 ****************************************************************************/ 904 905 /* Flags field bit definitions */ 906 907 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) 908 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) 909 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 910 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) 911 #define MPI2_SGE_FLAGS_DIRECTION (0x04) 912 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) 913 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01) 914 915 #define MPI2_SGE_FLAGS_SHIFT (24) 916 917 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) 918 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 919 920 /* Element Type */ 921 922 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) 923 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 924 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) 925 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) 926 927 /* Address location */ 928 929 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 930 931 /* Direction */ 932 933 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) 934 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) 935 936 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST) 937 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC) 938 939 /* Address Size */ 940 941 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 942 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 943 944 /* Context Size */ 945 946 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) 947 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) 948 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) 949 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) 950 951 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 952 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) 953 954 /**************************************************************************** 955 * MPI SGE operation Macros 956 ****************************************************************************/ 957 958 /* SIMPLE FlagsLength manipulations... */ 959 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) 960 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT) 961 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) 962 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) 963 964 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l)) 965 966 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) 967 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) 968 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l) 969 970 /* CAUTION - The following are READ-MODIFY-WRITE! */ 971 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f) 972 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l) 973 974 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT) 975 976 /***************************************************************************** 977 * 978 * Fusion-MPT IEEE Scatter Gather Elements 979 * 980 *****************************************************************************/ 981 982 /**************************************************************************** 983 * IEEE Simple Element structures 984 ****************************************************************************/ 985 986 typedef struct _MPI2_IEEE_SGE_SIMPLE32 987 { 988 U32 Address; 989 U32 FlagsLength; 990 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 991 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 992 993 typedef struct _MPI2_IEEE_SGE_SIMPLE64 994 { 995 U64 Address; 996 U32 Length; 997 U16 Reserved1; 998 U8 Reserved2; 999 U8 Flags; 1000 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 1001 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 1002 1003 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION 1004 { 1005 MPI2_IEEE_SGE_SIMPLE32 Simple32; 1006 MPI2_IEEE_SGE_SIMPLE64 Simple64; 1007 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 1008 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 1009 1010 /**************************************************************************** 1011 * IEEE Chain Element structures 1012 ****************************************************************************/ 1013 1014 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 1015 1016 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 1017 1018 typedef union _MPI2_IEEE_SGE_CHAIN_UNION 1019 { 1020 MPI2_IEEE_SGE_CHAIN32 Chain32; 1021 MPI2_IEEE_SGE_CHAIN64 Chain64; 1022 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 1023 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 1024 1025 /**************************************************************************** 1026 * All IEEE SGE types union 1027 ****************************************************************************/ 1028 1029 typedef struct _MPI2_IEEE_SGE_UNION 1030 { 1031 union 1032 { 1033 MPI2_IEEE_SGE_SIMPLE_UNION Simple; 1034 MPI2_IEEE_SGE_CHAIN_UNION Chain; 1035 } u; 1036 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION, 1037 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t; 1038 1039 /**************************************************************************** 1040 * IEEE SGE field definitions and masks 1041 ****************************************************************************/ 1042 1043 /* Flags field bit definitions */ 1044 1045 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1046 1047 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1048 1049 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1050 1051 /* Element Type */ 1052 1053 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1054 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1055 1056 /* Data Location Address Space */ 1057 1058 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1059 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* IEEE Simple Element only */ 1060 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* IEEE Simple Element only */ 1061 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1062 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* IEEE Simple Element only */ 1063 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (0x03) /* IEEE Chain Element only */ 1064 1065 /**************************************************************************** 1066 * IEEE SGE operation Macros 1067 ****************************************************************************/ 1068 1069 /* SIMPLE FlagsLength manipulations... */ 1070 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) 1071 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT) 1072 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) 1073 1074 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l)) 1075 1076 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) 1077 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) 1078 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l) 1079 1080 /* CAUTION - The following are READ-MODIFY-WRITE! */ 1081 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f) 1082 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l) 1083 1084 /***************************************************************************** 1085 * 1086 * Fusion-MPT MPI/IEEE Scatter Gather Unions 1087 * 1088 *****************************************************************************/ 1089 1090 typedef union _MPI2_SIMPLE_SGE_UNION 1091 { 1092 MPI2_SGE_SIMPLE_UNION MpiSimple; 1093 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1094 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION, 1095 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t; 1096 1097 typedef union _MPI2_SGE_IO_UNION 1098 { 1099 MPI2_SGE_SIMPLE_UNION MpiSimple; 1100 MPI2_SGE_CHAIN_UNION MpiChain; 1101 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1102 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1103 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 1104 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 1105 1106 /**************************************************************************** 1107 * 1108 * Values for SGLFlags field, used in many request messages with an SGL 1109 * 1110 ****************************************************************************/ 1111 1112 /* values for MPI SGL Data Location Address Space subfield */ 1113 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) 1114 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) 1115 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) 1116 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) 1117 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) 1118 /* values for SGL Type subfield */ 1119 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) 1120 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) 1121 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) 1122 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) 1123 1124 #endif 1125