1 /*- 2 * Copyright (c) 2009 Yahoo! Inc. 3 * Copyright (c) 2011-2015 LSI Corp. 4 * Copyright (c) 2013-2016 Avago Technologies 5 * Copyright 2000-2020 Broadcom Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD 30 * 31 * $FreeBSD$ 32 */ 33 34 #ifndef _MPRVAR_H 35 #define _MPRVAR_H 36 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 40 #define MPR_DRIVER_VERSION "23.00.00.00-fbsd" 41 42 #define MPR_DB_MAX_WAIT 2500 43 44 #define MPR_REQ_FRAMES 2048 45 #define MPR_PRI_REQ_FRAMES 128 46 #define MPR_EVT_REPLY_FRAMES 32 47 #define MPR_REPLY_FRAMES MPR_REQ_FRAMES 48 #define MPR_CHAIN_FRAMES 16384 49 #define MPR_MAXIO_PAGES (-1) 50 #define MPR_SENSE_LEN SSD_FULL_SIZE 51 #define MPR_MSI_MAX 1 52 #define MPR_MSIX_MAX 96 53 #define MPR_SGE64_SIZE 12 54 #define MPR_SGE32_SIZE 8 55 #define MPR_SGC_SIZE 8 56 #define MPR_DEFAULT_CHAIN_SEG_SIZE 8 57 #define MPR_MAX_CHAIN_ELEMENT_SIZE 16 58 59 /* 60 * PCIe NVMe Specific defines 61 */ 62 //SLM-for now just use the same value as a SAS disk 63 #define NVME_QDEPTH MPR_REQ_FRAMES 64 #define PRP_ENTRY_SIZE 8 65 #define NVME_CMD_PRP1_OFFSET 24 /* PRP1 offset in NVMe cmd */ 66 #define NVME_CMD_PRP2_OFFSET 32 /* PRP2 offset in NVMe cmd */ 67 #define NVME_ERROR_RESPONSE_SIZE 16 /* Max NVME Error Response */ 68 #define HOST_PAGE_SIZE_4K 12 69 70 #define MPR_FUNCTRACE(sc) \ 71 mpr_dprint((sc), MPR_TRACE, "%s\n", __func__) 72 73 #define CAN_SLEEP 1 74 #define NO_SLEEP 0 75 76 #define MPR_PERIODIC_DELAY 1 /* 1 second heartbeat/watchdog check */ 77 #define MPR_ATA_ID_TIMEOUT 5 /* 5 second timeout for SATA ID cmd */ 78 #define MPR_MISSING_CHECK_DELAY 10 /* 10 seconds between missing check */ 79 80 #define IFAULT_IOP_OVER_TEMP_THRESHOLD_EXCEEDED 0x2810 81 82 #define MPR_SCSI_RI_INVALID_FRAME (0x00000002) 83 84 #define DEFAULT_SPINUP_WAIT 3 /* seconds to wait for spinup */ 85 86 #include <sys/endian.h> 87 88 /* 89 * host mapping related macro definitions 90 */ 91 #define MPR_MAPTABLE_BAD_IDX 0xFFFFFFFF 92 #define MPR_DPM_BAD_IDX 0xFFFF 93 #define MPR_ENCTABLE_BAD_IDX 0xFF 94 #define MPR_MAX_MISSING_COUNT 0x0F 95 #define MPR_DEV_RESERVED 0x20000000 96 #define MPR_MAP_IN_USE 0x10000000 97 #define MPR_MAP_BAD_ID 0xFFFFFFFF 98 99 typedef uint8_t u8; 100 typedef uint16_t u16; 101 typedef uint32_t u32; 102 typedef uint64_t u64; 103 104 typedef struct _MPI2_CONFIG_PAGE_MAN_11 105 { 106 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 107 U8 FlashTime; /* 0x04 */ 108 U8 NVTime; /* 0x05 */ 109 U16 Flag; /* 0x06 */ 110 U8 RFIoTimeout; /* 0x08 */ 111 U8 EEDPTagMode; /* 0x09 */ 112 U8 AWTValue; /* 0x0A */ 113 U8 Reserve1; /* 0x0B */ 114 U8 MaxCmdFrames; /* 0x0C */ 115 U8 Reserve2; /* 0x0D */ 116 U16 AddlFlags; /* 0x0E */ 117 U32 SysRefClk; /* 0x10 */ 118 U64 Reserve3[3]; /* 0x14 */ 119 U16 AddlFlags2; /* 0x2C */ 120 U8 AddlFlags3; /* 0x2E */ 121 U8 Reserve4; /* 0x2F */ 122 U64 opDebugEnable; /* 0x30 */ 123 U64 PlDebugEnable; /* 0x38 */ 124 U64 IrDebugEnable; /* 0x40 */ 125 U32 BoardPowerRequirement; /* 0x48 */ 126 U8 NVMeAbortTO; /* 0x4C */ 127 U8 Reserve5; /* 0x4D */ 128 U16 Reserve6; /* 0x4E */ 129 U32 Reserve7[3]; /* 0x50 */ 130 } MPI2_CONFIG_PAGE_MAN_11, 131 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_11, 132 Mpi2ManufacturingPage11_t, MPI2_POINTER pMpi2ManufacturingPage11_t; 133 134 #define MPI2_MAN_PG11_ADDLFLAGS2_CUSTOM_TM_HANDLING_MASK (0x0010) 135 136 /** 137 * struct dev_mapping_table - device mapping information 138 * @physical_id: SAS address for drives or WWID for RAID volumes 139 * @device_info: bitfield provides detailed info about the device 140 * @phy_bits: bitfields indicating controller phys 141 * @dpm_entry_num: index of this device in device persistent map table 142 * @dev_handle: device handle for the device pointed by this entry 143 * @id: target id 144 * @missing_count: number of times the device not detected by driver 145 * @hide_flag: Hide this physical disk/not (foreign configuration) 146 * @init_complete: Whether the start of the day checks completed or not 147 * @TLR_bits: Turn TLR support on or off 148 */ 149 struct dev_mapping_table { 150 u64 physical_id; 151 u32 device_info; 152 u32 phy_bits; 153 u16 dpm_entry_num; 154 u16 dev_handle; 155 u16 reserved1; 156 u16 id; 157 u8 missing_count; 158 u8 init_complete; 159 u8 TLR_bits; 160 u8 reserved2; 161 }; 162 163 /** 164 * struct enc_mapping_table - mapping information about an enclosure 165 * @enclosure_id: Logical ID of this enclosure 166 * @start_index: index to the entry in dev_mapping_table 167 * @phy_bits: bitfields indicating controller phys 168 * @dpm_entry_num: index of this enclosure in device persistent map table 169 * @enc_handle: device handle for the enclosure pointed by this entry 170 * @num_slots: number of slots in the enclosure 171 * @start_slot: Starting slot id 172 * @missing_count: number of times the device not detected by driver 173 * @removal_flag: used to mark the device for removal 174 * @skip_search: used as a flag to include/exclude enclosure for search 175 * @init_complete: Whether the start of the day checks completed or not 176 */ 177 struct enc_mapping_table { 178 u64 enclosure_id; 179 u32 start_index; 180 u32 phy_bits; 181 u16 dpm_entry_num; 182 u16 enc_handle; 183 u16 num_slots; 184 u16 start_slot; 185 u8 missing_count; 186 u8 removal_flag; 187 u8 skip_search; 188 u8 init_complete; 189 }; 190 191 /** 192 * struct map_removal_table - entries to be removed from mapping table 193 * @dpm_entry_num: index of this device in device persistent map table 194 * @dev_handle: device handle for the device pointed by this entry 195 */ 196 struct map_removal_table{ 197 u16 dpm_entry_num; 198 u16 dev_handle; 199 }; 200 201 typedef struct mpr_fw_diagnostic_buffer { 202 size_t size; 203 uint8_t extended_type; 204 uint8_t buffer_type; 205 uint8_t force_release; 206 uint32_t product_specific[23]; 207 uint8_t immediate; 208 uint8_t enabled; 209 uint8_t valid_data; 210 uint8_t owned_by_firmware; 211 uint32_t unique_id; 212 } mpr_fw_diagnostic_buffer_t; 213 214 struct mpr_softc; 215 struct mpr_command; 216 struct mprsas_softc; 217 union ccb; 218 struct mprsas_target; 219 struct mpr_column_map; 220 221 MALLOC_DECLARE(M_MPR); 222 223 typedef void mpr_evt_callback_t(struct mpr_softc *, uintptr_t, 224 MPI2_EVENT_NOTIFICATION_REPLY *reply); 225 typedef void mpr_command_callback_t(struct mpr_softc *, struct mpr_command *cm); 226 227 struct mpr_chain { 228 TAILQ_ENTRY(mpr_chain) chain_link; 229 void *chain; 230 uint64_t chain_busaddr; 231 }; 232 233 struct mpr_prp_page { 234 TAILQ_ENTRY(mpr_prp_page) prp_page_link; 235 uint64_t *prp_page; 236 uint64_t prp_page_busaddr; 237 }; 238 239 /* 240 * This needs to be at least 2 to support SMP passthrough. 241 */ 242 #define MPR_IOVEC_COUNT 2 243 244 struct mpr_command { 245 TAILQ_ENTRY(mpr_command) cm_link; 246 TAILQ_ENTRY(mpr_command) cm_recovery; 247 struct mpr_softc *cm_sc; 248 union ccb *cm_ccb; 249 void *cm_data; 250 u_int cm_length; 251 u_int cm_out_len; 252 struct uio cm_uio; 253 struct iovec cm_iovec[MPR_IOVEC_COUNT]; 254 u_int cm_max_segs; 255 u_int cm_sglsize; 256 void *cm_sge; 257 uint8_t *cm_req; 258 uint8_t *cm_reply; 259 uint32_t cm_reply_data; 260 mpr_command_callback_t *cm_complete; 261 void *cm_complete_data; 262 struct mprsas_target *cm_targ; 263 MPI2_REQUEST_DESCRIPTOR_UNION cm_desc; 264 u_int cm_lun; 265 u_int cm_flags; 266 #define MPR_CM_FLAGS_POLLED (1 << 0) 267 #define MPR_CM_FLAGS_COMPLETE (1 << 1) 268 #define MPR_CM_FLAGS_SGE_SIMPLE (1 << 2) 269 #define MPR_CM_FLAGS_DATAOUT (1 << 3) 270 #define MPR_CM_FLAGS_DATAIN (1 << 4) 271 #define MPR_CM_FLAGS_WAKEUP (1 << 5) 272 #define MPR_CM_FLAGS_USE_UIO (1 << 6) 273 #define MPR_CM_FLAGS_SMP_PASS (1 << 7) 274 #define MPR_CM_FLAGS_CHAIN_FAILED (1 << 8) 275 #define MPR_CM_FLAGS_ERROR_MASK MPR_CM_FLAGS_CHAIN_FAILED 276 #define MPR_CM_FLAGS_USE_CCB (1 << 9) 277 #define MPR_CM_FLAGS_SATA_ID_TIMEOUT (1 << 10) 278 u_int cm_state; 279 #define MPR_CM_STATE_FREE 0 280 #define MPR_CM_STATE_BUSY 1 281 #define MPR_CM_STATE_TIMEDOUT 2 282 #define MPR_CM_STATE_INQUEUE 3 283 bus_dmamap_t cm_dmamap; 284 struct scsi_sense_data *cm_sense; 285 uint64_t *nvme_error_response; 286 TAILQ_HEAD(, mpr_chain) cm_chain_list; 287 TAILQ_HEAD(, mpr_prp_page) cm_prp_page_list; 288 uint32_t cm_req_busaddr; 289 bus_addr_t cm_sense_busaddr; 290 struct callout cm_callout; 291 mpr_command_callback_t *cm_timeout_handler; 292 }; 293 294 struct mpr_column_map { 295 uint16_t dev_handle; 296 uint8_t phys_disk_num; 297 }; 298 299 struct mpr_event_handle { 300 TAILQ_ENTRY(mpr_event_handle) eh_list; 301 mpr_evt_callback_t *callback; 302 void *data; 303 uint8_t mask[16]; 304 }; 305 306 struct mpr_busdma_context { 307 int completed; 308 int abandoned; 309 int error; 310 bus_addr_t *addr; 311 struct mpr_softc *softc; 312 bus_dmamap_t buffer_dmamap; 313 bus_dma_tag_t buffer_dmat; 314 }; 315 316 struct mpr_queue { 317 struct mpr_softc *sc; 318 int qnum; 319 MPI2_REPLY_DESCRIPTORS_UNION *post_queue; 320 int replypostindex; 321 #ifdef notyet 322 ck_ring_buffer_t *ringmem; 323 ck_ring_buffer_t *chainmem; 324 ck_ring_t req_ring; 325 ck_ring_t chain_ring; 326 #endif 327 bus_dma_tag_t buffer_dmat; 328 int io_cmds_highwater; 329 int chain_free_lowwater; 330 int chain_alloc_fail; 331 struct resource *irq; 332 void *intrhand; 333 int irq_rid; 334 }; 335 336 struct mpr_softc { 337 device_t mpr_dev; 338 struct cdev *mpr_cdev; 339 u_int mpr_flags; 340 #define MPR_FLAGS_INTX (1 << 0) 341 #define MPR_FLAGS_MSI (1 << 1) 342 #define MPR_FLAGS_BUSY (1 << 2) 343 #define MPR_FLAGS_SHUTDOWN (1 << 3) 344 #define MPR_FLAGS_DIAGRESET (1 << 4) 345 #define MPR_FLAGS_ATTACH_DONE (1 << 5) 346 #define MPR_FLAGS_GEN35_IOC (1 << 6) 347 #define MPR_FLAGS_REALLOCATED (1 << 7) 348 #define MPR_FLAGS_SEA_IOC (1 << 8) 349 u_int mpr_debug; 350 int msi_msgs; 351 u_int reqframesz; 352 u_int replyframesz; 353 u_int atomic_desc_capable; 354 int tm_cmds_active; 355 int io_cmds_active; 356 int io_cmds_highwater; 357 int chain_free; 358 int max_chains; 359 int max_io_pages; 360 u_int maxio; 361 int chain_free_lowwater; 362 uint32_t chain_frame_size; 363 int prp_buffer_size; 364 int prp_pages_free; 365 int prp_pages_free_lowwater; 366 u_int enable_ssu; 367 int spinup_wait_time; 368 int use_phynum; 369 uint64_t chain_alloc_fail; 370 uint64_t prp_page_alloc_fail; 371 struct sysctl_ctx_list sysctl_ctx; 372 struct sysctl_oid *sysctl_tree; 373 char fw_version[16]; 374 struct mpr_command *commands; 375 struct mpr_chain *chains; 376 struct mpr_prp_page *prps; 377 struct callout periodic; 378 struct callout device_check_callout; 379 struct mpr_queue *queues; 380 381 struct mprsas_softc *sassc; 382 TAILQ_HEAD(, mpr_command) req_list; 383 TAILQ_HEAD(, mpr_command) high_priority_req_list; 384 TAILQ_HEAD(, mpr_chain) chain_list; 385 TAILQ_HEAD(, mpr_prp_page) prp_page_list; 386 TAILQ_HEAD(, mpr_command) tm_list; 387 int replypostindex; 388 int replyfreeindex; 389 390 struct resource *mpr_regs_resource; 391 bus_space_handle_t mpr_bhandle; 392 bus_space_tag_t mpr_btag; 393 int mpr_regs_rid; 394 395 bus_dma_tag_t mpr_parent_dmat; 396 bus_dma_tag_t buffer_dmat; 397 398 MPI2_IOC_FACTS_REPLY *facts; 399 int num_reqs; 400 int num_prireqs; 401 int num_replies; 402 int num_chains; 403 int fqdepth; /* Free queue */ 404 int pqdepth; /* Post queue */ 405 406 uint8_t event_mask[16]; 407 TAILQ_HEAD(, mpr_event_handle) event_list; 408 struct mpr_event_handle *mpr_log_eh; 409 410 struct mtx mpr_mtx; 411 struct intr_config_hook mpr_ich; 412 413 uint8_t *req_frames; 414 bus_addr_t req_busaddr; 415 bus_dma_tag_t req_dmat; 416 bus_dmamap_t req_map; 417 418 uint8_t *reply_frames; 419 bus_addr_t reply_busaddr; 420 bus_dma_tag_t reply_dmat; 421 bus_dmamap_t reply_map; 422 423 struct scsi_sense_data *sense_frames; 424 bus_addr_t sense_busaddr; 425 bus_dma_tag_t sense_dmat; 426 bus_dmamap_t sense_map; 427 428 uint8_t *chain_frames; 429 bus_dma_tag_t chain_dmat; 430 bus_dmamap_t chain_map; 431 432 uint8_t *prp_pages; 433 bus_addr_t prp_page_busaddr; 434 bus_dma_tag_t prp_page_dmat; 435 bus_dmamap_t prp_page_map; 436 437 MPI2_REPLY_DESCRIPTORS_UNION *post_queue; 438 bus_addr_t post_busaddr; 439 uint32_t *free_queue; 440 bus_addr_t free_busaddr; 441 bus_dma_tag_t queues_dmat; 442 bus_dmamap_t queues_map; 443 444 uint8_t *fw_diag_buffer; 445 bus_addr_t fw_diag_busaddr; 446 bus_dma_tag_t fw_diag_dmat; 447 bus_dmamap_t fw_diag_map; 448 449 uint8_t ir_firmware; 450 451 /* static config pages */ 452 Mpi2IOCPage8_t ioc_pg8; 453 Mpi2IOUnitPage8_t iounit_pg8; 454 455 /* host mapping support */ 456 struct dev_mapping_table *mapping_table; 457 struct enc_mapping_table *enclosure_table; 458 struct map_removal_table *removal_table; 459 uint8_t *dpm_entry_used; 460 uint8_t *dpm_flush_entry; 461 Mpi2DriverMappingPage0_t *dpm_pg0; 462 uint16_t max_devices; 463 uint16_t max_enclosures; 464 uint16_t max_expanders; 465 uint8_t max_volumes; 466 uint8_t num_enc_table_entries; 467 uint8_t num_rsvd_entries; 468 uint16_t max_dpm_entries; 469 uint8_t is_dpm_enable; 470 uint8_t track_mapping_events; 471 uint32_t pending_map_events; 472 473 /* FW diag Buffer List */ 474 mpr_fw_diagnostic_buffer_t 475 fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT]; 476 477 /* Event Recording IOCTL support */ 478 uint32_t events_to_record[4]; 479 mpr_event_entry_t recorded_events[MPR_EVENT_QUEUE_SIZE]; 480 uint8_t event_index; 481 uint32_t event_number; 482 483 /* EEDP and TLR support */ 484 uint8_t eedp_enabled; 485 uint8_t control_TLR; 486 487 /* Shutdown Event Handler */ 488 eventhandler_tag shutdown_eh; 489 490 /* To track topo events during reset */ 491 #define MPR_DIAG_RESET_TIMEOUT 300000 492 uint8_t wait_for_port_enable; 493 uint8_t port_enable_complete; 494 uint8_t msleep_fake_chan; 495 496 /* StartStopUnit command handling at shutdown */ 497 uint32_t SSU_refcount; 498 uint8_t SSU_started; 499 500 /* Configuration tunables */ 501 u_int disable_msix; 502 u_int disable_msi; 503 u_int max_msix; 504 u_int max_reqframes; 505 u_int max_prireqframes; 506 u_int max_replyframes; 507 u_int max_evtframes; 508 char exclude_ids[80]; 509 510 struct timeval lastfail; 511 uint8_t custom_nvme_tm_handling; 512 uint8_t nvme_abort_timeout; 513 }; 514 515 struct mpr_config_params { 516 MPI2_CONFIG_EXT_PAGE_HEADER_UNION hdr; 517 u_int action; 518 u_int page_address; /* Attributes, not a phys address */ 519 u_int status; 520 void *buffer; 521 u_int length; 522 int timeout; 523 void (*callback)(struct mpr_softc *, struct mpr_config_params *); 524 void *cbdata; 525 }; 526 527 struct scsi_read_capacity_eedp 528 { 529 uint8_t addr[8]; 530 uint8_t length[4]; 531 uint8_t protect; 532 }; 533 534 static __inline uint32_t 535 mpr_regread(struct mpr_softc *sc, uint32_t offset) 536 { 537 uint32_t ret_val, i = 0; 538 do { 539 ret_val = 540 bus_space_read_4(sc->mpr_btag, sc->mpr_bhandle, offset); 541 } while((sc->mpr_flags & MPR_FLAGS_SEA_IOC) && 542 (ret_val == 0) && (++i < 3)); 543 544 return ret_val; 545 } 546 547 static __inline void 548 mpr_regwrite(struct mpr_softc *sc, uint32_t offset, uint32_t val) 549 { 550 bus_space_write_4(sc->mpr_btag, sc->mpr_bhandle, offset, val); 551 } 552 553 /* free_queue must have Little Endian address 554 * TODO- cm_reply_data is unwanted. We can remove it. 555 * */ 556 static __inline void 557 mpr_free_reply(struct mpr_softc *sc, uint32_t busaddr) 558 { 559 if (++sc->replyfreeindex >= sc->fqdepth) 560 sc->replyfreeindex = 0; 561 sc->free_queue[sc->replyfreeindex] = htole32(busaddr); 562 mpr_regwrite(sc, MPI2_REPLY_FREE_HOST_INDEX_OFFSET, sc->replyfreeindex); 563 } 564 565 static __inline struct mpr_chain * 566 mpr_alloc_chain(struct mpr_softc *sc) 567 { 568 struct mpr_chain *chain; 569 570 if ((chain = TAILQ_FIRST(&sc->chain_list)) != NULL) { 571 TAILQ_REMOVE(&sc->chain_list, chain, chain_link); 572 sc->chain_free--; 573 if (sc->chain_free < sc->chain_free_lowwater) 574 sc->chain_free_lowwater = sc->chain_free; 575 } else 576 sc->chain_alloc_fail++; 577 return (chain); 578 } 579 580 static __inline void 581 mpr_free_chain(struct mpr_softc *sc, struct mpr_chain *chain) 582 { 583 #if 0 584 bzero(chain->chain, 128); 585 #endif 586 sc->chain_free++; 587 TAILQ_INSERT_TAIL(&sc->chain_list, chain, chain_link); 588 } 589 590 static __inline struct mpr_prp_page * 591 mpr_alloc_prp_page(struct mpr_softc *sc) 592 { 593 struct mpr_prp_page *prp_page; 594 595 if ((prp_page = TAILQ_FIRST(&sc->prp_page_list)) != NULL) { 596 TAILQ_REMOVE(&sc->prp_page_list, prp_page, prp_page_link); 597 sc->prp_pages_free--; 598 if (sc->prp_pages_free < sc->prp_pages_free_lowwater) 599 sc->prp_pages_free_lowwater = sc->prp_pages_free; 600 } else 601 sc->prp_page_alloc_fail++; 602 return (prp_page); 603 } 604 605 static __inline void 606 mpr_free_prp_page(struct mpr_softc *sc, struct mpr_prp_page *prp_page) 607 { 608 sc->prp_pages_free++; 609 TAILQ_INSERT_TAIL(&sc->prp_page_list, prp_page, prp_page_link); 610 } 611 612 static __inline void 613 mpr_free_command(struct mpr_softc *sc, struct mpr_command *cm) 614 { 615 struct mpr_chain *chain, *chain_temp; 616 struct mpr_prp_page *prp_page, *prp_page_temp; 617 618 KASSERT(cm->cm_state == MPR_CM_STATE_BUSY, ("state not busy\n")); 619 620 if (cm->cm_reply != NULL) 621 mpr_free_reply(sc, cm->cm_reply_data); 622 cm->cm_reply = NULL; 623 cm->cm_flags = 0; 624 cm->cm_complete = NULL; 625 cm->cm_complete_data = NULL; 626 cm->cm_ccb = NULL; 627 cm->cm_targ = NULL; 628 cm->cm_max_segs = 0; 629 cm->cm_lun = 0; 630 cm->cm_state = MPR_CM_STATE_FREE; 631 cm->cm_data = NULL; 632 cm->cm_length = 0; 633 cm->cm_out_len = 0; 634 cm->cm_sglsize = 0; 635 cm->cm_sge = NULL; 636 637 TAILQ_FOREACH_SAFE(chain, &cm->cm_chain_list, chain_link, chain_temp) { 638 TAILQ_REMOVE(&cm->cm_chain_list, chain, chain_link); 639 mpr_free_chain(sc, chain); 640 } 641 TAILQ_FOREACH_SAFE(prp_page, &cm->cm_prp_page_list, prp_page_link, 642 prp_page_temp) { 643 TAILQ_REMOVE(&cm->cm_prp_page_list, prp_page, prp_page_link); 644 mpr_free_prp_page(sc, prp_page); 645 } 646 TAILQ_INSERT_TAIL(&sc->req_list, cm, cm_link); 647 } 648 649 static __inline struct mpr_command * 650 mpr_alloc_command(struct mpr_softc *sc) 651 { 652 struct mpr_command *cm; 653 654 cm = TAILQ_FIRST(&sc->req_list); 655 if (cm == NULL) 656 return (NULL); 657 658 KASSERT(cm->cm_state == MPR_CM_STATE_FREE, 659 ("mpr: Allocating busy command\n")); 660 661 TAILQ_REMOVE(&sc->req_list, cm, cm_link); 662 cm->cm_state = MPR_CM_STATE_BUSY; 663 cm->cm_timeout_handler = NULL; 664 return (cm); 665 } 666 667 static __inline void 668 mpr_free_high_priority_command(struct mpr_softc *sc, struct mpr_command *cm) 669 { 670 struct mpr_chain *chain, *chain_temp; 671 672 KASSERT(cm->cm_state == MPR_CM_STATE_BUSY, ("state not busy\n")); 673 674 if (cm->cm_reply != NULL) 675 mpr_free_reply(sc, cm->cm_reply_data); 676 cm->cm_reply = NULL; 677 cm->cm_flags = 0; 678 cm->cm_complete = NULL; 679 cm->cm_complete_data = NULL; 680 cm->cm_ccb = NULL; 681 cm->cm_targ = NULL; 682 cm->cm_lun = 0; 683 cm->cm_state = MPR_CM_STATE_FREE; 684 TAILQ_FOREACH_SAFE(chain, &cm->cm_chain_list, chain_link, chain_temp) { 685 TAILQ_REMOVE(&cm->cm_chain_list, chain, chain_link); 686 mpr_free_chain(sc, chain); 687 } 688 TAILQ_INSERT_TAIL(&sc->high_priority_req_list, cm, cm_link); 689 } 690 691 static __inline struct mpr_command * 692 mpr_alloc_high_priority_command(struct mpr_softc *sc) 693 { 694 struct mpr_command *cm; 695 696 cm = TAILQ_FIRST(&sc->high_priority_req_list); 697 if (cm == NULL) 698 return (NULL); 699 700 KASSERT(cm->cm_state == MPR_CM_STATE_FREE, 701 ("mpr: Allocating busy command\n")); 702 703 TAILQ_REMOVE(&sc->high_priority_req_list, cm, cm_link); 704 cm->cm_state = MPR_CM_STATE_BUSY; 705 cm->cm_timeout_handler = NULL; 706 cm->cm_desc.HighPriority.RequestFlags = 707 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY; 708 return (cm); 709 } 710 711 static __inline void 712 mpr_lock(struct mpr_softc *sc) 713 { 714 mtx_lock(&sc->mpr_mtx); 715 } 716 717 static __inline void 718 mpr_unlock(struct mpr_softc *sc) 719 { 720 mtx_unlock(&sc->mpr_mtx); 721 } 722 723 #define MPR_INFO (1 << 0) /* Basic info */ 724 #define MPR_FAULT (1 << 1) /* Hardware faults */ 725 #define MPR_EVENT (1 << 2) /* Event data from the controller */ 726 #define MPR_LOG (1 << 3) /* Log data from the controller */ 727 #define MPR_RECOVERY (1 << 4) /* Command error recovery tracing */ 728 #define MPR_ERROR (1 << 5) /* Parameter errors, programming bugs */ 729 #define MPR_INIT (1 << 6) /* Things related to system init */ 730 #define MPR_XINFO (1 << 7) /* More detailed/noisy info */ 731 #define MPR_USER (1 << 8) /* Trace user-generated commands */ 732 #define MPR_MAPPING (1 << 9) /* Trace device mappings */ 733 #define MPR_TRACE (1 << 10) /* Function-by-function trace */ 734 735 #define MPR_SSU_DISABLE_SSD_DISABLE_HDD 0 736 #define MPR_SSU_ENABLE_SSD_DISABLE_HDD 1 737 #define MPR_SSU_DISABLE_SSD_ENABLE_HDD 2 738 #define MPR_SSU_ENABLE_SSD_ENABLE_HDD 3 739 740 #define mpr_printf(sc, args...) \ 741 device_printf((sc)->mpr_dev, ##args) 742 743 #define mpr_print_field(sc, msg, args...) \ 744 printf("\t" msg, ##args) 745 746 #define mpr_vprintf(sc, args...) \ 747 do { \ 748 if (bootverbose) \ 749 mpr_printf(sc, ##args); \ 750 } while (0) 751 752 #define mpr_dprint(sc, level, msg, args...) \ 753 do { \ 754 if ((sc)->mpr_debug & (level)) \ 755 device_printf((sc)->mpr_dev, msg, ##args); \ 756 } while (0) 757 758 #define MPR_PRINTFIELD_START(sc, tag...) \ 759 mpr_printf((sc), ##tag); \ 760 mpr_print_field((sc), ":\n") 761 #define MPR_PRINTFIELD_END(sc, tag) \ 762 mpr_printf((sc), tag "\n") 763 #define MPR_PRINTFIELD(sc, facts, attr, fmt) \ 764 mpr_print_field((sc), #attr ": " #fmt "\n", (facts)->attr) 765 766 static __inline void 767 mpr_from_u64(uint64_t data, U64 *mpr) 768 { 769 (mpr)->High = htole32((uint32_t)((data) >> 32)); 770 (mpr)->Low = htole32((uint32_t)((data) & 0xffffffff)); 771 } 772 773 static __inline uint64_t 774 mpr_to_u64(U64 *data) 775 { 776 return (((uint64_t)le32toh(data->High) << 32) | le32toh(data->Low)); 777 } 778 779 static __inline void 780 mpr_mask_intr(struct mpr_softc *sc) 781 { 782 uint32_t mask; 783 784 mask = mpr_regread(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET); 785 mask |= MPI2_HIM_REPLY_INT_MASK; 786 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET, mask); 787 } 788 789 static __inline void 790 mpr_unmask_intr(struct mpr_softc *sc) 791 { 792 uint32_t mask; 793 794 mask = mpr_regread(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET); 795 mask &= ~MPI2_HIM_REPLY_INT_MASK; 796 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET, mask); 797 } 798 799 int mpr_pci_setup_interrupts(struct mpr_softc *sc); 800 void mpr_pci_free_interrupts(struct mpr_softc *sc); 801 int mpr_pci_restore(struct mpr_softc *sc); 802 803 void mpr_get_tunables(struct mpr_softc *sc); 804 int mpr_attach(struct mpr_softc *sc); 805 int mpr_free(struct mpr_softc *sc); 806 void mpr_intr(void *); 807 void mpr_intr_msi(void *); 808 void mpr_intr_locked(void *); 809 int mpr_register_events(struct mpr_softc *, uint8_t *, mpr_evt_callback_t *, 810 void *, struct mpr_event_handle **); 811 int mpr_restart(struct mpr_softc *); 812 int mpr_update_events(struct mpr_softc *, struct mpr_event_handle *, uint8_t *); 813 int mpr_deregister_events(struct mpr_softc *, struct mpr_event_handle *); 814 void mpr_build_nvme_prp(struct mpr_softc *sc, struct mpr_command *cm, 815 Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request, void *data, 816 uint32_t data_in_sz, uint32_t data_out_sz); 817 int mpr_push_sge(struct mpr_command *, MPI2_SGE_SIMPLE64 *, size_t, int); 818 int mpr_push_ieee_sge(struct mpr_command *, void *, int); 819 int mpr_add_dmaseg(struct mpr_command *, vm_paddr_t, size_t, u_int, int); 820 int mpr_attach_sas(struct mpr_softc *sc); 821 int mpr_detach_sas(struct mpr_softc *sc); 822 int mpr_read_config_page(struct mpr_softc *, struct mpr_config_params *); 823 int mpr_write_config_page(struct mpr_softc *, struct mpr_config_params *); 824 void mpr_memaddr_cb(void *, bus_dma_segment_t *, int , int ); 825 void mpr_memaddr_wait_cb(void *, bus_dma_segment_t *, int , int ); 826 void mpr_init_sge(struct mpr_command *cm, void *req, void *sge); 827 int mpr_attach_user(struct mpr_softc *); 828 void mpr_detach_user(struct mpr_softc *); 829 void mprsas_record_event(struct mpr_softc *sc, 830 MPI2_EVENT_NOTIFICATION_REPLY *event_reply); 831 832 int mpr_map_command(struct mpr_softc *sc, struct mpr_command *cm); 833 int mpr_wait_command(struct mpr_softc *sc, struct mpr_command **cm, int timeout, 834 int sleep_flag); 835 int mpr_request_polled(struct mpr_softc *sc, struct mpr_command **cm); 836 837 int mpr_config_get_bios_pg3(struct mpr_softc *sc, Mpi2ConfigReply_t 838 *mpi_reply, Mpi2BiosPage3_t *config_page); 839 int mpr_config_get_raid_volume_pg0(struct mpr_softc *sc, Mpi2ConfigReply_t 840 *mpi_reply, Mpi2RaidVolPage0_t *config_page, u32 page_address); 841 int mpr_config_get_ioc_pg8(struct mpr_softc *sc, Mpi2ConfigReply_t *, 842 Mpi2IOCPage8_t *); 843 int mpr_config_get_iounit_pg8(struct mpr_softc *sc, 844 Mpi2ConfigReply_t *mpi_reply, Mpi2IOUnitPage8_t *config_page); 845 int mpr_config_get_sas_device_pg0(struct mpr_softc *, Mpi2ConfigReply_t *, 846 Mpi2SasDevicePage0_t *, u32 , u16 ); 847 int mpr_config_get_pcie_device_pg0(struct mpr_softc *sc, Mpi2ConfigReply_t 848 *mpi_reply, Mpi26PCIeDevicePage0_t *config_page, u32 form, u16 handle); 849 int mpr_config_get_pcie_device_pg2(struct mpr_softc *sc, Mpi2ConfigReply_t 850 *mpi_reply, Mpi26PCIeDevicePage2_t *config_page, u32 form, u16 handle); 851 int mpr_config_get_dpm_pg0(struct mpr_softc *, Mpi2ConfigReply_t *, 852 Mpi2DriverMappingPage0_t *, u16 ); 853 int mpr_config_get_raid_volume_pg1(struct mpr_softc *sc, 854 Mpi2ConfigReply_t *mpi_reply, Mpi2RaidVolPage1_t *config_page, u32 form, 855 u16 handle); 856 int mpr_config_get_volume_wwid(struct mpr_softc *sc, u16 volume_handle, 857 u64 *wwid); 858 int mpr_config_get_raid_pd_pg0(struct mpr_softc *sc, 859 Mpi2ConfigReply_t *mpi_reply, Mpi2RaidPhysDiskPage0_t *config_page, 860 u32 page_address); 861 int mpr_config_get_man_pg11(struct mpr_softc *sc, Mpi2ConfigReply_t *mpi_reply, 862 Mpi2ManufacturingPage11_t *config_page); 863 void mprsas_ir_shutdown(struct mpr_softc *sc, int howto); 864 865 int mpr_reinit(struct mpr_softc *sc); 866 void mprsas_handle_reinit(struct mpr_softc *sc); 867 868 void mpr_base_static_config_pages(struct mpr_softc *sc); 869 870 int mpr_mapping_initialize(struct mpr_softc *); 871 void mpr_mapping_topology_change_event(struct mpr_softc *, 872 Mpi2EventDataSasTopologyChangeList_t *); 873 void mpr_mapping_pcie_topology_change_event(struct mpr_softc *sc, 874 Mpi26EventDataPCIeTopologyChangeList_t *event_data); 875 void mpr_mapping_free_memory(struct mpr_softc *sc); 876 int mpr_config_set_dpm_pg0(struct mpr_softc *, Mpi2ConfigReply_t *, 877 Mpi2DriverMappingPage0_t *, u16 ); 878 void mpr_mapping_exit(struct mpr_softc *); 879 void mpr_mapping_check_devices(void *); 880 int mpr_mapping_allocate_memory(struct mpr_softc *sc); 881 unsigned int mpr_mapping_get_tid(struct mpr_softc *, uint64_t , u16); 882 unsigned int mpr_mapping_get_tid_from_handle(struct mpr_softc *sc, 883 u16 handle); 884 unsigned int mpr_mapping_get_raid_tid(struct mpr_softc *sc, u64 wwid, 885 u16 volHandle); 886 unsigned int mpr_mapping_get_raid_tid_from_handle(struct mpr_softc *sc, 887 u16 volHandle); 888 void mpr_mapping_enclosure_dev_status_change_event(struct mpr_softc *, 889 Mpi2EventDataSasEnclDevStatusChange_t *event_data); 890 void mpr_mapping_ir_config_change_event(struct mpr_softc *sc, 891 Mpi2EventDataIrConfigChangeList_t *event_data); 892 893 void mprsas_evt_handler(struct mpr_softc *sc, uintptr_t data, 894 MPI2_EVENT_NOTIFICATION_REPLY *event); 895 void mprsas_prepare_remove(struct mprsas_softc *sassc, uint16_t handle); 896 void mprsas_prepare_volume_remove(struct mprsas_softc *sassc, uint16_t handle); 897 int mprsas_startup(struct mpr_softc *sc); 898 struct mprsas_target * mprsas_find_target_by_handle(struct mprsas_softc *, int, 899 uint16_t); 900 void mprsas_realloc_targets(struct mpr_softc *sc, int maxtargets); 901 struct mpr_command * mprsas_alloc_tm(struct mpr_softc *sc); 902 void mprsas_free_tm(struct mpr_softc *sc, struct mpr_command *tm); 903 void mprsas_release_simq_reinit(struct mprsas_softc *sassc); 904 int mprsas_send_reset(struct mpr_softc *sc, struct mpr_command *tm, 905 uint8_t type); 906 907 SYSCTL_DECL(_hw_mpr); 908 909 /* Compatibility shims for different OS versions */ 910 #if __FreeBSD_version >= 800001 911 #define mpr_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 912 kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 913 #define mpr_kproc_exit(arg) kproc_exit(arg) 914 #else 915 #define mpr_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 916 kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 917 #define mpr_kproc_exit(arg) kthread_exit(arg) 918 #endif 919 920 #if defined(CAM_PRIORITY_XPT) 921 #define MPR_PRIORITY_XPT CAM_PRIORITY_XPT 922 #else 923 #define MPR_PRIORITY_XPT 5 924 #endif 925 926 #if __FreeBSD_version < 800107 927 // Prior to FreeBSD-8.0 scp3_flags was not defined. 928 #define spc3_flags reserved 929 930 #define SPC3_SID_PROTECT 0x01 931 #define SPC3_SID_3PC 0x08 932 #define SPC3_SID_TPGS_MASK 0x30 933 #define SPC3_SID_TPGS_IMPLICIT 0x10 934 #define SPC3_SID_TPGS_EXPLICIT 0x20 935 #define SPC3_SID_ACC 0x40 936 #define SPC3_SID_SCCS 0x80 937 938 #define CAM_PRIORITY_NORMAL CAM_PRIORITY_NONE 939 #endif 940 941 /* Definitions for SCSI unmap translation to NVMe DSM command */ 942 943 /* UNMAP block descriptor structure */ 944 struct unmap_blk_desc { 945 uint64_t slba; 946 uint32_t nlb; 947 uint32_t resv; 948 }; 949 950 /* UNMAP command's data */ 951 struct unmap_parm_list { 952 uint16_t unmap_data_len; 953 uint16_t unmap_blk_desc_data_len; 954 uint32_t resv; 955 struct unmap_blk_desc desc[0]; 956 }; 957 958 /* SCSI ADDITIONAL SENSE Codes */ 959 #define FIXED_SENSE_DATA 0x70 960 #define SCSI_ASC_NO_SENSE 0x00 961 #define SCSI_ASC_PERIPHERAL_DEV_WRITE_FAULT 0x03 962 #define SCSI_ASC_LUN_NOT_READY 0x04 963 #define SCSI_ASC_WARNING 0x0B 964 #define SCSI_ASC_LOG_BLOCK_GUARD_CHECK_FAILED 0x10 965 #define SCSI_ASC_LOG_BLOCK_APPTAG_CHECK_FAILED 0x10 966 #define SCSI_ASC_LOG_BLOCK_REFTAG_CHECK_FAILED 0x10 967 #define SCSI_ASC_UNRECOVERED_READ_ERROR 0x11 968 #define SCSI_ASC_MISCOMPARE_DURING_VERIFY 0x1D 969 #define SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID 0x20 970 #define SCSI_ASC_ILLEGAL_COMMAND 0x20 971 #define SCSI_ASC_ILLEGAL_BLOCK 0x21 972 #define SCSI_ASC_INVALID_CDB 0x24 973 #define SCSI_ASC_INVALID_LUN 0x25 974 #define SCSI_ASC_INVALID_PARAMETER 0x26 975 #define SCSI_ASC_FORMAT_COMMAND_FAILED 0x31 976 #define SCSI_ASC_INTERNAL_TARGET_FAILURE 0x44 977 978 /* SCSI ADDITIONAL SENSE Code Qualifiers */ 979 #define SCSI_ASCQ_CAUSE_NOT_REPORTABLE 0x00 980 #define SCSI_ASCQ_FORMAT_COMMAND_FAILED 0x01 981 #define SCSI_ASCQ_LOG_BLOCK_GUARD_CHECK_FAILED 0x01 982 #define SCSI_ASCQ_LOG_BLOCK_APPTAG_CHECK_FAILED 0x02 983 #define SCSI_ASCQ_LOG_BLOCK_REFTAG_CHECK_FAILED 0x03 984 #define SCSI_ASCQ_FORMAT_IN_PROGRESS 0x04 985 #define SCSI_ASCQ_POWER_LOSS_EXPECTED 0x08 986 #define SCSI_ASCQ_INVALID_LUN_ID 0x09 987 988 #endif 989 990