1 /*- 2 * Copyright (c) 2009 Yahoo! Inc. 3 * Copyright (c) 2011-2015 LSI Corp. 4 * Copyright (c) 2013-2016 Avago Technologies 5 * Copyright 2000-2020 Broadcom Inc. 6 * All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD 30 */ 31 32 #ifndef _MPRVAR_H 33 #define _MPRVAR_H 34 35 #include <sys/lock.h> 36 #include <sys/mutex.h> 37 38 #define MPR_DRIVER_VERSION "23.00.00.00-fbsd" 39 40 #define MPR_DB_MAX_WAIT 2500 41 42 #define MPR_REQ_FRAMES 2048 43 #define MPR_PRI_REQ_FRAMES 128 44 #define MPR_EVT_REPLY_FRAMES 32 45 #define MPR_REPLY_FRAMES MPR_REQ_FRAMES 46 #define MPR_CHAIN_FRAMES 16384 47 #define MPR_MAXIO_PAGES (-1) 48 #define MPR_SENSE_LEN SSD_FULL_SIZE 49 #define MPR_MSI_MAX 1 50 #define MPR_MSIX_MAX 96 51 #define MPR_SGE64_SIZE 12 52 #define MPR_SGE32_SIZE 8 53 #define MPR_SGC_SIZE 8 54 #define MPR_DEFAULT_CHAIN_SEG_SIZE 8 55 #define MPR_MAX_CHAIN_ELEMENT_SIZE 16 56 57 /* 58 * PCIe NVMe Specific defines 59 */ 60 //SLM-for now just use the same value as a SAS disk 61 #define NVME_QDEPTH MPR_REQ_FRAMES 62 #define PRP_ENTRY_SIZE 8 63 #define NVME_CMD_PRP1_OFFSET 24 /* PRP1 offset in NVMe cmd */ 64 #define NVME_CMD_PRP2_OFFSET 32 /* PRP2 offset in NVMe cmd */ 65 #define NVME_ERROR_RESPONSE_SIZE 16 /* Max NVME Error Response */ 66 #define HOST_PAGE_SIZE_4K 12 67 68 #define MPR_FUNCTRACE(sc) \ 69 mpr_dprint((sc), MPR_TRACE, "%s\n", __func__) 70 71 #define CAN_SLEEP 1 72 #define NO_SLEEP 0 73 74 #define MPR_PERIODIC_DELAY 1 /* 1 second heartbeat/watchdog check */ 75 #define MPR_ATA_ID_TIMEOUT 5 /* 5 second timeout for SATA ID cmd */ 76 #define MPR_MISSING_CHECK_DELAY 10 /* 10 seconds between missing check */ 77 78 #define IFAULT_IOP_OVER_TEMP_THRESHOLD_EXCEEDED 0x2810 79 80 #define MPR_SCSI_RI_INVALID_FRAME (0x00000002) 81 82 #define DEFAULT_SPINUP_WAIT 3 /* seconds to wait for spinup */ 83 84 #include <sys/endian.h> 85 86 /* 87 * host mapping related macro definitions 88 */ 89 #define MPR_MAPTABLE_BAD_IDX 0xFFFFFFFF 90 #define MPR_DPM_BAD_IDX 0xFFFF 91 #define MPR_ENCTABLE_BAD_IDX 0xFF 92 #define MPR_MAX_MISSING_COUNT 0x0F 93 #define MPR_DEV_RESERVED 0x20000000 94 #define MPR_MAP_IN_USE 0x10000000 95 #define MPR_MAP_BAD_ID 0xFFFFFFFF 96 97 typedef uint8_t u8; 98 typedef uint16_t u16; 99 typedef uint32_t u32; 100 typedef uint64_t u64; 101 102 typedef struct _MPI2_CONFIG_PAGE_MAN_11 103 { 104 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 105 U8 FlashTime; /* 0x04 */ 106 U8 NVTime; /* 0x05 */ 107 U16 Flag; /* 0x06 */ 108 U8 RFIoTimeout; /* 0x08 */ 109 U8 EEDPTagMode; /* 0x09 */ 110 U8 AWTValue; /* 0x0A */ 111 U8 Reserve1; /* 0x0B */ 112 U8 MaxCmdFrames; /* 0x0C */ 113 U8 Reserve2; /* 0x0D */ 114 U16 AddlFlags; /* 0x0E */ 115 U32 SysRefClk; /* 0x10 */ 116 U64 Reserve3[3]; /* 0x14 */ 117 U16 AddlFlags2; /* 0x2C */ 118 U8 AddlFlags3; /* 0x2E */ 119 U8 Reserve4; /* 0x2F */ 120 U64 opDebugEnable; /* 0x30 */ 121 U64 PlDebugEnable; /* 0x38 */ 122 U64 IrDebugEnable; /* 0x40 */ 123 U32 BoardPowerRequirement; /* 0x48 */ 124 U8 NVMeAbortTO; /* 0x4C */ 125 U8 Reserve5; /* 0x4D */ 126 U16 Reserve6; /* 0x4E */ 127 U32 Reserve7[3]; /* 0x50 */ 128 } MPI2_CONFIG_PAGE_MAN_11, 129 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_11, 130 Mpi2ManufacturingPage11_t, MPI2_POINTER pMpi2ManufacturingPage11_t; 131 132 #define MPI2_MAN_PG11_ADDLFLAGS2_CUSTOM_TM_HANDLING_MASK (0x0010) 133 134 /** 135 * struct dev_mapping_table - device mapping information 136 * @physical_id: SAS address for drives or WWID for RAID volumes 137 * @device_info: bitfield provides detailed info about the device 138 * @phy_bits: bitfields indicating controller phys 139 * @dpm_entry_num: index of this device in device persistent map table 140 * @dev_handle: device handle for the device pointed by this entry 141 * @id: target id 142 * @missing_count: number of times the device not detected by driver 143 * @hide_flag: Hide this physical disk/not (foreign configuration) 144 * @init_complete: Whether the start of the day checks completed or not 145 * @TLR_bits: Turn TLR support on or off 146 */ 147 struct dev_mapping_table { 148 u64 physical_id; 149 u32 device_info; 150 u32 phy_bits; 151 u16 dpm_entry_num; 152 u16 dev_handle; 153 u16 reserved1; 154 u16 id; 155 u8 missing_count; 156 u8 init_complete; 157 u8 TLR_bits; 158 u8 reserved2; 159 }; 160 161 /** 162 * struct enc_mapping_table - mapping information about an enclosure 163 * @enclosure_id: Logical ID of this enclosure 164 * @start_index: index to the entry in dev_mapping_table 165 * @phy_bits: bitfields indicating controller phys 166 * @dpm_entry_num: index of this enclosure in device persistent map table 167 * @enc_handle: device handle for the enclosure pointed by this entry 168 * @num_slots: number of slots in the enclosure 169 * @start_slot: Starting slot id 170 * @missing_count: number of times the device not detected by driver 171 * @removal_flag: used to mark the device for removal 172 * @skip_search: used as a flag to include/exclude enclosure for search 173 * @init_complete: Whether the start of the day checks completed or not 174 */ 175 struct enc_mapping_table { 176 u64 enclosure_id; 177 u32 start_index; 178 u32 phy_bits; 179 u16 dpm_entry_num; 180 u16 enc_handle; 181 u16 num_slots; 182 u16 start_slot; 183 u8 missing_count; 184 u8 removal_flag; 185 u8 skip_search; 186 u8 init_complete; 187 }; 188 189 /** 190 * struct map_removal_table - entries to be removed from mapping table 191 * @dpm_entry_num: index of this device in device persistent map table 192 * @dev_handle: device handle for the device pointed by this entry 193 */ 194 struct map_removal_table{ 195 u16 dpm_entry_num; 196 u16 dev_handle; 197 }; 198 199 typedef struct mpr_fw_diagnostic_buffer { 200 size_t size; 201 uint8_t extended_type; 202 uint8_t buffer_type; 203 uint8_t force_release; 204 uint32_t product_specific[23]; 205 uint8_t immediate; 206 uint8_t enabled; 207 uint8_t valid_data; 208 uint8_t owned_by_firmware; 209 uint32_t unique_id; 210 } mpr_fw_diagnostic_buffer_t; 211 212 struct mpr_softc; 213 struct mpr_command; 214 struct mprsas_softc; 215 union ccb; 216 struct mprsas_target; 217 struct mpr_column_map; 218 219 MALLOC_DECLARE(M_MPR); 220 221 typedef void mpr_evt_callback_t(struct mpr_softc *, uintptr_t, 222 MPI2_EVENT_NOTIFICATION_REPLY *reply); 223 typedef void mpr_command_callback_t(struct mpr_softc *, struct mpr_command *cm); 224 225 struct mpr_chain { 226 TAILQ_ENTRY(mpr_chain) chain_link; 227 void *chain; 228 uint64_t chain_busaddr; 229 }; 230 231 struct mpr_prp_page { 232 TAILQ_ENTRY(mpr_prp_page) prp_page_link; 233 uint64_t *prp_page; 234 uint64_t prp_page_busaddr; 235 }; 236 237 /* 238 * This needs to be at least 2 to support SMP passthrough. 239 */ 240 #define MPR_IOVEC_COUNT 2 241 242 struct mpr_command { 243 TAILQ_ENTRY(mpr_command) cm_link; 244 TAILQ_ENTRY(mpr_command) cm_recovery; 245 struct mpr_softc *cm_sc; 246 union ccb *cm_ccb; 247 void *cm_data; 248 u_int cm_length; 249 u_int cm_out_len; 250 struct uio cm_uio; 251 struct iovec cm_iovec[MPR_IOVEC_COUNT]; 252 u_int cm_max_segs; 253 u_int cm_sglsize; 254 void *cm_sge; 255 uint8_t *cm_req; 256 uint8_t *cm_reply; 257 uint32_t cm_reply_data; 258 mpr_command_callback_t *cm_complete; 259 void *cm_complete_data; 260 struct mprsas_target *cm_targ; 261 MPI2_REQUEST_DESCRIPTOR_UNION cm_desc; 262 u_int cm_lun; 263 u_int cm_flags; 264 #define MPR_CM_FLAGS_POLLED (1 << 0) 265 #define MPR_CM_FLAGS_COMPLETE (1 << 1) 266 #define MPR_CM_FLAGS_SGE_SIMPLE (1 << 2) 267 #define MPR_CM_FLAGS_DATAOUT (1 << 3) 268 #define MPR_CM_FLAGS_DATAIN (1 << 4) 269 #define MPR_CM_FLAGS_WAKEUP (1 << 5) 270 #define MPR_CM_FLAGS_USE_UIO (1 << 6) 271 #define MPR_CM_FLAGS_SMP_PASS (1 << 7) 272 #define MPR_CM_FLAGS_CHAIN_FAILED (1 << 8) 273 #define MPR_CM_FLAGS_ERROR_MASK MPR_CM_FLAGS_CHAIN_FAILED 274 #define MPR_CM_FLAGS_USE_CCB (1 << 9) 275 #define MPR_CM_FLAGS_SATA_ID_TIMEOUT (1 << 10) 276 #define MPR_CM_FLAGS_ON_RECOVERY (1 << 12) 277 #define MPR_CM_FLAGS_TIMEDOUT (1 << 13) 278 u_int cm_state; 279 #define MPR_CM_STATE_FREE 0 280 #define MPR_CM_STATE_BUSY 1 281 #define MPR_CM_STATE_INQUEUE 2 282 bus_dmamap_t cm_dmamap; 283 struct scsi_sense_data *cm_sense; 284 uint64_t *nvme_error_response; 285 TAILQ_HEAD(, mpr_chain) cm_chain_list; 286 TAILQ_HEAD(, mpr_prp_page) cm_prp_page_list; 287 uint32_t cm_req_busaddr; 288 bus_addr_t cm_sense_busaddr; 289 struct callout cm_callout; 290 mpr_command_callback_t *cm_timeout_handler; 291 }; 292 293 struct mpr_column_map { 294 uint16_t dev_handle; 295 uint8_t phys_disk_num; 296 }; 297 298 struct mpr_event_handle { 299 TAILQ_ENTRY(mpr_event_handle) eh_list; 300 mpr_evt_callback_t *callback; 301 void *data; 302 uint8_t mask[16]; 303 }; 304 305 struct mpr_busdma_context { 306 int completed; 307 int abandoned; 308 int error; 309 bus_addr_t *addr; 310 struct mpr_softc *softc; 311 bus_dmamap_t buffer_dmamap; 312 bus_dma_tag_t buffer_dmat; 313 }; 314 315 struct mpr_queue { 316 struct mpr_softc *sc; 317 int qnum; 318 MPI2_REPLY_DESCRIPTORS_UNION *post_queue; 319 int replypostindex; 320 #ifdef notyet 321 ck_ring_buffer_t *ringmem; 322 ck_ring_buffer_t *chainmem; 323 ck_ring_t req_ring; 324 ck_ring_t chain_ring; 325 #endif 326 bus_dma_tag_t buffer_dmat; 327 int io_cmds_highwater; 328 int chain_free_lowwater; 329 int chain_alloc_fail; 330 struct resource *irq; 331 void *intrhand; 332 int irq_rid; 333 }; 334 335 struct mpr_softc { 336 device_t mpr_dev; 337 struct cdev *mpr_cdev; 338 u_int mpr_flags; 339 #define MPR_FLAGS_INTX (1 << 0) 340 #define MPR_FLAGS_MSI (1 << 1) 341 #define MPR_FLAGS_BUSY (1 << 2) 342 #define MPR_FLAGS_SHUTDOWN (1 << 3) 343 #define MPR_FLAGS_DIAGRESET (1 << 4) 344 #define MPR_FLAGS_ATTACH_DONE (1 << 5) 345 #define MPR_FLAGS_GEN35_IOC (1 << 6) 346 #define MPR_FLAGS_REALLOCATED (1 << 7) 347 #define MPR_FLAGS_SEA_IOC (1 << 8) 348 u_int mpr_debug; 349 int msi_msgs; 350 u_int reqframesz; 351 u_int replyframesz; 352 u_int atomic_desc_capable; 353 int tm_cmds_active; 354 int io_cmds_active; 355 int io_cmds_highwater; 356 int chain_free; 357 int max_chains; 358 int max_io_pages; 359 u_int maxio; 360 int chain_free_lowwater; 361 uint32_t chain_frame_size; 362 int prp_buffer_size; 363 int prp_pages_free; 364 int prp_pages_free_lowwater; 365 u_int enable_ssu; 366 int spinup_wait_time; 367 int use_phynum; 368 int dump_reqs_alltypes; 369 uint64_t chain_alloc_fail; 370 uint64_t prp_page_alloc_fail; 371 struct sysctl_ctx_list sysctl_ctx; 372 struct sysctl_oid *sysctl_tree; 373 char fw_version[16]; 374 char msg_version[8]; 375 struct mpr_command *commands; 376 struct mpr_chain *chains; 377 struct mpr_prp_page *prps; 378 struct callout periodic; 379 struct callout device_check_callout; 380 struct mpr_queue *queues; 381 382 struct mprsas_softc *sassc; 383 TAILQ_HEAD(, mpr_command) req_list; 384 TAILQ_HEAD(, mpr_command) high_priority_req_list; 385 TAILQ_HEAD(, mpr_chain) chain_list; 386 TAILQ_HEAD(, mpr_prp_page) prp_page_list; 387 TAILQ_HEAD(, mpr_command) tm_list; 388 int replypostindex; 389 int replyfreeindex; 390 391 struct resource *mpr_regs_resource; 392 bus_space_handle_t mpr_bhandle; 393 bus_space_tag_t mpr_btag; 394 int mpr_regs_rid; 395 396 bus_dma_tag_t mpr_parent_dmat; 397 bus_dma_tag_t buffer_dmat; 398 399 MPI2_IOC_FACTS_REPLY *facts; 400 int num_reqs; 401 int num_prireqs; 402 int num_replies; 403 int num_chains; 404 int fqdepth; /* Free queue */ 405 int pqdepth; /* Post queue */ 406 407 uint8_t event_mask[16]; 408 TAILQ_HEAD(, mpr_event_handle) event_list; 409 struct mpr_event_handle *mpr_log_eh; 410 411 struct mtx mpr_mtx; 412 struct intr_config_hook mpr_ich; 413 414 uint8_t *req_frames; 415 bus_addr_t req_busaddr; 416 bus_dma_tag_t req_dmat; 417 bus_dmamap_t req_map; 418 419 uint8_t *reply_frames; 420 bus_addr_t reply_busaddr; 421 bus_dma_tag_t reply_dmat; 422 bus_dmamap_t reply_map; 423 424 struct scsi_sense_data *sense_frames; 425 bus_addr_t sense_busaddr; 426 bus_dma_tag_t sense_dmat; 427 bus_dmamap_t sense_map; 428 429 uint8_t *chain_frames; 430 bus_dma_tag_t chain_dmat; 431 bus_dmamap_t chain_map; 432 433 uint8_t *prp_pages; 434 bus_addr_t prp_page_busaddr; 435 bus_dma_tag_t prp_page_dmat; 436 bus_dmamap_t prp_page_map; 437 438 MPI2_REPLY_DESCRIPTORS_UNION *post_queue; 439 bus_addr_t post_busaddr; 440 uint32_t *free_queue; 441 bus_addr_t free_busaddr; 442 bus_dma_tag_t queues_dmat; 443 bus_dmamap_t queues_map; 444 445 uint8_t *fw_diag_buffer; 446 bus_addr_t fw_diag_busaddr; 447 bus_dma_tag_t fw_diag_dmat; 448 bus_dmamap_t fw_diag_map; 449 450 uint8_t ir_firmware; 451 452 /* static config pages */ 453 Mpi2IOCPage8_t ioc_pg8; 454 Mpi2IOUnitPage8_t iounit_pg8; 455 456 /* host mapping support */ 457 struct dev_mapping_table *mapping_table; 458 struct enc_mapping_table *enclosure_table; 459 struct map_removal_table *removal_table; 460 uint8_t *dpm_entry_used; 461 uint8_t *dpm_flush_entry; 462 Mpi2DriverMappingPage0_t *dpm_pg0; 463 uint16_t max_devices; 464 uint16_t max_enclosures; 465 uint16_t max_expanders; 466 uint8_t max_volumes; 467 uint8_t num_enc_table_entries; 468 uint8_t num_rsvd_entries; 469 uint16_t max_dpm_entries; 470 uint8_t is_dpm_enable; 471 uint8_t track_mapping_events; 472 uint32_t pending_map_events; 473 474 /* FW diag Buffer List */ 475 mpr_fw_diagnostic_buffer_t 476 fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT]; 477 478 /* Event Recording IOCTL support */ 479 uint32_t events_to_record[4]; 480 mpr_event_entry_t recorded_events[MPR_EVENT_QUEUE_SIZE]; 481 uint8_t event_index; 482 uint32_t event_number; 483 484 /* EEDP and TLR support */ 485 uint8_t eedp_enabled; 486 uint8_t control_TLR; 487 488 /* Shutdown Event Handler */ 489 eventhandler_tag shutdown_eh; 490 491 /* To track topo events during reset */ 492 #define MPR_DIAG_RESET_TIMEOUT 300000 493 uint8_t wait_for_port_enable; 494 uint8_t port_enable_complete; 495 uint8_t msleep_fake_chan; 496 497 /* StartStopUnit command handling at shutdown */ 498 uint32_t SSU_refcount; 499 uint8_t SSU_started; 500 501 /* Configuration tunables */ 502 u_int disable_msix; 503 u_int disable_msi; 504 u_int max_msix; 505 u_int max_reqframes; 506 u_int max_prireqframes; 507 u_int max_replyframes; 508 u_int max_evtframes; 509 char exclude_ids[80]; 510 511 struct timeval lastfail; 512 uint8_t custom_nvme_tm_handling; 513 uint8_t nvme_abort_timeout; 514 }; 515 516 struct mpr_config_params { 517 MPI2_CONFIG_EXT_PAGE_HEADER_UNION hdr; 518 u_int action; 519 u_int page_address; /* Attributes, not a phys address */ 520 u_int status; 521 void *buffer; 522 u_int length; 523 int timeout; 524 void (*callback)(struct mpr_softc *, struct mpr_config_params *); 525 void *cbdata; 526 }; 527 528 struct scsi_read_capacity_eedp 529 { 530 uint8_t addr[8]; 531 uint8_t length[4]; 532 uint8_t protect; 533 }; 534 535 static __inline uint32_t 536 mpr_regread(struct mpr_softc *sc, uint32_t offset) 537 { 538 uint32_t ret_val, i = 0; 539 do { 540 ret_val = 541 bus_space_read_4(sc->mpr_btag, sc->mpr_bhandle, offset); 542 } while((sc->mpr_flags & MPR_FLAGS_SEA_IOC) && 543 (ret_val == 0) && (++i < 3)); 544 545 return ret_val; 546 } 547 548 static __inline void 549 mpr_regwrite(struct mpr_softc *sc, uint32_t offset, uint32_t val) 550 { 551 bus_space_write_4(sc->mpr_btag, sc->mpr_bhandle, offset, val); 552 } 553 554 /* free_queue must have Little Endian address 555 * TODO- cm_reply_data is unwanted. We can remove it. 556 * */ 557 static __inline void 558 mpr_free_reply(struct mpr_softc *sc, uint32_t busaddr) 559 { 560 if (++sc->replyfreeindex >= sc->fqdepth) 561 sc->replyfreeindex = 0; 562 sc->free_queue[sc->replyfreeindex] = htole32(busaddr); 563 mpr_regwrite(sc, MPI2_REPLY_FREE_HOST_INDEX_OFFSET, sc->replyfreeindex); 564 } 565 566 static __inline struct mpr_chain * 567 mpr_alloc_chain(struct mpr_softc *sc) 568 { 569 struct mpr_chain *chain; 570 571 if ((chain = TAILQ_FIRST(&sc->chain_list)) != NULL) { 572 TAILQ_REMOVE(&sc->chain_list, chain, chain_link); 573 sc->chain_free--; 574 if (sc->chain_free < sc->chain_free_lowwater) 575 sc->chain_free_lowwater = sc->chain_free; 576 } else 577 sc->chain_alloc_fail++; 578 return (chain); 579 } 580 581 static __inline void 582 mpr_free_chain(struct mpr_softc *sc, struct mpr_chain *chain) 583 { 584 #if 0 585 bzero(chain->chain, 128); 586 #endif 587 sc->chain_free++; 588 TAILQ_INSERT_TAIL(&sc->chain_list, chain, chain_link); 589 } 590 591 static __inline struct mpr_prp_page * 592 mpr_alloc_prp_page(struct mpr_softc *sc) 593 { 594 struct mpr_prp_page *prp_page; 595 596 if ((prp_page = TAILQ_FIRST(&sc->prp_page_list)) != NULL) { 597 TAILQ_REMOVE(&sc->prp_page_list, prp_page, prp_page_link); 598 sc->prp_pages_free--; 599 if (sc->prp_pages_free < sc->prp_pages_free_lowwater) 600 sc->prp_pages_free_lowwater = sc->prp_pages_free; 601 } else 602 sc->prp_page_alloc_fail++; 603 return (prp_page); 604 } 605 606 static __inline void 607 mpr_free_prp_page(struct mpr_softc *sc, struct mpr_prp_page *prp_page) 608 { 609 sc->prp_pages_free++; 610 TAILQ_INSERT_TAIL(&sc->prp_page_list, prp_page, prp_page_link); 611 } 612 613 static __inline void 614 mpr_free_command(struct mpr_softc *sc, struct mpr_command *cm) 615 { 616 struct mpr_chain *chain, *chain_temp; 617 struct mpr_prp_page *prp_page, *prp_page_temp; 618 619 KASSERT(cm->cm_state == MPR_CM_STATE_BUSY, 620 ("state not busy, state = %u\n", cm->cm_state)); 621 622 if (cm->cm_reply != NULL) 623 mpr_free_reply(sc, cm->cm_reply_data); 624 cm->cm_reply = NULL; 625 cm->cm_flags = 0; 626 cm->cm_complete = NULL; 627 cm->cm_complete_data = NULL; 628 cm->cm_ccb = NULL; 629 cm->cm_targ = NULL; 630 cm->cm_max_segs = 0; 631 cm->cm_lun = 0; 632 cm->cm_state = MPR_CM_STATE_FREE; 633 cm->cm_data = NULL; 634 cm->cm_length = 0; 635 cm->cm_out_len = 0; 636 cm->cm_sglsize = 0; 637 cm->cm_sge = NULL; 638 639 TAILQ_FOREACH_SAFE(chain, &cm->cm_chain_list, chain_link, chain_temp) { 640 TAILQ_REMOVE(&cm->cm_chain_list, chain, chain_link); 641 mpr_free_chain(sc, chain); 642 } 643 TAILQ_FOREACH_SAFE(prp_page, &cm->cm_prp_page_list, prp_page_link, 644 prp_page_temp) { 645 TAILQ_REMOVE(&cm->cm_prp_page_list, prp_page, prp_page_link); 646 mpr_free_prp_page(sc, prp_page); 647 } 648 TAILQ_INSERT_TAIL(&sc->req_list, cm, cm_link); 649 } 650 651 static __inline struct mpr_command * 652 mpr_alloc_command(struct mpr_softc *sc) 653 { 654 struct mpr_command *cm; 655 656 cm = TAILQ_FIRST(&sc->req_list); 657 if (cm == NULL) 658 return (NULL); 659 660 KASSERT(cm->cm_state == MPR_CM_STATE_FREE, 661 ("mpr: Allocating busy command, state = %u\n", cm->cm_state)); 662 663 TAILQ_REMOVE(&sc->req_list, cm, cm_link); 664 cm->cm_state = MPR_CM_STATE_BUSY; 665 cm->cm_timeout_handler = NULL; 666 return (cm); 667 } 668 669 void mprsas_prepare_remove_retry(struct mprsas_softc *sassc); 670 671 static __inline void 672 mpr_free_high_priority_command(struct mpr_softc *sc, struct mpr_command *cm) 673 { 674 struct mpr_chain *chain, *chain_temp; 675 676 KASSERT(cm->cm_state == MPR_CM_STATE_BUSY, 677 ("state not busy, state = %u\n", cm->cm_state)); 678 679 if (cm->cm_reply != NULL) 680 mpr_free_reply(sc, cm->cm_reply_data); 681 cm->cm_reply = NULL; 682 cm->cm_flags = 0; 683 cm->cm_complete = NULL; 684 cm->cm_complete_data = NULL; 685 cm->cm_ccb = NULL; 686 cm->cm_targ = NULL; 687 cm->cm_lun = 0; 688 cm->cm_state = MPR_CM_STATE_FREE; 689 TAILQ_FOREACH_SAFE(chain, &cm->cm_chain_list, chain_link, chain_temp) { 690 TAILQ_REMOVE(&cm->cm_chain_list, chain, chain_link); 691 mpr_free_chain(sc, chain); 692 } 693 TAILQ_INSERT_TAIL(&sc->high_priority_req_list, cm, cm_link); 694 695 if (sc->sassc) 696 mprsas_prepare_remove_retry(sc->sassc); 697 } 698 699 static __inline struct mpr_command * 700 mpr_alloc_high_priority_command(struct mpr_softc *sc) 701 { 702 struct mpr_command *cm; 703 704 cm = TAILQ_FIRST(&sc->high_priority_req_list); 705 if (cm == NULL) 706 return (NULL); 707 708 KASSERT(cm->cm_state == MPR_CM_STATE_FREE, 709 ("mpr: Allocating busy command, state = %u\n", cm->cm_state)); 710 711 TAILQ_REMOVE(&sc->high_priority_req_list, cm, cm_link); 712 cm->cm_state = MPR_CM_STATE_BUSY; 713 cm->cm_timeout_handler = NULL; 714 cm->cm_desc.HighPriority.RequestFlags = 715 MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY; 716 return (cm); 717 } 718 719 static __inline void 720 mpr_lock(struct mpr_softc *sc) 721 { 722 mtx_lock(&sc->mpr_mtx); 723 } 724 725 static __inline void 726 mpr_unlock(struct mpr_softc *sc) 727 { 728 mtx_unlock(&sc->mpr_mtx); 729 } 730 731 #define MPR_INFO (1 << 0) /* Basic info */ 732 #define MPR_FAULT (1 << 1) /* Hardware faults */ 733 #define MPR_EVENT (1 << 2) /* Event data from the controller */ 734 #define MPR_LOG (1 << 3) /* Log data from the controller */ 735 #define MPR_RECOVERY (1 << 4) /* Command error recovery tracing */ 736 #define MPR_ERROR (1 << 5) /* Parameter errors, programming bugs */ 737 #define MPR_INIT (1 << 6) /* Things related to system init */ 738 #define MPR_XINFO (1 << 7) /* More detailed/noisy info */ 739 #define MPR_USER (1 << 8) /* Trace user-generated commands */ 740 #define MPR_MAPPING (1 << 9) /* Trace device mappings */ 741 #define MPR_TRACE (1 << 10) /* Function-by-function trace */ 742 743 #define MPR_SSU_DISABLE_SSD_DISABLE_HDD 0 744 #define MPR_SSU_ENABLE_SSD_DISABLE_HDD 1 745 #define MPR_SSU_DISABLE_SSD_ENABLE_HDD 2 746 #define MPR_SSU_ENABLE_SSD_ENABLE_HDD 3 747 748 #define mpr_printf(sc, args...) \ 749 device_printf((sc)->mpr_dev, ##args) 750 751 #define mpr_print_field(sc, msg, args...) \ 752 printf("\t" msg, ##args) 753 754 #define mpr_vprintf(sc, args...) \ 755 do { \ 756 if (bootverbose) \ 757 mpr_printf(sc, ##args); \ 758 } while (0) 759 760 #define mpr_dprint(sc, level, msg, args...) \ 761 do { \ 762 if ((sc)->mpr_debug & (level)) \ 763 device_printf((sc)->mpr_dev, msg, ##args); \ 764 } while (0) 765 766 #define MPR_PRINTFIELD_START(sc, tag...) \ 767 mpr_printf((sc), ##tag); \ 768 mpr_print_field((sc), ":\n") 769 #define MPR_PRINTFIELD_END(sc, tag) \ 770 mpr_printf((sc), tag "\n") 771 #define MPR_PRINTFIELD(sc, facts, attr, fmt) \ 772 mpr_print_field((sc), #attr ": " #fmt "\n", (facts)->attr) 773 #define MPR_PRINTFIELD_16(sc, facts, attr, fmt) \ 774 mpr_print_field((sc), #attr ": " #fmt "\n", le16toh((facts)->attr)) 775 #define MPR_PRINTFIELD_32(sc, facts, attr, fmt) \ 776 mpr_print_field((sc), #attr ": " #fmt "\n", le32toh((facts)->attr)) 777 778 static __inline void 779 mpr_from_u64(uint64_t data, U64 *mpr) 780 { 781 (mpr)->High = htole32((uint32_t)((data) >> 32)); 782 (mpr)->Low = htole32((uint32_t)((data) & 0xffffffff)); 783 } 784 785 static __inline uint64_t 786 mpr_to_u64(U64 *data) 787 { 788 return (((uint64_t)le32toh(data->High) << 32) | le32toh(data->Low)); 789 } 790 791 static __inline void 792 mpr_mask_intr(struct mpr_softc *sc) 793 { 794 uint32_t mask; 795 796 mask = mpr_regread(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET); 797 mask |= MPI2_HIM_REPLY_INT_MASK; 798 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET, mask); 799 } 800 801 static __inline void 802 mpr_unmask_intr(struct mpr_softc *sc) 803 { 804 uint32_t mask; 805 806 mask = mpr_regread(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET); 807 mask &= ~MPI2_HIM_REPLY_INT_MASK; 808 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET, mask); 809 } 810 811 int mpr_pci_setup_interrupts(struct mpr_softc *sc); 812 void mpr_pci_free_interrupts(struct mpr_softc *sc); 813 int mpr_pci_restore(struct mpr_softc *sc); 814 815 void mpr_get_tunables(struct mpr_softc *sc); 816 int mpr_attach(struct mpr_softc *sc); 817 int mpr_free(struct mpr_softc *sc); 818 void mpr_intr(void *); 819 void mpr_intr_msi(void *); 820 void mpr_intr_locked(void *); 821 int mpr_register_events(struct mpr_softc *, uint8_t *, mpr_evt_callback_t *, 822 void *, struct mpr_event_handle **); 823 int mpr_restart(struct mpr_softc *); 824 int mpr_update_events(struct mpr_softc *, struct mpr_event_handle *, uint8_t *); 825 int mpr_deregister_events(struct mpr_softc *, struct mpr_event_handle *); 826 void mpr_build_nvme_prp(struct mpr_softc *sc, struct mpr_command *cm, 827 Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request, void *data, 828 uint32_t data_in_sz, uint32_t data_out_sz); 829 int mpr_push_sge(struct mpr_command *, MPI2_SGE_SIMPLE64 *, size_t, int); 830 int mpr_push_ieee_sge(struct mpr_command *, void *, int); 831 int mpr_add_dmaseg(struct mpr_command *, vm_paddr_t, size_t, u_int, int); 832 int mpr_attach_sas(struct mpr_softc *sc); 833 int mpr_detach_sas(struct mpr_softc *sc); 834 int mpr_read_config_page(struct mpr_softc *, struct mpr_config_params *); 835 int mpr_write_config_page(struct mpr_softc *, struct mpr_config_params *); 836 void mpr_memaddr_cb(void *, bus_dma_segment_t *, int , int ); 837 void mpr_memaddr_wait_cb(void *, bus_dma_segment_t *, int , int ); 838 void mpr_init_sge(struct mpr_command *cm, void *req, void *sge); 839 int mpr_attach_user(struct mpr_softc *); 840 void mpr_detach_user(struct mpr_softc *); 841 void mprsas_record_event(struct mpr_softc *sc, 842 MPI2_EVENT_NOTIFICATION_REPLY *event_reply); 843 844 int mpr_map_command(struct mpr_softc *sc, struct mpr_command *cm); 845 int mpr_wait_command(struct mpr_softc *sc, struct mpr_command **cm, int timeout, 846 int sleep_flag); 847 int mpr_request_polled(struct mpr_softc *sc, struct mpr_command **cm); 848 849 int mpr_config_get_bios_pg3(struct mpr_softc *sc, Mpi2ConfigReply_t 850 *mpi_reply, Mpi2BiosPage3_t *config_page); 851 int mpr_config_get_raid_volume_pg0(struct mpr_softc *sc, Mpi2ConfigReply_t 852 *mpi_reply, Mpi2RaidVolPage0_t *config_page, u32 page_address); 853 int mpr_config_get_ioc_pg8(struct mpr_softc *sc, Mpi2ConfigReply_t *, 854 Mpi2IOCPage8_t *); 855 int mpr_config_get_iounit_pg8(struct mpr_softc *sc, 856 Mpi2ConfigReply_t *mpi_reply, Mpi2IOUnitPage8_t *config_page); 857 int mpr_config_get_sas_device_pg0(struct mpr_softc *, Mpi2ConfigReply_t *, 858 Mpi2SasDevicePage0_t *, u32 , u16 ); 859 int mpr_config_get_pcie_device_pg0(struct mpr_softc *sc, Mpi2ConfigReply_t 860 *mpi_reply, Mpi26PCIeDevicePage0_t *config_page, u32 form, u16 handle); 861 int mpr_config_get_pcie_device_pg2(struct mpr_softc *sc, Mpi2ConfigReply_t 862 *mpi_reply, Mpi26PCIeDevicePage2_t *config_page, u32 form, u16 handle); 863 int mpr_config_get_dpm_pg0(struct mpr_softc *, Mpi2ConfigReply_t *, 864 Mpi2DriverMappingPage0_t *, u16 ); 865 int mpr_config_get_raid_volume_pg1(struct mpr_softc *sc, 866 Mpi2ConfigReply_t *mpi_reply, Mpi2RaidVolPage1_t *config_page, u32 form, 867 u16 handle); 868 int mpr_config_get_volume_wwid(struct mpr_softc *sc, u16 volume_handle, 869 u64 *wwid); 870 int mpr_config_get_raid_pd_pg0(struct mpr_softc *sc, 871 Mpi2ConfigReply_t *mpi_reply, Mpi2RaidPhysDiskPage0_t *config_page, 872 u32 page_address); 873 int mpr_config_get_man_pg11(struct mpr_softc *sc, Mpi2ConfigReply_t *mpi_reply, 874 Mpi2ManufacturingPage11_t *config_page); 875 void mprsas_ir_shutdown(struct mpr_softc *sc, int howto); 876 877 int mpr_reinit(struct mpr_softc *sc); 878 void mprsas_handle_reinit(struct mpr_softc *sc); 879 880 void mpr_base_static_config_pages(struct mpr_softc *sc); 881 882 int mpr_mapping_initialize(struct mpr_softc *); 883 void mpr_mapping_topology_change_event(struct mpr_softc *, 884 Mpi2EventDataSasTopologyChangeList_t *); 885 void mpr_mapping_pcie_topology_change_event(struct mpr_softc *sc, 886 Mpi26EventDataPCIeTopologyChangeList_t *event_data); 887 void mpr_mapping_free_memory(struct mpr_softc *sc); 888 int mpr_config_set_dpm_pg0(struct mpr_softc *, Mpi2ConfigReply_t *, 889 Mpi2DriverMappingPage0_t *, u16 ); 890 void mpr_mapping_exit(struct mpr_softc *); 891 void mpr_mapping_check_devices(void *); 892 int mpr_mapping_allocate_memory(struct mpr_softc *sc); 893 unsigned int mpr_mapping_get_tid(struct mpr_softc *, uint64_t , u16); 894 unsigned int mpr_mapping_get_tid_from_handle(struct mpr_softc *sc, 895 u16 handle); 896 unsigned int mpr_mapping_get_raid_tid(struct mpr_softc *sc, u64 wwid, 897 u16 volHandle); 898 unsigned int mpr_mapping_get_raid_tid_from_handle(struct mpr_softc *sc, 899 u16 volHandle); 900 void mpr_mapping_enclosure_dev_status_change_event(struct mpr_softc *, 901 Mpi2EventDataSasEnclDevStatusChange_t *event_data); 902 void mpr_mapping_ir_config_change_event(struct mpr_softc *sc, 903 Mpi2EventDataIrConfigChangeList_t *event_data); 904 905 void mprsas_evt_handler(struct mpr_softc *sc, uintptr_t data, 906 MPI2_EVENT_NOTIFICATION_REPLY *event); 907 void mprsas_prepare_remove(struct mprsas_softc *sassc, uint16_t handle); 908 void mprsas_prepare_volume_remove(struct mprsas_softc *sassc, uint16_t handle); 909 int mprsas_startup(struct mpr_softc *sc); 910 struct mprsas_target * mprsas_find_target_by_handle(struct mprsas_softc *, int, 911 uint16_t); 912 void mprsas_realloc_targets(struct mpr_softc *sc, int maxtargets); 913 struct mpr_command * mprsas_alloc_tm(struct mpr_softc *sc); 914 void mprsas_free_tm(struct mpr_softc *sc, struct mpr_command *tm); 915 void mprsas_release_simq_reinit(struct mprsas_softc *sassc); 916 int mprsas_send_reset(struct mpr_softc *sc, struct mpr_command *tm, 917 uint8_t type); 918 919 SYSCTL_DECL(_hw_mpr); 920 921 /* Compatibility shims for different OS versions */ 922 #if defined(CAM_PRIORITY_XPT) 923 #define MPR_PRIORITY_XPT CAM_PRIORITY_XPT 924 #else 925 #define MPR_PRIORITY_XPT 5 926 #endif 927 928 /* Definitions for SCSI unmap translation to NVMe DSM command */ 929 930 /* UNMAP block descriptor structure */ 931 struct unmap_blk_desc { 932 uint64_t slba; 933 uint32_t nlb; 934 uint32_t resv; 935 }; 936 937 /* UNMAP command's data */ 938 struct unmap_parm_list { 939 uint16_t unmap_data_len; 940 uint16_t unmap_blk_desc_data_len; 941 uint32_t resv; 942 struct unmap_blk_desc desc[0]; 943 }; 944 945 /* SCSI ADDITIONAL SENSE Codes */ 946 #define FIXED_SENSE_DATA 0x70 947 #define SCSI_ASC_NO_SENSE 0x00 948 #define SCSI_ASC_PERIPHERAL_DEV_WRITE_FAULT 0x03 949 #define SCSI_ASC_LUN_NOT_READY 0x04 950 #define SCSI_ASC_WARNING 0x0B 951 #define SCSI_ASC_LOG_BLOCK_GUARD_CHECK_FAILED 0x10 952 #define SCSI_ASC_LOG_BLOCK_APPTAG_CHECK_FAILED 0x10 953 #define SCSI_ASC_LOG_BLOCK_REFTAG_CHECK_FAILED 0x10 954 #define SCSI_ASC_UNRECOVERED_READ_ERROR 0x11 955 #define SCSI_ASC_MISCOMPARE_DURING_VERIFY 0x1D 956 #define SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID 0x20 957 #define SCSI_ASC_ILLEGAL_COMMAND 0x20 958 #define SCSI_ASC_ILLEGAL_BLOCK 0x21 959 #define SCSI_ASC_INVALID_CDB 0x24 960 #define SCSI_ASC_INVALID_LUN 0x25 961 #define SCSI_ASC_INVALID_PARAMETER 0x26 962 #define SCSI_ASC_FORMAT_COMMAND_FAILED 0x31 963 #define SCSI_ASC_INTERNAL_TARGET_FAILURE 0x44 964 965 /* SCSI ADDITIONAL SENSE Code Qualifiers */ 966 #define SCSI_ASCQ_CAUSE_NOT_REPORTABLE 0x00 967 #define SCSI_ASCQ_FORMAT_COMMAND_FAILED 0x01 968 #define SCSI_ASCQ_LOG_BLOCK_GUARD_CHECK_FAILED 0x01 969 #define SCSI_ASCQ_LOG_BLOCK_APPTAG_CHECK_FAILED 0x02 970 #define SCSI_ASCQ_LOG_BLOCK_REFTAG_CHECK_FAILED 0x03 971 #define SCSI_ASCQ_FORMAT_IN_PROGRESS 0x04 972 #define SCSI_ASCQ_POWER_LOSS_EXPECTED 0x08 973 #define SCSI_ASCQ_INVALID_LUN_ID 0x09 974 975 #endif 976