xref: /freebsd/sys/dev/mpr/mprvar.h (revision 86312e466c7f7d1fff90e9139e57bfd44e4906f3)
1991554f2SKenneth D. Merry /*-
2991554f2SKenneth D. Merry  * Copyright (c) 2009 Yahoo! Inc.
3a2c14879SStephen McConnell  * Copyright (c) 2011-2015 LSI Corp.
47a2a6a1aSStephen McConnell  * Copyright (c) 2013-2016 Avago Technologies
5991554f2SKenneth D. Merry  * All rights reserved.
6991554f2SKenneth D. Merry  *
7991554f2SKenneth D. Merry  * Redistribution and use in source and binary forms, with or without
8991554f2SKenneth D. Merry  * modification, are permitted provided that the following conditions
9991554f2SKenneth D. Merry  * are met:
10991554f2SKenneth D. Merry  * 1. Redistributions of source code must retain the above copyright
11991554f2SKenneth D. Merry  *    notice, this list of conditions and the following disclaimer.
12991554f2SKenneth D. Merry  * 2. Redistributions in binary form must reproduce the above copyright
13991554f2SKenneth D. Merry  *    notice, this list of conditions and the following disclaimer in the
14991554f2SKenneth D. Merry  *    documentation and/or other materials provided with the distribution.
15991554f2SKenneth D. Merry  *
16991554f2SKenneth D. Merry  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17991554f2SKenneth D. Merry  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18991554f2SKenneth D. Merry  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19991554f2SKenneth D. Merry  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20991554f2SKenneth D. Merry  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21991554f2SKenneth D. Merry  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22991554f2SKenneth D. Merry  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23991554f2SKenneth D. Merry  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24991554f2SKenneth D. Merry  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25991554f2SKenneth D. Merry  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26991554f2SKenneth D. Merry  * SUCH DAMAGE.
27991554f2SKenneth D. Merry  *
28a2c14879SStephen McConnell  * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD
29a2c14879SStephen McConnell  *
30991554f2SKenneth D. Merry  * $FreeBSD$
31991554f2SKenneth D. Merry  */
32991554f2SKenneth D. Merry 
33991554f2SKenneth D. Merry #ifndef _MPRVAR_H
34991554f2SKenneth D. Merry #define _MPRVAR_H
35991554f2SKenneth D. Merry 
365f5baf0eSAlexander Motin #define MPR_DRIVER_VERSION	"18.03.00.00-fbsd"
37991554f2SKenneth D. Merry 
38991554f2SKenneth D. Merry #define MPR_DB_MAX_WAIT		2500
39991554f2SKenneth D. Merry 
403c5ac992SScott Long #define MPR_REQ_FRAMES		2048
413c5ac992SScott Long #define MPR_PRI_REQ_FRAMES	128
42991554f2SKenneth D. Merry #define MPR_EVT_REPLY_FRAMES	32
43991554f2SKenneth D. Merry #define MPR_REPLY_FRAMES	MPR_REQ_FRAMES
44731308d0SAlexander Motin #define MPR_CHAIN_FRAMES	16384
4532b0a21eSStephen McConnell #define MPR_MAXIO_PAGES		(-1)
46991554f2SKenneth D. Merry #define MPR_SENSE_LEN		SSD_FULL_SIZE
473c5ac992SScott Long #define MPR_MSI_MAX		1
483c5ac992SScott Long #define MPR_MSIX_MAX		96
49991554f2SKenneth D. Merry #define MPR_SGE64_SIZE		12
50991554f2SKenneth D. Merry #define MPR_SGE32_SIZE		8
51991554f2SKenneth D. Merry #define MPR_SGC_SIZE		8
522bbc5fcbSStephen McConnell #define MPR_DEFAULT_CHAIN_SEG_SIZE	8
532bbc5fcbSStephen McConnell #define MPR_MAX_CHAIN_ELEMENT_SIZE	16
54991554f2SKenneth D. Merry 
5567feec50SStephen McConnell /*
5667feec50SStephen McConnell  * PCIe NVMe Specific defines
5767feec50SStephen McConnell  */
5867feec50SStephen McConnell //SLM-for now just use the same value as a SAS disk
5967feec50SStephen McConnell #define NVME_QDEPTH			MPR_REQ_FRAMES
6067feec50SStephen McConnell #define PRP_ENTRY_SIZE			8
6167feec50SStephen McConnell #define NVME_CMD_PRP1_OFFSET		24	/* PRP1 offset in NVMe cmd */
6267feec50SStephen McConnell #define NVME_CMD_PRP2_OFFSET		32	/* PRP2 offset in NVMe cmd */
6367feec50SStephen McConnell #define NVME_ERROR_RESPONSE_SIZE	16	/* Max NVME Error Response */
6467feec50SStephen McConnell #define HOST_PAGE_SIZE_4K		12
6567feec50SStephen McConnell 
66991554f2SKenneth D. Merry #define MPR_FUNCTRACE(sc)			\
67991554f2SKenneth D. Merry 	mpr_dprint((sc), MPR_TRACE, "%s\n", __func__)
68991554f2SKenneth D. Merry 
69991554f2SKenneth D. Merry #define	CAN_SLEEP			1
70991554f2SKenneth D. Merry #define	NO_SLEEP			0
71991554f2SKenneth D. Merry 
72991554f2SKenneth D. Merry #define MPR_PERIODIC_DELAY	1	/* 1 second heartbeat/watchdog check */
73a2c14879SStephen McConnell #define MPR_ATA_ID_TIMEOUT	5	/* 5 second timeout for SATA ID cmd */
74327f2e6cSStephen McConnell #define MPR_MISSING_CHECK_DELAY	10	/* 10 seconds between missing check */
75991554f2SKenneth D. Merry 
76991554f2SKenneth D. Merry #define	IFAULT_IOP_OVER_TEMP_THRESHOLD_EXCEEDED	0x2810
77991554f2SKenneth D. Merry 
78991554f2SKenneth D. Merry #define MPR_SCSI_RI_INVALID_FRAME	(0x00000002)
79991554f2SKenneth D. Merry 
80a2c14879SStephen McConnell #define DEFAULT_SPINUP_WAIT	3	/* seconds to wait for spinup */
81a2c14879SStephen McConnell 
82991554f2SKenneth D. Merry #include <sys/endian.h>
83991554f2SKenneth D. Merry 
84991554f2SKenneth D. Merry /*
85991554f2SKenneth D. Merry  * host mapping related macro definitions
86991554f2SKenneth D. Merry  */
87991554f2SKenneth D. Merry #define MPR_MAPTABLE_BAD_IDX	0xFFFFFFFF
88991554f2SKenneth D. Merry #define MPR_DPM_BAD_IDX		0xFFFF
89991554f2SKenneth D. Merry #define MPR_ENCTABLE_BAD_IDX	0xFF
90991554f2SKenneth D. Merry #define MPR_MAX_MISSING_COUNT	0x0F
91991554f2SKenneth D. Merry #define MPR_DEV_RESERVED	0x20000000
92991554f2SKenneth D. Merry #define MPR_MAP_IN_USE		0x10000000
93991554f2SKenneth D. Merry #define MPR_MAP_BAD_ID		0xFFFFFFFF
94991554f2SKenneth D. Merry 
95991554f2SKenneth D. Merry typedef uint8_t u8;
96991554f2SKenneth D. Merry typedef uint16_t u16;
97991554f2SKenneth D. Merry typedef uint32_t u32;
98991554f2SKenneth D. Merry typedef uint64_t u64;
99991554f2SKenneth D. Merry 
100991554f2SKenneth D. Merry /**
101991554f2SKenneth D. Merry  * struct dev_mapping_table - device mapping information
102991554f2SKenneth D. Merry  * @physical_id: SAS address for drives or WWID for RAID volumes
103991554f2SKenneth D. Merry  * @device_info: bitfield provides detailed info about the device
104991554f2SKenneth D. Merry  * @phy_bits: bitfields indicating controller phys
105991554f2SKenneth D. Merry  * @dpm_entry_num: index of this device in device persistent map table
106991554f2SKenneth D. Merry  * @dev_handle: device handle for the device pointed by this entry
107991554f2SKenneth D. Merry  * @id: target id
108991554f2SKenneth D. Merry  * @missing_count: number of times the device not detected by driver
109991554f2SKenneth D. Merry  * @hide_flag: Hide this physical disk/not (foreign configuration)
110991554f2SKenneth D. Merry  * @init_complete: Whether the start of the day checks completed or not
111991554f2SKenneth D. Merry  * @TLR_bits: Turn TLR support on or off
112991554f2SKenneth D. Merry  */
113991554f2SKenneth D. Merry struct dev_mapping_table {
114991554f2SKenneth D. Merry 	u64	physical_id;
115991554f2SKenneth D. Merry 	u32	device_info;
116991554f2SKenneth D. Merry 	u32	phy_bits;
117991554f2SKenneth D. Merry 	u16	dpm_entry_num;
118991554f2SKenneth D. Merry 	u16	dev_handle;
119327f2e6cSStephen McConnell 	u16	reserved1;
120991554f2SKenneth D. Merry 	u16	id;
121991554f2SKenneth D. Merry 	u8	missing_count;
122991554f2SKenneth D. Merry 	u8	init_complete;
123991554f2SKenneth D. Merry 	u8	TLR_bits;
124991554f2SKenneth D. Merry 	u8	reserved2;
125991554f2SKenneth D. Merry };
126991554f2SKenneth D. Merry 
127991554f2SKenneth D. Merry /**
128991554f2SKenneth D. Merry  * struct enc_mapping_table -  mapping information about an enclosure
129991554f2SKenneth D. Merry  * @enclosure_id: Logical ID of this enclosure
130991554f2SKenneth D. Merry  * @start_index: index to the entry in dev_mapping_table
131991554f2SKenneth D. Merry  * @phy_bits: bitfields indicating controller phys
132991554f2SKenneth D. Merry  * @dpm_entry_num: index of this enclosure in device persistent map table
133991554f2SKenneth D. Merry  * @enc_handle: device handle for the enclosure pointed by this entry
134991554f2SKenneth D. Merry  * @num_slots: number of slots in the enclosure
135991554f2SKenneth D. Merry  * @start_slot: Starting slot id
136991554f2SKenneth D. Merry  * @missing_count: number of times the device not detected by driver
137991554f2SKenneth D. Merry  * @removal_flag: used to mark the device for removal
138991554f2SKenneth D. Merry  * @skip_search: used as a flag to include/exclude enclosure for search
139991554f2SKenneth D. Merry  * @init_complete: Whether the start of the day checks completed or not
140991554f2SKenneth D. Merry  */
141991554f2SKenneth D. Merry struct enc_mapping_table {
142991554f2SKenneth D. Merry 	u64	enclosure_id;
143991554f2SKenneth D. Merry 	u32	start_index;
144991554f2SKenneth D. Merry 	u32	phy_bits;
145991554f2SKenneth D. Merry 	u16	dpm_entry_num;
146991554f2SKenneth D. Merry 	u16	enc_handle;
147991554f2SKenneth D. Merry 	u16	num_slots;
148991554f2SKenneth D. Merry 	u16	start_slot;
149991554f2SKenneth D. Merry 	u8	missing_count;
150991554f2SKenneth D. Merry 	u8	removal_flag;
151991554f2SKenneth D. Merry 	u8	skip_search;
152991554f2SKenneth D. Merry 	u8	init_complete;
153991554f2SKenneth D. Merry };
154991554f2SKenneth D. Merry 
155991554f2SKenneth D. Merry /**
156991554f2SKenneth D. Merry  * struct map_removal_table - entries to be removed from mapping table
157991554f2SKenneth D. Merry  * @dpm_entry_num: index of this device in device persistent map table
158991554f2SKenneth D. Merry  * @dev_handle: device handle for the device pointed by this entry
159991554f2SKenneth D. Merry  */
160991554f2SKenneth D. Merry struct map_removal_table{
161991554f2SKenneth D. Merry 	u16	dpm_entry_num;
162991554f2SKenneth D. Merry 	u16	dev_handle;
163991554f2SKenneth D. Merry };
164991554f2SKenneth D. Merry 
165991554f2SKenneth D. Merry typedef struct mpr_fw_diagnostic_buffer {
166991554f2SKenneth D. Merry 	size_t		size;
167991554f2SKenneth D. Merry 	uint8_t		extended_type;
168991554f2SKenneth D. Merry 	uint8_t		buffer_type;
169991554f2SKenneth D. Merry 	uint8_t		force_release;
170991554f2SKenneth D. Merry 	uint32_t	product_specific[23];
171991554f2SKenneth D. Merry 	uint8_t		immediate;
172991554f2SKenneth D. Merry 	uint8_t		enabled;
173991554f2SKenneth D. Merry 	uint8_t		valid_data;
174991554f2SKenneth D. Merry 	uint8_t		owned_by_firmware;
175991554f2SKenneth D. Merry 	uint32_t	unique_id;
176991554f2SKenneth D. Merry } mpr_fw_diagnostic_buffer_t;
177991554f2SKenneth D. Merry 
178991554f2SKenneth D. Merry struct mpr_softc;
179991554f2SKenneth D. Merry struct mpr_command;
180991554f2SKenneth D. Merry struct mprsas_softc;
181991554f2SKenneth D. Merry union ccb;
182991554f2SKenneth D. Merry struct mprsas_target;
183991554f2SKenneth D. Merry struct mpr_column_map;
184991554f2SKenneth D. Merry 
185991554f2SKenneth D. Merry MALLOC_DECLARE(M_MPR);
186991554f2SKenneth D. Merry 
187991554f2SKenneth D. Merry typedef void mpr_evt_callback_t(struct mpr_softc *, uintptr_t,
188991554f2SKenneth D. Merry     MPI2_EVENT_NOTIFICATION_REPLY *reply);
189991554f2SKenneth D. Merry typedef void mpr_command_callback_t(struct mpr_softc *, struct mpr_command *cm);
190991554f2SKenneth D. Merry 
191991554f2SKenneth D. Merry struct mpr_chain {
192991554f2SKenneth D. Merry 	TAILQ_ENTRY(mpr_chain)		chain_link;
193991554f2SKenneth D. Merry 	void				*chain;
194991554f2SKenneth D. Merry 	uint64_t			chain_busaddr;
195991554f2SKenneth D. Merry };
196991554f2SKenneth D. Merry 
19767feec50SStephen McConnell struct mpr_prp_page {
19867feec50SStephen McConnell 	TAILQ_ENTRY(mpr_prp_page)	prp_page_link;
19967feec50SStephen McConnell 	uint64_t			*prp_page;
20067feec50SStephen McConnell 	uint64_t			prp_page_busaddr;
20167feec50SStephen McConnell };
20267feec50SStephen McConnell 
203991554f2SKenneth D. Merry /*
204991554f2SKenneth D. Merry  * This needs to be at least 2 to support SMP passthrough.
205991554f2SKenneth D. Merry  */
206991554f2SKenneth D. Merry #define       MPR_IOVEC_COUNT 2
207991554f2SKenneth D. Merry 
208991554f2SKenneth D. Merry struct mpr_command {
209991554f2SKenneth D. Merry 	TAILQ_ENTRY(mpr_command)	cm_link;
210991554f2SKenneth D. Merry 	TAILQ_ENTRY(mpr_command)	cm_recovery;
211991554f2SKenneth D. Merry 	struct mpr_softc		*cm_sc;
212991554f2SKenneth D. Merry 	union ccb			*cm_ccb;
213991554f2SKenneth D. Merry 	void				*cm_data;
214991554f2SKenneth D. Merry 	u_int				cm_length;
215991554f2SKenneth D. Merry 	u_int				cm_out_len;
216991554f2SKenneth D. Merry 	struct uio			cm_uio;
217991554f2SKenneth D. Merry 	struct iovec			cm_iovec[MPR_IOVEC_COUNT];
218991554f2SKenneth D. Merry 	u_int				cm_max_segs;
219991554f2SKenneth D. Merry 	u_int				cm_sglsize;
220991554f2SKenneth D. Merry 	void				*cm_sge;
221991554f2SKenneth D. Merry 	uint8_t				*cm_req;
222991554f2SKenneth D. Merry 	uint8_t				*cm_reply;
223991554f2SKenneth D. Merry 	uint32_t			cm_reply_data;
224991554f2SKenneth D. Merry 	mpr_command_callback_t		*cm_complete;
225991554f2SKenneth D. Merry 	void				*cm_complete_data;
226991554f2SKenneth D. Merry 	struct mprsas_target		*cm_targ;
227991554f2SKenneth D. Merry 	MPI2_REQUEST_DESCRIPTOR_UNION	cm_desc;
228991554f2SKenneth D. Merry 	u_int	                	cm_lun;
229991554f2SKenneth D. Merry 	u_int				cm_flags;
230991554f2SKenneth D. Merry #define MPR_CM_FLAGS_POLLED		(1 << 0)
231991554f2SKenneth D. Merry #define MPR_CM_FLAGS_COMPLETE		(1 << 1)
232991554f2SKenneth D. Merry #define MPR_CM_FLAGS_SGE_SIMPLE		(1 << 2)
233991554f2SKenneth D. Merry #define MPR_CM_FLAGS_DATAOUT		(1 << 3)
234991554f2SKenneth D. Merry #define MPR_CM_FLAGS_DATAIN		(1 << 4)
235991554f2SKenneth D. Merry #define MPR_CM_FLAGS_WAKEUP		(1 << 5)
236991554f2SKenneth D. Merry #define MPR_CM_FLAGS_USE_UIO		(1 << 6)
237991554f2SKenneth D. Merry #define MPR_CM_FLAGS_SMP_PASS		(1 << 7)
238991554f2SKenneth D. Merry #define	MPR_CM_FLAGS_CHAIN_FAILED	(1 << 8)
239991554f2SKenneth D. Merry #define	MPR_CM_FLAGS_ERROR_MASK		MPR_CM_FLAGS_CHAIN_FAILED
240991554f2SKenneth D. Merry #define	MPR_CM_FLAGS_USE_CCB		(1 << 9)
241a2c14879SStephen McConnell #define	MPR_CM_FLAGS_SATA_ID_TIMEOUT	(1 << 10)
242991554f2SKenneth D. Merry 	u_int				cm_state;
243991554f2SKenneth D. Merry #define MPR_CM_STATE_FREE		0
244991554f2SKenneth D. Merry #define MPR_CM_STATE_BUSY		1
245991554f2SKenneth D. Merry #define MPR_CM_STATE_TIMEDOUT		2
246f0779b04SScott Long #define MPR_CM_STATE_INQUEUE		3
247991554f2SKenneth D. Merry 	bus_dmamap_t			cm_dmamap;
248991554f2SKenneth D. Merry 	struct scsi_sense_data		*cm_sense;
24967feec50SStephen McConnell 	uint64_t			*nvme_error_response;
250991554f2SKenneth D. Merry 	TAILQ_HEAD(, mpr_chain)		cm_chain_list;
25167feec50SStephen McConnell  	TAILQ_HEAD(, mpr_prp_page)	cm_prp_page_list;
252991554f2SKenneth D. Merry 	uint32_t			cm_req_busaddr;
25367feec50SStephen McConnell 	bus_addr_t			cm_sense_busaddr;
254991554f2SKenneth D. Merry 	struct callout			cm_callout;
255*86312e46SConrad Meyer 	mpr_command_callback_t		*cm_timeout_handler;
256991554f2SKenneth D. Merry };
257991554f2SKenneth D. Merry 
258991554f2SKenneth D. Merry struct mpr_column_map {
259991554f2SKenneth D. Merry 	uint16_t			dev_handle;
260991554f2SKenneth D. Merry 	uint8_t				phys_disk_num;
261991554f2SKenneth D. Merry };
262991554f2SKenneth D. Merry 
263991554f2SKenneth D. Merry struct mpr_event_handle {
264991554f2SKenneth D. Merry 	TAILQ_ENTRY(mpr_event_handle)	eh_list;
265991554f2SKenneth D. Merry 	mpr_evt_callback_t		*callback;
266991554f2SKenneth D. Merry 	void				*data;
267991554f2SKenneth D. Merry 	uint8_t				mask[16];
268991554f2SKenneth D. Merry };
269991554f2SKenneth D. Merry 
270e2997a03SKenneth D. Merry struct mpr_busdma_context {
271e2997a03SKenneth D. Merry 	int				completed;
272e2997a03SKenneth D. Merry 	int				abandoned;
273e2997a03SKenneth D. Merry 	int				error;
274e2997a03SKenneth D. Merry 	bus_addr_t			*addr;
275e2997a03SKenneth D. Merry 	struct mpr_softc		*softc;
276e2997a03SKenneth D. Merry 	bus_dmamap_t			buffer_dmamap;
277e2997a03SKenneth D. Merry 	bus_dma_tag_t			buffer_dmat;
278e2997a03SKenneth D. Merry };
279e2997a03SKenneth D. Merry 
280bec09074SScott Long struct mpr_queue {
281bec09074SScott Long 	struct mpr_softc		*sc;
282bec09074SScott Long 	int				qnum;
283bec09074SScott Long 	MPI2_REPLY_DESCRIPTORS_UNION	*post_queue;
284bec09074SScott Long 	int				replypostindex;
285bec09074SScott Long #ifdef notyet
286bec09074SScott Long 	ck_ring_buffer_t		*ringmem;
287bec09074SScott Long 	ck_ring_buffer_t		*chainmem;
288bec09074SScott Long 	ck_ring_t			req_ring;
289bec09074SScott Long 	ck_ring_t			chain_ring;
290bec09074SScott Long #endif
291bec09074SScott Long 	bus_dma_tag_t			buffer_dmat;
292bec09074SScott Long 	int				io_cmds_highwater;
293bec09074SScott Long 	int				chain_free_lowwater;
294bec09074SScott Long 	int				chain_alloc_fail;
295bec09074SScott Long 	struct resource			*irq;
296bec09074SScott Long 	void				*intrhand;
297bec09074SScott Long 	int				irq_rid;
298bec09074SScott Long };
299bec09074SScott Long 
300991554f2SKenneth D. Merry struct mpr_softc {
301991554f2SKenneth D. Merry 	device_t			mpr_dev;
302991554f2SKenneth D. Merry 	struct cdev			*mpr_cdev;
303991554f2SKenneth D. Merry 	u_int				mpr_flags;
304991554f2SKenneth D. Merry #define MPR_FLAGS_INTX		(1 << 0)
305991554f2SKenneth D. Merry #define MPR_FLAGS_MSI		(1 << 1)
306991554f2SKenneth D. Merry #define MPR_FLAGS_BUSY		(1 << 2)
307991554f2SKenneth D. Merry #define MPR_FLAGS_SHUTDOWN	(1 << 3)
308991554f2SKenneth D. Merry #define MPR_FLAGS_DIAGRESET	(1 << 4)
309991554f2SKenneth D. Merry #define	MPR_FLAGS_ATTACH_DONE	(1 << 5)
31067feec50SStephen McConnell #define	MPR_FLAGS_GEN35_IOC	(1 << 6)
3116d4ffcb4SKenneth D. Merry #define	MPR_FLAGS_REALLOCATED	(1 << 7)
312991554f2SKenneth D. Merry 	u_int				mpr_debug;
313252b2b4fSScott Long 	int				msi_msgs;
31496410703SScott Long 	u_int				reqframesz;
31596410703SScott Long 	u_int				replyframesz;
31667feec50SStephen McConnell 	u_int				atomic_desc_capable;
317991554f2SKenneth D. Merry 	int				tm_cmds_active;
318991554f2SKenneth D. Merry 	int				io_cmds_active;
319991554f2SKenneth D. Merry 	int				io_cmds_highwater;
320991554f2SKenneth D. Merry 	int				chain_free;
321991554f2SKenneth D. Merry 	int				max_chains;
32232b0a21eSStephen McConnell 	int				max_io_pages;
32367feec50SStephen McConnell 	u_int				maxio;
324991554f2SKenneth D. Merry 	int				chain_free_lowwater;
3252bbc5fcbSStephen McConnell 	uint32_t			chain_frame_size;
32667feec50SStephen McConnell 	int				prp_buffer_size;
32767feec50SStephen McConnell 	int				prp_pages_free;
32867feec50SStephen McConnell 	int				prp_pages_free_lowwater;
329a2c14879SStephen McConnell 	u_int				enable_ssu;
330a2c14879SStephen McConnell 	int				spinup_wait_time;
3314ab1cdc5SScott Long 	int				use_phynum;
332991554f2SKenneth D. Merry 	uint64_t			chain_alloc_fail;
33367feec50SStephen McConnell 	uint64_t			prp_page_alloc_fail;
334991554f2SKenneth D. Merry 	struct sysctl_ctx_list		sysctl_ctx;
335991554f2SKenneth D. Merry 	struct sysctl_oid		*sysctl_tree;
336991554f2SKenneth D. Merry 	char                            fw_version[16];
337991554f2SKenneth D. Merry 	struct mpr_command		*commands;
338991554f2SKenneth D. Merry 	struct mpr_chain		*chains;
33967feec50SStephen McConnell 	struct mpr_prp_page		*prps;
340991554f2SKenneth D. Merry 	struct callout			periodic;
341327f2e6cSStephen McConnell 	struct callout			device_check_callout;
342bec09074SScott Long 	struct mpr_queue		*queues;
343991554f2SKenneth D. Merry 
344991554f2SKenneth D. Merry 	struct mprsas_softc		*sassc;
345991554f2SKenneth D. Merry 	TAILQ_HEAD(, mpr_command)	req_list;
346991554f2SKenneth D. Merry 	TAILQ_HEAD(, mpr_command)	high_priority_req_list;
347991554f2SKenneth D. Merry 	TAILQ_HEAD(, mpr_chain)		chain_list;
34867feec50SStephen McConnell 	TAILQ_HEAD(, mpr_prp_page)	prp_page_list;
349991554f2SKenneth D. Merry 	TAILQ_HEAD(, mpr_command)	tm_list;
350991554f2SKenneth D. Merry 	int				replypostindex;
351991554f2SKenneth D. Merry 	int				replyfreeindex;
352991554f2SKenneth D. Merry 
353991554f2SKenneth D. Merry 	struct resource			*mpr_regs_resource;
354991554f2SKenneth D. Merry 	bus_space_handle_t		mpr_bhandle;
355991554f2SKenneth D. Merry 	bus_space_tag_t			mpr_btag;
356991554f2SKenneth D. Merry 	int				mpr_regs_rid;
357991554f2SKenneth D. Merry 
358991554f2SKenneth D. Merry 	bus_dma_tag_t			mpr_parent_dmat;
359991554f2SKenneth D. Merry 	bus_dma_tag_t			buffer_dmat;
360991554f2SKenneth D. Merry 
361991554f2SKenneth D. Merry 	MPI2_IOC_FACTS_REPLY		*facts;
362991554f2SKenneth D. Merry 	int				num_reqs;
36362a09ee9SAlexander Motin 	int				num_prireqs;
364991554f2SKenneth D. Merry 	int				num_replies;
3654f5d6573SAlexander Motin 	int				num_chains;
366991554f2SKenneth D. Merry 	int				fqdepth;	/* Free queue */
367991554f2SKenneth D. Merry 	int				pqdepth;	/* Post queue */
368991554f2SKenneth D. Merry 
369991554f2SKenneth D. Merry 	uint8_t				event_mask[16];
370991554f2SKenneth D. Merry 	TAILQ_HEAD(, mpr_event_handle)	event_list;
371991554f2SKenneth D. Merry 	struct mpr_event_handle		*mpr_log_eh;
372991554f2SKenneth D. Merry 
373991554f2SKenneth D. Merry 	struct mtx			mpr_mtx;
374991554f2SKenneth D. Merry 	struct intr_config_hook		mpr_ich;
375991554f2SKenneth D. Merry 
376991554f2SKenneth D. Merry 	uint8_t				*req_frames;
377991554f2SKenneth D. Merry 	bus_addr_t			req_busaddr;
378991554f2SKenneth D. Merry 	bus_dma_tag_t			req_dmat;
379991554f2SKenneth D. Merry 	bus_dmamap_t			req_map;
380991554f2SKenneth D. Merry 
381991554f2SKenneth D. Merry 	uint8_t				*reply_frames;
382991554f2SKenneth D. Merry 	bus_addr_t			reply_busaddr;
383991554f2SKenneth D. Merry 	bus_dma_tag_t			reply_dmat;
384991554f2SKenneth D. Merry 	bus_dmamap_t			reply_map;
385991554f2SKenneth D. Merry 
386991554f2SKenneth D. Merry 	struct scsi_sense_data		*sense_frames;
387991554f2SKenneth D. Merry 	bus_addr_t			sense_busaddr;
388991554f2SKenneth D. Merry 	bus_dma_tag_t			sense_dmat;
389991554f2SKenneth D. Merry 	bus_dmamap_t			sense_map;
390991554f2SKenneth D. Merry 
391991554f2SKenneth D. Merry 	uint8_t				*chain_frames;
392991554f2SKenneth D. Merry 	bus_dma_tag_t			chain_dmat;
393991554f2SKenneth D. Merry 	bus_dmamap_t			chain_map;
394991554f2SKenneth D. Merry 
39567feec50SStephen McConnell 	uint8_t				*prp_pages;
39667feec50SStephen McConnell 	bus_addr_t			prp_page_busaddr;
39767feec50SStephen McConnell 	bus_dma_tag_t			prp_page_dmat;
39867feec50SStephen McConnell 	bus_dmamap_t			prp_page_map;
39967feec50SStephen McConnell 
400991554f2SKenneth D. Merry 	MPI2_REPLY_DESCRIPTORS_UNION	*post_queue;
401991554f2SKenneth D. Merry 	bus_addr_t			post_busaddr;
402991554f2SKenneth D. Merry 	uint32_t			*free_queue;
403991554f2SKenneth D. Merry 	bus_addr_t			free_busaddr;
404991554f2SKenneth D. Merry 	bus_dma_tag_t			queues_dmat;
405991554f2SKenneth D. Merry 	bus_dmamap_t			queues_map;
406991554f2SKenneth D. Merry 
407991554f2SKenneth D. Merry 	uint8_t				*fw_diag_buffer;
408991554f2SKenneth D. Merry 	bus_addr_t			fw_diag_busaddr;
409991554f2SKenneth D. Merry 	bus_dma_tag_t			fw_diag_dmat;
410991554f2SKenneth D. Merry 	bus_dmamap_t			fw_diag_map;
411991554f2SKenneth D. Merry 
412991554f2SKenneth D. Merry 	uint8_t				ir_firmware;
413991554f2SKenneth D. Merry 
414991554f2SKenneth D. Merry 	/* static config pages */
415991554f2SKenneth D. Merry 	Mpi2IOCPage8_t			ioc_pg8;
416991554f2SKenneth D. Merry 	Mpi2IOUnitPage8_t		iounit_pg8;
417991554f2SKenneth D. Merry 
418991554f2SKenneth D. Merry 	/* host mapping support */
419991554f2SKenneth D. Merry 	struct dev_mapping_table	*mapping_table;
420991554f2SKenneth D. Merry 	struct enc_mapping_table	*enclosure_table;
421991554f2SKenneth D. Merry 	struct map_removal_table	*removal_table;
422991554f2SKenneth D. Merry 	uint8_t				*dpm_entry_used;
423991554f2SKenneth D. Merry 	uint8_t				*dpm_flush_entry;
424991554f2SKenneth D. Merry 	Mpi2DriverMappingPage0_t	*dpm_pg0;
425991554f2SKenneth D. Merry 	uint16_t			max_devices;
426991554f2SKenneth D. Merry 	uint16_t			max_enclosures;
427991554f2SKenneth D. Merry 	uint16_t			max_expanders;
428991554f2SKenneth D. Merry 	uint8_t				max_volumes;
429991554f2SKenneth D. Merry 	uint8_t				num_enc_table_entries;
430991554f2SKenneth D. Merry 	uint8_t				num_rsvd_entries;
431991554f2SKenneth D. Merry 	uint16_t			max_dpm_entries;
432991554f2SKenneth D. Merry 	uint8_t				is_dpm_enable;
433991554f2SKenneth D. Merry 	uint8_t				track_mapping_events;
434991554f2SKenneth D. Merry 	uint32_t			pending_map_events;
435991554f2SKenneth D. Merry 
436991554f2SKenneth D. Merry 	/* FW diag Buffer List */
437991554f2SKenneth D. Merry 	mpr_fw_diagnostic_buffer_t
438991554f2SKenneth D. Merry 				fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_COUNT];
439991554f2SKenneth D. Merry 
440991554f2SKenneth D. Merry 	/* Event Recording IOCTL support */
441991554f2SKenneth D. Merry 	uint32_t			events_to_record[4];
442991554f2SKenneth D. Merry 	mpr_event_entry_t		recorded_events[MPR_EVENT_QUEUE_SIZE];
443991554f2SKenneth D. Merry 	uint8_t				event_index;
444991554f2SKenneth D. Merry 	uint32_t			event_number;
445991554f2SKenneth D. Merry 
446991554f2SKenneth D. Merry 	/* EEDP and TLR support */
447991554f2SKenneth D. Merry 	uint8_t				eedp_enabled;
448991554f2SKenneth D. Merry 	uint8_t				control_TLR;
449991554f2SKenneth D. Merry 
450991554f2SKenneth D. Merry 	/* Shutdown Event Handler */
451991554f2SKenneth D. Merry 	eventhandler_tag		shutdown_eh;
452991554f2SKenneth D. Merry 
453991554f2SKenneth D. Merry 	/* To track topo events during reset */
454991554f2SKenneth D. Merry #define	MPR_DIAG_RESET_TIMEOUT	300000
455991554f2SKenneth D. Merry 	uint8_t				wait_for_port_enable;
456991554f2SKenneth D. Merry 	uint8_t				port_enable_complete;
457991554f2SKenneth D. Merry 	uint8_t				msleep_fake_chan;
458991554f2SKenneth D. Merry 
459991554f2SKenneth D. Merry 	/* StartStopUnit command handling at shutdown */
460991554f2SKenneth D. Merry 	uint32_t			SSU_refcount;
461991554f2SKenneth D. Merry 	uint8_t				SSU_started;
462991554f2SKenneth D. Merry 
4633c5ac992SScott Long 	/* Configuration tunables */
4643c5ac992SScott Long 	u_int				disable_msix;
4653c5ac992SScott Long 	u_int				disable_msi;
4663c5ac992SScott Long 	u_int				max_msix;
4673c5ac992SScott Long 	u_int				max_reqframes;
4683c5ac992SScott Long 	u_int				max_prireqframes;
4693c5ac992SScott Long 	u_int				max_replyframes;
4703c5ac992SScott Long 	u_int				max_evtframes;
471991554f2SKenneth D. Merry 	char				exclude_ids[80];
4723c5ac992SScott Long 
473991554f2SKenneth D. Merry 	struct timeval			lastfail;
474991554f2SKenneth D. Merry };
475991554f2SKenneth D. Merry 
476991554f2SKenneth D. Merry struct mpr_config_params {
477991554f2SKenneth D. Merry 	MPI2_CONFIG_EXT_PAGE_HEADER_UNION	hdr;
478991554f2SKenneth D. Merry 	u_int		action;
479991554f2SKenneth D. Merry 	u_int		page_address;	/* Attributes, not a phys address */
480991554f2SKenneth D. Merry 	u_int		status;
481991554f2SKenneth D. Merry 	void		*buffer;
482991554f2SKenneth D. Merry 	u_int		length;
483991554f2SKenneth D. Merry 	int		timeout;
484991554f2SKenneth D. Merry 	void		(*callback)(struct mpr_softc *, struct mpr_config_params *);
485991554f2SKenneth D. Merry 	void		*cbdata;
486991554f2SKenneth D. Merry };
487991554f2SKenneth D. Merry 
488991554f2SKenneth D. Merry struct scsi_read_capacity_eedp
489991554f2SKenneth D. Merry {
490991554f2SKenneth D. Merry 	uint8_t addr[8];
491991554f2SKenneth D. Merry 	uint8_t length[4];
492991554f2SKenneth D. Merry 	uint8_t protect;
493991554f2SKenneth D. Merry };
494991554f2SKenneth D. Merry 
495991554f2SKenneth D. Merry static __inline uint32_t
496991554f2SKenneth D. Merry mpr_regread(struct mpr_softc *sc, uint32_t offset)
497991554f2SKenneth D. Merry {
498991554f2SKenneth D. Merry 	return (bus_space_read_4(sc->mpr_btag, sc->mpr_bhandle, offset));
499991554f2SKenneth D. Merry }
500991554f2SKenneth D. Merry 
501991554f2SKenneth D. Merry static __inline void
502991554f2SKenneth D. Merry mpr_regwrite(struct mpr_softc *sc, uint32_t offset, uint32_t val)
503991554f2SKenneth D. Merry {
504991554f2SKenneth D. Merry 	bus_space_write_4(sc->mpr_btag, sc->mpr_bhandle, offset, val);
505991554f2SKenneth D. Merry }
506991554f2SKenneth D. Merry 
507991554f2SKenneth D. Merry /* free_queue must have Little Endian address
508991554f2SKenneth D. Merry  * TODO- cm_reply_data is unwanted. We can remove it.
509991554f2SKenneth D. Merry  * */
510991554f2SKenneth D. Merry static __inline void
511991554f2SKenneth D. Merry mpr_free_reply(struct mpr_softc *sc, uint32_t busaddr)
512991554f2SKenneth D. Merry {
513991554f2SKenneth D. Merry 	if (++sc->replyfreeindex >= sc->fqdepth)
514991554f2SKenneth D. Merry 		sc->replyfreeindex = 0;
515991554f2SKenneth D. Merry 	sc->free_queue[sc->replyfreeindex] = htole32(busaddr);
516991554f2SKenneth D. Merry 	mpr_regwrite(sc, MPI2_REPLY_FREE_HOST_INDEX_OFFSET, sc->replyfreeindex);
517991554f2SKenneth D. Merry }
518991554f2SKenneth D. Merry 
519991554f2SKenneth D. Merry static __inline struct mpr_chain *
520991554f2SKenneth D. Merry mpr_alloc_chain(struct mpr_softc *sc)
521991554f2SKenneth D. Merry {
522991554f2SKenneth D. Merry 	struct mpr_chain *chain;
523991554f2SKenneth D. Merry 
524991554f2SKenneth D. Merry 	if ((chain = TAILQ_FIRST(&sc->chain_list)) != NULL) {
525991554f2SKenneth D. Merry 		TAILQ_REMOVE(&sc->chain_list, chain, chain_link);
526991554f2SKenneth D. Merry 		sc->chain_free--;
527991554f2SKenneth D. Merry 		if (sc->chain_free < sc->chain_free_lowwater)
528991554f2SKenneth D. Merry 			sc->chain_free_lowwater = sc->chain_free;
529d0be3479SScott Long 	} else
530991554f2SKenneth D. Merry 		sc->chain_alloc_fail++;
531991554f2SKenneth D. Merry 	return (chain);
532991554f2SKenneth D. Merry }
533991554f2SKenneth D. Merry 
534991554f2SKenneth D. Merry static __inline void
535991554f2SKenneth D. Merry mpr_free_chain(struct mpr_softc *sc, struct mpr_chain *chain)
536991554f2SKenneth D. Merry {
537991554f2SKenneth D. Merry #if 0
538991554f2SKenneth D. Merry 	bzero(chain->chain, 128);
539991554f2SKenneth D. Merry #endif
540991554f2SKenneth D. Merry 	sc->chain_free++;
541991554f2SKenneth D. Merry 	TAILQ_INSERT_TAIL(&sc->chain_list, chain, chain_link);
542991554f2SKenneth D. Merry }
543991554f2SKenneth D. Merry 
54467feec50SStephen McConnell static __inline struct mpr_prp_page *
54567feec50SStephen McConnell mpr_alloc_prp_page(struct mpr_softc *sc)
54667feec50SStephen McConnell {
54767feec50SStephen McConnell 	struct mpr_prp_page *prp_page;
54867feec50SStephen McConnell 
54967feec50SStephen McConnell 	if ((prp_page = TAILQ_FIRST(&sc->prp_page_list)) != NULL) {
55067feec50SStephen McConnell 		TAILQ_REMOVE(&sc->prp_page_list, prp_page, prp_page_link);
55167feec50SStephen McConnell 		sc->prp_pages_free--;
55267feec50SStephen McConnell 		if (sc->prp_pages_free < sc->prp_pages_free_lowwater)
55367feec50SStephen McConnell 			sc->prp_pages_free_lowwater = sc->prp_pages_free;
55467feec50SStephen McConnell 	} else
55567feec50SStephen McConnell 		sc->prp_page_alloc_fail++;
55667feec50SStephen McConnell 	return (prp_page);
55767feec50SStephen McConnell }
55867feec50SStephen McConnell 
55967feec50SStephen McConnell static __inline void
56067feec50SStephen McConnell mpr_free_prp_page(struct mpr_softc *sc, struct mpr_prp_page *prp_page)
56167feec50SStephen McConnell {
56267feec50SStephen McConnell 	sc->prp_pages_free++;
56367feec50SStephen McConnell 	TAILQ_INSERT_TAIL(&sc->prp_page_list, prp_page, prp_page_link);
56467feec50SStephen McConnell }
56567feec50SStephen McConnell 
566991554f2SKenneth D. Merry static __inline void
567991554f2SKenneth D. Merry mpr_free_command(struct mpr_softc *sc, struct mpr_command *cm)
568991554f2SKenneth D. Merry {
569991554f2SKenneth D. Merry 	struct mpr_chain *chain, *chain_temp;
57067feec50SStephen McConnell 	struct mpr_prp_page *prp_page, *prp_page_temp;
571991554f2SKenneth D. Merry 
572f0779b04SScott Long 	KASSERT(cm->cm_state == MPR_CM_STATE_BUSY, ("state not busy\n"));
573f0779b04SScott Long 
574991554f2SKenneth D. Merry 	if (cm->cm_reply != NULL)
575991554f2SKenneth D. Merry 		mpr_free_reply(sc, cm->cm_reply_data);
576991554f2SKenneth D. Merry 	cm->cm_reply = NULL;
577991554f2SKenneth D. Merry 	cm->cm_flags = 0;
578991554f2SKenneth D. Merry 	cm->cm_complete = NULL;
579991554f2SKenneth D. Merry 	cm->cm_complete_data = NULL;
580991554f2SKenneth D. Merry 	cm->cm_ccb = NULL;
581991554f2SKenneth D. Merry 	cm->cm_targ = NULL;
582991554f2SKenneth D. Merry 	cm->cm_max_segs = 0;
583991554f2SKenneth D. Merry 	cm->cm_lun = 0;
584991554f2SKenneth D. Merry 	cm->cm_state = MPR_CM_STATE_FREE;
585991554f2SKenneth D. Merry 	cm->cm_data = NULL;
586991554f2SKenneth D. Merry 	cm->cm_length = 0;
587991554f2SKenneth D. Merry 	cm->cm_out_len = 0;
588991554f2SKenneth D. Merry 	cm->cm_sglsize = 0;
589991554f2SKenneth D. Merry 	cm->cm_sge = NULL;
590991554f2SKenneth D. Merry 
591991554f2SKenneth D. Merry 	TAILQ_FOREACH_SAFE(chain, &cm->cm_chain_list, chain_link, chain_temp) {
592991554f2SKenneth D. Merry 		TAILQ_REMOVE(&cm->cm_chain_list, chain, chain_link);
593991554f2SKenneth D. Merry 		mpr_free_chain(sc, chain);
594991554f2SKenneth D. Merry 	}
59567feec50SStephen McConnell 	TAILQ_FOREACH_SAFE(prp_page, &cm->cm_prp_page_list, prp_page_link,
59667feec50SStephen McConnell 	    prp_page_temp) {
59767feec50SStephen McConnell 		TAILQ_REMOVE(&cm->cm_prp_page_list, prp_page, prp_page_link);
59867feec50SStephen McConnell 		mpr_free_prp_page(sc, prp_page);
59967feec50SStephen McConnell 	}
600991554f2SKenneth D. Merry 	TAILQ_INSERT_TAIL(&sc->req_list, cm, cm_link);
601991554f2SKenneth D. Merry }
602991554f2SKenneth D. Merry 
603991554f2SKenneth D. Merry static __inline struct mpr_command *
604991554f2SKenneth D. Merry mpr_alloc_command(struct mpr_softc *sc)
605991554f2SKenneth D. Merry {
606991554f2SKenneth D. Merry 	struct mpr_command *cm;
607991554f2SKenneth D. Merry 
608991554f2SKenneth D. Merry 	cm = TAILQ_FIRST(&sc->req_list);
609991554f2SKenneth D. Merry 	if (cm == NULL)
610991554f2SKenneth D. Merry 		return (NULL);
611991554f2SKenneth D. Merry 
612f0779b04SScott Long 	KASSERT(cm->cm_state == MPR_CM_STATE_FREE,
613f0779b04SScott Long 	    ("mpr: Allocating busy command\n"));
614f0779b04SScott Long 
615991554f2SKenneth D. Merry 	TAILQ_REMOVE(&sc->req_list, cm, cm_link);
616991554f2SKenneth D. Merry 	cm->cm_state = MPR_CM_STATE_BUSY;
617*86312e46SConrad Meyer 	cm->cm_timeout_handler = NULL;
618991554f2SKenneth D. Merry 	return (cm);
619991554f2SKenneth D. Merry }
620991554f2SKenneth D. Merry 
621991554f2SKenneth D. Merry static __inline void
622991554f2SKenneth D. Merry mpr_free_high_priority_command(struct mpr_softc *sc, struct mpr_command *cm)
623991554f2SKenneth D. Merry {
624991554f2SKenneth D. Merry 	struct mpr_chain *chain, *chain_temp;
625991554f2SKenneth D. Merry 
626f0779b04SScott Long 	KASSERT(cm->cm_state == MPR_CM_STATE_BUSY, ("state not busy\n"));
627f0779b04SScott Long 
628991554f2SKenneth D. Merry 	if (cm->cm_reply != NULL)
629991554f2SKenneth D. Merry 		mpr_free_reply(sc, cm->cm_reply_data);
630991554f2SKenneth D. Merry 	cm->cm_reply = NULL;
631991554f2SKenneth D. Merry 	cm->cm_flags = 0;
632991554f2SKenneth D. Merry 	cm->cm_complete = NULL;
633991554f2SKenneth D. Merry 	cm->cm_complete_data = NULL;
634991554f2SKenneth D. Merry 	cm->cm_ccb = NULL;
635991554f2SKenneth D. Merry 	cm->cm_targ = NULL;
636991554f2SKenneth D. Merry 	cm->cm_lun = 0;
637991554f2SKenneth D. Merry 	cm->cm_state = MPR_CM_STATE_FREE;
638991554f2SKenneth D. Merry 	TAILQ_FOREACH_SAFE(chain, &cm->cm_chain_list, chain_link, chain_temp) {
639991554f2SKenneth D. Merry 		TAILQ_REMOVE(&cm->cm_chain_list, chain, chain_link);
640991554f2SKenneth D. Merry 		mpr_free_chain(sc, chain);
641991554f2SKenneth D. Merry 	}
642991554f2SKenneth D. Merry 	TAILQ_INSERT_TAIL(&sc->high_priority_req_list, cm, cm_link);
643991554f2SKenneth D. Merry }
644991554f2SKenneth D. Merry 
645991554f2SKenneth D. Merry static __inline struct mpr_command *
646991554f2SKenneth D. Merry mpr_alloc_high_priority_command(struct mpr_softc *sc)
647991554f2SKenneth D. Merry {
648991554f2SKenneth D. Merry 	struct mpr_command *cm;
649991554f2SKenneth D. Merry 
650991554f2SKenneth D. Merry 	cm = TAILQ_FIRST(&sc->high_priority_req_list);
651991554f2SKenneth D. Merry 	if (cm == NULL)
652991554f2SKenneth D. Merry 		return (NULL);
653991554f2SKenneth D. Merry 
654f0779b04SScott Long 	KASSERT(cm->cm_state == MPR_CM_STATE_FREE,
655f0779b04SScott Long 	    ("mpr: Allocating busy command\n"));
656f0779b04SScott Long 
657991554f2SKenneth D. Merry 	TAILQ_REMOVE(&sc->high_priority_req_list, cm, cm_link);
658991554f2SKenneth D. Merry 	cm->cm_state = MPR_CM_STATE_BUSY;
659*86312e46SConrad Meyer 	cm->cm_timeout_handler = NULL;
660991554f2SKenneth D. Merry 	return (cm);
661991554f2SKenneth D. Merry }
662991554f2SKenneth D. Merry 
663991554f2SKenneth D. Merry static __inline void
664991554f2SKenneth D. Merry mpr_lock(struct mpr_softc *sc)
665991554f2SKenneth D. Merry {
666991554f2SKenneth D. Merry 	mtx_lock(&sc->mpr_mtx);
667991554f2SKenneth D. Merry }
668991554f2SKenneth D. Merry 
669991554f2SKenneth D. Merry static __inline void
670991554f2SKenneth D. Merry mpr_unlock(struct mpr_softc *sc)
671991554f2SKenneth D. Merry {
672991554f2SKenneth D. Merry 	mtx_unlock(&sc->mpr_mtx);
673991554f2SKenneth D. Merry }
674991554f2SKenneth D. Merry 
675991554f2SKenneth D. Merry #define MPR_INFO	(1 << 0)	/* Basic info */
676991554f2SKenneth D. Merry #define MPR_FAULT	(1 << 1)	/* Hardware faults */
677991554f2SKenneth D. Merry #define MPR_EVENT	(1 << 2)	/* Event data from the controller */
678991554f2SKenneth D. Merry #define MPR_LOG		(1 << 3)	/* Log data from the controller */
679991554f2SKenneth D. Merry #define MPR_RECOVERY	(1 << 4)	/* Command error recovery tracing */
680991554f2SKenneth D. Merry #define MPR_ERROR	(1 << 5)	/* Parameter errors, programming bugs */
681991554f2SKenneth D. Merry #define MPR_INIT	(1 << 6)	/* Things related to system init */
682991554f2SKenneth D. Merry #define MPR_XINFO	(1 << 7)	/* More detailed/noisy info */
683991554f2SKenneth D. Merry #define MPR_USER	(1 << 8)	/* Trace user-generated commands */
684991554f2SKenneth D. Merry #define MPR_MAPPING	(1 << 9)	/* Trace device mappings */
685991554f2SKenneth D. Merry #define MPR_TRACE	(1 << 10)	/* Function-by-function trace */
686991554f2SKenneth D. Merry 
687a2c14879SStephen McConnell #define	MPR_SSU_DISABLE_SSD_DISABLE_HDD	0
688a2c14879SStephen McConnell #define	MPR_SSU_ENABLE_SSD_DISABLE_HDD	1
689a2c14879SStephen McConnell #define	MPR_SSU_DISABLE_SSD_ENABLE_HDD	2
690a2c14879SStephen McConnell #define	MPR_SSU_ENABLE_SSD_ENABLE_HDD	3
691a2c14879SStephen McConnell 
692991554f2SKenneth D. Merry #define mpr_printf(sc, args...)				\
693991554f2SKenneth D. Merry 	device_printf((sc)->mpr_dev, ##args)
694991554f2SKenneth D. Merry 
695c11c484fSScott Long #define mpr_print_field(sc, msg, args...)		\
696c11c484fSScott Long 	printf("\t" msg, ##args)
697c11c484fSScott Long 
698991554f2SKenneth D. Merry #define mpr_vprintf(sc, args...)			\
699991554f2SKenneth D. Merry do {							\
700991554f2SKenneth D. Merry 	if (bootverbose)				\
701991554f2SKenneth D. Merry 		mpr_printf(sc, ##args);			\
702991554f2SKenneth D. Merry } while (0)
703991554f2SKenneth D. Merry 
704991554f2SKenneth D. Merry #define mpr_dprint(sc, level, msg, args...)		\
705991554f2SKenneth D. Merry do {							\
7067a2a6a1aSStephen McConnell 	if ((sc)->mpr_debug & (level))			\
707991554f2SKenneth D. Merry 		device_printf((sc)->mpr_dev, msg, ##args);	\
708991554f2SKenneth D. Merry } while (0)
709991554f2SKenneth D. Merry 
710991554f2SKenneth D. Merry #define MPR_PRINTFIELD_START(sc, tag...)	\
711c11c484fSScott Long 	mpr_printf((sc), ##tag);		\
712c11c484fSScott Long 	mpr_print_field((sc), ":\n")
713991554f2SKenneth D. Merry #define MPR_PRINTFIELD_END(sc, tag)		\
714c11c484fSScott Long 	mpr_printf((sc), tag "\n")
715991554f2SKenneth D. Merry #define MPR_PRINTFIELD(sc, facts, attr, fmt)	\
716c11c484fSScott Long 	mpr_print_field((sc), #attr ": " #fmt "\n", (facts)->attr)
717991554f2SKenneth D. Merry 
718991554f2SKenneth D. Merry static __inline void
719991554f2SKenneth D. Merry mpr_from_u64(uint64_t data, U64 *mpr)
720991554f2SKenneth D. Merry {
721991554f2SKenneth D. Merry 	(mpr)->High = htole32((uint32_t)((data) >> 32));
722991554f2SKenneth D. Merry 	(mpr)->Low = htole32((uint32_t)((data) & 0xffffffff));
723991554f2SKenneth D. Merry }
724991554f2SKenneth D. Merry 
725991554f2SKenneth D. Merry static __inline uint64_t
726991554f2SKenneth D. Merry mpr_to_u64(U64 *data)
727991554f2SKenneth D. Merry {
728991554f2SKenneth D. Merry 	return (((uint64_t)le32toh(data->High) << 32) | le32toh(data->Low));
729991554f2SKenneth D. Merry }
730991554f2SKenneth D. Merry 
731991554f2SKenneth D. Merry static __inline void
732991554f2SKenneth D. Merry mpr_mask_intr(struct mpr_softc *sc)
733991554f2SKenneth D. Merry {
734991554f2SKenneth D. Merry 	uint32_t mask;
735991554f2SKenneth D. Merry 
736991554f2SKenneth D. Merry 	mask = mpr_regread(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET);
737991554f2SKenneth D. Merry 	mask |= MPI2_HIM_REPLY_INT_MASK;
738991554f2SKenneth D. Merry 	mpr_regwrite(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET, mask);
739991554f2SKenneth D. Merry }
740991554f2SKenneth D. Merry 
741991554f2SKenneth D. Merry static __inline void
742991554f2SKenneth D. Merry mpr_unmask_intr(struct mpr_softc *sc)
743991554f2SKenneth D. Merry {
744991554f2SKenneth D. Merry 	uint32_t mask;
745991554f2SKenneth D. Merry 
746991554f2SKenneth D. Merry 	mask = mpr_regread(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET);
747991554f2SKenneth D. Merry 	mask &= ~MPI2_HIM_REPLY_INT_MASK;
748991554f2SKenneth D. Merry 	mpr_regwrite(sc, MPI2_HOST_INTERRUPT_MASK_OFFSET, mask);
749991554f2SKenneth D. Merry }
750991554f2SKenneth D. Merry 
751991554f2SKenneth D. Merry int mpr_pci_setup_interrupts(struct mpr_softc *sc);
752bec09074SScott Long void mpr_pci_free_interrupts(struct mpr_softc *sc);
753991554f2SKenneth D. Merry int mpr_pci_restore(struct mpr_softc *sc);
754991554f2SKenneth D. Merry 
755252b2b4fSScott Long void mpr_get_tunables(struct mpr_softc *sc);
756991554f2SKenneth D. Merry int mpr_attach(struct mpr_softc *sc);
757991554f2SKenneth D. Merry int mpr_free(struct mpr_softc *sc);
758991554f2SKenneth D. Merry void mpr_intr(void *);
759991554f2SKenneth D. Merry void mpr_intr_msi(void *);
760991554f2SKenneth D. Merry void mpr_intr_locked(void *);
761991554f2SKenneth D. Merry int mpr_register_events(struct mpr_softc *, uint8_t *, mpr_evt_callback_t *,
762991554f2SKenneth D. Merry     void *, struct mpr_event_handle **);
763991554f2SKenneth D. Merry int mpr_restart(struct mpr_softc *);
7647a2a6a1aSStephen McConnell int mpr_update_events(struct mpr_softc *, struct mpr_event_handle *, uint8_t *);
765991554f2SKenneth D. Merry int mpr_deregister_events(struct mpr_softc *, struct mpr_event_handle *);
76667feec50SStephen McConnell void mpr_build_nvme_prp(struct mpr_softc *sc, struct mpr_command *cm,
76767feec50SStephen McConnell     Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request, void *data,
76867feec50SStephen McConnell     uint32_t data_in_sz, uint32_t data_out_sz);
769991554f2SKenneth D. Merry int mpr_push_sge(struct mpr_command *, MPI2_SGE_SIMPLE64 *, size_t, int);
770991554f2SKenneth D. Merry int mpr_push_ieee_sge(struct mpr_command *, void *, int);
771991554f2SKenneth D. Merry int mpr_add_dmaseg(struct mpr_command *, vm_paddr_t, size_t, u_int, int);
772991554f2SKenneth D. Merry int mpr_attach_sas(struct mpr_softc *sc);
773991554f2SKenneth D. Merry int mpr_detach_sas(struct mpr_softc *sc);
774991554f2SKenneth D. Merry int mpr_read_config_page(struct mpr_softc *, struct mpr_config_params *);
775991554f2SKenneth D. Merry int mpr_write_config_page(struct mpr_softc *, struct mpr_config_params *);
776991554f2SKenneth D. Merry void mpr_memaddr_cb(void *, bus_dma_segment_t *, int , int );
777e2997a03SKenneth D. Merry void mpr_memaddr_wait_cb(void *, bus_dma_segment_t *, int , int );
778991554f2SKenneth D. Merry void mpr_init_sge(struct mpr_command *cm, void *req, void *sge);
779991554f2SKenneth D. Merry int mpr_attach_user(struct mpr_softc *);
780991554f2SKenneth D. Merry void mpr_detach_user(struct mpr_softc *);
781991554f2SKenneth D. Merry void mprsas_record_event(struct mpr_softc *sc,
782991554f2SKenneth D. Merry     MPI2_EVENT_NOTIFICATION_REPLY *event_reply);
783991554f2SKenneth D. Merry 
784991554f2SKenneth D. Merry int mpr_map_command(struct mpr_softc *sc, struct mpr_command *cm);
7856d4ffcb4SKenneth D. Merry int mpr_wait_command(struct mpr_softc *sc, struct mpr_command **cm, int timeout,
7867a2a6a1aSStephen McConnell     int sleep_flag);
7876d4ffcb4SKenneth D. Merry int mpr_request_polled(struct mpr_softc *sc, struct mpr_command **cm);
788991554f2SKenneth D. Merry 
789991554f2SKenneth D. Merry int mpr_config_get_bios_pg3(struct mpr_softc *sc, Mpi2ConfigReply_t
790991554f2SKenneth D. Merry     *mpi_reply, Mpi2BiosPage3_t *config_page);
791991554f2SKenneth D. Merry int mpr_config_get_raid_volume_pg0(struct mpr_softc *sc, Mpi2ConfigReply_t
792991554f2SKenneth D. Merry     *mpi_reply, Mpi2RaidVolPage0_t *config_page, u32 page_address);
793991554f2SKenneth D. Merry int mpr_config_get_ioc_pg8(struct mpr_softc *sc, Mpi2ConfigReply_t *,
794991554f2SKenneth D. Merry     Mpi2IOCPage8_t *);
795991554f2SKenneth D. Merry int mpr_config_get_iounit_pg8(struct mpr_softc *sc,
796991554f2SKenneth D. Merry     Mpi2ConfigReply_t *mpi_reply, Mpi2IOUnitPage8_t *config_page);
797991554f2SKenneth D. Merry int mpr_config_get_sas_device_pg0(struct mpr_softc *, Mpi2ConfigReply_t *,
798991554f2SKenneth D. Merry     Mpi2SasDevicePage0_t *, u32 , u16 );
79967feec50SStephen McConnell int mpr_config_get_pcie_device_pg0(struct mpr_softc *sc, Mpi2ConfigReply_t
80067feec50SStephen McConnell     *mpi_reply, Mpi26PCIeDevicePage0_t *config_page, u32 form, u16 handle);
80167feec50SStephen McConnell int mpr_config_get_pcie_device_pg2(struct mpr_softc *sc, Mpi2ConfigReply_t
80267feec50SStephen McConnell     *mpi_reply, Mpi26PCIeDevicePage2_t *config_page, u32 form, u16 handle);
803991554f2SKenneth D. Merry int mpr_config_get_dpm_pg0(struct mpr_softc *, Mpi2ConfigReply_t *,
804991554f2SKenneth D. Merry     Mpi2DriverMappingPage0_t *, u16 );
805991554f2SKenneth D. Merry int mpr_config_get_raid_volume_pg1(struct mpr_softc *sc,
806991554f2SKenneth D. Merry     Mpi2ConfigReply_t *mpi_reply, Mpi2RaidVolPage1_t *config_page, u32 form,
807991554f2SKenneth D. Merry     u16 handle);
808991554f2SKenneth D. Merry int mpr_config_get_volume_wwid(struct mpr_softc *sc, u16 volume_handle,
809991554f2SKenneth D. Merry     u64 *wwid);
810991554f2SKenneth D. Merry int mpr_config_get_raid_pd_pg0(struct mpr_softc *sc,
811991554f2SKenneth D. Merry     Mpi2ConfigReply_t *mpi_reply, Mpi2RaidPhysDiskPage0_t *config_page,
812991554f2SKenneth D. Merry     u32 page_address);
813acc173a6SWarner Losh void mprsas_ir_shutdown(struct mpr_softc *sc, int howto);
814991554f2SKenneth D. Merry 
815991554f2SKenneth D. Merry int mpr_reinit(struct mpr_softc *sc);
816991554f2SKenneth D. Merry void mprsas_handle_reinit(struct mpr_softc *sc);
817991554f2SKenneth D. Merry 
818991554f2SKenneth D. Merry void mpr_base_static_config_pages(struct mpr_softc *sc);
819991554f2SKenneth D. Merry 
820991554f2SKenneth D. Merry int mpr_mapping_initialize(struct mpr_softc *);
821991554f2SKenneth D. Merry void mpr_mapping_topology_change_event(struct mpr_softc *,
822991554f2SKenneth D. Merry     Mpi2EventDataSasTopologyChangeList_t *);
82367feec50SStephen McConnell void mpr_mapping_pcie_topology_change_event(struct mpr_softc *sc,
82467feec50SStephen McConnell     Mpi26EventDataPCIeTopologyChangeList_t *event_data);
825991554f2SKenneth D. Merry void mpr_mapping_free_memory(struct mpr_softc *sc);
826991554f2SKenneth D. Merry int mpr_config_set_dpm_pg0(struct mpr_softc *, Mpi2ConfigReply_t *,
827991554f2SKenneth D. Merry     Mpi2DriverMappingPage0_t *, u16 );
828991554f2SKenneth D. Merry void mpr_mapping_exit(struct mpr_softc *);
829327f2e6cSStephen McConnell void mpr_mapping_check_devices(void *);
830991554f2SKenneth D. Merry int mpr_mapping_allocate_memory(struct mpr_softc *sc);
831327f2e6cSStephen McConnell unsigned int mpr_mapping_get_tid(struct mpr_softc *, uint64_t , u16);
832327f2e6cSStephen McConnell unsigned int mpr_mapping_get_tid_from_handle(struct mpr_softc *sc,
833991554f2SKenneth D. Merry     u16 handle);
834327f2e6cSStephen McConnell unsigned int mpr_mapping_get_raid_tid(struct mpr_softc *sc, u64 wwid,
835327f2e6cSStephen McConnell     u16 volHandle);
836327f2e6cSStephen McConnell unsigned int mpr_mapping_get_raid_tid_from_handle(struct mpr_softc *sc,
837991554f2SKenneth D. Merry     u16 volHandle);
838991554f2SKenneth D. Merry void mpr_mapping_enclosure_dev_status_change_event(struct mpr_softc *,
839991554f2SKenneth D. Merry     Mpi2EventDataSasEnclDevStatusChange_t *event_data);
840991554f2SKenneth D. Merry void mpr_mapping_ir_config_change_event(struct mpr_softc *sc,
841991554f2SKenneth D. Merry     Mpi2EventDataIrConfigChangeList_t *event_data);
842991554f2SKenneth D. Merry 
843991554f2SKenneth D. Merry void mprsas_evt_handler(struct mpr_softc *sc, uintptr_t data,
844991554f2SKenneth D. Merry     MPI2_EVENT_NOTIFICATION_REPLY *event);
845991554f2SKenneth D. Merry void mprsas_prepare_remove(struct mprsas_softc *sassc, uint16_t handle);
8467a2a6a1aSStephen McConnell void mprsas_prepare_volume_remove(struct mprsas_softc *sassc, uint16_t handle);
847991554f2SKenneth D. Merry int mprsas_startup(struct mpr_softc *sc);
8487a2a6a1aSStephen McConnell struct mprsas_target * mprsas_find_target_by_handle(struct mprsas_softc *, int,
8497a2a6a1aSStephen McConnell     uint16_t);
850a2c14879SStephen McConnell void mprsas_realloc_targets(struct mpr_softc *sc, int maxtargets);
851a2c14879SStephen McConnell struct mpr_command * mprsas_alloc_tm(struct mpr_softc *sc);
852a2c14879SStephen McConnell void mprsas_free_tm(struct mpr_softc *sc, struct mpr_command *tm);
853a2c14879SStephen McConnell void mprsas_release_simq_reinit(struct mprsas_softc *sassc);
854a2c14879SStephen McConnell int mprsas_send_reset(struct mpr_softc *sc, struct mpr_command *tm,
855a2c14879SStephen McConnell     uint8_t type);
856991554f2SKenneth D. Merry 
857991554f2SKenneth D. Merry SYSCTL_DECL(_hw_mpr);
858991554f2SKenneth D. Merry 
859991554f2SKenneth D. Merry /* Compatibility shims for different OS versions */
860991554f2SKenneth D. Merry #if __FreeBSD_version >= 800001
861991554f2SKenneth D. Merry #define mpr_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
862991554f2SKenneth D. Merry     kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
863991554f2SKenneth D. Merry #define mpr_kproc_exit(arg)	kproc_exit(arg)
864991554f2SKenneth D. Merry #else
865991554f2SKenneth D. Merry #define mpr_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \
866991554f2SKenneth D. Merry     kthread_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg)
867991554f2SKenneth D. Merry #define mpr_kproc_exit(arg)	kthread_exit(arg)
868991554f2SKenneth D. Merry #endif
869991554f2SKenneth D. Merry 
870991554f2SKenneth D. Merry #if defined(CAM_PRIORITY_XPT)
871991554f2SKenneth D. Merry #define MPR_PRIORITY_XPT	CAM_PRIORITY_XPT
872991554f2SKenneth D. Merry #else
873991554f2SKenneth D. Merry #define MPR_PRIORITY_XPT	5
874991554f2SKenneth D. Merry #endif
875991554f2SKenneth D. Merry 
876991554f2SKenneth D. Merry #if __FreeBSD_version < 800107
877991554f2SKenneth D. Merry // Prior to FreeBSD-8.0 scp3_flags was not defined.
878991554f2SKenneth D. Merry #define spc3_flags reserved
879991554f2SKenneth D. Merry 
880991554f2SKenneth D. Merry #define SPC3_SID_PROTECT    0x01
881991554f2SKenneth D. Merry #define SPC3_SID_3PC        0x08
882991554f2SKenneth D. Merry #define SPC3_SID_TPGS_MASK  0x30
883991554f2SKenneth D. Merry #define SPC3_SID_TPGS_IMPLICIT  0x10
884991554f2SKenneth D. Merry #define SPC3_SID_TPGS_EXPLICIT  0x20
885991554f2SKenneth D. Merry #define SPC3_SID_ACC        0x40
886991554f2SKenneth D. Merry #define SPC3_SID_SCCS       0x80
887991554f2SKenneth D. Merry 
888991554f2SKenneth D. Merry #define CAM_PRIORITY_NORMAL CAM_PRIORITY_NONE
889991554f2SKenneth D. Merry #endif
890991554f2SKenneth D. Merry 
89167feec50SStephen McConnell /* Definitions for SCSI unmap translation to NVMe DSM command */
89267feec50SStephen McConnell 
89367feec50SStephen McConnell /* UNMAP block descriptor structure */
89467feec50SStephen McConnell struct unmap_blk_desc {
89567feec50SStephen McConnell 	uint64_t slba;
89667feec50SStephen McConnell 	uint32_t nlb;
89767feec50SStephen McConnell 	uint32_t resv;
89867feec50SStephen McConnell };
89967feec50SStephen McConnell 
90067feec50SStephen McConnell /* UNMAP command's data */
90167feec50SStephen McConnell struct unmap_parm_list {
90267feec50SStephen McConnell 	uint16_t unmap_data_len;
90367feec50SStephen McConnell 	uint16_t unmap_blk_desc_data_len;
90467feec50SStephen McConnell 	uint32_t resv;
90567feec50SStephen McConnell 	struct unmap_blk_desc desc[0];
90667feec50SStephen McConnell };
90767feec50SStephen McConnell 
90867feec50SStephen McConnell /* SCSI ADDITIONAL SENSE Codes */
90967feec50SStephen McConnell #define FIXED_SENSE_DATA                                0x70
91067feec50SStephen McConnell #define SCSI_ASC_NO_SENSE                               0x00
91167feec50SStephen McConnell #define SCSI_ASC_PERIPHERAL_DEV_WRITE_FAULT             0x03
91267feec50SStephen McConnell #define SCSI_ASC_LUN_NOT_READY                          0x04
91367feec50SStephen McConnell #define SCSI_ASC_WARNING                                0x0B
91467feec50SStephen McConnell #define SCSI_ASC_LOG_BLOCK_GUARD_CHECK_FAILED           0x10
91567feec50SStephen McConnell #define SCSI_ASC_LOG_BLOCK_APPTAG_CHECK_FAILED          0x10
91667feec50SStephen McConnell #define SCSI_ASC_LOG_BLOCK_REFTAG_CHECK_FAILED          0x10
91767feec50SStephen McConnell #define SCSI_ASC_UNRECOVERED_READ_ERROR                 0x11
91867feec50SStephen McConnell #define SCSI_ASC_MISCOMPARE_DURING_VERIFY               0x1D
91967feec50SStephen McConnell #define SCSI_ASC_ACCESS_DENIED_INVALID_LUN_ID           0x20
92067feec50SStephen McConnell #define SCSI_ASC_ILLEGAL_COMMAND                        0x20
92167feec50SStephen McConnell #define SCSI_ASC_ILLEGAL_BLOCK                          0x21
92267feec50SStephen McConnell #define SCSI_ASC_INVALID_CDB                            0x24
92367feec50SStephen McConnell #define SCSI_ASC_INVALID_LUN                            0x25
92467feec50SStephen McConnell #define SCSI_ASC_INVALID_PARAMETER                      0x26
92567feec50SStephen McConnell #define SCSI_ASC_FORMAT_COMMAND_FAILED                  0x31
92667feec50SStephen McConnell #define SCSI_ASC_INTERNAL_TARGET_FAILURE                0x44
92767feec50SStephen McConnell 
92867feec50SStephen McConnell /* SCSI ADDITIONAL SENSE Code Qualifiers */
92967feec50SStephen McConnell #define SCSI_ASCQ_CAUSE_NOT_REPORTABLE                  0x00
93067feec50SStephen McConnell #define SCSI_ASCQ_FORMAT_COMMAND_FAILED                 0x01
93167feec50SStephen McConnell #define SCSI_ASCQ_LOG_BLOCK_GUARD_CHECK_FAILED          0x01
93267feec50SStephen McConnell #define SCSI_ASCQ_LOG_BLOCK_APPTAG_CHECK_FAILED         0x02
93367feec50SStephen McConnell #define SCSI_ASCQ_LOG_BLOCK_REFTAG_CHECK_FAILED         0x03
93467feec50SStephen McConnell #define SCSI_ASCQ_FORMAT_IN_PROGRESS                    0x04
93567feec50SStephen McConnell #define SCSI_ASCQ_POWER_LOSS_EXPECTED                   0x08
93667feec50SStephen McConnell #define SCSI_ASCQ_INVALID_LUN_ID                        0x09
93767feec50SStephen McConnell 
938991554f2SKenneth D. Merry #endif
939991554f2SKenneth D. Merry 
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