xref: /freebsd/sys/dev/mpr/mpr_pci.c (revision e32fecd0c2c3ee37c47ee100f169e7eb0282a873)
1 /*-
2  * Copyright (c) 2009 Yahoo! Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright
11  *    notice, this list of conditions and the following disclaimer in the
12  *    documentation and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24  * SUCH DAMAGE.
25  */
26 
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
29 
30 /* PCI/PCI-X/PCIe bus interface for the Avago Tech (LSI) MPT3 controllers */
31 
32 /* TODO Move headers to mprvar */
33 #include <sys/types.h>
34 #include <sys/param.h>
35 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/module.h>
38 #include <sys/bus.h>
39 #include <sys/conf.h>
40 #include <sys/malloc.h>
41 #include <sys/sysctl.h>
42 #include <sys/uio.h>
43 
44 #include <machine/bus.h>
45 #include <machine/resource.h>
46 #include <sys/rman.h>
47 
48 #include <dev/pci/pcireg.h>
49 #include <dev/pci/pcivar.h>
50 #include <dev/pci/pci_private.h>
51 
52 #include <dev/mpr/mpi/mpi2_type.h>
53 #include <dev/mpr/mpi/mpi2.h>
54 #include <dev/mpr/mpi/mpi2_ioc.h>
55 #include <dev/mpr/mpi/mpi2_cnfg.h>
56 #include <dev/mpr/mpi/mpi2_tool.h>
57 #include <dev/mpr/mpi/mpi2_pci.h>
58 
59 #include <sys/queue.h>
60 #include <sys/kthread.h>
61 #include <dev/mpr/mpr_ioctl.h>
62 #include <dev/mpr/mprvar.h>
63 
64 static int	mpr_pci_probe(device_t);
65 static int	mpr_pci_attach(device_t);
66 static int	mpr_pci_detach(device_t);
67 static int	mpr_pci_suspend(device_t);
68 static int	mpr_pci_resume(device_t);
69 static void	mpr_pci_free(struct mpr_softc *);
70 static int	mpr_alloc_msix(struct mpr_softc *sc, int msgs);
71 static int	mpr_alloc_msi(struct mpr_softc *sc, int msgs);
72 static int	mpr_pci_alloc_interrupts(struct mpr_softc *sc);
73 
74 static device_method_t mpr_methods[] = {
75 	DEVMETHOD(device_probe,		mpr_pci_probe),
76 	DEVMETHOD(device_attach,	mpr_pci_attach),
77 	DEVMETHOD(device_detach,	mpr_pci_detach),
78 	DEVMETHOD(device_suspend,	mpr_pci_suspend),
79 	DEVMETHOD(device_resume,	mpr_pci_resume),
80 	DEVMETHOD(bus_print_child,	bus_generic_print_child),
81 	DEVMETHOD(bus_driver_added,	bus_generic_driver_added),
82 	{ 0, 0 }
83 };
84 
85 static driver_t mpr_pci_driver = {
86 	"mpr",
87 	mpr_methods,
88 	sizeof(struct mpr_softc)
89 };
90 
91 struct mpr_ident {
92 	uint16_t	vendor;
93 	uint16_t	device;
94 	uint16_t	subvendor;
95 	uint16_t	subdevice;
96 	u_int		flags;
97 	const char	*desc;
98 } mpr_identifiers[] = {
99 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI25_MFGPAGE_DEVID_SAS3004,
100 	    0xffff, 0xffff, 0, "Avago Technologies (LSI) SAS3004" },
101 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI25_MFGPAGE_DEVID_SAS3008,
102 	    0xffff, 0xffff, 0, "Avago Technologies (LSI) SAS3008" },
103 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI25_MFGPAGE_DEVID_SAS3108_1,
104 	    0xffff, 0xffff, 0, "Avago Technologies (LSI) SAS3108_1" },
105 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI25_MFGPAGE_DEVID_SAS3108_2,
106 	    0xffff, 0xffff, 0, "Avago Technologies (LSI) SAS3108_2" },
107 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI25_MFGPAGE_DEVID_SAS3108_5,
108 	    0xffff, 0xffff, 0, "Avago Technologies (LSI) SAS3108_5" },
109 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI25_MFGPAGE_DEVID_SAS3108_6,
110 	    0xffff, 0xffff, 0, "Avago Technologies (LSI) SAS3108_6" },
111 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_SAS3216,
112 	    0xffff, 0xffff, 0, "Avago Technologies (LSI) SAS3216" },
113 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_SAS3224,
114 	    0xffff, 0xffff, 0, "Avago Technologies (LSI) SAS3224" },
115 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_SAS3316_1,
116 	    0xffff, 0xffff, 0, "Avago Technologies (LSI) SAS3316_1" },
117 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_SAS3316_2,
118 	    0xffff, 0xffff, 0, "Avago Technologies (LSI) SAS3316_2" },
119 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_SAS3324_1,
120 	    0xffff, 0xffff, 0, "Avago Technologies (LSI) SAS3324_1" },
121 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_SAS3324_2,
122 	    0xffff, 0xffff, 0, "Avago Technologies (LSI) SAS3324_2" },
123 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_SAS3408,
124 	    0xffff, 0xffff, MPR_FLAGS_GEN35_IOC,
125 	    "Avago Technologies (LSI) SAS3408" },
126 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_SAS3416,
127 	    0xffff, 0xffff, MPR_FLAGS_GEN35_IOC,
128 	    "Avago Technologies (LSI) SAS3416" },
129 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_SAS3508,
130 	    0xffff, 0xffff, MPR_FLAGS_GEN35_IOC,
131 	    "Avago Technologies (LSI) SAS3508" },
132 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_SAS3508_1,
133 	    0xffff, 0xffff, MPR_FLAGS_GEN35_IOC,
134 	    "Avago Technologies (LSI) SAS3508_1" },
135 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_SAS3516,
136 	    0xffff, 0xffff, MPR_FLAGS_GEN35_IOC,
137 	    "Avago Technologies (LSI) SAS3516" },
138 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_SAS3516_1,
139 	    0xffff, 0xffff, MPR_FLAGS_GEN35_IOC,
140 	    "Avago Technologies (LSI) SAS3516_1" },
141 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_SAS3616,
142 	    0xffff, 0xffff, MPR_FLAGS_GEN35_IOC,
143 	    "Avago Technologies (LSI) SAS3616" },
144 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_SAS3708,
145 	    0xffff, 0xffff, MPR_FLAGS_GEN35_IOC,
146 	    "Avago Technologies (LSI) SAS3708" },
147 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_SAS3716,
148 	    0xffff, 0xffff, MPR_FLAGS_GEN35_IOC,
149 	    "Avago Technologies (LSI) SAS3716" },
150 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_INVALID0_SAS3816,
151 	    0xffff, 0xffff, (MPR_FLAGS_GEN35_IOC | MPR_FLAGS_SEA_IOC),
152 	    "Broadcom Inc. (LSI) INVALID0 SAS3816" },
153 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_CFG_SEC_SAS3816,
154 	    0xffff, 0xffff, (MPR_FLAGS_GEN35_IOC | MPR_FLAGS_SEA_IOC),
155 	    "Broadcom Inc. (LSI) CFG SEC SAS3816" },
156 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_HARD_SEC_SAS3816,
157 	    0xffff, 0xffff, (MPR_FLAGS_GEN35_IOC | MPR_FLAGS_SEA_IOC),
158 	    "Broadcom Inc. (LSI) HARD SEC SAS3816" },
159 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_INVALID1_SAS3816,
160 	    0xffff, 0xffff, (MPR_FLAGS_GEN35_IOC | MPR_FLAGS_SEA_IOC),
161 	    "Broadcom Inc. (LSI) INVALID1 SAS3816" },
162 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_INVALID0_SAS3916,
163 	    0xffff, 0xffff, (MPR_FLAGS_GEN35_IOC | MPR_FLAGS_SEA_IOC),
164 	    "Broadcom Inc. (LSI) INVALID0 SAS3916" },
165 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_CFG_SEC_SAS3916,
166 	    0xffff, 0xffff, (MPR_FLAGS_GEN35_IOC | MPR_FLAGS_SEA_IOC),
167 	    "Broadcom Inc. (LSI) CFG SEC SAS3916" },
168 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_HARD_SEC_SAS3916,
169 	    0xffff, 0xffff, (MPR_FLAGS_GEN35_IOC | MPR_FLAGS_SEA_IOC),
170 	    "Broadcom Inc. (LSI) HARD SEC SAS3916" },
171 	{ MPI2_MFGPAGE_VENDORID_LSI, MPI26_MFGPAGE_DEVID_INVALID1_SAS3916,
172 	    0xffff, 0xffff, (MPR_FLAGS_GEN35_IOC | MPR_FLAGS_SEA_IOC),
173 	    "Broadcom Inc. (LSI) INVALID1 SAS3916" },
174 	{ 0, 0, 0, 0, 0, NULL }
175 };
176 
177 DRIVER_MODULE(mpr, pci, mpr_pci_driver, 0, 0);
178 MODULE_PNP_INFO("U16:vendor;U16:device;U16:subvendor;U16:subdevice;D:#", pci,
179     mpr, mpr_identifiers, nitems(mpr_identifiers) - 1);
180 
181 MODULE_DEPEND(mpr, cam, 1, 1, 1);
182 
183 static struct mpr_ident *
184 mpr_find_ident(device_t dev)
185 {
186 	struct mpr_ident *m;
187 
188 	for (m = mpr_identifiers; m->vendor != 0; m++) {
189 		if (m->vendor != pci_get_vendor(dev))
190 			continue;
191 		if (m->device != pci_get_device(dev))
192 			continue;
193 		if ((m->subvendor != 0xffff) &&
194 		    (m->subvendor != pci_get_subvendor(dev)))
195 			continue;
196 		if ((m->subdevice != 0xffff) &&
197 		    (m->subdevice != pci_get_subdevice(dev)))
198 			continue;
199 		return (m);
200 	}
201 
202 	return (NULL);
203 }
204 
205 static int
206 mpr_pci_probe(device_t dev)
207 {
208 	struct mpr_ident *id;
209 
210 	if ((id = mpr_find_ident(dev)) != NULL) {
211 		device_set_desc(dev, id->desc);
212 		return (BUS_PROBE_DEFAULT);
213 	}
214 	return (ENXIO);
215 }
216 
217 static int
218 mpr_pci_attach(device_t dev)
219 {
220 	bus_dma_template_t t;
221 	struct mpr_softc *sc;
222 	struct mpr_ident *m;
223 	int error, i;
224 
225 	sc = device_get_softc(dev);
226 	bzero(sc, sizeof(*sc));
227 	sc->mpr_dev = dev;
228 	m = mpr_find_ident(dev);
229 	sc->mpr_flags = m->flags;
230 
231 	switch (m->device) {
232 	case MPI26_MFGPAGE_DEVID_INVALID0_SAS3816:
233 	case MPI26_MFGPAGE_DEVID_INVALID1_SAS3816:
234 	case MPI26_MFGPAGE_DEVID_INVALID0_SAS3916:
235 	case MPI26_MFGPAGE_DEVID_INVALID1_SAS3916:
236 		mpr_printf(sc, "HBA is in Non Secure mode\n");
237 		return (ENXIO);
238 	case MPI26_MFGPAGE_DEVID_CFG_SEC_SAS3816:
239 	case MPI26_MFGPAGE_DEVID_CFG_SEC_SAS3916:
240 		mpr_printf(sc, "HBA is in Configurable Secure mode\n");
241 		break;
242 	default:
243 		break;
244 	}
245 
246 	mpr_get_tunables(sc);
247 
248 	/* Twiddle basic PCI config bits for a sanity check */
249 	pci_enable_busmaster(dev);
250 
251 	for (i = 0; i < PCI_MAXMAPS_0; i++) {
252 		sc->mpr_regs_rid = PCIR_BAR(i);
253 
254 		if ((sc->mpr_regs_resource = bus_alloc_resource_any(dev,
255 		    SYS_RES_MEMORY, &sc->mpr_regs_rid, RF_ACTIVE)) != NULL)
256 			break;
257 	}
258 
259 	if (sc->mpr_regs_resource == NULL) {
260 		mpr_printf(sc, "Cannot allocate PCI registers\n");
261 		return (ENXIO);
262 	}
263 
264 	sc->mpr_btag = rman_get_bustag(sc->mpr_regs_resource);
265 	sc->mpr_bhandle = rman_get_bushandle(sc->mpr_regs_resource);
266 
267 	/* Allocate the parent DMA tag */
268 	bus_dma_template_init(&t, bus_get_dma_tag(dev));
269 	if (bus_dma_template_tag(&t, &sc->mpr_parent_dmat)) {
270 		mpr_printf(sc, "Cannot allocate parent DMA tag\n");
271 		mpr_pci_free(sc);
272 		return (ENOMEM);
273 	}
274 
275 	if (((error = mpr_pci_alloc_interrupts(sc)) != 0) ||
276 	    ((error = mpr_attach(sc)) != 0))
277 		mpr_pci_free(sc);
278 
279 	return (error);
280 }
281 
282 /*
283  * Allocate, but don't assign interrupts early.  Doing it before requesting
284  * the IOCFacts message informs the firmware that we want to do MSI-X
285  * multiqueue.  We might not use all of the available messages, but there's
286  * no reason to re-alloc if we don't.
287  */
288 int
289 mpr_pci_alloc_interrupts(struct mpr_softc *sc)
290 {
291 	device_t dev;
292 	int error, msgs;
293 
294 	dev = sc->mpr_dev;
295 	error = 0;
296 	msgs = 0;
297 
298 	if (sc->disable_msix == 0) {
299 		msgs = pci_msix_count(dev);
300 		mpr_dprint(sc, MPR_INIT, "Counted %d MSI-X messages\n", msgs);
301 		msgs = min(msgs, sc->max_msix);
302 		msgs = min(msgs, MPR_MSIX_MAX);
303 		msgs = min(msgs, 1);	/* XXX */
304 		if (msgs != 0) {
305 			mpr_dprint(sc, MPR_INIT, "Attempting to allocate %d "
306 			    "MSI-X messages\n", msgs);
307 			error = mpr_alloc_msix(sc, msgs);
308 		}
309 	}
310 	if (((error != 0) || (msgs == 0)) && (sc->disable_msi == 0)) {
311 		msgs = pci_msi_count(dev);
312 		mpr_dprint(sc, MPR_INIT, "Counted %d MSI messages\n", msgs);
313 		msgs = min(msgs, MPR_MSI_MAX);
314 		if (msgs != 0) {
315 			mpr_dprint(sc, MPR_INIT, "Attempting to allocated %d "
316 			    "MSI messages\n", MPR_MSI_MAX);
317 			error = mpr_alloc_msi(sc, MPR_MSI_MAX);
318 		}
319 	}
320 	if ((error != 0) || (msgs == 0)) {
321 		/*
322 		 * If neither MSI or MSI-X are available, assume legacy INTx.
323 		 * This also implies that there will be only 1 queue.
324 		 */
325 		mpr_dprint(sc, MPR_INIT, "Falling back to legacy INTx\n");
326 		sc->mpr_flags |= MPR_FLAGS_INTX;
327 		msgs = 1;
328 	} else
329 		sc->mpr_flags |= MPR_FLAGS_MSI;
330 
331 	sc->msi_msgs = msgs;
332 	mpr_dprint(sc, MPR_INIT, "Allocated %d interrupts\n", msgs);
333 
334 	return (error);
335 }
336 
337 int
338 mpr_pci_setup_interrupts(struct mpr_softc *sc)
339 {
340 	device_t dev;
341 	struct mpr_queue *q;
342 	void *ihandler;
343 	int i, error, rid, initial_rid;
344 
345 	dev = sc->mpr_dev;
346 	error = ENXIO;
347 
348 	if (sc->mpr_flags & MPR_FLAGS_INTX) {
349 		initial_rid = 0;
350 		ihandler = mpr_intr;
351 	} else if (sc->mpr_flags & MPR_FLAGS_MSI) {
352 		initial_rid = 1;
353 		ihandler = mpr_intr_msi;
354 	} else {
355 		mpr_dprint(sc, MPR_ERROR|MPR_INIT,
356 		    "Unable to set up interrupts\n");
357 		return (EINVAL);
358 	}
359 
360 	for (i = 0; i < sc->msi_msgs; i++) {
361 		q = &sc->queues[i];
362 		rid = i + initial_rid;
363 		q->irq_rid = rid;
364 		q->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
365 		    &q->irq_rid, RF_ACTIVE);
366 		if (q->irq == NULL) {
367 			mpr_dprint(sc, MPR_ERROR|MPR_INIT,
368 			    "Cannot allocate interrupt RID %d\n", rid);
369 			sc->msi_msgs = i;
370 			break;
371 		}
372 		error = bus_setup_intr(dev, q->irq,
373 		    INTR_TYPE_BIO | INTR_MPSAFE, NULL, ihandler,
374 		    sc, &q->intrhand);
375 		if (error) {
376 			mpr_dprint(sc, MPR_ERROR|MPR_INIT,
377 			    "Cannot setup interrupt RID %d\n", rid);
378 			sc->msi_msgs = i;
379 			break;
380 		}
381 	}
382 
383         mpr_dprint(sc, MPR_INIT, "Set up %d interrupts\n", sc->msi_msgs);
384 	return (error);
385 }
386 
387 static int
388 mpr_pci_detach(device_t dev)
389 {
390 	struct mpr_softc *sc;
391 	int error;
392 
393 	sc = device_get_softc(dev);
394 
395 	if ((error = mpr_free(sc)) != 0)
396 		return (error);
397 
398 	mpr_pci_free(sc);
399 	return (0);
400 }
401 
402 void
403 mpr_pci_free_interrupts(struct mpr_softc *sc)
404 {
405 	struct mpr_queue *q;
406 	int i;
407 
408 	if (sc->queues == NULL)
409 		return;
410 
411 	for (i = 0; i < sc->msi_msgs; i++) {
412 		q = &sc->queues[i];
413 		if (q->irq != NULL) {
414 			bus_teardown_intr(sc->mpr_dev, q->irq,
415 			    q->intrhand);
416 			bus_release_resource(sc->mpr_dev, SYS_RES_IRQ,
417 			    q->irq_rid, q->irq);
418 		}
419 	}
420 }
421 
422 static void
423 mpr_pci_free(struct mpr_softc *sc)
424 {
425 
426 	if (sc->mpr_parent_dmat != NULL) {
427 		bus_dma_tag_destroy(sc->mpr_parent_dmat);
428 	}
429 
430 	mpr_pci_free_interrupts(sc);
431 
432 	if (sc->mpr_flags & MPR_FLAGS_MSI)
433 		pci_release_msi(sc->mpr_dev);
434 
435 	if (sc->mpr_regs_resource != NULL) {
436 		bus_release_resource(sc->mpr_dev, SYS_RES_MEMORY,
437 		    sc->mpr_regs_rid, sc->mpr_regs_resource);
438 	}
439 
440 	return;
441 }
442 
443 static int
444 mpr_pci_suspend(device_t dev)
445 {
446 	return (EINVAL);
447 }
448 
449 static int
450 mpr_pci_resume(device_t dev)
451 {
452 	return (EINVAL);
453 }
454 
455 static int
456 mpr_alloc_msix(struct mpr_softc *sc, int msgs)
457 {
458 	int error;
459 
460 	error = pci_alloc_msix(sc->mpr_dev, &msgs);
461 	return (error);
462 }
463 
464 static int
465 mpr_alloc_msi(struct mpr_softc *sc, int msgs)
466 {
467 	int error;
468 
469 	error = pci_alloc_msi(sc->mpr_dev, &msgs);
470 	return (error);
471 }
472 
473 int
474 mpr_pci_restore(struct mpr_softc *sc)
475 {
476 	struct pci_devinfo *dinfo;
477 
478 	mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
479 
480 	dinfo = device_get_ivars(sc->mpr_dev);
481 	if (dinfo == NULL) {
482 		mpr_dprint(sc, MPR_FAULT, "%s: NULL dinfo\n", __func__);
483 		return (EINVAL);
484 	}
485 
486 	pci_cfg_restore(sc->mpr_dev, dinfo);
487 	return (0);
488 }
489