xref: /freebsd/sys/dev/mpr/mpr.c (revision dc318a4ffabcbfa23bb56a33403aad36e6de30af)
1 /*-
2  * Copyright (c) 2009 Yahoo! Inc.
3  * Copyright (c) 2011-2015 LSI Corp.
4  * Copyright (c) 2013-2016 Avago Technologies
5  * Copyright 2000-2020 Broadcom Inc.
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following conditions
10  * are met:
11  * 1. Redistributions of source code must retain the above copyright
12  *    notice, this list of conditions and the following disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  *
29  * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD
30  *
31  */
32 
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
35 
36 /* Communications core for Avago Technologies (LSI) MPT3 */
37 
38 /* TODO Move headers to mprvar */
39 #include <sys/types.h>
40 #include <sys/param.h>
41 #include <sys/systm.h>
42 #include <sys/kernel.h>
43 #include <sys/selinfo.h>
44 #include <sys/lock.h>
45 #include <sys/mutex.h>
46 #include <sys/module.h>
47 #include <sys/bus.h>
48 #include <sys/conf.h>
49 #include <sys/bio.h>
50 #include <sys/malloc.h>
51 #include <sys/uio.h>
52 #include <sys/sysctl.h>
53 #include <sys/smp.h>
54 #include <sys/queue.h>
55 #include <sys/kthread.h>
56 #include <sys/taskqueue.h>
57 #include <sys/endian.h>
58 #include <sys/eventhandler.h>
59 #include <sys/sbuf.h>
60 #include <sys/priv.h>
61 
62 #include <machine/bus.h>
63 #include <machine/resource.h>
64 #include <sys/rman.h>
65 #include <sys/proc.h>
66 
67 #include <dev/pci/pcivar.h>
68 
69 #include <cam/cam.h>
70 #include <cam/cam_ccb.h>
71 #include <cam/scsi/scsi_all.h>
72 
73 #include <dev/mpr/mpi/mpi2_type.h>
74 #include <dev/mpr/mpi/mpi2.h>
75 #include <dev/mpr/mpi/mpi2_ioc.h>
76 #include <dev/mpr/mpi/mpi2_sas.h>
77 #include <dev/mpr/mpi/mpi2_pci.h>
78 #include <dev/mpr/mpi/mpi2_cnfg.h>
79 #include <dev/mpr/mpi/mpi2_init.h>
80 #include <dev/mpr/mpi/mpi2_tool.h>
81 #include <dev/mpr/mpr_ioctl.h>
82 #include <dev/mpr/mprvar.h>
83 #include <dev/mpr/mpr_table.h>
84 #include <dev/mpr/mpr_sas.h>
85 
86 static int mpr_diag_reset(struct mpr_softc *sc, int sleep_flag);
87 static int mpr_init_queues(struct mpr_softc *sc);
88 static void mpr_resize_queues(struct mpr_softc *sc);
89 static int mpr_message_unit_reset(struct mpr_softc *sc, int sleep_flag);
90 static int mpr_transition_operational(struct mpr_softc *sc);
91 static int mpr_iocfacts_allocate(struct mpr_softc *sc, uint8_t attaching);
92 static void mpr_iocfacts_free(struct mpr_softc *sc);
93 static void mpr_startup(void *arg);
94 static int mpr_send_iocinit(struct mpr_softc *sc);
95 static int mpr_alloc_queues(struct mpr_softc *sc);
96 static int mpr_alloc_hw_queues(struct mpr_softc *sc);
97 static int mpr_alloc_replies(struct mpr_softc *sc);
98 static int mpr_alloc_requests(struct mpr_softc *sc);
99 static int mpr_alloc_nvme_prp_pages(struct mpr_softc *sc);
100 static int mpr_attach_log(struct mpr_softc *sc);
101 static __inline void mpr_complete_command(struct mpr_softc *sc,
102     struct mpr_command *cm);
103 static void mpr_dispatch_event(struct mpr_softc *sc, uintptr_t data,
104     MPI2_EVENT_NOTIFICATION_REPLY *reply);
105 static void mpr_config_complete(struct mpr_softc *sc, struct mpr_command *cm);
106 static void mpr_periodic(void *);
107 static int mpr_reregister_events(struct mpr_softc *sc);
108 static void mpr_enqueue_request(struct mpr_softc *sc, struct mpr_command *cm);
109 static int mpr_get_iocfacts(struct mpr_softc *sc, MPI2_IOC_FACTS_REPLY *facts);
110 static int mpr_wait_db_ack(struct mpr_softc *sc, int timeout, int sleep_flag);
111 static int mpr_debug_sysctl(SYSCTL_HANDLER_ARGS);
112 static int mpr_dump_reqs(SYSCTL_HANDLER_ARGS);
113 static void mpr_parse_debug(struct mpr_softc *sc, char *list);
114 static void adjust_iocfacts_endianness(MPI2_IOC_FACTS_REPLY *facts);
115 
116 SYSCTL_NODE(_hw, OID_AUTO, mpr, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
117     "MPR Driver Parameters");
118 
119 MALLOC_DEFINE(M_MPR, "mpr", "mpr driver memory");
120 
121 /*
122  * Do a "Diagnostic Reset" aka a hard reset.  This should get the chip out of
123  * any state and back to its initialization state machine.
124  */
125 static char mpt2_reset_magic[] = { 0x00, 0x0f, 0x04, 0x0b, 0x02, 0x07, 0x0d };
126 
127 /*
128  * Added this union to smoothly convert le64toh cm->cm_desc.Words.
129  * Compiler only supports uint64_t to be passed as an argument.
130  * Otherwise it will throw this error:
131  * "aggregate value used where an integer was expected"
132  */
133 typedef union {
134         u64 word;
135         struct {
136                 u32 low;
137                 u32 high;
138         } u;
139 } request_descriptor_t;
140 
141 /* Rate limit chain-fail messages to 1 per minute */
142 static struct timeval mpr_chainfail_interval = { 60, 0 };
143 
144 /*
145  * sleep_flag can be either CAN_SLEEP or NO_SLEEP.
146  * If this function is called from process context, it can sleep
147  * and there is no harm to sleep, in case if this fuction is called
148  * from Interrupt handler, we can not sleep and need NO_SLEEP flag set.
149  * based on sleep flags driver will call either msleep, pause or DELAY.
150  * msleep and pause are of same variant, but pause is used when mpr_mtx
151  * is not hold by driver.
152  */
153 static int
154 mpr_diag_reset(struct mpr_softc *sc,int sleep_flag)
155 {
156 	uint32_t reg;
157 	int i, error, tries = 0;
158 	uint8_t first_wait_done = FALSE;
159 
160 	mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__);
161 
162 	/* Clear any pending interrupts */
163 	mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
164 
165 	/*
166 	 * Force NO_SLEEP for threads prohibited to sleep
167  	 * e.a Thread from interrupt handler are prohibited to sleep.
168  	 */
169 	if (curthread->td_no_sleeping)
170 		sleep_flag = NO_SLEEP;
171 
172 	mpr_dprint(sc, MPR_INIT, "sequence start, sleep_flag=%d\n", sleep_flag);
173 	/* Push the magic sequence */
174 	error = ETIMEDOUT;
175 	while (tries++ < 20) {
176 		for (i = 0; i < sizeof(mpt2_reset_magic); i++)
177 			mpr_regwrite(sc, MPI2_WRITE_SEQUENCE_OFFSET,
178 			    mpt2_reset_magic[i]);
179 
180 		/* wait 100 msec */
181 		if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP)
182 			msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0,
183 			    "mprdiag", hz/10);
184 		else if (sleep_flag == CAN_SLEEP)
185 			pause("mprdiag", hz/10);
186 		else
187 			DELAY(100 * 1000);
188 
189 		reg = mpr_regread(sc, MPI2_HOST_DIAGNOSTIC_OFFSET);
190 		if (reg & MPI2_DIAG_DIAG_WRITE_ENABLE) {
191 			error = 0;
192 			break;
193 		}
194 	}
195 	if (error) {
196 		mpr_dprint(sc, MPR_INIT, "sequence failed, error=%d, exit\n",
197 		    error);
198 		return (error);
199 	}
200 
201 	/* Send the actual reset.  XXX need to refresh the reg? */
202 	reg |= MPI2_DIAG_RESET_ADAPTER;
203 	mpr_dprint(sc, MPR_INIT, "sequence success, sending reset, reg= 0x%x\n",
204 	    reg);
205 	mpr_regwrite(sc, MPI2_HOST_DIAGNOSTIC_OFFSET, reg);
206 
207 	/* Wait up to 300 seconds in 50ms intervals */
208 	error = ETIMEDOUT;
209 	for (i = 0; i < 6000; i++) {
210 		/*
211 		 * Wait 50 msec. If this is the first time through, wait 256
212 		 * msec to satisfy Diag Reset timing requirements.
213 		 */
214 		if (first_wait_done) {
215 			if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP)
216 				msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0,
217 				    "mprdiag", hz/20);
218 			else if (sleep_flag == CAN_SLEEP)
219 				pause("mprdiag", hz/20);
220 			else
221 				DELAY(50 * 1000);
222 		} else {
223 			DELAY(256 * 1000);
224 			first_wait_done = TRUE;
225 		}
226 		/*
227 		 * Check for the RESET_ADAPTER bit to be cleared first, then
228 		 * wait for the RESET state to be cleared, which takes a little
229 		 * longer.
230 		 */
231 		reg = mpr_regread(sc, MPI2_HOST_DIAGNOSTIC_OFFSET);
232 		if (reg & MPI2_DIAG_RESET_ADAPTER) {
233 			continue;
234 		}
235 		reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET);
236 		if ((reg & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_RESET) {
237 			error = 0;
238 			break;
239 		}
240 	}
241 	if (error) {
242 		mpr_dprint(sc, MPR_INIT, "reset failed, error= %d, exit\n",
243 		    error);
244 		return (error);
245 	}
246 
247 	mpr_regwrite(sc, MPI2_WRITE_SEQUENCE_OFFSET, 0x0);
248 	mpr_dprint(sc, MPR_INIT, "diag reset success, exit\n");
249 
250 	return (0);
251 }
252 
253 static int
254 mpr_message_unit_reset(struct mpr_softc *sc, int sleep_flag)
255 {
256 	int error;
257 
258 	MPR_FUNCTRACE(sc);
259 
260 	mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__);
261 
262 	error = 0;
263 	mpr_regwrite(sc, MPI2_DOORBELL_OFFSET,
264 	    MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET <<
265 	    MPI2_DOORBELL_FUNCTION_SHIFT);
266 
267 	if (mpr_wait_db_ack(sc, 5, sleep_flag) != 0) {
268 		mpr_dprint(sc, MPR_INIT|MPR_FAULT,
269 		    "Doorbell handshake failed\n");
270 		error = ETIMEDOUT;
271 	}
272 
273 	mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__);
274 	return (error);
275 }
276 
277 static int
278 mpr_transition_ready(struct mpr_softc *sc)
279 {
280 	uint32_t reg, state;
281 	int error, tries = 0;
282 	int sleep_flags;
283 
284 	MPR_FUNCTRACE(sc);
285 	/* If we are in attach call, do not sleep */
286 	sleep_flags = (sc->mpr_flags & MPR_FLAGS_ATTACH_DONE)
287 	    ? CAN_SLEEP : NO_SLEEP;
288 
289 	error = 0;
290 
291 	mpr_dprint(sc, MPR_INIT, "%s entered, sleep_flags= %d\n",
292 	    __func__, sleep_flags);
293 
294 	while (tries++ < 1200) {
295 		reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET);
296 		mpr_dprint(sc, MPR_INIT, "  Doorbell= 0x%x\n", reg);
297 
298 		/*
299 		 * Ensure the IOC is ready to talk.  If it's not, try
300 		 * resetting it.
301 		 */
302 		if (reg & MPI2_DOORBELL_USED) {
303 			mpr_dprint(sc, MPR_INIT, "  Not ready, sending diag "
304 			    "reset\n");
305 			mpr_diag_reset(sc, sleep_flags);
306 			DELAY(50000);
307 			continue;
308 		}
309 
310 		/* Is the adapter owned by another peer? */
311 		if ((reg & MPI2_DOORBELL_WHO_INIT_MASK) ==
312 		    (MPI2_WHOINIT_PCI_PEER << MPI2_DOORBELL_WHO_INIT_SHIFT)) {
313 			mpr_dprint(sc, MPR_INIT|MPR_FAULT, "IOC is under the "
314 			    "control of another peer host, aborting "
315 			    "initialization.\n");
316 			error = ENXIO;
317 			break;
318 		}
319 
320 		state = reg & MPI2_IOC_STATE_MASK;
321 		if (state == MPI2_IOC_STATE_READY) {
322 			/* Ready to go! */
323 			error = 0;
324 			break;
325 		} else if (state == MPI2_IOC_STATE_FAULT) {
326 			mpr_dprint(sc, MPR_INIT|MPR_FAULT, "IOC in fault "
327 			    "state 0x%x, resetting\n",
328 			    state & MPI2_DOORBELL_FAULT_CODE_MASK);
329 			mpr_diag_reset(sc, sleep_flags);
330 		} else if (state == MPI2_IOC_STATE_OPERATIONAL) {
331 			/* Need to take ownership */
332 			mpr_message_unit_reset(sc, sleep_flags);
333 		} else if (state == MPI2_IOC_STATE_RESET) {
334 			/* Wait a bit, IOC might be in transition */
335 			mpr_dprint(sc, MPR_INIT|MPR_FAULT,
336 			    "IOC in unexpected reset state\n");
337 		} else {
338 			mpr_dprint(sc, MPR_INIT|MPR_FAULT,
339 			    "IOC in unknown state 0x%x\n", state);
340 			error = EINVAL;
341 			break;
342 		}
343 
344 		/* Wait 50ms for things to settle down. */
345 		DELAY(50000);
346 	}
347 
348 	if (error)
349 		mpr_dprint(sc, MPR_INIT|MPR_FAULT,
350 		    "Cannot transition IOC to ready\n");
351 	mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__);
352 	return (error);
353 }
354 
355 static int
356 mpr_transition_operational(struct mpr_softc *sc)
357 {
358 	uint32_t reg, state;
359 	int error;
360 
361 	MPR_FUNCTRACE(sc);
362 
363 	error = 0;
364 	reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET);
365 	mpr_dprint(sc, MPR_INIT, "%s entered, Doorbell= 0x%x\n", __func__, reg);
366 
367 	state = reg & MPI2_IOC_STATE_MASK;
368 	if (state != MPI2_IOC_STATE_READY) {
369 		mpr_dprint(sc, MPR_INIT, "IOC not ready\n");
370 		if ((error = mpr_transition_ready(sc)) != 0) {
371 			mpr_dprint(sc, MPR_INIT|MPR_FAULT,
372 			    "failed to transition ready, exit\n");
373 			return (error);
374 		}
375 	}
376 
377 	error = mpr_send_iocinit(sc);
378 	mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__);
379 
380 	return (error);
381 }
382 
383 static void
384 mpr_resize_queues(struct mpr_softc *sc)
385 {
386 	u_int reqcr, prireqcr, maxio, sges_per_frame, chain_seg_size;
387 
388 	/*
389 	 * Size the queues. Since the reply queues always need one free
390 	 * entry, we'll deduct one reply message here.  The LSI documents
391 	 * suggest instead to add a count to the request queue, but I think
392 	 * that it's better to deduct from reply queue.
393 	 */
394 	prireqcr = MAX(1, sc->max_prireqframes);
395 	prireqcr = MIN(prireqcr, sc->facts->HighPriorityCredit);
396 
397 	reqcr = MAX(2, sc->max_reqframes);
398 	reqcr = MIN(reqcr, sc->facts->RequestCredit);
399 
400 	sc->num_reqs = prireqcr + reqcr;
401 	sc->num_prireqs = prireqcr;
402 	sc->num_replies = MIN(sc->max_replyframes + sc->max_evtframes,
403 	    sc->facts->MaxReplyDescriptorPostQueueDepth) - 1;
404 
405 	/* Store the request frame size in bytes rather than as 32bit words */
406 	sc->reqframesz = sc->facts->IOCRequestFrameSize * 4;
407 
408 	/*
409 	 * Gen3 and beyond uses the IOCMaxChainSegmentSize from IOC Facts to
410 	 * get the size of a Chain Frame.  Previous versions use the size as a
411 	 * Request Frame for the Chain Frame size.  If IOCMaxChainSegmentSize
412 	 * is 0, use the default value.  The IOCMaxChainSegmentSize is the
413 	 * number of 16-byte elelements that can fit in a Chain Frame, which is
414 	 * the size of an IEEE Simple SGE.
415 	 */
416 	if (sc->facts->MsgVersion >= MPI2_VERSION_02_05) {
417 		chain_seg_size = sc->facts->IOCMaxChainSegmentSize;
418 		if (chain_seg_size == 0)
419 			chain_seg_size = MPR_DEFAULT_CHAIN_SEG_SIZE;
420 		sc->chain_frame_size = chain_seg_size *
421 		    MPR_MAX_CHAIN_ELEMENT_SIZE;
422 	} else {
423 		sc->chain_frame_size = sc->reqframesz;
424 	}
425 
426 	/*
427 	 * Max IO Size is Page Size * the following:
428 	 * ((SGEs per frame - 1 for chain element) * Max Chain Depth)
429 	 * + 1 for no chain needed in last frame
430 	 *
431 	 * If user suggests a Max IO size to use, use the smaller of the
432 	 * user's value and the calculated value as long as the user's
433 	 * value is larger than 0. The user's value is in pages.
434 	 */
435 	sges_per_frame = sc->chain_frame_size/sizeof(MPI2_IEEE_SGE_SIMPLE64)-1;
436 	maxio = (sges_per_frame * sc->facts->MaxChainDepth + 1) * PAGE_SIZE;
437 
438 	/*
439 	 * If I/O size limitation requested then use it and pass up to CAM.
440 	 * If not, use maxphys as an optimization hint, but report HW limit.
441 	 */
442 	if (sc->max_io_pages > 0) {
443 		maxio = min(maxio, sc->max_io_pages * PAGE_SIZE);
444 		sc->maxio = maxio;
445 	} else {
446 		sc->maxio = maxio;
447 		maxio = min(maxio, maxphys);
448 	}
449 
450 	sc->num_chains = (maxio / PAGE_SIZE + sges_per_frame - 2) /
451 	    sges_per_frame * reqcr;
452 	if (sc->max_chains > 0 && sc->max_chains < sc->num_chains)
453 		sc->num_chains = sc->max_chains;
454 
455 	/*
456 	 * Figure out the number of MSIx-based queues.  If the firmware or
457 	 * user has done something crazy and not allowed enough credit for
458 	 * the queues to be useful then don't enable multi-queue.
459 	 */
460 	if (sc->facts->MaxMSIxVectors < 2)
461 		sc->msi_msgs = 1;
462 
463 	if (sc->msi_msgs > 1) {
464 		sc->msi_msgs = MIN(sc->msi_msgs, mp_ncpus);
465 		sc->msi_msgs = MIN(sc->msi_msgs, sc->facts->MaxMSIxVectors);
466 		if (sc->num_reqs / sc->msi_msgs < 2)
467 			sc->msi_msgs = 1;
468 	}
469 
470 	mpr_dprint(sc, MPR_INIT, "Sized queues to q=%d reqs=%d replies=%d\n",
471 	    sc->msi_msgs, sc->num_reqs, sc->num_replies);
472 }
473 
474 /*
475  * This is called during attach and when re-initializing due to a Diag Reset.
476  * IOC Facts is used to allocate many of the structures needed by the driver.
477  * If called from attach, de-allocation is not required because the driver has
478  * not allocated any structures yet, but if called from a Diag Reset, previously
479  * allocated structures based on IOC Facts will need to be freed and re-
480  * allocated bases on the latest IOC Facts.
481  */
482 static int
483 mpr_iocfacts_allocate(struct mpr_softc *sc, uint8_t attaching)
484 {
485 	int error;
486 	Mpi2IOCFactsReply_t saved_facts;
487 	uint8_t saved_mode, reallocating;
488 
489 	mpr_dprint(sc, MPR_INIT|MPR_TRACE, "%s entered\n", __func__);
490 
491 	/* Save old IOC Facts and then only reallocate if Facts have changed */
492 	if (!attaching) {
493 		bcopy(sc->facts, &saved_facts, sizeof(MPI2_IOC_FACTS_REPLY));
494 	}
495 
496 	/*
497 	 * Get IOC Facts.  In all cases throughout this function, panic if doing
498 	 * a re-initialization and only return the error if attaching so the OS
499 	 * can handle it.
500 	 */
501 	if ((error = mpr_get_iocfacts(sc, sc->facts)) != 0) {
502 		if (attaching) {
503 			mpr_dprint(sc, MPR_INIT|MPR_FAULT, "Failed to get "
504 			    "IOC Facts with error %d, exit\n", error);
505 			return (error);
506 		} else {
507 			panic("%s failed to get IOC Facts with error %d\n",
508 			    __func__, error);
509 		}
510 	}
511 
512 	MPR_DPRINT_PAGE(sc, MPR_XINFO, iocfacts, sc->facts);
513 
514 	snprintf(sc->fw_version, sizeof(sc->fw_version),
515 	    "%02d.%02d.%02d.%02d",
516 	    sc->facts->FWVersion.Struct.Major,
517 	    sc->facts->FWVersion.Struct.Minor,
518 	    sc->facts->FWVersion.Struct.Unit,
519 	    sc->facts->FWVersion.Struct.Dev);
520 
521 	snprintf(sc->msg_version, sizeof(sc->msg_version), "%d.%d",
522 	    (sc->facts->MsgVersion & MPI2_IOCFACTS_MSGVERSION_MAJOR_MASK) >>
523 	    MPI2_IOCFACTS_MSGVERSION_MAJOR_SHIFT,
524 	    (sc->facts->MsgVersion & MPI2_IOCFACTS_MSGVERSION_MINOR_MASK) >>
525 	    MPI2_IOCFACTS_MSGVERSION_MINOR_SHIFT);
526 
527 	mpr_dprint(sc, MPR_INFO, "Firmware: %s, Driver: %s\n", sc->fw_version,
528 	    MPR_DRIVER_VERSION);
529 	mpr_dprint(sc, MPR_INFO,
530 	    "IOCCapabilities: %b\n", sc->facts->IOCCapabilities,
531 	    "\20" "\3ScsiTaskFull" "\4DiagTrace" "\5SnapBuf" "\6ExtBuf"
532 	    "\7EEDP" "\10BiDirTarg" "\11Multicast" "\14TransRetry" "\15IR"
533 	    "\16EventReplay" "\17RaidAccel" "\20MSIXIndex" "\21HostDisc"
534 	    "\22FastPath" "\23RDPQArray" "\24AtomicReqDesc" "\25PCIeSRIOV");
535 
536 	/*
537 	 * If the chip doesn't support event replay then a hard reset will be
538 	 * required to trigger a full discovery.  Do the reset here then
539 	 * retransition to Ready.  A hard reset might have already been done,
540 	 * but it doesn't hurt to do it again.  Only do this if attaching, not
541 	 * for a Diag Reset.
542 	 */
543 	if (attaching && ((sc->facts->IOCCapabilities &
544 	    MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY) == 0)) {
545 		mpr_dprint(sc, MPR_INIT, "No event replay, resetting\n");
546 		mpr_diag_reset(sc, NO_SLEEP);
547 		if ((error = mpr_transition_ready(sc)) != 0) {
548 			mpr_dprint(sc, MPR_INIT|MPR_FAULT, "Failed to "
549 			    "transition to ready with error %d, exit\n",
550 			    error);
551 			return (error);
552 		}
553 	}
554 
555 	/*
556 	 * Set flag if IR Firmware is loaded.  If the RAID Capability has
557 	 * changed from the previous IOC Facts, log a warning, but only if
558 	 * checking this after a Diag Reset and not during attach.
559 	 */
560 	saved_mode = sc->ir_firmware;
561 	if (sc->facts->IOCCapabilities &
562 	    MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID)
563 		sc->ir_firmware = 1;
564 	if (!attaching) {
565 		if (sc->ir_firmware != saved_mode) {
566 			mpr_dprint(sc, MPR_INIT|MPR_FAULT, "new IR/IT mode "
567 			    "in IOC Facts does not match previous mode\n");
568 		}
569 	}
570 
571 	/* Only deallocate and reallocate if relevant IOC Facts have changed */
572 	reallocating = FALSE;
573 	sc->mpr_flags &= ~MPR_FLAGS_REALLOCATED;
574 
575 	if ((!attaching) &&
576 	    ((saved_facts.MsgVersion != sc->facts->MsgVersion) ||
577 	    (saved_facts.HeaderVersion != sc->facts->HeaderVersion) ||
578 	    (saved_facts.MaxChainDepth != sc->facts->MaxChainDepth) ||
579 	    (saved_facts.RequestCredit != sc->facts->RequestCredit) ||
580 	    (saved_facts.ProductID != sc->facts->ProductID) ||
581 	    (saved_facts.IOCCapabilities != sc->facts->IOCCapabilities) ||
582 	    (saved_facts.IOCRequestFrameSize !=
583 	    sc->facts->IOCRequestFrameSize) ||
584 	    (saved_facts.IOCMaxChainSegmentSize !=
585 	    sc->facts->IOCMaxChainSegmentSize) ||
586 	    (saved_facts.MaxTargets != sc->facts->MaxTargets) ||
587 	    (saved_facts.MaxSasExpanders != sc->facts->MaxSasExpanders) ||
588 	    (saved_facts.MaxEnclosures != sc->facts->MaxEnclosures) ||
589 	    (saved_facts.HighPriorityCredit != sc->facts->HighPriorityCredit) ||
590 	    (saved_facts.MaxReplyDescriptorPostQueueDepth !=
591 	    sc->facts->MaxReplyDescriptorPostQueueDepth) ||
592 	    (saved_facts.ReplyFrameSize != sc->facts->ReplyFrameSize) ||
593 	    (saved_facts.MaxVolumes != sc->facts->MaxVolumes) ||
594 	    (saved_facts.MaxPersistentEntries !=
595 	    sc->facts->MaxPersistentEntries))) {
596 		reallocating = TRUE;
597 
598 		/* Record that we reallocated everything */
599 		sc->mpr_flags |= MPR_FLAGS_REALLOCATED;
600 	}
601 
602 	/*
603 	 * Some things should be done if attaching or re-allocating after a Diag
604 	 * Reset, but are not needed after a Diag Reset if the FW has not
605 	 * changed.
606 	 */
607 	if (attaching || reallocating) {
608 		/*
609 		 * Check if controller supports FW diag buffers and set flag to
610 		 * enable each type.
611 		 */
612 		if (sc->facts->IOCCapabilities &
613 		    MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER)
614 			sc->fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_TRACE].
615 			    enabled = TRUE;
616 		if (sc->facts->IOCCapabilities &
617 		    MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER)
618 			sc->fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_SNAPSHOT].
619 			    enabled = TRUE;
620 		if (sc->facts->IOCCapabilities &
621 		    MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER)
622 			sc->fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_EXTENDED].
623 			    enabled = TRUE;
624 
625 		/*
626 		 * Set flags for some supported items.
627 		 */
628 		if (sc->facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP)
629 			sc->eedp_enabled = TRUE;
630 		if (sc->facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR)
631 			sc->control_TLR = TRUE;
632 		if ((sc->facts->IOCCapabilities &
633 		    MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ) &&
634 		    (sc->mpr_flags & MPR_FLAGS_SEA_IOC))
635 			sc->atomic_desc_capable = TRUE;
636 
637 		mpr_resize_queues(sc);
638 
639 		/*
640 		 * Initialize all Tail Queues
641 		 */
642 		TAILQ_INIT(&sc->req_list);
643 		TAILQ_INIT(&sc->high_priority_req_list);
644 		TAILQ_INIT(&sc->chain_list);
645 		TAILQ_INIT(&sc->prp_page_list);
646 		TAILQ_INIT(&sc->tm_list);
647 	}
648 
649 	/*
650 	 * If doing a Diag Reset and the FW is significantly different
651 	 * (reallocating will be set above in IOC Facts comparison), then all
652 	 * buffers based on the IOC Facts will need to be freed before they are
653 	 * reallocated.
654 	 */
655 	if (reallocating) {
656 		mpr_iocfacts_free(sc);
657 		mprsas_realloc_targets(sc, saved_facts.MaxTargets +
658 		    saved_facts.MaxVolumes);
659 	}
660 
661 	/*
662 	 * Any deallocation has been completed.  Now start reallocating
663 	 * if needed.  Will only need to reallocate if attaching or if the new
664 	 * IOC Facts are different from the previous IOC Facts after a Diag
665 	 * Reset. Targets have already been allocated above if needed.
666 	 */
667 	error = 0;
668 	while (attaching || reallocating) {
669 		if ((error = mpr_alloc_hw_queues(sc)) != 0)
670 			break;
671 		if ((error = mpr_alloc_replies(sc)) != 0)
672 			break;
673 		if ((error = mpr_alloc_requests(sc)) != 0)
674 			break;
675 		if ((error = mpr_alloc_queues(sc)) != 0)
676 			break;
677 		break;
678 	}
679 	if (error) {
680 		mpr_dprint(sc, MPR_INIT|MPR_ERROR,
681 		    "Failed to alloc queues with error %d\n", error);
682 		mpr_free(sc);
683 		return (error);
684 	}
685 
686 	/* Always initialize the queues */
687 	bzero(sc->free_queue, sc->fqdepth * 4);
688 	mpr_init_queues(sc);
689 
690 	/*
691 	 * Always get the chip out of the reset state, but only panic if not
692 	 * attaching.  If attaching and there is an error, that is handled by
693 	 * the OS.
694 	 */
695 	error = mpr_transition_operational(sc);
696 	if (error != 0) {
697 		mpr_dprint(sc, MPR_INIT|MPR_FAULT, "Failed to "
698 		    "transition to operational with error %d\n", error);
699 		mpr_free(sc);
700 		return (error);
701 	}
702 
703 	/*
704 	 * Finish the queue initialization.
705 	 * These are set here instead of in mpr_init_queues() because the
706 	 * IOC resets these values during the state transition in
707 	 * mpr_transition_operational().  The free index is set to 1
708 	 * because the corresponding index in the IOC is set to 0, and the
709 	 * IOC treats the queues as full if both are set to the same value.
710 	 * Hence the reason that the queue can't hold all of the possible
711 	 * replies.
712 	 */
713 	sc->replypostindex = 0;
714 	mpr_regwrite(sc, MPI2_REPLY_FREE_HOST_INDEX_OFFSET, sc->replyfreeindex);
715 	mpr_regwrite(sc, MPI2_REPLY_POST_HOST_INDEX_OFFSET, 0);
716 
717 	/*
718 	 * Attach the subsystems so they can prepare their event masks.
719 	 * XXX Should be dynamic so that IM/IR and user modules can attach
720 	 */
721 	error = 0;
722 	while (attaching) {
723 		mpr_dprint(sc, MPR_INIT, "Attaching subsystems\n");
724 		if ((error = mpr_attach_log(sc)) != 0)
725 			break;
726 		if ((error = mpr_attach_sas(sc)) != 0)
727 			break;
728 		if ((error = mpr_attach_user(sc)) != 0)
729 			break;
730 		break;
731 	}
732 	if (error) {
733 		mpr_dprint(sc, MPR_INIT|MPR_ERROR,
734 		    "Failed to attach all subsystems: error %d\n", error);
735 		mpr_free(sc);
736 		return (error);
737 	}
738 
739 	/*
740 	 * XXX If the number of MSI-X vectors changes during re-init, this
741 	 * won't see it and adjust.
742 	 */
743 	if (attaching && (error = mpr_pci_setup_interrupts(sc)) != 0) {
744 		mpr_dprint(sc, MPR_INIT|MPR_ERROR,
745 		    "Failed to setup interrupts\n");
746 		mpr_free(sc);
747 		return (error);
748 	}
749 
750 	return (error);
751 }
752 
753 /*
754  * This is called if memory is being free (during detach for example) and when
755  * buffers need to be reallocated due to a Diag Reset.
756  */
757 static void
758 mpr_iocfacts_free(struct mpr_softc *sc)
759 {
760 	struct mpr_command *cm;
761 	int i;
762 
763 	mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
764 
765 	if (sc->free_busaddr != 0)
766 		bus_dmamap_unload(sc->queues_dmat, sc->queues_map);
767 	if (sc->free_queue != NULL)
768 		bus_dmamem_free(sc->queues_dmat, sc->free_queue,
769 		    sc->queues_map);
770 	if (sc->queues_dmat != NULL)
771 		bus_dma_tag_destroy(sc->queues_dmat);
772 
773 	if (sc->chain_frames != NULL) {
774 		bus_dmamap_unload(sc->chain_dmat, sc->chain_map);
775 		bus_dmamem_free(sc->chain_dmat, sc->chain_frames,
776 		    sc->chain_map);
777 	}
778 	if (sc->chain_dmat != NULL)
779 		bus_dma_tag_destroy(sc->chain_dmat);
780 
781 	if (sc->sense_busaddr != 0)
782 		bus_dmamap_unload(sc->sense_dmat, sc->sense_map);
783 	if (sc->sense_frames != NULL)
784 		bus_dmamem_free(sc->sense_dmat, sc->sense_frames,
785 		    sc->sense_map);
786 	if (sc->sense_dmat != NULL)
787 		bus_dma_tag_destroy(sc->sense_dmat);
788 
789 	if (sc->prp_page_busaddr != 0)
790 		bus_dmamap_unload(sc->prp_page_dmat, sc->prp_page_map);
791 	if (sc->prp_pages != NULL)
792 		bus_dmamem_free(sc->prp_page_dmat, sc->prp_pages,
793 		    sc->prp_page_map);
794 	if (sc->prp_page_dmat != NULL)
795 		bus_dma_tag_destroy(sc->prp_page_dmat);
796 
797 	if (sc->reply_busaddr != 0)
798 		bus_dmamap_unload(sc->reply_dmat, sc->reply_map);
799 	if (sc->reply_frames != NULL)
800 		bus_dmamem_free(sc->reply_dmat, sc->reply_frames,
801 		    sc->reply_map);
802 	if (sc->reply_dmat != NULL)
803 		bus_dma_tag_destroy(sc->reply_dmat);
804 
805 	if (sc->req_busaddr != 0)
806 		bus_dmamap_unload(sc->req_dmat, sc->req_map);
807 	if (sc->req_frames != NULL)
808 		bus_dmamem_free(sc->req_dmat, sc->req_frames, sc->req_map);
809 	if (sc->req_dmat != NULL)
810 		bus_dma_tag_destroy(sc->req_dmat);
811 
812 	if (sc->chains != NULL)
813 		free(sc->chains, M_MPR);
814 	if (sc->prps != NULL)
815 		free(sc->prps, M_MPR);
816 	if (sc->commands != NULL) {
817 		for (i = 1; i < sc->num_reqs; i++) {
818 			cm = &sc->commands[i];
819 			bus_dmamap_destroy(sc->buffer_dmat, cm->cm_dmamap);
820 		}
821 		free(sc->commands, M_MPR);
822 	}
823 	if (sc->buffer_dmat != NULL)
824 		bus_dma_tag_destroy(sc->buffer_dmat);
825 
826 	mpr_pci_free_interrupts(sc);
827 	free(sc->queues, M_MPR);
828 	sc->queues = NULL;
829 }
830 
831 /*
832  * The terms diag reset and hard reset are used interchangeably in the MPI
833  * docs to mean resetting the controller chip.  In this code diag reset
834  * cleans everything up, and the hard reset function just sends the reset
835  * sequence to the chip.  This should probably be refactored so that every
836  * subsystem gets a reset notification of some sort, and can clean up
837  * appropriately.
838  */
839 int
840 mpr_reinit(struct mpr_softc *sc)
841 {
842 	int error;
843 	struct mprsas_softc *sassc;
844 
845 	sassc = sc->sassc;
846 
847 	MPR_FUNCTRACE(sc);
848 
849 	mtx_assert(&sc->mpr_mtx, MA_OWNED);
850 
851 	mpr_dprint(sc, MPR_INIT|MPR_INFO, "Reinitializing controller\n");
852 	if (sc->mpr_flags & MPR_FLAGS_DIAGRESET) {
853 		mpr_dprint(sc, MPR_INIT, "Reset already in progress\n");
854 		return 0;
855 	}
856 
857 	/*
858 	 * Make sure the completion callbacks can recognize they're getting
859 	 * a NULL cm_reply due to a reset.
860 	 */
861 	sc->mpr_flags |= MPR_FLAGS_DIAGRESET;
862 
863 	/*
864 	 * Mask interrupts here.
865 	 */
866 	mpr_dprint(sc, MPR_INIT, "Masking interrupts and resetting\n");
867 	mpr_mask_intr(sc);
868 
869 	error = mpr_diag_reset(sc, CAN_SLEEP);
870 	if (error != 0) {
871 		panic("%s hard reset failed with error %d\n", __func__, error);
872 	}
873 
874 	/* Restore the PCI state, including the MSI-X registers */
875 	mpr_pci_restore(sc);
876 
877 	/* Give the I/O subsystem special priority to get itself prepared */
878 	mprsas_handle_reinit(sc);
879 
880 	/*
881 	 * Get IOC Facts and allocate all structures based on this information.
882 	 * The attach function will also call mpr_iocfacts_allocate at startup.
883 	 * If relevant values have changed in IOC Facts, this function will free
884 	 * all of the memory based on IOC Facts and reallocate that memory.
885 	 */
886 	if ((error = mpr_iocfacts_allocate(sc, FALSE)) != 0) {
887 		panic("%s IOC Facts based allocation failed with error %d\n",
888 		    __func__, error);
889 	}
890 
891 	/*
892 	 * Mapping structures will be re-allocated after getting IOC Page8, so
893 	 * free these structures here.
894 	 */
895 	mpr_mapping_exit(sc);
896 
897 	/*
898 	 * The static page function currently read is IOC Page8.  Others can be
899 	 * added in future.  It's possible that the values in IOC Page8 have
900 	 * changed after a Diag Reset due to user modification, so always read
901 	 * these.  Interrupts are masked, so unmask them before getting config
902 	 * pages.
903 	 */
904 	mpr_unmask_intr(sc);
905 	sc->mpr_flags &= ~MPR_FLAGS_DIAGRESET;
906 	mpr_base_static_config_pages(sc);
907 
908 	/*
909 	 * Some mapping info is based in IOC Page8 data, so re-initialize the
910 	 * mapping tables.
911 	 */
912 	mpr_mapping_initialize(sc);
913 
914 	/*
915 	 * Restart will reload the event masks clobbered by the reset, and
916 	 * then enable the port.
917 	 */
918 	mpr_reregister_events(sc);
919 
920 	/* the end of discovery will release the simq, so we're done. */
921 	mpr_dprint(sc, MPR_INIT|MPR_XINFO, "Finished sc %p post %u free %u\n",
922 	    sc, sc->replypostindex, sc->replyfreeindex);
923 	mprsas_release_simq_reinit(sassc);
924 	mpr_dprint(sc, MPR_INIT, "%s exit error= %d\n", __func__, error);
925 
926 	return 0;
927 }
928 
929 /* Wait for the chip to ACK a word that we've put into its FIFO
930  * Wait for <timeout> seconds. In single loop wait for busy loop
931  * for 500 microseconds.
932  * Total is [ 0.5 * (2000 * <timeout>) ] in miliseconds.
933  * */
934 static int
935 mpr_wait_db_ack(struct mpr_softc *sc, int timeout, int sleep_flag)
936 {
937 	u32 cntdn, count;
938 	u32 int_status;
939 	u32 doorbell;
940 
941 	count = 0;
942 	cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout;
943 	do {
944 		int_status = mpr_regread(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET);
945 		if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) {
946 			mpr_dprint(sc, MPR_TRACE, "%s: successful count(%d), "
947 			    "timeout(%d)\n", __func__, count, timeout);
948 			return 0;
949 		} else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) {
950 			doorbell = mpr_regread(sc, MPI2_DOORBELL_OFFSET);
951 			if ((doorbell & MPI2_IOC_STATE_MASK) ==
952 			    MPI2_IOC_STATE_FAULT) {
953 				mpr_dprint(sc, MPR_FAULT,
954 				    "fault_state(0x%04x)!\n", doorbell);
955 				return (EFAULT);
956 			}
957 		} else if (int_status == 0xFFFFFFFF)
958 			goto out;
959 
960 		/*
961 		 * If it can sleep, sleep for 1 milisecond, else busy loop for
962  		 * 0.5 milisecond
963 		 */
964 		if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP)
965 			msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0, "mprdba",
966 			    hz/1000);
967 		else if (sleep_flag == CAN_SLEEP)
968 			pause("mprdba", hz/1000);
969 		else
970 			DELAY(500);
971 		count++;
972 	} while (--cntdn);
973 
974 out:
975 	mpr_dprint(sc, MPR_FAULT, "%s: failed due to timeout count(%d), "
976 		"int_status(%x)!\n", __func__, count, int_status);
977 	return (ETIMEDOUT);
978 }
979 
980 /* Wait for the chip to signal that the next word in its FIFO can be fetched */
981 static int
982 mpr_wait_db_int(struct mpr_softc *sc)
983 {
984 	int retry;
985 
986 	for (retry = 0; retry < MPR_DB_MAX_WAIT; retry++) {
987 		if ((mpr_regread(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET) &
988 		    MPI2_HIS_IOC2SYS_DB_STATUS) != 0)
989 			return (0);
990 		DELAY(2000);
991 	}
992 	return (ETIMEDOUT);
993 }
994 
995 /* Step through the synchronous command state machine, i.e. "Doorbell mode" */
996 static int
997 mpr_request_sync(struct mpr_softc *sc, void *req, MPI2_DEFAULT_REPLY *reply,
998     int req_sz, int reply_sz, int timeout)
999 {
1000 	uint32_t *data32;
1001 	uint16_t *data16;
1002 	int i, count, ioc_sz, residual;
1003 	int sleep_flags = CAN_SLEEP;
1004 
1005 	if (curthread->td_no_sleeping)
1006 		sleep_flags = NO_SLEEP;
1007 
1008 	/* Step 1 */
1009 	mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
1010 
1011 	/* Step 2 */
1012 	if (mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_USED)
1013 		return (EBUSY);
1014 
1015 	/* Step 3
1016 	 * Announce that a message is coming through the doorbell.  Messages
1017 	 * are pushed at 32bit words, so round up if needed.
1018 	 */
1019 	count = (req_sz + 3) / 4;
1020 	mpr_regwrite(sc, MPI2_DOORBELL_OFFSET,
1021 	    (MPI2_FUNCTION_HANDSHAKE << MPI2_DOORBELL_FUNCTION_SHIFT) |
1022 	    (count << MPI2_DOORBELL_ADD_DWORDS_SHIFT));
1023 
1024 	/* Step 4 */
1025 	if (mpr_wait_db_int(sc) ||
1026 	    (mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_USED) == 0) {
1027 		mpr_dprint(sc, MPR_FAULT, "Doorbell failed to activate\n");
1028 		return (ENXIO);
1029 	}
1030 	mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
1031 	if (mpr_wait_db_ack(sc, 5, sleep_flags) != 0) {
1032 		mpr_dprint(sc, MPR_FAULT, "Doorbell handshake failed\n");
1033 		return (ENXIO);
1034 	}
1035 
1036 	/* Step 5 */
1037 	/* Clock out the message data synchronously in 32-bit dwords*/
1038 	data32 = (uint32_t *)req;
1039 	for (i = 0; i < count; i++) {
1040 		mpr_regwrite(sc, MPI2_DOORBELL_OFFSET, htole32(data32[i]));
1041 		if (mpr_wait_db_ack(sc, 5, sleep_flags) != 0) {
1042 			mpr_dprint(sc, MPR_FAULT,
1043 			    "Timeout while writing doorbell\n");
1044 			return (ENXIO);
1045 		}
1046 	}
1047 
1048 	/* Step 6 */
1049 	/* Clock in the reply in 16-bit words.  The total length of the
1050 	 * message is always in the 4th byte, so clock out the first 2 words
1051 	 * manually, then loop the rest.
1052 	 */
1053 	data16 = (uint16_t *)reply;
1054 	if (mpr_wait_db_int(sc) != 0) {
1055 		mpr_dprint(sc, MPR_FAULT, "Timeout reading doorbell 0\n");
1056 		return (ENXIO);
1057 	}
1058 
1059 	/*
1060 	 * If in a BE platform, swap bytes using le16toh to not
1061 	 * disturb 8 bit field neighbors in destination structure
1062 	 * pointed by data16.
1063 	 */
1064 	data16[0] =
1065 	    le16toh(mpr_regread(sc, MPI2_DOORBELL_OFFSET)) & MPI2_DOORBELL_DATA_MASK;
1066 	mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
1067 	if (mpr_wait_db_int(sc) != 0) {
1068 		mpr_dprint(sc, MPR_FAULT, "Timeout reading doorbell 1\n");
1069 		return (ENXIO);
1070 	}
1071 	data16[1] =
1072 	    le16toh(mpr_regread(sc, MPI2_DOORBELL_OFFSET)) & MPI2_DOORBELL_DATA_MASK;
1073 	mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
1074 
1075 	/* Number of 32bit words in the message */
1076 	ioc_sz = reply->MsgLength;
1077 
1078 	/*
1079 	 * Figure out how many 16bit words to clock in without overrunning.
1080 	 * The precision loss with dividing reply_sz can safely be
1081 	 * ignored because the messages can only be multiples of 32bits.
1082 	 */
1083 	residual = 0;
1084 	count = MIN((reply_sz / 4), ioc_sz) * 2;
1085 	if (count < ioc_sz * 2) {
1086 		residual = ioc_sz * 2 - count;
1087 		mpr_dprint(sc, MPR_ERROR, "Driver error, throwing away %d "
1088 		    "residual message words\n", residual);
1089 	}
1090 
1091 	for (i = 2; i < count; i++) {
1092 		if (mpr_wait_db_int(sc) != 0) {
1093 			mpr_dprint(sc, MPR_FAULT,
1094 			    "Timeout reading doorbell %d\n", i);
1095 			return (ENXIO);
1096 		}
1097 		data16[i] = le16toh(mpr_regread(sc, MPI2_DOORBELL_OFFSET)) &
1098 		    MPI2_DOORBELL_DATA_MASK;
1099 		mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
1100 	}
1101 
1102 	/*
1103 	 * Pull out residual words that won't fit into the provided buffer.
1104 	 * This keeps the chip from hanging due to a driver programming
1105 	 * error.
1106 	 */
1107 	while (residual--) {
1108 		if (mpr_wait_db_int(sc) != 0) {
1109 			mpr_dprint(sc, MPR_FAULT, "Timeout reading doorbell\n");
1110 			return (ENXIO);
1111 		}
1112 		(void)mpr_regread(sc, MPI2_DOORBELL_OFFSET);
1113 		mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
1114 	}
1115 
1116 	/* Step 7 */
1117 	if (mpr_wait_db_int(sc) != 0) {
1118 		mpr_dprint(sc, MPR_FAULT, "Timeout waiting to exit doorbell\n");
1119 		return (ENXIO);
1120 	}
1121 	if (mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_USED)
1122 		mpr_dprint(sc, MPR_FAULT, "Warning, doorbell still active\n");
1123 	mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0);
1124 
1125 	return (0);
1126 }
1127 
1128 static void
1129 mpr_enqueue_request(struct mpr_softc *sc, struct mpr_command *cm)
1130 {
1131 	request_descriptor_t rd;
1132 
1133 	MPR_FUNCTRACE(sc);
1134 	mpr_dprint(sc, MPR_TRACE, "SMID %u cm %p ccb %p\n",
1135 	    cm->cm_desc.Default.SMID, cm, cm->cm_ccb);
1136 
1137 	if (sc->mpr_flags & MPR_FLAGS_ATTACH_DONE && !(sc->mpr_flags &
1138 	    MPR_FLAGS_SHUTDOWN))
1139 		mtx_assert(&sc->mpr_mtx, MA_OWNED);
1140 
1141 	if (++sc->io_cmds_active > sc->io_cmds_highwater)
1142 		sc->io_cmds_highwater++;
1143 
1144 	KASSERT(cm->cm_state == MPR_CM_STATE_BUSY,
1145 	    ("command not busy, state = %u\n", cm->cm_state));
1146 	cm->cm_state = MPR_CM_STATE_INQUEUE;
1147 
1148 	if (sc->atomic_desc_capable) {
1149 		rd.u.low = cm->cm_desc.Words.Low;
1150 		mpr_regwrite(sc, MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET,
1151 		    rd.u.low);
1152 	} else {
1153 		rd.u.low = htole32(cm->cm_desc.Words.Low);
1154 		rd.u.high = htole32(cm->cm_desc.Words.High);
1155 		mpr_regwrite(sc, MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET,
1156 		    rd.u.low);
1157 		mpr_regwrite(sc, MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET,
1158 		    rd.u.high);
1159 	}
1160 }
1161 
1162 /*
1163  * Ioc facts are read in 16 bit words and and stored with le16toh,
1164  * this takes care of proper U8 fields endianness in
1165  * MPI2_IOC_FACTS_REPLY, but we still need to swap back U16 fields.
1166  */
1167 static void
1168 adjust_iocfacts_endianness(MPI2_IOC_FACTS_REPLY *facts)
1169 {
1170 	facts->HeaderVersion = le16toh(facts->HeaderVersion);
1171 	facts->Reserved1 = le16toh(facts->Reserved1);
1172 	facts->IOCExceptions = le16toh(facts->IOCExceptions);
1173 	facts->IOCStatus = le16toh(facts->IOCStatus);
1174 	facts->IOCLogInfo = le32toh(facts->IOCLogInfo);
1175 	facts->RequestCredit = le16toh(facts->RequestCredit);
1176 	facts->ProductID = le16toh(facts->ProductID);
1177 	facts->IOCCapabilities = le32toh(facts->IOCCapabilities);
1178 	facts->IOCRequestFrameSize = le16toh(facts->IOCRequestFrameSize);
1179 	facts->IOCMaxChainSegmentSize = le16toh(facts->IOCMaxChainSegmentSize);
1180 	facts->MaxInitiators = le16toh(facts->MaxInitiators);
1181 	facts->MaxTargets = le16toh(facts->MaxTargets);
1182 	facts->MaxSasExpanders = le16toh(facts->MaxSasExpanders);
1183 	facts->MaxEnclosures = le16toh(facts->MaxEnclosures);
1184 	facts->ProtocolFlags = le16toh(facts->ProtocolFlags);
1185 	facts->HighPriorityCredit = le16toh(facts->HighPriorityCredit);
1186 	facts->MaxReplyDescriptorPostQueueDepth = le16toh(facts->MaxReplyDescriptorPostQueueDepth);
1187 	facts->MaxDevHandle = le16toh(facts->MaxDevHandle);
1188 	facts->MaxPersistentEntries = le16toh(facts->MaxPersistentEntries);
1189 	facts->MinDevHandle = le16toh(facts->MinDevHandle);
1190 }
1191 
1192 /*
1193  * Just the FACTS, ma'am.
1194  */
1195 static int
1196 mpr_get_iocfacts(struct mpr_softc *sc, MPI2_IOC_FACTS_REPLY *facts)
1197 {
1198 	MPI2_DEFAULT_REPLY *reply;
1199 	MPI2_IOC_FACTS_REQUEST request;
1200 	int error, req_sz, reply_sz;
1201 
1202 	MPR_FUNCTRACE(sc);
1203 	mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__);
1204 
1205 	req_sz = sizeof(MPI2_IOC_FACTS_REQUEST);
1206 	reply_sz = sizeof(MPI2_IOC_FACTS_REPLY);
1207 	reply = (MPI2_DEFAULT_REPLY *)facts;
1208 
1209 	bzero(&request, req_sz);
1210 	request.Function = MPI2_FUNCTION_IOC_FACTS;
1211 	error = mpr_request_sync(sc, &request, reply, req_sz, reply_sz, 5);
1212 
1213 	adjust_iocfacts_endianness(facts);
1214 	mpr_dprint(sc, MPR_TRACE, "facts->IOCCapabilities 0x%x\n", facts->IOCCapabilities);
1215 
1216 	mpr_dprint(sc, MPR_INIT, "%s exit, error= %d\n", __func__, error);
1217 	return (error);
1218 }
1219 
1220 static int
1221 mpr_send_iocinit(struct mpr_softc *sc)
1222 {
1223 	MPI2_IOC_INIT_REQUEST	init;
1224 	MPI2_DEFAULT_REPLY	reply;
1225 	int req_sz, reply_sz, error;
1226 	struct timeval now;
1227 	uint64_t time_in_msec;
1228 
1229 	MPR_FUNCTRACE(sc);
1230 	mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__);
1231 
1232 	/* Do a quick sanity check on proper initialization */
1233 	if ((sc->pqdepth == 0) || (sc->fqdepth == 0) || (sc->reqframesz == 0)
1234 	    || (sc->replyframesz == 0)) {
1235 		mpr_dprint(sc, MPR_INIT|MPR_ERROR,
1236 		    "Driver not fully initialized for IOCInit\n");
1237 		return (EINVAL);
1238 	}
1239 
1240 	req_sz = sizeof(MPI2_IOC_INIT_REQUEST);
1241 	reply_sz = sizeof(MPI2_IOC_INIT_REPLY);
1242 	bzero(&init, req_sz);
1243 	bzero(&reply, reply_sz);
1244 
1245 	/*
1246 	 * Fill in the init block.  Note that most addresses are
1247 	 * deliberately in the lower 32bits of memory.  This is a micro-
1248 	 * optimzation for PCI/PCIX, though it's not clear if it helps PCIe.
1249 	 */
1250 	init.Function = MPI2_FUNCTION_IOC_INIT;
1251 	init.WhoInit = MPI2_WHOINIT_HOST_DRIVER;
1252 	init.MsgVersion = htole16(MPI2_VERSION);
1253 	init.HeaderVersion = htole16(MPI2_HEADER_VERSION);
1254 	init.SystemRequestFrameSize = htole16((uint16_t)(sc->reqframesz / 4));
1255 	init.ReplyDescriptorPostQueueDepth = htole16(sc->pqdepth);
1256 	init.ReplyFreeQueueDepth = htole16(sc->fqdepth);
1257 	init.SenseBufferAddressHigh = 0;
1258 	init.SystemReplyAddressHigh = 0;
1259 	init.SystemRequestFrameBaseAddress.High = 0;
1260 	init.SystemRequestFrameBaseAddress.Low =
1261 	    htole32((uint32_t)sc->req_busaddr);
1262 	init.ReplyDescriptorPostQueueAddress.High = 0;
1263 	init.ReplyDescriptorPostQueueAddress.Low =
1264 	    htole32((uint32_t)sc->post_busaddr);
1265 	init.ReplyFreeQueueAddress.High = 0;
1266 	init.ReplyFreeQueueAddress.Low = htole32((uint32_t)sc->free_busaddr);
1267 	getmicrotime(&now);
1268 	time_in_msec = (now.tv_sec * 1000 + now.tv_usec/1000);
1269 	init.TimeStamp.High = htole32((time_in_msec >> 32) & 0xFFFFFFFF);
1270 	init.TimeStamp.Low = htole32(time_in_msec & 0xFFFFFFFF);
1271 	init.HostPageSize = HOST_PAGE_SIZE_4K;
1272 
1273 	error = mpr_request_sync(sc, &init, &reply, req_sz, reply_sz, 5);
1274 	if ((le16toh(reply.IOCStatus) & MPI2_IOCSTATUS_MASK) != MPI2_IOCSTATUS_SUCCESS)
1275 		error = ENXIO;
1276 
1277 	mpr_dprint(sc, MPR_INIT, "IOCInit status= 0x%x\n", le16toh(reply.IOCStatus));
1278 	mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__);
1279 	return (error);
1280 }
1281 
1282 void
1283 mpr_memaddr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1284 {
1285 	bus_addr_t *addr;
1286 
1287 	addr = arg;
1288 	*addr = segs[0].ds_addr;
1289 }
1290 
1291 void
1292 mpr_memaddr_wait_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1293 {
1294 	struct mpr_busdma_context *ctx;
1295 	int need_unload, need_free;
1296 
1297 	ctx = (struct mpr_busdma_context *)arg;
1298 	need_unload = 0;
1299 	need_free = 0;
1300 
1301 	mpr_lock(ctx->softc);
1302 	ctx->error = error;
1303 	ctx->completed = 1;
1304 	if ((error == 0) && (ctx->abandoned == 0)) {
1305 		*ctx->addr = segs[0].ds_addr;
1306 	} else {
1307 		if (nsegs != 0)
1308 			need_unload = 1;
1309 		if (ctx->abandoned != 0)
1310 			need_free = 1;
1311 	}
1312 	if (need_free == 0)
1313 		wakeup(ctx);
1314 
1315 	mpr_unlock(ctx->softc);
1316 
1317 	if (need_unload != 0) {
1318 		bus_dmamap_unload(ctx->buffer_dmat,
1319 				  ctx->buffer_dmamap);
1320 		*ctx->addr = 0;
1321 	}
1322 
1323 	if (need_free != 0)
1324 		free(ctx, M_MPR);
1325 }
1326 
1327 static int
1328 mpr_alloc_queues(struct mpr_softc *sc)
1329 {
1330 	struct mpr_queue *q;
1331 	int nq, i;
1332 
1333 	nq = sc->msi_msgs;
1334 	mpr_dprint(sc, MPR_INIT|MPR_XINFO, "Allocating %d I/O queues\n", nq);
1335 
1336 	sc->queues = malloc(sizeof(struct mpr_queue) * nq, M_MPR,
1337 	     M_NOWAIT|M_ZERO);
1338 	if (sc->queues == NULL)
1339 		return (ENOMEM);
1340 
1341 	for (i = 0; i < nq; i++) {
1342 		q = &sc->queues[i];
1343 		mpr_dprint(sc, MPR_INIT, "Configuring queue %d %p\n", i, q);
1344 		q->sc = sc;
1345 		q->qnum = i;
1346 	}
1347 	return (0);
1348 }
1349 
1350 static int
1351 mpr_alloc_hw_queues(struct mpr_softc *sc)
1352 {
1353 	bus_dma_template_t t;
1354 	bus_addr_t queues_busaddr;
1355 	uint8_t *queues;
1356 	int qsize, fqsize, pqsize;
1357 
1358 	/*
1359 	 * The reply free queue contains 4 byte entries in multiples of 16 and
1360 	 * aligned on a 16 byte boundary. There must always be an unused entry.
1361 	 * This queue supplies fresh reply frames for the firmware to use.
1362 	 *
1363 	 * The reply descriptor post queue contains 8 byte entries in
1364 	 * multiples of 16 and aligned on a 16 byte boundary.  This queue
1365 	 * contains filled-in reply frames sent from the firmware to the host.
1366 	 *
1367 	 * These two queues are allocated together for simplicity.
1368 	 */
1369 	sc->fqdepth = roundup2(sc->num_replies + 1, 16);
1370 	sc->pqdepth = roundup2(sc->num_replies + 1, 16);
1371 	fqsize= sc->fqdepth * 4;
1372 	pqsize = sc->pqdepth * 8;
1373 	qsize = fqsize + pqsize;
1374 
1375 	bus_dma_template_init(&t, sc->mpr_parent_dmat);
1376 	BUS_DMA_TEMPLATE_FILL(&t, BD_ALIGNMENT(16), BD_MAXSIZE(qsize),
1377 	    BD_MAXSEGSIZE(qsize), BD_NSEGMENTS(1),
1378 	    BD_LOWADDR(BUS_SPACE_MAXADDR_32BIT));
1379 	if (bus_dma_template_tag(&t, &sc->queues_dmat)) {
1380 		mpr_dprint(sc, MPR_ERROR, "Cannot allocate queues DMA tag\n");
1381 		return (ENOMEM);
1382         }
1383         if (bus_dmamem_alloc(sc->queues_dmat, (void **)&queues, BUS_DMA_NOWAIT,
1384 	    &sc->queues_map)) {
1385 		mpr_dprint(sc, MPR_ERROR, "Cannot allocate queues memory\n");
1386 		return (ENOMEM);
1387         }
1388         bzero(queues, qsize);
1389         bus_dmamap_load(sc->queues_dmat, sc->queues_map, queues, qsize,
1390 	    mpr_memaddr_cb, &queues_busaddr, 0);
1391 
1392 	sc->free_queue = (uint32_t *)queues;
1393 	sc->free_busaddr = queues_busaddr;
1394 	sc->post_queue = (MPI2_REPLY_DESCRIPTORS_UNION *)(queues + fqsize);
1395 	sc->post_busaddr = queues_busaddr + fqsize;
1396 	mpr_dprint(sc, MPR_INIT, "free queue busaddr= %#016jx size= %d\n",
1397 	    (uintmax_t)sc->free_busaddr, fqsize);
1398 	mpr_dprint(sc, MPR_INIT, "reply queue busaddr= %#016jx size= %d\n",
1399 	    (uintmax_t)sc->post_busaddr, pqsize);
1400 
1401 	return (0);
1402 }
1403 
1404 static int
1405 mpr_alloc_replies(struct mpr_softc *sc)
1406 {
1407 	bus_dma_template_t t;
1408 	int rsize, num_replies;
1409 
1410 	/* Store the reply frame size in bytes rather than as 32bit words */
1411 	sc->replyframesz = sc->facts->ReplyFrameSize * 4;
1412 
1413 	/*
1414 	 * sc->num_replies should be one less than sc->fqdepth.  We need to
1415 	 * allocate space for sc->fqdepth replies, but only sc->num_replies
1416 	 * replies can be used at once.
1417 	 */
1418 	num_replies = max(sc->fqdepth, sc->num_replies);
1419 
1420 	rsize = sc->replyframesz * num_replies;
1421 	bus_dma_template_init(&t, sc->mpr_parent_dmat);
1422 	BUS_DMA_TEMPLATE_FILL(&t, BD_ALIGNMENT(4), BD_MAXSIZE(rsize),
1423 	    BD_MAXSEGSIZE(rsize), BD_NSEGMENTS(1),
1424 	    BD_LOWADDR(BUS_SPACE_MAXADDR_32BIT));
1425 	if (bus_dma_template_tag(&t, &sc->reply_dmat)) {
1426 		mpr_dprint(sc, MPR_ERROR, "Cannot allocate replies DMA tag\n");
1427 		return (ENOMEM);
1428         }
1429         if (bus_dmamem_alloc(sc->reply_dmat, (void **)&sc->reply_frames,
1430 	    BUS_DMA_NOWAIT, &sc->reply_map)) {
1431 		mpr_dprint(sc, MPR_ERROR, "Cannot allocate replies memory\n");
1432 		return (ENOMEM);
1433         }
1434         bzero(sc->reply_frames, rsize);
1435         bus_dmamap_load(sc->reply_dmat, sc->reply_map, sc->reply_frames, rsize,
1436 	    mpr_memaddr_cb, &sc->reply_busaddr, 0);
1437 	mpr_dprint(sc, MPR_INIT, "reply frames busaddr= %#016jx size= %d\n",
1438 	    (uintmax_t)sc->reply_busaddr, rsize);
1439 
1440 	return (0);
1441 }
1442 
1443 static void
1444 mpr_load_chains_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1445 {
1446 	struct mpr_softc *sc = arg;
1447 	struct mpr_chain *chain;
1448 	bus_size_t bo;
1449 	int i, o, s;
1450 
1451 	if (error != 0)
1452 		return;
1453 
1454 	for (i = 0, o = 0, s = 0; s < nsegs; s++) {
1455 		for (bo = 0; bo + sc->chain_frame_size <= segs[s].ds_len;
1456 		    bo += sc->chain_frame_size) {
1457 			chain = &sc->chains[i++];
1458 			chain->chain =(MPI2_SGE_IO_UNION *)(sc->chain_frames+o);
1459 			chain->chain_busaddr = segs[s].ds_addr + bo;
1460 			o += sc->chain_frame_size;
1461 			mpr_free_chain(sc, chain);
1462 		}
1463 		if (bo != segs[s].ds_len)
1464 			o += segs[s].ds_len - bo;
1465 	}
1466 	sc->chain_free_lowwater = i;
1467 }
1468 
1469 static int
1470 mpr_alloc_requests(struct mpr_softc *sc)
1471 {
1472 	bus_dma_template_t t;
1473 	struct mpr_command *cm;
1474 	int i, rsize, nsegs;
1475 
1476 	rsize = sc->reqframesz * sc->num_reqs;
1477 	bus_dma_template_init(&t, sc->mpr_parent_dmat);
1478 	BUS_DMA_TEMPLATE_FILL(&t, BD_ALIGNMENT(16), BD_MAXSIZE(rsize),
1479 	    BD_MAXSEGSIZE(rsize), BD_NSEGMENTS(1),
1480 	    BD_LOWADDR(BUS_SPACE_MAXADDR_32BIT));
1481 	if (bus_dma_template_tag(&t, &sc->req_dmat)) {
1482 		mpr_dprint(sc, MPR_ERROR, "Cannot allocate request DMA tag\n");
1483 		return (ENOMEM);
1484         }
1485         if (bus_dmamem_alloc(sc->req_dmat, (void **)&sc->req_frames,
1486 	    BUS_DMA_NOWAIT, &sc->req_map)) {
1487 		mpr_dprint(sc, MPR_ERROR, "Cannot allocate request memory\n");
1488 		return (ENOMEM);
1489         }
1490         bzero(sc->req_frames, rsize);
1491         bus_dmamap_load(sc->req_dmat, sc->req_map, sc->req_frames, rsize,
1492 	    mpr_memaddr_cb, &sc->req_busaddr, 0);
1493 	mpr_dprint(sc, MPR_INIT, "request frames busaddr= %#016jx size= %d\n",
1494 	    (uintmax_t)sc->req_busaddr, rsize);
1495 
1496 	sc->chains = malloc(sizeof(struct mpr_chain) * sc->num_chains, M_MPR,
1497 	    M_NOWAIT | M_ZERO);
1498 	if (!sc->chains) {
1499 		mpr_dprint(sc, MPR_ERROR, "Cannot allocate chain memory\n");
1500 		return (ENOMEM);
1501 	}
1502 	rsize = sc->chain_frame_size * sc->num_chains;
1503 	bus_dma_template_init(&t, sc->mpr_parent_dmat);
1504 	BUS_DMA_TEMPLATE_FILL(&t, BD_ALIGNMENT(16), BD_MAXSIZE(rsize),
1505 	    BD_MAXSEGSIZE(rsize), BD_NSEGMENTS((howmany(rsize, PAGE_SIZE))));
1506 	if (bus_dma_template_tag(&t, &sc->chain_dmat)) {
1507 		mpr_dprint(sc, MPR_ERROR, "Cannot allocate chain DMA tag\n");
1508 		return (ENOMEM);
1509 	}
1510 	if (bus_dmamem_alloc(sc->chain_dmat, (void **)&sc->chain_frames,
1511 	    BUS_DMA_NOWAIT | BUS_DMA_ZERO, &sc->chain_map)) {
1512 		mpr_dprint(sc, MPR_ERROR, "Cannot allocate chain memory\n");
1513 		return (ENOMEM);
1514 	}
1515 	if (bus_dmamap_load(sc->chain_dmat, sc->chain_map, sc->chain_frames,
1516 	    rsize, mpr_load_chains_cb, sc, BUS_DMA_NOWAIT)) {
1517 		mpr_dprint(sc, MPR_ERROR, "Cannot load chain memory\n");
1518 		bus_dmamem_free(sc->chain_dmat, sc->chain_frames,
1519 		    sc->chain_map);
1520 		return (ENOMEM);
1521 	}
1522 
1523 	rsize = MPR_SENSE_LEN * sc->num_reqs;
1524 	bus_dma_template_clone(&t, sc->req_dmat);
1525 	BUS_DMA_TEMPLATE_FILL(&t, BD_ALIGNMENT(1), BD_MAXSIZE(rsize),
1526 	    BD_MAXSEGSIZE(rsize));
1527 	if (bus_dma_template_tag(&t, &sc->sense_dmat)) {
1528 		mpr_dprint(sc, MPR_ERROR, "Cannot allocate sense DMA tag\n");
1529 		return (ENOMEM);
1530         }
1531         if (bus_dmamem_alloc(sc->sense_dmat, (void **)&sc->sense_frames,
1532 	    BUS_DMA_NOWAIT, &sc->sense_map)) {
1533 		mpr_dprint(sc, MPR_ERROR, "Cannot allocate sense memory\n");
1534 		return (ENOMEM);
1535         }
1536         bzero(sc->sense_frames, rsize);
1537         bus_dmamap_load(sc->sense_dmat, sc->sense_map, sc->sense_frames, rsize,
1538 	    mpr_memaddr_cb, &sc->sense_busaddr, 0);
1539 	mpr_dprint(sc, MPR_INIT, "sense frames busaddr= %#016jx size= %d\n",
1540 	    (uintmax_t)sc->sense_busaddr, rsize);
1541 
1542 	/*
1543 	 * Allocate NVMe PRP Pages for NVMe SGL support only if the FW supports
1544 	 * these devices.
1545 	 */
1546 	if ((sc->facts->MsgVersion >= MPI2_VERSION_02_06) &&
1547 	    (sc->facts->ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES)) {
1548 		if (mpr_alloc_nvme_prp_pages(sc) == ENOMEM)
1549 			return (ENOMEM);
1550 	}
1551 
1552 	nsegs = (sc->maxio / PAGE_SIZE) + 1;
1553 	bus_dma_template_init(&t, sc->mpr_parent_dmat);
1554 	BUS_DMA_TEMPLATE_FILL(&t, BD_MAXSIZE(BUS_SPACE_MAXSIZE_32BIT),
1555 	    BD_NSEGMENTS(nsegs), BD_MAXSEGSIZE(BUS_SPACE_MAXSIZE_32BIT),
1556 	    BD_FLAGS(BUS_DMA_ALLOCNOW), BD_LOCKFUNC(busdma_lock_mutex),
1557 	    BD_LOCKFUNCARG(&sc->mpr_mtx));
1558 	if (bus_dma_template_tag(&t, &sc->buffer_dmat)) {
1559 		mpr_dprint(sc, MPR_ERROR, "Cannot allocate buffer DMA tag\n");
1560 		return (ENOMEM);
1561         }
1562 
1563 	/*
1564 	 * SMID 0 cannot be used as a free command per the firmware spec.
1565 	 * Just drop that command instead of risking accounting bugs.
1566 	 */
1567 	sc->commands = malloc(sizeof(struct mpr_command) * sc->num_reqs,
1568 	    M_MPR, M_WAITOK | M_ZERO);
1569 	for (i = 1; i < sc->num_reqs; i++) {
1570 		cm = &sc->commands[i];
1571 		cm->cm_req = sc->req_frames + i * sc->reqframesz;
1572 		cm->cm_req_busaddr = sc->req_busaddr + i * sc->reqframesz;
1573 		cm->cm_sense = &sc->sense_frames[i];
1574 		cm->cm_sense_busaddr = sc->sense_busaddr + i * MPR_SENSE_LEN;
1575 		cm->cm_desc.Default.SMID = htole16(i);
1576 		cm->cm_sc = sc;
1577 		cm->cm_state = MPR_CM_STATE_BUSY;
1578 		TAILQ_INIT(&cm->cm_chain_list);
1579 		TAILQ_INIT(&cm->cm_prp_page_list);
1580 		callout_init_mtx(&cm->cm_callout, &sc->mpr_mtx, 0);
1581 
1582 		/* XXX Is a failure here a critical problem? */
1583 		if (bus_dmamap_create(sc->buffer_dmat, 0, &cm->cm_dmamap)
1584 		    == 0) {
1585 			if (i <= sc->num_prireqs)
1586 				mpr_free_high_priority_command(sc, cm);
1587 			else
1588 				mpr_free_command(sc, cm);
1589 		} else {
1590 			panic("failed to allocate command %d\n", i);
1591 			sc->num_reqs = i;
1592 			break;
1593 		}
1594 	}
1595 
1596 	return (0);
1597 }
1598 
1599 /*
1600  * Allocate contiguous buffers for PCIe NVMe devices for building native PRPs,
1601  * which are scatter/gather lists for NVMe devices.
1602  *
1603  * This buffer must be contiguous due to the nature of how NVMe PRPs are built
1604  * and translated by FW.
1605  *
1606  * returns ENOMEM if memory could not be allocated, otherwise returns 0.
1607  */
1608 static int
1609 mpr_alloc_nvme_prp_pages(struct mpr_softc *sc)
1610 {
1611 	bus_dma_template_t t;
1612 	struct mpr_prp_page *prp_page;
1613 	int PRPs_per_page, PRPs_required, pages_required;
1614 	int rsize, i;
1615 
1616 	/*
1617 	 * Assuming a MAX_IO_SIZE of 1MB and a PAGE_SIZE of 4k, the max number
1618 	 * of PRPs (NVMe's Scatter/Gather Element) needed per I/O is:
1619 	 * MAX_IO_SIZE / PAGE_SIZE = 256
1620 	 *
1621 	 * 1 PRP entry in main frame for PRP list pointer still leaves 255 PRPs
1622 	 * required for the remainder of the 1MB I/O. 512 PRPs can fit into one
1623 	 * page (4096 / 8 = 512), so only one page is required for each I/O.
1624 	 *
1625 	 * Each of these buffers will need to be contiguous. For simplicity,
1626 	 * only one buffer is allocated here, which has all of the space
1627 	 * required for the NVMe Queue Depth. If there are problems allocating
1628 	 * this one buffer, this function will need to change to allocate
1629 	 * individual, contiguous NVME_QDEPTH buffers.
1630 	 *
1631 	 * The real calculation will use the real max io size. Above is just an
1632 	 * example.
1633 	 *
1634 	 */
1635 	PRPs_required = sc->maxio / PAGE_SIZE;
1636 	PRPs_per_page = (PAGE_SIZE / PRP_ENTRY_SIZE) - 1;
1637 	pages_required = (PRPs_required / PRPs_per_page) + 1;
1638 
1639 	sc->prp_buffer_size = PAGE_SIZE * pages_required;
1640 	rsize = sc->prp_buffer_size * NVME_QDEPTH;
1641 	bus_dma_template_init(&t, sc->mpr_parent_dmat);
1642 	BUS_DMA_TEMPLATE_FILL(&t, BD_ALIGNMENT(4), BD_MAXSIZE(rsize),
1643 	    BD_MAXSEGSIZE(rsize), BD_NSEGMENTS(1),
1644 	    BD_LOWADDR(BUS_SPACE_MAXADDR_32BIT));
1645 	if (bus_dma_template_tag(&t, &sc->prp_page_dmat)) {
1646 		mpr_dprint(sc, MPR_ERROR, "Cannot allocate NVMe PRP DMA "
1647 		    "tag\n");
1648 		return (ENOMEM);
1649 	}
1650 	if (bus_dmamem_alloc(sc->prp_page_dmat, (void **)&sc->prp_pages,
1651 	    BUS_DMA_NOWAIT, &sc->prp_page_map)) {
1652 		mpr_dprint(sc, MPR_ERROR, "Cannot allocate NVMe PRP memory\n");
1653 		return (ENOMEM);
1654 	}
1655 	bzero(sc->prp_pages, rsize);
1656 	bus_dmamap_load(sc->prp_page_dmat, sc->prp_page_map, sc->prp_pages,
1657 	    rsize, mpr_memaddr_cb, &sc->prp_page_busaddr, 0);
1658 
1659 	sc->prps = malloc(sizeof(struct mpr_prp_page) * NVME_QDEPTH, M_MPR,
1660 	    M_WAITOK | M_ZERO);
1661 	for (i = 0; i < NVME_QDEPTH; i++) {
1662 		prp_page = &sc->prps[i];
1663 		prp_page->prp_page = (uint64_t *)(sc->prp_pages +
1664 		    i * sc->prp_buffer_size);
1665 		prp_page->prp_page_busaddr = (uint64_t)(sc->prp_page_busaddr +
1666 		    i * sc->prp_buffer_size);
1667 		mpr_free_prp_page(sc, prp_page);
1668 		sc->prp_pages_free_lowwater++;
1669 	}
1670 
1671 	return (0);
1672 }
1673 
1674 static int
1675 mpr_init_queues(struct mpr_softc *sc)
1676 {
1677 	int i;
1678 
1679 	memset((uint8_t *)sc->post_queue, 0xff, sc->pqdepth * 8);
1680 
1681 	/*
1682 	 * According to the spec, we need to use one less reply than we
1683 	 * have space for on the queue.  So sc->num_replies (the number we
1684 	 * use) should be less than sc->fqdepth (allocated size).
1685 	 */
1686 	if (sc->num_replies >= sc->fqdepth)
1687 		return (EINVAL);
1688 
1689 	/*
1690 	 * Initialize all of the free queue entries.
1691 	 */
1692 	for (i = 0; i < sc->fqdepth; i++) {
1693 		sc->free_queue[i] = htole32(sc->reply_busaddr + (i * sc->replyframesz));
1694 	}
1695 	sc->replyfreeindex = sc->num_replies;
1696 
1697 	return (0);
1698 }
1699 
1700 /* Get the driver parameter tunables.  Lowest priority are the driver defaults.
1701  * Next are the global settings, if they exist.  Highest are the per-unit
1702  * settings, if they exist.
1703  */
1704 void
1705 mpr_get_tunables(struct mpr_softc *sc)
1706 {
1707 	char tmpstr[80], mpr_debug[80];
1708 
1709 	/* XXX default to some debugging for now */
1710 	sc->mpr_debug = MPR_INFO | MPR_FAULT;
1711 	sc->disable_msix = 0;
1712 	sc->disable_msi = 0;
1713 	sc->max_msix = MPR_MSIX_MAX;
1714 	sc->max_chains = MPR_CHAIN_FRAMES;
1715 	sc->max_io_pages = MPR_MAXIO_PAGES;
1716 	sc->enable_ssu = MPR_SSU_ENABLE_SSD_DISABLE_HDD;
1717 	sc->spinup_wait_time = DEFAULT_SPINUP_WAIT;
1718 	sc->use_phynum = 1;
1719 	sc->max_reqframes = MPR_REQ_FRAMES;
1720 	sc->max_prireqframes = MPR_PRI_REQ_FRAMES;
1721 	sc->max_replyframes = MPR_REPLY_FRAMES;
1722 	sc->max_evtframes = MPR_EVT_REPLY_FRAMES;
1723 
1724 	/*
1725 	 * Grab the global variables.
1726 	 */
1727 	bzero(mpr_debug, 80);
1728 	if (TUNABLE_STR_FETCH("hw.mpr.debug_level", mpr_debug, 80) != 0)
1729 		mpr_parse_debug(sc, mpr_debug);
1730 	TUNABLE_INT_FETCH("hw.mpr.disable_msix", &sc->disable_msix);
1731 	TUNABLE_INT_FETCH("hw.mpr.disable_msi", &sc->disable_msi);
1732 	TUNABLE_INT_FETCH("hw.mpr.max_msix", &sc->max_msix);
1733 	TUNABLE_INT_FETCH("hw.mpr.max_chains", &sc->max_chains);
1734 	TUNABLE_INT_FETCH("hw.mpr.max_io_pages", &sc->max_io_pages);
1735 	TUNABLE_INT_FETCH("hw.mpr.enable_ssu", &sc->enable_ssu);
1736 	TUNABLE_INT_FETCH("hw.mpr.spinup_wait_time", &sc->spinup_wait_time);
1737 	TUNABLE_INT_FETCH("hw.mpr.use_phy_num", &sc->use_phynum);
1738 	TUNABLE_INT_FETCH("hw.mpr.max_reqframes", &sc->max_reqframes);
1739 	TUNABLE_INT_FETCH("hw.mpr.max_prireqframes", &sc->max_prireqframes);
1740 	TUNABLE_INT_FETCH("hw.mpr.max_replyframes", &sc->max_replyframes);
1741 	TUNABLE_INT_FETCH("hw.mpr.max_evtframes", &sc->max_evtframes);
1742 
1743 	/* Grab the unit-instance variables */
1744 	snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.debug_level",
1745 	    device_get_unit(sc->mpr_dev));
1746 	bzero(mpr_debug, 80);
1747 	if (TUNABLE_STR_FETCH(tmpstr, mpr_debug, 80) != 0)
1748 		mpr_parse_debug(sc, mpr_debug);
1749 
1750 	snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.disable_msix",
1751 	    device_get_unit(sc->mpr_dev));
1752 	TUNABLE_INT_FETCH(tmpstr, &sc->disable_msix);
1753 
1754 	snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.disable_msi",
1755 	    device_get_unit(sc->mpr_dev));
1756 	TUNABLE_INT_FETCH(tmpstr, &sc->disable_msi);
1757 
1758 	snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_msix",
1759 	    device_get_unit(sc->mpr_dev));
1760 	TUNABLE_INT_FETCH(tmpstr, &sc->max_msix);
1761 
1762 	snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_chains",
1763 	    device_get_unit(sc->mpr_dev));
1764 	TUNABLE_INT_FETCH(tmpstr, &sc->max_chains);
1765 
1766 	snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_io_pages",
1767 	    device_get_unit(sc->mpr_dev));
1768 	TUNABLE_INT_FETCH(tmpstr, &sc->max_io_pages);
1769 
1770 	bzero(sc->exclude_ids, sizeof(sc->exclude_ids));
1771 	snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.exclude_ids",
1772 	    device_get_unit(sc->mpr_dev));
1773 	TUNABLE_STR_FETCH(tmpstr, sc->exclude_ids, sizeof(sc->exclude_ids));
1774 
1775 	snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.enable_ssu",
1776 	    device_get_unit(sc->mpr_dev));
1777 	TUNABLE_INT_FETCH(tmpstr, &sc->enable_ssu);
1778 
1779 	snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.spinup_wait_time",
1780 	    device_get_unit(sc->mpr_dev));
1781 	TUNABLE_INT_FETCH(tmpstr, &sc->spinup_wait_time);
1782 
1783 	snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.use_phy_num",
1784 	    device_get_unit(sc->mpr_dev));
1785 	TUNABLE_INT_FETCH(tmpstr, &sc->use_phynum);
1786 
1787 	snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_reqframes",
1788 	    device_get_unit(sc->mpr_dev));
1789 	TUNABLE_INT_FETCH(tmpstr, &sc->max_reqframes);
1790 
1791 	snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_prireqframes",
1792 	    device_get_unit(sc->mpr_dev));
1793 	TUNABLE_INT_FETCH(tmpstr, &sc->max_prireqframes);
1794 
1795 	snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_replyframes",
1796 	    device_get_unit(sc->mpr_dev));
1797 	TUNABLE_INT_FETCH(tmpstr, &sc->max_replyframes);
1798 
1799 	snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_evtframes",
1800 	    device_get_unit(sc->mpr_dev));
1801 	TUNABLE_INT_FETCH(tmpstr, &sc->max_evtframes);
1802 }
1803 
1804 static void
1805 mpr_setup_sysctl(struct mpr_softc *sc)
1806 {
1807 	struct sysctl_ctx_list	*sysctl_ctx = NULL;
1808 	struct sysctl_oid	*sysctl_tree = NULL;
1809 	char tmpstr[80], tmpstr2[80];
1810 
1811 	/*
1812 	 * Setup the sysctl variable so the user can change the debug level
1813 	 * on the fly.
1814 	 */
1815 	snprintf(tmpstr, sizeof(tmpstr), "MPR controller %d",
1816 	    device_get_unit(sc->mpr_dev));
1817 	snprintf(tmpstr2, sizeof(tmpstr2), "%d", device_get_unit(sc->mpr_dev));
1818 
1819 	sysctl_ctx = device_get_sysctl_ctx(sc->mpr_dev);
1820 	if (sysctl_ctx != NULL)
1821 		sysctl_tree = device_get_sysctl_tree(sc->mpr_dev);
1822 
1823 	if (sysctl_tree == NULL) {
1824 		sysctl_ctx_init(&sc->sysctl_ctx);
1825 		sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx,
1826 		    SYSCTL_STATIC_CHILDREN(_hw_mpr), OID_AUTO, tmpstr2,
1827 		    CTLFLAG_RD | CTLFLAG_MPSAFE, 0, tmpstr);
1828 		if (sc->sysctl_tree == NULL)
1829 			return;
1830 		sysctl_ctx = &sc->sysctl_ctx;
1831 		sysctl_tree = sc->sysctl_tree;
1832 	}
1833 
1834 	SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1835 	    OID_AUTO, "debug_level", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE,
1836 	    sc, 0, mpr_debug_sysctl, "A", "mpr debug level");
1837 
1838 	SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1839 	    OID_AUTO, "disable_msix", CTLFLAG_RD, &sc->disable_msix, 0,
1840 	    "Disable the use of MSI-X interrupts");
1841 
1842 	SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1843 	    OID_AUTO, "max_msix", CTLFLAG_RD, &sc->max_msix, 0,
1844 	    "User-defined maximum number of MSIX queues");
1845 
1846 	SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1847 	    OID_AUTO, "msix_msgs", CTLFLAG_RD, &sc->msi_msgs, 0,
1848 	    "Negotiated number of MSIX queues");
1849 
1850 	SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1851 	    OID_AUTO, "max_reqframes", CTLFLAG_RD, &sc->max_reqframes, 0,
1852 	    "Total number of allocated request frames");
1853 
1854 	SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1855 	    OID_AUTO, "max_prireqframes", CTLFLAG_RD, &sc->max_prireqframes, 0,
1856 	    "Total number of allocated high priority request frames");
1857 
1858 	SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1859 	    OID_AUTO, "max_replyframes", CTLFLAG_RD, &sc->max_replyframes, 0,
1860 	    "Total number of allocated reply frames");
1861 
1862 	SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1863 	    OID_AUTO, "max_evtframes", CTLFLAG_RD, &sc->max_evtframes, 0,
1864 	    "Total number of event frames allocated");
1865 
1866 	SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1867 	    OID_AUTO, "firmware_version", CTLFLAG_RD, sc->fw_version,
1868 	    strlen(sc->fw_version), "firmware version");
1869 
1870 	SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1871 	    OID_AUTO, "driver_version", CTLFLAG_RD, MPR_DRIVER_VERSION,
1872 	    strlen(MPR_DRIVER_VERSION), "driver version");
1873 
1874 	SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1875 	    OID_AUTO, "msg_version", CTLFLAG_RD, sc->msg_version,
1876 	    strlen(sc->msg_version), "message interface version");
1877 
1878 	SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1879 	    OID_AUTO, "io_cmds_active", CTLFLAG_RD,
1880 	    &sc->io_cmds_active, 0, "number of currently active commands");
1881 
1882 	SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1883 	    OID_AUTO, "io_cmds_highwater", CTLFLAG_RD,
1884 	    &sc->io_cmds_highwater, 0, "maximum active commands seen");
1885 
1886 	SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1887 	    OID_AUTO, "chain_free", CTLFLAG_RD,
1888 	    &sc->chain_free, 0, "number of free chain elements");
1889 
1890 	SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1891 	    OID_AUTO, "chain_free_lowwater", CTLFLAG_RD,
1892 	    &sc->chain_free_lowwater, 0,"lowest number of free chain elements");
1893 
1894 	SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1895 	    OID_AUTO, "max_chains", CTLFLAG_RD,
1896 	    &sc->max_chains, 0,"maximum chain frames that will be allocated");
1897 
1898 	SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1899 	    OID_AUTO, "max_io_pages", CTLFLAG_RD,
1900 	    &sc->max_io_pages, 0,"maximum pages to allow per I/O (if <1 use "
1901 	    "IOCFacts)");
1902 
1903 	SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1904 	    OID_AUTO, "enable_ssu", CTLFLAG_RW, &sc->enable_ssu, 0,
1905 	    "enable SSU to SATA SSD/HDD at shutdown");
1906 
1907 	SYSCTL_ADD_UQUAD(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1908 	    OID_AUTO, "chain_alloc_fail", CTLFLAG_RD,
1909 	    &sc->chain_alloc_fail, "chain allocation failures");
1910 
1911 	SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1912 	    OID_AUTO, "spinup_wait_time", CTLFLAG_RD,
1913 	    &sc->spinup_wait_time, DEFAULT_SPINUP_WAIT, "seconds to wait for "
1914 	    "spinup after SATA ID error");
1915 
1916 	SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1917 	    OID_AUTO, "dump_reqs",
1918 	    CTLTYPE_OPAQUE | CTLFLAG_RD | CTLFLAG_SKIP | CTLFLAG_NEEDGIANT,
1919 	    sc, 0, mpr_dump_reqs, "I", "Dump Active Requests");
1920 
1921 	SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1922 	    OID_AUTO, "dump_reqs_alltypes", CTLFLAG_RW,
1923 	    &sc->dump_reqs_alltypes, 0,
1924 	    "dump all request types not just inqueue");
1925 
1926 	SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1927 	    OID_AUTO, "use_phy_num", CTLFLAG_RD, &sc->use_phynum, 0,
1928 	    "Use the phy number for enumeration");
1929 
1930 	SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1931 	    OID_AUTO, "prp_pages_free", CTLFLAG_RD,
1932 	    &sc->prp_pages_free, 0, "number of free PRP pages");
1933 
1934 	SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1935 	    OID_AUTO, "prp_pages_free_lowwater", CTLFLAG_RD,
1936 	    &sc->prp_pages_free_lowwater, 0,"lowest number of free PRP pages");
1937 
1938 	SYSCTL_ADD_UQUAD(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree),
1939 	    OID_AUTO, "prp_page_alloc_fail", CTLFLAG_RD,
1940 	    &sc->prp_page_alloc_fail, "PRP page allocation failures");
1941 }
1942 
1943 static struct mpr_debug_string {
1944 	char *name;
1945 	int flag;
1946 } mpr_debug_strings[] = {
1947 	{"info", MPR_INFO},
1948 	{"fault", MPR_FAULT},
1949 	{"event", MPR_EVENT},
1950 	{"log", MPR_LOG},
1951 	{"recovery", MPR_RECOVERY},
1952 	{"error", MPR_ERROR},
1953 	{"init", MPR_INIT},
1954 	{"xinfo", MPR_XINFO},
1955 	{"user", MPR_USER},
1956 	{"mapping", MPR_MAPPING},
1957 	{"trace", MPR_TRACE}
1958 };
1959 
1960 enum mpr_debug_level_combiner {
1961 	COMB_NONE,
1962 	COMB_ADD,
1963 	COMB_SUB
1964 };
1965 
1966 static int
1967 mpr_debug_sysctl(SYSCTL_HANDLER_ARGS)
1968 {
1969 	struct mpr_softc *sc;
1970 	struct mpr_debug_string *string;
1971 	struct sbuf *sbuf;
1972 	char *buffer;
1973 	size_t sz;
1974 	int i, len, debug, error;
1975 
1976 	sc = (struct mpr_softc *)arg1;
1977 
1978 	error = sysctl_wire_old_buffer(req, 0);
1979 	if (error != 0)
1980 		return (error);
1981 
1982 	sbuf = sbuf_new_for_sysctl(NULL, NULL, 128, req);
1983 	debug = sc->mpr_debug;
1984 
1985 	sbuf_printf(sbuf, "%#x", debug);
1986 
1987 	sz = sizeof(mpr_debug_strings) / sizeof(mpr_debug_strings[0]);
1988 	for (i = 0; i < sz; i++) {
1989 		string = &mpr_debug_strings[i];
1990 		if (debug & string->flag)
1991 			sbuf_printf(sbuf, ",%s", string->name);
1992 	}
1993 
1994 	error = sbuf_finish(sbuf);
1995 	sbuf_delete(sbuf);
1996 
1997 	if (error || req->newptr == NULL)
1998 		return (error);
1999 
2000 	len = req->newlen - req->newidx;
2001 	if (len == 0)
2002 		return (0);
2003 
2004 	buffer = malloc(len, M_MPR, M_ZERO|M_WAITOK);
2005 	error = SYSCTL_IN(req, buffer, len);
2006 
2007 	mpr_parse_debug(sc, buffer);
2008 
2009 	free(buffer, M_MPR);
2010 	return (error);
2011 }
2012 
2013 static void
2014 mpr_parse_debug(struct mpr_softc *sc, char *list)
2015 {
2016 	struct mpr_debug_string *string;
2017 	enum mpr_debug_level_combiner op;
2018 	char *token, *endtoken;
2019 	size_t sz;
2020 	int flags, i;
2021 
2022 	if (list == NULL || *list == '\0')
2023 		return;
2024 
2025 	if (*list == '+') {
2026 		op = COMB_ADD;
2027 		list++;
2028 	} else if (*list == '-') {
2029 		op = COMB_SUB;
2030 		list++;
2031 	} else
2032 		op = COMB_NONE;
2033 	if (*list == '\0')
2034 		return;
2035 
2036 	flags = 0;
2037 	sz = sizeof(mpr_debug_strings) / sizeof(mpr_debug_strings[0]);
2038 	while ((token = strsep(&list, ":,")) != NULL) {
2039 		/* Handle integer flags */
2040 		flags |= strtol(token, &endtoken, 0);
2041 		if (token != endtoken)
2042 			continue;
2043 
2044 		/* Handle text flags */
2045 		for (i = 0; i < sz; i++) {
2046 			string = &mpr_debug_strings[i];
2047 			if (strcasecmp(token, string->name) == 0) {
2048 				flags |= string->flag;
2049 				break;
2050 			}
2051 		}
2052 	}
2053 
2054 	switch (op) {
2055 	case COMB_NONE:
2056 		sc->mpr_debug = flags;
2057 		break;
2058 	case COMB_ADD:
2059 		sc->mpr_debug |= flags;
2060 		break;
2061 	case COMB_SUB:
2062 		sc->mpr_debug &= (~flags);
2063 		break;
2064 	}
2065 	return;
2066 }
2067 
2068 struct mpr_dumpreq_hdr {
2069 	uint32_t	smid;
2070 	uint32_t	state;
2071 	uint32_t	numframes;
2072 	uint32_t	deschi;
2073 	uint32_t	desclo;
2074 };
2075 
2076 static int
2077 mpr_dump_reqs(SYSCTL_HANDLER_ARGS)
2078 {
2079 	struct mpr_softc *sc;
2080 	struct mpr_chain *chain, *chain1;
2081 	struct mpr_command *cm;
2082 	struct mpr_dumpreq_hdr hdr;
2083 	struct sbuf *sb;
2084 	uint32_t smid, state;
2085 	int i, numreqs, error = 0;
2086 
2087 	sc = (struct mpr_softc *)arg1;
2088 
2089 	if ((error = priv_check(curthread, PRIV_DRIVER)) != 0) {
2090 		printf("priv check error %d\n", error);
2091 		return (error);
2092 	}
2093 
2094 	state = MPR_CM_STATE_INQUEUE;
2095 	smid = 1;
2096 	numreqs = sc->num_reqs;
2097 
2098 	if (req->newptr != NULL)
2099 		return (EINVAL);
2100 
2101 	if (smid == 0 || smid > sc->num_reqs)
2102 		return (EINVAL);
2103 	if (numreqs <= 0 || (numreqs + smid > sc->num_reqs))
2104 		numreqs = sc->num_reqs;
2105 	sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
2106 
2107 	/* Best effort, no locking */
2108 	for (i = smid; i < numreqs; i++) {
2109 		cm = &sc->commands[i];
2110 		if ((sc->dump_reqs_alltypes == 0) && (cm->cm_state != state))
2111 			continue;
2112 		hdr.smid = i;
2113 		hdr.state = cm->cm_state;
2114 		hdr.numframes = 1;
2115 		hdr.deschi = cm->cm_desc.Words.High;
2116 		hdr.desclo = cm->cm_desc.Words.Low;
2117 		TAILQ_FOREACH_SAFE(chain, &cm->cm_chain_list, chain_link,
2118 		   chain1)
2119 			hdr.numframes++;
2120 		sbuf_bcat(sb, &hdr, sizeof(hdr));
2121 		sbuf_bcat(sb, cm->cm_req, 128);
2122 		TAILQ_FOREACH_SAFE(chain, &cm->cm_chain_list, chain_link,
2123 		    chain1)
2124 			sbuf_bcat(sb, chain->chain, 128);
2125 	}
2126 
2127 	error = sbuf_finish(sb);
2128 	sbuf_delete(sb);
2129 	return (error);
2130 }
2131 
2132 int
2133 mpr_attach(struct mpr_softc *sc)
2134 {
2135 	int error;
2136 
2137 	MPR_FUNCTRACE(sc);
2138 	mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__);
2139 
2140 	mtx_init(&sc->mpr_mtx, "MPR lock", NULL, MTX_DEF);
2141 	callout_init_mtx(&sc->periodic, &sc->mpr_mtx, 0);
2142 	callout_init_mtx(&sc->device_check_callout, &sc->mpr_mtx, 0);
2143 	TAILQ_INIT(&sc->event_list);
2144 	timevalclear(&sc->lastfail);
2145 
2146 	if ((error = mpr_transition_ready(sc)) != 0) {
2147 		mpr_dprint(sc, MPR_INIT|MPR_FAULT,
2148 		    "Failed to transition ready\n");
2149 		return (error);
2150 	}
2151 
2152 	sc->facts = malloc(sizeof(MPI2_IOC_FACTS_REPLY), M_MPR,
2153 	    M_ZERO|M_NOWAIT);
2154 	if (!sc->facts) {
2155 		mpr_dprint(sc, MPR_INIT|MPR_FAULT,
2156 		    "Cannot allocate memory, exit\n");
2157 		return (ENOMEM);
2158 	}
2159 
2160 	/*
2161 	 * Get IOC Facts and allocate all structures based on this information.
2162 	 * A Diag Reset will also call mpr_iocfacts_allocate and re-read the IOC
2163 	 * Facts. If relevant values have changed in IOC Facts, this function
2164 	 * will free all of the memory based on IOC Facts and reallocate that
2165 	 * memory.  If this fails, any allocated memory should already be freed.
2166 	 */
2167 	if ((error = mpr_iocfacts_allocate(sc, TRUE)) != 0) {
2168 		mpr_dprint(sc, MPR_INIT|MPR_FAULT, "IOC Facts allocation "
2169 		    "failed with error %d\n", error);
2170 		return (error);
2171 	}
2172 
2173 	/* Start the periodic watchdog check on the IOC Doorbell */
2174 	mpr_periodic(sc);
2175 
2176 	/*
2177 	 * The portenable will kick off discovery events that will drive the
2178 	 * rest of the initialization process.  The CAM/SAS module will
2179 	 * hold up the boot sequence until discovery is complete.
2180 	 */
2181 	sc->mpr_ich.ich_func = mpr_startup;
2182 	sc->mpr_ich.ich_arg = sc;
2183 	if (config_intrhook_establish(&sc->mpr_ich) != 0) {
2184 		mpr_dprint(sc, MPR_INIT|MPR_ERROR,
2185 		    "Cannot establish MPR config hook\n");
2186 		error = EINVAL;
2187 	}
2188 
2189 	/*
2190 	 * Allow IR to shutdown gracefully when shutdown occurs.
2191 	 */
2192 	sc->shutdown_eh = EVENTHANDLER_REGISTER(shutdown_final,
2193 	    mprsas_ir_shutdown, sc, SHUTDOWN_PRI_DEFAULT);
2194 
2195 	if (sc->shutdown_eh == NULL)
2196 		mpr_dprint(sc, MPR_INIT|MPR_ERROR,
2197 		    "shutdown event registration failed\n");
2198 
2199 	mpr_setup_sysctl(sc);
2200 
2201 	sc->mpr_flags |= MPR_FLAGS_ATTACH_DONE;
2202 	mpr_dprint(sc, MPR_INIT, "%s exit error= %d\n", __func__, error);
2203 
2204 	return (error);
2205 }
2206 
2207 /* Run through any late-start handlers. */
2208 static void
2209 mpr_startup(void *arg)
2210 {
2211 	struct mpr_softc *sc;
2212 
2213 	sc = (struct mpr_softc *)arg;
2214 	mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__);
2215 
2216 	mpr_lock(sc);
2217 	mpr_unmask_intr(sc);
2218 
2219 	/* initialize device mapping tables */
2220 	mpr_base_static_config_pages(sc);
2221 	mpr_mapping_initialize(sc);
2222 	mprsas_startup(sc);
2223 	mpr_unlock(sc);
2224 
2225 	mpr_dprint(sc, MPR_INIT, "disestablish config intrhook\n");
2226 	config_intrhook_disestablish(&sc->mpr_ich);
2227 	sc->mpr_ich.ich_arg = NULL;
2228 
2229 	mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__);
2230 }
2231 
2232 /* Periodic watchdog.  Is called with the driver lock already held. */
2233 static void
2234 mpr_periodic(void *arg)
2235 {
2236 	struct mpr_softc *sc;
2237 	uint32_t db;
2238 
2239 	sc = (struct mpr_softc *)arg;
2240 	if (sc->mpr_flags & MPR_FLAGS_SHUTDOWN)
2241 		return;
2242 
2243 	db = mpr_regread(sc, MPI2_DOORBELL_OFFSET);
2244 	if ((db & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
2245 		if ((db & MPI2_DOORBELL_FAULT_CODE_MASK) ==
2246 		    IFAULT_IOP_OVER_TEMP_THRESHOLD_EXCEEDED) {
2247 			panic("TEMPERATURE FAULT: STOPPING.");
2248 		}
2249 		mpr_dprint(sc, MPR_FAULT, "IOC Fault 0x%08x, Resetting\n", db);
2250 		mpr_reinit(sc);
2251 	}
2252 
2253 	callout_reset(&sc->periodic, MPR_PERIODIC_DELAY * hz, mpr_periodic, sc);
2254 }
2255 
2256 static void
2257 mpr_log_evt_handler(struct mpr_softc *sc, uintptr_t data,
2258     MPI2_EVENT_NOTIFICATION_REPLY *event)
2259 {
2260 	MPI2_EVENT_DATA_LOG_ENTRY_ADDED *entry;
2261 
2262 	MPR_DPRINT_EVENT(sc, generic, event);
2263 
2264 	switch (event->Event) {
2265 	case MPI2_EVENT_LOG_DATA:
2266 		mpr_dprint(sc, MPR_EVENT, "MPI2_EVENT_LOG_DATA:\n");
2267 		if (sc->mpr_debug & MPR_EVENT)
2268 			hexdump(event->EventData, event->EventDataLength, NULL,
2269 			    0);
2270 		break;
2271 	case MPI2_EVENT_LOG_ENTRY_ADDED:
2272 		entry = (MPI2_EVENT_DATA_LOG_ENTRY_ADDED *)event->EventData;
2273 		mpr_dprint(sc, MPR_EVENT, "MPI2_EVENT_LOG_ENTRY_ADDED event "
2274 		    "0x%x Sequence %d:\n", entry->LogEntryQualifier,
2275 		     entry->LogSequence);
2276 		break;
2277 	default:
2278 		break;
2279 	}
2280 	return;
2281 }
2282 
2283 static int
2284 mpr_attach_log(struct mpr_softc *sc)
2285 {
2286 	uint8_t events[16];
2287 
2288 	bzero(events, 16);
2289 	setbit(events, MPI2_EVENT_LOG_DATA);
2290 	setbit(events, MPI2_EVENT_LOG_ENTRY_ADDED);
2291 
2292 	mpr_register_events(sc, events, mpr_log_evt_handler, NULL,
2293 	    &sc->mpr_log_eh);
2294 
2295 	return (0);
2296 }
2297 
2298 static int
2299 mpr_detach_log(struct mpr_softc *sc)
2300 {
2301 
2302 	if (sc->mpr_log_eh != NULL)
2303 		mpr_deregister_events(sc, sc->mpr_log_eh);
2304 	return (0);
2305 }
2306 
2307 /*
2308  * Free all of the driver resources and detach submodules.  Should be called
2309  * without the lock held.
2310  */
2311 int
2312 mpr_free(struct mpr_softc *sc)
2313 {
2314 	int error;
2315 
2316 	mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__);
2317 	/* Turn off the watchdog */
2318 	mpr_lock(sc);
2319 	sc->mpr_flags |= MPR_FLAGS_SHUTDOWN;
2320 	mpr_unlock(sc);
2321 	/* Lock must not be held for this */
2322 	callout_drain(&sc->periodic);
2323 	callout_drain(&sc->device_check_callout);
2324 
2325 	if (((error = mpr_detach_log(sc)) != 0) ||
2326 	    ((error = mpr_detach_sas(sc)) != 0)) {
2327 		mpr_dprint(sc, MPR_INIT|MPR_FAULT, "failed to detach "
2328 		    "subsystems, error= %d, exit\n", error);
2329 		return (error);
2330 	}
2331 
2332 	mpr_detach_user(sc);
2333 
2334 	/* Put the IOC back in the READY state. */
2335 	mpr_lock(sc);
2336 	if ((error = mpr_transition_ready(sc)) != 0) {
2337 		mpr_unlock(sc);
2338 		return (error);
2339 	}
2340 	mpr_unlock(sc);
2341 
2342 	if (sc->facts != NULL)
2343 		free(sc->facts, M_MPR);
2344 
2345 	/*
2346 	 * Free all buffers that are based on IOC Facts.  A Diag Reset may need
2347 	 * to free these buffers too.
2348 	 */
2349 	mpr_iocfacts_free(sc);
2350 
2351 	if (sc->sysctl_tree != NULL)
2352 		sysctl_ctx_free(&sc->sysctl_ctx);
2353 
2354 	/* Deregister the shutdown function */
2355 	if (sc->shutdown_eh != NULL)
2356 		EVENTHANDLER_DEREGISTER(shutdown_final, sc->shutdown_eh);
2357 
2358 	mtx_destroy(&sc->mpr_mtx);
2359 	mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__);
2360 
2361 	return (0);
2362 }
2363 
2364 static __inline void
2365 mpr_complete_command(struct mpr_softc *sc, struct mpr_command *cm)
2366 {
2367 	MPR_FUNCTRACE(sc);
2368 
2369 	if (cm == NULL) {
2370 		mpr_dprint(sc, MPR_ERROR, "Completing NULL command\n");
2371 		return;
2372 	}
2373 
2374 	KASSERT(cm->cm_state == MPR_CM_STATE_INQUEUE,
2375 	    ("command not inqueue, state = %u\n", cm->cm_state));
2376 	cm->cm_state = MPR_CM_STATE_BUSY;
2377 	if (cm->cm_flags & MPR_CM_FLAGS_POLLED)
2378 		cm->cm_flags |= MPR_CM_FLAGS_COMPLETE;
2379 
2380 	if (cm->cm_complete != NULL) {
2381 		mpr_dprint(sc, MPR_TRACE,
2382 		    "%s cm %p calling cm_complete %p data %p reply %p\n",
2383 		    __func__, cm, cm->cm_complete, cm->cm_complete_data,
2384 		    cm->cm_reply);
2385 		cm->cm_complete(sc, cm);
2386 	}
2387 
2388 	if (cm->cm_flags & MPR_CM_FLAGS_WAKEUP) {
2389 		mpr_dprint(sc, MPR_TRACE, "waking up %p\n", cm);
2390 		wakeup(cm);
2391 	}
2392 
2393 	if (sc->io_cmds_active != 0) {
2394 		sc->io_cmds_active--;
2395 	} else {
2396 		mpr_dprint(sc, MPR_ERROR, "Warning: io_cmds_active is "
2397 		    "out of sync - resynching to 0\n");
2398 	}
2399 }
2400 
2401 static void
2402 mpr_sas_log_info(struct mpr_softc *sc , u32 log_info)
2403 {
2404 	union loginfo_type {
2405 		u32	loginfo;
2406 		struct {
2407 			u32	subcode:16;
2408 			u32	code:8;
2409 			u32	originator:4;
2410 			u32	bus_type:4;
2411 		} dw;
2412 	};
2413 	union loginfo_type sas_loginfo;
2414 	char *originator_str = NULL;
2415 
2416 	sas_loginfo.loginfo = log_info;
2417 	if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
2418 		return;
2419 
2420 	/* each nexus loss loginfo */
2421 	if (log_info == 0x31170000)
2422 		return;
2423 
2424 	/* eat the loginfos associated with task aborts */
2425 	if ((log_info == 30050000) || (log_info == 0x31140000) ||
2426 	    (log_info == 0x31130000))
2427 		return;
2428 
2429 	switch (sas_loginfo.dw.originator) {
2430 	case 0:
2431 		originator_str = "IOP";
2432 		break;
2433 	case 1:
2434 		originator_str = "PL";
2435 		break;
2436 	case 2:
2437 		originator_str = "IR";
2438 		break;
2439 	}
2440 
2441 	mpr_dprint(sc, MPR_LOG, "log_info(0x%08x): originator(%s), "
2442 	    "code(0x%02x), sub_code(0x%04x)\n", log_info, originator_str,
2443 	    sas_loginfo.dw.code, sas_loginfo.dw.subcode);
2444 }
2445 
2446 static void
2447 mpr_display_reply_info(struct mpr_softc *sc, uint8_t *reply)
2448 {
2449 	MPI2DefaultReply_t *mpi_reply;
2450 	u16 sc_status;
2451 
2452 	mpi_reply = (MPI2DefaultReply_t*)reply;
2453 	sc_status = le16toh(mpi_reply->IOCStatus);
2454 	if (sc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE)
2455 		mpr_sas_log_info(sc, le32toh(mpi_reply->IOCLogInfo));
2456 }
2457 
2458 void
2459 mpr_intr(void *data)
2460 {
2461 	struct mpr_softc *sc;
2462 	uint32_t status;
2463 
2464 	sc = (struct mpr_softc *)data;
2465 	mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
2466 
2467 	/*
2468 	 * Check interrupt status register to flush the bus.  This is
2469 	 * needed for both INTx interrupts and driver-driven polling
2470 	 */
2471 	status = mpr_regread(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET);
2472 	if ((status & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT) == 0)
2473 		return;
2474 
2475 	mpr_lock(sc);
2476 	mpr_intr_locked(data);
2477 	mpr_unlock(sc);
2478 	return;
2479 }
2480 
2481 /*
2482  * In theory, MSI/MSIX interrupts shouldn't need to read any registers on the
2483  * chip.  Hopefully this theory is correct.
2484  */
2485 void
2486 mpr_intr_msi(void *data)
2487 {
2488 	struct mpr_softc *sc;
2489 
2490 	sc = (struct mpr_softc *)data;
2491 	mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
2492 	mpr_lock(sc);
2493 	mpr_intr_locked(data);
2494 	mpr_unlock(sc);
2495 	return;
2496 }
2497 
2498 /*
2499  * The locking is overly broad and simplistic, but easy to deal with for now.
2500  */
2501 void
2502 mpr_intr_locked(void *data)
2503 {
2504 	MPI2_REPLY_DESCRIPTORS_UNION *desc;
2505 	MPI2_DIAG_RELEASE_REPLY *rel_rep;
2506 	mpr_fw_diagnostic_buffer_t *pBuffer;
2507 	struct mpr_softc *sc;
2508 	uint64_t tdesc;
2509 	struct mpr_command *cm = NULL;
2510 	uint8_t flags;
2511 	u_int pq;
2512 
2513 	sc = (struct mpr_softc *)data;
2514 
2515 	pq = sc->replypostindex;
2516 	mpr_dprint(sc, MPR_TRACE,
2517 	    "%s sc %p starting with replypostindex %u\n",
2518 	    __func__, sc, sc->replypostindex);
2519 
2520 	for ( ;; ) {
2521 		cm = NULL;
2522 		desc = &sc->post_queue[sc->replypostindex];
2523 
2524 		/*
2525 		 * Copy and clear out the descriptor so that any reentry will
2526 		 * immediately know that this descriptor has already been
2527 		 * looked at.  There is unfortunate casting magic because the
2528 		 * MPI API doesn't have a cardinal 64bit type.
2529 		 */
2530 		tdesc = 0xffffffffffffffff;
2531 		tdesc = atomic_swap_64((uint64_t *)desc, tdesc);
2532 		desc = (MPI2_REPLY_DESCRIPTORS_UNION *)&tdesc;
2533 
2534 		flags = desc->Default.ReplyFlags &
2535 		    MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
2536 		if ((flags == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) ||
2537 		    (le32toh(desc->Words.High) == 0xffffffff))
2538 			break;
2539 
2540 		/* increment the replypostindex now, so that event handlers
2541 		 * and cm completion handlers which decide to do a diag
2542 		 * reset can zero it without it getting incremented again
2543 		 * afterwards, and we break out of this loop on the next
2544 		 * iteration since the reply post queue has been cleared to
2545 		 * 0xFF and all descriptors look unused (which they are).
2546 		 */
2547 		if (++sc->replypostindex >= sc->pqdepth)
2548 			sc->replypostindex = 0;
2549 
2550 		switch (flags) {
2551 		case MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS:
2552 		case MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS:
2553 		case MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS:
2554 			cm = &sc->commands[le16toh(desc->SCSIIOSuccess.SMID)];
2555 			cm->cm_reply = NULL;
2556 			break;
2557 		case MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY:
2558 		{
2559 			uint32_t baddr;
2560 			uint8_t *reply;
2561 
2562 			/*
2563 			 * Re-compose the reply address from the address
2564 			 * sent back from the chip.  The ReplyFrameAddress
2565 			 * is the lower 32 bits of the physical address of
2566 			 * particular reply frame.  Convert that address to
2567 			 * host format, and then use that to provide the
2568 			 * offset against the virtual address base
2569 			 * (sc->reply_frames).
2570 			 */
2571 			baddr = le32toh(desc->AddressReply.ReplyFrameAddress);
2572 			reply = sc->reply_frames +
2573 				(baddr - ((uint32_t)sc->reply_busaddr));
2574 			/*
2575 			 * Make sure the reply we got back is in a valid
2576 			 * range.  If not, go ahead and panic here, since
2577 			 * we'll probably panic as soon as we deference the
2578 			 * reply pointer anyway.
2579 			 */
2580 			if ((reply < sc->reply_frames)
2581 			 || (reply > (sc->reply_frames +
2582 			     (sc->fqdepth * sc->replyframesz)))) {
2583 				printf("%s: WARNING: reply %p out of range!\n",
2584 				       __func__, reply);
2585 				printf("%s: reply_frames %p, fqdepth %d, "
2586 				       "frame size %d\n", __func__,
2587 				       sc->reply_frames, sc->fqdepth,
2588 				       sc->replyframesz);
2589 				printf("%s: baddr %#x,\n", __func__, baddr);
2590 				/* LSI-TODO. See Linux Code for Graceful exit */
2591 				panic("Reply address out of range");
2592 			}
2593 			if (le16toh(desc->AddressReply.SMID) == 0) {
2594 				if (((MPI2_DEFAULT_REPLY *)reply)->Function ==
2595 				    MPI2_FUNCTION_DIAG_BUFFER_POST) {
2596 					/*
2597 					 * If SMID is 0 for Diag Buffer Post,
2598 					 * this implies that the reply is due to
2599 					 * a release function with a status that
2600 					 * the buffer has been released.  Set
2601 					 * the buffer flags accordingly.
2602 					 */
2603 					rel_rep =
2604 					    (MPI2_DIAG_RELEASE_REPLY *)reply;
2605 					if ((le16toh(rel_rep->IOCStatus) &
2606 					    MPI2_IOCSTATUS_MASK) ==
2607 					    MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED)
2608 					{
2609 						pBuffer =
2610 						    &sc->fw_diag_buffer_list[
2611 						    rel_rep->BufferType];
2612 						pBuffer->valid_data = TRUE;
2613 						pBuffer->owned_by_firmware =
2614 						    FALSE;
2615 						pBuffer->immediate = FALSE;
2616 					}
2617 				} else
2618 					mpr_dispatch_event(sc, baddr,
2619 					    (MPI2_EVENT_NOTIFICATION_REPLY *)
2620 					    reply);
2621 			} else {
2622 				cm = &sc->commands[
2623 				    le16toh(desc->AddressReply.SMID)];
2624 				if (cm->cm_state == MPR_CM_STATE_INQUEUE) {
2625 					cm->cm_reply = reply;
2626 					cm->cm_reply_data =
2627 					    le32toh(desc->AddressReply.
2628 						ReplyFrameAddress);
2629 				} else {
2630 					mpr_dprint(sc, MPR_RECOVERY,
2631 					    "Bad state for ADDRESS_REPLY status,"
2632 					    " ignoring state %d cm %p\n",
2633 					    cm->cm_state, cm);
2634 				}
2635 			}
2636 			break;
2637 		}
2638 		case MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS:
2639 		case MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER:
2640 		case MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS:
2641 		default:
2642 			/* Unhandled */
2643 			mpr_dprint(sc, MPR_ERROR, "Unhandled reply 0x%x\n",
2644 			    desc->Default.ReplyFlags);
2645 			cm = NULL;
2646 			break;
2647 		}
2648 
2649 		if (cm != NULL) {
2650 			// Print Error reply frame
2651 			if (cm->cm_reply)
2652 				mpr_display_reply_info(sc,cm->cm_reply);
2653 			mpr_complete_command(sc, cm);
2654 		}
2655 	}
2656 
2657 	if (pq != sc->replypostindex) {
2658 		mpr_dprint(sc, MPR_TRACE, "%s sc %p writing postindex %d\n",
2659 		    __func__, sc, sc->replypostindex);
2660 		mpr_regwrite(sc, MPI2_REPLY_POST_HOST_INDEX_OFFSET,
2661 		    sc->replypostindex);
2662 	}
2663 
2664 	return;
2665 }
2666 
2667 static void
2668 mpr_dispatch_event(struct mpr_softc *sc, uintptr_t data,
2669     MPI2_EVENT_NOTIFICATION_REPLY *reply)
2670 {
2671 	struct mpr_event_handle *eh;
2672 	int event, handled = 0;
2673 
2674 	event = le16toh(reply->Event);
2675 	TAILQ_FOREACH(eh, &sc->event_list, eh_list) {
2676 		if (isset(eh->mask, event)) {
2677 			eh->callback(sc, data, reply);
2678 			handled++;
2679 		}
2680 	}
2681 
2682 	if (handled == 0)
2683 		mpr_dprint(sc, MPR_EVENT, "Unhandled event 0x%x\n",
2684 		    le16toh(event));
2685 
2686 	/*
2687 	 * This is the only place that the event/reply should be freed.
2688 	 * Anything wanting to hold onto the event data should have
2689 	 * already copied it into their own storage.
2690 	 */
2691 	mpr_free_reply(sc, data);
2692 }
2693 
2694 static void
2695 mpr_reregister_events_complete(struct mpr_softc *sc, struct mpr_command *cm)
2696 {
2697 	mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
2698 
2699 	if (cm->cm_reply)
2700 		MPR_DPRINT_EVENT(sc, generic,
2701 			(MPI2_EVENT_NOTIFICATION_REPLY *)cm->cm_reply);
2702 
2703 	mpr_free_command(sc, cm);
2704 
2705 	/* next, send a port enable */
2706 	mprsas_startup(sc);
2707 }
2708 
2709 /*
2710  * For both register_events and update_events, the caller supplies a bitmap
2711  * of events that it _wants_.  These functions then turn that into a bitmask
2712  * suitable for the controller.
2713  */
2714 int
2715 mpr_register_events(struct mpr_softc *sc, uint8_t *mask,
2716     mpr_evt_callback_t *cb, void *data, struct mpr_event_handle **handle)
2717 {
2718 	struct mpr_event_handle *eh;
2719 	int error = 0;
2720 
2721 	eh = malloc(sizeof(struct mpr_event_handle), M_MPR, M_WAITOK|M_ZERO);
2722 	eh->callback = cb;
2723 	eh->data = data;
2724 	TAILQ_INSERT_TAIL(&sc->event_list, eh, eh_list);
2725 	if (mask != NULL)
2726 		error = mpr_update_events(sc, eh, mask);
2727 	*handle = eh;
2728 
2729 	return (error);
2730 }
2731 
2732 int
2733 mpr_update_events(struct mpr_softc *sc, struct mpr_event_handle *handle,
2734     uint8_t *mask)
2735 {
2736 	MPI2_EVENT_NOTIFICATION_REQUEST *evtreq;
2737 	MPI2_EVENT_NOTIFICATION_REPLY *reply = NULL;
2738 	struct mpr_command *cm = NULL;
2739 	struct mpr_event_handle *eh;
2740 	int error, i;
2741 
2742 	mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
2743 
2744 	if ((mask != NULL) && (handle != NULL))
2745 		bcopy(mask, &handle->mask[0], 16);
2746 	memset(sc->event_mask, 0xff, 16);
2747 
2748 	TAILQ_FOREACH(eh, &sc->event_list, eh_list) {
2749 		for (i = 0; i < 16; i++)
2750 			sc->event_mask[i] &= ~eh->mask[i];
2751 	}
2752 
2753 	if ((cm = mpr_alloc_command(sc)) == NULL)
2754 		return (EBUSY);
2755 	evtreq = (MPI2_EVENT_NOTIFICATION_REQUEST *)cm->cm_req;
2756 	evtreq->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
2757 	evtreq->MsgFlags = 0;
2758 	evtreq->SASBroadcastPrimitiveMasks = 0;
2759 #ifdef MPR_DEBUG_ALL_EVENTS
2760 	{
2761 		u_char fullmask[16];
2762 		memset(fullmask, 0x00, 16);
2763 		bcopy(fullmask, (uint8_t *)&evtreq->EventMasks, 16);
2764 	}
2765 #else
2766 	for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
2767 		evtreq->EventMasks[i] = htole32(sc->event_mask[i]);
2768 #endif
2769 	cm->cm_desc.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
2770 	cm->cm_data = NULL;
2771 
2772 	error = mpr_request_polled(sc, &cm);
2773 	if (cm != NULL)
2774 		reply = (MPI2_EVENT_NOTIFICATION_REPLY *)cm->cm_reply;
2775 	if ((reply == NULL) ||
2776 	    (reply->IOCStatus & MPI2_IOCSTATUS_MASK) != MPI2_IOCSTATUS_SUCCESS)
2777 		error = ENXIO;
2778 
2779 	if (reply)
2780 		MPR_DPRINT_EVENT(sc, generic, reply);
2781 
2782 	mpr_dprint(sc, MPR_TRACE, "%s finished error %d\n", __func__, error);
2783 
2784 	if (cm != NULL)
2785 		mpr_free_command(sc, cm);
2786 	return (error);
2787 }
2788 
2789 static int
2790 mpr_reregister_events(struct mpr_softc *sc)
2791 {
2792 	MPI2_EVENT_NOTIFICATION_REQUEST *evtreq;
2793 	struct mpr_command *cm;
2794 	struct mpr_event_handle *eh;
2795 	int error, i;
2796 
2797 	mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
2798 
2799 	/* first, reregister events */
2800 
2801 	memset(sc->event_mask, 0xff, 16);
2802 
2803 	TAILQ_FOREACH(eh, &sc->event_list, eh_list) {
2804 		for (i = 0; i < 16; i++)
2805 			sc->event_mask[i] &= ~eh->mask[i];
2806 	}
2807 
2808 	if ((cm = mpr_alloc_command(sc)) == NULL)
2809 		return (EBUSY);
2810 	evtreq = (MPI2_EVENT_NOTIFICATION_REQUEST *)cm->cm_req;
2811 	evtreq->Function = MPI2_FUNCTION_EVENT_NOTIFICATION;
2812 	evtreq->MsgFlags = 0;
2813 	evtreq->SASBroadcastPrimitiveMasks = 0;
2814 #ifdef MPR_DEBUG_ALL_EVENTS
2815 	{
2816 		u_char fullmask[16];
2817 		memset(fullmask, 0x00, 16);
2818 		bcopy(fullmask, (uint8_t *)&evtreq->EventMasks, 16);
2819 	}
2820 #else
2821 	for (i = 0; i < MPI2_EVENT_NOTIFY_EVENTMASK_WORDS; i++)
2822 		evtreq->EventMasks[i] = htole32(sc->event_mask[i]);
2823 #endif
2824 	cm->cm_desc.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
2825 	cm->cm_data = NULL;
2826 	cm->cm_complete = mpr_reregister_events_complete;
2827 
2828 	error = mpr_map_command(sc, cm);
2829 
2830 	mpr_dprint(sc, MPR_TRACE, "%s finished with error %d\n", __func__,
2831 	    error);
2832 	return (error);
2833 }
2834 
2835 int
2836 mpr_deregister_events(struct mpr_softc *sc, struct mpr_event_handle *handle)
2837 {
2838 
2839 	TAILQ_REMOVE(&sc->event_list, handle, eh_list);
2840 	free(handle, M_MPR);
2841 	return (mpr_update_events(sc, NULL, NULL));
2842 }
2843 
2844 /**
2845 * mpr_build_nvme_prp - This function is called for NVMe end devices to build a
2846 * native SGL (NVMe PRP). The native SGL is built starting in the first PRP entry
2847 * of the NVMe message (PRP1). If the data buffer is small enough to be described
2848 * entirely using PRP1, then PRP2 is not used. If needed, PRP2 is used to
2849 * describe a larger data buffer. If the data buffer is too large to describe
2850 * using the two PRP entriess inside the NVMe message, then PRP1 describes the
2851 * first data memory segment, and PRP2 contains a pointer to a PRP list located
2852 * elsewhere in memory to describe the remaining data memory segments. The PRP
2853 * list will be contiguous.
2854 
2855 * The native SGL for NVMe devices is a Physical Region Page (PRP). A PRP
2856 * consists of a list of PRP entries to describe a number of noncontigous
2857 * physical memory segments as a single memory buffer, just as a SGL does. Note
2858 * however, that this function is only used by the IOCTL call, so the memory
2859 * given will be guaranteed to be contiguous. There is no need to translate
2860 * non-contiguous SGL into a PRP in this case. All PRPs will describe contiguous
2861 * space that is one page size each.
2862 *
2863 * Each NVMe message contains two PRP entries. The first (PRP1) either contains
2864 * a PRP list pointer or a PRP element, depending upon the command. PRP2 contains
2865 * the second PRP element if the memory being described fits within 2 PRP
2866 * entries, or a PRP list pointer if the PRP spans more than two entries.
2867 *
2868 * A PRP list pointer contains the address of a PRP list, structured as a linear
2869 * array of PRP entries. Each PRP entry in this list describes a segment of
2870 * physical memory.
2871 *
2872 * Each 64-bit PRP entry comprises an address and an offset field. The address
2873 * always points to the beginning of a PAGE_SIZE physical memory page, and the
2874 * offset describes where within that page the memory segment begins. Only the
2875 * first element in a PRP list may contain a non-zero offest, implying that all
2876 * memory segments following the first begin at the start of a PAGE_SIZE page.
2877 *
2878 * Each PRP element normally describes a chunck of PAGE_SIZE physical memory,
2879 * with exceptions for the first and last elements in the list. If the memory
2880 * being described by the list begins at a non-zero offset within the first page,
2881 * then the first PRP element will contain a non-zero offset indicating where the
2882 * region begins within the page. The last memory segment may end before the end
2883 * of the PAGE_SIZE segment, depending upon the overall size of the memory being
2884 * described by the PRP list.
2885 *
2886 * Since PRP entries lack any indication of size, the overall data buffer length
2887 * is used to determine where the end of the data memory buffer is located, and
2888 * how many PRP entries are required to describe it.
2889 *
2890 * Returns nothing.
2891 */
2892 void
2893 mpr_build_nvme_prp(struct mpr_softc *sc, struct mpr_command *cm,
2894     Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request, void *data,
2895     uint32_t data_in_sz, uint32_t data_out_sz)
2896 {
2897 	int			prp_size = PRP_ENTRY_SIZE;
2898 	uint64_t		*prp_entry, *prp1_entry, *prp2_entry;
2899 	uint64_t		*prp_entry_phys, *prp_page, *prp_page_phys;
2900 	uint32_t		offset, entry_len, page_mask_result, page_mask;
2901 	bus_addr_t		paddr;
2902 	size_t			length;
2903 	struct mpr_prp_page	*prp_page_info = NULL;
2904 
2905 	/*
2906 	 * Not all commands require a data transfer. If no data, just return
2907 	 * without constructing any PRP.
2908 	 */
2909 	if (!data_in_sz && !data_out_sz)
2910 		return;
2911 
2912 	/*
2913 	 * Set pointers to PRP1 and PRP2, which are in the NVMe command. PRP1 is
2914 	 * located at a 24 byte offset from the start of the NVMe command. Then
2915 	 * set the current PRP entry pointer to PRP1.
2916 	 */
2917 	prp1_entry = (uint64_t *)(nvme_encap_request->NVMe_Command +
2918 	    NVME_CMD_PRP1_OFFSET);
2919 	prp2_entry = (uint64_t *)(nvme_encap_request->NVMe_Command +
2920 	    NVME_CMD_PRP2_OFFSET);
2921 	prp_entry = prp1_entry;
2922 
2923 	/*
2924 	 * For the PRP entries, use the specially allocated buffer of
2925 	 * contiguous memory. PRP Page allocation failures should not happen
2926 	 * because there should be enough PRP page buffers to account for the
2927 	 * possible NVMe QDepth.
2928 	 */
2929 	prp_page_info = mpr_alloc_prp_page(sc);
2930 	KASSERT(prp_page_info != NULL, ("%s: There are no PRP Pages left to be "
2931 	    "used for building a native NVMe SGL.\n", __func__));
2932 	prp_page = (uint64_t *)prp_page_info->prp_page;
2933 	prp_page_phys = (uint64_t *)(uintptr_t)prp_page_info->prp_page_busaddr;
2934 
2935 	/*
2936 	 * Insert the allocated PRP page into the command's PRP page list. This
2937 	 * will be freed when the command is freed.
2938 	 */
2939 	TAILQ_INSERT_TAIL(&cm->cm_prp_page_list, prp_page_info, prp_page_link);
2940 
2941 	/*
2942 	 * Check if we are within 1 entry of a page boundary we don't want our
2943 	 * first entry to be a PRP List entry.
2944 	 */
2945 	page_mask = PAGE_SIZE - 1;
2946 	page_mask_result = (uintptr_t)((uint8_t *)prp_page + prp_size) &
2947 	    page_mask;
2948 	if (!page_mask_result)
2949 	{
2950 		/* Bump up to next page boundary. */
2951 		prp_page = (uint64_t *)((uint8_t *)prp_page + prp_size);
2952 		prp_page_phys = (uint64_t *)((uint8_t *)prp_page_phys +
2953 		    prp_size);
2954 	}
2955 
2956 	/*
2957 	 * Set PRP physical pointer, which initially points to the current PRP
2958 	 * DMA memory page.
2959 	 */
2960 	prp_entry_phys = prp_page_phys;
2961 
2962 	/* Get physical address and length of the data buffer. */
2963 	paddr = (bus_addr_t)(uintptr_t)data;
2964 	if (data_in_sz)
2965 		length = data_in_sz;
2966 	else
2967 		length = data_out_sz;
2968 
2969 	/* Loop while the length is not zero. */
2970 	while (length)
2971 	{
2972 		/*
2973 		 * Check if we need to put a list pointer here if we are at page
2974 		 * boundary - prp_size (8 bytes).
2975 		 */
2976 		page_mask_result = (uintptr_t)((uint8_t *)prp_entry_phys +
2977 		    prp_size) & page_mask;
2978 		if (!page_mask_result)
2979 		{
2980 			/*
2981 			 * This is the last entry in a PRP List, so we need to
2982 			 * put a PRP list pointer here. What this does is:
2983 			 *   - bump the current memory pointer to the next
2984 			 *     address, which will be the next full page.
2985 			 *   - set the PRP Entry to point to that page. This is
2986 			 *     now the PRP List pointer.
2987 			 *   - bump the PRP Entry pointer the start of the next
2988 			 *     page. Since all of this PRP memory is contiguous,
2989 			 *     no need to get a new page - it's just the next
2990 			 *     address.
2991 			 */
2992 			prp_entry_phys++;
2993 			*prp_entry =
2994 			    htole64((uint64_t)(uintptr_t)prp_entry_phys);
2995 			prp_entry++;
2996 		}
2997 
2998 		/* Need to handle if entry will be part of a page. */
2999 		offset = (uint32_t)paddr & page_mask;
3000 		entry_len = PAGE_SIZE - offset;
3001 
3002 		if (prp_entry == prp1_entry)
3003 		{
3004 			/*
3005 			 * Must fill in the first PRP pointer (PRP1) before
3006 			 * moving on.
3007 			 */
3008 			*prp1_entry = htole64((uint64_t)paddr);
3009 
3010 			/*
3011 			 * Now point to the second PRP entry within the
3012 			 * command (PRP2).
3013 			 */
3014 			prp_entry = prp2_entry;
3015 		}
3016 		else if (prp_entry == prp2_entry)
3017 		{
3018 			/*
3019 			 * Should the PRP2 entry be a PRP List pointer or just a
3020 			 * regular PRP pointer? If there is more than one more
3021 			 * page of data, must use a PRP List pointer.
3022 			 */
3023 			if (length > PAGE_SIZE)
3024 			{
3025 				/*
3026 				 * PRP2 will contain a PRP List pointer because
3027 				 * more PRP's are needed with this command. The
3028 				 * list will start at the beginning of the
3029 				 * contiguous buffer.
3030 				 */
3031 				*prp2_entry =
3032 				    htole64(
3033 				    (uint64_t)(uintptr_t)prp_entry_phys);
3034 
3035 				/*
3036 				 * The next PRP Entry will be the start of the
3037 				 * first PRP List.
3038 				 */
3039 				prp_entry = prp_page;
3040 			}
3041 			else
3042 			{
3043 				/*
3044 				 * After this, the PRP Entries are complete.
3045 				 * This command uses 2 PRP's and no PRP list.
3046 				 */
3047 				*prp2_entry = htole64((uint64_t)paddr);
3048 			}
3049 		}
3050 		else
3051 		{
3052 			/*
3053 			 * Put entry in list and bump the addresses.
3054 			 *
3055 			 * After PRP1 and PRP2 are filled in, this will fill in
3056 			 * all remaining PRP entries in a PRP List, one per each
3057 			 * time through the loop.
3058 			 */
3059 			*prp_entry = htole64((uint64_t)paddr);
3060 			prp_entry++;
3061 			prp_entry_phys++;
3062 		}
3063 
3064 		/*
3065 		 * Bump the phys address of the command's data buffer by the
3066 		 * entry_len.
3067 		 */
3068 		paddr += entry_len;
3069 
3070 		/* Decrement length accounting for last partial page. */
3071 		if (entry_len > length)
3072 			length = 0;
3073 		else
3074 			length -= entry_len;
3075 	}
3076 }
3077 
3078 /*
3079  * mpr_check_pcie_native_sgl - This function is called for PCIe end devices to
3080  * determine if the driver needs to build a native SGL. If so, that native SGL
3081  * is built in the contiguous buffers allocated especially for PCIe SGL
3082  * creation. If the driver will not build a native SGL, return TRUE and a
3083  * normal IEEE SGL will be built. Currently this routine supports NVMe devices
3084  * only.
3085  *
3086  * Returns FALSE (0) if native SGL was built, TRUE (1) if no SGL was built.
3087  */
3088 static int
3089 mpr_check_pcie_native_sgl(struct mpr_softc *sc, struct mpr_command *cm,
3090     bus_dma_segment_t *segs, int segs_left)
3091 {
3092 	uint32_t		i, sge_dwords, length, offset, entry_len;
3093 	uint32_t		num_entries, buff_len = 0, sges_in_segment;
3094 	uint32_t		page_mask, page_mask_result, *curr_buff;
3095 	uint32_t		*ptr_sgl, *ptr_first_sgl, first_page_offset;
3096 	uint32_t		first_page_data_size, end_residual;
3097 	uint64_t		*msg_phys;
3098 	bus_addr_t		paddr;
3099 	int			build_native_sgl = 0, first_prp_entry;
3100 	int			prp_size = PRP_ENTRY_SIZE;
3101 	Mpi25IeeeSgeChain64_t	*main_chain_element = NULL;
3102 	struct mpr_prp_page	*prp_page_info = NULL;
3103 
3104 	mpr_dprint(sc, MPR_TRACE, "%s\n", __func__);
3105 
3106 	/*
3107 	 * Add up the sizes of each segment length to get the total transfer
3108 	 * size, which will be checked against the Maximum Data Transfer Size.
3109 	 * If the data transfer length exceeds the MDTS for this device, just
3110 	 * return 1 so a normal IEEE SGL will be built. F/W will break the I/O
3111 	 * up into multiple I/O's. [nvme_mdts = 0 means unlimited]
3112 	 */
3113 	for (i = 0; i < segs_left; i++)
3114 		buff_len += htole32(segs[i].ds_len);
3115 	if ((cm->cm_targ->MDTS > 0) && (buff_len > cm->cm_targ->MDTS))
3116 		return 1;
3117 
3118 	/* Create page_mask (to get offset within page) */
3119 	page_mask = PAGE_SIZE - 1;
3120 
3121 	/*
3122 	 * Check if the number of elements exceeds the max number that can be
3123 	 * put in the main message frame (H/W can only translate an SGL that
3124 	 * is contained entirely in the main message frame).
3125 	 */
3126 	sges_in_segment = (sc->reqframesz -
3127 	    offsetof(Mpi25SCSIIORequest_t, SGL)) / sizeof(MPI25_SGE_IO_UNION);
3128 	if (segs_left > sges_in_segment)
3129 		build_native_sgl = 1;
3130 	else
3131 	{
3132 		/*
3133 		 * NVMe uses one PRP for each physical page (or part of physical
3134 		 * page).
3135 		 *    if 4 pages or less then IEEE is OK
3136 		 *    if > 5 pages then we need to build a native SGL
3137 		 *    if > 4 and <= 5 pages, then check the physical address of
3138 		 *      the first SG entry, then if this first size in the page
3139 		 *      is >= the residual beyond 4 pages then use IEEE,
3140 		 *      otherwise use native SGL
3141 		 */
3142 		if (buff_len > (PAGE_SIZE * 5))
3143 			build_native_sgl = 1;
3144 		else if ((buff_len > (PAGE_SIZE * 4)) &&
3145 		    (buff_len <= (PAGE_SIZE * 5)) )
3146 		{
3147 			msg_phys = (uint64_t *)(uintptr_t)segs[0].ds_addr;
3148 			first_page_offset =
3149 			    ((uint32_t)(uint64_t)(uintptr_t)msg_phys &
3150 			    page_mask);
3151 			first_page_data_size = PAGE_SIZE - first_page_offset;
3152 			end_residual = buff_len % PAGE_SIZE;
3153 
3154 			/*
3155 			 * If offset into first page pushes the end of the data
3156 			 * beyond end of the 5th page, we need the extra PRP
3157 			 * list.
3158 			 */
3159 			if (first_page_data_size < end_residual)
3160 				build_native_sgl = 1;
3161 
3162 			/*
3163 			 * Check if first SG entry size is < residual beyond 4
3164 			 * pages.
3165 			 */
3166 			if (htole32(segs[0].ds_len) <
3167 			    (buff_len - (PAGE_SIZE * 4)))
3168 				build_native_sgl = 1;
3169 		}
3170 	}
3171 
3172 	/* check if native SGL is needed */
3173 	if (!build_native_sgl)
3174 		return 1;
3175 
3176 	/*
3177 	 * Native SGL is needed.
3178 	 * Put a chain element in main message frame that points to the first
3179 	 * chain buffer.
3180 	 *
3181 	 * NOTE:  The ChainOffset field must be 0 when using a chain pointer to
3182 	 *        a native SGL.
3183 	 */
3184 
3185 	/* Set main message chain element pointer */
3186 	main_chain_element = (pMpi25IeeeSgeChain64_t)cm->cm_sge;
3187 
3188 	/*
3189 	 * For NVMe the chain element needs to be the 2nd SGL entry in the main
3190 	 * message.
3191 	 */
3192 	main_chain_element = (Mpi25IeeeSgeChain64_t *)
3193 	    ((uint8_t *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64));
3194 
3195 	/*
3196 	 * For the PRP entries, use the specially allocated buffer of
3197 	 * contiguous memory. PRP Page allocation failures should not happen
3198 	 * because there should be enough PRP page buffers to account for the
3199 	 * possible NVMe QDepth.
3200 	 */
3201 	prp_page_info = mpr_alloc_prp_page(sc);
3202 	KASSERT(prp_page_info != NULL, ("%s: There are no PRP Pages left to be "
3203 	    "used for building a native NVMe SGL.\n", __func__));
3204 	curr_buff = (uint32_t *)prp_page_info->prp_page;
3205 	msg_phys = (uint64_t *)(uintptr_t)prp_page_info->prp_page_busaddr;
3206 
3207 	/*
3208 	 * Insert the allocated PRP page into the command's PRP page list. This
3209 	 * will be freed when the command is freed.
3210 	 */
3211 	TAILQ_INSERT_TAIL(&cm->cm_prp_page_list, prp_page_info, prp_page_link);
3212 
3213 	/*
3214 	 * Check if we are within 1 entry of a page boundary we don't want our
3215 	 * first entry to be a PRP List entry.
3216 	 */
3217 	page_mask_result = (uintptr_t)((uint8_t *)curr_buff + prp_size) &
3218 	    page_mask;
3219 	if (!page_mask_result) {
3220 		/* Bump up to next page boundary. */
3221 		curr_buff = (uint32_t *)((uint8_t *)curr_buff + prp_size);
3222 		msg_phys = (uint64_t *)((uint8_t *)msg_phys + prp_size);
3223 	}
3224 
3225 	/* Fill in the chain element and make it an NVMe segment type. */
3226 	main_chain_element->Address.High =
3227 	    htole32((uint32_t)((uint64_t)(uintptr_t)msg_phys >> 32));
3228 	main_chain_element->Address.Low =
3229 	    htole32((uint32_t)(uintptr_t)msg_phys);
3230 	main_chain_element->NextChainOffset = 0;
3231 	main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
3232 	    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
3233 	    MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP;
3234 
3235 	/* Set SGL pointer to start of contiguous PCIe buffer. */
3236 	ptr_sgl = curr_buff;
3237 	sge_dwords = 2;
3238 	num_entries = 0;
3239 
3240 	/*
3241 	 * NVMe has a very convoluted PRP format. One PRP is required for each
3242 	 * page or partial page. We need to split up OS SG entries if they are
3243 	 * longer than one page or cross a page boundary. We also have to insert
3244 	 * a PRP list pointer entry as the last entry in each physical page of
3245 	 * the PRP list.
3246 	 *
3247 	 * NOTE: The first PRP "entry" is actually placed in the first SGL entry
3248 	 * in the main message in IEEE 64 format. The 2nd entry in the main
3249 	 * message is the chain element, and the rest of the PRP entries are
3250 	 * built in the contiguous PCIe buffer.
3251 	 */
3252 	first_prp_entry = 1;
3253 	ptr_first_sgl = (uint32_t *)cm->cm_sge;
3254 
3255 	for (i = 0; i < segs_left; i++) {
3256 		/* Get physical address and length of this SG entry. */
3257 		paddr = segs[i].ds_addr;
3258 		length = segs[i].ds_len;
3259 
3260 		/*
3261 		 * Check whether a given SGE buffer lies on a non-PAGED
3262 		 * boundary if this is not the first page. If so, this is not
3263 		 * expected so have FW build the SGL.
3264 		 */
3265 		if ((i != 0) && (((uint32_t)paddr & page_mask) != 0)) {
3266 			mpr_dprint(sc, MPR_ERROR, "Unaligned SGE while "
3267 			    "building NVMe PRPs, low address is 0x%x\n",
3268 			    (uint32_t)paddr);
3269 			return 1;
3270 		}
3271 
3272 		/* Apart from last SGE, if any other SGE boundary is not page
3273 		 * aligned then it means that hole exists. Existence of hole
3274 		 * leads to data corruption. So fallback to IEEE SGEs.
3275 		 */
3276 		if (i != (segs_left - 1)) {
3277 			if (((uint32_t)paddr + length) & page_mask) {
3278 				mpr_dprint(sc, MPR_ERROR, "Unaligned SGE "
3279 				    "boundary while building NVMe PRPs, low "
3280 				    "address: 0x%x and length: %u\n",
3281 				    (uint32_t)paddr, length);
3282 				return 1;
3283 			}
3284 		}
3285 
3286 		/* Loop while the length is not zero. */
3287 		while (length) {
3288 			/*
3289 			 * Check if we need to put a list pointer here if we are
3290 			 * at page boundary - prp_size.
3291 			 */
3292 			page_mask_result = (uintptr_t)((uint8_t *)ptr_sgl +
3293 			    prp_size) & page_mask;
3294 			if (!page_mask_result) {
3295 				/*
3296 				 * Need to put a PRP list pointer here.
3297 				 */
3298 				msg_phys = (uint64_t *)((uint8_t *)msg_phys +
3299 				    prp_size);
3300 				*ptr_sgl = htole32((uintptr_t)msg_phys);
3301 				*(ptr_sgl+1) = htole32((uint64_t)(uintptr_t)
3302 				    msg_phys >> 32);
3303 				ptr_sgl += sge_dwords;
3304 				num_entries++;
3305 			}
3306 
3307 			/* Need to handle if entry will be part of a page. */
3308 			offset = (uint32_t)paddr & page_mask;
3309 			entry_len = PAGE_SIZE - offset;
3310 			if (first_prp_entry) {
3311 				/*
3312 				 * Put IEEE entry in first SGE in main message.
3313 				 * (Simple element, System addr, not end of
3314 				 * list.)
3315 				 */
3316 				*ptr_first_sgl = htole32((uint32_t)paddr);
3317 				*(ptr_first_sgl + 1) =
3318 				    htole32((uint32_t)((uint64_t)paddr >> 32));
3319 				*(ptr_first_sgl + 2) = htole32(entry_len);
3320 				*(ptr_first_sgl + 3) = 0;
3321 
3322 				/* No longer the first PRP entry. */
3323 				first_prp_entry = 0;
3324 			} else {
3325 				/* Put entry in list. */
3326 				*ptr_sgl = htole32((uint32_t)paddr);
3327 				*(ptr_sgl + 1) =
3328 				    htole32((uint32_t)((uint64_t)paddr >> 32));
3329 
3330 				/* Bump ptr_sgl, msg_phys, and num_entries. */
3331 				ptr_sgl += sge_dwords;
3332 				msg_phys = (uint64_t *)((uint8_t *)msg_phys +
3333 				    prp_size);
3334 				num_entries++;
3335 			}
3336 
3337 			/* Bump the phys address by the entry_len. */
3338 			paddr += entry_len;
3339 
3340 			/* Decrement length accounting for last partial page. */
3341 			if (entry_len > length)
3342 				length = 0;
3343 			else
3344 				length -= entry_len;
3345 		}
3346 	}
3347 
3348 	/* Set chain element Length. */
3349 	main_chain_element->Length = htole32(num_entries * prp_size);
3350 
3351 	/* Return 0, indicating we built a native SGL. */
3352 	return 0;
3353 }
3354 
3355 /*
3356  * Add a chain element as the next SGE for the specified command.
3357  * Reset cm_sge and cm_sgesize to indicate all the available space. Chains are
3358  * only required for IEEE commands.  Therefore there is no code for commands
3359  * that have the MPR_CM_FLAGS_SGE_SIMPLE flag set (and those commands
3360  * shouldn't be requesting chains).
3361  */
3362 static int
3363 mpr_add_chain(struct mpr_command *cm, int segsleft)
3364 {
3365 	struct mpr_softc *sc = cm->cm_sc;
3366 	MPI2_REQUEST_HEADER *req;
3367 	MPI25_IEEE_SGE_CHAIN64 *ieee_sgc;
3368 	struct mpr_chain *chain;
3369 	int sgc_size, current_segs, rem_segs, segs_per_frame;
3370 	uint8_t next_chain_offset = 0;
3371 
3372 	/*
3373 	 * Fail if a command is requesting a chain for SIMPLE SGE's.  For SAS3
3374 	 * only IEEE commands should be requesting chains.  Return some error
3375 	 * code other than 0.
3376 	 */
3377 	if (cm->cm_flags & MPR_CM_FLAGS_SGE_SIMPLE) {
3378 		mpr_dprint(sc, MPR_ERROR, "A chain element cannot be added to "
3379 		    "an MPI SGL.\n");
3380 		return(ENOBUFS);
3381 	}
3382 
3383 	sgc_size = sizeof(MPI25_IEEE_SGE_CHAIN64);
3384 	if (cm->cm_sglsize < sgc_size)
3385 		panic("MPR: Need SGE Error Code\n");
3386 
3387 	chain = mpr_alloc_chain(cm->cm_sc);
3388 	if (chain == NULL)
3389 		return (ENOBUFS);
3390 
3391 	/*
3392 	 * Note: a double-linked list is used to make it easier to walk for
3393 	 * debugging.
3394 	 */
3395 	TAILQ_INSERT_TAIL(&cm->cm_chain_list, chain, chain_link);
3396 
3397 	/*
3398 	 * Need to know if the number of frames left is more than 1 or not.  If
3399 	 * more than 1 frame is required, NextChainOffset will need to be set,
3400 	 * which will just be the last segment of the frame.
3401 	 */
3402 	rem_segs = 0;
3403 	if (cm->cm_sglsize < (sgc_size * segsleft)) {
3404 		/*
3405 		 * rem_segs is the number of segements remaining after the
3406 		 * segments that will go into the current frame.  Since it is
3407 		 * known that at least one more frame is required, account for
3408 		 * the chain element.  To know if more than one more frame is
3409 		 * required, just check if there will be a remainder after using
3410 		 * the current frame (with this chain) and the next frame.  If
3411 		 * so the NextChainOffset must be the last element of the next
3412 		 * frame.
3413 		 */
3414 		current_segs = (cm->cm_sglsize / sgc_size) - 1;
3415 		rem_segs = segsleft - current_segs;
3416 		segs_per_frame = sc->chain_frame_size / sgc_size;
3417 		if (rem_segs > segs_per_frame) {
3418 			next_chain_offset = segs_per_frame - 1;
3419 		}
3420 	}
3421 	ieee_sgc = &((MPI25_SGE_IO_UNION *)cm->cm_sge)->IeeeChain;
3422 	ieee_sgc->Length = next_chain_offset ?
3423 	    htole32((uint32_t)sc->chain_frame_size) :
3424 	    htole32((uint32_t)rem_segs * (uint32_t)sgc_size);
3425 	ieee_sgc->NextChainOffset = next_chain_offset;
3426 	ieee_sgc->Flags = (MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
3427 	    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
3428 	ieee_sgc->Address.Low = htole32(chain->chain_busaddr);
3429 	ieee_sgc->Address.High = htole32(chain->chain_busaddr >> 32);
3430 	cm->cm_sge = &((MPI25_SGE_IO_UNION *)chain->chain)->IeeeSimple;
3431 	req = (MPI2_REQUEST_HEADER *)cm->cm_req;
3432 	req->ChainOffset = (sc->chain_frame_size - sgc_size) >> 4;
3433 
3434 	cm->cm_sglsize = sc->chain_frame_size;
3435 	return (0);
3436 }
3437 
3438 /*
3439  * Add one scatter-gather element to the scatter-gather list for a command.
3440  * Maintain cm_sglsize and cm_sge as the remaining size and pointer to the
3441  * next SGE to fill in, respectively.  In Gen3, the MPI SGL does not have a
3442  * chain, so don't consider any chain additions.
3443  */
3444 int
3445 mpr_push_sge(struct mpr_command *cm, MPI2_SGE_SIMPLE64 *sge, size_t len,
3446     int segsleft)
3447 {
3448 	uint32_t saved_buf_len, saved_address_low, saved_address_high;
3449 	u32 sge_flags;
3450 
3451 	/*
3452 	 * case 1: >=1 more segment, no room for anything (error)
3453 	 * case 2: 1 more segment and enough room for it
3454          */
3455 
3456 	if (cm->cm_sglsize < (segsleft * sizeof(MPI2_SGE_SIMPLE64))) {
3457 		mpr_dprint(cm->cm_sc, MPR_ERROR,
3458 		    "%s: warning: Not enough room for MPI SGL in frame.\n",
3459 		    __func__);
3460 		return(ENOBUFS);
3461 	}
3462 
3463 	KASSERT(segsleft == 1,
3464 	    ("segsleft cannot be more than 1 for an MPI SGL; segsleft = %d\n",
3465 	    segsleft));
3466 
3467 	/*
3468 	 * There is one more segment left to add for the MPI SGL and there is
3469 	 * enough room in the frame to add it.  This is the normal case because
3470 	 * MPI SGL's don't have chains, otherwise something is wrong.
3471 	 *
3472 	 * If this is a bi-directional request, need to account for that
3473 	 * here.  Save the pre-filled sge values.  These will be used
3474 	 * either for the 2nd SGL or for a single direction SGL.  If
3475 	 * cm_out_len is non-zero, this is a bi-directional request, so
3476 	 * fill in the OUT SGL first, then the IN SGL, otherwise just
3477 	 * fill in the IN SGL.  Note that at this time, when filling in
3478 	 * 2 SGL's for a bi-directional request, they both use the same
3479 	 * DMA buffer (same cm command).
3480 	 */
3481 	saved_buf_len = sge->FlagsLength & 0x00FFFFFF;
3482 	saved_address_low = sge->Address.Low;
3483 	saved_address_high = sge->Address.High;
3484 	if (cm->cm_out_len) {
3485 		sge->FlagsLength = cm->cm_out_len |
3486 		    ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
3487 		    MPI2_SGE_FLAGS_END_OF_BUFFER |
3488 		    MPI2_SGE_FLAGS_HOST_TO_IOC |
3489 		    MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
3490 		    MPI2_SGE_FLAGS_SHIFT);
3491 		cm->cm_sglsize -= len;
3492 		/* Endian Safe code */
3493 		sge_flags = sge->FlagsLength;
3494 		sge->FlagsLength = htole32(sge_flags);
3495 		bcopy(sge, cm->cm_sge, len);
3496 		cm->cm_sge = (MPI2_SGE_IO_UNION *)((uintptr_t)cm->cm_sge + len);
3497 	}
3498 	sge->FlagsLength = saved_buf_len |
3499 	    ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
3500 	    MPI2_SGE_FLAGS_END_OF_BUFFER |
3501 	    MPI2_SGE_FLAGS_LAST_ELEMENT |
3502 	    MPI2_SGE_FLAGS_END_OF_LIST |
3503 	    MPI2_SGE_FLAGS_64_BIT_ADDRESSING) <<
3504 	    MPI2_SGE_FLAGS_SHIFT);
3505 	if (cm->cm_flags & MPR_CM_FLAGS_DATAIN) {
3506 		sge->FlagsLength |=
3507 		    ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) <<
3508 		    MPI2_SGE_FLAGS_SHIFT);
3509 	} else {
3510 		sge->FlagsLength |=
3511 		    ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) <<
3512 		    MPI2_SGE_FLAGS_SHIFT);
3513 	}
3514 	sge->Address.Low = saved_address_low;
3515 	sge->Address.High = saved_address_high;
3516 
3517 	cm->cm_sglsize -= len;
3518 	/* Endian Safe code */
3519 	sge_flags = sge->FlagsLength;
3520 	sge->FlagsLength = htole32(sge_flags);
3521 	bcopy(sge, cm->cm_sge, len);
3522 	cm->cm_sge = (MPI2_SGE_IO_UNION *)((uintptr_t)cm->cm_sge + len);
3523 	return (0);
3524 }
3525 
3526 /*
3527  * Add one IEEE scatter-gather element (chain or simple) to the IEEE scatter-
3528  * gather list for a command.  Maintain cm_sglsize and cm_sge as the
3529  * remaining size and pointer to the next SGE to fill in, respectively.
3530  */
3531 int
3532 mpr_push_ieee_sge(struct mpr_command *cm, void *sgep, int segsleft)
3533 {
3534 	MPI2_IEEE_SGE_SIMPLE64 *sge = sgep;
3535 	int error, ieee_sge_size = sizeof(MPI25_SGE_IO_UNION);
3536 	uint32_t saved_buf_len, saved_address_low, saved_address_high;
3537 	uint32_t sge_length;
3538 
3539 	/*
3540 	 * case 1: No room for chain or segment (error).
3541 	 * case 2: Two or more segments left but only room for chain.
3542 	 * case 3: Last segment and room for it, so set flags.
3543 	 */
3544 
3545 	/*
3546 	 * There should be room for at least one element, or there is a big
3547 	 * problem.
3548 	 */
3549 	if (cm->cm_sglsize < ieee_sge_size)
3550 		panic("MPR: Need SGE Error Code\n");
3551 
3552 	if ((segsleft >= 2) && (cm->cm_sglsize < (ieee_sge_size * 2))) {
3553 		if ((error = mpr_add_chain(cm, segsleft)) != 0)
3554 			return (error);
3555 	}
3556 
3557 	if (segsleft == 1) {
3558 		/*
3559 		 * If this is a bi-directional request, need to account for that
3560 		 * here.  Save the pre-filled sge values.  These will be used
3561 		 * either for the 2nd SGL or for a single direction SGL.  If
3562 		 * cm_out_len is non-zero, this is a bi-directional request, so
3563 		 * fill in the OUT SGL first, then the IN SGL, otherwise just
3564 		 * fill in the IN SGL.  Note that at this time, when filling in
3565 		 * 2 SGL's for a bi-directional request, they both use the same
3566 		 * DMA buffer (same cm command).
3567 		 */
3568 		saved_buf_len = sge->Length;
3569 		saved_address_low = sge->Address.Low;
3570 		saved_address_high = sge->Address.High;
3571 		if (cm->cm_out_len) {
3572 			sge->Length = cm->cm_out_len;
3573 			sge->Flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
3574 			    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
3575 			cm->cm_sglsize -= ieee_sge_size;
3576 			/* Endian Safe code */
3577 			sge_length = sge->Length;
3578 			sge->Length = htole32(sge_length);
3579 			bcopy(sgep, cm->cm_sge, ieee_sge_size);
3580 			cm->cm_sge =
3581 			    (MPI25_SGE_IO_UNION *)((uintptr_t)cm->cm_sge +
3582 			    ieee_sge_size);
3583 		}
3584 		sge->Length = saved_buf_len;
3585 		sge->Flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
3586 		    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
3587 		    MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
3588 		sge->Address.Low = saved_address_low;
3589 		sge->Address.High = saved_address_high;
3590 	}
3591 
3592 	cm->cm_sglsize -= ieee_sge_size;
3593 	/* Endian Safe code */
3594 	sge_length = sge->Length;
3595 	sge->Length = htole32(sge_length);
3596 	bcopy(sgep, cm->cm_sge, ieee_sge_size);
3597 	cm->cm_sge = (MPI25_SGE_IO_UNION *)((uintptr_t)cm->cm_sge +
3598 	    ieee_sge_size);
3599 	return (0);
3600 }
3601 
3602 /*
3603  * Add one dma segment to the scatter-gather list for a command.
3604  */
3605 int
3606 mpr_add_dmaseg(struct mpr_command *cm, vm_paddr_t pa, size_t len, u_int flags,
3607     int segsleft)
3608 {
3609 	MPI2_SGE_SIMPLE64 sge;
3610 	MPI2_IEEE_SGE_SIMPLE64 ieee_sge;
3611 
3612 	if (!(cm->cm_flags & MPR_CM_FLAGS_SGE_SIMPLE)) {
3613 		ieee_sge.Flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
3614 		    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR);
3615 		ieee_sge.Length = len;
3616 		mpr_from_u64(pa, &ieee_sge.Address);
3617 
3618 		return (mpr_push_ieee_sge(cm, &ieee_sge, segsleft));
3619 	} else {
3620 		/*
3621 		 * This driver always uses 64-bit address elements for
3622 		 * simplicity.
3623 		 */
3624 		flags |= MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
3625 		    MPI2_SGE_FLAGS_64_BIT_ADDRESSING;
3626 		/* Set Endian safe macro in mpr_push_sge */
3627 		sge.FlagsLength = len | (flags << MPI2_SGE_FLAGS_SHIFT);
3628 		mpr_from_u64(pa, &sge.Address);
3629 
3630 		return (mpr_push_sge(cm, &sge, sizeof sge, segsleft));
3631 	}
3632 }
3633 
3634 static void
3635 mpr_data_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
3636 {
3637 	struct mpr_softc *sc;
3638 	struct mpr_command *cm;
3639 	u_int i, dir, sflags;
3640 
3641 	cm = (struct mpr_command *)arg;
3642 	sc = cm->cm_sc;
3643 
3644 	/*
3645 	 * In this case, just print out a warning and let the chip tell the
3646 	 * user they did the wrong thing.
3647 	 */
3648 	if ((cm->cm_max_segs != 0) && (nsegs > cm->cm_max_segs)) {
3649 		mpr_dprint(sc, MPR_ERROR, "%s: warning: busdma returned %d "
3650 		    "segments, more than the %d allowed\n", __func__, nsegs,
3651 		    cm->cm_max_segs);
3652 	}
3653 
3654 	/*
3655 	 * Set up DMA direction flags.  Bi-directional requests are also handled
3656 	 * here.  In that case, both direction flags will be set.
3657 	 */
3658 	sflags = 0;
3659 	if (cm->cm_flags & MPR_CM_FLAGS_SMP_PASS) {
3660 		/*
3661 		 * We have to add a special case for SMP passthrough, there
3662 		 * is no easy way to generically handle it.  The first
3663 		 * S/G element is used for the command (therefore the
3664 		 * direction bit needs to be set).  The second one is used
3665 		 * for the reply.  We'll leave it to the caller to make
3666 		 * sure we only have two buffers.
3667 		 */
3668 		/*
3669 		 * Even though the busdma man page says it doesn't make
3670 		 * sense to have both direction flags, it does in this case.
3671 		 * We have one s/g element being accessed in each direction.
3672 		 */
3673 		dir = BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD;
3674 
3675 		/*
3676 		 * Set the direction flag on the first buffer in the SMP
3677 		 * passthrough request.  We'll clear it for the second one.
3678 		 */
3679 		sflags |= MPI2_SGE_FLAGS_DIRECTION |
3680 			  MPI2_SGE_FLAGS_END_OF_BUFFER;
3681 	} else if (cm->cm_flags & MPR_CM_FLAGS_DATAOUT) {
3682 		sflags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
3683 		dir = BUS_DMASYNC_PREWRITE;
3684 	} else
3685 		dir = BUS_DMASYNC_PREREAD;
3686 
3687 	/* Check if a native SG list is needed for an NVMe PCIe device. */
3688 	if (cm->cm_targ && cm->cm_targ->is_nvme &&
3689 	    mpr_check_pcie_native_sgl(sc, cm, segs, nsegs) == 0) {
3690 		/* A native SG list was built, skip to end. */
3691 		goto out;
3692 	}
3693 
3694 	for (i = 0; i < nsegs; i++) {
3695 		if ((cm->cm_flags & MPR_CM_FLAGS_SMP_PASS) && (i != 0)) {
3696 			sflags &= ~MPI2_SGE_FLAGS_DIRECTION;
3697 		}
3698 		error = mpr_add_dmaseg(cm, segs[i].ds_addr, segs[i].ds_len,
3699 		    sflags, nsegs - i);
3700 		if (error != 0) {
3701 			/* Resource shortage, roll back! */
3702 			if (ratecheck(&sc->lastfail, &mpr_chainfail_interval))
3703 				mpr_dprint(sc, MPR_INFO, "Out of chain frames, "
3704 				    "consider increasing hw.mpr.max_chains.\n");
3705 			cm->cm_flags |= MPR_CM_FLAGS_CHAIN_FAILED;
3706 			cm->cm_state = MPR_CM_STATE_INQUEUE;
3707 			mpr_complete_command(sc, cm);
3708 			return;
3709 		}
3710 	}
3711 
3712 out:
3713 	bus_dmamap_sync(sc->buffer_dmat, cm->cm_dmamap, dir);
3714 	mpr_enqueue_request(sc, cm);
3715 
3716 	return;
3717 }
3718 
3719 static void
3720 mpr_data_cb2(void *arg, bus_dma_segment_t *segs, int nsegs, bus_size_t mapsize,
3721 	     int error)
3722 {
3723 	mpr_data_cb(arg, segs, nsegs, error);
3724 }
3725 
3726 /*
3727  * This is the routine to enqueue commands ansynchronously.
3728  * Note that the only error path here is from bus_dmamap_load(), which can
3729  * return EINPROGRESS if it is waiting for resources.  Other than this, it's
3730  * assumed that if you have a command in-hand, then you have enough credits
3731  * to use it.
3732  */
3733 int
3734 mpr_map_command(struct mpr_softc *sc, struct mpr_command *cm)
3735 {
3736 	int error = 0;
3737 
3738 	if (cm->cm_flags & MPR_CM_FLAGS_USE_UIO) {
3739 		error = bus_dmamap_load_uio(sc->buffer_dmat, cm->cm_dmamap,
3740 		    &cm->cm_uio, mpr_data_cb2, cm, 0);
3741 	} else if (cm->cm_flags & MPR_CM_FLAGS_USE_CCB) {
3742 		error = bus_dmamap_load_ccb(sc->buffer_dmat, cm->cm_dmamap,
3743 		    cm->cm_data, mpr_data_cb, cm, 0);
3744 	} else if ((cm->cm_data != NULL) && (cm->cm_length != 0)) {
3745 		error = bus_dmamap_load(sc->buffer_dmat, cm->cm_dmamap,
3746 		    cm->cm_data, cm->cm_length, mpr_data_cb, cm, 0);
3747 	} else {
3748 		/* Add a zero-length element as needed */
3749 		if (cm->cm_sge != NULL)
3750 			mpr_add_dmaseg(cm, 0, 0, 0, 1);
3751 		mpr_enqueue_request(sc, cm);
3752 	}
3753 
3754 	return (error);
3755 }
3756 
3757 /*
3758  * This is the routine to enqueue commands synchronously.  An error of
3759  * EINPROGRESS from mpr_map_command() is ignored since the command will
3760  * be executed and enqueued automatically.  Other errors come from msleep().
3761  */
3762 int
3763 mpr_wait_command(struct mpr_softc *sc, struct mpr_command **cmp, int timeout,
3764     int sleep_flag)
3765 {
3766 	int error, rc;
3767 	struct timeval cur_time, start_time;
3768 	struct mpr_command *cm = *cmp;
3769 
3770 	if (sc->mpr_flags & MPR_FLAGS_DIAGRESET)
3771 		return  EBUSY;
3772 
3773 	cm->cm_complete = NULL;
3774 	cm->cm_flags |= (MPR_CM_FLAGS_WAKEUP + MPR_CM_FLAGS_POLLED);
3775 	error = mpr_map_command(sc, cm);
3776 	if ((error != 0) && (error != EINPROGRESS))
3777 		return (error);
3778 
3779 	// Check for context and wait for 50 mSec at a time until time has
3780 	// expired or the command has finished.  If msleep can't be used, need
3781 	// to poll.
3782 	if (curthread->td_no_sleeping)
3783 		sleep_flag = NO_SLEEP;
3784 	getmicrouptime(&start_time);
3785 	if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP) {
3786 		error = msleep(cm, &sc->mpr_mtx, 0, "mprwait", timeout*hz);
3787 		if (error == EWOULDBLOCK) {
3788 			/*
3789 			 * Record the actual elapsed time in the case of a
3790 			 * timeout for the message below.
3791 			 */
3792 			getmicrouptime(&cur_time);
3793 			timevalsub(&cur_time, &start_time);
3794 		}
3795 	} else {
3796 		while ((cm->cm_flags & MPR_CM_FLAGS_COMPLETE) == 0) {
3797 			mpr_intr_locked(sc);
3798 			if (sleep_flag == CAN_SLEEP)
3799 				pause("mprwait", hz/20);
3800 			else
3801 				DELAY(50000);
3802 
3803 			getmicrouptime(&cur_time);
3804 			timevalsub(&cur_time, &start_time);
3805 			if (cur_time.tv_sec > timeout) {
3806 				error = EWOULDBLOCK;
3807 				break;
3808 			}
3809 		}
3810 	}
3811 
3812 	if (error == EWOULDBLOCK) {
3813 		if (cm->cm_timeout_handler == NULL) {
3814 			mpr_dprint(sc, MPR_FAULT, "Calling Reinit from %s, timeout=%d,"
3815 			    " elapsed=%jd\n", __func__, timeout,
3816 			    (intmax_t)cur_time.tv_sec);
3817 			rc = mpr_reinit(sc);
3818 			mpr_dprint(sc, MPR_FAULT, "Reinit %s\n", (rc == 0) ? "success" :
3819 			    "failed");
3820 		} else
3821 			cm->cm_timeout_handler(sc, cm);
3822 		if (sc->mpr_flags & MPR_FLAGS_REALLOCATED) {
3823 			/*
3824 			 * Tell the caller that we freed the command in a
3825 			 * reinit.
3826 			 */
3827 			*cmp = NULL;
3828 		}
3829 		error = ETIMEDOUT;
3830 	}
3831 	return (error);
3832 }
3833 
3834 /*
3835  * This is the routine to enqueue a command synchonously and poll for
3836  * completion.  Its use should be rare.
3837  */
3838 int
3839 mpr_request_polled(struct mpr_softc *sc, struct mpr_command **cmp)
3840 {
3841 	int error, rc;
3842 	struct timeval cur_time, start_time;
3843 	struct mpr_command *cm = *cmp;
3844 
3845 	error = 0;
3846 
3847 	cm->cm_flags |= MPR_CM_FLAGS_POLLED;
3848 	cm->cm_complete = NULL;
3849 	mpr_map_command(sc, cm);
3850 
3851 	getmicrouptime(&start_time);
3852 	while ((cm->cm_flags & MPR_CM_FLAGS_COMPLETE) == 0) {
3853 		mpr_intr_locked(sc);
3854 
3855 		if (mtx_owned(&sc->mpr_mtx))
3856 			msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0,
3857 			    "mprpoll", hz/20);
3858 		else
3859 			pause("mprpoll", hz/20);
3860 
3861 		/*
3862 		 * Check for real-time timeout and fail if more than 60 seconds.
3863 		 */
3864 		getmicrouptime(&cur_time);
3865 		timevalsub(&cur_time, &start_time);
3866 		if (cur_time.tv_sec > 60) {
3867 			mpr_dprint(sc, MPR_FAULT, "polling failed\n");
3868 			error = ETIMEDOUT;
3869 			break;
3870 		}
3871 	}
3872 	cm->cm_state = MPR_CM_STATE_BUSY;
3873 	if (error) {
3874 		mpr_dprint(sc, MPR_FAULT, "Calling Reinit from %s\n", __func__);
3875 		rc = mpr_reinit(sc);
3876 		mpr_dprint(sc, MPR_FAULT, "Reinit %s\n", (rc == 0) ? "success" :
3877 		    "failed");
3878 
3879 		if (sc->mpr_flags & MPR_FLAGS_REALLOCATED) {
3880 			/*
3881 			 * Tell the caller that we freed the command in a
3882 			 * reinit.
3883 			 */
3884 			*cmp = NULL;
3885 		}
3886 	}
3887 	return (error);
3888 }
3889 
3890 /*
3891  * The MPT driver had a verbose interface for config pages.  In this driver,
3892  * reduce it to much simpler terms, similar to the Linux driver.
3893  */
3894 int
3895 mpr_read_config_page(struct mpr_softc *sc, struct mpr_config_params *params)
3896 {
3897 	MPI2_CONFIG_REQUEST *req;
3898 	struct mpr_command *cm;
3899 	int error;
3900 
3901 	if (sc->mpr_flags & MPR_FLAGS_BUSY) {
3902 		return (EBUSY);
3903 	}
3904 
3905 	cm = mpr_alloc_command(sc);
3906 	if (cm == NULL) {
3907 		return (EBUSY);
3908 	}
3909 
3910 	req = (MPI2_CONFIG_REQUEST *)cm->cm_req;
3911 	req->Function = MPI2_FUNCTION_CONFIG;
3912 	req->Action = params->action;
3913 	req->SGLFlags = 0;
3914 	req->ChainOffset = 0;
3915 	req->PageAddress = params->page_address;
3916 	if (params->hdr.Struct.PageType == MPI2_CONFIG_PAGETYPE_EXTENDED) {
3917 		MPI2_CONFIG_EXTENDED_PAGE_HEADER *hdr;
3918 
3919 		hdr = &params->hdr.Ext;
3920 		req->ExtPageType = hdr->ExtPageType;
3921 		req->ExtPageLength = hdr->ExtPageLength;
3922 		req->Header.PageType = MPI2_CONFIG_PAGETYPE_EXTENDED;
3923 		req->Header.PageLength = 0; /* Must be set to zero */
3924 		req->Header.PageNumber = hdr->PageNumber;
3925 		req->Header.PageVersion = hdr->PageVersion;
3926 	} else {
3927 		MPI2_CONFIG_PAGE_HEADER *hdr;
3928 
3929 		hdr = &params->hdr.Struct;
3930 		req->Header.PageType = hdr->PageType;
3931 		req->Header.PageNumber = hdr->PageNumber;
3932 		req->Header.PageLength = hdr->PageLength;
3933 		req->Header.PageVersion = hdr->PageVersion;
3934 	}
3935 
3936 	cm->cm_data = params->buffer;
3937 	cm->cm_length = params->length;
3938 	if (cm->cm_data != NULL) {
3939 		cm->cm_sge = &req->PageBufferSGE;
3940 		cm->cm_sglsize = sizeof(MPI2_SGE_IO_UNION);
3941 		cm->cm_flags = MPR_CM_FLAGS_SGE_SIMPLE | MPR_CM_FLAGS_DATAIN;
3942 	} else
3943 		cm->cm_sge = NULL;
3944 	cm->cm_desc.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
3945 
3946 	cm->cm_complete_data = params;
3947 	if (params->callback != NULL) {
3948 		cm->cm_complete = mpr_config_complete;
3949 		return (mpr_map_command(sc, cm));
3950 	} else {
3951 		error = mpr_wait_command(sc, &cm, 0, CAN_SLEEP);
3952 		if (error) {
3953 			mpr_dprint(sc, MPR_FAULT,
3954 			    "Error %d reading config page\n", error);
3955 			if (cm != NULL)
3956 				mpr_free_command(sc, cm);
3957 			return (error);
3958 		}
3959 		mpr_config_complete(sc, cm);
3960 	}
3961 
3962 	return (0);
3963 }
3964 
3965 int
3966 mpr_write_config_page(struct mpr_softc *sc, struct mpr_config_params *params)
3967 {
3968 	return (EINVAL);
3969 }
3970 
3971 static void
3972 mpr_config_complete(struct mpr_softc *sc, struct mpr_command *cm)
3973 {
3974 	MPI2_CONFIG_REPLY *reply;
3975 	struct mpr_config_params *params;
3976 
3977 	MPR_FUNCTRACE(sc);
3978 	params = cm->cm_complete_data;
3979 
3980 	if (cm->cm_data != NULL) {
3981 		bus_dmamap_sync(sc->buffer_dmat, cm->cm_dmamap,
3982 		    BUS_DMASYNC_POSTREAD);
3983 		bus_dmamap_unload(sc->buffer_dmat, cm->cm_dmamap);
3984 	}
3985 
3986 	/*
3987 	 * XXX KDM need to do more error recovery?  This results in the
3988 	 * device in question not getting probed.
3989 	 */
3990 	if ((cm->cm_flags & MPR_CM_FLAGS_ERROR_MASK) != 0) {
3991 		params->status = MPI2_IOCSTATUS_BUSY;
3992 		goto done;
3993 	}
3994 
3995 	reply = (MPI2_CONFIG_REPLY *)cm->cm_reply;
3996 	if (reply == NULL) {
3997 		params->status = MPI2_IOCSTATUS_BUSY;
3998 		goto done;
3999 	}
4000 	params->status = reply->IOCStatus;
4001 	if (params->hdr.Struct.PageType == MPI2_CONFIG_PAGETYPE_EXTENDED) {
4002 		params->hdr.Ext.ExtPageType = reply->ExtPageType;
4003 		params->hdr.Ext.ExtPageLength = reply->ExtPageLength;
4004 		params->hdr.Ext.PageType = reply->Header.PageType;
4005 		params->hdr.Ext.PageNumber = reply->Header.PageNumber;
4006 		params->hdr.Ext.PageVersion = reply->Header.PageVersion;
4007 	} else {
4008 		params->hdr.Struct.PageType = reply->Header.PageType;
4009 		params->hdr.Struct.PageNumber = reply->Header.PageNumber;
4010 		params->hdr.Struct.PageLength = reply->Header.PageLength;
4011 		params->hdr.Struct.PageVersion = reply->Header.PageVersion;
4012 	}
4013 
4014 done:
4015 	mpr_free_command(sc, cm);
4016 	if (params->callback != NULL)
4017 		params->callback(sc, params);
4018 
4019 	return;
4020 }
4021