1 /*- 2 * Copyright (c) 2009 Yahoo! Inc. 3 * Copyright (c) 2011-2015 LSI Corp. 4 * Copyright (c) 2013-2016 Avago Technologies 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD 29 * 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* Communications core for Avago Technologies (LSI) MPT3 */ 36 37 /* TODO Move headers to mprvar */ 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/kernel.h> 42 #include <sys/selinfo.h> 43 #include <sys/lock.h> 44 #include <sys/mutex.h> 45 #include <sys/module.h> 46 #include <sys/bus.h> 47 #include <sys/conf.h> 48 #include <sys/bio.h> 49 #include <sys/malloc.h> 50 #include <sys/uio.h> 51 #include <sys/sysctl.h> 52 #include <sys/smp.h> 53 #include <sys/queue.h> 54 #include <sys/kthread.h> 55 #include <sys/taskqueue.h> 56 #include <sys/endian.h> 57 #include <sys/eventhandler.h> 58 #include <sys/sbuf.h> 59 60 #include <machine/bus.h> 61 #include <machine/resource.h> 62 #include <sys/rman.h> 63 #include <sys/proc.h> 64 65 #include <dev/pci/pcivar.h> 66 67 #include <cam/cam.h> 68 #include <cam/cam_ccb.h> 69 #include <cam/scsi/scsi_all.h> 70 71 #include <dev/mpr/mpi/mpi2_type.h> 72 #include <dev/mpr/mpi/mpi2.h> 73 #include <dev/mpr/mpi/mpi2_ioc.h> 74 #include <dev/mpr/mpi/mpi2_sas.h> 75 #include <dev/mpr/mpi/mpi2_pci.h> 76 #include <dev/mpr/mpi/mpi2_cnfg.h> 77 #include <dev/mpr/mpi/mpi2_init.h> 78 #include <dev/mpr/mpi/mpi2_tool.h> 79 #include <dev/mpr/mpr_ioctl.h> 80 #include <dev/mpr/mprvar.h> 81 #include <dev/mpr/mpr_table.h> 82 #include <dev/mpr/mpr_sas.h> 83 84 static int mpr_diag_reset(struct mpr_softc *sc, int sleep_flag); 85 static int mpr_init_queues(struct mpr_softc *sc); 86 static void mpr_resize_queues(struct mpr_softc *sc); 87 static int mpr_message_unit_reset(struct mpr_softc *sc, int sleep_flag); 88 static int mpr_transition_operational(struct mpr_softc *sc); 89 static int mpr_iocfacts_allocate(struct mpr_softc *sc, uint8_t attaching); 90 static void mpr_iocfacts_free(struct mpr_softc *sc); 91 static void mpr_startup(void *arg); 92 static int mpr_send_iocinit(struct mpr_softc *sc); 93 static int mpr_alloc_queues(struct mpr_softc *sc); 94 static int mpr_alloc_hw_queues(struct mpr_softc *sc); 95 static int mpr_alloc_replies(struct mpr_softc *sc); 96 static int mpr_alloc_requests(struct mpr_softc *sc); 97 static int mpr_alloc_nvme_prp_pages(struct mpr_softc *sc); 98 static int mpr_attach_log(struct mpr_softc *sc); 99 static __inline void mpr_complete_command(struct mpr_softc *sc, 100 struct mpr_command *cm); 101 static void mpr_dispatch_event(struct mpr_softc *sc, uintptr_t data, 102 MPI2_EVENT_NOTIFICATION_REPLY *reply); 103 static void mpr_config_complete(struct mpr_softc *sc, struct mpr_command *cm); 104 static void mpr_periodic(void *); 105 static int mpr_reregister_events(struct mpr_softc *sc); 106 static void mpr_enqueue_request(struct mpr_softc *sc, struct mpr_command *cm); 107 static int mpr_get_iocfacts(struct mpr_softc *sc, MPI2_IOC_FACTS_REPLY *facts); 108 static int mpr_wait_db_ack(struct mpr_softc *sc, int timeout, int sleep_flag); 109 static int mpr_debug_sysctl(SYSCTL_HANDLER_ARGS); 110 static void mpr_parse_debug(struct mpr_softc *sc, char *list); 111 112 SYSCTL_NODE(_hw, OID_AUTO, mpr, CTLFLAG_RD, 0, "MPR Driver Parameters"); 113 114 MALLOC_DEFINE(M_MPR, "mpr", "mpr driver memory"); 115 116 /* 117 * Do a "Diagnostic Reset" aka a hard reset. This should get the chip out of 118 * any state and back to its initialization state machine. 119 */ 120 static char mpt2_reset_magic[] = { 0x00, 0x0f, 0x04, 0x0b, 0x02, 0x07, 0x0d }; 121 122 /* 123 * Added this union to smoothly convert le64toh cm->cm_desc.Words. 124 * Compiler only supports uint64_t to be passed as an argument. 125 * Otherwise it will throw this error: 126 * "aggregate value used where an integer was expected" 127 */ 128 typedef union _reply_descriptor { 129 u64 word; 130 struct { 131 u32 low; 132 u32 high; 133 } u; 134 } reply_descriptor, request_descriptor; 135 136 /* Rate limit chain-fail messages to 1 per minute */ 137 static struct timeval mpr_chainfail_interval = { 60, 0 }; 138 139 /* 140 * sleep_flag can be either CAN_SLEEP or NO_SLEEP. 141 * If this function is called from process context, it can sleep 142 * and there is no harm to sleep, in case if this fuction is called 143 * from Interrupt handler, we can not sleep and need NO_SLEEP flag set. 144 * based on sleep flags driver will call either msleep, pause or DELAY. 145 * msleep and pause are of same variant, but pause is used when mpr_mtx 146 * is not hold by driver. 147 */ 148 static int 149 mpr_diag_reset(struct mpr_softc *sc,int sleep_flag) 150 { 151 uint32_t reg; 152 int i, error, tries = 0; 153 uint8_t first_wait_done = FALSE; 154 155 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 156 157 /* Clear any pending interrupts */ 158 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 159 160 /* 161 * Force NO_SLEEP for threads prohibited to sleep 162 * e.a Thread from interrupt handler are prohibited to sleep. 163 */ 164 #if __FreeBSD_version >= 1000029 165 if (curthread->td_no_sleeping) 166 #else //__FreeBSD_version < 1000029 167 if (curthread->td_pflags & TDP_NOSLEEPING) 168 #endif //__FreeBSD_version >= 1000029 169 sleep_flag = NO_SLEEP; 170 171 mpr_dprint(sc, MPR_INIT, "sequence start, sleep_flag=%d\n", sleep_flag); 172 /* Push the magic sequence */ 173 error = ETIMEDOUT; 174 while (tries++ < 20) { 175 for (i = 0; i < sizeof(mpt2_reset_magic); i++) 176 mpr_regwrite(sc, MPI2_WRITE_SEQUENCE_OFFSET, 177 mpt2_reset_magic[i]); 178 179 /* wait 100 msec */ 180 if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP) 181 msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0, 182 "mprdiag", hz/10); 183 else if (sleep_flag == CAN_SLEEP) 184 pause("mprdiag", hz/10); 185 else 186 DELAY(100 * 1000); 187 188 reg = mpr_regread(sc, MPI2_HOST_DIAGNOSTIC_OFFSET); 189 if (reg & MPI2_DIAG_DIAG_WRITE_ENABLE) { 190 error = 0; 191 break; 192 } 193 } 194 if (error) { 195 mpr_dprint(sc, MPR_INIT, "sequence failed, error=%d, exit\n", 196 error); 197 return (error); 198 } 199 200 /* Send the actual reset. XXX need to refresh the reg? */ 201 reg |= MPI2_DIAG_RESET_ADAPTER; 202 mpr_dprint(sc, MPR_INIT, "sequence success, sending reset, reg= 0x%x\n", 203 reg); 204 mpr_regwrite(sc, MPI2_HOST_DIAGNOSTIC_OFFSET, reg); 205 206 /* Wait up to 300 seconds in 50ms intervals */ 207 error = ETIMEDOUT; 208 for (i = 0; i < 6000; i++) { 209 /* 210 * Wait 50 msec. If this is the first time through, wait 256 211 * msec to satisfy Diag Reset timing requirements. 212 */ 213 if (first_wait_done) { 214 if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP) 215 msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0, 216 "mprdiag", hz/20); 217 else if (sleep_flag == CAN_SLEEP) 218 pause("mprdiag", hz/20); 219 else 220 DELAY(50 * 1000); 221 } else { 222 DELAY(256 * 1000); 223 first_wait_done = TRUE; 224 } 225 /* 226 * Check for the RESET_ADAPTER bit to be cleared first, then 227 * wait for the RESET state to be cleared, which takes a little 228 * longer. 229 */ 230 reg = mpr_regread(sc, MPI2_HOST_DIAGNOSTIC_OFFSET); 231 if (reg & MPI2_DIAG_RESET_ADAPTER) { 232 continue; 233 } 234 reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET); 235 if ((reg & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_RESET) { 236 error = 0; 237 break; 238 } 239 } 240 if (error) { 241 mpr_dprint(sc, MPR_INIT, "reset failed, error= %d, exit\n", 242 error); 243 return (error); 244 } 245 246 mpr_regwrite(sc, MPI2_WRITE_SEQUENCE_OFFSET, 0x0); 247 mpr_dprint(sc, MPR_INIT, "diag reset success, exit\n"); 248 249 return (0); 250 } 251 252 static int 253 mpr_message_unit_reset(struct mpr_softc *sc, int sleep_flag) 254 { 255 int error; 256 257 MPR_FUNCTRACE(sc); 258 259 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 260 261 error = 0; 262 mpr_regwrite(sc, MPI2_DOORBELL_OFFSET, 263 MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET << 264 MPI2_DOORBELL_FUNCTION_SHIFT); 265 266 if (mpr_wait_db_ack(sc, 5, sleep_flag) != 0) { 267 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 268 "Doorbell handshake failed\n"); 269 error = ETIMEDOUT; 270 } 271 272 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__); 273 return (error); 274 } 275 276 static int 277 mpr_transition_ready(struct mpr_softc *sc) 278 { 279 uint32_t reg, state; 280 int error, tries = 0; 281 int sleep_flags; 282 283 MPR_FUNCTRACE(sc); 284 /* If we are in attach call, do not sleep */ 285 sleep_flags = (sc->mpr_flags & MPR_FLAGS_ATTACH_DONE) 286 ? CAN_SLEEP : NO_SLEEP; 287 288 error = 0; 289 290 mpr_dprint(sc, MPR_INIT, "%s entered, sleep_flags= %d\n", 291 __func__, sleep_flags); 292 293 while (tries++ < 1200) { 294 reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET); 295 mpr_dprint(sc, MPR_INIT, " Doorbell= 0x%x\n", reg); 296 297 /* 298 * Ensure the IOC is ready to talk. If it's not, try 299 * resetting it. 300 */ 301 if (reg & MPI2_DOORBELL_USED) { 302 mpr_dprint(sc, MPR_INIT, " Not ready, sending diag " 303 "reset\n"); 304 mpr_diag_reset(sc, sleep_flags); 305 DELAY(50000); 306 continue; 307 } 308 309 /* Is the adapter owned by another peer? */ 310 if ((reg & MPI2_DOORBELL_WHO_INIT_MASK) == 311 (MPI2_WHOINIT_PCI_PEER << MPI2_DOORBELL_WHO_INIT_SHIFT)) { 312 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "IOC is under the " 313 "control of another peer host, aborting " 314 "initialization.\n"); 315 error = ENXIO; 316 break; 317 } 318 319 state = reg & MPI2_IOC_STATE_MASK; 320 if (state == MPI2_IOC_STATE_READY) { 321 /* Ready to go! */ 322 error = 0; 323 break; 324 } else if (state == MPI2_IOC_STATE_FAULT) { 325 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "IOC in fault " 326 "state 0x%x, resetting\n", 327 state & MPI2_DOORBELL_FAULT_CODE_MASK); 328 mpr_diag_reset(sc, sleep_flags); 329 } else if (state == MPI2_IOC_STATE_OPERATIONAL) { 330 /* Need to take ownership */ 331 mpr_message_unit_reset(sc, sleep_flags); 332 } else if (state == MPI2_IOC_STATE_RESET) { 333 /* Wait a bit, IOC might be in transition */ 334 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 335 "IOC in unexpected reset state\n"); 336 } else { 337 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 338 "IOC in unknown state 0x%x\n", state); 339 error = EINVAL; 340 break; 341 } 342 343 /* Wait 50ms for things to settle down. */ 344 DELAY(50000); 345 } 346 347 if (error) 348 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 349 "Cannot transition IOC to ready\n"); 350 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__); 351 return (error); 352 } 353 354 static int 355 mpr_transition_operational(struct mpr_softc *sc) 356 { 357 uint32_t reg, state; 358 int error; 359 360 MPR_FUNCTRACE(sc); 361 362 error = 0; 363 reg = mpr_regread(sc, MPI2_DOORBELL_OFFSET); 364 mpr_dprint(sc, MPR_INIT, "%s entered, Doorbell= 0x%x\n", __func__, reg); 365 366 state = reg & MPI2_IOC_STATE_MASK; 367 if (state != MPI2_IOC_STATE_READY) { 368 mpr_dprint(sc, MPR_INIT, "IOC not ready\n"); 369 if ((error = mpr_transition_ready(sc)) != 0) { 370 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 371 "failed to transition ready, exit\n"); 372 return (error); 373 } 374 } 375 376 error = mpr_send_iocinit(sc); 377 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__); 378 379 return (error); 380 } 381 382 static void 383 mpr_resize_queues(struct mpr_softc *sc) 384 { 385 int reqcr, prireqcr; 386 387 /* 388 * Size the queues. Since the reply queues always need one free 389 * entry, we'll deduct one reply message here. The LSI documents 390 * suggest instead to add a count to the request queue, but I think 391 * that it's better to deduct from reply queue. 392 */ 393 prireqcr = MAX(1, sc->max_prireqframes); 394 prireqcr = MIN(prireqcr, sc->facts->HighPriorityCredit); 395 396 reqcr = MAX(2, sc->max_reqframes); 397 reqcr = MIN(reqcr, sc->facts->RequestCredit); 398 399 sc->num_reqs = prireqcr + reqcr; 400 sc->num_replies = MIN(sc->max_replyframes + sc->max_evtframes, 401 sc->facts->MaxReplyDescriptorPostQueueDepth) - 1; 402 403 /* 404 * Figure out the number of MSIx-based queues. If the firmware or 405 * user has done something crazy and not allowed enough credit for 406 * the queues to be useful then don't enable multi-queue. 407 */ 408 if (sc->facts->MaxMSIxVectors < 2) 409 sc->msi_msgs = 1; 410 411 if (sc->msi_msgs > 1) { 412 sc->msi_msgs = MIN(sc->msi_msgs, mp_ncpus); 413 sc->msi_msgs = MIN(sc->msi_msgs, sc->facts->MaxMSIxVectors); 414 if (sc->num_reqs / sc->msi_msgs < 2) 415 sc->msi_msgs = 1; 416 } 417 418 mpr_dprint(sc, MPR_INIT, "Sized queues to q=%d reqs=%d replies=%d\n", 419 sc->msi_msgs, sc->num_reqs, sc->num_replies); 420 } 421 422 /* 423 * This is called during attach and when re-initializing due to a Diag Reset. 424 * IOC Facts is used to allocate many of the structures needed by the driver. 425 * If called from attach, de-allocation is not required because the driver has 426 * not allocated any structures yet, but if called from a Diag Reset, previously 427 * allocated structures based on IOC Facts will need to be freed and re- 428 * allocated bases on the latest IOC Facts. 429 */ 430 static int 431 mpr_iocfacts_allocate(struct mpr_softc *sc, uint8_t attaching) 432 { 433 int error; 434 Mpi2IOCFactsReply_t saved_facts; 435 uint8_t saved_mode, reallocating; 436 437 mpr_dprint(sc, MPR_INIT|MPR_TRACE, "%s entered\n", __func__); 438 439 /* Save old IOC Facts and then only reallocate if Facts have changed */ 440 if (!attaching) { 441 bcopy(sc->facts, &saved_facts, sizeof(MPI2_IOC_FACTS_REPLY)); 442 } 443 444 /* 445 * Get IOC Facts. In all cases throughout this function, panic if doing 446 * a re-initialization and only return the error if attaching so the OS 447 * can handle it. 448 */ 449 if ((error = mpr_get_iocfacts(sc, sc->facts)) != 0) { 450 if (attaching) { 451 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "Failed to get " 452 "IOC Facts with error %d, exit\n", error); 453 return (error); 454 } else { 455 panic("%s failed to get IOC Facts with error %d\n", 456 __func__, error); 457 } 458 } 459 460 MPR_DPRINT_PAGE(sc, MPR_XINFO, iocfacts, sc->facts); 461 462 snprintf(sc->fw_version, sizeof(sc->fw_version), 463 "%02d.%02d.%02d.%02d", 464 sc->facts->FWVersion.Struct.Major, 465 sc->facts->FWVersion.Struct.Minor, 466 sc->facts->FWVersion.Struct.Unit, 467 sc->facts->FWVersion.Struct.Dev); 468 469 mpr_dprint(sc, MPR_INFO, "Firmware: %s, Driver: %s\n", sc->fw_version, 470 MPR_DRIVER_VERSION); 471 mpr_dprint(sc, MPR_INFO, 472 "IOCCapabilities: %b\n", sc->facts->IOCCapabilities, 473 "\20" "\3ScsiTaskFull" "\4DiagTrace" "\5SnapBuf" "\6ExtBuf" 474 "\7EEDP" "\10BiDirTarg" "\11Multicast" "\14TransRetry" "\15IR" 475 "\16EventReplay" "\17RaidAccel" "\20MSIXIndex" "\21HostDisc" 476 "\22FastPath" "\23RDPQArray" "\24AtomicReqDesc" "\25PCIeSRIOV"); 477 478 /* 479 * If the chip doesn't support event replay then a hard reset will be 480 * required to trigger a full discovery. Do the reset here then 481 * retransition to Ready. A hard reset might have already been done, 482 * but it doesn't hurt to do it again. Only do this if attaching, not 483 * for a Diag Reset. 484 */ 485 if (attaching && ((sc->facts->IOCCapabilities & 486 MPI2_IOCFACTS_CAPABILITY_EVENT_REPLAY) == 0)) { 487 mpr_dprint(sc, MPR_INIT, "No event replay, resetting\n"); 488 mpr_diag_reset(sc, NO_SLEEP); 489 if ((error = mpr_transition_ready(sc)) != 0) { 490 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "Failed to " 491 "transition to ready with error %d, exit\n", 492 error); 493 return (error); 494 } 495 } 496 497 /* 498 * Set flag if IR Firmware is loaded. If the RAID Capability has 499 * changed from the previous IOC Facts, log a warning, but only if 500 * checking this after a Diag Reset and not during attach. 501 */ 502 saved_mode = sc->ir_firmware; 503 if (sc->facts->IOCCapabilities & 504 MPI2_IOCFACTS_CAPABILITY_INTEGRATED_RAID) 505 sc->ir_firmware = 1; 506 if (!attaching) { 507 if (sc->ir_firmware != saved_mode) { 508 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "new IR/IT mode " 509 "in IOC Facts does not match previous mode\n"); 510 } 511 } 512 513 /* Only deallocate and reallocate if relevant IOC Facts have changed */ 514 reallocating = FALSE; 515 sc->mpr_flags &= ~MPR_FLAGS_REALLOCATED; 516 517 if ((!attaching) && 518 ((saved_facts.MsgVersion != sc->facts->MsgVersion) || 519 (saved_facts.HeaderVersion != sc->facts->HeaderVersion) || 520 (saved_facts.MaxChainDepth != sc->facts->MaxChainDepth) || 521 (saved_facts.RequestCredit != sc->facts->RequestCredit) || 522 (saved_facts.ProductID != sc->facts->ProductID) || 523 (saved_facts.IOCCapabilities != sc->facts->IOCCapabilities) || 524 (saved_facts.IOCRequestFrameSize != 525 sc->facts->IOCRequestFrameSize) || 526 (saved_facts.IOCMaxChainSegmentSize != 527 sc->facts->IOCMaxChainSegmentSize) || 528 (saved_facts.MaxTargets != sc->facts->MaxTargets) || 529 (saved_facts.MaxSasExpanders != sc->facts->MaxSasExpanders) || 530 (saved_facts.MaxEnclosures != sc->facts->MaxEnclosures) || 531 (saved_facts.HighPriorityCredit != sc->facts->HighPriorityCredit) || 532 (saved_facts.MaxReplyDescriptorPostQueueDepth != 533 sc->facts->MaxReplyDescriptorPostQueueDepth) || 534 (saved_facts.ReplyFrameSize != sc->facts->ReplyFrameSize) || 535 (saved_facts.MaxVolumes != sc->facts->MaxVolumes) || 536 (saved_facts.MaxPersistentEntries != 537 sc->facts->MaxPersistentEntries))) { 538 reallocating = TRUE; 539 540 /* Record that we reallocated everything */ 541 sc->mpr_flags |= MPR_FLAGS_REALLOCATED; 542 } 543 544 /* 545 * Some things should be done if attaching or re-allocating after a Diag 546 * Reset, but are not needed after a Diag Reset if the FW has not 547 * changed. 548 */ 549 if (attaching || reallocating) { 550 /* 551 * Check if controller supports FW diag buffers and set flag to 552 * enable each type. 553 */ 554 if (sc->facts->IOCCapabilities & 555 MPI2_IOCFACTS_CAPABILITY_DIAG_TRACE_BUFFER) 556 sc->fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_TRACE]. 557 enabled = TRUE; 558 if (sc->facts->IOCCapabilities & 559 MPI2_IOCFACTS_CAPABILITY_SNAPSHOT_BUFFER) 560 sc->fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_SNAPSHOT]. 561 enabled = TRUE; 562 if (sc->facts->IOCCapabilities & 563 MPI2_IOCFACTS_CAPABILITY_EXTENDED_BUFFER) 564 sc->fw_diag_buffer_list[MPI2_DIAG_BUF_TYPE_EXTENDED]. 565 enabled = TRUE; 566 567 /* 568 * Set flags for some supported items. 569 */ 570 if (sc->facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_EEDP) 571 sc->eedp_enabled = TRUE; 572 if (sc->facts->IOCCapabilities & MPI2_IOCFACTS_CAPABILITY_TLR) 573 sc->control_TLR = TRUE; 574 if (sc->facts->IOCCapabilities & 575 MPI26_IOCFACTS_CAPABILITY_ATOMIC_REQ) 576 sc->atomic_desc_capable = TRUE; 577 578 mpr_resize_queues(sc); 579 580 /* 581 * Initialize all Tail Queues 582 */ 583 TAILQ_INIT(&sc->req_list); 584 TAILQ_INIT(&sc->high_priority_req_list); 585 TAILQ_INIT(&sc->chain_list); 586 TAILQ_INIT(&sc->prp_page_list); 587 TAILQ_INIT(&sc->tm_list); 588 } 589 590 /* 591 * If doing a Diag Reset and the FW is significantly different 592 * (reallocating will be set above in IOC Facts comparison), then all 593 * buffers based on the IOC Facts will need to be freed before they are 594 * reallocated. 595 */ 596 if (reallocating) { 597 mpr_iocfacts_free(sc); 598 mprsas_realloc_targets(sc, saved_facts.MaxTargets + 599 saved_facts.MaxVolumes); 600 } 601 602 /* 603 * Any deallocation has been completed. Now start reallocating 604 * if needed. Will only need to reallocate if attaching or if the new 605 * IOC Facts are different from the previous IOC Facts after a Diag 606 * Reset. Targets have already been allocated above if needed. 607 */ 608 error = 0; 609 while (attaching || reallocating) { 610 if ((error = mpr_alloc_hw_queues(sc)) != 0) 611 break; 612 if ((error = mpr_alloc_replies(sc)) != 0) 613 break; 614 if ((error = mpr_alloc_requests(sc)) != 0) 615 break; 616 if ((error = mpr_alloc_queues(sc)) != 0) 617 break; 618 break; 619 } 620 if (error) { 621 mpr_dprint(sc, MPR_INIT|MPR_ERROR, 622 "Failed to alloc queues with error %d\n", error); 623 mpr_free(sc); 624 return (error); 625 } 626 627 /* Always initialize the queues */ 628 bzero(sc->free_queue, sc->fqdepth * 4); 629 mpr_init_queues(sc); 630 631 /* 632 * Always get the chip out of the reset state, but only panic if not 633 * attaching. If attaching and there is an error, that is handled by 634 * the OS. 635 */ 636 error = mpr_transition_operational(sc); 637 if (error != 0) { 638 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "Failed to " 639 "transition to operational with error %d\n", error); 640 mpr_free(sc); 641 return (error); 642 } 643 644 /* 645 * Finish the queue initialization. 646 * These are set here instead of in mpr_init_queues() because the 647 * IOC resets these values during the state transition in 648 * mpr_transition_operational(). The free index is set to 1 649 * because the corresponding index in the IOC is set to 0, and the 650 * IOC treats the queues as full if both are set to the same value. 651 * Hence the reason that the queue can't hold all of the possible 652 * replies. 653 */ 654 sc->replypostindex = 0; 655 mpr_regwrite(sc, MPI2_REPLY_FREE_HOST_INDEX_OFFSET, sc->replyfreeindex); 656 mpr_regwrite(sc, MPI2_REPLY_POST_HOST_INDEX_OFFSET, 0); 657 658 /* 659 * Attach the subsystems so they can prepare their event masks. 660 * XXX Should be dynamic so that IM/IR and user modules can attach 661 */ 662 error = 0; 663 while (attaching) { 664 mpr_dprint(sc, MPR_INIT, "Attaching subsystems\n"); 665 if ((error = mpr_attach_log(sc)) != 0) 666 break; 667 if ((error = mpr_attach_sas(sc)) != 0) 668 break; 669 if ((error = mpr_attach_user(sc)) != 0) 670 break; 671 break; 672 } 673 if (error) { 674 mpr_dprint(sc, MPR_INIT|MPR_ERROR, 675 "Failed to attach all subsystems: error %d\n", error); 676 mpr_free(sc); 677 return (error); 678 } 679 680 if ((error = mpr_pci_setup_interrupts(sc)) != 0) { 681 mpr_dprint(sc, MPR_INIT|MPR_ERROR, 682 "Failed to setup interrupts\n"); 683 mpr_free(sc); 684 return (error); 685 } 686 687 return (error); 688 } 689 690 /* 691 * This is called if memory is being free (during detach for example) and when 692 * buffers need to be reallocated due to a Diag Reset. 693 */ 694 static void 695 mpr_iocfacts_free(struct mpr_softc *sc) 696 { 697 struct mpr_command *cm; 698 int i; 699 700 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 701 702 if (sc->free_busaddr != 0) 703 bus_dmamap_unload(sc->queues_dmat, sc->queues_map); 704 if (sc->free_queue != NULL) 705 bus_dmamem_free(sc->queues_dmat, sc->free_queue, 706 sc->queues_map); 707 if (sc->queues_dmat != NULL) 708 bus_dma_tag_destroy(sc->queues_dmat); 709 710 if (sc->chain_busaddr != 0) 711 bus_dmamap_unload(sc->chain_dmat, sc->chain_map); 712 if (sc->chain_frames != NULL) 713 bus_dmamem_free(sc->chain_dmat, sc->chain_frames, 714 sc->chain_map); 715 if (sc->chain_dmat != NULL) 716 bus_dma_tag_destroy(sc->chain_dmat); 717 718 if (sc->sense_busaddr != 0) 719 bus_dmamap_unload(sc->sense_dmat, sc->sense_map); 720 if (sc->sense_frames != NULL) 721 bus_dmamem_free(sc->sense_dmat, sc->sense_frames, 722 sc->sense_map); 723 if (sc->sense_dmat != NULL) 724 bus_dma_tag_destroy(sc->sense_dmat); 725 726 if (sc->prp_page_busaddr != 0) 727 bus_dmamap_unload(sc->prp_page_dmat, sc->prp_page_map); 728 if (sc->prp_pages != NULL) 729 bus_dmamem_free(sc->prp_page_dmat, sc->prp_pages, 730 sc->prp_page_map); 731 if (sc->prp_page_dmat != NULL) 732 bus_dma_tag_destroy(sc->prp_page_dmat); 733 734 if (sc->reply_busaddr != 0) 735 bus_dmamap_unload(sc->reply_dmat, sc->reply_map); 736 if (sc->reply_frames != NULL) 737 bus_dmamem_free(sc->reply_dmat, sc->reply_frames, 738 sc->reply_map); 739 if (sc->reply_dmat != NULL) 740 bus_dma_tag_destroy(sc->reply_dmat); 741 742 if (sc->req_busaddr != 0) 743 bus_dmamap_unload(sc->req_dmat, sc->req_map); 744 if (sc->req_frames != NULL) 745 bus_dmamem_free(sc->req_dmat, sc->req_frames, sc->req_map); 746 if (sc->req_dmat != NULL) 747 bus_dma_tag_destroy(sc->req_dmat); 748 749 if (sc->chains != NULL) 750 free(sc->chains, M_MPR); 751 if (sc->prps != NULL) 752 free(sc->prps, M_MPR); 753 if (sc->commands != NULL) { 754 for (i = 1; i < sc->num_reqs; i++) { 755 cm = &sc->commands[i]; 756 bus_dmamap_destroy(sc->buffer_dmat, cm->cm_dmamap); 757 } 758 free(sc->commands, M_MPR); 759 } 760 if (sc->buffer_dmat != NULL) 761 bus_dma_tag_destroy(sc->buffer_dmat); 762 763 mpr_pci_free_interrupts(sc); 764 free(sc->queues, M_MPR); 765 sc->queues = NULL; 766 } 767 768 /* 769 * The terms diag reset and hard reset are used interchangeably in the MPI 770 * docs to mean resetting the controller chip. In this code diag reset 771 * cleans everything up, and the hard reset function just sends the reset 772 * sequence to the chip. This should probably be refactored so that every 773 * subsystem gets a reset notification of some sort, and can clean up 774 * appropriately. 775 */ 776 int 777 mpr_reinit(struct mpr_softc *sc) 778 { 779 int error; 780 struct mprsas_softc *sassc; 781 782 sassc = sc->sassc; 783 784 MPR_FUNCTRACE(sc); 785 786 mtx_assert(&sc->mpr_mtx, MA_OWNED); 787 788 mpr_dprint(sc, MPR_INIT|MPR_INFO, "Reinitializing controller\n"); 789 if (sc->mpr_flags & MPR_FLAGS_DIAGRESET) { 790 mpr_dprint(sc, MPR_INIT, "Reset already in progress\n"); 791 return 0; 792 } 793 794 /* 795 * Make sure the completion callbacks can recognize they're getting 796 * a NULL cm_reply due to a reset. 797 */ 798 sc->mpr_flags |= MPR_FLAGS_DIAGRESET; 799 800 /* 801 * Mask interrupts here. 802 */ 803 mpr_dprint(sc, MPR_INIT, "Masking interrupts and resetting\n"); 804 mpr_mask_intr(sc); 805 806 error = mpr_diag_reset(sc, CAN_SLEEP); 807 if (error != 0) { 808 panic("%s hard reset failed with error %d\n", __func__, error); 809 } 810 811 /* Restore the PCI state, including the MSI-X registers */ 812 mpr_pci_restore(sc); 813 814 /* Give the I/O subsystem special priority to get itself prepared */ 815 mprsas_handle_reinit(sc); 816 817 /* 818 * Get IOC Facts and allocate all structures based on this information. 819 * The attach function will also call mpr_iocfacts_allocate at startup. 820 * If relevant values have changed in IOC Facts, this function will free 821 * all of the memory based on IOC Facts and reallocate that memory. 822 */ 823 if ((error = mpr_iocfacts_allocate(sc, FALSE)) != 0) { 824 panic("%s IOC Facts based allocation failed with error %d\n", 825 __func__, error); 826 } 827 828 /* 829 * Mapping structures will be re-allocated after getting IOC Page8, so 830 * free these structures here. 831 */ 832 mpr_mapping_exit(sc); 833 834 /* 835 * The static page function currently read is IOC Page8. Others can be 836 * added in future. It's possible that the values in IOC Page8 have 837 * changed after a Diag Reset due to user modification, so always read 838 * these. Interrupts are masked, so unmask them before getting config 839 * pages. 840 */ 841 mpr_unmask_intr(sc); 842 sc->mpr_flags &= ~MPR_FLAGS_DIAGRESET; 843 mpr_base_static_config_pages(sc); 844 845 /* 846 * Some mapping info is based in IOC Page8 data, so re-initialize the 847 * mapping tables. 848 */ 849 mpr_mapping_initialize(sc); 850 851 /* 852 * Restart will reload the event masks clobbered by the reset, and 853 * then enable the port. 854 */ 855 mpr_reregister_events(sc); 856 857 /* the end of discovery will release the simq, so we're done. */ 858 mpr_dprint(sc, MPR_INIT|MPR_XINFO, "Finished sc %p post %u free %u\n", 859 sc, sc->replypostindex, sc->replyfreeindex); 860 mprsas_release_simq_reinit(sassc); 861 mpr_dprint(sc, MPR_INIT, "%s exit error= %d\n", __func__, error); 862 863 return 0; 864 } 865 866 /* Wait for the chip to ACK a word that we've put into its FIFO 867 * Wait for <timeout> seconds. In single loop wait for busy loop 868 * for 500 microseconds. 869 * Total is [ 0.5 * (2000 * <timeout>) ] in miliseconds. 870 * */ 871 static int 872 mpr_wait_db_ack(struct mpr_softc *sc, int timeout, int sleep_flag) 873 { 874 u32 cntdn, count; 875 u32 int_status; 876 u32 doorbell; 877 878 count = 0; 879 cntdn = (sleep_flag == CAN_SLEEP) ? 1000*timeout : 2000*timeout; 880 do { 881 int_status = mpr_regread(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET); 882 if (!(int_status & MPI2_HIS_SYS2IOC_DB_STATUS)) { 883 mpr_dprint(sc, MPR_TRACE, "%s: successful count(%d), " 884 "timeout(%d)\n", __func__, count, timeout); 885 return 0; 886 } else if (int_status & MPI2_HIS_IOC2SYS_DB_STATUS) { 887 doorbell = mpr_regread(sc, MPI2_DOORBELL_OFFSET); 888 if ((doorbell & MPI2_IOC_STATE_MASK) == 889 MPI2_IOC_STATE_FAULT) { 890 mpr_dprint(sc, MPR_FAULT, 891 "fault_state(0x%04x)!\n", doorbell); 892 return (EFAULT); 893 } 894 } else if (int_status == 0xFFFFFFFF) 895 goto out; 896 897 /* 898 * If it can sleep, sleep for 1 milisecond, else busy loop for 899 * 0.5 milisecond 900 */ 901 if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP) 902 msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0, "mprdba", 903 hz/1000); 904 else if (sleep_flag == CAN_SLEEP) 905 pause("mprdba", hz/1000); 906 else 907 DELAY(500); 908 count++; 909 } while (--cntdn); 910 911 out: 912 mpr_dprint(sc, MPR_FAULT, "%s: failed due to timeout count(%d), " 913 "int_status(%x)!\n", __func__, count, int_status); 914 return (ETIMEDOUT); 915 } 916 917 /* Wait for the chip to signal that the next word in its FIFO can be fetched */ 918 static int 919 mpr_wait_db_int(struct mpr_softc *sc) 920 { 921 int retry; 922 923 for (retry = 0; retry < MPR_DB_MAX_WAIT; retry++) { 924 if ((mpr_regread(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET) & 925 MPI2_HIS_IOC2SYS_DB_STATUS) != 0) 926 return (0); 927 DELAY(2000); 928 } 929 return (ETIMEDOUT); 930 } 931 932 /* Step through the synchronous command state machine, i.e. "Doorbell mode" */ 933 static int 934 mpr_request_sync(struct mpr_softc *sc, void *req, MPI2_DEFAULT_REPLY *reply, 935 int req_sz, int reply_sz, int timeout) 936 { 937 uint32_t *data32; 938 uint16_t *data16; 939 int i, count, ioc_sz, residual; 940 int sleep_flags = CAN_SLEEP; 941 942 #if __FreeBSD_version >= 1000029 943 if (curthread->td_no_sleeping) 944 #else //__FreeBSD_version < 1000029 945 if (curthread->td_pflags & TDP_NOSLEEPING) 946 #endif //__FreeBSD_version >= 1000029 947 sleep_flags = NO_SLEEP; 948 949 /* Step 1 */ 950 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 951 952 /* Step 2 */ 953 if (mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_USED) 954 return (EBUSY); 955 956 /* Step 3 957 * Announce that a message is coming through the doorbell. Messages 958 * are pushed at 32bit words, so round up if needed. 959 */ 960 count = (req_sz + 3) / 4; 961 mpr_regwrite(sc, MPI2_DOORBELL_OFFSET, 962 (MPI2_FUNCTION_HANDSHAKE << MPI2_DOORBELL_FUNCTION_SHIFT) | 963 (count << MPI2_DOORBELL_ADD_DWORDS_SHIFT)); 964 965 /* Step 4 */ 966 if (mpr_wait_db_int(sc) || 967 (mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_USED) == 0) { 968 mpr_dprint(sc, MPR_FAULT, "Doorbell failed to activate\n"); 969 return (ENXIO); 970 } 971 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 972 if (mpr_wait_db_ack(sc, 5, sleep_flags) != 0) { 973 mpr_dprint(sc, MPR_FAULT, "Doorbell handshake failed\n"); 974 return (ENXIO); 975 } 976 977 /* Step 5 */ 978 /* Clock out the message data synchronously in 32-bit dwords*/ 979 data32 = (uint32_t *)req; 980 for (i = 0; i < count; i++) { 981 mpr_regwrite(sc, MPI2_DOORBELL_OFFSET, htole32(data32[i])); 982 if (mpr_wait_db_ack(sc, 5, sleep_flags) != 0) { 983 mpr_dprint(sc, MPR_FAULT, 984 "Timeout while writing doorbell\n"); 985 return (ENXIO); 986 } 987 } 988 989 /* Step 6 */ 990 /* Clock in the reply in 16-bit words. The total length of the 991 * message is always in the 4th byte, so clock out the first 2 words 992 * manually, then loop the rest. 993 */ 994 data16 = (uint16_t *)reply; 995 if (mpr_wait_db_int(sc) != 0) { 996 mpr_dprint(sc, MPR_FAULT, "Timeout reading doorbell 0\n"); 997 return (ENXIO); 998 } 999 data16[0] = 1000 mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_DATA_MASK; 1001 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 1002 if (mpr_wait_db_int(sc) != 0) { 1003 mpr_dprint(sc, MPR_FAULT, "Timeout reading doorbell 1\n"); 1004 return (ENXIO); 1005 } 1006 data16[1] = 1007 mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_DATA_MASK; 1008 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 1009 1010 /* Number of 32bit words in the message */ 1011 ioc_sz = reply->MsgLength; 1012 1013 /* 1014 * Figure out how many 16bit words to clock in without overrunning. 1015 * The precision loss with dividing reply_sz can safely be 1016 * ignored because the messages can only be multiples of 32bits. 1017 */ 1018 residual = 0; 1019 count = MIN((reply_sz / 4), ioc_sz) * 2; 1020 if (count < ioc_sz * 2) { 1021 residual = ioc_sz * 2 - count; 1022 mpr_dprint(sc, MPR_ERROR, "Driver error, throwing away %d " 1023 "residual message words\n", residual); 1024 } 1025 1026 for (i = 2; i < count; i++) { 1027 if (mpr_wait_db_int(sc) != 0) { 1028 mpr_dprint(sc, MPR_FAULT, 1029 "Timeout reading doorbell %d\n", i); 1030 return (ENXIO); 1031 } 1032 data16[i] = mpr_regread(sc, MPI2_DOORBELL_OFFSET) & 1033 MPI2_DOORBELL_DATA_MASK; 1034 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 1035 } 1036 1037 /* 1038 * Pull out residual words that won't fit into the provided buffer. 1039 * This keeps the chip from hanging due to a driver programming 1040 * error. 1041 */ 1042 while (residual--) { 1043 if (mpr_wait_db_int(sc) != 0) { 1044 mpr_dprint(sc, MPR_FAULT, "Timeout reading doorbell\n"); 1045 return (ENXIO); 1046 } 1047 (void)mpr_regread(sc, MPI2_DOORBELL_OFFSET); 1048 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 1049 } 1050 1051 /* Step 7 */ 1052 if (mpr_wait_db_int(sc) != 0) { 1053 mpr_dprint(sc, MPR_FAULT, "Timeout waiting to exit doorbell\n"); 1054 return (ENXIO); 1055 } 1056 if (mpr_regread(sc, MPI2_DOORBELL_OFFSET) & MPI2_DOORBELL_USED) 1057 mpr_dprint(sc, MPR_FAULT, "Warning, doorbell still active\n"); 1058 mpr_regwrite(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET, 0x0); 1059 1060 return (0); 1061 } 1062 1063 static void 1064 mpr_enqueue_request(struct mpr_softc *sc, struct mpr_command *cm) 1065 { 1066 request_descriptor rd; 1067 1068 MPR_FUNCTRACE(sc); 1069 mpr_dprint(sc, MPR_TRACE, "SMID %u cm %p ccb %p\n", 1070 cm->cm_desc.Default.SMID, cm, cm->cm_ccb); 1071 1072 if (sc->mpr_flags & MPR_FLAGS_ATTACH_DONE && !(sc->mpr_flags & 1073 MPR_FLAGS_SHUTDOWN)) 1074 mtx_assert(&sc->mpr_mtx, MA_OWNED); 1075 1076 if (++sc->io_cmds_active > sc->io_cmds_highwater) 1077 sc->io_cmds_highwater++; 1078 1079 if (sc->atomic_desc_capable) { 1080 rd.u.low = cm->cm_desc.Words.Low; 1081 mpr_regwrite(sc, MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET, 1082 rd.u.low); 1083 } else { 1084 rd.u.low = cm->cm_desc.Words.Low; 1085 rd.u.high = cm->cm_desc.Words.High; 1086 rd.word = htole64(rd.word); 1087 mpr_regwrite(sc, MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET, 1088 rd.u.low); 1089 mpr_regwrite(sc, MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET, 1090 rd.u.high); 1091 } 1092 } 1093 1094 /* 1095 * Just the FACTS, ma'am. 1096 */ 1097 static int 1098 mpr_get_iocfacts(struct mpr_softc *sc, MPI2_IOC_FACTS_REPLY *facts) 1099 { 1100 MPI2_DEFAULT_REPLY *reply; 1101 MPI2_IOC_FACTS_REQUEST request; 1102 int error, req_sz, reply_sz; 1103 1104 MPR_FUNCTRACE(sc); 1105 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 1106 1107 req_sz = sizeof(MPI2_IOC_FACTS_REQUEST); 1108 reply_sz = sizeof(MPI2_IOC_FACTS_REPLY); 1109 reply = (MPI2_DEFAULT_REPLY *)facts; 1110 1111 bzero(&request, req_sz); 1112 request.Function = MPI2_FUNCTION_IOC_FACTS; 1113 error = mpr_request_sync(sc, &request, reply, req_sz, reply_sz, 5); 1114 1115 mpr_dprint(sc, MPR_INIT, "%s exit, error= %d\n", __func__, error); 1116 return (error); 1117 } 1118 1119 static int 1120 mpr_send_iocinit(struct mpr_softc *sc) 1121 { 1122 MPI2_IOC_INIT_REQUEST init; 1123 MPI2_DEFAULT_REPLY reply; 1124 int req_sz, reply_sz, error; 1125 struct timeval now; 1126 uint64_t time_in_msec; 1127 1128 MPR_FUNCTRACE(sc); 1129 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 1130 1131 req_sz = sizeof(MPI2_IOC_INIT_REQUEST); 1132 reply_sz = sizeof(MPI2_IOC_INIT_REPLY); 1133 bzero(&init, req_sz); 1134 bzero(&reply, reply_sz); 1135 1136 /* 1137 * Fill in the init block. Note that most addresses are 1138 * deliberately in the lower 32bits of memory. This is a micro- 1139 * optimzation for PCI/PCIX, though it's not clear if it helps PCIe. 1140 */ 1141 init.Function = MPI2_FUNCTION_IOC_INIT; 1142 init.WhoInit = MPI2_WHOINIT_HOST_DRIVER; 1143 init.MsgVersion = htole16(MPI2_VERSION); 1144 init.HeaderVersion = htole16(MPI2_HEADER_VERSION); 1145 init.SystemRequestFrameSize = htole16(sc->facts->IOCRequestFrameSize); 1146 init.ReplyDescriptorPostQueueDepth = htole16(sc->pqdepth); 1147 init.ReplyFreeQueueDepth = htole16(sc->fqdepth); 1148 init.SenseBufferAddressHigh = 0; 1149 init.SystemReplyAddressHigh = 0; 1150 init.SystemRequestFrameBaseAddress.High = 0; 1151 init.SystemRequestFrameBaseAddress.Low = 1152 htole32((uint32_t)sc->req_busaddr); 1153 init.ReplyDescriptorPostQueueAddress.High = 0; 1154 init.ReplyDescriptorPostQueueAddress.Low = 1155 htole32((uint32_t)sc->post_busaddr); 1156 init.ReplyFreeQueueAddress.High = 0; 1157 init.ReplyFreeQueueAddress.Low = htole32((uint32_t)sc->free_busaddr); 1158 getmicrotime(&now); 1159 time_in_msec = (now.tv_sec * 1000 + now.tv_usec/1000); 1160 init.TimeStamp.High = htole32((time_in_msec >> 32) & 0xFFFFFFFF); 1161 init.TimeStamp.Low = htole32(time_in_msec & 0xFFFFFFFF); 1162 init.HostPageSize = HOST_PAGE_SIZE_4K; 1163 1164 error = mpr_request_sync(sc, &init, &reply, req_sz, reply_sz, 5); 1165 if ((reply.IOCStatus & MPI2_IOCSTATUS_MASK) != MPI2_IOCSTATUS_SUCCESS) 1166 error = ENXIO; 1167 1168 mpr_dprint(sc, MPR_INIT, "IOCInit status= 0x%x\n", reply.IOCStatus); 1169 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__); 1170 return (error); 1171 } 1172 1173 void 1174 mpr_memaddr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1175 { 1176 bus_addr_t *addr; 1177 1178 addr = arg; 1179 *addr = segs[0].ds_addr; 1180 } 1181 1182 static int 1183 mpr_alloc_queues(struct mpr_softc *sc) 1184 { 1185 struct mpr_queue *q; 1186 int nq, i; 1187 1188 nq = sc->msi_msgs; 1189 mpr_dprint(sc, MPR_INIT|MPR_XINFO, "Allocating %d I/O queues\n", nq); 1190 1191 sc->queues = malloc(sizeof(struct mpr_queue) * nq, M_MPR, 1192 M_NOWAIT|M_ZERO); 1193 if (sc->queues == NULL) 1194 return (ENOMEM); 1195 1196 for (i = 0; i < nq; i++) { 1197 q = &sc->queues[i]; 1198 mpr_dprint(sc, MPR_INIT, "Configuring queue %d %p\n", i, q); 1199 q->sc = sc; 1200 q->qnum = i; 1201 } 1202 return (0); 1203 } 1204 1205 static int 1206 mpr_alloc_hw_queues(struct mpr_softc *sc) 1207 { 1208 bus_addr_t queues_busaddr; 1209 uint8_t *queues; 1210 int qsize, fqsize, pqsize; 1211 1212 /* 1213 * The reply free queue contains 4 byte entries in multiples of 16 and 1214 * aligned on a 16 byte boundary. There must always be an unused entry. 1215 * This queue supplies fresh reply frames for the firmware to use. 1216 * 1217 * The reply descriptor post queue contains 8 byte entries in 1218 * multiples of 16 and aligned on a 16 byte boundary. This queue 1219 * contains filled-in reply frames sent from the firmware to the host. 1220 * 1221 * These two queues are allocated together for simplicity. 1222 */ 1223 sc->fqdepth = roundup2(sc->num_replies + 1, 16); 1224 sc->pqdepth = roundup2(sc->num_replies + 1, 16); 1225 fqsize= sc->fqdepth * 4; 1226 pqsize = sc->pqdepth * 8; 1227 qsize = fqsize + pqsize; 1228 1229 if (bus_dma_tag_create( sc->mpr_parent_dmat, /* parent */ 1230 16, 0, /* algnmnt, boundary */ 1231 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1232 BUS_SPACE_MAXADDR, /* highaddr */ 1233 NULL, NULL, /* filter, filterarg */ 1234 qsize, /* maxsize */ 1235 1, /* nsegments */ 1236 qsize, /* maxsegsize */ 1237 0, /* flags */ 1238 NULL, NULL, /* lockfunc, lockarg */ 1239 &sc->queues_dmat)) { 1240 mpr_dprint(sc, MPR_ERROR, "Cannot allocate queues DMA tag\n"); 1241 return (ENOMEM); 1242 } 1243 if (bus_dmamem_alloc(sc->queues_dmat, (void **)&queues, BUS_DMA_NOWAIT, 1244 &sc->queues_map)) { 1245 mpr_dprint(sc, MPR_ERROR, "Cannot allocate queues memory\n"); 1246 return (ENOMEM); 1247 } 1248 bzero(queues, qsize); 1249 bus_dmamap_load(sc->queues_dmat, sc->queues_map, queues, qsize, 1250 mpr_memaddr_cb, &queues_busaddr, 0); 1251 1252 sc->free_queue = (uint32_t *)queues; 1253 sc->free_busaddr = queues_busaddr; 1254 sc->post_queue = (MPI2_REPLY_DESCRIPTORS_UNION *)(queues + fqsize); 1255 sc->post_busaddr = queues_busaddr + fqsize; 1256 1257 return (0); 1258 } 1259 1260 static int 1261 mpr_alloc_replies(struct mpr_softc *sc) 1262 { 1263 int rsize, num_replies; 1264 1265 /* 1266 * sc->num_replies should be one less than sc->fqdepth. We need to 1267 * allocate space for sc->fqdepth replies, but only sc->num_replies 1268 * replies can be used at once. 1269 */ 1270 num_replies = max(sc->fqdepth, sc->num_replies); 1271 1272 rsize = sc->facts->ReplyFrameSize * num_replies * 4; 1273 if (bus_dma_tag_create( sc->mpr_parent_dmat, /* parent */ 1274 4, 0, /* algnmnt, boundary */ 1275 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1276 BUS_SPACE_MAXADDR, /* highaddr */ 1277 NULL, NULL, /* filter, filterarg */ 1278 rsize, /* maxsize */ 1279 1, /* nsegments */ 1280 rsize, /* maxsegsize */ 1281 0, /* flags */ 1282 NULL, NULL, /* lockfunc, lockarg */ 1283 &sc->reply_dmat)) { 1284 mpr_dprint(sc, MPR_ERROR, "Cannot allocate replies DMA tag\n"); 1285 return (ENOMEM); 1286 } 1287 if (bus_dmamem_alloc(sc->reply_dmat, (void **)&sc->reply_frames, 1288 BUS_DMA_NOWAIT, &sc->reply_map)) { 1289 mpr_dprint(sc, MPR_ERROR, "Cannot allocate replies memory\n"); 1290 return (ENOMEM); 1291 } 1292 bzero(sc->reply_frames, rsize); 1293 bus_dmamap_load(sc->reply_dmat, sc->reply_map, sc->reply_frames, rsize, 1294 mpr_memaddr_cb, &sc->reply_busaddr, 0); 1295 1296 return (0); 1297 } 1298 1299 static int 1300 mpr_alloc_requests(struct mpr_softc *sc) 1301 { 1302 struct mpr_command *cm; 1303 struct mpr_chain *chain; 1304 int i, rsize, nsegs; 1305 1306 rsize = sc->facts->IOCRequestFrameSize * sc->num_reqs * 4; 1307 if (bus_dma_tag_create( sc->mpr_parent_dmat, /* parent */ 1308 16, 0, /* algnmnt, boundary */ 1309 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1310 BUS_SPACE_MAXADDR, /* highaddr */ 1311 NULL, NULL, /* filter, filterarg */ 1312 rsize, /* maxsize */ 1313 1, /* nsegments */ 1314 rsize, /* maxsegsize */ 1315 0, /* flags */ 1316 NULL, NULL, /* lockfunc, lockarg */ 1317 &sc->req_dmat)) { 1318 mpr_dprint(sc, MPR_ERROR, "Cannot allocate request DMA tag\n"); 1319 return (ENOMEM); 1320 } 1321 if (bus_dmamem_alloc(sc->req_dmat, (void **)&sc->req_frames, 1322 BUS_DMA_NOWAIT, &sc->req_map)) { 1323 mpr_dprint(sc, MPR_ERROR, "Cannot allocate request memory\n"); 1324 return (ENOMEM); 1325 } 1326 bzero(sc->req_frames, rsize); 1327 bus_dmamap_load(sc->req_dmat, sc->req_map, sc->req_frames, rsize, 1328 mpr_memaddr_cb, &sc->req_busaddr, 0); 1329 1330 /* 1331 * Gen3 and beyond uses the IOCMaxChainSegmentSize from IOC Facts to 1332 * get the size of a Chain Frame. Previous versions use the size as a 1333 * Request Frame for the Chain Frame size. If IOCMaxChainSegmentSize 1334 * is 0, use the default value. The IOCMaxChainSegmentSize is the 1335 * number of 16-byte elelements that can fit in a Chain Frame, which is 1336 * the size of an IEEE Simple SGE. 1337 */ 1338 if (sc->facts->MsgVersion >= MPI2_VERSION_02_05) { 1339 sc->chain_seg_size = 1340 htole16(sc->facts->IOCMaxChainSegmentSize); 1341 if (sc->chain_seg_size == 0) { 1342 sc->chain_frame_size = MPR_DEFAULT_CHAIN_SEG_SIZE * 1343 MPR_MAX_CHAIN_ELEMENT_SIZE; 1344 } else { 1345 sc->chain_frame_size = sc->chain_seg_size * 1346 MPR_MAX_CHAIN_ELEMENT_SIZE; 1347 } 1348 } else { 1349 sc->chain_frame_size = sc->facts->IOCRequestFrameSize * 4; 1350 } 1351 rsize = sc->chain_frame_size * sc->max_chains; 1352 if (bus_dma_tag_create( sc->mpr_parent_dmat, /* parent */ 1353 16, 0, /* algnmnt, boundary */ 1354 BUS_SPACE_MAXADDR, /* lowaddr */ 1355 BUS_SPACE_MAXADDR, /* highaddr */ 1356 NULL, NULL, /* filter, filterarg */ 1357 rsize, /* maxsize */ 1358 1, /* nsegments */ 1359 rsize, /* maxsegsize */ 1360 0, /* flags */ 1361 NULL, NULL, /* lockfunc, lockarg */ 1362 &sc->chain_dmat)) { 1363 mpr_dprint(sc, MPR_ERROR, "Cannot allocate chain DMA tag\n"); 1364 return (ENOMEM); 1365 } 1366 if (bus_dmamem_alloc(sc->chain_dmat, (void **)&sc->chain_frames, 1367 BUS_DMA_NOWAIT, &sc->chain_map)) { 1368 mpr_dprint(sc, MPR_ERROR, "Cannot allocate chain memory\n"); 1369 return (ENOMEM); 1370 } 1371 bzero(sc->chain_frames, rsize); 1372 bus_dmamap_load(sc->chain_dmat, sc->chain_map, sc->chain_frames, rsize, 1373 mpr_memaddr_cb, &sc->chain_busaddr, 0); 1374 1375 rsize = MPR_SENSE_LEN * sc->num_reqs; 1376 if (bus_dma_tag_create( sc->mpr_parent_dmat, /* parent */ 1377 1, 0, /* algnmnt, boundary */ 1378 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1379 BUS_SPACE_MAXADDR, /* highaddr */ 1380 NULL, NULL, /* filter, filterarg */ 1381 rsize, /* maxsize */ 1382 1, /* nsegments */ 1383 rsize, /* maxsegsize */ 1384 0, /* flags */ 1385 NULL, NULL, /* lockfunc, lockarg */ 1386 &sc->sense_dmat)) { 1387 mpr_dprint(sc, MPR_ERROR, "Cannot allocate sense DMA tag\n"); 1388 return (ENOMEM); 1389 } 1390 if (bus_dmamem_alloc(sc->sense_dmat, (void **)&sc->sense_frames, 1391 BUS_DMA_NOWAIT, &sc->sense_map)) { 1392 mpr_dprint(sc, MPR_ERROR, "Cannot allocate sense memory\n"); 1393 return (ENOMEM); 1394 } 1395 bzero(sc->sense_frames, rsize); 1396 bus_dmamap_load(sc->sense_dmat, sc->sense_map, sc->sense_frames, rsize, 1397 mpr_memaddr_cb, &sc->sense_busaddr, 0); 1398 1399 sc->chains = malloc(sizeof(struct mpr_chain) * sc->max_chains, M_MPR, 1400 M_WAITOK | M_ZERO); 1401 if (!sc->chains) { 1402 mpr_dprint(sc, MPR_ERROR, "Cannot allocate chain memory\n"); 1403 return (ENOMEM); 1404 } 1405 for (i = 0; i < sc->max_chains; i++) { 1406 chain = &sc->chains[i]; 1407 chain->chain = (MPI2_SGE_IO_UNION *)(sc->chain_frames + 1408 i * sc->chain_frame_size); 1409 chain->chain_busaddr = sc->chain_busaddr + 1410 i * sc->chain_frame_size; 1411 mpr_free_chain(sc, chain); 1412 sc->chain_free_lowwater++; 1413 } 1414 1415 /* 1416 * Allocate NVMe PRP Pages for NVMe SGL support only if the FW supports 1417 * these devices. 1418 */ 1419 if ((sc->facts->MsgVersion >= MPI2_VERSION_02_06) && 1420 (sc->facts->ProtocolFlags & MPI2_IOCFACTS_PROTOCOL_NVME_DEVICES)) { 1421 if (mpr_alloc_nvme_prp_pages(sc) == ENOMEM) 1422 return (ENOMEM); 1423 } 1424 1425 /* XXX Need to pick a more precise value */ 1426 nsegs = (MAXPHYS / PAGE_SIZE) + 1; 1427 if (bus_dma_tag_create( sc->mpr_parent_dmat, /* parent */ 1428 1, 0, /* algnmnt, boundary */ 1429 BUS_SPACE_MAXADDR, /* lowaddr */ 1430 BUS_SPACE_MAXADDR, /* highaddr */ 1431 NULL, NULL, /* filter, filterarg */ 1432 BUS_SPACE_MAXSIZE_32BIT,/* maxsize */ 1433 nsegs, /* nsegments */ 1434 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1435 BUS_DMA_ALLOCNOW, /* flags */ 1436 busdma_lock_mutex, /* lockfunc */ 1437 &sc->mpr_mtx, /* lockarg */ 1438 &sc->buffer_dmat)) { 1439 mpr_dprint(sc, MPR_ERROR, "Cannot allocate buffer DMA tag\n"); 1440 return (ENOMEM); 1441 } 1442 1443 /* 1444 * SMID 0 cannot be used as a free command per the firmware spec. 1445 * Just drop that command instead of risking accounting bugs. 1446 */ 1447 sc->commands = malloc(sizeof(struct mpr_command) * sc->num_reqs, 1448 M_MPR, M_WAITOK | M_ZERO); 1449 if (!sc->commands) { 1450 mpr_dprint(sc, MPR_ERROR, "Cannot allocate command memory\n"); 1451 return (ENOMEM); 1452 } 1453 for (i = 1; i < sc->num_reqs; i++) { 1454 cm = &sc->commands[i]; 1455 cm->cm_req = sc->req_frames + 1456 i * sc->facts->IOCRequestFrameSize * 4; 1457 cm->cm_req_busaddr = sc->req_busaddr + 1458 i * sc->facts->IOCRequestFrameSize * 4; 1459 cm->cm_sense = &sc->sense_frames[i]; 1460 cm->cm_sense_busaddr = sc->sense_busaddr + i * MPR_SENSE_LEN; 1461 cm->cm_desc.Default.SMID = i; 1462 cm->cm_sc = sc; 1463 TAILQ_INIT(&cm->cm_chain_list); 1464 TAILQ_INIT(&cm->cm_prp_page_list); 1465 callout_init_mtx(&cm->cm_callout, &sc->mpr_mtx, 0); 1466 1467 /* XXX Is a failure here a critical problem? */ 1468 if (bus_dmamap_create(sc->buffer_dmat, 0, &cm->cm_dmamap) 1469 == 0) { 1470 if (i <= sc->facts->HighPriorityCredit) 1471 mpr_free_high_priority_command(sc, cm); 1472 else 1473 mpr_free_command(sc, cm); 1474 } else { 1475 panic("failed to allocate command %d\n", i); 1476 sc->num_reqs = i; 1477 break; 1478 } 1479 } 1480 1481 return (0); 1482 } 1483 1484 /* 1485 * Allocate contiguous buffers for PCIe NVMe devices for building native PRPs, 1486 * which are scatter/gather lists for NVMe devices. 1487 * 1488 * This buffer must be contiguous due to the nature of how NVMe PRPs are built 1489 * and translated by FW. 1490 * 1491 * returns ENOMEM if memory could not be allocated, otherwise returns 0. 1492 */ 1493 static int 1494 mpr_alloc_nvme_prp_pages(struct mpr_softc *sc) 1495 { 1496 int PRPs_per_page, PRPs_required, pages_required; 1497 int rsize, i; 1498 struct mpr_prp_page *prp_page; 1499 1500 /* 1501 * Assuming a MAX_IO_SIZE of 1MB and a PAGE_SIZE of 4k, the max number 1502 * of PRPs (NVMe's Scatter/Gather Element) needed per I/O is: 1503 * MAX_IO_SIZE / PAGE_SIZE = 256 1504 * 1505 * 1 PRP entry in main frame for PRP list pointer still leaves 255 PRPs 1506 * required for the remainder of the 1MB I/O. 512 PRPs can fit into one 1507 * page (4096 / 8 = 512), so only one page is required for each I/O. 1508 * 1509 * Each of these buffers will need to be contiguous. For simplicity, 1510 * only one buffer is allocated here, which has all of the space 1511 * required for the NVMe Queue Depth. If there are problems allocating 1512 * this one buffer, this function will need to change to allocate 1513 * individual, contiguous NVME_QDEPTH buffers. 1514 * 1515 * The real calculation will use the real max io size. Above is just an 1516 * example. 1517 * 1518 */ 1519 PRPs_required = sc->maxio / PAGE_SIZE; 1520 PRPs_per_page = (PAGE_SIZE / PRP_ENTRY_SIZE) - 1; 1521 pages_required = (PRPs_required / PRPs_per_page) + 1; 1522 1523 sc->prp_buffer_size = PAGE_SIZE * pages_required; 1524 rsize = sc->prp_buffer_size * NVME_QDEPTH; 1525 if (bus_dma_tag_create( sc->mpr_parent_dmat, /* parent */ 1526 4, 0, /* algnmnt, boundary */ 1527 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1528 BUS_SPACE_MAXADDR, /* highaddr */ 1529 NULL, NULL, /* filter, filterarg */ 1530 rsize, /* maxsize */ 1531 1, /* nsegments */ 1532 rsize, /* maxsegsize */ 1533 0, /* flags */ 1534 NULL, NULL, /* lockfunc, lockarg */ 1535 &sc->prp_page_dmat)) { 1536 mpr_dprint(sc, MPR_ERROR, "Cannot allocate NVMe PRP DMA " 1537 "tag\n"); 1538 return (ENOMEM); 1539 } 1540 if (bus_dmamem_alloc(sc->prp_page_dmat, (void **)&sc->prp_pages, 1541 BUS_DMA_NOWAIT, &sc->prp_page_map)) { 1542 mpr_dprint(sc, MPR_ERROR, "Cannot allocate NVMe PRP memory\n"); 1543 return (ENOMEM); 1544 } 1545 bzero(sc->prp_pages, rsize); 1546 bus_dmamap_load(sc->prp_page_dmat, sc->prp_page_map, sc->prp_pages, 1547 rsize, mpr_memaddr_cb, &sc->prp_page_busaddr, 0); 1548 1549 sc->prps = malloc(sizeof(struct mpr_prp_page) * NVME_QDEPTH, M_MPR, 1550 M_WAITOK | M_ZERO); 1551 for (i = 0; i < NVME_QDEPTH; i++) { 1552 prp_page = &sc->prps[i]; 1553 prp_page->prp_page = (uint64_t *)(sc->prp_pages + 1554 i * sc->prp_buffer_size); 1555 prp_page->prp_page_busaddr = (uint64_t)(sc->prp_page_busaddr + 1556 i * sc->prp_buffer_size); 1557 mpr_free_prp_page(sc, prp_page); 1558 sc->prp_pages_free_lowwater++; 1559 } 1560 1561 return (0); 1562 } 1563 1564 static int 1565 mpr_init_queues(struct mpr_softc *sc) 1566 { 1567 int i; 1568 1569 memset((uint8_t *)sc->post_queue, 0xff, sc->pqdepth * 8); 1570 1571 /* 1572 * According to the spec, we need to use one less reply than we 1573 * have space for on the queue. So sc->num_replies (the number we 1574 * use) should be less than sc->fqdepth (allocated size). 1575 */ 1576 if (sc->num_replies >= sc->fqdepth) 1577 return (EINVAL); 1578 1579 /* 1580 * Initialize all of the free queue entries. 1581 */ 1582 for (i = 0; i < sc->fqdepth; i++) { 1583 sc->free_queue[i] = sc->reply_busaddr + 1584 (i * sc->facts->ReplyFrameSize * 4); 1585 } 1586 sc->replyfreeindex = sc->num_replies; 1587 1588 return (0); 1589 } 1590 1591 /* Get the driver parameter tunables. Lowest priority are the driver defaults. 1592 * Next are the global settings, if they exist. Highest are the per-unit 1593 * settings, if they exist. 1594 */ 1595 void 1596 mpr_get_tunables(struct mpr_softc *sc) 1597 { 1598 char tmpstr[80], mpr_debug[80]; 1599 1600 /* XXX default to some debugging for now */ 1601 sc->mpr_debug = MPR_INFO | MPR_FAULT; 1602 sc->disable_msix = 0; 1603 sc->disable_msi = 0; 1604 sc->max_msix = MPR_MSIX_MAX; 1605 sc->max_chains = MPR_CHAIN_FRAMES; 1606 sc->max_io_pages = MPR_MAXIO_PAGES; 1607 sc->enable_ssu = MPR_SSU_ENABLE_SSD_DISABLE_HDD; 1608 sc->spinup_wait_time = DEFAULT_SPINUP_WAIT; 1609 sc->use_phynum = 1; 1610 sc->max_reqframes = MPR_REQ_FRAMES; 1611 sc->max_prireqframes = MPR_PRI_REQ_FRAMES; 1612 sc->max_replyframes = MPR_REPLY_FRAMES; 1613 sc->max_evtframes = MPR_EVT_REPLY_FRAMES; 1614 1615 /* 1616 * Grab the global variables. 1617 */ 1618 bzero(mpr_debug, 80); 1619 if (TUNABLE_STR_FETCH("hw.mpr.debug_level", mpr_debug, 80) != 0) 1620 mpr_parse_debug(sc, mpr_debug); 1621 TUNABLE_INT_FETCH("hw.mpr.disable_msix", &sc->disable_msix); 1622 TUNABLE_INT_FETCH("hw.mpr.disable_msi", &sc->disable_msi); 1623 TUNABLE_INT_FETCH("hw.mpr.max_msix", &sc->max_msix); 1624 TUNABLE_INT_FETCH("hw.mpr.max_chains", &sc->max_chains); 1625 TUNABLE_INT_FETCH("hw.mpr.max_io_pages", &sc->max_io_pages); 1626 TUNABLE_INT_FETCH("hw.mpr.enable_ssu", &sc->enable_ssu); 1627 TUNABLE_INT_FETCH("hw.mpr.spinup_wait_time", &sc->spinup_wait_time); 1628 TUNABLE_INT_FETCH("hw.mpr.use_phy_num", &sc->use_phynum); 1629 TUNABLE_INT_FETCH("hw.mpr.max_reqframes", &sc->max_reqframes); 1630 TUNABLE_INT_FETCH("hw.mpr.max_prireqframes", &sc->max_prireqframes); 1631 TUNABLE_INT_FETCH("hw.mpr.max_replyframes", &sc->max_replyframes); 1632 TUNABLE_INT_FETCH("hw.mpr.max_evtframes", &sc->max_evtframes); 1633 1634 /* Grab the unit-instance variables */ 1635 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.debug_level", 1636 device_get_unit(sc->mpr_dev)); 1637 bzero(mpr_debug, 80); 1638 if (TUNABLE_STR_FETCH(tmpstr, mpr_debug, 80) != 0) 1639 mpr_parse_debug(sc, mpr_debug); 1640 1641 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.disable_msix", 1642 device_get_unit(sc->mpr_dev)); 1643 TUNABLE_INT_FETCH(tmpstr, &sc->disable_msix); 1644 1645 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.disable_msi", 1646 device_get_unit(sc->mpr_dev)); 1647 TUNABLE_INT_FETCH(tmpstr, &sc->disable_msi); 1648 1649 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_msix", 1650 device_get_unit(sc->mpr_dev)); 1651 TUNABLE_INT_FETCH(tmpstr, &sc->max_msix); 1652 1653 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_chains", 1654 device_get_unit(sc->mpr_dev)); 1655 TUNABLE_INT_FETCH(tmpstr, &sc->max_chains); 1656 1657 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_io_pages", 1658 device_get_unit(sc->mpr_dev)); 1659 TUNABLE_INT_FETCH(tmpstr, &sc->max_io_pages); 1660 1661 bzero(sc->exclude_ids, sizeof(sc->exclude_ids)); 1662 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.exclude_ids", 1663 device_get_unit(sc->mpr_dev)); 1664 TUNABLE_STR_FETCH(tmpstr, sc->exclude_ids, sizeof(sc->exclude_ids)); 1665 1666 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.enable_ssu", 1667 device_get_unit(sc->mpr_dev)); 1668 TUNABLE_INT_FETCH(tmpstr, &sc->enable_ssu); 1669 1670 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.spinup_wait_time", 1671 device_get_unit(sc->mpr_dev)); 1672 TUNABLE_INT_FETCH(tmpstr, &sc->spinup_wait_time); 1673 1674 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.use_phy_num", 1675 device_get_unit(sc->mpr_dev)); 1676 TUNABLE_INT_FETCH(tmpstr, &sc->use_phynum); 1677 1678 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_reqframes", 1679 device_get_unit(sc->mpr_dev)); 1680 TUNABLE_INT_FETCH(tmpstr, &sc->max_reqframes); 1681 1682 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_prireqframes", 1683 device_get_unit(sc->mpr_dev)); 1684 TUNABLE_INT_FETCH(tmpstr, &sc->max_prireqframes); 1685 1686 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_replyframes", 1687 device_get_unit(sc->mpr_dev)); 1688 TUNABLE_INT_FETCH(tmpstr, &sc->max_replyframes); 1689 1690 snprintf(tmpstr, sizeof(tmpstr), "dev.mpr.%d.max_evtframes", 1691 device_get_unit(sc->mpr_dev)); 1692 TUNABLE_INT_FETCH(tmpstr, &sc->max_evtframes); 1693 } 1694 1695 static void 1696 mpr_setup_sysctl(struct mpr_softc *sc) 1697 { 1698 struct sysctl_ctx_list *sysctl_ctx = NULL; 1699 struct sysctl_oid *sysctl_tree = NULL; 1700 char tmpstr[80], tmpstr2[80]; 1701 1702 /* 1703 * Setup the sysctl variable so the user can change the debug level 1704 * on the fly. 1705 */ 1706 snprintf(tmpstr, sizeof(tmpstr), "MPR controller %d", 1707 device_get_unit(sc->mpr_dev)); 1708 snprintf(tmpstr2, sizeof(tmpstr2), "%d", device_get_unit(sc->mpr_dev)); 1709 1710 sysctl_ctx = device_get_sysctl_ctx(sc->mpr_dev); 1711 if (sysctl_ctx != NULL) 1712 sysctl_tree = device_get_sysctl_tree(sc->mpr_dev); 1713 1714 if (sysctl_tree == NULL) { 1715 sysctl_ctx_init(&sc->sysctl_ctx); 1716 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 1717 SYSCTL_STATIC_CHILDREN(_hw_mpr), OID_AUTO, tmpstr2, 1718 CTLFLAG_RD, 0, tmpstr); 1719 if (sc->sysctl_tree == NULL) 1720 return; 1721 sysctl_ctx = &sc->sysctl_ctx; 1722 sysctl_tree = sc->sysctl_tree; 1723 } 1724 1725 SYSCTL_ADD_PROC(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1726 OID_AUTO, "debug_level", CTLTYPE_STRING | CTLFLAG_RW | CTLFLAG_MPSAFE, 1727 sc, 0, mpr_debug_sysctl, "A", "mpr debug level"); 1728 1729 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1730 OID_AUTO, "disable_msix", CTLFLAG_RD, &sc->disable_msix, 0, 1731 "Disable the use of MSI-X interrupts"); 1732 1733 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1734 OID_AUTO, "max_msix", CTLFLAG_RD, &sc->max_msix, 0, 1735 "User-defined maximum number of MSIX queues"); 1736 1737 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1738 OID_AUTO, "msix_msgs", CTLFLAG_RD, &sc->msi_msgs, 0, 1739 "Negotiated number of MSIX queues"); 1740 1741 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1742 OID_AUTO, "max_reqframes", CTLFLAG_RD, &sc->max_reqframes, 0, 1743 "Total number of allocated request frames"); 1744 1745 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1746 OID_AUTO, "max_prireqframes", CTLFLAG_RD, &sc->max_prireqframes, 0, 1747 "Total number of allocated high priority request frames"); 1748 1749 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1750 OID_AUTO, "max_replyframes", CTLFLAG_RD, &sc->max_replyframes, 0, 1751 "Total number of allocated reply frames"); 1752 1753 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1754 OID_AUTO, "max_evtframes", CTLFLAG_RD, &sc->max_evtframes, 0, 1755 "Total number of event frames allocated"); 1756 1757 SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1758 OID_AUTO, "firmware_version", CTLFLAG_RW, sc->fw_version, 1759 strlen(sc->fw_version), "firmware version"); 1760 1761 SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1762 OID_AUTO, "driver_version", CTLFLAG_RW, MPR_DRIVER_VERSION, 1763 strlen(MPR_DRIVER_VERSION), "driver version"); 1764 1765 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1766 OID_AUTO, "io_cmds_active", CTLFLAG_RD, 1767 &sc->io_cmds_active, 0, "number of currently active commands"); 1768 1769 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1770 OID_AUTO, "io_cmds_highwater", CTLFLAG_RD, 1771 &sc->io_cmds_highwater, 0, "maximum active commands seen"); 1772 1773 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1774 OID_AUTO, "chain_free", CTLFLAG_RD, 1775 &sc->chain_free, 0, "number of free chain elements"); 1776 1777 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1778 OID_AUTO, "chain_free_lowwater", CTLFLAG_RD, 1779 &sc->chain_free_lowwater, 0,"lowest number of free chain elements"); 1780 1781 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1782 OID_AUTO, "max_chains", CTLFLAG_RD, 1783 &sc->max_chains, 0,"maximum chain frames that will be allocated"); 1784 1785 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1786 OID_AUTO, "max_io_pages", CTLFLAG_RD, 1787 &sc->max_io_pages, 0,"maximum pages to allow per I/O (if <1 use " 1788 "IOCFacts)"); 1789 1790 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1791 OID_AUTO, "enable_ssu", CTLFLAG_RW, &sc->enable_ssu, 0, 1792 "enable SSU to SATA SSD/HDD at shutdown"); 1793 1794 SYSCTL_ADD_UQUAD(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1795 OID_AUTO, "chain_alloc_fail", CTLFLAG_RD, 1796 &sc->chain_alloc_fail, "chain allocation failures"); 1797 1798 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1799 OID_AUTO, "spinup_wait_time", CTLFLAG_RD, 1800 &sc->spinup_wait_time, DEFAULT_SPINUP_WAIT, "seconds to wait for " 1801 "spinup after SATA ID error"); 1802 1803 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1804 OID_AUTO, "use_phy_num", CTLFLAG_RD, &sc->use_phynum, 0, 1805 "Use the phy number for enumeration"); 1806 1807 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1808 OID_AUTO, "prp_pages_free", CTLFLAG_RD, 1809 &sc->prp_pages_free, 0, "number of free PRP pages"); 1810 1811 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1812 OID_AUTO, "prp_pages_free_lowwater", CTLFLAG_RD, 1813 &sc->prp_pages_free_lowwater, 0,"lowest number of free PRP pages"); 1814 1815 SYSCTL_ADD_UQUAD(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 1816 OID_AUTO, "prp_page_alloc_fail", CTLFLAG_RD, 1817 &sc->prp_page_alloc_fail, "PRP page allocation failures"); 1818 } 1819 1820 static struct mpr_debug_string { 1821 char *name; 1822 int flag; 1823 } mpr_debug_strings[] = { 1824 {"info", MPR_INFO}, 1825 {"fault", MPR_FAULT}, 1826 {"event", MPR_EVENT}, 1827 {"log", MPR_LOG}, 1828 {"recovery", MPR_RECOVERY}, 1829 {"error", MPR_ERROR}, 1830 {"init", MPR_INIT}, 1831 {"xinfo", MPR_XINFO}, 1832 {"user", MPR_USER}, 1833 {"mapping", MPR_MAPPING}, 1834 {"trace", MPR_TRACE} 1835 }; 1836 1837 static int 1838 mpr_debug_sysctl(SYSCTL_HANDLER_ARGS) 1839 { 1840 struct mpr_softc *sc; 1841 struct mpr_debug_string *string; 1842 struct sbuf *sbuf; 1843 char *buffer; 1844 size_t sz; 1845 int i, len, debug, error; 1846 1847 sc = (struct mpr_softc *)arg1; 1848 1849 error = sysctl_wire_old_buffer(req, 0); 1850 if (error != 0) 1851 return (error); 1852 1853 sbuf = sbuf_new_for_sysctl(NULL, NULL, 128, req); 1854 debug = sc->mpr_debug; 1855 1856 sbuf_printf(sbuf, "%#x", debug); 1857 1858 sz = sizeof(mpr_debug_strings) / sizeof(mpr_debug_strings[0]); 1859 for (i = 0; i < sz; i++) { 1860 string = &mpr_debug_strings[i]; 1861 if (debug & string->flag) 1862 sbuf_printf(sbuf, ",%s", string->name); 1863 } 1864 1865 error = sbuf_finish(sbuf); 1866 sbuf_delete(sbuf); 1867 1868 if (error || req->newptr == NULL) 1869 return (error); 1870 1871 len = req->newlen - req->newidx; 1872 if (len == 0) 1873 return (0); 1874 1875 buffer = malloc(len, M_MPR, M_ZERO|M_WAITOK); 1876 error = SYSCTL_IN(req, buffer, len); 1877 1878 mpr_parse_debug(sc, buffer); 1879 1880 free(buffer, M_MPR); 1881 return (error); 1882 } 1883 1884 static void 1885 mpr_parse_debug(struct mpr_softc *sc, char *list) 1886 { 1887 struct mpr_debug_string *string; 1888 char *token, *endtoken; 1889 size_t sz; 1890 int flags, i; 1891 1892 if (list == NULL || *list == '\0') 1893 return; 1894 1895 flags = 0; 1896 sz = sizeof(mpr_debug_strings) / sizeof(mpr_debug_strings[0]); 1897 while ((token = strsep(&list, ":,")) != NULL) { 1898 1899 /* Handle integer flags */ 1900 flags |= strtol(token, &endtoken, 0); 1901 if (token != endtoken) 1902 continue; 1903 1904 /* Handle text flags */ 1905 for (i = 0; i < sz; i++) { 1906 string = &mpr_debug_strings[i]; 1907 if (strcasecmp(token, string->name) == 0) { 1908 flags |= string->flag; 1909 break; 1910 } 1911 } 1912 } 1913 1914 sc->mpr_debug = flags; 1915 return; 1916 } 1917 1918 int 1919 mpr_attach(struct mpr_softc *sc) 1920 { 1921 int error; 1922 1923 MPR_FUNCTRACE(sc); 1924 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 1925 1926 mtx_init(&sc->mpr_mtx, "MPR lock", NULL, MTX_DEF); 1927 callout_init_mtx(&sc->periodic, &sc->mpr_mtx, 0); 1928 callout_init_mtx(&sc->device_check_callout, &sc->mpr_mtx, 0); 1929 TAILQ_INIT(&sc->event_list); 1930 timevalclear(&sc->lastfail); 1931 1932 if ((error = mpr_transition_ready(sc)) != 0) { 1933 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 1934 "Failed to transition ready\n"); 1935 return (error); 1936 } 1937 1938 sc->facts = malloc(sizeof(MPI2_IOC_FACTS_REPLY), M_MPR, 1939 M_ZERO|M_NOWAIT); 1940 if (!sc->facts) { 1941 mpr_dprint(sc, MPR_INIT|MPR_FAULT, 1942 "Cannot allocate memory, exit\n"); 1943 return (ENOMEM); 1944 } 1945 1946 /* 1947 * Get IOC Facts and allocate all structures based on this information. 1948 * A Diag Reset will also call mpr_iocfacts_allocate and re-read the IOC 1949 * Facts. If relevant values have changed in IOC Facts, this function 1950 * will free all of the memory based on IOC Facts and reallocate that 1951 * memory. If this fails, any allocated memory should already be freed. 1952 */ 1953 if ((error = mpr_iocfacts_allocate(sc, TRUE)) != 0) { 1954 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "IOC Facts allocation " 1955 "failed with error %d\n", error); 1956 return (error); 1957 } 1958 1959 /* Start the periodic watchdog check on the IOC Doorbell */ 1960 mpr_periodic(sc); 1961 1962 /* 1963 * The portenable will kick off discovery events that will drive the 1964 * rest of the initialization process. The CAM/SAS module will 1965 * hold up the boot sequence until discovery is complete. 1966 */ 1967 sc->mpr_ich.ich_func = mpr_startup; 1968 sc->mpr_ich.ich_arg = sc; 1969 if (config_intrhook_establish(&sc->mpr_ich) != 0) { 1970 mpr_dprint(sc, MPR_INIT|MPR_ERROR, 1971 "Cannot establish MPR config hook\n"); 1972 error = EINVAL; 1973 } 1974 1975 /* 1976 * Allow IR to shutdown gracefully when shutdown occurs. 1977 */ 1978 sc->shutdown_eh = EVENTHANDLER_REGISTER(shutdown_final, 1979 mprsas_ir_shutdown, sc, SHUTDOWN_PRI_DEFAULT); 1980 1981 if (sc->shutdown_eh == NULL) 1982 mpr_dprint(sc, MPR_INIT|MPR_ERROR, 1983 "shutdown event registration failed\n"); 1984 1985 mpr_setup_sysctl(sc); 1986 1987 sc->mpr_flags |= MPR_FLAGS_ATTACH_DONE; 1988 mpr_dprint(sc, MPR_INIT, "%s exit error= %d\n", __func__, error); 1989 1990 return (error); 1991 } 1992 1993 /* Run through any late-start handlers. */ 1994 static void 1995 mpr_startup(void *arg) 1996 { 1997 struct mpr_softc *sc; 1998 1999 sc = (struct mpr_softc *)arg; 2000 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 2001 2002 mpr_lock(sc); 2003 mpr_unmask_intr(sc); 2004 2005 /* initialize device mapping tables */ 2006 mpr_base_static_config_pages(sc); 2007 mpr_mapping_initialize(sc); 2008 mprsas_startup(sc); 2009 mpr_unlock(sc); 2010 2011 mpr_dprint(sc, MPR_INIT, "disestablish config intrhook\n"); 2012 config_intrhook_disestablish(&sc->mpr_ich); 2013 sc->mpr_ich.ich_arg = NULL; 2014 2015 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__); 2016 } 2017 2018 /* Periodic watchdog. Is called with the driver lock already held. */ 2019 static void 2020 mpr_periodic(void *arg) 2021 { 2022 struct mpr_softc *sc; 2023 uint32_t db; 2024 2025 sc = (struct mpr_softc *)arg; 2026 if (sc->mpr_flags & MPR_FLAGS_SHUTDOWN) 2027 return; 2028 2029 db = mpr_regread(sc, MPI2_DOORBELL_OFFSET); 2030 if ((db & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) { 2031 if ((db & MPI2_DOORBELL_FAULT_CODE_MASK) == 2032 IFAULT_IOP_OVER_TEMP_THRESHOLD_EXCEEDED) { 2033 panic("TEMPERATURE FAULT: STOPPING."); 2034 } 2035 mpr_dprint(sc, MPR_FAULT, "IOC Fault 0x%08x, Resetting\n", db); 2036 mpr_reinit(sc); 2037 } 2038 2039 callout_reset(&sc->periodic, MPR_PERIODIC_DELAY * hz, mpr_periodic, sc); 2040 } 2041 2042 static void 2043 mpr_log_evt_handler(struct mpr_softc *sc, uintptr_t data, 2044 MPI2_EVENT_NOTIFICATION_REPLY *event) 2045 { 2046 MPI2_EVENT_DATA_LOG_ENTRY_ADDED *entry; 2047 2048 MPR_DPRINT_EVENT(sc, generic, event); 2049 2050 switch (event->Event) { 2051 case MPI2_EVENT_LOG_DATA: 2052 mpr_dprint(sc, MPR_EVENT, "MPI2_EVENT_LOG_DATA:\n"); 2053 if (sc->mpr_debug & MPR_EVENT) 2054 hexdump(event->EventData, event->EventDataLength, NULL, 2055 0); 2056 break; 2057 case MPI2_EVENT_LOG_ENTRY_ADDED: 2058 entry = (MPI2_EVENT_DATA_LOG_ENTRY_ADDED *)event->EventData; 2059 mpr_dprint(sc, MPR_EVENT, "MPI2_EVENT_LOG_ENTRY_ADDED event " 2060 "0x%x Sequence %d:\n", entry->LogEntryQualifier, 2061 entry->LogSequence); 2062 break; 2063 default: 2064 break; 2065 } 2066 return; 2067 } 2068 2069 static int 2070 mpr_attach_log(struct mpr_softc *sc) 2071 { 2072 uint8_t events[16]; 2073 2074 bzero(events, 16); 2075 setbit(events, MPI2_EVENT_LOG_DATA); 2076 setbit(events, MPI2_EVENT_LOG_ENTRY_ADDED); 2077 2078 mpr_register_events(sc, events, mpr_log_evt_handler, NULL, 2079 &sc->mpr_log_eh); 2080 2081 return (0); 2082 } 2083 2084 static int 2085 mpr_detach_log(struct mpr_softc *sc) 2086 { 2087 2088 if (sc->mpr_log_eh != NULL) 2089 mpr_deregister_events(sc, sc->mpr_log_eh); 2090 return (0); 2091 } 2092 2093 /* 2094 * Free all of the driver resources and detach submodules. Should be called 2095 * without the lock held. 2096 */ 2097 int 2098 mpr_free(struct mpr_softc *sc) 2099 { 2100 int error; 2101 2102 mpr_dprint(sc, MPR_INIT, "%s entered\n", __func__); 2103 /* Turn off the watchdog */ 2104 mpr_lock(sc); 2105 sc->mpr_flags |= MPR_FLAGS_SHUTDOWN; 2106 mpr_unlock(sc); 2107 /* Lock must not be held for this */ 2108 callout_drain(&sc->periodic); 2109 callout_drain(&sc->device_check_callout); 2110 2111 if (((error = mpr_detach_log(sc)) != 0) || 2112 ((error = mpr_detach_sas(sc)) != 0)) { 2113 mpr_dprint(sc, MPR_INIT|MPR_FAULT, "failed to detach " 2114 "subsystems, error= %d, exit\n", error); 2115 return (error); 2116 } 2117 2118 mpr_detach_user(sc); 2119 2120 /* Put the IOC back in the READY state. */ 2121 mpr_lock(sc); 2122 if ((error = mpr_transition_ready(sc)) != 0) { 2123 mpr_unlock(sc); 2124 return (error); 2125 } 2126 mpr_unlock(sc); 2127 2128 if (sc->facts != NULL) 2129 free(sc->facts, M_MPR); 2130 2131 /* 2132 * Free all buffers that are based on IOC Facts. A Diag Reset may need 2133 * to free these buffers too. 2134 */ 2135 mpr_iocfacts_free(sc); 2136 2137 if (sc->sysctl_tree != NULL) 2138 sysctl_ctx_free(&sc->sysctl_ctx); 2139 2140 /* Deregister the shutdown function */ 2141 if (sc->shutdown_eh != NULL) 2142 EVENTHANDLER_DEREGISTER(shutdown_final, sc->shutdown_eh); 2143 2144 mtx_destroy(&sc->mpr_mtx); 2145 mpr_dprint(sc, MPR_INIT, "%s exit\n", __func__); 2146 2147 return (0); 2148 } 2149 2150 static __inline void 2151 mpr_complete_command(struct mpr_softc *sc, struct mpr_command *cm) 2152 { 2153 MPR_FUNCTRACE(sc); 2154 2155 if (cm == NULL) { 2156 mpr_dprint(sc, MPR_ERROR, "Completing NULL command\n"); 2157 return; 2158 } 2159 2160 if (cm->cm_flags & MPR_CM_FLAGS_POLLED) 2161 cm->cm_flags |= MPR_CM_FLAGS_COMPLETE; 2162 2163 if (cm->cm_complete != NULL) { 2164 mpr_dprint(sc, MPR_TRACE, 2165 "%s cm %p calling cm_complete %p data %p reply %p\n", 2166 __func__, cm, cm->cm_complete, cm->cm_complete_data, 2167 cm->cm_reply); 2168 cm->cm_complete(sc, cm); 2169 } 2170 2171 if (cm->cm_flags & MPR_CM_FLAGS_WAKEUP) { 2172 mpr_dprint(sc, MPR_TRACE, "waking up %p\n", cm); 2173 wakeup(cm); 2174 } 2175 2176 if (sc->io_cmds_active != 0) { 2177 sc->io_cmds_active--; 2178 } else { 2179 mpr_dprint(sc, MPR_ERROR, "Warning: io_cmds_active is " 2180 "out of sync - resynching to 0\n"); 2181 } 2182 } 2183 2184 static void 2185 mpr_sas_log_info(struct mpr_softc *sc , u32 log_info) 2186 { 2187 union loginfo_type { 2188 u32 loginfo; 2189 struct { 2190 u32 subcode:16; 2191 u32 code:8; 2192 u32 originator:4; 2193 u32 bus_type:4; 2194 } dw; 2195 }; 2196 union loginfo_type sas_loginfo; 2197 char *originator_str = NULL; 2198 2199 sas_loginfo.loginfo = log_info; 2200 if (sas_loginfo.dw.bus_type != 3 /*SAS*/) 2201 return; 2202 2203 /* each nexus loss loginfo */ 2204 if (log_info == 0x31170000) 2205 return; 2206 2207 /* eat the loginfos associated with task aborts */ 2208 if ((log_info == 30050000) || (log_info == 0x31140000) || 2209 (log_info == 0x31130000)) 2210 return; 2211 2212 switch (sas_loginfo.dw.originator) { 2213 case 0: 2214 originator_str = "IOP"; 2215 break; 2216 case 1: 2217 originator_str = "PL"; 2218 break; 2219 case 2: 2220 originator_str = "IR"; 2221 break; 2222 } 2223 2224 mpr_dprint(sc, MPR_LOG, "log_info(0x%08x): originator(%s), " 2225 "code(0x%02x), sub_code(0x%04x)\n", log_info, originator_str, 2226 sas_loginfo.dw.code, sas_loginfo.dw.subcode); 2227 } 2228 2229 static void 2230 mpr_display_reply_info(struct mpr_softc *sc, uint8_t *reply) 2231 { 2232 MPI2DefaultReply_t *mpi_reply; 2233 u16 sc_status; 2234 2235 mpi_reply = (MPI2DefaultReply_t*)reply; 2236 sc_status = le16toh(mpi_reply->IOCStatus); 2237 if (sc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) 2238 mpr_sas_log_info(sc, le32toh(mpi_reply->IOCLogInfo)); 2239 } 2240 2241 void 2242 mpr_intr(void *data) 2243 { 2244 struct mpr_softc *sc; 2245 uint32_t status; 2246 2247 sc = (struct mpr_softc *)data; 2248 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 2249 2250 /* 2251 * Check interrupt status register to flush the bus. This is 2252 * needed for both INTx interrupts and driver-driven polling 2253 */ 2254 status = mpr_regread(sc, MPI2_HOST_INTERRUPT_STATUS_OFFSET); 2255 if ((status & MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT) == 0) 2256 return; 2257 2258 mpr_lock(sc); 2259 mpr_intr_locked(data); 2260 mpr_unlock(sc); 2261 return; 2262 } 2263 2264 /* 2265 * In theory, MSI/MSIX interrupts shouldn't need to read any registers on the 2266 * chip. Hopefully this theory is correct. 2267 */ 2268 void 2269 mpr_intr_msi(void *data) 2270 { 2271 struct mpr_softc *sc; 2272 2273 sc = (struct mpr_softc *)data; 2274 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 2275 mpr_lock(sc); 2276 mpr_intr_locked(data); 2277 mpr_unlock(sc); 2278 return; 2279 } 2280 2281 /* 2282 * The locking is overly broad and simplistic, but easy to deal with for now. 2283 */ 2284 void 2285 mpr_intr_locked(void *data) 2286 { 2287 MPI2_REPLY_DESCRIPTORS_UNION *desc; 2288 struct mpr_softc *sc; 2289 struct mpr_command *cm = NULL; 2290 uint8_t flags; 2291 u_int pq; 2292 MPI2_DIAG_RELEASE_REPLY *rel_rep; 2293 mpr_fw_diagnostic_buffer_t *pBuffer; 2294 2295 sc = (struct mpr_softc *)data; 2296 2297 pq = sc->replypostindex; 2298 mpr_dprint(sc, MPR_TRACE, 2299 "%s sc %p starting with replypostindex %u\n", 2300 __func__, sc, sc->replypostindex); 2301 2302 for ( ;; ) { 2303 cm = NULL; 2304 desc = &sc->post_queue[sc->replypostindex]; 2305 flags = desc->Default.ReplyFlags & 2306 MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK; 2307 if ((flags == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) || 2308 (le32toh(desc->Words.High) == 0xffffffff)) 2309 break; 2310 2311 /* increment the replypostindex now, so that event handlers 2312 * and cm completion handlers which decide to do a diag 2313 * reset can zero it without it getting incremented again 2314 * afterwards, and we break out of this loop on the next 2315 * iteration since the reply post queue has been cleared to 2316 * 0xFF and all descriptors look unused (which they are). 2317 */ 2318 if (++sc->replypostindex >= sc->pqdepth) 2319 sc->replypostindex = 0; 2320 2321 switch (flags) { 2322 case MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS: 2323 case MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS: 2324 case MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS: 2325 cm = &sc->commands[le16toh(desc->SCSIIOSuccess.SMID)]; 2326 cm->cm_reply = NULL; 2327 break; 2328 case MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY: 2329 { 2330 uint32_t baddr; 2331 uint8_t *reply; 2332 2333 /* 2334 * Re-compose the reply address from the address 2335 * sent back from the chip. The ReplyFrameAddress 2336 * is the lower 32 bits of the physical address of 2337 * particular reply frame. Convert that address to 2338 * host format, and then use that to provide the 2339 * offset against the virtual address base 2340 * (sc->reply_frames). 2341 */ 2342 baddr = le32toh(desc->AddressReply.ReplyFrameAddress); 2343 reply = sc->reply_frames + 2344 (baddr - ((uint32_t)sc->reply_busaddr)); 2345 /* 2346 * Make sure the reply we got back is in a valid 2347 * range. If not, go ahead and panic here, since 2348 * we'll probably panic as soon as we deference the 2349 * reply pointer anyway. 2350 */ 2351 if ((reply < sc->reply_frames) 2352 || (reply > (sc->reply_frames + 2353 (sc->fqdepth * sc->facts->ReplyFrameSize * 4)))) { 2354 printf("%s: WARNING: reply %p out of range!\n", 2355 __func__, reply); 2356 printf("%s: reply_frames %p, fqdepth %d, " 2357 "frame size %d\n", __func__, 2358 sc->reply_frames, sc->fqdepth, 2359 sc->facts->ReplyFrameSize * 4); 2360 printf("%s: baddr %#x,\n", __func__, baddr); 2361 /* LSI-TODO. See Linux Code for Graceful exit */ 2362 panic("Reply address out of range"); 2363 } 2364 if (le16toh(desc->AddressReply.SMID) == 0) { 2365 if (((MPI2_DEFAULT_REPLY *)reply)->Function == 2366 MPI2_FUNCTION_DIAG_BUFFER_POST) { 2367 /* 2368 * If SMID is 0 for Diag Buffer Post, 2369 * this implies that the reply is due to 2370 * a release function with a status that 2371 * the buffer has been released. Set 2372 * the buffer flags accordingly. 2373 */ 2374 rel_rep = 2375 (MPI2_DIAG_RELEASE_REPLY *)reply; 2376 if ((le16toh(rel_rep->IOCStatus) & 2377 MPI2_IOCSTATUS_MASK) == 2378 MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED) 2379 { 2380 pBuffer = 2381 &sc->fw_diag_buffer_list[ 2382 rel_rep->BufferType]; 2383 pBuffer->valid_data = TRUE; 2384 pBuffer->owned_by_firmware = 2385 FALSE; 2386 pBuffer->immediate = FALSE; 2387 } 2388 } else 2389 mpr_dispatch_event(sc, baddr, 2390 (MPI2_EVENT_NOTIFICATION_REPLY *) 2391 reply); 2392 } else { 2393 cm = &sc->commands[ 2394 le16toh(desc->AddressReply.SMID)]; 2395 cm->cm_reply = reply; 2396 cm->cm_reply_data = 2397 le32toh(desc->AddressReply. 2398 ReplyFrameAddress); 2399 } 2400 break; 2401 } 2402 case MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS: 2403 case MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER: 2404 case MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS: 2405 default: 2406 /* Unhandled */ 2407 mpr_dprint(sc, MPR_ERROR, "Unhandled reply 0x%x\n", 2408 desc->Default.ReplyFlags); 2409 cm = NULL; 2410 break; 2411 } 2412 2413 if (cm != NULL) { 2414 // Print Error reply frame 2415 if (cm->cm_reply) 2416 mpr_display_reply_info(sc,cm->cm_reply); 2417 mpr_complete_command(sc, cm); 2418 } 2419 2420 desc->Words.Low = 0xffffffff; 2421 desc->Words.High = 0xffffffff; 2422 } 2423 2424 if (pq != sc->replypostindex) { 2425 mpr_dprint(sc, MPR_TRACE, 2426 "%s sc %p writing postindex %d\n", 2427 __func__, sc, sc->replypostindex); 2428 mpr_regwrite(sc, MPI2_REPLY_POST_HOST_INDEX_OFFSET, 2429 sc->replypostindex); 2430 } 2431 2432 return; 2433 } 2434 2435 static void 2436 mpr_dispatch_event(struct mpr_softc *sc, uintptr_t data, 2437 MPI2_EVENT_NOTIFICATION_REPLY *reply) 2438 { 2439 struct mpr_event_handle *eh; 2440 int event, handled = 0; 2441 2442 event = le16toh(reply->Event); 2443 TAILQ_FOREACH(eh, &sc->event_list, eh_list) { 2444 if (isset(eh->mask, event)) { 2445 eh->callback(sc, data, reply); 2446 handled++; 2447 } 2448 } 2449 2450 if (handled == 0) 2451 mpr_dprint(sc, MPR_EVENT, "Unhandled event 0x%x\n", 2452 le16toh(event)); 2453 2454 /* 2455 * This is the only place that the event/reply should be freed. 2456 * Anything wanting to hold onto the event data should have 2457 * already copied it into their own storage. 2458 */ 2459 mpr_free_reply(sc, data); 2460 } 2461 2462 static void 2463 mpr_reregister_events_complete(struct mpr_softc *sc, struct mpr_command *cm) 2464 { 2465 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 2466 2467 if (cm->cm_reply) 2468 MPR_DPRINT_EVENT(sc, generic, 2469 (MPI2_EVENT_NOTIFICATION_REPLY *)cm->cm_reply); 2470 2471 mpr_free_command(sc, cm); 2472 2473 /* next, send a port enable */ 2474 mprsas_startup(sc); 2475 } 2476 2477 /* 2478 * For both register_events and update_events, the caller supplies a bitmap 2479 * of events that it _wants_. These functions then turn that into a bitmask 2480 * suitable for the controller. 2481 */ 2482 int 2483 mpr_register_events(struct mpr_softc *sc, uint8_t *mask, 2484 mpr_evt_callback_t *cb, void *data, struct mpr_event_handle **handle) 2485 { 2486 struct mpr_event_handle *eh; 2487 int error = 0; 2488 2489 eh = malloc(sizeof(struct mpr_event_handle), M_MPR, M_WAITOK|M_ZERO); 2490 if (!eh) { 2491 mpr_dprint(sc, MPR_EVENT|MPR_ERROR, 2492 "Cannot allocate event memory\n"); 2493 return (ENOMEM); 2494 } 2495 eh->callback = cb; 2496 eh->data = data; 2497 TAILQ_INSERT_TAIL(&sc->event_list, eh, eh_list); 2498 if (mask != NULL) 2499 error = mpr_update_events(sc, eh, mask); 2500 *handle = eh; 2501 2502 return (error); 2503 } 2504 2505 int 2506 mpr_update_events(struct mpr_softc *sc, struct mpr_event_handle *handle, 2507 uint8_t *mask) 2508 { 2509 MPI2_EVENT_NOTIFICATION_REQUEST *evtreq; 2510 MPI2_EVENT_NOTIFICATION_REPLY *reply = NULL; 2511 struct mpr_command *cm = NULL; 2512 struct mpr_event_handle *eh; 2513 int error, i; 2514 2515 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 2516 2517 if ((mask != NULL) && (handle != NULL)) 2518 bcopy(mask, &handle->mask[0], 16); 2519 memset(sc->event_mask, 0xff, 16); 2520 2521 TAILQ_FOREACH(eh, &sc->event_list, eh_list) { 2522 for (i = 0; i < 16; i++) 2523 sc->event_mask[i] &= ~eh->mask[i]; 2524 } 2525 2526 if ((cm = mpr_alloc_command(sc)) == NULL) 2527 return (EBUSY); 2528 evtreq = (MPI2_EVENT_NOTIFICATION_REQUEST *)cm->cm_req; 2529 evtreq->Function = MPI2_FUNCTION_EVENT_NOTIFICATION; 2530 evtreq->MsgFlags = 0; 2531 evtreq->SASBroadcastPrimitiveMasks = 0; 2532 #ifdef MPR_DEBUG_ALL_EVENTS 2533 { 2534 u_char fullmask[16]; 2535 memset(fullmask, 0x00, 16); 2536 bcopy(fullmask, (uint8_t *)&evtreq->EventMasks, 16); 2537 } 2538 #else 2539 bcopy(sc->event_mask, (uint8_t *)&evtreq->EventMasks, 16); 2540 #endif 2541 cm->cm_desc.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 2542 cm->cm_data = NULL; 2543 2544 error = mpr_request_polled(sc, &cm); 2545 if (cm != NULL) 2546 reply = (MPI2_EVENT_NOTIFICATION_REPLY *)cm->cm_reply; 2547 if ((reply == NULL) || 2548 (reply->IOCStatus & MPI2_IOCSTATUS_MASK) != MPI2_IOCSTATUS_SUCCESS) 2549 error = ENXIO; 2550 2551 if (reply) 2552 MPR_DPRINT_EVENT(sc, generic, reply); 2553 2554 mpr_dprint(sc, MPR_TRACE, "%s finished error %d\n", __func__, error); 2555 2556 if (cm != NULL) 2557 mpr_free_command(sc, cm); 2558 return (error); 2559 } 2560 2561 static int 2562 mpr_reregister_events(struct mpr_softc *sc) 2563 { 2564 MPI2_EVENT_NOTIFICATION_REQUEST *evtreq; 2565 struct mpr_command *cm; 2566 struct mpr_event_handle *eh; 2567 int error, i; 2568 2569 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 2570 2571 /* first, reregister events */ 2572 2573 memset(sc->event_mask, 0xff, 16); 2574 2575 TAILQ_FOREACH(eh, &sc->event_list, eh_list) { 2576 for (i = 0; i < 16; i++) 2577 sc->event_mask[i] &= ~eh->mask[i]; 2578 } 2579 2580 if ((cm = mpr_alloc_command(sc)) == NULL) 2581 return (EBUSY); 2582 evtreq = (MPI2_EVENT_NOTIFICATION_REQUEST *)cm->cm_req; 2583 evtreq->Function = MPI2_FUNCTION_EVENT_NOTIFICATION; 2584 evtreq->MsgFlags = 0; 2585 evtreq->SASBroadcastPrimitiveMasks = 0; 2586 #ifdef MPR_DEBUG_ALL_EVENTS 2587 { 2588 u_char fullmask[16]; 2589 memset(fullmask, 0x00, 16); 2590 bcopy(fullmask, (uint8_t *)&evtreq->EventMasks, 16); 2591 } 2592 #else 2593 bcopy(sc->event_mask, (uint8_t *)&evtreq->EventMasks, 16); 2594 #endif 2595 cm->cm_desc.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 2596 cm->cm_data = NULL; 2597 cm->cm_complete = mpr_reregister_events_complete; 2598 2599 error = mpr_map_command(sc, cm); 2600 2601 mpr_dprint(sc, MPR_TRACE, "%s finished with error %d\n", __func__, 2602 error); 2603 return (error); 2604 } 2605 2606 int 2607 mpr_deregister_events(struct mpr_softc *sc, struct mpr_event_handle *handle) 2608 { 2609 2610 TAILQ_REMOVE(&sc->event_list, handle, eh_list); 2611 free(handle, M_MPR); 2612 return (mpr_update_events(sc, NULL, NULL)); 2613 } 2614 2615 /** 2616 * mpr_build_nvme_prp - This function is called for NVMe end devices to build a 2617 * native SGL (NVMe PRP). The native SGL is built starting in the first PRP entry 2618 * of the NVMe message (PRP1). If the data buffer is small enough to be described 2619 * entirely using PRP1, then PRP2 is not used. If needed, PRP2 is used to 2620 * describe a larger data buffer. If the data buffer is too large to describe 2621 * using the two PRP entriess inside the NVMe message, then PRP1 describes the 2622 * first data memory segment, and PRP2 contains a pointer to a PRP list located 2623 * elsewhere in memory to describe the remaining data memory segments. The PRP 2624 * list will be contiguous. 2625 2626 * The native SGL for NVMe devices is a Physical Region Page (PRP). A PRP 2627 * consists of a list of PRP entries to describe a number of noncontigous 2628 * physical memory segments as a single memory buffer, just as a SGL does. Note 2629 * however, that this function is only used by the IOCTL call, so the memory 2630 * given will be guaranteed to be contiguous. There is no need to translate 2631 * non-contiguous SGL into a PRP in this case. All PRPs will describe contiguous 2632 * space that is one page size each. 2633 * 2634 * Each NVMe message contains two PRP entries. The first (PRP1) either contains 2635 * a PRP list pointer or a PRP element, depending upon the command. PRP2 contains 2636 * the second PRP element if the memory being described fits within 2 PRP 2637 * entries, or a PRP list pointer if the PRP spans more than two entries. 2638 * 2639 * A PRP list pointer contains the address of a PRP list, structured as a linear 2640 * array of PRP entries. Each PRP entry in this list describes a segment of 2641 * physical memory. 2642 * 2643 * Each 64-bit PRP entry comprises an address and an offset field. The address 2644 * always points to the beginning of a PAGE_SIZE physical memory page, and the 2645 * offset describes where within that page the memory segment begins. Only the 2646 * first element in a PRP list may contain a non-zero offest, implying that all 2647 * memory segments following the first begin at the start of a PAGE_SIZE page. 2648 * 2649 * Each PRP element normally describes a chunck of PAGE_SIZE physical memory, 2650 * with exceptions for the first and last elements in the list. If the memory 2651 * being described by the list begins at a non-zero offset within the first page, 2652 * then the first PRP element will contain a non-zero offset indicating where the 2653 * region begins within the page. The last memory segment may end before the end 2654 * of the PAGE_SIZE segment, depending upon the overall size of the memory being 2655 * described by the PRP list. 2656 * 2657 * Since PRP entries lack any indication of size, the overall data buffer length 2658 * is used to determine where the end of the data memory buffer is located, and 2659 * how many PRP entries are required to describe it. 2660 * 2661 * Returns nothing. 2662 */ 2663 void 2664 mpr_build_nvme_prp(struct mpr_softc *sc, struct mpr_command *cm, 2665 Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request, void *data, 2666 uint32_t data_in_sz, uint32_t data_out_sz) 2667 { 2668 int prp_size = PRP_ENTRY_SIZE; 2669 uint64_t *prp_entry, *prp1_entry, *prp2_entry; 2670 uint64_t *prp_entry_phys, *prp_page, *prp_page_phys; 2671 uint32_t offset, entry_len, page_mask_result, page_mask; 2672 bus_addr_t paddr; 2673 size_t length; 2674 struct mpr_prp_page *prp_page_info = NULL; 2675 2676 /* 2677 * Not all commands require a data transfer. If no data, just return 2678 * without constructing any PRP. 2679 */ 2680 if (!data_in_sz && !data_out_sz) 2681 return; 2682 2683 /* 2684 * Set pointers to PRP1 and PRP2, which are in the NVMe command. PRP1 is 2685 * located at a 24 byte offset from the start of the NVMe command. Then 2686 * set the current PRP entry pointer to PRP1. 2687 */ 2688 prp1_entry = (uint64_t *)(nvme_encap_request->NVMe_Command + 2689 NVME_CMD_PRP1_OFFSET); 2690 prp2_entry = (uint64_t *)(nvme_encap_request->NVMe_Command + 2691 NVME_CMD_PRP2_OFFSET); 2692 prp_entry = prp1_entry; 2693 2694 /* 2695 * For the PRP entries, use the specially allocated buffer of 2696 * contiguous memory. PRP Page allocation failures should not happen 2697 * because there should be enough PRP page buffers to account for the 2698 * possible NVMe QDepth. 2699 */ 2700 prp_page_info = mpr_alloc_prp_page(sc); 2701 KASSERT(prp_page_info != NULL, ("%s: There are no PRP Pages left to be " 2702 "used for building a native NVMe SGL.\n", __func__)); 2703 prp_page = (uint64_t *)prp_page_info->prp_page; 2704 prp_page_phys = (uint64_t *)(uintptr_t)prp_page_info->prp_page_busaddr; 2705 2706 /* 2707 * Insert the allocated PRP page into the command's PRP page list. This 2708 * will be freed when the command is freed. 2709 */ 2710 TAILQ_INSERT_TAIL(&cm->cm_prp_page_list, prp_page_info, prp_page_link); 2711 2712 /* 2713 * Check if we are within 1 entry of a page boundary we don't want our 2714 * first entry to be a PRP List entry. 2715 */ 2716 page_mask = PAGE_SIZE - 1; 2717 page_mask_result = (uintptr_t)((uint8_t *)prp_page + prp_size) & 2718 page_mask; 2719 if (!page_mask_result) 2720 { 2721 /* Bump up to next page boundary. */ 2722 prp_page = (uint64_t *)((uint8_t *)prp_page + prp_size); 2723 prp_page_phys = (uint64_t *)((uint8_t *)prp_page_phys + 2724 prp_size); 2725 } 2726 2727 /* 2728 * Set PRP physical pointer, which initially points to the current PRP 2729 * DMA memory page. 2730 */ 2731 prp_entry_phys = prp_page_phys; 2732 2733 /* Get physical address and length of the data buffer. */ 2734 paddr = (bus_addr_t)data; 2735 if (data_in_sz) 2736 length = data_in_sz; 2737 else 2738 length = data_out_sz; 2739 2740 /* Loop while the length is not zero. */ 2741 while (length) 2742 { 2743 /* 2744 * Check if we need to put a list pointer here if we are at page 2745 * boundary - prp_size (8 bytes). 2746 */ 2747 page_mask_result = (uintptr_t)((uint8_t *)prp_entry_phys + 2748 prp_size) & page_mask; 2749 if (!page_mask_result) 2750 { 2751 /* 2752 * This is the last entry in a PRP List, so we need to 2753 * put a PRP list pointer here. What this does is: 2754 * - bump the current memory pointer to the next 2755 * address, which will be the next full page. 2756 * - set the PRP Entry to point to that page. This is 2757 * now the PRP List pointer. 2758 * - bump the PRP Entry pointer the start of the next 2759 * page. Since all of this PRP memory is contiguous, 2760 * no need to get a new page - it's just the next 2761 * address. 2762 */ 2763 prp_entry_phys++; 2764 *prp_entry = 2765 htole64((uint64_t)(uintptr_t)prp_entry_phys); 2766 prp_entry++; 2767 } 2768 2769 /* Need to handle if entry will be part of a page. */ 2770 offset = (uint32_t)paddr & page_mask; 2771 entry_len = PAGE_SIZE - offset; 2772 2773 if (prp_entry == prp1_entry) 2774 { 2775 /* 2776 * Must fill in the first PRP pointer (PRP1) before 2777 * moving on. 2778 */ 2779 *prp1_entry = htole64((uint64_t)paddr); 2780 2781 /* 2782 * Now point to the second PRP entry within the 2783 * command (PRP2). 2784 */ 2785 prp_entry = prp2_entry; 2786 } 2787 else if (prp_entry == prp2_entry) 2788 { 2789 /* 2790 * Should the PRP2 entry be a PRP List pointer or just a 2791 * regular PRP pointer? If there is more than one more 2792 * page of data, must use a PRP List pointer. 2793 */ 2794 if (length > PAGE_SIZE) 2795 { 2796 /* 2797 * PRP2 will contain a PRP List pointer because 2798 * more PRP's are needed with this command. The 2799 * list will start at the beginning of the 2800 * contiguous buffer. 2801 */ 2802 *prp2_entry = 2803 htole64( 2804 (uint64_t)(uintptr_t)prp_entry_phys); 2805 2806 /* 2807 * The next PRP Entry will be the start of the 2808 * first PRP List. 2809 */ 2810 prp_entry = prp_page; 2811 } 2812 else 2813 { 2814 /* 2815 * After this, the PRP Entries are complete. 2816 * This command uses 2 PRP's and no PRP list. 2817 */ 2818 *prp2_entry = htole64((uint64_t)paddr); 2819 } 2820 } 2821 else 2822 { 2823 /* 2824 * Put entry in list and bump the addresses. 2825 * 2826 * After PRP1 and PRP2 are filled in, this will fill in 2827 * all remaining PRP entries in a PRP List, one per each 2828 * time through the loop. 2829 */ 2830 *prp_entry = htole64((uint64_t)paddr); 2831 prp_entry++; 2832 prp_entry_phys++; 2833 } 2834 2835 /* 2836 * Bump the phys address of the command's data buffer by the 2837 * entry_len. 2838 */ 2839 paddr += entry_len; 2840 2841 /* Decrement length accounting for last partial page. */ 2842 if (entry_len > length) 2843 length = 0; 2844 else 2845 length -= entry_len; 2846 } 2847 } 2848 2849 /* 2850 * mpr_check_pcie_native_sgl - This function is called for PCIe end devices to 2851 * determine if the driver needs to build a native SGL. If so, that native SGL 2852 * is built in the contiguous buffers allocated especially for PCIe SGL 2853 * creation. If the driver will not build a native SGL, return TRUE and a 2854 * normal IEEE SGL will be built. Currently this routine supports NVMe devices 2855 * only. 2856 * 2857 * Returns FALSE (0) if native SGL was built, TRUE (1) if no SGL was built. 2858 */ 2859 static int 2860 mpr_check_pcie_native_sgl(struct mpr_softc *sc, struct mpr_command *cm, 2861 bus_dma_segment_t *segs, int segs_left) 2862 { 2863 uint32_t i, sge_dwords, length, offset, entry_len; 2864 uint32_t num_entries, buff_len = 0, sges_in_segment; 2865 uint32_t page_mask, page_mask_result, *curr_buff; 2866 uint32_t *ptr_sgl, *ptr_first_sgl, first_page_offset; 2867 uint32_t first_page_data_size, end_residual; 2868 uint64_t *msg_phys; 2869 bus_addr_t paddr; 2870 int build_native_sgl = 0, first_prp_entry; 2871 int prp_size = PRP_ENTRY_SIZE; 2872 Mpi25IeeeSgeChain64_t *main_chain_element = NULL; 2873 struct mpr_prp_page *prp_page_info = NULL; 2874 2875 mpr_dprint(sc, MPR_TRACE, "%s\n", __func__); 2876 2877 /* 2878 * Add up the sizes of each segment length to get the total transfer 2879 * size, which will be checked against the Maximum Data Transfer Size. 2880 * If the data transfer length exceeds the MDTS for this device, just 2881 * return 1 so a normal IEEE SGL will be built. F/W will break the I/O 2882 * up into multiple I/O's. [nvme_mdts = 0 means unlimited] 2883 */ 2884 for (i = 0; i < segs_left; i++) 2885 buff_len += htole32(segs[i].ds_len); 2886 if ((cm->cm_targ->MDTS > 0) && (buff_len > cm->cm_targ->MDTS)) 2887 return 1; 2888 2889 /* Create page_mask (to get offset within page) */ 2890 page_mask = PAGE_SIZE - 1; 2891 2892 /* 2893 * Check if the number of elements exceeds the max number that can be 2894 * put in the main message frame (H/W can only translate an SGL that 2895 * is contained entirely in the main message frame). 2896 */ 2897 sges_in_segment = (sc->facts->IOCRequestFrameSize - 2898 offsetof(Mpi25SCSIIORequest_t, SGL)) / sizeof(MPI25_SGE_IO_UNION); 2899 if (segs_left > sges_in_segment) 2900 build_native_sgl = 1; 2901 else 2902 { 2903 /* 2904 * NVMe uses one PRP for each physical page (or part of physical 2905 * page). 2906 * if 4 pages or less then IEEE is OK 2907 * if > 5 pages then we need to build a native SGL 2908 * if > 4 and <= 5 pages, then check the physical address of 2909 * the first SG entry, then if this first size in the page 2910 * is >= the residual beyond 4 pages then use IEEE, 2911 * otherwise use native SGL 2912 */ 2913 if (buff_len > (PAGE_SIZE * 5)) 2914 build_native_sgl = 1; 2915 else if ((buff_len > (PAGE_SIZE * 4)) && 2916 (buff_len <= (PAGE_SIZE * 5)) ) 2917 { 2918 msg_phys = (uint64_t *)segs[0].ds_addr; 2919 first_page_offset = 2920 ((uint32_t)(uint64_t)(uintptr_t)msg_phys & 2921 page_mask); 2922 first_page_data_size = PAGE_SIZE - first_page_offset; 2923 end_residual = buff_len % PAGE_SIZE; 2924 2925 /* 2926 * If offset into first page pushes the end of the data 2927 * beyond end of the 5th page, we need the extra PRP 2928 * list. 2929 */ 2930 if (first_page_data_size < end_residual) 2931 build_native_sgl = 1; 2932 2933 /* 2934 * Check if first SG entry size is < residual beyond 4 2935 * pages. 2936 */ 2937 if (htole32(segs[0].ds_len) < 2938 (buff_len - (PAGE_SIZE * 4))) 2939 build_native_sgl = 1; 2940 } 2941 } 2942 2943 /* check if native SGL is needed */ 2944 if (!build_native_sgl) 2945 return 1; 2946 2947 /* 2948 * Native SGL is needed. 2949 * Put a chain element in main message frame that points to the first 2950 * chain buffer. 2951 * 2952 * NOTE: The ChainOffset field must be 0 when using a chain pointer to 2953 * a native SGL. 2954 */ 2955 2956 /* Set main message chain element pointer */ 2957 main_chain_element = (pMpi25IeeeSgeChain64_t)cm->cm_sge; 2958 2959 /* 2960 * For NVMe the chain element needs to be the 2nd SGL entry in the main 2961 * message. 2962 */ 2963 main_chain_element = (Mpi25IeeeSgeChain64_t *) 2964 ((uint8_t *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64)); 2965 2966 /* 2967 * For the PRP entries, use the specially allocated buffer of 2968 * contiguous memory. PRP Page allocation failures should not happen 2969 * because there should be enough PRP page buffers to account for the 2970 * possible NVMe QDepth. 2971 */ 2972 prp_page_info = mpr_alloc_prp_page(sc); 2973 KASSERT(prp_page_info != NULL, ("%s: There are no PRP Pages left to be " 2974 "used for building a native NVMe SGL.\n", __func__)); 2975 curr_buff = (uint32_t *)prp_page_info->prp_page; 2976 msg_phys = (uint64_t *)(uintptr_t)prp_page_info->prp_page_busaddr; 2977 2978 /* 2979 * Insert the allocated PRP page into the command's PRP page list. This 2980 * will be freed when the command is freed. 2981 */ 2982 TAILQ_INSERT_TAIL(&cm->cm_prp_page_list, prp_page_info, prp_page_link); 2983 2984 /* 2985 * Check if we are within 1 entry of a page boundary we don't want our 2986 * first entry to be a PRP List entry. 2987 */ 2988 page_mask_result = (uintptr_t)((uint8_t *)curr_buff + prp_size) & 2989 page_mask; 2990 if (!page_mask_result) { 2991 /* Bump up to next page boundary. */ 2992 curr_buff = (uint32_t *)((uint8_t *)curr_buff + prp_size); 2993 msg_phys = (uint64_t *)((uint8_t *)msg_phys + prp_size); 2994 } 2995 2996 /* Fill in the chain element and make it an NVMe segment type. */ 2997 main_chain_element->Address.High = 2998 htole32((uint32_t)((uint64_t)(uintptr_t)msg_phys >> 32)); 2999 main_chain_element->Address.Low = 3000 htole32((uint32_t)(uintptr_t)msg_phys); 3001 main_chain_element->NextChainOffset = 0; 3002 main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 3003 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | 3004 MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP; 3005 3006 /* Set SGL pointer to start of contiguous PCIe buffer. */ 3007 ptr_sgl = curr_buff; 3008 sge_dwords = 2; 3009 num_entries = 0; 3010 3011 /* 3012 * NVMe has a very convoluted PRP format. One PRP is required for each 3013 * page or partial page. We need to split up OS SG entries if they are 3014 * longer than one page or cross a page boundary. We also have to insert 3015 * a PRP list pointer entry as the last entry in each physical page of 3016 * the PRP list. 3017 * 3018 * NOTE: The first PRP "entry" is actually placed in the first SGL entry 3019 * in the main message in IEEE 64 format. The 2nd entry in the main 3020 * message is the chain element, and the rest of the PRP entries are 3021 * built in the contiguous PCIe buffer. 3022 */ 3023 first_prp_entry = 1; 3024 ptr_first_sgl = (uint32_t *)cm->cm_sge; 3025 3026 for (i = 0; i < segs_left; i++) { 3027 /* Get physical address and length of this SG entry. */ 3028 paddr = segs[i].ds_addr; 3029 length = segs[i].ds_len; 3030 3031 /* 3032 * Check whether a given SGE buffer lies on a non-PAGED 3033 * boundary if this is not the first page. If so, this is not 3034 * expected so have FW build the SGL. 3035 */ 3036 if ((i != 0) && (((uint32_t)paddr & page_mask) != 0)) { 3037 mpr_dprint(sc, MPR_ERROR, "Unaligned SGE while " 3038 "building NVMe PRPs, low address is 0x%x\n", 3039 (uint32_t)paddr); 3040 return 1; 3041 } 3042 3043 /* Apart from last SGE, if any other SGE boundary is not page 3044 * aligned then it means that hole exists. Existence of hole 3045 * leads to data corruption. So fallback to IEEE SGEs. 3046 */ 3047 if (i != (segs_left - 1)) { 3048 if (((uint32_t)paddr + length) & page_mask) { 3049 mpr_dprint(sc, MPR_ERROR, "Unaligned SGE " 3050 "boundary while building NVMe PRPs, low " 3051 "address: 0x%x and length: %u\n", 3052 (uint32_t)paddr, length); 3053 return 1; 3054 } 3055 } 3056 3057 /* Loop while the length is not zero. */ 3058 while (length) { 3059 /* 3060 * Check if we need to put a list pointer here if we are 3061 * at page boundary - prp_size. 3062 */ 3063 page_mask_result = (uintptr_t)((uint8_t *)ptr_sgl + 3064 prp_size) & page_mask; 3065 if (!page_mask_result) { 3066 /* 3067 * Need to put a PRP list pointer here. 3068 */ 3069 msg_phys = (uint64_t *)((uint8_t *)msg_phys + 3070 prp_size); 3071 *ptr_sgl = htole32((uintptr_t)msg_phys); 3072 *(ptr_sgl+1) = htole32((uint64_t)(uintptr_t) 3073 msg_phys >> 32); 3074 ptr_sgl += sge_dwords; 3075 num_entries++; 3076 } 3077 3078 /* Need to handle if entry will be part of a page. */ 3079 offset = (uint32_t)paddr & page_mask; 3080 entry_len = PAGE_SIZE - offset; 3081 if (first_prp_entry) { 3082 /* 3083 * Put IEEE entry in first SGE in main message. 3084 * (Simple element, System addr, not end of 3085 * list.) 3086 */ 3087 *ptr_first_sgl = htole32((uint32_t)paddr); 3088 *(ptr_first_sgl + 1) = 3089 htole32((uint32_t)((uint64_t)paddr >> 32)); 3090 *(ptr_first_sgl + 2) = htole32(entry_len); 3091 *(ptr_first_sgl + 3) = 0; 3092 3093 /* No longer the first PRP entry. */ 3094 first_prp_entry = 0; 3095 } else { 3096 /* Put entry in list. */ 3097 *ptr_sgl = htole32((uint32_t)paddr); 3098 *(ptr_sgl + 1) = 3099 htole32((uint32_t)((uint64_t)paddr >> 32)); 3100 3101 /* Bump ptr_sgl, msg_phys, and num_entries. */ 3102 ptr_sgl += sge_dwords; 3103 msg_phys = (uint64_t *)((uint8_t *)msg_phys + 3104 prp_size); 3105 num_entries++; 3106 } 3107 3108 /* Bump the phys address by the entry_len. */ 3109 paddr += entry_len; 3110 3111 /* Decrement length accounting for last partial page. */ 3112 if (entry_len > length) 3113 length = 0; 3114 else 3115 length -= entry_len; 3116 } 3117 } 3118 3119 /* Set chain element Length. */ 3120 main_chain_element->Length = htole32(num_entries * prp_size); 3121 3122 /* Return 0, indicating we built a native SGL. */ 3123 return 0; 3124 } 3125 3126 /* 3127 * Add a chain element as the next SGE for the specified command. 3128 * Reset cm_sge and cm_sgesize to indicate all the available space. Chains are 3129 * only required for IEEE commands. Therefore there is no code for commands 3130 * that have the MPR_CM_FLAGS_SGE_SIMPLE flag set (and those commands 3131 * shouldn't be requesting chains). 3132 */ 3133 static int 3134 mpr_add_chain(struct mpr_command *cm, int segsleft) 3135 { 3136 struct mpr_softc *sc = cm->cm_sc; 3137 MPI2_REQUEST_HEADER *req; 3138 MPI25_IEEE_SGE_CHAIN64 *ieee_sgc; 3139 struct mpr_chain *chain; 3140 int sgc_size, current_segs, rem_segs, segs_per_frame; 3141 uint8_t next_chain_offset = 0; 3142 3143 /* 3144 * Fail if a command is requesting a chain for SIMPLE SGE's. For SAS3 3145 * only IEEE commands should be requesting chains. Return some error 3146 * code other than 0. 3147 */ 3148 if (cm->cm_flags & MPR_CM_FLAGS_SGE_SIMPLE) { 3149 mpr_dprint(sc, MPR_ERROR, "A chain element cannot be added to " 3150 "an MPI SGL.\n"); 3151 return(ENOBUFS); 3152 } 3153 3154 sgc_size = sizeof(MPI25_IEEE_SGE_CHAIN64); 3155 if (cm->cm_sglsize < sgc_size) 3156 panic("MPR: Need SGE Error Code\n"); 3157 3158 chain = mpr_alloc_chain(cm->cm_sc); 3159 if (chain == NULL) 3160 return (ENOBUFS); 3161 3162 /* 3163 * Note: a double-linked list is used to make it easier to walk for 3164 * debugging. 3165 */ 3166 TAILQ_INSERT_TAIL(&cm->cm_chain_list, chain, chain_link); 3167 3168 /* 3169 * Need to know if the number of frames left is more than 1 or not. If 3170 * more than 1 frame is required, NextChainOffset will need to be set, 3171 * which will just be the last segment of the frame. 3172 */ 3173 rem_segs = 0; 3174 if (cm->cm_sglsize < (sgc_size * segsleft)) { 3175 /* 3176 * rem_segs is the number of segements remaining after the 3177 * segments that will go into the current frame. Since it is 3178 * known that at least one more frame is required, account for 3179 * the chain element. To know if more than one more frame is 3180 * required, just check if there will be a remainder after using 3181 * the current frame (with this chain) and the next frame. If 3182 * so the NextChainOffset must be the last element of the next 3183 * frame. 3184 */ 3185 current_segs = (cm->cm_sglsize / sgc_size) - 1; 3186 rem_segs = segsleft - current_segs; 3187 segs_per_frame = sc->chain_frame_size / sgc_size; 3188 if (rem_segs > segs_per_frame) { 3189 next_chain_offset = segs_per_frame - 1; 3190 } 3191 } 3192 ieee_sgc = &((MPI25_SGE_IO_UNION *)cm->cm_sge)->IeeeChain; 3193 ieee_sgc->Length = next_chain_offset ? 3194 htole32((uint32_t)sc->chain_frame_size) : 3195 htole32((uint32_t)rem_segs * (uint32_t)sgc_size); 3196 ieee_sgc->NextChainOffset = next_chain_offset; 3197 ieee_sgc->Flags = (MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT | 3198 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 3199 ieee_sgc->Address.Low = htole32(chain->chain_busaddr); 3200 ieee_sgc->Address.High = htole32(chain->chain_busaddr >> 32); 3201 cm->cm_sge = &((MPI25_SGE_IO_UNION *)chain->chain)->IeeeSimple; 3202 req = (MPI2_REQUEST_HEADER *)cm->cm_req; 3203 req->ChainOffset = (sc->chain_frame_size - sgc_size) >> 4; 3204 3205 cm->cm_sglsize = sc->chain_frame_size; 3206 return (0); 3207 } 3208 3209 /* 3210 * Add one scatter-gather element to the scatter-gather list for a command. 3211 * Maintain cm_sglsize and cm_sge as the remaining size and pointer to the 3212 * next SGE to fill in, respectively. In Gen3, the MPI SGL does not have a 3213 * chain, so don't consider any chain additions. 3214 */ 3215 int 3216 mpr_push_sge(struct mpr_command *cm, MPI2_SGE_SIMPLE64 *sge, size_t len, 3217 int segsleft) 3218 { 3219 uint32_t saved_buf_len, saved_address_low, saved_address_high; 3220 u32 sge_flags; 3221 3222 /* 3223 * case 1: >=1 more segment, no room for anything (error) 3224 * case 2: 1 more segment and enough room for it 3225 */ 3226 3227 if (cm->cm_sglsize < (segsleft * sizeof(MPI2_SGE_SIMPLE64))) { 3228 mpr_dprint(cm->cm_sc, MPR_ERROR, 3229 "%s: warning: Not enough room for MPI SGL in frame.\n", 3230 __func__); 3231 return(ENOBUFS); 3232 } 3233 3234 KASSERT(segsleft == 1, 3235 ("segsleft cannot be more than 1 for an MPI SGL; segsleft = %d\n", 3236 segsleft)); 3237 3238 /* 3239 * There is one more segment left to add for the MPI SGL and there is 3240 * enough room in the frame to add it. This is the normal case because 3241 * MPI SGL's don't have chains, otherwise something is wrong. 3242 * 3243 * If this is a bi-directional request, need to account for that 3244 * here. Save the pre-filled sge values. These will be used 3245 * either for the 2nd SGL or for a single direction SGL. If 3246 * cm_out_len is non-zero, this is a bi-directional request, so 3247 * fill in the OUT SGL first, then the IN SGL, otherwise just 3248 * fill in the IN SGL. Note that at this time, when filling in 3249 * 2 SGL's for a bi-directional request, they both use the same 3250 * DMA buffer (same cm command). 3251 */ 3252 saved_buf_len = sge->FlagsLength & 0x00FFFFFF; 3253 saved_address_low = sge->Address.Low; 3254 saved_address_high = sge->Address.High; 3255 if (cm->cm_out_len) { 3256 sge->FlagsLength = cm->cm_out_len | 3257 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 3258 MPI2_SGE_FLAGS_END_OF_BUFFER | 3259 MPI2_SGE_FLAGS_HOST_TO_IOC | 3260 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 3261 MPI2_SGE_FLAGS_SHIFT); 3262 cm->cm_sglsize -= len; 3263 /* Endian Safe code */ 3264 sge_flags = sge->FlagsLength; 3265 sge->FlagsLength = htole32(sge_flags); 3266 sge->Address.High = htole32(sge->Address.High); 3267 sge->Address.Low = htole32(sge->Address.Low); 3268 bcopy(sge, cm->cm_sge, len); 3269 cm->cm_sge = (MPI2_SGE_IO_UNION *)((uintptr_t)cm->cm_sge + len); 3270 } 3271 sge->FlagsLength = saved_buf_len | 3272 ((uint32_t)(MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 3273 MPI2_SGE_FLAGS_END_OF_BUFFER | 3274 MPI2_SGE_FLAGS_LAST_ELEMENT | 3275 MPI2_SGE_FLAGS_END_OF_LIST | 3276 MPI2_SGE_FLAGS_64_BIT_ADDRESSING) << 3277 MPI2_SGE_FLAGS_SHIFT); 3278 if (cm->cm_flags & MPR_CM_FLAGS_DATAIN) { 3279 sge->FlagsLength |= 3280 ((uint32_t)(MPI2_SGE_FLAGS_IOC_TO_HOST) << 3281 MPI2_SGE_FLAGS_SHIFT); 3282 } else { 3283 sge->FlagsLength |= 3284 ((uint32_t)(MPI2_SGE_FLAGS_HOST_TO_IOC) << 3285 MPI2_SGE_FLAGS_SHIFT); 3286 } 3287 sge->Address.Low = saved_address_low; 3288 sge->Address.High = saved_address_high; 3289 3290 cm->cm_sglsize -= len; 3291 /* Endian Safe code */ 3292 sge_flags = sge->FlagsLength; 3293 sge->FlagsLength = htole32(sge_flags); 3294 sge->Address.High = htole32(sge->Address.High); 3295 sge->Address.Low = htole32(sge->Address.Low); 3296 bcopy(sge, cm->cm_sge, len); 3297 cm->cm_sge = (MPI2_SGE_IO_UNION *)((uintptr_t)cm->cm_sge + len); 3298 return (0); 3299 } 3300 3301 /* 3302 * Add one IEEE scatter-gather element (chain or simple) to the IEEE scatter- 3303 * gather list for a command. Maintain cm_sglsize and cm_sge as the 3304 * remaining size and pointer to the next SGE to fill in, respectively. 3305 */ 3306 int 3307 mpr_push_ieee_sge(struct mpr_command *cm, void *sgep, int segsleft) 3308 { 3309 MPI2_IEEE_SGE_SIMPLE64 *sge = sgep; 3310 int error, ieee_sge_size = sizeof(MPI25_SGE_IO_UNION); 3311 uint32_t saved_buf_len, saved_address_low, saved_address_high; 3312 uint32_t sge_length; 3313 3314 /* 3315 * case 1: No room for chain or segment (error). 3316 * case 2: Two or more segments left but only room for chain. 3317 * case 3: Last segment and room for it, so set flags. 3318 */ 3319 3320 /* 3321 * There should be room for at least one element, or there is a big 3322 * problem. 3323 */ 3324 if (cm->cm_sglsize < ieee_sge_size) 3325 panic("MPR: Need SGE Error Code\n"); 3326 3327 if ((segsleft >= 2) && (cm->cm_sglsize < (ieee_sge_size * 2))) { 3328 if ((error = mpr_add_chain(cm, segsleft)) != 0) 3329 return (error); 3330 } 3331 3332 if (segsleft == 1) { 3333 /* 3334 * If this is a bi-directional request, need to account for that 3335 * here. Save the pre-filled sge values. These will be used 3336 * either for the 2nd SGL or for a single direction SGL. If 3337 * cm_out_len is non-zero, this is a bi-directional request, so 3338 * fill in the OUT SGL first, then the IN SGL, otherwise just 3339 * fill in the IN SGL. Note that at this time, when filling in 3340 * 2 SGL's for a bi-directional request, they both use the same 3341 * DMA buffer (same cm command). 3342 */ 3343 saved_buf_len = sge->Length; 3344 saved_address_low = sge->Address.Low; 3345 saved_address_high = sge->Address.High; 3346 if (cm->cm_out_len) { 3347 sge->Length = cm->cm_out_len; 3348 sge->Flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 3349 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 3350 cm->cm_sglsize -= ieee_sge_size; 3351 /* Endian Safe code */ 3352 sge_length = sge->Length; 3353 sge->Length = htole32(sge_length); 3354 sge->Address.High = htole32(sge->Address.High); 3355 sge->Address.Low = htole32(sge->Address.Low); 3356 bcopy(sgep, cm->cm_sge, ieee_sge_size); 3357 cm->cm_sge = 3358 (MPI25_SGE_IO_UNION *)((uintptr_t)cm->cm_sge + 3359 ieee_sge_size); 3360 } 3361 sge->Length = saved_buf_len; 3362 sge->Flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 3363 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR | 3364 MPI25_IEEE_SGE_FLAGS_END_OF_LIST); 3365 sge->Address.Low = saved_address_low; 3366 sge->Address.High = saved_address_high; 3367 } 3368 3369 cm->cm_sglsize -= ieee_sge_size; 3370 /* Endian Safe code */ 3371 sge_length = sge->Length; 3372 sge->Length = htole32(sge_length); 3373 sge->Address.High = htole32(sge->Address.High); 3374 sge->Address.Low = htole32(sge->Address.Low); 3375 bcopy(sgep, cm->cm_sge, ieee_sge_size); 3376 cm->cm_sge = (MPI25_SGE_IO_UNION *)((uintptr_t)cm->cm_sge + 3377 ieee_sge_size); 3378 return (0); 3379 } 3380 3381 /* 3382 * Add one dma segment to the scatter-gather list for a command. 3383 */ 3384 int 3385 mpr_add_dmaseg(struct mpr_command *cm, vm_paddr_t pa, size_t len, u_int flags, 3386 int segsleft) 3387 { 3388 MPI2_SGE_SIMPLE64 sge; 3389 MPI2_IEEE_SGE_SIMPLE64 ieee_sge; 3390 3391 if (!(cm->cm_flags & MPR_CM_FLAGS_SGE_SIMPLE)) { 3392 ieee_sge.Flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT | 3393 MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR); 3394 ieee_sge.Length = len; 3395 mpr_from_u64(pa, &ieee_sge.Address); 3396 3397 return (mpr_push_ieee_sge(cm, &ieee_sge, segsleft)); 3398 } else { 3399 /* 3400 * This driver always uses 64-bit address elements for 3401 * simplicity. 3402 */ 3403 flags |= MPI2_SGE_FLAGS_SIMPLE_ELEMENT | 3404 MPI2_SGE_FLAGS_64_BIT_ADDRESSING; 3405 /* Set Endian safe macro in mpr_push_sge */ 3406 sge.FlagsLength = len | (flags << MPI2_SGE_FLAGS_SHIFT); 3407 mpr_from_u64(pa, &sge.Address); 3408 3409 return (mpr_push_sge(cm, &sge, sizeof sge, segsleft)); 3410 } 3411 } 3412 3413 static void 3414 mpr_data_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 3415 { 3416 struct mpr_softc *sc; 3417 struct mpr_command *cm; 3418 u_int i, dir, sflags; 3419 3420 cm = (struct mpr_command *)arg; 3421 sc = cm->cm_sc; 3422 3423 /* 3424 * In this case, just print out a warning and let the chip tell the 3425 * user they did the wrong thing. 3426 */ 3427 if ((cm->cm_max_segs != 0) && (nsegs > cm->cm_max_segs)) { 3428 mpr_dprint(sc, MPR_ERROR, "%s: warning: busdma returned %d " 3429 "segments, more than the %d allowed\n", __func__, nsegs, 3430 cm->cm_max_segs); 3431 } 3432 3433 /* 3434 * Set up DMA direction flags. Bi-directional requests are also handled 3435 * here. In that case, both direction flags will be set. 3436 */ 3437 sflags = 0; 3438 if (cm->cm_flags & MPR_CM_FLAGS_SMP_PASS) { 3439 /* 3440 * We have to add a special case for SMP passthrough, there 3441 * is no easy way to generically handle it. The first 3442 * S/G element is used for the command (therefore the 3443 * direction bit needs to be set). The second one is used 3444 * for the reply. We'll leave it to the caller to make 3445 * sure we only have two buffers. 3446 */ 3447 /* 3448 * Even though the busdma man page says it doesn't make 3449 * sense to have both direction flags, it does in this case. 3450 * We have one s/g element being accessed in each direction. 3451 */ 3452 dir = BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD; 3453 3454 /* 3455 * Set the direction flag on the first buffer in the SMP 3456 * passthrough request. We'll clear it for the second one. 3457 */ 3458 sflags |= MPI2_SGE_FLAGS_DIRECTION | 3459 MPI2_SGE_FLAGS_END_OF_BUFFER; 3460 } else if (cm->cm_flags & MPR_CM_FLAGS_DATAOUT) { 3461 sflags |= MPI2_SGE_FLAGS_HOST_TO_IOC; 3462 dir = BUS_DMASYNC_PREWRITE; 3463 } else 3464 dir = BUS_DMASYNC_PREREAD; 3465 3466 /* Check if a native SG list is needed for an NVMe PCIe device. */ 3467 if (cm->cm_targ && cm->cm_targ->is_nvme && 3468 mpr_check_pcie_native_sgl(sc, cm, segs, nsegs) == 0) { 3469 /* A native SG list was built, skip to end. */ 3470 goto out; 3471 } 3472 3473 for (i = 0; i < nsegs; i++) { 3474 if ((cm->cm_flags & MPR_CM_FLAGS_SMP_PASS) && (i != 0)) { 3475 sflags &= ~MPI2_SGE_FLAGS_DIRECTION; 3476 } 3477 error = mpr_add_dmaseg(cm, segs[i].ds_addr, segs[i].ds_len, 3478 sflags, nsegs - i); 3479 if (error != 0) { 3480 /* Resource shortage, roll back! */ 3481 if (ratecheck(&sc->lastfail, &mpr_chainfail_interval)) 3482 mpr_dprint(sc, MPR_INFO, "Out of chain frames, " 3483 "consider increasing hw.mpr.max_chains.\n"); 3484 cm->cm_flags |= MPR_CM_FLAGS_CHAIN_FAILED; 3485 mpr_complete_command(sc, cm); 3486 return; 3487 } 3488 } 3489 3490 out: 3491 bus_dmamap_sync(sc->buffer_dmat, cm->cm_dmamap, dir); 3492 mpr_enqueue_request(sc, cm); 3493 3494 return; 3495 } 3496 3497 static void 3498 mpr_data_cb2(void *arg, bus_dma_segment_t *segs, int nsegs, bus_size_t mapsize, 3499 int error) 3500 { 3501 mpr_data_cb(arg, segs, nsegs, error); 3502 } 3503 3504 /* 3505 * This is the routine to enqueue commands ansynchronously. 3506 * Note that the only error path here is from bus_dmamap_load(), which can 3507 * return EINPROGRESS if it is waiting for resources. Other than this, it's 3508 * assumed that if you have a command in-hand, then you have enough credits 3509 * to use it. 3510 */ 3511 int 3512 mpr_map_command(struct mpr_softc *sc, struct mpr_command *cm) 3513 { 3514 int error = 0; 3515 3516 if (cm->cm_flags & MPR_CM_FLAGS_USE_UIO) { 3517 error = bus_dmamap_load_uio(sc->buffer_dmat, cm->cm_dmamap, 3518 &cm->cm_uio, mpr_data_cb2, cm, 0); 3519 } else if (cm->cm_flags & MPR_CM_FLAGS_USE_CCB) { 3520 error = bus_dmamap_load_ccb(sc->buffer_dmat, cm->cm_dmamap, 3521 cm->cm_data, mpr_data_cb, cm, 0); 3522 } else if ((cm->cm_data != NULL) && (cm->cm_length != 0)) { 3523 error = bus_dmamap_load(sc->buffer_dmat, cm->cm_dmamap, 3524 cm->cm_data, cm->cm_length, mpr_data_cb, cm, 0); 3525 } else { 3526 /* Add a zero-length element as needed */ 3527 if (cm->cm_sge != NULL) 3528 mpr_add_dmaseg(cm, 0, 0, 0, 1); 3529 mpr_enqueue_request(sc, cm); 3530 } 3531 3532 return (error); 3533 } 3534 3535 /* 3536 * This is the routine to enqueue commands synchronously. An error of 3537 * EINPROGRESS from mpr_map_command() is ignored since the command will 3538 * be executed and enqueued automatically. Other errors come from msleep(). 3539 */ 3540 int 3541 mpr_wait_command(struct mpr_softc *sc, struct mpr_command **cmp, int timeout, 3542 int sleep_flag) 3543 { 3544 int error, rc; 3545 struct timeval cur_time, start_time; 3546 struct mpr_command *cm = *cmp; 3547 3548 if (sc->mpr_flags & MPR_FLAGS_DIAGRESET) 3549 return EBUSY; 3550 3551 cm->cm_complete = NULL; 3552 cm->cm_flags |= (MPR_CM_FLAGS_WAKEUP + MPR_CM_FLAGS_POLLED); 3553 error = mpr_map_command(sc, cm); 3554 if ((error != 0) && (error != EINPROGRESS)) 3555 return (error); 3556 3557 // Check for context and wait for 50 mSec at a time until time has 3558 // expired or the command has finished. If msleep can't be used, need 3559 // to poll. 3560 #if __FreeBSD_version >= 1000029 3561 if (curthread->td_no_sleeping) 3562 #else //__FreeBSD_version < 1000029 3563 if (curthread->td_pflags & TDP_NOSLEEPING) 3564 #endif //__FreeBSD_version >= 1000029 3565 sleep_flag = NO_SLEEP; 3566 getmicrouptime(&start_time); 3567 if (mtx_owned(&sc->mpr_mtx) && sleep_flag == CAN_SLEEP) { 3568 error = msleep(cm, &sc->mpr_mtx, 0, "mprwait", timeout*hz); 3569 if (error == EWOULDBLOCK) { 3570 /* 3571 * Record the actual elapsed time in the case of a 3572 * timeout for the message below. 3573 */ 3574 getmicrouptime(&cur_time); 3575 timevalsub(&cur_time, &start_time); 3576 } 3577 } else { 3578 while ((cm->cm_flags & MPR_CM_FLAGS_COMPLETE) == 0) { 3579 mpr_intr_locked(sc); 3580 if (sleep_flag == CAN_SLEEP) 3581 pause("mprwait", hz/20); 3582 else 3583 DELAY(50000); 3584 3585 getmicrouptime(&cur_time); 3586 timevalsub(&cur_time, &start_time); 3587 if (cur_time.tv_sec > timeout) { 3588 error = EWOULDBLOCK; 3589 break; 3590 } 3591 } 3592 } 3593 3594 if (error == EWOULDBLOCK) { 3595 mpr_dprint(sc, MPR_FAULT, "Calling Reinit from %s, timeout=%d," 3596 " elapsed=%jd\n", __func__, timeout, 3597 (intmax_t)cur_time.tv_sec); 3598 rc = mpr_reinit(sc); 3599 mpr_dprint(sc, MPR_FAULT, "Reinit %s\n", (rc == 0) ? "success" : 3600 "failed"); 3601 if (sc->mpr_flags & MPR_FLAGS_REALLOCATED) { 3602 /* 3603 * Tell the caller that we freed the command in a 3604 * reinit. 3605 */ 3606 *cmp = NULL; 3607 } 3608 error = ETIMEDOUT; 3609 } 3610 return (error); 3611 } 3612 3613 /* 3614 * This is the routine to enqueue a command synchonously and poll for 3615 * completion. Its use should be rare. 3616 */ 3617 int 3618 mpr_request_polled(struct mpr_softc *sc, struct mpr_command **cmp) 3619 { 3620 int error, rc; 3621 struct timeval cur_time, start_time; 3622 struct mpr_command *cm = *cmp; 3623 3624 error = 0; 3625 3626 cm->cm_flags |= MPR_CM_FLAGS_POLLED; 3627 cm->cm_complete = NULL; 3628 mpr_map_command(sc, cm); 3629 3630 getmicrouptime(&start_time); 3631 while ((cm->cm_flags & MPR_CM_FLAGS_COMPLETE) == 0) { 3632 mpr_intr_locked(sc); 3633 3634 if (mtx_owned(&sc->mpr_mtx)) 3635 msleep(&sc->msleep_fake_chan, &sc->mpr_mtx, 0, 3636 "mprpoll", hz/20); 3637 else 3638 pause("mprpoll", hz/20); 3639 3640 /* 3641 * Check for real-time timeout and fail if more than 60 seconds. 3642 */ 3643 getmicrouptime(&cur_time); 3644 timevalsub(&cur_time, &start_time); 3645 if (cur_time.tv_sec > 60) { 3646 mpr_dprint(sc, MPR_FAULT, "polling failed\n"); 3647 error = ETIMEDOUT; 3648 break; 3649 } 3650 } 3651 3652 if (error) { 3653 mpr_dprint(sc, MPR_FAULT, "Calling Reinit from %s\n", __func__); 3654 rc = mpr_reinit(sc); 3655 mpr_dprint(sc, MPR_FAULT, "Reinit %s\n", (rc == 0) ? "success" : 3656 "failed"); 3657 3658 if (sc->mpr_flags & MPR_FLAGS_REALLOCATED) { 3659 /* 3660 * Tell the caller that we freed the command in a 3661 * reinit. 3662 */ 3663 *cmp = NULL; 3664 } 3665 } 3666 return (error); 3667 } 3668 3669 /* 3670 * The MPT driver had a verbose interface for config pages. In this driver, 3671 * reduce it to much simpler terms, similar to the Linux driver. 3672 */ 3673 int 3674 mpr_read_config_page(struct mpr_softc *sc, struct mpr_config_params *params) 3675 { 3676 MPI2_CONFIG_REQUEST *req; 3677 struct mpr_command *cm; 3678 int error; 3679 3680 if (sc->mpr_flags & MPR_FLAGS_BUSY) { 3681 return (EBUSY); 3682 } 3683 3684 cm = mpr_alloc_command(sc); 3685 if (cm == NULL) { 3686 return (EBUSY); 3687 } 3688 3689 req = (MPI2_CONFIG_REQUEST *)cm->cm_req; 3690 req->Function = MPI2_FUNCTION_CONFIG; 3691 req->Action = params->action; 3692 req->SGLFlags = 0; 3693 req->ChainOffset = 0; 3694 req->PageAddress = params->page_address; 3695 if (params->hdr.Struct.PageType == MPI2_CONFIG_PAGETYPE_EXTENDED) { 3696 MPI2_CONFIG_EXTENDED_PAGE_HEADER *hdr; 3697 3698 hdr = ¶ms->hdr.Ext; 3699 req->ExtPageType = hdr->ExtPageType; 3700 req->ExtPageLength = hdr->ExtPageLength; 3701 req->Header.PageType = MPI2_CONFIG_PAGETYPE_EXTENDED; 3702 req->Header.PageLength = 0; /* Must be set to zero */ 3703 req->Header.PageNumber = hdr->PageNumber; 3704 req->Header.PageVersion = hdr->PageVersion; 3705 } else { 3706 MPI2_CONFIG_PAGE_HEADER *hdr; 3707 3708 hdr = ¶ms->hdr.Struct; 3709 req->Header.PageType = hdr->PageType; 3710 req->Header.PageNumber = hdr->PageNumber; 3711 req->Header.PageLength = hdr->PageLength; 3712 req->Header.PageVersion = hdr->PageVersion; 3713 } 3714 3715 cm->cm_data = params->buffer; 3716 cm->cm_length = params->length; 3717 if (cm->cm_data != NULL) { 3718 cm->cm_sge = &req->PageBufferSGE; 3719 cm->cm_sglsize = sizeof(MPI2_SGE_IO_UNION); 3720 cm->cm_flags = MPR_CM_FLAGS_SGE_SIMPLE | MPR_CM_FLAGS_DATAIN; 3721 } else 3722 cm->cm_sge = NULL; 3723 cm->cm_desc.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE; 3724 3725 cm->cm_complete_data = params; 3726 if (params->callback != NULL) { 3727 cm->cm_complete = mpr_config_complete; 3728 return (mpr_map_command(sc, cm)); 3729 } else { 3730 error = mpr_wait_command(sc, &cm, 0, CAN_SLEEP); 3731 if (error) { 3732 mpr_dprint(sc, MPR_FAULT, 3733 "Error %d reading config page\n", error); 3734 if (cm != NULL) 3735 mpr_free_command(sc, cm); 3736 return (error); 3737 } 3738 mpr_config_complete(sc, cm); 3739 } 3740 3741 return (0); 3742 } 3743 3744 int 3745 mpr_write_config_page(struct mpr_softc *sc, struct mpr_config_params *params) 3746 { 3747 return (EINVAL); 3748 } 3749 3750 static void 3751 mpr_config_complete(struct mpr_softc *sc, struct mpr_command *cm) 3752 { 3753 MPI2_CONFIG_REPLY *reply; 3754 struct mpr_config_params *params; 3755 3756 MPR_FUNCTRACE(sc); 3757 params = cm->cm_complete_data; 3758 3759 if (cm->cm_data != NULL) { 3760 bus_dmamap_sync(sc->buffer_dmat, cm->cm_dmamap, 3761 BUS_DMASYNC_POSTREAD); 3762 bus_dmamap_unload(sc->buffer_dmat, cm->cm_dmamap); 3763 } 3764 3765 /* 3766 * XXX KDM need to do more error recovery? This results in the 3767 * device in question not getting probed. 3768 */ 3769 if ((cm->cm_flags & MPR_CM_FLAGS_ERROR_MASK) != 0) { 3770 params->status = MPI2_IOCSTATUS_BUSY; 3771 goto done; 3772 } 3773 3774 reply = (MPI2_CONFIG_REPLY *)cm->cm_reply; 3775 if (reply == NULL) { 3776 params->status = MPI2_IOCSTATUS_BUSY; 3777 goto done; 3778 } 3779 params->status = reply->IOCStatus; 3780 if (params->hdr.Struct.PageType == MPI2_CONFIG_PAGETYPE_EXTENDED) { 3781 params->hdr.Ext.ExtPageType = reply->ExtPageType; 3782 params->hdr.Ext.ExtPageLength = reply->ExtPageLength; 3783 params->hdr.Ext.PageType = reply->Header.PageType; 3784 params->hdr.Ext.PageNumber = reply->Header.PageNumber; 3785 params->hdr.Ext.PageVersion = reply->Header.PageVersion; 3786 } else { 3787 params->hdr.Struct.PageType = reply->Header.PageType; 3788 params->hdr.Struct.PageNumber = reply->Header.PageNumber; 3789 params->hdr.Struct.PageLength = reply->Header.PageLength; 3790 params->hdr.Struct.PageVersion = reply->Header.PageVersion; 3791 } 3792 3793 done: 3794 mpr_free_command(sc, cm); 3795 if (params->callback != NULL) 3796 params->callback(sc, params); 3797 3798 return; 3799 } 3800