1 /*- 2 * Copyright (c) 2012-2015 LSI Corp. 3 * Copyright (c) 2013-2016 Avago Technologies 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * Copyright (c) 2000-2015 LSI Corporation. 37 * Copyright (c) 2013-2016 Avago Technologies 38 * All rights reserved. 39 * 40 * 41 * Name: mpi2_cnfg.h 42 * Title: MPI Configuration messages and pages 43 * Creation Date: November 10, 2006 44 * 45 * mpi2_cnfg.h Version: 02.00.39 46 * 47 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 48 * prefix are for use only on MPI v2.5 products, and must not be used 49 * with MPI v2.0 products. Unless otherwise noted, names beginning with 50 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 51 * 52 * Version History 53 * --------------- 54 * 55 * Date Version Description 56 * -------- -------- ------------------------------------------------------ 57 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 58 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 59 * Added Manufacturing Page 11. 60 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 61 * define. 62 * 06-26-07 02.00.02 Adding generic structure for product-specific 63 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 64 * Rework of BIOS Page 2 configuration page. 65 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 66 * forms. 67 * Added configuration pages IOC Page 8 and Driver 68 * Persistent Mapping Page 0. 69 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 70 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 71 * RAID Physical Disk Pages 0 and 1, RAID Configuration 72 * Page 0). 73 * Added new value for AccessStatus field of SAS Device 74 * Page 0 (_SATA_NEEDS_INITIALIZATION). 75 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 76 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 77 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 78 * NVDATA. 79 * Modified IOC Page 7 to use masks and added field for 80 * SASBroadcastPrimitiveMasks. 81 * Added MPI2_CONFIG_PAGE_BIOS_4. 82 * Added MPI2_CONFIG_PAGE_LOG_0. 83 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 84 * Added SAS Device IDs. 85 * Updated Integrated RAID configuration pages including 86 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 87 * Page 0. 88 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 89 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 90 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 91 * Added missing MaxNumRoutedSasAddresses field to 92 * MPI2_CONFIG_PAGE_EXPANDER_0. 93 * Added SAS Port Page 0. 94 * Modified structure layout for 95 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 96 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 97 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 98 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 99 * to 0x000000FF. 100 * Added two new values for the Physical Disk Coercion Size 101 * bits in the Flags field of Manufacturing Page 4. 102 * Added product-specific Manufacturing pages 16 to 31. 103 * Modified Flags bits for controlling write cache on SATA 104 * drives in IO Unit Page 1. 105 * Added new bit to AdditionalControlFlags of SAS IO Unit 106 * Page 1 to control Invalid Topology Correction. 107 * Added additional defines for RAID Volume Page 0 108 * VolumeStatusFlags field. 109 * Modified meaning of RAID Volume Page 0 VolumeSettings 110 * define for auto-configure of hot-swap drives. 111 * Added SupportedPhysDisks field to RAID Volume Page 1 and 112 * added related defines. 113 * Added PhysDiskAttributes field (and related defines) to 114 * RAID Physical Disk Page 0. 115 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 116 * Added three new DiscoveryStatus bits for SAS IO Unit 117 * Page 0 and SAS Expander Page 0. 118 * Removed multiplexing information from SAS IO Unit pages. 119 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 120 * Removed Zone Address Resolved bit from PhyInfo and from 121 * Expander Page 0 Flags field. 122 * Added two new AccessStatus values to SAS Device Page 0 123 * for indicating routing problems. Added 3 reserved words 124 * to this page. 125 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 126 * Inserted missing reserved field into structure for IOC 127 * Page 6. 128 * Added more pending task bits to RAID Volume Page 0 129 * VolumeStatusFlags defines. 130 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 131 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 132 * and SAS Expander Page 0 to flag a downstream initiator 133 * when in simplified routing mode. 134 * Removed SATA Init Failure defines for DiscoveryStatus 135 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 136 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 137 * Added PortGroups, DmaGroup, and ControlGroup fields to 138 * SAS Device Page 0. 139 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 140 * Unit Page 6. 141 * Added expander reduced functionality data to SAS 142 * Expander Page 0. 143 * Added SAS PHY Page 2 and SAS PHY Page 3. 144 * 07-30-09 02.00.12 Added IO Unit Page 7. 145 * Added new device ids. 146 * Added SAS IO Unit Page 5. 147 * Added partial and slumber power management capable flags 148 * to SAS Device Page 0 Flags field. 149 * Added PhyInfo defines for power condition. 150 * Added Ethernet configuration pages. 151 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 152 * Added SAS PHY Page 4 structure and defines. 153 * 02-10-10 02.00.14 Modified the comments for the configuration page 154 * structures that contain an array of data. The host 155 * should use the "count" field in the page data (e.g. the 156 * NumPhys field) to determine the number of valid elements 157 * in the array. 158 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 159 * Added PowerManagementCapabilities to IO Unit Page 7. 160 * Added PortWidthModGroup field to 161 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 162 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 163 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 164 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 165 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 166 * define. 167 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 168 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 169 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 170 * defines. 171 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 172 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 173 * the Pinout field. 174 * Added BoardTemperature and BoardTemperatureUnits fields 175 * to MPI2_CONFIG_PAGE_IO_UNIT_7. 176 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 177 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 178 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST. 179 * Added IO Unit Page 8, IO Unit Page 9, 180 * and IO Unit Page 10. 181 * Added SASNotifyPrimitiveMasks field to 182 * MPI2_CONFIG_PAGE_IOC_7. 183 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec). 184 * 05-25-11 02.00.20 Cleaned up a few comments. 185 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities 186 * for PCIe link as obsolete. 187 * Added SpinupFlags field containing a Disable Spin-up bit 188 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO 189 * Unit Page 4. 190 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT. 191 * Added UEFIVersion field to BIOS Page 1 and defined new 192 * BiosOptions bits. 193 * Incorporating additions for MPI v2.5. 194 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER. 195 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID. 196 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as 197 * obsolete for MPI v2.5 and later. 198 * Added some defines for 12G SAS speeds. 199 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK. 200 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to 201 * match the specification. 202 * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for 203 * future use. 204 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for 205 * MPI2_CONFIG_PAGE_MAN_7. 206 * Added EnclosureLevel and ConnectorName fields to 207 * MPI2_CONFIG_PAGE_SAS_DEV_0. 208 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for 209 * MPI2_CONFIG_PAGE_SAS_DEV_0. 210 * Added EnclosureLevel field to 211 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 212 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for 213 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 214 * 01-08-14 02.00.28 Added more defines for the BiosOptions field of 215 * MPI2_CONFIG_PAGE_BIOS_1. 216 * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and 217 * more defines for the BiosOptions field. 218 * 11-18-14 02.00.30 Updated copyright information. 219 * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG. 220 * Added AdapterOrderAux fields to BIOS Page 3. 221 * 03-16-15 02.00.31 Updated for MPI v2.6. 222 * Added BoardPowerRequirement, PCISlotPowerAllocation, and 223 * Flags field to IO Unit Page 7. 224 * Added IO Unit Page 11. 225 * Added new SAS Phy Event codes 226 * Added PCIe configuration pages. 227 * 03-19-15 02.00.32 Fixed PCIe Link Config page structure names to be 228 * unique in first 32 characters. 229 * 05-25-15 02.00.33 Added more defines for the BiosOptions field of 230 * MPI2_CONFIG_PAGE_BIOS_1. 231 * 08-25-15 02.00.34 Added PCIe Device Page 2 SGL format capability. 232 * 12-18-15 02.00.35 Added SATADeviceWaitTime to SAS IO Unit Page 4. 233 * 01-21-16 02.00.36 Added/modified MPI2_MFGPAGE_DEVID_SAS defines. 234 * Added Link field to PCIe Link Pages 235 * Added EnclosureLevel and ConnectorName to PCIe 236 * Device Page 0. 237 * Added define for PCIE IoUnit page 1 max rate shift. 238 * Added comment for reserved ExtPageTypes. 239 * Added SAS 4 22.5 gbs speed support. 240 * Added PCIe 4 16.0 GT/sec speec support. 241 * Removed AHCI support. 242 * Removed SOP support. 243 * Added NegotiatedLinkRate and NegotiatedPortWidth to 244 * PCIe device page 0. 245 * 04-10-16 02.00.37 Fixed MPI2_MFGPAGE_DEVID_SAS3616/3708 defines 246 * 07-01-16 02.00.38 Added Manufacturing page 7 Connector types. 247 * Changed declaration of ConnectorName in PCIe DevicePage0 248 * to match SAS DevicePage 0. 249 * Added SATADeviceWaitTime to IO Unit Page 11. 250 * Added MPI26_MFGPAGE_DEVID_SAS4008 251 * Added x16 PCIe width to IO Unit Page 7 252 * Added LINKFLAGS to control SRIS in PCIe IO Unit page 1 253 * phy data. 254 * Added InitStatus to PCIe IO Unit Page 1 header. 255 * 09-01-16 02.00.39 Added MPI26_CONFIG_PAGE_ENCLOSURE_0 and related defines. 256 * Added MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE and 257 * MPI26_ENCLOS_PGAD_FORM_HANDLE page address formats. 258 * -------------------------------------------------------------------------- 259 */ 260 261 #ifndef MPI2_CNFG_H 262 #define MPI2_CNFG_H 263 264 /***************************************************************************** 265 * Configuration Page Header and defines 266 *****************************************************************************/ 267 268 /* Config Page Header */ 269 typedef struct _MPI2_CONFIG_PAGE_HEADER 270 { 271 U8 PageVersion; /* 0x00 */ 272 U8 PageLength; /* 0x01 */ 273 U8 PageNumber; /* 0x02 */ 274 U8 PageType; /* 0x03 */ 275 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER, 276 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t; 277 278 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION 279 { 280 MPI2_CONFIG_PAGE_HEADER Struct; 281 U8 Bytes[4]; 282 U16 Word16[2]; 283 U32 Word32; 284 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 285 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion; 286 287 /* Extended Config Page Header */ 288 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER 289 { 290 U8 PageVersion; /* 0x00 */ 291 U8 Reserved1; /* 0x01 */ 292 U8 PageNumber; /* 0x02 */ 293 U8 PageType; /* 0x03 */ 294 U16 ExtPageLength; /* 0x04 */ 295 U8 ExtPageType; /* 0x06 */ 296 U8 Reserved2; /* 0x07 */ 297 } MPI2_CONFIG_EXTENDED_PAGE_HEADER, 298 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 299 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t; 300 301 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION 302 { 303 MPI2_CONFIG_PAGE_HEADER Struct; 304 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 305 U8 Bytes[8]; 306 U16 Word16[4]; 307 U32 Word32[2]; 308 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 309 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion; 310 311 312 /* PageType field values */ 313 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 314 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 315 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 316 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 317 318 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 319 #define MPI2_CONFIG_PAGETYPE_IOC (0x01) 320 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 321 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 322 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 323 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 324 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 325 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 326 327 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 328 329 330 /* ExtPageType field values */ 331 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 332 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 333 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 334 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 335 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 336 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 337 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 338 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 339 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 340 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 341 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 342 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_IO_UNIT (0x1B) /* MPI v2.6 and later */ 343 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_SWITCH (0x1C) /* MPI v2.6 and later */ 344 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_DEVICE (0x1D) /* MPI v2.6 and later */ 345 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_LINK (0x1E) /* MPI v2.6 and later */ 346 /* Product specific reserved values 0xE0 - 0xEF */ 347 /* Vendor specific reserved values 0xF0 - 0xFF */ 348 349 350 /***************************************************************************** 351 * PageAddress defines 352 *****************************************************************************/ 353 354 /* RAID Volume PageAddress format */ 355 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 356 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 357 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 358 359 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 360 361 362 /* RAID Physical Disk PageAddress format */ 363 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 364 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 365 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 366 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 367 368 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 369 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 370 371 372 /* SAS Expander PageAddress format */ 373 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 374 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 375 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 376 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 377 378 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 379 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 380 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 381 382 383 /* SAS Device PageAddress format */ 384 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 385 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 386 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 387 388 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 389 390 391 /* SAS PHY PageAddress format */ 392 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 393 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 394 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 395 396 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 397 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 398 399 400 /* SAS Port PageAddress format */ 401 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 402 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 403 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 404 405 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 406 407 408 /* SAS Enclosure PageAddress format */ 409 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 410 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 411 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 412 413 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 414 415 /* Enclosure PageAddress format */ 416 #define MPI26_ENCLOS_PGAD_FORM_MASK (0xF0000000) 417 #define MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 418 #define MPI26_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 419 420 #define MPI26_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 421 422 /* RAID Configuration PageAddress format */ 423 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 424 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 425 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 426 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 427 428 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 429 430 431 /* Driver Persistent Mapping PageAddress format */ 432 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 433 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 434 435 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 436 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 437 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 438 439 440 /* Ethernet PageAddress format */ 441 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 442 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 443 444 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 445 446 447 /* PCIe Switch PageAddress format */ 448 #define MPI26_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000) 449 #define MPI26_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 450 #define MPI26_PCIE_SWITCH_PGAD_FORM_HNDL_PORTNUM (0x10000000) 451 #define MPI26_PCIE_SWITCH_EXPAND_PGAD_FORM_HNDL (0x20000000) 452 453 #define MPI26_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF) 454 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000) 455 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) 456 457 458 /* PCIe Device PageAddress format */ 459 #define MPI26_PCIE_DEVICE_PGAD_FORM_MASK (0xF0000000) 460 #define MPI26_PCIE_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 461 #define MPI26_PCIE_DEVICE_PGAD_FORM_HANDLE (0x20000000) 462 463 #define MPI26_PCIE_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 464 465 /* PCIe Link PageAddress format */ 466 #define MPI26_PCIE_LINK_PGAD_FORM_MASK (0xF0000000) 467 #define MPI26_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) 468 #define MPI26_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) 469 470 #define MPI26_PCIE_DEVICE_PGAD_LINKNUM_MASK (0x000000FF) 471 472 473 474 /**************************************************************************** 475 * Configuration messages 476 ****************************************************************************/ 477 478 /* Configuration Request Message */ 479 typedef struct _MPI2_CONFIG_REQUEST 480 { 481 U8 Action; /* 0x00 */ 482 U8 SGLFlags; /* 0x01 */ 483 U8 ChainOffset; /* 0x02 */ 484 U8 Function; /* 0x03 */ 485 U16 ExtPageLength; /* 0x04 */ 486 U8 ExtPageType; /* 0x06 */ 487 U8 MsgFlags; /* 0x07 */ 488 U8 VP_ID; /* 0x08 */ 489 U8 VF_ID; /* 0x09 */ 490 U16 Reserved1; /* 0x0A */ 491 U8 Reserved2; /* 0x0C */ 492 U8 ProxyVF_ID; /* 0x0D */ 493 U16 Reserved4; /* 0x0E */ 494 U32 Reserved3; /* 0x10 */ 495 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 496 U32 PageAddress; /* 0x18 */ 497 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */ 498 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST, 499 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t; 500 501 /* values for the Action field */ 502 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 503 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 504 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 505 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 506 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 507 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 508 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 509 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 510 511 /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 512 513 514 /* Config Reply Message */ 515 typedef struct _MPI2_CONFIG_REPLY 516 { 517 U8 Action; /* 0x00 */ 518 U8 SGLFlags; /* 0x01 */ 519 U8 MsgLength; /* 0x02 */ 520 U8 Function; /* 0x03 */ 521 U16 ExtPageLength; /* 0x04 */ 522 U8 ExtPageType; /* 0x06 */ 523 U8 MsgFlags; /* 0x07 */ 524 U8 VP_ID; /* 0x08 */ 525 U8 VF_ID; /* 0x09 */ 526 U16 Reserved1; /* 0x0A */ 527 U16 Reserved2; /* 0x0C */ 528 U16 IOCStatus; /* 0x0E */ 529 U32 IOCLogInfo; /* 0x10 */ 530 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 531 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY, 532 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t; 533 534 535 536 /***************************************************************************** 537 * 538 * C o n f i g u r a t i o n P a g e s 539 * 540 *****************************************************************************/ 541 542 /**************************************************************************** 543 * Manufacturing Config pages 544 ****************************************************************************/ 545 546 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 547 548 /* MPI v2.0 SAS products */ 549 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 550 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 551 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 552 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 553 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 554 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 555 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 556 557 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 558 559 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 560 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 561 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 562 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 563 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 564 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 565 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 566 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 567 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 568 569 /* MPI v2.5 SAS products */ 570 #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096) 571 #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097) 572 #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090) 573 #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091) 574 #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094) 575 #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095) 576 577 /* MPI v2.6 SAS Products */ 578 #define MPI26_MFGPAGE_DEVID_SAS3216 (0x00C9) 579 #define MPI26_MFGPAGE_DEVID_SAS3224 (0x00C4) 580 #define MPI26_MFGPAGE_DEVID_SAS3316_1 (0x00C5) 581 #define MPI26_MFGPAGE_DEVID_SAS3316_2 (0x00C6) 582 #define MPI26_MFGPAGE_DEVID_SAS3316_3 (0x00C7) 583 #define MPI26_MFGPAGE_DEVID_SAS3316_4 (0x00C8) 584 #define MPI26_MFGPAGE_DEVID_SAS3324_1 (0x00C0) 585 #define MPI26_MFGPAGE_DEVID_SAS3324_2 (0x00C1) 586 #define MPI26_MFGPAGE_DEVID_SAS3324_3 (0x00C2) 587 #define MPI26_MFGPAGE_DEVID_SAS3324_4 (0x00C3) 588 589 #define MPI26_MFGPAGE_DEVID_SAS3516 (0x00AA) 590 #define MPI26_MFGPAGE_DEVID_SAS3516_1 (0x00AB) 591 #define MPI26_MFGPAGE_DEVID_SAS3416 (0x00AC) 592 #define MPI26_MFGPAGE_DEVID_SAS3508 (0x00AD) 593 #define MPI26_MFGPAGE_DEVID_SAS3508_1 (0x00AE) 594 #define MPI26_MFGPAGE_DEVID_SAS3408 (0x00AF) 595 596 #define MPI26_MFGPAGE_DEVID_SAS3716 (0x00D0) 597 #define MPI26_MFGPAGE_DEVID_SAS3616 (0x00D1) 598 #define MPI26_MFGPAGE_DEVID_SAS3708 (0x00D2) 599 600 #define MPI26_MFGPAGE_DEVID_SAS4008 (0x00A1) 601 602 603 /* Manufacturing Page 0 */ 604 605 typedef struct _MPI2_CONFIG_PAGE_MAN_0 606 { 607 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 608 U8 ChipName[16]; /* 0x04 */ 609 U8 ChipRevision[8]; /* 0x14 */ 610 U8 BoardName[16]; /* 0x1C */ 611 U8 BoardAssembly[16]; /* 0x2C */ 612 U8 BoardTracerNumber[16]; /* 0x3C */ 613 } MPI2_CONFIG_PAGE_MAN_0, 614 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0, 615 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t; 616 617 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 618 619 620 /* Manufacturing Page 1 */ 621 622 typedef struct _MPI2_CONFIG_PAGE_MAN_1 623 { 624 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 625 U8 VPD[256]; /* 0x04 */ 626 } MPI2_CONFIG_PAGE_MAN_1, 627 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1, 628 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t; 629 630 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 631 632 633 typedef struct _MPI2_CHIP_REVISION_ID 634 { 635 U16 DeviceID; /* 0x00 */ 636 U8 PCIRevisionID; /* 0x02 */ 637 U8 Reserved; /* 0x03 */ 638 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID, 639 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t; 640 641 642 /* Manufacturing Page 2 */ 643 644 /* 645 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 646 * one and check Header.PageLength at runtime. 647 */ 648 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 649 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 650 #endif 651 652 typedef struct _MPI2_CONFIG_PAGE_MAN_2 653 { 654 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 655 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 656 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */ 657 } MPI2_CONFIG_PAGE_MAN_2, 658 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2, 659 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t; 660 661 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 662 663 664 /* Manufacturing Page 3 */ 665 666 /* 667 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 668 * one and check Header.PageLength at runtime. 669 */ 670 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS 671 #define MPI2_MAN_PAGE_3_INFO_WORDS (1) 672 #endif 673 674 typedef struct _MPI2_CONFIG_PAGE_MAN_3 675 { 676 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 677 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 678 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */ 679 } MPI2_CONFIG_PAGE_MAN_3, 680 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3, 681 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t; 682 683 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 684 685 686 /* Manufacturing Page 4 */ 687 688 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS 689 { 690 U8 PowerSaveFlags; /* 0x00 */ 691 U8 InternalOperationsSleepTime; /* 0x01 */ 692 U8 InternalOperationsRunTime; /* 0x02 */ 693 U8 HostIdleTime; /* 0x03 */ 694 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 695 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 696 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t; 697 698 /* defines for the PowerSaveFlags field */ 699 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 700 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 701 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 702 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 703 704 typedef struct _MPI2_CONFIG_PAGE_MAN_4 705 { 706 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 707 U32 Reserved1; /* 0x04 */ 708 U32 Flags; /* 0x08 */ 709 U8 InquirySize; /* 0x0C */ 710 U8 Reserved2; /* 0x0D */ 711 U16 Reserved3; /* 0x0E */ 712 U8 InquiryData[56]; /* 0x10 */ 713 U32 RAID0VolumeSettings; /* 0x48 */ 714 U32 RAID1EVolumeSettings; /* 0x4C */ 715 U32 RAID1VolumeSettings; /* 0x50 */ 716 U32 RAID10VolumeSettings; /* 0x54 */ 717 U32 Reserved4; /* 0x58 */ 718 U32 Reserved5; /* 0x5C */ 719 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */ 720 U8 MaxOCEDisks; /* 0x64 */ 721 U8 ResyncRate; /* 0x65 */ 722 U16 DataScrubDuration; /* 0x66 */ 723 U8 MaxHotSpares; /* 0x68 */ 724 U8 MaxPhysDisksPerVol; /* 0x69 */ 725 U8 MaxPhysDisks; /* 0x6A */ 726 U8 MaxVolumes; /* 0x6B */ 727 } MPI2_CONFIG_PAGE_MAN_4, 728 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4, 729 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t; 730 731 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 732 733 /* Manufacturing Page 4 Flags field */ 734 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 735 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 736 737 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 738 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 739 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 740 741 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 742 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 743 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 744 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 745 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 746 747 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 748 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 749 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 750 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 751 752 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 753 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 754 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 755 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 756 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 757 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 758 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 759 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 760 761 762 /* Manufacturing Page 5 */ 763 764 /* 765 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 766 * one and check the value returned for NumPhys at runtime. 767 */ 768 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 769 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 770 #endif 771 772 typedef struct _MPI2_MANUFACTURING5_ENTRY 773 { 774 U64 WWID; /* 0x00 */ 775 U64 DeviceName; /* 0x08 */ 776 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY, 777 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t; 778 779 typedef struct _MPI2_CONFIG_PAGE_MAN_5 780 { 781 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 782 U8 NumPhys; /* 0x04 */ 783 U8 Reserved1; /* 0x05 */ 784 U16 Reserved2; /* 0x06 */ 785 U32 Reserved3; /* 0x08 */ 786 U32 Reserved4; /* 0x0C */ 787 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */ 788 } MPI2_CONFIG_PAGE_MAN_5, 789 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5, 790 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t; 791 792 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 793 794 795 /* Manufacturing Page 6 */ 796 797 typedef struct _MPI2_CONFIG_PAGE_MAN_6 798 { 799 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 800 U32 ProductSpecificInfo;/* 0x04 */ 801 } MPI2_CONFIG_PAGE_MAN_6, 802 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6, 803 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t; 804 805 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 806 807 808 /* Manufacturing Page 7 */ 809 810 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO 811 { 812 U32 Pinout; /* 0x00 */ 813 U8 Connector[16]; /* 0x04 */ 814 U8 Location; /* 0x14 */ 815 U8 ReceptacleID; /* 0x15 */ 816 U16 Slot; /* 0x16 */ 817 U32 Reserved2; /* 0x18 */ 818 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 819 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t; 820 821 /* defines for the Pinout field */ 822 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 823 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 824 825 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 826 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 827 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 828 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 829 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 830 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 831 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 832 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 833 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 834 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 835 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 836 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 837 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 838 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 839 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 840 #define MPI2_MANPAGE7_PINOUT_SFF_8088_A (0x0E) 841 #define MPI2_MANPAGE7_PINOUT_SFF_8643_16i (0x0F) 842 #define MPI2_MANPAGE7_PINOUT_SFF_8654_4i (0x10) 843 #define MPI2_MANPAGE7_PINOUT_SFF_8654_8i (0x11) 844 #define MPI2_MANPAGE7_PINOUT_SFF_8611_4i (0x12) 845 #define MPI2_MANPAGE7_PINOUT_SFF_8611_8i (0x13) 846 847 /* defines for the Location field */ 848 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 849 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 850 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 851 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 852 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 853 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 854 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 855 856 /* 857 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 858 * one and check the value returned for NumPhys at runtime. 859 */ 860 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 861 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 862 #endif 863 864 typedef struct _MPI2_CONFIG_PAGE_MAN_7 865 { 866 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 867 U32 Reserved1; /* 0x04 */ 868 U32 Reserved2; /* 0x08 */ 869 U32 Flags; /* 0x0C */ 870 U8 EnclosureName[16]; /* 0x10 */ 871 U8 NumPhys; /* 0x20 */ 872 U8 Reserved3; /* 0x21 */ 873 U16 Reserved4; /* 0x22 */ 874 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */ 875 } MPI2_CONFIG_PAGE_MAN_7, 876 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7, 877 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t; 878 879 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 880 881 /* defines for the Flags field */ 882 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008) 883 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002) 884 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 885 886 887 /* 888 * Generic structure to use for product-specific manufacturing pages 889 * (currently Manufacturing Page 8 through Manufacturing Page 31). 890 */ 891 892 typedef struct _MPI2_CONFIG_PAGE_MAN_PS 893 { 894 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 895 U32 ProductSpecificInfo;/* 0x04 */ 896 } MPI2_CONFIG_PAGE_MAN_PS, 897 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS, 898 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t; 899 900 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 901 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 902 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 903 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 904 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 905 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 906 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 907 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 908 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 909 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 910 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 911 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 912 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 913 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 914 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 915 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 916 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 917 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 918 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 919 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 920 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 921 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 922 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 923 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 924 925 926 /**************************************************************************** 927 * IO Unit Config Pages 928 ****************************************************************************/ 929 930 /* IO Unit Page 0 */ 931 932 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 933 { 934 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 935 U64 UniqueValue; /* 0x04 */ 936 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */ 937 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */ 938 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 939 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t; 940 941 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 942 943 944 /* IO Unit Page 1 */ 945 946 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 947 { 948 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 949 U32 Flags; /* 0x04 */ 950 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 951 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t; 952 953 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 954 955 /* IO Unit Page 1 Flags defines */ 956 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000) 957 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000) 958 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000) 959 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 960 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 961 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 962 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 963 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 964 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 965 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 966 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 967 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 968 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 969 970 971 /* IO Unit Page 3 */ 972 973 /* 974 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 975 * one and check the value returned for GPIOCount at runtime. 976 */ 977 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 978 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 979 #endif 980 981 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 982 { 983 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 984 U8 GPIOCount; /* 0x04 */ 985 U8 Reserved1; /* 0x05 */ 986 U16 Reserved2; /* 0x06 */ 987 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */ 988 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 989 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t; 990 991 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 992 993 /* defines for IO Unit Page 3 GPIOVal field */ 994 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 995 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 996 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 997 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 998 999 1000 /* IO Unit Page 5 */ 1001 1002 /* 1003 * Upper layer code (drivers, utilities, etc.) should leave this define set to 1004 * one and check the value returned for NumDmaEngines at runtime. 1005 */ 1006 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 1007 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 1008 #endif 1009 1010 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 1011 { 1012 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1013 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */ 1014 U64 RaidAcceleratorBufferSize; /* 0x0C */ 1015 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */ 1016 U8 RAControlSize; /* 0x1C */ 1017 U8 NumDmaEngines; /* 0x1D */ 1018 U8 RAMinControlSize; /* 0x1E */ 1019 U8 RAMaxControlSize; /* 0x1F */ 1020 U32 Reserved1; /* 0x20 */ 1021 U32 Reserved2; /* 0x24 */ 1022 U32 Reserved3; /* 0x28 */ 1023 U32 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */ 1024 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 1025 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t; 1026 1027 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 1028 1029 /* defines for IO Unit Page 5 DmaEngineCapabilities field */ 1030 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000) 1031 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 1032 1033 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 1034 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 1035 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 1036 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 1037 1038 1039 /* IO Unit Page 6 */ 1040 1041 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 1042 { 1043 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1044 U16 Flags; /* 0x04 */ 1045 U8 RAHostControlSize; /* 0x06 */ 1046 U8 Reserved0; /* 0x07 */ 1047 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */ 1048 U32 Reserved1; /* 0x10 */ 1049 U32 Reserved2; /* 0x14 */ 1050 U32 Reserved3; /* 0x18 */ 1051 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 1052 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t; 1053 1054 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 1055 1056 /* defines for IO Unit Page 6 Flags field */ 1057 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 1058 1059 1060 /* IO Unit Page 7 */ 1061 1062 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 1063 { 1064 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1065 U8 CurrentPowerMode; /* 0x04 */ /* reserved in MPI 2.0 */ 1066 U8 PreviousPowerMode; /* 0x05 */ /* reserved in MPI 2.0 */ 1067 U8 PCIeWidth; /* 0x06 */ 1068 U8 PCIeSpeed; /* 0x07 */ 1069 U32 ProcessorState; /* 0x08 */ 1070 U32 PowerManagementCapabilities; /* 0x0C */ 1071 U16 IOCTemperature; /* 0x10 */ 1072 U8 IOCTemperatureUnits; /* 0x12 */ 1073 U8 IOCSpeed; /* 0x13 */ 1074 U16 BoardTemperature; /* 0x14 */ 1075 U8 BoardTemperatureUnits; /* 0x16 */ 1076 U8 Reserved3; /* 0x17 */ 1077 U32 BoardPowerRequirement; /* 0x18 */ /* reserved prior to MPI v2.6 */ 1078 U32 PCISlotPowerAllocation; /* 0x1C */ /* reserved prior to MPI v2.6 */ 1079 U8 Flags; /* 0x20 */ /* reserved prior to MPI v2.6 */ 1080 U8 Reserved6; /* 0x21 */ 1081 U16 Reserved7; /* 0x22 */ 1082 U32 Reserved8; /* 0x24 */ 1083 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 1084 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t; 1085 1086 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x05) 1087 1088 /* defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */ 1089 #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0) 1090 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00) 1091 #define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40) 1092 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80) 1093 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0) 1094 1095 #define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07) 1096 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00) 1097 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01) 1098 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04) 1099 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05) 1100 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06) 1101 1102 1103 /* defines for IO Unit Page 7 PCIeWidth field */ 1104 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 1105 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 1106 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 1107 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 1108 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X16 (0x10) 1109 1110 /* defines for IO Unit Page 7 PCIeSpeed field */ 1111 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 1112 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 1113 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 1114 #define MPI2_IOUNITPAGE7_PCIE_SPEED_16_0_GBPS (0x03) 1115 1116 /* defines for IO Unit Page 7 ProcessorState field */ 1117 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 1118 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 1119 1120 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 1121 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 1122 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 1123 1124 /* defines for IO Unit Page 7 PowerManagementCapabilities field */ 1125 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000) 1126 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000) 1127 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000) 1128 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000) 1129 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000) 1130 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000) 1131 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000) 1132 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000) 1133 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000) 1134 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400) 1135 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200) 1136 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100) 1137 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040) 1138 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020) 1139 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010) 1140 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008) /* obsolete */ 1141 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004) /* obsolete */ 1142 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002) /* obsolete */ 1143 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001) /* obsolete */ 1144 1145 /* obsolete names for the PowerManagementCapabilities bits (above) */ 1146 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 1147 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 1148 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 1149 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /* obsolete */ 1150 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /* obsolete */ 1151 1152 1153 /* defines for IO Unit Page 7 IOCTemperatureUnits field */ 1154 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 1155 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 1156 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 1157 1158 /* defines for IO Unit Page 7 IOCSpeed field */ 1159 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 1160 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 1161 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 1162 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 1163 1164 /* defines for IO Unit Page 7 BoardTemperatureUnits field */ 1165 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 1166 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 1167 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 1168 1169 /* defines for IO Unit Page 7 Flags field */ 1170 #define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC (0x01) 1171 1172 1173 /* IO Unit Page 8 */ 1174 1175 #define MPI2_IOUNIT8_NUM_THRESHOLDS (4) 1176 1177 typedef struct _MPI2_IOUNIT8_SENSOR 1178 { 1179 U16 Flags; /* 0x00 */ 1180 U16 Reserved1; /* 0x02 */ 1181 U16 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */ 1182 U32 Reserved2; /* 0x0C */ 1183 U32 Reserved3; /* 0x10 */ 1184 U32 Reserved4; /* 0x14 */ 1185 } MPI2_IOUNIT8_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT8_SENSOR, 1186 Mpi2IOUnit8Sensor_t, MPI2_POINTER pMpi2IOUnit8Sensor_t; 1187 1188 /* defines for IO Unit Page 8 Sensor Flags field */ 1189 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008) 1190 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004) 1191 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002) 1192 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001) 1193 1194 /* 1195 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1196 * one and check the value returned for NumSensors at runtime. 1197 */ 1198 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES 1199 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1) 1200 #endif 1201 1202 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 1203 { 1204 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1205 U32 Reserved1; /* 0x04 */ 1206 U32 Reserved2; /* 0x08 */ 1207 U8 NumSensors; /* 0x0C */ 1208 U8 PollingInterval; /* 0x0D */ 1209 U16 Reserved3; /* 0x0E */ 1210 MPI2_IOUNIT8_SENSOR Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */ 1211 } MPI2_CONFIG_PAGE_IO_UNIT_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_8, 1212 Mpi2IOUnitPage8_t, MPI2_POINTER pMpi2IOUnitPage8_t; 1213 1214 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00) 1215 1216 1217 /* IO Unit Page 9 */ 1218 1219 typedef struct _MPI2_IOUNIT9_SENSOR 1220 { 1221 U16 CurrentTemperature; /* 0x00 */ 1222 U16 Reserved1; /* 0x02 */ 1223 U8 Flags; /* 0x04 */ 1224 U8 Reserved2; /* 0x05 */ 1225 U16 Reserved3; /* 0x06 */ 1226 U32 Reserved4; /* 0x08 */ 1227 U32 Reserved5; /* 0x0C */ 1228 } MPI2_IOUNIT9_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT9_SENSOR, 1229 Mpi2IOUnit9Sensor_t, MPI2_POINTER pMpi2IOUnit9Sensor_t; 1230 1231 /* defines for IO Unit Page 9 Sensor Flags field */ 1232 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01) 1233 1234 /* 1235 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1236 * one and check the value returned for NumSensors at runtime. 1237 */ 1238 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES 1239 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1) 1240 #endif 1241 1242 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 1243 { 1244 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1245 U32 Reserved1; /* 0x04 */ 1246 U32 Reserved2; /* 0x08 */ 1247 U8 NumSensors; /* 0x0C */ 1248 U8 Reserved4; /* 0x0D */ 1249 U16 Reserved3; /* 0x0E */ 1250 MPI2_IOUNIT9_SENSOR Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */ 1251 } MPI2_CONFIG_PAGE_IO_UNIT_9, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_9, 1252 Mpi2IOUnitPage9_t, MPI2_POINTER pMpi2IOUnitPage9_t; 1253 1254 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00) 1255 1256 1257 /* IO Unit Page 10 */ 1258 1259 typedef struct _MPI2_IOUNIT10_FUNCTION 1260 { 1261 U8 CreditPercent; /* 0x00 */ 1262 U8 Reserved1; /* 0x01 */ 1263 U16 Reserved2; /* 0x02 */ 1264 } MPI2_IOUNIT10_FUNCTION, MPI2_POINTER PTR_MPI2_IOUNIT10_FUNCTION, 1265 Mpi2IOUnit10Function_t, MPI2_POINTER pMpi2IOUnit10Function_t; 1266 1267 /* 1268 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1269 * one and check the value returned for NumFunctions at runtime. 1270 */ 1271 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES 1272 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1) 1273 #endif 1274 1275 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 1276 { 1277 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1278 U8 NumFunctions; /* 0x04 */ 1279 U8 Reserved1; /* 0x05 */ 1280 U16 Reserved2; /* 0x06 */ 1281 U32 Reserved3; /* 0x08 */ 1282 U32 Reserved4; /* 0x0C */ 1283 MPI2_IOUNIT10_FUNCTION Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES]; /* 0x10 */ 1284 } MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10, 1285 Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t; 1286 1287 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01) 1288 1289 1290 /* IO Unit Page 11 (for MPI v2.6 and later) */ 1291 1292 typedef struct _MPI26_IOUNIT11_SPINUP_GROUP 1293 { 1294 U8 MaxTargetSpinup; /* 0x00 */ 1295 U8 SpinupDelay; /* 0x01 */ 1296 U8 SpinupFlags; /* 0x02 */ 1297 U8 Reserved1; /* 0x03 */ 1298 } MPI26_IOUNIT11_SPINUP_GROUP, MPI2_POINTER PTR_MPI26_IOUNIT11_SPINUP_GROUP, 1299 Mpi26IOUnit11SpinupGroup_t, MPI2_POINTER pMpi26IOUnit11SpinupGroup_t; 1300 1301 /* defines for IO Unit Page 11 SpinupFlags */ 1302 #define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG (0x01) 1303 1304 1305 /* 1306 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1307 * four and check the value returned for NumPhys at runtime. 1308 */ 1309 #ifndef MPI26_IOUNITPAGE11_PHY_MAX 1310 #define MPI26_IOUNITPAGE11_PHY_MAX (4) 1311 #endif 1312 1313 typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 1314 { 1315 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1316 U32 Reserved1; /* 0x04 */ 1317 MPI26_IOUNIT11_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 1318 U32 Reserved2; /* 0x18 */ 1319 U32 Reserved3; /* 0x1C */ 1320 U32 Reserved4; /* 0x20 */ 1321 U8 BootDeviceWaitTime; /* 0x24 */ 1322 U8 SATADeviceWaitTime; /* 0x25 */ 1323 U16 Reserved6; /* 0x26 */ 1324 U8 NumPhys; /* 0x28 */ 1325 U8 PEInitialSpinupDelay; /* 0x29 */ 1326 U8 PEReplyDelay; /* 0x2A */ 1327 U8 Flags; /* 0x2B */ 1328 U8 PHY[MPI26_IOUNITPAGE11_PHY_MAX];/* 0x2C */ 1329 } MPI26_CONFIG_PAGE_IO_UNIT_11, 1330 MPI2_POINTER PTR_MPI26_CONFIG_PAGE_IO_UNIT_11, 1331 Mpi26IOUnitPage11_t, MPI2_POINTER pMpi26IOUnitPage11_t; 1332 1333 #define MPI26_IOUNITPAGE11_PAGEVERSION (0x00) 1334 1335 /* defines for Flags field */ 1336 #define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE (0x01) 1337 1338 /* defines for PHY field */ 1339 #define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK (0x03) 1340 1341 1342 1343 /**************************************************************************** 1344 * IOC Config Pages 1345 ****************************************************************************/ 1346 1347 /* IOC Page 0 */ 1348 1349 typedef struct _MPI2_CONFIG_PAGE_IOC_0 1350 { 1351 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1352 U32 Reserved1; /* 0x04 */ 1353 U32 Reserved2; /* 0x08 */ 1354 U16 VendorID; /* 0x0C */ 1355 U16 DeviceID; /* 0x0E */ 1356 U8 RevisionID; /* 0x10 */ 1357 U8 Reserved3; /* 0x11 */ 1358 U16 Reserved4; /* 0x12 */ 1359 U32 ClassCode; /* 0x14 */ 1360 U16 SubsystemVendorID; /* 0x18 */ 1361 U16 SubsystemID; /* 0x1A */ 1362 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0, 1363 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t; 1364 1365 #define MPI2_IOCPAGE0_PAGEVERSION (0x02) 1366 1367 1368 /* IOC Page 1 */ 1369 1370 typedef struct _MPI2_CONFIG_PAGE_IOC_1 1371 { 1372 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1373 U32 Flags; /* 0x04 */ 1374 U32 CoalescingTimeout; /* 0x08 */ 1375 U8 CoalescingDepth; /* 0x0C */ 1376 U8 PCISlotNum; /* 0x0D */ 1377 U8 PCIBusNum; /* 0x0E */ 1378 U8 PCIDomainSegment; /* 0x0F */ 1379 U32 Reserved1; /* 0x10 */ 1380 U32 Reserved2; /* 0x14 */ 1381 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1, 1382 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t; 1383 1384 #define MPI2_IOCPAGE1_PAGEVERSION (0x05) 1385 1386 /* defines for IOC Page 1 Flags field */ 1387 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 1388 1389 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1390 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 1391 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 1392 1393 /* IOC Page 6 */ 1394 1395 typedef struct _MPI2_CONFIG_PAGE_IOC_6 1396 { 1397 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1398 U32 CapabilitiesFlags; /* 0x04 */ 1399 U8 MaxDrivesRAID0; /* 0x08 */ 1400 U8 MaxDrivesRAID1; /* 0x09 */ 1401 U8 MaxDrivesRAID1E; /* 0x0A */ 1402 U8 MaxDrivesRAID10; /* 0x0B */ 1403 U8 MinDrivesRAID0; /* 0x0C */ 1404 U8 MinDrivesRAID1; /* 0x0D */ 1405 U8 MinDrivesRAID1E; /* 0x0E */ 1406 U8 MinDrivesRAID10; /* 0x0F */ 1407 U32 Reserved1; /* 0x10 */ 1408 U8 MaxGlobalHotSpares; /* 0x14 */ 1409 U8 MaxPhysDisks; /* 0x15 */ 1410 U8 MaxVolumes; /* 0x16 */ 1411 U8 MaxConfigs; /* 0x17 */ 1412 U8 MaxOCEDisks; /* 0x18 */ 1413 U8 Reserved2; /* 0x19 */ 1414 U16 Reserved3; /* 0x1A */ 1415 U32 SupportedStripeSizeMapRAID0; /* 0x1C */ 1416 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */ 1417 U32 SupportedStripeSizeMapRAID10; /* 0x24 */ 1418 U32 Reserved4; /* 0x28 */ 1419 U32 Reserved5; /* 0x2C */ 1420 U16 DefaultMetadataSize; /* 0x30 */ 1421 U16 Reserved6; /* 0x32 */ 1422 U16 MaxBadBlockTableEntries; /* 0x34 */ 1423 U16 Reserved7; /* 0x36 */ 1424 U32 IRNvsramVersion; /* 0x38 */ 1425 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6, 1426 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t; 1427 1428 #define MPI2_IOCPAGE6_PAGEVERSION (0x05) 1429 1430 /* defines for IOC Page 6 CapabilitiesFlags */ 1431 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020) 1432 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1433 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1434 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1435 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1436 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1437 1438 1439 /* IOC Page 7 */ 1440 1441 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1442 1443 typedef struct _MPI2_CONFIG_PAGE_IOC_7 1444 { 1445 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1446 U32 Reserved1; /* 0x04 */ 1447 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */ 1448 U16 SASBroadcastPrimitiveMasks; /* 0x18 */ 1449 U16 SASNotifyPrimitiveMasks; /* 0x1A */ 1450 U32 Reserved3; /* 0x1C */ 1451 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7, 1452 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t; 1453 1454 #define MPI2_IOCPAGE7_PAGEVERSION (0x02) 1455 1456 1457 /* IOC Page 8 */ 1458 1459 typedef struct _MPI2_CONFIG_PAGE_IOC_8 1460 { 1461 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1462 U8 NumDevsPerEnclosure; /* 0x04 */ 1463 U8 Reserved1; /* 0x05 */ 1464 U16 Reserved2; /* 0x06 */ 1465 U16 MaxPersistentEntries; /* 0x08 */ 1466 U16 MaxNumPhysicalMappedIDs; /* 0x0A */ 1467 U16 Flags; /* 0x0C */ 1468 U16 Reserved3; /* 0x0E */ 1469 U16 IRVolumeMappingFlags; /* 0x10 */ 1470 U16 Reserved4; /* 0x12 */ 1471 U32 Reserved5; /* 0x14 */ 1472 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8, 1473 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t; 1474 1475 #define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1476 1477 /* defines for IOC Page 8 Flags field */ 1478 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1479 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1480 1481 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1482 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1483 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1484 1485 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1486 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1487 1488 /* defines for IOC Page 8 IRVolumeMappingFlags */ 1489 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1490 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1491 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1492 1493 1494 /**************************************************************************** 1495 * BIOS Config Pages 1496 ****************************************************************************/ 1497 1498 /* BIOS Page 1 */ 1499 1500 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 1501 { 1502 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1503 U32 BiosOptions; /* 0x04 */ 1504 U32 IOCSettings; /* 0x08 */ 1505 U8 SSUTimeout; /* 0x0C */ 1506 U8 Reserved1; /* 0x0D */ 1507 U16 Reserved2; /* 0x0E */ 1508 U32 DeviceSettings; /* 0x10 */ 1509 U16 NumberOfDevices; /* 0x14 */ 1510 U16 UEFIVersion; /* 0x16 */ 1511 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */ 1512 U16 IOTimeoutSequential; /* 0x1A */ 1513 U16 IOTimeoutOther; /* 0x1C */ 1514 U16 IOTimeoutBlockDevicesRM; /* 0x1E */ 1515 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1, 1516 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t; 1517 1518 #define MPI2_BIOSPAGE1_PAGEVERSION (0x07) 1519 1520 /* values for BIOS Page 1 BiosOptions field */ 1521 #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE (0x00008000) 1522 #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000) 1523 1524 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) 1525 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000) 1526 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800) 1527 #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000) 1528 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800) 1529 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000) 1530 1531 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400) 1532 1533 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300) 1534 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000) 1535 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100) 1536 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200) 1537 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300) 1538 1539 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0) 1540 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000) 1541 1542 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) 1543 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) 1544 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) 1545 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) 1546 1547 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1548 1549 /* values for BIOS Page 1 IOCSettings field */ 1550 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1551 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1552 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1553 1554 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1555 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1556 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1557 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1558 1559 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1560 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1561 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1562 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1563 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1564 1565 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1566 1567 /* values for BIOS Page 1 DeviceSettings field */ 1568 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1569 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1570 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1571 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1572 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1573 1574 /* defines for BIOS Page 1 UEFIVersion field */ 1575 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00) 1576 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8) 1577 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF) 1578 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0) 1579 1580 1581 1582 /* BIOS Page 2 */ 1583 1584 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER 1585 { 1586 U32 Reserved1; /* 0x00 */ 1587 U32 Reserved2; /* 0x04 */ 1588 U32 Reserved3; /* 0x08 */ 1589 U32 Reserved4; /* 0x0C */ 1590 U32 Reserved5; /* 0x10 */ 1591 U32 Reserved6; /* 0x14 */ 1592 } MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1593 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1594 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t; 1595 1596 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID 1597 { 1598 U64 SASAddress; /* 0x00 */ 1599 U8 LUN[8]; /* 0x08 */ 1600 U32 Reserved1; /* 0x10 */ 1601 U32 Reserved2; /* 0x14 */ 1602 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1603 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t; 1604 1605 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT 1606 { 1607 U64 EnclosureLogicalID; /* 0x00 */ 1608 U32 Reserved1; /* 0x08 */ 1609 U32 Reserved2; /* 0x0C */ 1610 U16 SlotNumber; /* 0x10 */ 1611 U16 Reserved3; /* 0x12 */ 1612 U32 Reserved4; /* 0x14 */ 1613 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1614 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1615 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t; 1616 1617 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME 1618 { 1619 U64 DeviceName; /* 0x00 */ 1620 U8 LUN[8]; /* 0x08 */ 1621 U32 Reserved1; /* 0x10 */ 1622 U32 Reserved2; /* 0x14 */ 1623 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1624 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t; 1625 1626 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE 1627 { 1628 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1629 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1630 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1631 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1632 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1633 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t; 1634 1635 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 1636 { 1637 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1638 U32 Reserved1; /* 0x04 */ 1639 U32 Reserved2; /* 0x08 */ 1640 U32 Reserved3; /* 0x0C */ 1641 U32 Reserved4; /* 0x10 */ 1642 U32 Reserved5; /* 0x14 */ 1643 U32 Reserved6; /* 0x18 */ 1644 U8 ReqBootDeviceForm; /* 0x1C */ 1645 U8 Reserved7; /* 0x1D */ 1646 U16 Reserved8; /* 0x1E */ 1647 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */ 1648 U8 ReqAltBootDeviceForm; /* 0x38 */ 1649 U8 Reserved9; /* 0x39 */ 1650 U16 Reserved10; /* 0x3A */ 1651 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */ 1652 U8 CurrentBootDeviceForm; /* 0x58 */ 1653 U8 Reserved11; /* 0x59 */ 1654 U16 Reserved12; /* 0x5A */ 1655 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */ 1656 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2, 1657 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t; 1658 1659 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1660 1661 /* values for BIOS Page 2 BootDeviceForm fields */ 1662 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1663 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1664 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1665 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1666 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1667 1668 1669 /* BIOS Page 3 */ 1670 1671 #define MPI2_BIOSPAGE3_NUM_ADAPTER (4) 1672 1673 typedef struct _MPI2_ADAPTER_INFO 1674 { 1675 U8 PciBusNumber; /* 0x00 */ 1676 U8 PciDeviceAndFunctionNumber; /* 0x01 */ 1677 U16 AdapterFlags; /* 0x02 */ 1678 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO, 1679 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t; 1680 1681 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1682 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1683 1684 typedef struct _MPI2_ADAPTER_ORDER_AUX 1685 { 1686 U64 WWID; /* 0x00 */ 1687 U32 Reserved1; /* 0x08 */ 1688 U32 Reserved2; /* 0x0C */ 1689 } MPI2_ADAPTER_ORDER_AUX, MPI2_POINTER PTR_MPI2_ADAPTER_ORDER_AUX, 1690 Mpi2AdapterOrderAux_t, MPI2_POINTER pMpi2AdapterOrderAux_t; 1691 1692 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 1693 { 1694 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1695 U32 GlobalFlags; /* 0x04 */ 1696 U32 BiosVersion; /* 0x08 */ 1697 MPI2_ADAPTER_INFO AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x0C */ 1698 U32 Reserved1; /* 0x1C */ 1699 MPI2_ADAPTER_ORDER_AUX AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x20 */ /* MPI v2.5 and newer */ 1700 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3, 1701 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t; 1702 1703 #define MPI2_BIOSPAGE3_PAGEVERSION (0x01) 1704 1705 /* values for BIOS Page 3 GlobalFlags */ 1706 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1707 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1708 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1709 1710 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1711 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1712 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1713 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1714 1715 1716 /* BIOS Page 4 */ 1717 1718 /* 1719 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1720 * one and check the value returned for NumPhys at runtime. 1721 */ 1722 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1723 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1724 #endif 1725 1726 typedef struct _MPI2_BIOS4_ENTRY 1727 { 1728 U64 ReassignmentWWID; /* 0x00 */ 1729 U64 ReassignmentDeviceName; /* 0x08 */ 1730 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY, 1731 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t; 1732 1733 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 1734 { 1735 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1736 U8 NumPhys; /* 0x04 */ 1737 U8 Reserved1; /* 0x05 */ 1738 U16 Reserved2; /* 0x06 */ 1739 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */ 1740 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4, 1741 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t; 1742 1743 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1744 1745 1746 /**************************************************************************** 1747 * RAID Volume Config Pages 1748 ****************************************************************************/ 1749 1750 /* RAID Volume Page 0 */ 1751 1752 typedef struct _MPI2_RAIDVOL0_PHYS_DISK 1753 { 1754 U8 RAIDSetNum; /* 0x00 */ 1755 U8 PhysDiskMap; /* 0x01 */ 1756 U8 PhysDiskNum; /* 0x02 */ 1757 U8 Reserved; /* 0x03 */ 1758 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK, 1759 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t; 1760 1761 /* defines for the PhysDiskMap field */ 1762 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1763 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1764 1765 typedef struct _MPI2_RAIDVOL0_SETTINGS 1766 { 1767 U16 Settings; /* 0x00 */ 1768 U8 HotSparePool; /* 0x01 */ 1769 U8 Reserved; /* 0x02 */ 1770 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS, 1771 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t; 1772 1773 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1774 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1775 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1776 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1777 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1778 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1779 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1780 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1781 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1782 1783 /* RAID Volume Page 0 VolumeSettings defines */ 1784 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1785 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1786 1787 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1788 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1789 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1790 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1791 1792 /* 1793 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1794 * one and check the value returned for NumPhysDisks at runtime. 1795 */ 1796 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1797 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1798 #endif 1799 1800 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 1801 { 1802 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1803 U16 DevHandle; /* 0x04 */ 1804 U8 VolumeState; /* 0x06 */ 1805 U8 VolumeType; /* 0x07 */ 1806 U32 VolumeStatusFlags; /* 0x08 */ 1807 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */ 1808 U64 MaxLBA; /* 0x10 */ 1809 U32 StripeSize; /* 0x18 */ 1810 U16 BlockSize; /* 0x1C */ 1811 U16 Reserved1; /* 0x1E */ 1812 U8 SupportedPhysDisks; /* 0x20 */ 1813 U8 ResyncRate; /* 0x21 */ 1814 U16 DataScrubDuration; /* 0x22 */ 1815 U8 NumPhysDisks; /* 0x24 */ 1816 U8 Reserved2; /* 0x25 */ 1817 U8 Reserved3; /* 0x26 */ 1818 U8 InactiveStatus; /* 0x27 */ 1819 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */ 1820 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1821 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t; 1822 1823 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1824 1825 /* values for RAID VolumeState */ 1826 #define MPI2_RAID_VOL_STATE_MISSING (0x00) 1827 #define MPI2_RAID_VOL_STATE_FAILED (0x01) 1828 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1829 #define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1830 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1831 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1832 1833 /* values for RAID VolumeType */ 1834 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1835 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1836 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1837 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1838 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1839 1840 /* values for RAID Volume Page 0 VolumeStatusFlags field */ 1841 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1842 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1843 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1844 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1845 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1846 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1847 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1848 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1849 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1850 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1851 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1852 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1853 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1854 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1855 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1856 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1857 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1858 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1859 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1860 1861 /* values for RAID Volume Page 0 SupportedPhysDisks field */ 1862 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1863 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1864 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1865 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1866 1867 /* values for RAID Volume Page 0 InactiveStatus field */ 1868 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1869 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1870 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1871 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1872 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1873 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1874 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1875 1876 1877 /* RAID Volume Page 1 */ 1878 1879 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 1880 { 1881 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1882 U16 DevHandle; /* 0x04 */ 1883 U16 Reserved0; /* 0x06 */ 1884 U8 GUID[24]; /* 0x08 */ 1885 U8 Name[16]; /* 0x20 */ 1886 U64 WWID; /* 0x30 */ 1887 U32 Reserved1; /* 0x38 */ 1888 U32 Reserved2; /* 0x3C */ 1889 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1890 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t; 1891 1892 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1893 1894 1895 /**************************************************************************** 1896 * RAID Physical Disk Config Pages 1897 ****************************************************************************/ 1898 1899 /* RAID Physical Disk Page 0 */ 1900 1901 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS 1902 { 1903 U16 Reserved1; /* 0x00 */ 1904 U8 HotSparePool; /* 0x02 */ 1905 U8 Reserved2; /* 0x03 */ 1906 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1907 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t; 1908 1909 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1910 1911 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA 1912 { 1913 U8 VendorID[8]; /* 0x00 */ 1914 U8 ProductID[16]; /* 0x08 */ 1915 U8 ProductRevLevel[4]; /* 0x18 */ 1916 U8 SerialNum[32]; /* 0x1C */ 1917 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1918 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1919 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t; 1920 1921 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 1922 { 1923 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1924 U16 DevHandle; /* 0x04 */ 1925 U8 Reserved1; /* 0x06 */ 1926 U8 PhysDiskNum; /* 0x07 */ 1927 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */ 1928 U32 Reserved2; /* 0x0C */ 1929 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */ 1930 U32 Reserved3; /* 0x4C */ 1931 U8 PhysDiskState; /* 0x50 */ 1932 U8 OfflineReason; /* 0x51 */ 1933 U8 IncompatibleReason; /* 0x52 */ 1934 U8 PhysDiskAttributes; /* 0x53 */ 1935 U32 PhysDiskStatusFlags; /* 0x54 */ 1936 U64 DeviceMaxLBA; /* 0x58 */ 1937 U64 HostMaxLBA; /* 0x60 */ 1938 U64 CoercedMaxLBA; /* 0x68 */ 1939 U16 BlockSize; /* 0x70 */ 1940 U16 Reserved5; /* 0x72 */ 1941 U32 Reserved6; /* 0x74 */ 1942 } MPI2_CONFIG_PAGE_RD_PDISK_0, 1943 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1944 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t; 1945 1946 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1947 1948 /* PhysDiskState defines */ 1949 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1950 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1951 #define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1952 #define MPI2_RAID_PD_STATE_ONLINE (0x03) 1953 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1954 #define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1955 #define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1956 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1957 1958 /* OfflineReason defines */ 1959 #define MPI2_PHYSDISK0_ONLINE (0x00) 1960 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1961 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1962 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1963 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1964 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1965 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1966 1967 /* IncompatibleReason defines */ 1968 #define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1969 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1970 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1971 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1972 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1973 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1974 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 1975 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1976 1977 /* PhysDiskAttributes defines */ 1978 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 1979 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1980 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1981 1982 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 1983 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1984 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1985 1986 /* PhysDiskStatusFlags defines */ 1987 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1988 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1989 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1990 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1991 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1992 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 1993 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 1994 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 1995 1996 1997 /* RAID Physical Disk Page 1 */ 1998 1999 /* 2000 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2001 * one and check the value returned for NumPhysDiskPaths at runtime. 2002 */ 2003 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 2004 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 2005 #endif 2006 2007 typedef struct _MPI2_RAIDPHYSDISK1_PATH 2008 { 2009 U16 DevHandle; /* 0x00 */ 2010 U16 Reserved1; /* 0x02 */ 2011 U64 WWID; /* 0x04 */ 2012 U64 OwnerWWID; /* 0x0C */ 2013 U8 OwnerIdentifier; /* 0x14 */ 2014 U8 Reserved2; /* 0x15 */ 2015 U16 Flags; /* 0x16 */ 2016 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH, 2017 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t; 2018 2019 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 2020 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 2021 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 2022 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 2023 2024 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 2025 { 2026 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2027 U8 NumPhysDiskPaths; /* 0x04 */ 2028 U8 PhysDiskNum; /* 0x05 */ 2029 U16 Reserved1; /* 0x06 */ 2030 U32 Reserved2; /* 0x08 */ 2031 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */ 2032 } MPI2_CONFIG_PAGE_RD_PDISK_1, 2033 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 2034 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t; 2035 2036 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 2037 2038 2039 /**************************************************************************** 2040 * values for fields used by several types of SAS Config Pages 2041 ****************************************************************************/ 2042 2043 /* values for NegotiatedLinkRates fields */ 2044 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 2045 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 2046 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 2047 /* link rates used for Negotiated Physical and Logical Link Rate */ 2048 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 2049 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 2050 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 2051 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 2052 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 2053 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 2054 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 2055 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 2056 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 2057 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 2058 #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B) 2059 #define MPI26_SAS_NEG_LINK_RATE_22_5 (0x0C) 2060 2061 2062 /* values for AttachedPhyInfo fields */ 2063 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 2064 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 2065 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 2066 2067 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 2068 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 2069 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 2070 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 2071 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 2072 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 2073 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 2074 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 2075 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 2076 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 2077 2078 2079 /* values for PhyInfo fields */ 2080 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 2081 2082 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 2083 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 2084 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 2085 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 2086 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 2087 2088 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 2089 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 2090 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 2091 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 2092 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 2093 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 2094 2095 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 2096 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 2097 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 2098 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 2099 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 2100 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 2101 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 2102 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 2103 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 2104 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 2105 2106 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 2107 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 2108 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 2109 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 2110 2111 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 2112 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 2113 2114 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 2115 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 2116 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 2117 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 2118 2119 2120 /* values for SAS ProgrammedLinkRate fields */ 2121 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 2122 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 2123 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 2124 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 2125 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 2126 #define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0) 2127 #define MPI26_SAS_PRATE_MAX_RATE_22_5 (0xC0) 2128 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 2129 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 2130 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 2131 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 2132 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 2133 #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B) 2134 #define MPI26_SAS_PRATE_MIN_RATE_22_5 (0x0C) 2135 2136 2137 /* values for SAS HwLinkRate fields */ 2138 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 2139 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 2140 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 2141 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 2142 #define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0) 2143 #define MPI26_SAS_HWRATE_MAX_RATE_22_5 (0xC0) 2144 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 2145 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 2146 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 2147 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 2148 #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B) 2149 #define MPI26_SAS_HWRATE_MIN_RATE_22_5 (0x0C) 2150 2151 2152 2153 /**************************************************************************** 2154 * SAS IO Unit Config Pages 2155 ****************************************************************************/ 2156 2157 /* SAS IO Unit Page 0 */ 2158 2159 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA 2160 { 2161 U8 Port; /* 0x00 */ 2162 U8 PortFlags; /* 0x01 */ 2163 U8 PhyFlags; /* 0x02 */ 2164 U8 NegotiatedLinkRate; /* 0x03 */ 2165 U32 ControllerPhyDeviceInfo;/* 0x04 */ 2166 U16 AttachedDevHandle; /* 0x08 */ 2167 U16 ControllerDevHandle; /* 0x0A */ 2168 U32 DiscoveryStatus; /* 0x0C */ 2169 U32 Reserved; /* 0x10 */ 2170 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 2171 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t; 2172 2173 /* 2174 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2175 * one and check the value returned for NumPhys at runtime. 2176 */ 2177 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX 2178 #define MPI2_SAS_IOUNIT0_PHY_MAX (1) 2179 #endif 2180 2181 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 2182 { 2183 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2184 U32 Reserved1; /* 0x08 */ 2185 U8 NumPhys; /* 0x0C */ 2186 U8 Reserved2; /* 0x0D */ 2187 U16 Reserved3; /* 0x0E */ 2188 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */ 2189 } MPI2_CONFIG_PAGE_SASIOUNIT_0, 2190 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 2191 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t; 2192 2193 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 2194 2195 /* values for SAS IO Unit Page 0 PortFlags */ 2196 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 2197 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 2198 2199 /* values for SAS IO Unit Page 0 PhyFlags */ 2200 #define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2201 #define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2202 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 2203 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 2204 2205 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2206 2207 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 2208 2209 /* values for SAS IO Unit Page 0 DiscoveryStatus */ 2210 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2211 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2212 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 2213 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2214 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2215 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2216 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2217 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 2218 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2219 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2220 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 2221 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2222 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2223 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2224 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2225 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2226 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2227 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2228 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2229 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 2230 2231 2232 /* SAS IO Unit Page 1 */ 2233 2234 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA 2235 { 2236 U8 Port; /* 0x00 */ 2237 U8 PortFlags; /* 0x01 */ 2238 U8 PhyFlags; /* 0x02 */ 2239 U8 MaxMinLinkRate; /* 0x03 */ 2240 U32 ControllerPhyDeviceInfo; /* 0x04 */ 2241 U16 MaxTargetPortConnectTime; /* 0x08 */ 2242 U16 Reserved1; /* 0x0A */ 2243 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 2244 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t; 2245 2246 /* 2247 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2248 * one and check the value returned for NumPhys at runtime. 2249 */ 2250 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX 2251 #define MPI2_SAS_IOUNIT1_PHY_MAX (1) 2252 #endif 2253 2254 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 2255 { 2256 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2257 U16 ControlFlags; /* 0x08 */ 2258 U16 SASNarrowMaxQueueDepth; /* 0x0A */ 2259 U16 AdditionalControlFlags; /* 0x0C */ 2260 U16 SASWideMaxQueueDepth; /* 0x0E */ 2261 U8 NumPhys; /* 0x10 */ 2262 U8 SATAMaxQDepth; /* 0x11 */ 2263 U8 ReportDeviceMissingDelay; /* 0x12 */ 2264 U8 IODeviceMissingDelay; /* 0x13 */ 2265 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */ 2266 } MPI2_CONFIG_PAGE_SASIOUNIT_1, 2267 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 2268 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t; 2269 2270 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 2271 2272 /* values for SAS IO Unit Page 1 ControlFlags */ 2273 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2274 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2275 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */ 2276 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2277 2278 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2279 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2280 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 2281 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 2282 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 2283 2284 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2285 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2286 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2287 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2288 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 2289 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2290 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2291 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */ 2292 2293 /* values for SAS IO Unit Page 1 AdditionalControlFlags */ 2294 #define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 2295 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2296 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2297 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 2298 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2299 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2300 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2301 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2302 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2303 2304 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2305 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2306 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2307 2308 /* values for SAS IO Unit Page 1 PortFlags */ 2309 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2310 2311 /* values for SAS IO Unit Page 1 PhyFlags */ 2312 #define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2313 #define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2314 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 2315 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2316 2317 /* values for SAS IO Unit Page 1 MaxMinLinkRate */ 2318 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 2319 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 2320 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 2321 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 2322 #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0) 2323 #define MPI26_SASIOUNIT1_MAX_RATE_22_5 (0xC0) 2324 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 2325 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 2326 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 2327 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 2328 #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B) 2329 #define MPI26_SASIOUNIT1_MIN_RATE_22_5 (0x0C) 2330 2331 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2332 2333 2334 /* SAS IO Unit Page 4 (for MPI v2.5 and earlier) */ 2335 2336 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP 2337 { 2338 U8 MaxTargetSpinup; /* 0x00 */ 2339 U8 SpinupDelay; /* 0x01 */ 2340 U8 SpinupFlags; /* 0x02 */ 2341 U8 Reserved1; /* 0x03 */ 2342 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2343 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t; 2344 2345 /* defines for SAS IO Unit Page 4 SpinupFlags */ 2346 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01) 2347 2348 2349 /* 2350 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2351 * one and check the value returned for NumPhys at runtime. 2352 */ 2353 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX 2354 #define MPI2_SAS_IOUNIT4_PHY_MAX (4) 2355 #endif 2356 2357 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 2358 { 2359 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2360 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 2361 U32 Reserved1; /* 0x18 */ 2362 U32 Reserved2; /* 0x1C */ 2363 U32 Reserved3; /* 0x20 */ 2364 U8 BootDeviceWaitTime; /* 0x24 */ 2365 U8 SATADeviceWaitTime; /* 0x25 */ 2366 U16 Reserved5; /* 0x26 */ 2367 U8 NumPhys; /* 0x28 */ 2368 U8 PEInitialSpinupDelay; /* 0x29 */ 2369 U8 PEReplyDelay; /* 0x2A */ 2370 U8 Flags; /* 0x2B */ 2371 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */ 2372 } MPI2_CONFIG_PAGE_SASIOUNIT_4, 2373 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 2374 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t; 2375 2376 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 2377 2378 /* defines for Flags field */ 2379 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 2380 2381 /* defines for PHY field */ 2382 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 2383 2384 2385 /* SAS IO Unit Page 5 */ 2386 2387 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 2388 { 2389 U8 ControlFlags; /* 0x00 */ 2390 U8 PortWidthModGroup; /* 0x01 */ 2391 U16 InactivityTimerExponent; /* 0x02 */ 2392 U8 SATAPartialTimeout; /* 0x04 */ 2393 U8 Reserved2; /* 0x05 */ 2394 U8 SATASlumberTimeout; /* 0x06 */ 2395 U8 Reserved3; /* 0x07 */ 2396 U8 SASPartialTimeout; /* 0x08 */ 2397 U8 Reserved4; /* 0x09 */ 2398 U8 SASSlumberTimeout; /* 0x0A */ 2399 U8 Reserved5; /* 0x0B */ 2400 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2401 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2402 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t; 2403 2404 /* defines for ControlFlags field */ 2405 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 2406 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 2407 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 2408 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 2409 2410 /* defines for PortWidthModeGroup field */ 2411 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 2412 2413 /* defines for InactivityTimerExponent field */ 2414 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 2415 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 2416 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 2417 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 2418 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 2419 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 2420 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 2421 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 2422 2423 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 2424 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 2425 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 2426 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 2427 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 2428 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 2429 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 2430 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 2431 2432 /* 2433 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2434 * one and check the value returned for NumPhys at runtime. 2435 */ 2436 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX 2437 #define MPI2_SAS_IOUNIT5_PHY_MAX (1) 2438 #endif 2439 2440 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 2441 { 2442 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2443 U8 NumPhys; /* 0x08 */ 2444 U8 Reserved1; /* 0x09 */ 2445 U16 Reserved2; /* 0x0A */ 2446 U32 Reserved3; /* 0x0C */ 2447 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */ 2448 } MPI2_CONFIG_PAGE_SASIOUNIT_5, 2449 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 2450 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t; 2451 2452 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 2453 2454 2455 /* SAS IO Unit Page 6 */ 2456 2457 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2458 { 2459 U8 CurrentStatus; /* 0x00 */ 2460 U8 CurrentModulation; /* 0x01 */ 2461 U8 CurrentUtilization; /* 0x02 */ 2462 U8 Reserved1; /* 0x03 */ 2463 U32 Reserved2; /* 0x04 */ 2464 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2465 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2466 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 2467 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t; 2468 2469 /* defines for CurrentStatus field */ 2470 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 2471 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 2472 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 2473 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 2474 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 2475 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 2476 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 2477 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 2478 2479 /* defines for CurrentModulation field */ 2480 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 2481 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 2482 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 2483 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 2484 2485 /* 2486 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2487 * one and check the value returned for NumGroups at runtime. 2488 */ 2489 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 2490 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 2491 #endif 2492 2493 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 2494 { 2495 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2496 U32 Reserved1; /* 0x08 */ 2497 U32 Reserved2; /* 0x0C */ 2498 U8 NumGroups; /* 0x10 */ 2499 U8 Reserved3; /* 0x11 */ 2500 U16 Reserved4; /* 0x12 */ 2501 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2502 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */ 2503 } MPI2_CONFIG_PAGE_SASIOUNIT_6, 2504 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 2505 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t; 2506 2507 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 2508 2509 2510 /* SAS IO Unit Page 7 */ 2511 2512 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2513 { 2514 U8 Flags; /* 0x00 */ 2515 U8 Reserved1; /* 0x01 */ 2516 U16 Reserved2; /* 0x02 */ 2517 U8 Threshold75Pct; /* 0x04 */ 2518 U8 Threshold50Pct; /* 0x05 */ 2519 U8 Threshold25Pct; /* 0x06 */ 2520 U8 Reserved3; /* 0x07 */ 2521 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2522 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2523 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2524 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2525 2526 /* defines for Flags field */ 2527 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2528 2529 2530 /* 2531 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2532 * one and check the value returned for NumGroups at runtime. 2533 */ 2534 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2535 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2536 #endif 2537 2538 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 2539 { 2540 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2541 U8 SamplingInterval; /* 0x08 */ 2542 U8 WindowLength; /* 0x09 */ 2543 U16 Reserved1; /* 0x0A */ 2544 U32 Reserved2; /* 0x0C */ 2545 U32 Reserved3; /* 0x10 */ 2546 U8 NumGroups; /* 0x14 */ 2547 U8 Reserved4; /* 0x15 */ 2548 U16 Reserved5; /* 0x16 */ 2549 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2550 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */ 2551 } MPI2_CONFIG_PAGE_SASIOUNIT_7, 2552 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2553 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t; 2554 2555 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2556 2557 2558 /* SAS IO Unit Page 8 */ 2559 2560 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 2561 { 2562 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2563 U32 Reserved1; /* 0x08 */ 2564 U32 PowerManagementCapabilities; /* 0x0C */ 2565 U8 TxRxSleepStatus; /* 0x10 */ /* reserved in MPI 2.0 */ 2566 U8 Reserved2; /* 0x11 */ 2567 U16 Reserved3; /* 0x12 */ 2568 } MPI2_CONFIG_PAGE_SASIOUNIT_8, 2569 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2570 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t; 2571 2572 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2573 2574 /* defines for PowerManagementCapabilities field */ 2575 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000) 2576 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 2577 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 2578 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 2579 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 2580 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010) 2581 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 2582 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 2583 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 2584 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 2585 2586 /* defines for TxRxSleepStatus field */ 2587 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00) 2588 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01) 2589 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02) 2590 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03) 2591 2592 2593 2594 /* SAS IO Unit Page 16 */ 2595 2596 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 2597 { 2598 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2599 U64 TimeStamp; /* 0x08 */ 2600 U32 Reserved1; /* 0x10 */ 2601 U32 Reserved2; /* 0x14 */ 2602 U32 FastPathPendedRequests; /* 0x18 */ 2603 U32 FastPathUnPendedRequests; /* 0x1C */ 2604 U32 FastPathHostRequestStarts; /* 0x20 */ 2605 U32 FastPathFirmwareRequestStarts; /* 0x24 */ 2606 U32 FastPathHostCompletions; /* 0x28 */ 2607 U32 FastPathFirmwareCompletions; /* 0x2C */ 2608 U32 NonFastPathRequestStarts; /* 0x30 */ 2609 U32 NonFastPathHostCompletions; /* 0x30 */ 2610 } MPI2_CONFIG_PAGE_SASIOUNIT16, 2611 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT16, 2612 Mpi2SasIOUnitPage16_t, MPI2_POINTER pMpi2SasIOUnitPage16_t; 2613 2614 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00) 2615 2616 2617 /**************************************************************************** 2618 * SAS Expander Config Pages 2619 ****************************************************************************/ 2620 2621 /* SAS Expander Page 0 */ 2622 2623 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 2624 { 2625 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2626 U8 PhysicalPort; /* 0x08 */ 2627 U8 ReportGenLength; /* 0x09 */ 2628 U16 EnclosureHandle; /* 0x0A */ 2629 U64 SASAddress; /* 0x0C */ 2630 U32 DiscoveryStatus; /* 0x14 */ 2631 U16 DevHandle; /* 0x18 */ 2632 U16 ParentDevHandle; /* 0x1A */ 2633 U16 ExpanderChangeCount; /* 0x1C */ 2634 U16 ExpanderRouteIndexes; /* 0x1E */ 2635 U8 NumPhys; /* 0x20 */ 2636 U8 SASLevel; /* 0x21 */ 2637 U16 Flags; /* 0x22 */ 2638 U16 STPBusInactivityTimeLimit; /* 0x24 */ 2639 U16 STPMaxConnectTimeLimit; /* 0x26 */ 2640 U16 STP_SMP_NexusLossTime; /* 0x28 */ 2641 U16 MaxNumRoutedSasAddresses; /* 0x2A */ 2642 U64 ActiveZoneManagerSASAddress;/* 0x2C */ 2643 U16 ZoneLockInactivityLimit; /* 0x34 */ 2644 U16 Reserved1; /* 0x36 */ 2645 U8 TimeToReducedFunc; /* 0x38 */ 2646 U8 InitialTimeToReducedFunc; /* 0x39 */ 2647 U8 MaxReducedFuncTime; /* 0x3A */ 2648 U8 Reserved2; /* 0x3B */ 2649 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2650 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t; 2651 2652 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2653 2654 /* values for SAS Expander Page 0 DiscoveryStatus field */ 2655 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2656 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2657 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2658 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2659 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2660 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2661 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2662 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2663 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2664 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2665 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2666 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2667 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2668 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2669 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2670 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2671 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2672 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2673 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2674 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2675 2676 /* values for SAS Expander Page 0 Flags field */ 2677 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2678 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2679 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2680 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2681 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2682 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2683 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2684 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2685 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2686 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2687 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2688 2689 2690 /* SAS Expander Page 1 */ 2691 2692 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 2693 { 2694 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2695 U8 PhysicalPort; /* 0x08 */ 2696 U8 Reserved1; /* 0x09 */ 2697 U16 Reserved2; /* 0x0A */ 2698 U8 NumPhys; /* 0x0C */ 2699 U8 Phy; /* 0x0D */ 2700 U16 NumTableEntriesProgrammed; /* 0x0E */ 2701 U8 ProgrammedLinkRate; /* 0x10 */ 2702 U8 HwLinkRate; /* 0x11 */ 2703 U16 AttachedDevHandle; /* 0x12 */ 2704 U32 PhyInfo; /* 0x14 */ 2705 U32 AttachedDeviceInfo; /* 0x18 */ 2706 U16 ExpanderDevHandle; /* 0x1C */ 2707 U8 ChangeCount; /* 0x1E */ 2708 U8 NegotiatedLinkRate; /* 0x1F */ 2709 U8 PhyIdentifier; /* 0x20 */ 2710 U8 AttachedPhyIdentifier; /* 0x21 */ 2711 U8 Reserved3; /* 0x22 */ 2712 U8 DiscoveryInfo; /* 0x23 */ 2713 U32 AttachedPhyInfo; /* 0x24 */ 2714 U8 ZoneGroup; /* 0x28 */ 2715 U8 SelfConfigStatus; /* 0x29 */ 2716 U16 Reserved4; /* 0x2A */ 2717 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2718 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t; 2719 2720 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2721 2722 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2723 2724 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2725 2726 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2727 2728 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */ 2729 2730 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2731 2732 /* values for SAS Expander Page 1 DiscoveryInfo field */ 2733 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2734 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2735 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2736 2737 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2738 2739 2740 /**************************************************************************** 2741 * SAS Device Config Pages 2742 ****************************************************************************/ 2743 2744 /* SAS Device Page 0 */ 2745 2746 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 2747 { 2748 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2749 U16 Slot; /* 0x08 */ 2750 U16 EnclosureHandle; /* 0x0A */ 2751 U64 SASAddress; /* 0x0C */ 2752 U16 ParentDevHandle; /* 0x14 */ 2753 U8 PhyNum; /* 0x16 */ 2754 U8 AccessStatus; /* 0x17 */ 2755 U16 DevHandle; /* 0x18 */ 2756 U8 AttachedPhyIdentifier; /* 0x1A */ 2757 U8 ZoneGroup; /* 0x1B */ 2758 U32 DeviceInfo; /* 0x1C */ 2759 U16 Flags; /* 0x20 */ 2760 U8 PhysicalPort; /* 0x22 */ 2761 U8 MaxPortConnections; /* 0x23 */ 2762 U64 DeviceName; /* 0x24 */ 2763 U8 PortGroups; /* 0x2C */ 2764 U8 DmaGroup; /* 0x2D */ 2765 U8 ControlGroup; /* 0x2E */ 2766 U8 EnclosureLevel; /* 0x2F */ 2767 U8 ConnectorName[4]; /* 0x30 */ 2768 U32 Reserved3; /* 0x34 */ 2769 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2770 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t; 2771 2772 #define MPI2_SASDEVICE0_PAGEVERSION (0x09) 2773 2774 /* values for SAS Device Page 0 AccessStatus field */ 2775 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2776 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2777 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2778 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2779 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2780 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2781 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2782 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2783 /* specific values for SATA Init failures */ 2784 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2785 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2786 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2787 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2788 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2789 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2790 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2791 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2792 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2793 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2794 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2795 2796 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2797 2798 /* values for SAS Device Page 0 Flags field */ 2799 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 2800 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000) 2801 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000) 2802 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2803 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2804 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2805 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2806 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2807 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2808 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2809 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2810 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2811 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2812 #define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE (0x0004) 2813 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002) 2814 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2815 2816 /* SAS Device Page 1 */ 2817 2818 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 2819 { 2820 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2821 U32 Reserved1; /* 0x08 */ 2822 U64 SASAddress; /* 0x0C */ 2823 U32 Reserved2; /* 0x14 */ 2824 U16 DevHandle; /* 0x18 */ 2825 U16 Reserved3; /* 0x1A */ 2826 U8 InitialRegDeviceFIS[20];/* 0x1C */ 2827 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2828 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t; 2829 2830 #define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2831 2832 2833 /**************************************************************************** 2834 * SAS PHY Config Pages 2835 ****************************************************************************/ 2836 2837 /* SAS PHY Page 0 */ 2838 2839 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 2840 { 2841 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2842 U16 OwnerDevHandle; /* 0x08 */ 2843 U16 Reserved1; /* 0x0A */ 2844 U16 AttachedDevHandle; /* 0x0C */ 2845 U8 AttachedPhyIdentifier; /* 0x0E */ 2846 U8 Reserved2; /* 0x0F */ 2847 U32 AttachedPhyInfo; /* 0x10 */ 2848 U8 ProgrammedLinkRate; /* 0x14 */ 2849 U8 HwLinkRate; /* 0x15 */ 2850 U8 ChangeCount; /* 0x16 */ 2851 U8 Flags; /* 0x17 */ 2852 U32 PhyInfo; /* 0x18 */ 2853 U8 NegotiatedLinkRate; /* 0x1C */ 2854 U8 Reserved3; /* 0x1D */ 2855 U16 Reserved4; /* 0x1E */ 2856 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2857 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t; 2858 2859 #define MPI2_SASPHY0_PAGEVERSION (0x03) 2860 2861 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2862 2863 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2864 2865 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2866 2867 /* values for SAS PHY Page 0 Flags field */ 2868 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2869 2870 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2871 2872 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2873 2874 2875 /* SAS PHY Page 1 */ 2876 2877 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 2878 { 2879 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2880 U32 Reserved1; /* 0x08 */ 2881 U32 InvalidDwordCount; /* 0x0C */ 2882 U32 RunningDisparityErrorCount; /* 0x10 */ 2883 U32 LossDwordSynchCount; /* 0x14 */ 2884 U32 PhyResetProblemCount; /* 0x18 */ 2885 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 2886 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t; 2887 2888 #define MPI2_SASPHY1_PAGEVERSION (0x01) 2889 2890 2891 /* SAS PHY Page 2 */ 2892 2893 typedef struct _MPI2_SASPHY2_PHY_EVENT 2894 { 2895 U8 PhyEventCode; /* 0x00 */ 2896 U8 Reserved1; /* 0x01 */ 2897 U16 Reserved2; /* 0x02 */ 2898 U32 PhyEventInfo; /* 0x04 */ 2899 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT, 2900 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t; 2901 2902 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 2903 2904 2905 /* 2906 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2907 * one and check the value returned for NumPhyEvents at runtime. 2908 */ 2909 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX 2910 #define MPI2_SASPHY2_PHY_EVENT_MAX (1) 2911 #endif 2912 2913 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 2914 { 2915 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2916 U32 Reserved1; /* 0x08 */ 2917 U8 NumPhyEvents; /* 0x0C */ 2918 U8 Reserved2; /* 0x0D */ 2919 U16 Reserved3; /* 0x0E */ 2920 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */ 2921 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 2922 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t; 2923 2924 #define MPI2_SASPHY2_PAGEVERSION (0x00) 2925 2926 2927 /* SAS PHY Page 3 */ 2928 2929 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG 2930 { 2931 U8 PhyEventCode; /* 0x00 */ 2932 U8 Reserved1; /* 0x01 */ 2933 U16 Reserved2; /* 0x02 */ 2934 U8 CounterType; /* 0x04 */ 2935 U8 ThresholdWindow; /* 0x05 */ 2936 U8 TimeUnits; /* 0x06 */ 2937 U8 Reserved3; /* 0x07 */ 2938 U32 EventThreshold; /* 0x08 */ 2939 U16 ThresholdFlags; /* 0x0C */ 2940 U16 Reserved4; /* 0x0E */ 2941 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 2942 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t; 2943 2944 /* values for PhyEventCode field */ 2945 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2946 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2947 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2948 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2949 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2950 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 2951 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 2952 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 2953 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 2954 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 2955 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 2956 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 2957 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 2958 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 2959 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 2960 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 2961 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 2962 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 2963 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 2964 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 2965 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 2966 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 2967 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 2968 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 2969 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 2970 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 2971 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 2972 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 2973 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 2974 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 2975 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 2976 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 2977 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 2978 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 2979 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 2980 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 2981 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 2982 /* Following codes are product specific and in MPI v2.6 and later */ 2983 #define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3) 2984 #define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4) 2985 #define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5) 2986 #define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6) 2987 #define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7) 2988 #define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8) 2989 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9) 2990 #define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA) 2991 #define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB) 2992 #define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC) 2993 2994 /* values for the CounterType field */ 2995 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 2996 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 2997 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 2998 2999 /* values for the TimeUnits field */ 3000 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 3001 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 3002 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 3003 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 3004 3005 /* values for the ThresholdFlags field */ 3006 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 3007 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 3008 3009 /* 3010 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3011 * one and check the value returned for NumPhyEvents at runtime. 3012 */ 3013 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX 3014 #define MPI2_SASPHY3_PHY_EVENT_MAX (1) 3015 #endif 3016 3017 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 3018 { 3019 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3020 U32 Reserved1; /* 0x08 */ 3021 U8 NumPhyEvents; /* 0x0C */ 3022 U8 Reserved2; /* 0x0D */ 3023 U16 Reserved3; /* 0x0E */ 3024 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */ 3025 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 3026 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t; 3027 3028 #define MPI2_SASPHY3_PAGEVERSION (0x00) 3029 3030 3031 /* SAS PHY Page 4 */ 3032 3033 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 3034 { 3035 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3036 U16 Reserved1; /* 0x08 */ 3037 U8 Reserved2; /* 0x0A */ 3038 U8 Flags; /* 0x0B */ 3039 U8 InitialFrame[28]; /* 0x0C */ 3040 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 3041 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t; 3042 3043 #define MPI2_SASPHY4_PAGEVERSION (0x00) 3044 3045 /* values for the Flags field */ 3046 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 3047 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 3048 3049 3050 3051 3052 /**************************************************************************** 3053 * SAS Port Config Pages 3054 ****************************************************************************/ 3055 3056 /* SAS Port Page 0 */ 3057 3058 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 3059 { 3060 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3061 U8 PortNumber; /* 0x08 */ 3062 U8 PhysicalPort; /* 0x09 */ 3063 U8 PortWidth; /* 0x0A */ 3064 U8 PhysicalPortWidth; /* 0x0B */ 3065 U8 ZoneGroup; /* 0x0C */ 3066 U8 Reserved1; /* 0x0D */ 3067 U16 Reserved2; /* 0x0E */ 3068 U64 SASAddress; /* 0x10 */ 3069 U32 DeviceInfo; /* 0x18 */ 3070 U32 Reserved3; /* 0x1C */ 3071 U32 Reserved4; /* 0x20 */ 3072 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 3073 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t; 3074 3075 #define MPI2_SASPORT0_PAGEVERSION (0x00) 3076 3077 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 3078 3079 3080 /**************************************************************************** 3081 * SAS Enclosure Config Pages 3082 ****************************************************************************/ 3083 3084 /* SAS Enclosure Page 0, Enclosure Page 0 */ 3085 3086 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 3087 { 3088 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3089 U32 Reserved1; /* 0x08 */ 3090 U64 EnclosureLogicalID; /* 0x0C */ 3091 U16 Flags; /* 0x14 */ 3092 U16 EnclosureHandle; /* 0x16 */ 3093 U16 NumSlots; /* 0x18 */ 3094 U16 StartSlot; /* 0x1A */ 3095 U8 Reserved2; /* 0x1C */ 3096 U8 EnclosureLevel; /* 0x1D */ 3097 U16 SEPDevHandle; /* 0x1E */ 3098 U32 Reserved3; /* 0x20 */ 3099 U32 Reserved4; /* 0x24 */ 3100 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3101 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3102 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t, 3103 MPI26_CONFIG_PAGE_ENCLOSURE_0, 3104 MPI2_POINTER PTR_MPI26_CONFIG_PAGE_ENCLOSURE_0, 3105 Mpi26EnclosurePage0_t, MPI2_POINTER pMpi26EnclosurePage0_t; 3106 3107 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x04) 3108 3109 /* values for SAS Enclosure Page 0 Flags field */ 3110 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3111 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3112 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3113 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3114 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3115 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3116 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3117 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3118 3119 #define MPI26_ENCLOSURE0_PAGEVERSION (0x04) 3120 3121 /* Values for Enclosure Page 0 Flags field */ 3122 #define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3123 #define MPI26_ENCLS0_FLAGS_MNG_MASK (0x000F) 3124 #define MPI26_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3125 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3126 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3127 #define MPI26_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3128 #define MPI26_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3129 #define MPI26_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3130 3131 /**************************************************************************** 3132 * Log Config Page 3133 ****************************************************************************/ 3134 3135 /* Log Page 0 */ 3136 3137 /* 3138 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3139 * one and check the value returned for NumLogEntries at runtime. 3140 */ 3141 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 3142 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 3143 #endif 3144 3145 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 3146 3147 typedef struct _MPI2_LOG_0_ENTRY 3148 { 3149 U64 TimeStamp; /* 0x00 */ 3150 U32 Reserved1; /* 0x08 */ 3151 U16 LogSequence; /* 0x0C */ 3152 U16 LogEntryQualifier; /* 0x0E */ 3153 U8 VP_ID; /* 0x10 */ 3154 U8 VF_ID; /* 0x11 */ 3155 U16 Reserved2; /* 0x12 */ 3156 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */ 3157 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY, 3158 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t; 3159 3160 /* values for Log Page 0 LogEntry LogEntryQualifier field */ 3161 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3162 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3163 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 3164 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 3165 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 3166 3167 typedef struct _MPI2_CONFIG_PAGE_LOG_0 3168 { 3169 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3170 U32 Reserved1; /* 0x08 */ 3171 U32 Reserved2; /* 0x0C */ 3172 U16 NumLogEntries; /* 0x10 */ 3173 U16 Reserved3; /* 0x12 */ 3174 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */ 3175 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0, 3176 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t; 3177 3178 #define MPI2_LOG_0_PAGEVERSION (0x02) 3179 3180 3181 /**************************************************************************** 3182 * RAID Config Page 3183 ****************************************************************************/ 3184 3185 /* RAID Page 0 */ 3186 3187 /* 3188 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3189 * one and check the value returned for NumElements at runtime. 3190 */ 3191 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 3192 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 3193 #endif 3194 3195 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT 3196 { 3197 U16 ElementFlags; /* 0x00 */ 3198 U16 VolDevHandle; /* 0x02 */ 3199 U8 HotSparePool; /* 0x04 */ 3200 U8 PhysDiskNum; /* 0x05 */ 3201 U16 PhysDiskDevHandle; /* 0x06 */ 3202 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3203 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3204 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t; 3205 3206 /* values for the ElementFlags field */ 3207 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 3208 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 3209 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 3210 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 3211 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 3212 3213 3214 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 3215 { 3216 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3217 U8 NumHotSpares; /* 0x08 */ 3218 U8 NumPhysDisks; /* 0x09 */ 3219 U8 NumVolumes; /* 0x0A */ 3220 U8 ConfigNum; /* 0x0B */ 3221 U32 Flags; /* 0x0C */ 3222 U8 ConfigGUID[24]; /* 0x10 */ 3223 U32 Reserved1; /* 0x28 */ 3224 U8 NumElements; /* 0x2C */ 3225 U8 Reserved2; /* 0x2D */ 3226 U16 Reserved3; /* 0x2E */ 3227 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */ 3228 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3229 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3230 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t; 3231 3232 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 3233 3234 /* values for RAID Configuration Page 0 Flags field */ 3235 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 3236 3237 3238 /**************************************************************************** 3239 * Driver Persistent Mapping Config Pages 3240 ****************************************************************************/ 3241 3242 /* Driver Persistent Mapping Page 0 */ 3243 3244 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY 3245 { 3246 U64 PhysicalIdentifier; /* 0x00 */ 3247 U16 MappingInformation; /* 0x08 */ 3248 U16 DeviceIndex; /* 0x0A */ 3249 U32 PhysicalBitsMapping; /* 0x0C */ 3250 U32 Reserved1; /* 0x10 */ 3251 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3252 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3253 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t; 3254 3255 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 3256 { 3257 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3258 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */ 3259 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3260 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3261 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t; 3262 3263 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 3264 3265 /* values for Driver Persistent Mapping Page 0 MappingInformation field */ 3266 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 3267 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 3268 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 3269 3270 3271 /**************************************************************************** 3272 * Ethernet Config Pages 3273 ****************************************************************************/ 3274 3275 /* Ethernet Page 0 */ 3276 3277 /* IP address (union of IPv4 and IPv6) */ 3278 typedef union _MPI2_ETHERNET_IP_ADDR 3279 { 3280 U32 IPv4Addr; 3281 U32 IPv6Addr[4]; 3282 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR, 3283 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t; 3284 3285 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 3286 3287 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 3288 { 3289 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3290 U8 NumInterfaces; /* 0x08 */ 3291 U8 Reserved0; /* 0x09 */ 3292 U16 Reserved1; /* 0x0A */ 3293 U32 Status; /* 0x0C */ 3294 U8 MediaState; /* 0x10 */ 3295 U8 Reserved2; /* 0x11 */ 3296 U16 Reserved3; /* 0x12 */ 3297 U8 MacAddress[6]; /* 0x14 */ 3298 U8 Reserved4; /* 0x1A */ 3299 U8 Reserved5; /* 0x1B */ 3300 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */ 3301 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */ 3302 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */ 3303 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */ 3304 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */ 3305 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */ 3306 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 3307 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 3308 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t; 3309 3310 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 3311 3312 /* values for Ethernet Page 0 Status field */ 3313 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 3314 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 3315 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 3316 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 3317 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 3318 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 3319 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 3320 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 3321 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 3322 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 3323 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 3324 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 3325 3326 /* values for Ethernet Page 0 MediaState field */ 3327 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 3328 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 3329 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 3330 3331 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 3332 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 3333 #define MPI2_ETHPG0_MS_10MBIT (0x01) 3334 #define MPI2_ETHPG0_MS_100MBIT (0x02) 3335 #define MPI2_ETHPG0_MS_1GBIT (0x03) 3336 3337 3338 /* Ethernet Page 1 */ 3339 3340 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 3341 { 3342 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3343 U32 Reserved0; /* 0x08 */ 3344 U32 Flags; /* 0x0C */ 3345 U8 MediaState; /* 0x10 */ 3346 U8 Reserved1; /* 0x11 */ 3347 U16 Reserved2; /* 0x12 */ 3348 U8 MacAddress[6]; /* 0x14 */ 3349 U8 Reserved3; /* 0x1A */ 3350 U8 Reserved4; /* 0x1B */ 3351 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */ 3352 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */ 3353 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */ 3354 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */ 3355 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */ 3356 U32 Reserved5; /* 0x6C */ 3357 U32 Reserved6; /* 0x70 */ 3358 U32 Reserved7; /* 0x74 */ 3359 U32 Reserved8; /* 0x78 */ 3360 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 3361 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 3362 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t; 3363 3364 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 3365 3366 /* values for Ethernet Page 1 Flags field */ 3367 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 3368 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 3369 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 3370 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 3371 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 3372 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 3373 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 3374 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 3375 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 3376 3377 /* values for Ethernet Page 1 MediaState field */ 3378 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 3379 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 3380 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 3381 3382 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 3383 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 3384 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 3385 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 3386 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 3387 3388 3389 /**************************************************************************** 3390 * Extended Manufacturing Config Pages 3391 ****************************************************************************/ 3392 3393 /* 3394 * Generic structure to use for product-specific extended manufacturing pages 3395 * (currently Extended Manufacturing Page 40 through Extended Manufacturing 3396 * Page 60). 3397 */ 3398 3399 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS 3400 { 3401 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3402 U32 ProductSpecificInfo; /* 0x08 */ 3403 } MPI2_CONFIG_PAGE_EXT_MAN_PS, 3404 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 3405 Mpi2ExtManufacturingPagePS_t, MPI2_POINTER pMpi2ExtManufacturingPagePS_t; 3406 3407 /* PageVersion should be provided by product-specific code */ 3408 3409 3410 /**************************************************************************** 3411 * values for fields used by several types of PCIe Config Pages 3412 ****************************************************************************/ 3413 3414 /* values for NegotiatedLinkRates fields */ 3415 #define MPI26_PCIE_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 3416 /* link rates used for Negotiated Physical Link Rate */ 3417 #define MPI26_PCIE_NEG_LINK_RATE_UNKNOWN (0x00) 3418 #define MPI26_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01) 3419 #define MPI26_PCIE_NEG_LINK_RATE_2_5 (0x02) 3420 #define MPI26_PCIE_NEG_LINK_RATE_5_0 (0x03) 3421 #define MPI26_PCIE_NEG_LINK_RATE_8_0 (0x04) 3422 #define MPI26_PCIE_NEG_LINK_RATE_16_0 (0x05) 3423 3424 3425 /**************************************************************************** 3426 * PCIe IO Unit Config Pages (MPI v2.6 and later) 3427 ****************************************************************************/ 3428 3429 /* PCIe IO Unit Page 0 */ 3430 3431 typedef struct _MPI26_PCIE_IO_UNIT0_PHY_DATA 3432 { 3433 U8 Link; /* 0x00 */ 3434 U8 LinkFlags; /* 0x01 */ 3435 U8 PhyFlags; /* 0x02 */ 3436 U8 NegotiatedLinkRate; /* 0x03 */ 3437 U32 ControllerPhyDeviceInfo;/* 0x04 */ 3438 U16 AttachedDevHandle; /* 0x08 */ 3439 U16 ControllerDevHandle; /* 0x0A */ 3440 U32 EnumerationStatus; /* 0x0C */ 3441 U32 Reserved1; /* 0x10 */ 3442 } MPI26_PCIE_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI26_PCIE_IO_UNIT0_PHY_DATA, 3443 Mpi26PCIeIOUnit0PhyData_t, MPI2_POINTER pMpi26PCIeIOUnit0PhyData_t; 3444 3445 /* 3446 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3447 * one and check the value returned for NumPhys at runtime. 3448 */ 3449 #ifndef MPI26_PCIE_IOUNIT0_PHY_MAX 3450 #define MPI26_PCIE_IOUNIT0_PHY_MAX (1) 3451 #endif 3452 3453 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_0 3454 { 3455 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3456 U32 Reserved1; /* 0x08 */ 3457 U8 NumPhys; /* 0x0C */ 3458 U8 InitStatus; /* 0x0D */ 3459 U16 Reserved3; /* 0x0E */ 3460 MPI26_PCIE_IO_UNIT0_PHY_DATA PhyData[MPI26_PCIE_IOUNIT0_PHY_MAX]; /* 0x10 */ 3461 } MPI26_CONFIG_PAGE_PIOUNIT_0, 3462 MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PIOUNIT_0, 3463 Mpi26PCIeIOUnitPage0_t, MPI2_POINTER pMpi26PCIeIOUnitPage0_t; 3464 3465 #define MPI26_PCIEIOUNITPAGE0_PAGEVERSION (0x00) 3466 3467 /* values for PCIe IO Unit Page 0 LinkFlags */ 3468 #define MPI26_PCIEIOUNIT0_LINKFLAGS_ENUMERATION_IN_PROGRESS (0x08) 3469 3470 /* values for PCIe IO Unit Page 0 PhyFlags */ 3471 #define MPI26_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 3472 3473 /* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3474 3475 /* see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo values */ 3476 3477 /* values for PCIe IO Unit Page 0 EnumerationStatus */ 3478 #define MPI26_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000) 3479 #define MPI26_PCIEIOUNIT0_ES_MAX_DEVICES_EXCEEDED (0x20000000) 3480 3481 3482 /* PCIe IO Unit Page 1 */ 3483 3484 typedef struct _MPI26_PCIE_IO_UNIT1_PHY_DATA 3485 { 3486 U8 Link; /* 0x00 */ 3487 U8 LinkFlags; /* 0x01 */ 3488 U8 PhyFlags; /* 0x02 */ 3489 U8 MaxMinLinkRate; /* 0x03 */ 3490 U32 ControllerPhyDeviceInfo; /* 0x04 */ 3491 U32 Reserved1; /* 0x08 */ 3492 } MPI26_PCIE_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI26_PCIE_IO_UNIT1_PHY_DATA, 3493 Mpi26PCIeIOUnit1PhyData_t, MPI2_POINTER pMpi26PCIeIOUnit1PhyData_t; 3494 3495 /* values for LinkFlags */ 3496 #define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS (0x00) 3497 #define MPI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS (0x01) 3498 3499 /* 3500 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3501 * one and check the value returned for NumPhys at runtime. 3502 */ 3503 #ifndef MPI26_PCIE_IOUNIT1_PHY_MAX 3504 #define MPI26_PCIE_IOUNIT1_PHY_MAX (1) 3505 #endif 3506 3507 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1 3508 { 3509 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3510 U16 ControlFlags; /* 0x08 */ 3511 U16 Reserved; /* 0x0A */ 3512 U16 AdditionalControlFlags; /* 0x0C */ 3513 U16 NVMeMaxQueueDepth; /* 0x0E */ 3514 U8 NumPhys; /* 0x10 */ 3515 U8 Reserved1; /* 0x11 */ 3516 U16 Reserved2; /* 0x12 */ 3517 MPI26_PCIE_IO_UNIT1_PHY_DATA PhyData[MPI26_PCIE_IOUNIT1_PHY_MAX];/* 0x14 */ 3518 } MPI26_CONFIG_PAGE_PIOUNIT_1, 3519 MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PIOUNIT_1, 3520 Mpi26PCIeIOUnitPage1_t, MPI2_POINTER pMpi26PCIeIOUnitPage1_t; 3521 3522 #define MPI26_PCIEIOUNITPAGE1_PAGEVERSION (0x00) 3523 3524 /* values for PCIe IO Unit Page 1 PhyFlags */ 3525 #define MPI26_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 3526 #define MPI26_PCIEIOUNIT1_PHYFLAGS_ENDPOINT_ONLY (0x01) 3527 3528 /* values for PCIe IO Unit Page 1 MaxMinLinkRate */ 3529 #define MPI26_PCIEIOUNIT1_MAX_RATE_MASK (0xF0) 3530 #define MPI26_PCIEIOUNIT1_MAX_RATE_SHIFT (4) 3531 #define MPI26_PCIEIOUNIT1_MAX_RATE_2_5 (0x20) 3532 #define MPI26_PCIEIOUNIT1_MAX_RATE_5_0 (0x30) 3533 #define MPI26_PCIEIOUNIT1_MAX_RATE_8_0 (0x40) 3534 #define MPI26_PCIEIOUNIT1_MAX_RATE_16_0 (0x50) 3535 3536 /* see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo values */ 3537 3538 3539 /**************************************************************************** 3540 * PCIe Switch Config Pages (MPI v2.6 and later) 3541 ****************************************************************************/ 3542 3543 /* PCIe Switch Page 0 */ 3544 3545 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_0 3546 { 3547 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3548 U8 PhysicalPort; /* 0x08 */ 3549 U8 Reserved1; /* 0x09 */ 3550 U16 Reserved2; /* 0x0A */ 3551 U16 DevHandle; /* 0x0C */ 3552 U16 ParentDevHandle; /* 0x0E */ 3553 U8 NumPorts; /* 0x10 */ 3554 U8 PCIeLevel; /* 0x11 */ 3555 U16 Reserved3; /* 0x12 */ 3556 U32 Reserved4; /* 0x14 */ 3557 U32 Reserved5; /* 0x18 */ 3558 U32 Reserved6; /* 0x1C */ 3559 } MPI26_CONFIG_PAGE_PSWITCH_0, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PSWITCH_0, 3560 Mpi26PCIeSwitchPage0_t, MPI2_POINTER pMpi26PCIeSwitchPage0_t; 3561 3562 #define MPI26_PCIESWITCH0_PAGEVERSION (0x00) 3563 3564 3565 /* PCIe Switch Page 1 */ 3566 3567 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_1 3568 { 3569 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3570 U8 PhysicalPort; /* 0x08 */ 3571 U8 Reserved1; /* 0x09 */ 3572 U16 Reserved2; /* 0x0A */ 3573 U8 NumPorts; /* 0x0C */ 3574 U8 PortNum; /* 0x0D */ 3575 U16 AttachedDevHandle; /* 0x0E */ 3576 U16 SwitchDevHandle; /* 0x10 */ 3577 U8 NegotiatedPortWidth; /* 0x12 */ 3578 U8 NegotiatedLinkRate; /* 0x13 */ 3579 U32 Reserved4; /* 0x14 */ 3580 U32 Reserved5; /* 0x18 */ 3581 } MPI26_CONFIG_PAGE_PSWITCH_1, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PSWITCH_1, 3582 Mpi26PCIeSwitchPage1_t, MPI2_POINTER pMpi26PCIeSwitchPage1_t; 3583 3584 #define MPI26_PCIESWITCH1_PAGEVERSION (0x00) 3585 3586 /* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3587 3588 3589 /**************************************************************************** 3590 * PCIe Device Config Pages (MPI v2.6 and later) 3591 ****************************************************************************/ 3592 3593 /* PCIe Device Page 0 */ 3594 3595 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0 3596 { 3597 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3598 U16 Slot; /* 0x08 */ 3599 U16 EnclosureHandle; /* 0x0A */ 3600 U64 WWID; /* 0x0C */ 3601 U16 ParentDevHandle; /* 0x14 */ 3602 U8 PortNum; /* 0x16 */ 3603 U8 AccessStatus; /* 0x17 */ 3604 U16 DevHandle; /* 0x18 */ 3605 U8 PhysicalPort; /* 0x1A */ 3606 U8 Reserved1; /* 0x1B */ 3607 U32 DeviceInfo; /* 0x1C */ 3608 U32 Flags; /* 0x20 */ 3609 U8 SupportedLinkRates; /* 0x24 */ 3610 U8 MaxPortWidth; /* 0x25 */ 3611 U8 NegotiatedPortWidth; /* 0x26 */ 3612 U8 NegotiatedLinkRate; /* 0x27 */ 3613 U8 EnclosureLevel; /* 0x28 */ 3614 U8 Reserved2; /* 0x29 */ 3615 U16 Reserved3; /* 0x2A */ 3616 U8 ConnectorName[4]; /* 0x2C */ 3617 U32 Reserved4; /* 0x30 */ 3618 U32 Reserved5; /* 0x34 */ 3619 } MPI26_CONFIG_PAGE_PCIEDEV_0, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIEDEV_0, 3620 Mpi26PCIeDevicePage0_t, MPI2_POINTER pMpi26PCIeDevicePage0_t; 3621 3622 #define MPI26_PCIEDEVICE0_PAGEVERSION (0x01) 3623 3624 /* values for PCIe Device Page 0 AccessStatus field */ 3625 #define MPI26_PCIEDEV0_ASTATUS_NO_ERRORS (0x00) 3626 #define MPI26_PCIEDEV0_ASTATUS_NEEDS_INITIALIZATION (0x04) 3627 #define MPI26_PCIEDEV0_ASTATUS_CAPABILITY_FAILED (0x02) 3628 #define MPI26_PCIEDEV0_ASTATUS_DEVICE_BLOCKED (0x07) 3629 #define MPI26_PCIEDEV0_ASTATUS_MEMORY_SPACE_ACCESS_FAILED (0x08) 3630 #define MPI26_PCIEDEV0_ASTATUS_UNSUPPORTED_DEVICE (0x09) 3631 #define MPI26_PCIEDEV0_ASTATUS_MSIX_REQUIRED (0x0A) 3632 #define MPI26_PCIEDEV0_ASTATUS_UNKNOWN (0x10) 3633 3634 #define MPI26_PCIEDEV0_ASTATUS_NVME_READY_TIMEOUT (0x30) 3635 #define MPI26_PCIEDEV0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x31) 3636 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDENTIFY_FAILED (0x32) 3637 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCONFIG_FAILED (0x33) 3638 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCREATION_FAILED (0x34) 3639 #define MPI26_PCIEDEV0_ASTATUS_NVME_EVENTCFG_FAILED (0x35) 3640 #define MPI26_PCIEDEV0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x36) 3641 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDLE_TIMEOUT (0x37) 3642 #define MPI26_PCIEDEV0_ASTATUS_NVME_FAILURE_STATUS (0x38) 3643 3644 #define MPI26_PCIEDEV0_ASTATUS_INIT_FAIL_MAX (0x3F) 3645 3646 /* see mpi2_pci.h for the MPI26_PCIE_DEVINFO_ defines used for the DeviceInfo field */ 3647 3648 /* values for PCIe Device Page 0 Flags field */ 3649 #define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 3650 #define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH (0x4000) 3651 #define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE (0x2000) 3652 #define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION (0x0400) 3653 #define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION (0x0200) 3654 #define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 3655 #define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED (0x0080) 3656 #define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED (0x0040) 3657 #define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED (0x0020) 3658 #define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED (0x0010) 3659 #define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID (0x0002) 3660 #define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT (0x0001) 3661 3662 /* values for PCIe Device Page 0 SupportedLinkRates field */ 3663 #define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED (0x08) 3664 #define MPI26_PCIEDEV0_LINK_RATE_8_0_SUPPORTED (0x04) 3665 #define MPI26_PCIEDEV0_LINK_RATE_5_0_SUPPORTED (0x02) 3666 #define MPI26_PCIEDEV0_LINK_RATE_2_5_SUPPORTED (0x01) 3667 3668 /* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3669 3670 3671 /* PCIe Device Page 2 */ 3672 3673 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2 3674 { 3675 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3676 U16 DevHandle; /* 0x08 */ 3677 U16 Reserved1; /* 0x0A */ 3678 U32 MaximumDataTransferSize;/* 0x0C */ 3679 U32 Capabilities; /* 0x10 */ 3680 U32 Reserved2; /* 0x14 */ 3681 } MPI26_CONFIG_PAGE_PCIEDEV_2, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIEDEV_2, 3682 Mpi26PCIeDevicePage2_t, MPI2_POINTER pMpi26PCIeDevicePage2_t; 3683 3684 #define MPI26_PCIEDEVICE2_PAGEVERSION (0x00) 3685 3686 /* defines for PCIe Device Page 2 Capabilities field */ 3687 #define MPI26_PCIEDEV2_CAP_SGL_FORMAT (0x00000004) 3688 #define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT (0x00000002) 3689 #define MPI26_PCIEDEV2_CAP_SGL_SUPPORT (0x00000001) 3690 3691 3692 /**************************************************************************** 3693 * PCIe Link Config Pages (MPI v2.6 and later) 3694 ****************************************************************************/ 3695 3696 /* PCIe Link Page 1 */ 3697 3698 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_1 3699 { 3700 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3701 U8 Link; /* 0x08 */ 3702 U8 Reserved1; /* 0x09 */ 3703 U16 Reserved2; /* 0x0A */ 3704 U32 CorrectableErrorCount; /* 0x0C */ 3705 U16 NonFatalErrorCount; /* 0x10 */ 3706 U16 Reserved3; /* 0x12 */ 3707 U16 FatalErrorCount; /* 0x14 */ 3708 U16 Reserved4; /* 0x16 */ 3709 } MPI26_CONFIG_PAGE_PCIELINK_1, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_1, 3710 Mpi26PcieLinkPage1_t, MPI2_POINTER pMpi26PcieLinkPage1_t; 3711 3712 #define MPI26_PCIELINK1_PAGEVERSION (0x00) 3713 3714 /* PCIe Link Page 2 */ 3715 3716 typedef struct _MPI26_PCIELINK2_LINK_EVENT 3717 { 3718 U8 LinkEventCode; /* 0x00 */ 3719 U8 Reserved1; /* 0x01 */ 3720 U16 Reserved2; /* 0x02 */ 3721 U32 LinkEventInfo; /* 0x04 */ 3722 } MPI26_PCIELINK2_LINK_EVENT, MPI2_POINTER PTR_MPI26_PCIELINK2_LINK_EVENT, 3723 Mpi26PcieLink2LinkEvent_t, MPI2_POINTER pMpi26PcieLink2LinkEvent_t; 3724 3725 /* use MPI26_PCIELINK3_EVTCODE_ for the LinkEventCode field */ 3726 3727 3728 /* 3729 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3730 * one and check the value returned for NumLinkEvents at runtime. 3731 */ 3732 #ifndef MPI26_PCIELINK2_LINK_EVENT_MAX 3733 #define MPI26_PCIELINK2_LINK_EVENT_MAX (1) 3734 #endif 3735 3736 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_2 3737 { 3738 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3739 U8 Link; /* 0x08 */ 3740 U8 Reserved1; /* 0x09 */ 3741 U16 Reserved2; /* 0x0A */ 3742 U8 NumLinkEvents; /* 0x0C */ 3743 U8 Reserved3; /* 0x0D */ 3744 U16 Reserved4; /* 0x0E */ 3745 MPI26_PCIELINK2_LINK_EVENT LinkEvent[MPI26_PCIELINK2_LINK_EVENT_MAX]; /* 0x10 */ 3746 } MPI26_CONFIG_PAGE_PCIELINK_2, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_2, 3747 Mpi26PcieLinkPage2_t, MPI2_POINTER pMpi26PcieLinkPage2_t; 3748 3749 #define MPI26_PCIELINK2_PAGEVERSION (0x00) 3750 3751 3752 /* PCIe Link Page 3 */ 3753 3754 typedef struct _MPI26_PCIELINK3_LINK_EVENT_CONFIG 3755 { 3756 U8 LinkEventCode; /* 0x00 */ 3757 U8 Reserved1; /* 0x01 */ 3758 U16 Reserved2; /* 0x02 */ 3759 U8 CounterType; /* 0x04 */ 3760 U8 ThresholdWindow; /* 0x05 */ 3761 U8 TimeUnits; /* 0x06 */ 3762 U8 Reserved3; /* 0x07 */ 3763 U32 EventThreshold; /* 0x08 */ 3764 U16 ThresholdFlags; /* 0x0C */ 3765 U16 Reserved4; /* 0x0E */ 3766 } MPI26_PCIELINK3_LINK_EVENT_CONFIG, MPI2_POINTER PTR_MPI26_PCIELINK3_LINK_EVENT_CONFIG, 3767 Mpi26PcieLink3LinkEventConfig_t, MPI2_POINTER pMpi26PcieLink3LinkEventConfig_t; 3768 3769 /* values for LinkEventCode field */ 3770 #define MPI26_PCIELINK3_EVTCODE_NO_EVENT (0x00) 3771 #define MPI26_PCIELINK3_EVTCODE_CORRECTABLE_ERROR_RECEIVED (0x01) 3772 #define MPI26_PCIELINK3_EVTCODE_NON_FATAL_ERROR_RECEIVED (0x02) 3773 #define MPI26_PCIELINK3_EVTCODE_FATAL_ERROR_RECEIVED (0x03) 3774 #define MPI26_PCIELINK3_EVTCODE_DATA_LINK_ERROR_DETECTED (0x04) 3775 #define MPI26_PCIELINK3_EVTCODE_TRANSACTION_LAYER_ERROR_DETECTED (0x05) 3776 #define MPI26_PCIELINK3_EVTCODE_TLP_ECRC_ERROR_DETECTED (0x06) 3777 #define MPI26_PCIELINK3_EVTCODE_POISONED_TLP (0x07) 3778 #define MPI26_PCIELINK3_EVTCODE_RECEIVED_NAK_DLLP (0x08) 3779 #define MPI26_PCIELINK3_EVTCODE_SENT_NAK_DLLP (0x09) 3780 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RECOVERY_STATE (0x0A) 3781 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RXL0S_STATE (0x0B) 3782 #define MPI26_PCIELINK3_EVTCODE_LTSSM_TXL0S_STATE (0x0C) 3783 #define MPI26_PCIELINK3_EVTCODE_LTSSM_L1_STATE (0x0D) 3784 #define MPI26_PCIELINK3_EVTCODE_LTSSM_DISABLED_STATE (0x0E) 3785 #define MPI26_PCIELINK3_EVTCODE_LTSSM_HOT_RESET_STATE (0x0F) 3786 #define MPI26_PCIELINK3_EVTCODE_SYSTEM_ERROR (0x10) 3787 #define MPI26_PCIELINK3_EVTCODE_DECODE_ERROR (0x11) 3788 #define MPI26_PCIELINK3_EVTCODE_DISPARITY_ERROR (0x12) 3789 3790 /* values for the CounterType field */ 3791 #define MPI26_PCIELINK3_COUNTER_TYPE_WRAPPING (0x00) 3792 #define MPI26_PCIELINK3_COUNTER_TYPE_SATURATING (0x01) 3793 #define MPI26_PCIELINK3_COUNTER_TYPE_PEAK_VALUE (0x02) 3794 3795 /* values for the TimeUnits field */ 3796 #define MPI26_PCIELINK3_TM_UNITS_10_MICROSECONDS (0x00) 3797 #define MPI26_PCIELINK3_TM_UNITS_100_MICROSECONDS (0x01) 3798 #define MPI26_PCIELINK3_TM_UNITS_1_MILLISECOND (0x02) 3799 #define MPI26_PCIELINK3_TM_UNITS_10_MILLISECONDS (0x03) 3800 3801 /* values for the ThresholdFlags field */ 3802 #define MPI26_PCIELINK3_TFLAGS_EVENT_NOTIFY (0x0001) 3803 3804 /* 3805 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3806 * one and check the value returned for NumLinkEvents at runtime. 3807 */ 3808 #ifndef MPI26_PCIELINK3_LINK_EVENT_MAX 3809 #define MPI26_PCIELINK3_LINK_EVENT_MAX (1) 3810 #endif 3811 3812 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_3 3813 { 3814 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3815 U8 Link; /* 0x08 */ 3816 U8 Reserved1; /* 0x09 */ 3817 U16 Reserved2; /* 0x0A */ 3818 U8 NumLinkEvents; /* 0x0C */ 3819 U8 Reserved3; /* 0x0D */ 3820 U16 Reserved4; /* 0x0E */ 3821 MPI26_PCIELINK3_LINK_EVENT_CONFIG LinkEventConfig[MPI26_PCIELINK3_LINK_EVENT_MAX]; /* 0x10 */ 3822 } MPI26_CONFIG_PAGE_PCIELINK_3, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_3, 3823 Mpi26PcieLinkPage3_t, MPI2_POINTER pMpi26PcieLinkPage3_t; 3824 3825 #define MPI26_PCIELINK3_PAGEVERSION (0x00) 3826 3827 3828 #endif 3829 3830