1 /*- 2 * Copyright 2000-2020 Broadcom Inc. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. Neither the name of the author nor the names of any co-contributors 13 * may be used to endorse or promote products derived from this software 14 * without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD 29 * 30 * $FreeBSD$ 31 */ 32 33 /* 34 * Copyright 2000-2020 Broadcom Inc. All rights reserved. 35 * 36 * 37 * Name: mpi2_cnfg.h 38 * Title: MPI Configuration messages and pages 39 * Creation Date: November 10, 2006 40 * 41 * mpi2_cnfg.h Version: 02.00.45 42 * 43 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 44 * prefix are for use only on MPI v2.5 products, and must not be used 45 * with MPI v2.0 products. Unless otherwise noted, names beginning with 46 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 47 * 48 * Version History 49 * --------------- 50 * 51 * Date Version Description 52 * -------- -------- ------------------------------------------------------ 53 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 54 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 55 * Added Manufacturing Page 11. 56 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 57 * define. 58 * 06-26-07 02.00.02 Adding generic structure for product-specific 59 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 60 * Rework of BIOS Page 2 configuration page. 61 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 62 * forms. 63 * Added configuration pages IOC Page 8 and Driver 64 * Persistent Mapping Page 0. 65 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 66 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 67 * RAID Physical Disk Pages 0 and 1, RAID Configuration 68 * Page 0). 69 * Added new value for AccessStatus field of SAS Device 70 * Page 0 (_SATA_NEEDS_INITIALIZATION). 71 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 72 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 73 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 74 * NVDATA. 75 * Modified IOC Page 7 to use masks and added field for 76 * SASBroadcastPrimitiveMasks. 77 * Added MPI2_CONFIG_PAGE_BIOS_4. 78 * Added MPI2_CONFIG_PAGE_LOG_0. 79 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 80 * Added SAS Device IDs. 81 * Updated Integrated RAID configuration pages including 82 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 83 * Page 0. 84 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 85 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 86 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 87 * Added missing MaxNumRoutedSasAddresses field to 88 * MPI2_CONFIG_PAGE_EXPANDER_0. 89 * Added SAS Port Page 0. 90 * Modified structure layout for 91 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 92 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 93 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 94 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 95 * to 0x000000FF. 96 * Added two new values for the Physical Disk Coercion Size 97 * bits in the Flags field of Manufacturing Page 4. 98 * Added product-specific Manufacturing pages 16 to 31. 99 * Modified Flags bits for controlling write cache on SATA 100 * drives in IO Unit Page 1. 101 * Added new bit to AdditionalControlFlags of SAS IO Unit 102 * Page 1 to control Invalid Topology Correction. 103 * Added additional defines for RAID Volume Page 0 104 * VolumeStatusFlags field. 105 * Modified meaning of RAID Volume Page 0 VolumeSettings 106 * define for auto-configure of hot-swap drives. 107 * Added SupportedPhysDisks field to RAID Volume Page 1 and 108 * added related defines. 109 * Added PhysDiskAttributes field (and related defines) to 110 * RAID Physical Disk Page 0. 111 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 112 * Added three new DiscoveryStatus bits for SAS IO Unit 113 * Page 0 and SAS Expander Page 0. 114 * Removed multiplexing information from SAS IO Unit pages. 115 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 116 * Removed Zone Address Resolved bit from PhyInfo and from 117 * Expander Page 0 Flags field. 118 * Added two new AccessStatus values to SAS Device Page 0 119 * for indicating routing problems. Added 3 reserved words 120 * to this page. 121 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 122 * Inserted missing reserved field into structure for IOC 123 * Page 6. 124 * Added more pending task bits to RAID Volume Page 0 125 * VolumeStatusFlags defines. 126 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 127 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 128 * and SAS Expander Page 0 to flag a downstream initiator 129 * when in simplified routing mode. 130 * Removed SATA Init Failure defines for DiscoveryStatus 131 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 132 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 133 * Added PortGroups, DmaGroup, and ControlGroup fields to 134 * SAS Device Page 0. 135 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 136 * Unit Page 6. 137 * Added expander reduced functionality data to SAS 138 * Expander Page 0. 139 * Added SAS PHY Page 2 and SAS PHY Page 3. 140 * 07-30-09 02.00.12 Added IO Unit Page 7. 141 * Added new device ids. 142 * Added SAS IO Unit Page 5. 143 * Added partial and slumber power management capable flags 144 * to SAS Device Page 0 Flags field. 145 * Added PhyInfo defines for power condition. 146 * Added Ethernet configuration pages. 147 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 148 * Added SAS PHY Page 4 structure and defines. 149 * 02-10-10 02.00.14 Modified the comments for the configuration page 150 * structures that contain an array of data. The host 151 * should use the "count" field in the page data (e.g. the 152 * NumPhys field) to determine the number of valid elements 153 * in the array. 154 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 155 * Added PowerManagementCapabilities to IO Unit Page 7. 156 * Added PortWidthModGroup field to 157 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 158 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 159 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 160 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 161 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 162 * define. 163 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 164 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 165 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 166 * defines. 167 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 168 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 169 * the Pinout field. 170 * Added BoardTemperature and BoardTemperatureUnits fields 171 * to MPI2_CONFIG_PAGE_IO_UNIT_7. 172 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 173 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 174 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST. 175 * Added IO Unit Page 8, IO Unit Page 9, 176 * and IO Unit Page 10. 177 * Added SASNotifyPrimitiveMasks field to 178 * MPI2_CONFIG_PAGE_IOC_7. 179 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec). 180 * 05-25-11 02.00.20 Cleaned up a few comments. 181 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities 182 * for PCIe link as obsolete. 183 * Added SpinupFlags field containing a Disable Spin-up bit 184 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO 185 * Unit Page 4. 186 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT. 187 * Added UEFIVersion field to BIOS Page 1 and defined new 188 * BiosOptions bits. 189 * Incorporating additions for MPI v2.5. 190 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER. 191 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID. 192 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as 193 * obsolete for MPI v2.5 and later. 194 * Added some defines for 12G SAS speeds. 195 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK. 196 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to 197 * match the specification. 198 * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for 199 * future use. 200 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for 201 * MPI2_CONFIG_PAGE_MAN_7. 202 * Added EnclosureLevel and ConnectorName fields to 203 * MPI2_CONFIG_PAGE_SAS_DEV_0. 204 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for 205 * MPI2_CONFIG_PAGE_SAS_DEV_0. 206 * Added EnclosureLevel field to 207 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 208 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for 209 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 210 * 01-08-14 02.00.28 Added more defines for the BiosOptions field of 211 * MPI2_CONFIG_PAGE_BIOS_1. 212 * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and 213 * more defines for the BiosOptions field. 214 * 11-18-14 02.00.30 Updated copyright information. 215 * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG. 216 * Added AdapterOrderAux fields to BIOS Page 3. 217 * 03-16-15 02.00.31 Updated for MPI v2.6. 218 * Added BoardPowerRequirement, PCISlotPowerAllocation, and 219 * Flags field to IO Unit Page 7. 220 * Added IO Unit Page 11. 221 * Added new SAS Phy Event codes 222 * Added PCIe configuration pages. 223 * 03-19-15 02.00.32 Fixed PCIe Link Config page structure names to be 224 * unique in first 32 characters. 225 * 05-25-15 02.00.33 Added more defines for the BiosOptions field of 226 * MPI2_CONFIG_PAGE_BIOS_1. 227 * 08-25-15 02.00.34 Added PCIe Device Page 2 SGL format capability. 228 * 12-18-15 02.00.35 Added SATADeviceWaitTime to SAS IO Unit Page 4. 229 * 01-21-16 02.00.36 Added/modified MPI2_MFGPAGE_DEVID_SAS defines. 230 * Added Link field to PCIe Link Pages 231 * Added EnclosureLevel and ConnectorName to PCIe 232 * Device Page 0. 233 * Added define for PCIE IoUnit page 1 max rate shift. 234 * Added comment for reserved ExtPageTypes. 235 * Added SAS 4 22.5 gbs speed support. 236 * Added PCIe 4 16.0 GT/sec speec support. 237 * Removed AHCI support. 238 * Removed SOP support. 239 * Added NegotiatedLinkRate and NegotiatedPortWidth to 240 * PCIe device page 0. 241 * 04-10-16 02.00.37 Fixed MPI2_MFGPAGE_DEVID_SAS3616/3708 defines 242 * 07-01-16 02.00.38 Added Manufacturing page 7 Connector types. 243 * Changed declaration of ConnectorName in PCIe DevicePage0 244 * to match SAS DevicePage 0. 245 * Added SATADeviceWaitTime to IO Unit Page 11. 246 * Added MPI26_MFGPAGE_DEVID_SAS4008 247 * Added x16 PCIe width to IO Unit Page 7 248 * Added LINKFLAGS to control SRIS in PCIe IO Unit page 1 249 * phy data. 250 * Added InitStatus to PCIe IO Unit Page 1 header. 251 * 09-01-16 02.00.39 Added MPI26_CONFIG_PAGE_ENCLOSURE_0 and related defines. 252 * Added MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE and 253 * MPI26_ENCLOS_PGAD_FORM_HANDLE page address formats. 254 * 02-02-17 02.00.40 Added MPI2_MANPAGE7_SLOT_UNKNOWN. 255 * Added ChassisSlot field to SAS Enclosure Page 0. 256 * Added ChassisSlot Valid bit (bit 5) to the Flags field 257 * in SAS Enclosure Page 0. 258 * 06-13-17 02.00.41 Added MPI26_MFGPAGE_DEVID_SAS3816 and 259 * MPI26_MFGPAGE_DEVID_SAS3916 defines. 260 * Removed MPI26_MFGPAGE_DEVID_SAS4008 define. 261 * Added MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN define. 262 * Renamed PI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS to 263 * PI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN. 264 * Renamed MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS to 265 * MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK. 266 * 09-29-17 02.00.42 Added ControllerResetTO field to PCIe Device Page 2. 267 * Added NOIOB field to PCIe Device Page 2. 268 * Added MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN to 269 * the Capabilities field of PCIe Device Page 2. 270 * 07-22-18 02.00.43 Added defines for SAS3916 and SAS3816. 271 * Added WRiteCache defines to IO Unit Page 1. 272 * Added MaxEnclosureLevel to BIOS Page 1. 273 * Added OEMRD to SAS Enclosure Page 1. 274 * Added DMDReportPCIe to PCIe IO Unit Page 1. 275 * Added Flags field and flags for Retimers to 276 * PCIe Switch Page 1. 277 * 08-02-18 02.00.44 Added Slotx2, Slotx4 to ManPage 7. 278 * 08-15-18 02.00.45 Added ProductSpecific field at end of IOC Page 1 279 * -------------------------------------------------------------------------- 280 */ 281 282 #ifndef MPI2_CNFG_H 283 #define MPI2_CNFG_H 284 285 /***************************************************************************** 286 * Configuration Page Header and defines 287 *****************************************************************************/ 288 289 /* Config Page Header */ 290 typedef struct _MPI2_CONFIG_PAGE_HEADER 291 { 292 U8 PageVersion; /* 0x00 */ 293 U8 PageLength; /* 0x01 */ 294 U8 PageNumber; /* 0x02 */ 295 U8 PageType; /* 0x03 */ 296 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER, 297 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t; 298 299 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION 300 { 301 MPI2_CONFIG_PAGE_HEADER Struct; 302 U8 Bytes[4]; 303 U16 Word16[2]; 304 U32 Word32; 305 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 306 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion; 307 308 /* Extended Config Page Header */ 309 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER 310 { 311 U8 PageVersion; /* 0x00 */ 312 U8 Reserved1; /* 0x01 */ 313 U8 PageNumber; /* 0x02 */ 314 U8 PageType; /* 0x03 */ 315 U16 ExtPageLength; /* 0x04 */ 316 U8 ExtPageType; /* 0x06 */ 317 U8 Reserved2; /* 0x07 */ 318 } MPI2_CONFIG_EXTENDED_PAGE_HEADER, 319 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 320 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t; 321 322 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION 323 { 324 MPI2_CONFIG_PAGE_HEADER Struct; 325 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 326 U8 Bytes[8]; 327 U16 Word16[4]; 328 U32 Word32[2]; 329 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 330 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion; 331 332 /* PageType field values */ 333 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 334 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 335 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 336 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 337 338 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 339 #define MPI2_CONFIG_PAGETYPE_IOC (0x01) 340 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 341 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 342 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 343 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 344 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 345 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 346 347 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 348 349 /* ExtPageType field values */ 350 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 351 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 352 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 353 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 354 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 355 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 356 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 357 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 358 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 359 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 360 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 361 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_IO_UNIT (0x1B) /* MPI v2.6 and later */ 362 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_SWITCH (0x1C) /* MPI v2.6 and later */ 363 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_DEVICE (0x1D) /* MPI v2.6 and later */ 364 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_LINK (0x1E) /* MPI v2.6 and later */ 365 /* Product specific reserved values 0xE0 - 0xEF */ 366 /* Vendor specific reserved values 0xF0 - 0xFF */ 367 368 /***************************************************************************** 369 * PageAddress defines 370 *****************************************************************************/ 371 372 /* RAID Volume PageAddress format */ 373 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 374 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 375 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 376 377 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 378 379 /* RAID Physical Disk PageAddress format */ 380 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 381 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 382 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 383 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 384 385 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 386 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 387 388 /* SAS Expander PageAddress format */ 389 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 390 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 391 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 392 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 393 394 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 395 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 396 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 397 398 /* SAS Device PageAddress format */ 399 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 400 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 401 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 402 403 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 404 405 /* SAS PHY PageAddress format */ 406 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 407 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 408 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 409 410 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 411 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 412 413 /* SAS Port PageAddress format */ 414 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 415 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 416 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 417 418 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 419 420 /* SAS Enclosure PageAddress format */ 421 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 422 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 423 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 424 425 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 426 427 /* Enclosure PageAddress format */ 428 #define MPI26_ENCLOS_PGAD_FORM_MASK (0xF0000000) 429 #define MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 430 #define MPI26_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 431 432 #define MPI26_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 433 434 /* RAID Configuration PageAddress format */ 435 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 436 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 437 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 438 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 439 440 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 441 442 /* Driver Persistent Mapping PageAddress format */ 443 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 444 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 445 446 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 447 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 448 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 449 450 /* Ethernet PageAddress format */ 451 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 452 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 453 454 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 455 456 /* PCIe Switch PageAddress format */ 457 #define MPI26_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000) 458 #define MPI26_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 459 #define MPI26_PCIE_SWITCH_PGAD_FORM_HNDL_PORTNUM (0x10000000) 460 #define MPI26_PCIE_SWITCH_EXPAND_PGAD_FORM_HNDL (0x20000000) 461 462 #define MPI26_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF) 463 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000) 464 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) 465 466 /* PCIe Device PageAddress format */ 467 #define MPI26_PCIE_DEVICE_PGAD_FORM_MASK (0xF0000000) 468 #define MPI26_PCIE_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 469 #define MPI26_PCIE_DEVICE_PGAD_FORM_HANDLE (0x20000000) 470 471 #define MPI26_PCIE_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 472 473 /* PCIe Link PageAddress format */ 474 #define MPI26_PCIE_LINK_PGAD_FORM_MASK (0xF0000000) 475 #define MPI26_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) 476 #define MPI26_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) 477 478 #define MPI26_PCIE_DEVICE_PGAD_LINKNUM_MASK (0x000000FF) 479 480 /**************************************************************************** 481 * Configuration messages 482 ****************************************************************************/ 483 484 /* Configuration Request Message */ 485 typedef struct _MPI2_CONFIG_REQUEST 486 { 487 U8 Action; /* 0x00 */ 488 U8 SGLFlags; /* 0x01 */ 489 U8 ChainOffset; /* 0x02 */ 490 U8 Function; /* 0x03 */ 491 U16 ExtPageLength; /* 0x04 */ 492 U8 ExtPageType; /* 0x06 */ 493 U8 MsgFlags; /* 0x07 */ 494 U8 VP_ID; /* 0x08 */ 495 U8 VF_ID; /* 0x09 */ 496 U16 Reserved1; /* 0x0A */ 497 U8 Reserved2; /* 0x0C */ 498 U8 ProxyVF_ID; /* 0x0D */ 499 U16 Reserved4; /* 0x0E */ 500 U32 Reserved3; /* 0x10 */ 501 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 502 U32 PageAddress; /* 0x18 */ 503 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */ 504 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST, 505 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t; 506 507 /* values for the Action field */ 508 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 509 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 510 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 511 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 512 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 513 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 514 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 515 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 516 517 /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 518 519 /* Config Reply Message */ 520 typedef struct _MPI2_CONFIG_REPLY 521 { 522 U8 Action; /* 0x00 */ 523 U8 SGLFlags; /* 0x01 */ 524 U8 MsgLength; /* 0x02 */ 525 U8 Function; /* 0x03 */ 526 U16 ExtPageLength; /* 0x04 */ 527 U8 ExtPageType; /* 0x06 */ 528 U8 MsgFlags; /* 0x07 */ 529 U8 VP_ID; /* 0x08 */ 530 U8 VF_ID; /* 0x09 */ 531 U16 Reserved1; /* 0x0A */ 532 U16 Reserved2; /* 0x0C */ 533 U16 IOCStatus; /* 0x0E */ 534 U32 IOCLogInfo; /* 0x10 */ 535 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 536 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY, 537 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t; 538 539 /***************************************************************************** 540 * 541 * C o n f i g u r a t i o n P a g e s 542 * 543 *****************************************************************************/ 544 545 /**************************************************************************** 546 * Manufacturing Config pages 547 ****************************************************************************/ 548 549 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 550 551 /* MPI v2.0 SAS products */ 552 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 553 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 554 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 555 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 556 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 557 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 558 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 559 560 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 561 562 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 563 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 564 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 565 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 566 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 567 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 568 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 569 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 570 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 571 572 /* MPI v2.5 SAS products */ 573 #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096) 574 #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097) 575 #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090) 576 #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091) 577 #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094) 578 #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095) 579 580 /* MPI v2.6 SAS Products */ 581 #define MPI26_MFGPAGE_DEVID_SAS3216 (0x00C9) 582 #define MPI26_MFGPAGE_DEVID_SAS3224 (0x00C4) 583 #define MPI26_MFGPAGE_DEVID_SAS3316_1 (0x00C5) 584 #define MPI26_MFGPAGE_DEVID_SAS3316_2 (0x00C6) 585 #define MPI26_MFGPAGE_DEVID_SAS3316_3 (0x00C7) 586 #define MPI26_MFGPAGE_DEVID_SAS3316_4 (0x00C8) 587 #define MPI26_MFGPAGE_DEVID_SAS3324_1 (0x00C0) 588 #define MPI26_MFGPAGE_DEVID_SAS3324_2 (0x00C1) 589 #define MPI26_MFGPAGE_DEVID_SAS3324_3 (0x00C2) 590 #define MPI26_MFGPAGE_DEVID_SAS3324_4 (0x00C3) 591 592 #define MPI26_MFGPAGE_DEVID_SAS3516 (0x00AA) 593 #define MPI26_MFGPAGE_DEVID_SAS3516_1 (0x00AB) 594 #define MPI26_MFGPAGE_DEVID_SAS3416 (0x00AC) 595 #define MPI26_MFGPAGE_DEVID_SAS3508 (0x00AD) 596 #define MPI26_MFGPAGE_DEVID_SAS3508_1 (0x00AE) 597 #define MPI26_MFGPAGE_DEVID_SAS3408 (0x00AF) 598 599 #define MPI26_MFGPAGE_DEVID_SAS3716 (0x00D0) 600 #define MPI26_MFGPAGE_DEVID_SAS3616 (0x00D1) 601 #define MPI26_MFGPAGE_DEVID_SAS3708 (0x00D2) 602 603 #define MPI26_MFGPAGE_DEVID_SEC_MASK_SAS3916 (0x0003) 604 #define MPI26_MFGPAGE_DEVID_INVALID0_SAS3916 (0x00E0) 605 #define MPI26_MFGPAGE_DEVID_CFG_SEC_SAS3916 (0x00E1) 606 #define MPI26_MFGPAGE_DEVID_HARD_SEC_SAS3916 (0x00E2) 607 #define MPI26_MFGPAGE_DEVID_INVALID1_SAS3916 (0x00E3) 608 609 #define MPI26_MFGPAGE_DEVID_SEC_MASK_SAS3816 (0x0003) 610 #define MPI26_MFGPAGE_DEVID_INVALID0_SAS3816 (0x00E4) 611 #define MPI26_MFGPAGE_DEVID_CFG_SEC_SAS3816 (0x00E5) 612 #define MPI26_MFGPAGE_DEVID_HARD_SEC_SAS3816 (0x00E6) 613 #define MPI26_MFGPAGE_DEVID_INVALID1_SAS3816 (0x00E7) 614 615 /* Manufacturing Page 0 */ 616 617 typedef struct _MPI2_CONFIG_PAGE_MAN_0 618 { 619 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 620 U8 ChipName[16]; /* 0x04 */ 621 U8 ChipRevision[8]; /* 0x14 */ 622 U8 BoardName[16]; /* 0x1C */ 623 U8 BoardAssembly[16]; /* 0x2C */ 624 U8 BoardTracerNumber[16]; /* 0x3C */ 625 } MPI2_CONFIG_PAGE_MAN_0, 626 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0, 627 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t; 628 629 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 630 631 /* Manufacturing Page 1 */ 632 633 typedef struct _MPI2_CONFIG_PAGE_MAN_1 634 { 635 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 636 U8 VPD[256]; /* 0x04 */ 637 } MPI2_CONFIG_PAGE_MAN_1, 638 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1, 639 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t; 640 641 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 642 643 typedef struct _MPI2_CHIP_REVISION_ID 644 { 645 U16 DeviceID; /* 0x00 */ 646 U8 PCIRevisionID; /* 0x02 */ 647 U8 Reserved; /* 0x03 */ 648 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID, 649 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t; 650 651 /* Manufacturing Page 2 */ 652 653 /* 654 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 655 * one and check Header.PageLength at runtime. 656 */ 657 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 658 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 659 #endif 660 661 typedef struct _MPI2_CONFIG_PAGE_MAN_2 662 { 663 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 664 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 665 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */ 666 } MPI2_CONFIG_PAGE_MAN_2, 667 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2, 668 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t; 669 670 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 671 672 /* Manufacturing Page 3 */ 673 674 /* 675 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 676 * one and check Header.PageLength at runtime. 677 */ 678 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS 679 #define MPI2_MAN_PAGE_3_INFO_WORDS (1) 680 #endif 681 682 typedef struct _MPI2_CONFIG_PAGE_MAN_3 683 { 684 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 685 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 686 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */ 687 } MPI2_CONFIG_PAGE_MAN_3, 688 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3, 689 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t; 690 691 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 692 693 /* Manufacturing Page 4 */ 694 695 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS 696 { 697 U8 PowerSaveFlags; /* 0x00 */ 698 U8 InternalOperationsSleepTime; /* 0x01 */ 699 U8 InternalOperationsRunTime; /* 0x02 */ 700 U8 HostIdleTime; /* 0x03 */ 701 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 702 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 703 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t; 704 705 /* defines for the PowerSaveFlags field */ 706 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 707 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 708 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 709 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 710 711 typedef struct _MPI2_CONFIG_PAGE_MAN_4 712 { 713 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 714 U32 Reserved1; /* 0x04 */ 715 U32 Flags; /* 0x08 */ 716 U8 InquirySize; /* 0x0C */ 717 U8 Reserved2; /* 0x0D */ 718 U16 Reserved3; /* 0x0E */ 719 U8 InquiryData[56]; /* 0x10 */ 720 U32 RAID0VolumeSettings; /* 0x48 */ 721 U32 RAID1EVolumeSettings; /* 0x4C */ 722 U32 RAID1VolumeSettings; /* 0x50 */ 723 U32 RAID10VolumeSettings; /* 0x54 */ 724 U32 Reserved4; /* 0x58 */ 725 U32 Reserved5; /* 0x5C */ 726 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */ 727 U8 MaxOCEDisks; /* 0x64 */ 728 U8 ResyncRate; /* 0x65 */ 729 U16 DataScrubDuration; /* 0x66 */ 730 U8 MaxHotSpares; /* 0x68 */ 731 U8 MaxPhysDisksPerVol; /* 0x69 */ 732 U8 MaxPhysDisks; /* 0x6A */ 733 U8 MaxVolumes; /* 0x6B */ 734 } MPI2_CONFIG_PAGE_MAN_4, 735 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4, 736 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t; 737 738 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 739 740 /* Manufacturing Page 4 Flags field */ 741 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 742 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 743 744 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 745 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 746 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 747 748 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 749 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 750 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 751 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 752 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 753 754 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 755 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 756 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 757 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 758 759 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 760 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 761 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 762 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 763 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 764 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 765 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 766 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 767 768 /* Manufacturing Page 5 */ 769 770 /* 771 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 772 * one and check the value returned for NumPhys at runtime. 773 */ 774 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 775 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 776 #endif 777 778 typedef struct _MPI2_MANUFACTURING5_ENTRY 779 { 780 U64 WWID; /* 0x00 */ 781 U64 DeviceName; /* 0x08 */ 782 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY, 783 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t; 784 785 typedef struct _MPI2_CONFIG_PAGE_MAN_5 786 { 787 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 788 U8 NumPhys; /* 0x04 */ 789 U8 Reserved1; /* 0x05 */ 790 U16 Reserved2; /* 0x06 */ 791 U32 Reserved3; /* 0x08 */ 792 U32 Reserved4; /* 0x0C */ 793 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */ 794 } MPI2_CONFIG_PAGE_MAN_5, 795 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5, 796 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t; 797 798 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 799 800 /* Manufacturing Page 6 */ 801 802 typedef struct _MPI2_CONFIG_PAGE_MAN_6 803 { 804 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 805 U32 ProductSpecificInfo;/* 0x04 */ 806 } MPI2_CONFIG_PAGE_MAN_6, 807 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6, 808 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t; 809 810 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 811 812 /* Manufacturing Page 7 */ 813 814 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO 815 { 816 U32 Pinout; /* 0x00 */ 817 U8 Connector[16]; /* 0x04 */ 818 U8 Location; /* 0x14 */ 819 U8 ReceptacleID; /* 0x15 */ 820 U16 Slot; /* 0x16 */ 821 U16 Slotx4; /* 0x18 */ 822 U16 Slotx2; /* 0x1A */ 823 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 824 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t; 825 826 /* defines for the Pinout field */ 827 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 828 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 829 830 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 831 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 832 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 833 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 834 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 835 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 836 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 837 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 838 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 839 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 840 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 841 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 842 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 843 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 844 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 845 #define MPI2_MANPAGE7_PINOUT_SFF_8088_A (0x0E) 846 #define MPI2_MANPAGE7_PINOUT_SFF_8643_16i (0x0F) 847 #define MPI2_MANPAGE7_PINOUT_SFF_8654_4i (0x10) 848 #define MPI2_MANPAGE7_PINOUT_SFF_8654_8i (0x11) 849 #define MPI2_MANPAGE7_PINOUT_SFF_8611_4i (0x12) 850 #define MPI2_MANPAGE7_PINOUT_SFF_8611_8i (0x13) 851 852 /* defines for the Location field */ 853 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 854 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 855 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 856 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 857 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 858 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 859 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 860 861 /* defines for the Slot field */ 862 #define MPI2_MANPAGE7_SLOT_UNKNOWN (0xFFFF) 863 864 /* 865 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 866 * one and check the value returned for NumPhys at runtime. 867 */ 868 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 869 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 870 #endif 871 872 typedef struct _MPI2_CONFIG_PAGE_MAN_7 873 { 874 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 875 U32 Reserved1; /* 0x04 */ 876 U32 Reserved2; /* 0x08 */ 877 U32 Flags; /* 0x0C */ 878 U8 EnclosureName[16]; /* 0x10 */ 879 U8 NumPhys; /* 0x20 */ 880 U8 Reserved3; /* 0x21 */ 881 U16 Reserved4; /* 0x22 */ 882 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */ 883 } MPI2_CONFIG_PAGE_MAN_7, 884 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7, 885 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t; 886 887 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 888 889 /* defines for the Flags field */ 890 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008) 891 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002) 892 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 893 894 /* 895 * Generic structure to use for product-specific manufacturing pages 896 * (currently Manufacturing Page 8 through Manufacturing Page 31). 897 */ 898 899 typedef struct _MPI2_CONFIG_PAGE_MAN_PS 900 { 901 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 902 U32 ProductSpecificInfo;/* 0x04 */ 903 } MPI2_CONFIG_PAGE_MAN_PS, 904 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS, 905 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t; 906 907 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 908 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 909 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 910 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 911 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 912 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 913 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 914 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 915 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 916 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 917 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 918 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 919 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 920 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 921 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 922 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 923 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 924 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 925 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 926 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 927 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 928 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 929 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 930 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 931 932 /**************************************************************************** 933 * IO Unit Config Pages 934 ****************************************************************************/ 935 936 /* IO Unit Page 0 */ 937 938 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 939 { 940 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 941 U64 UniqueValue; /* 0x04 */ 942 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */ 943 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */ 944 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 945 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t; 946 947 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 948 949 /* IO Unit Page 1 */ 950 951 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 952 { 953 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 954 U32 Flags; /* 0x04 */ 955 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 956 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t; 957 958 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 959 960 /* IO Unit Page 1 Flags defines */ 961 #define MPI26_IOUNITPAGE1_NVME_WRITE_CACHE_MASK (0x00030000) 962 #define MPI26_IOUNITPAGE1_NVME_WRITE_CACHE_ENABLE (0x00000000) 963 #define MPI26_IOUNITPAGE1_NVME_WRITE_CACHE_DISABLE (0x00010000) 964 #define MPI26_IOUNITPAGE1_NVME_WRITE_CACHE_NO_CHANGE (0x00020000) 965 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000) 966 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000) 967 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000) 968 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 969 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 970 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 971 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 972 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 973 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 974 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 975 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 976 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 977 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 978 979 /* IO Unit Page 3 */ 980 981 /* 982 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 983 * one and check the value returned for GPIOCount at runtime. 984 */ 985 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 986 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 987 #endif 988 989 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 990 { 991 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 992 U8 GPIOCount; /* 0x04 */ 993 U8 Reserved1; /* 0x05 */ 994 U16 Reserved2; /* 0x06 */ 995 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */ 996 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 997 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t; 998 999 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 1000 1001 /* defines for IO Unit Page 3 GPIOVal field */ 1002 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 1003 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 1004 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 1005 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 1006 1007 /* IO Unit Page 5 */ 1008 1009 /* 1010 * Upper layer code (drivers, utilities, etc.) should leave this define set to 1011 * one and check the value returned for NumDmaEngines at runtime. 1012 */ 1013 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 1014 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 1015 #endif 1016 1017 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 1018 { 1019 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1020 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */ 1021 U64 RaidAcceleratorBufferSize; /* 0x0C */ 1022 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */ 1023 U8 RAControlSize; /* 0x1C */ 1024 U8 NumDmaEngines; /* 0x1D */ 1025 U8 RAMinControlSize; /* 0x1E */ 1026 U8 RAMaxControlSize; /* 0x1F */ 1027 U32 Reserved1; /* 0x20 */ 1028 U32 Reserved2; /* 0x24 */ 1029 U32 Reserved3; /* 0x28 */ 1030 U32 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */ 1031 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 1032 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t; 1033 1034 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 1035 1036 /* defines for IO Unit Page 5 DmaEngineCapabilities field */ 1037 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000) 1038 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 1039 1040 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 1041 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 1042 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 1043 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 1044 1045 /* IO Unit Page 6 */ 1046 1047 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 1048 { 1049 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1050 U16 Flags; /* 0x04 */ 1051 U8 RAHostControlSize; /* 0x06 */ 1052 U8 Reserved0; /* 0x07 */ 1053 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */ 1054 U32 Reserved1; /* 0x10 */ 1055 U32 Reserved2; /* 0x14 */ 1056 U32 Reserved3; /* 0x18 */ 1057 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 1058 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t; 1059 1060 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 1061 1062 /* defines for IO Unit Page 6 Flags field */ 1063 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 1064 1065 /* IO Unit Page 7 */ 1066 1067 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 1068 { 1069 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1070 U8 CurrentPowerMode; /* 0x04 */ /* reserved in MPI 2.0 */ 1071 U8 PreviousPowerMode; /* 0x05 */ /* reserved in MPI 2.0 */ 1072 U8 PCIeWidth; /* 0x06 */ 1073 U8 PCIeSpeed; /* 0x07 */ 1074 U32 ProcessorState; /* 0x08 */ 1075 U32 PowerManagementCapabilities; /* 0x0C */ 1076 U16 IOCTemperature; /* 0x10 */ 1077 U8 IOCTemperatureUnits; /* 0x12 */ 1078 U8 IOCSpeed; /* 0x13 */ 1079 U16 BoardTemperature; /* 0x14 */ 1080 U8 BoardTemperatureUnits; /* 0x16 */ 1081 U8 Reserved3; /* 0x17 */ 1082 U32 BoardPowerRequirement; /* 0x18 */ /* reserved prior to MPI v2.6 */ 1083 U32 PCISlotPowerAllocation; /* 0x1C */ /* reserved prior to MPI v2.6 */ 1084 U8 Flags; /* 0x20 */ /* reserved prior to MPI v2.6 */ 1085 U8 Reserved6; /* 0x21 */ 1086 U16 Reserved7; /* 0x22 */ 1087 U32 Reserved8; /* 0x24 */ 1088 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 1089 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t; 1090 1091 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x05) 1092 1093 /* defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */ 1094 #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0) 1095 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00) 1096 #define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40) 1097 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80) 1098 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0) 1099 1100 #define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07) 1101 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00) 1102 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01) 1103 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04) 1104 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05) 1105 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06) 1106 1107 /* defines for IO Unit Page 7 PCIeWidth field */ 1108 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 1109 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 1110 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 1111 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 1112 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X16 (0x10) 1113 1114 /* defines for IO Unit Page 7 PCIeSpeed field */ 1115 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 1116 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 1117 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 1118 #define MPI2_IOUNITPAGE7_PCIE_SPEED_16_0_GBPS (0x03) 1119 1120 /* defines for IO Unit Page 7 ProcessorState field */ 1121 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 1122 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 1123 1124 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 1125 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 1126 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 1127 1128 /* defines for IO Unit Page 7 PowerManagementCapabilities field */ 1129 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000) 1130 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000) 1131 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000) 1132 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000) 1133 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000) 1134 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000) 1135 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000) 1136 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000) 1137 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000) 1138 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400) 1139 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200) 1140 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100) 1141 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040) 1142 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020) 1143 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010) 1144 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008) /* obsolete */ 1145 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004) /* obsolete */ 1146 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002) /* obsolete */ 1147 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001) /* obsolete */ 1148 1149 /* obsolete names for the PowerManagementCapabilities bits (above) */ 1150 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 1151 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 1152 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 1153 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /* obsolete */ 1154 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /* obsolete */ 1155 1156 /* defines for IO Unit Page 7 IOCTemperatureUnits field */ 1157 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 1158 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 1159 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 1160 1161 /* defines for IO Unit Page 7 IOCSpeed field */ 1162 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 1163 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 1164 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 1165 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 1166 1167 /* defines for IO Unit Page 7 BoardTemperatureUnits field */ 1168 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 1169 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 1170 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 1171 1172 /* defines for IO Unit Page 7 Flags field */ 1173 #define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC (0x01) 1174 1175 /* IO Unit Page 8 */ 1176 1177 #define MPI2_IOUNIT8_NUM_THRESHOLDS (4) 1178 1179 typedef struct _MPI2_IOUNIT8_SENSOR 1180 { 1181 U16 Flags; /* 0x00 */ 1182 U16 Reserved1; /* 0x02 */ 1183 U16 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */ 1184 U32 Reserved2; /* 0x0C */ 1185 U32 Reserved3; /* 0x10 */ 1186 U32 Reserved4; /* 0x14 */ 1187 } MPI2_IOUNIT8_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT8_SENSOR, 1188 Mpi2IOUnit8Sensor_t, MPI2_POINTER pMpi2IOUnit8Sensor_t; 1189 1190 /* defines for IO Unit Page 8 Sensor Flags field */ 1191 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008) 1192 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004) 1193 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002) 1194 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001) 1195 1196 /* 1197 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1198 * one and check the value returned for NumSensors at runtime. 1199 */ 1200 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES 1201 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1) 1202 #endif 1203 1204 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 1205 { 1206 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1207 U32 Reserved1; /* 0x04 */ 1208 U32 Reserved2; /* 0x08 */ 1209 U8 NumSensors; /* 0x0C */ 1210 U8 PollingInterval; /* 0x0D */ 1211 U16 Reserved3; /* 0x0E */ 1212 MPI2_IOUNIT8_SENSOR Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */ 1213 } MPI2_CONFIG_PAGE_IO_UNIT_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_8, 1214 Mpi2IOUnitPage8_t, MPI2_POINTER pMpi2IOUnitPage8_t; 1215 1216 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00) 1217 1218 /* IO Unit Page 9 */ 1219 1220 typedef struct _MPI2_IOUNIT9_SENSOR 1221 { 1222 U16 CurrentTemperature; /* 0x00 */ 1223 U16 Reserved1; /* 0x02 */ 1224 U8 Flags; /* 0x04 */ 1225 U8 Reserved2; /* 0x05 */ 1226 U16 Reserved3; /* 0x06 */ 1227 U32 Reserved4; /* 0x08 */ 1228 U32 Reserved5; /* 0x0C */ 1229 } MPI2_IOUNIT9_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT9_SENSOR, 1230 Mpi2IOUnit9Sensor_t, MPI2_POINTER pMpi2IOUnit9Sensor_t; 1231 1232 /* defines for IO Unit Page 9 Sensor Flags field */ 1233 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01) 1234 1235 /* 1236 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1237 * one and check the value returned for NumSensors at runtime. 1238 */ 1239 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES 1240 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1) 1241 #endif 1242 1243 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 1244 { 1245 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1246 U32 Reserved1; /* 0x04 */ 1247 U32 Reserved2; /* 0x08 */ 1248 U8 NumSensors; /* 0x0C */ 1249 U8 Reserved4; /* 0x0D */ 1250 U16 Reserved3; /* 0x0E */ 1251 MPI2_IOUNIT9_SENSOR Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */ 1252 } MPI2_CONFIG_PAGE_IO_UNIT_9, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_9, 1253 Mpi2IOUnitPage9_t, MPI2_POINTER pMpi2IOUnitPage9_t; 1254 1255 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00) 1256 1257 /* IO Unit Page 10 */ 1258 1259 typedef struct _MPI2_IOUNIT10_FUNCTION 1260 { 1261 U8 CreditPercent; /* 0x00 */ 1262 U8 Reserved1; /* 0x01 */ 1263 U16 Reserved2; /* 0x02 */ 1264 } MPI2_IOUNIT10_FUNCTION, MPI2_POINTER PTR_MPI2_IOUNIT10_FUNCTION, 1265 Mpi2IOUnit10Function_t, MPI2_POINTER pMpi2IOUnit10Function_t; 1266 1267 /* 1268 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1269 * one and check the value returned for NumFunctions at runtime. 1270 */ 1271 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES 1272 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1) 1273 #endif 1274 1275 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 1276 { 1277 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1278 U8 NumFunctions; /* 0x04 */ 1279 U8 Reserved1; /* 0x05 */ 1280 U16 Reserved2; /* 0x06 */ 1281 U32 Reserved3; /* 0x08 */ 1282 U32 Reserved4; /* 0x0C */ 1283 MPI2_IOUNIT10_FUNCTION Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES]; /* 0x10 */ 1284 } MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10, 1285 Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t; 1286 1287 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01) 1288 1289 /* IO Unit Page 11 (for MPI v2.6 and later) */ 1290 1291 typedef struct _MPI26_IOUNIT11_SPINUP_GROUP 1292 { 1293 U8 MaxTargetSpinup; /* 0x00 */ 1294 U8 SpinupDelay; /* 0x01 */ 1295 U8 SpinupFlags; /* 0x02 */ 1296 U8 Reserved1; /* 0x03 */ 1297 } MPI26_IOUNIT11_SPINUP_GROUP, MPI2_POINTER PTR_MPI26_IOUNIT11_SPINUP_GROUP, 1298 Mpi26IOUnit11SpinupGroup_t, MPI2_POINTER pMpi26IOUnit11SpinupGroup_t; 1299 1300 /* defines for IO Unit Page 11 SpinupFlags */ 1301 #define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG (0x01) 1302 1303 /* 1304 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1305 * four and check the value returned for NumPhys at runtime. 1306 */ 1307 #ifndef MPI26_IOUNITPAGE11_PHY_MAX 1308 #define MPI26_IOUNITPAGE11_PHY_MAX (4) 1309 #endif 1310 1311 typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 1312 { 1313 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1314 U32 Reserved1; /* 0x04 */ 1315 MPI26_IOUNIT11_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 1316 U32 Reserved2; /* 0x18 */ 1317 U32 Reserved3; /* 0x1C */ 1318 U32 Reserved4; /* 0x20 */ 1319 U8 BootDeviceWaitTime; /* 0x24 */ 1320 U8 SATADeviceWaitTime; /* 0x25 */ 1321 U16 Reserved6; /* 0x26 */ 1322 U8 NumPhys; /* 0x28 */ 1323 U8 PEInitialSpinupDelay; /* 0x29 */ 1324 U8 PEReplyDelay; /* 0x2A */ 1325 U8 Flags; /* 0x2B */ 1326 U8 PHY[MPI26_IOUNITPAGE11_PHY_MAX];/* 0x2C */ 1327 } MPI26_CONFIG_PAGE_IO_UNIT_11, 1328 MPI2_POINTER PTR_MPI26_CONFIG_PAGE_IO_UNIT_11, 1329 Mpi26IOUnitPage11_t, MPI2_POINTER pMpi26IOUnitPage11_t; 1330 1331 #define MPI26_IOUNITPAGE11_PAGEVERSION (0x00) 1332 1333 /* defines for Flags field */ 1334 #define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE (0x01) 1335 1336 /* defines for PHY field */ 1337 #define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK (0x03) 1338 1339 /**************************************************************************** 1340 * IOC Config Pages 1341 ****************************************************************************/ 1342 1343 /* IOC Page 0 */ 1344 1345 typedef struct _MPI2_CONFIG_PAGE_IOC_0 1346 { 1347 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1348 U32 Reserved1; /* 0x04 */ 1349 U32 Reserved2; /* 0x08 */ 1350 U16 VendorID; /* 0x0C */ 1351 U16 DeviceID; /* 0x0E */ 1352 U8 RevisionID; /* 0x10 */ 1353 U8 Reserved3; /* 0x11 */ 1354 U16 Reserved4; /* 0x12 */ 1355 U32 ClassCode; /* 0x14 */ 1356 U16 SubsystemVendorID; /* 0x18 */ 1357 U16 SubsystemID; /* 0x1A */ 1358 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0, 1359 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t; 1360 1361 #define MPI2_IOCPAGE0_PAGEVERSION (0x02) 1362 1363 /* IOC Page 1 */ 1364 1365 typedef struct _MPI2_CONFIG_PAGE_IOC_1 1366 { 1367 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1368 U32 Flags; /* 0x04 */ 1369 U32 CoalescingTimeout; /* 0x08 */ 1370 U8 CoalescingDepth; /* 0x0C */ 1371 U8 PCISlotNum; /* 0x0D */ 1372 U8 PCIBusNum; /* 0x0E */ 1373 U8 PCIDomainSegment; /* 0x0F */ 1374 U32 Reserved1; /* 0x10 */ 1375 U32 ProductSpecific; /* 0x14 */ 1376 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1, 1377 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t; 1378 1379 #define MPI2_IOCPAGE1_PAGEVERSION (0x05) 1380 1381 /* defines for IOC Page 1 Flags field */ 1382 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 1383 1384 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1385 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 1386 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 1387 1388 /* IOC Page 6 */ 1389 1390 typedef struct _MPI2_CONFIG_PAGE_IOC_6 1391 { 1392 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1393 U32 CapabilitiesFlags; /* 0x04 */ 1394 U8 MaxDrivesRAID0; /* 0x08 */ 1395 U8 MaxDrivesRAID1; /* 0x09 */ 1396 U8 MaxDrivesRAID1E; /* 0x0A */ 1397 U8 MaxDrivesRAID10; /* 0x0B */ 1398 U8 MinDrivesRAID0; /* 0x0C */ 1399 U8 MinDrivesRAID1; /* 0x0D */ 1400 U8 MinDrivesRAID1E; /* 0x0E */ 1401 U8 MinDrivesRAID10; /* 0x0F */ 1402 U32 Reserved1; /* 0x10 */ 1403 U8 MaxGlobalHotSpares; /* 0x14 */ 1404 U8 MaxPhysDisks; /* 0x15 */ 1405 U8 MaxVolumes; /* 0x16 */ 1406 U8 MaxConfigs; /* 0x17 */ 1407 U8 MaxOCEDisks; /* 0x18 */ 1408 U8 Reserved2; /* 0x19 */ 1409 U16 Reserved3; /* 0x1A */ 1410 U32 SupportedStripeSizeMapRAID0; /* 0x1C */ 1411 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */ 1412 U32 SupportedStripeSizeMapRAID10; /* 0x24 */ 1413 U32 Reserved4; /* 0x28 */ 1414 U32 Reserved5; /* 0x2C */ 1415 U16 DefaultMetadataSize; /* 0x30 */ 1416 U16 Reserved6; /* 0x32 */ 1417 U16 MaxBadBlockTableEntries; /* 0x34 */ 1418 U16 Reserved7; /* 0x36 */ 1419 U32 IRNvsramVersion; /* 0x38 */ 1420 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6, 1421 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t; 1422 1423 #define MPI2_IOCPAGE6_PAGEVERSION (0x05) 1424 1425 /* defines for IOC Page 6 CapabilitiesFlags */ 1426 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020) 1427 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1428 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1429 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1430 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1431 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1432 1433 /* IOC Page 7 */ 1434 1435 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1436 1437 typedef struct _MPI2_CONFIG_PAGE_IOC_7 1438 { 1439 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1440 U32 Reserved1; /* 0x04 */ 1441 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */ 1442 U16 SASBroadcastPrimitiveMasks; /* 0x18 */ 1443 U16 SASNotifyPrimitiveMasks; /* 0x1A */ 1444 U32 Reserved3; /* 0x1C */ 1445 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7, 1446 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t; 1447 1448 #define MPI2_IOCPAGE7_PAGEVERSION (0x02) 1449 1450 /* IOC Page 8 */ 1451 1452 typedef struct _MPI2_CONFIG_PAGE_IOC_8 1453 { 1454 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1455 U8 NumDevsPerEnclosure; /* 0x04 */ 1456 U8 Reserved1; /* 0x05 */ 1457 U16 Reserved2; /* 0x06 */ 1458 U16 MaxPersistentEntries; /* 0x08 */ 1459 U16 MaxNumPhysicalMappedIDs; /* 0x0A */ 1460 U16 Flags; /* 0x0C */ 1461 U16 Reserved3; /* 0x0E */ 1462 U16 IRVolumeMappingFlags; /* 0x10 */ 1463 U16 Reserved4; /* 0x12 */ 1464 U32 Reserved5; /* 0x14 */ 1465 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8, 1466 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t; 1467 1468 #define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1469 1470 /* defines for IOC Page 8 Flags field */ 1471 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1472 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1473 1474 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1475 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1476 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1477 1478 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1479 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1480 1481 /* defines for IOC Page 8 IRVolumeMappingFlags */ 1482 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1483 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1484 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1485 1486 /**************************************************************************** 1487 * BIOS Config Pages 1488 ****************************************************************************/ 1489 1490 /* BIOS Page 1 */ 1491 1492 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 1493 { 1494 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1495 U32 BiosOptions; /* 0x04 */ 1496 U32 IOCSettings; /* 0x08 */ 1497 U8 SSUTimeout; /* 0x0C */ 1498 U8 MaxEnclosureLevel; /* 0x0D */ 1499 U16 Reserved2; /* 0x0E */ 1500 U32 DeviceSettings; /* 0x10 */ 1501 U16 NumberOfDevices; /* 0x14 */ 1502 U16 UEFIVersion; /* 0x16 */ 1503 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */ 1504 U16 IOTimeoutSequential; /* 0x1A */ 1505 U16 IOTimeoutOther; /* 0x1C */ 1506 U16 IOTimeoutBlockDevicesRM; /* 0x1E */ 1507 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1, 1508 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t; 1509 1510 #define MPI2_BIOSPAGE1_PAGEVERSION (0x07) 1511 1512 /* values for BIOS Page 1 BiosOptions field */ 1513 #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE (0x00008000) 1514 #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000) 1515 1516 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) 1517 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000) 1518 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800) 1519 #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000) 1520 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800) 1521 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000) 1522 1523 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400) 1524 1525 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300) 1526 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000) 1527 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100) 1528 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200) 1529 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300) 1530 1531 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0) 1532 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000) 1533 1534 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) 1535 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) 1536 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) 1537 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) 1538 1539 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1540 1541 /* values for BIOS Page 1 IOCSettings field */ 1542 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1543 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1544 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1545 1546 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1547 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1548 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1549 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1550 1551 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1552 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1553 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1554 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1555 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1556 1557 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1558 1559 /* values for BIOS Page 1 DeviceSettings field */ 1560 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1561 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1562 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1563 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1564 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1565 1566 /* defines for BIOS Page 1 UEFIVersion field */ 1567 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00) 1568 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8) 1569 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF) 1570 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0) 1571 1572 /* BIOS Page 2 */ 1573 1574 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER 1575 { 1576 U32 Reserved1; /* 0x00 */ 1577 U32 Reserved2; /* 0x04 */ 1578 U32 Reserved3; /* 0x08 */ 1579 U32 Reserved4; /* 0x0C */ 1580 U32 Reserved5; /* 0x10 */ 1581 U32 Reserved6; /* 0x14 */ 1582 } MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1583 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1584 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t; 1585 1586 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID 1587 { 1588 U64 SASAddress; /* 0x00 */ 1589 U8 LUN[8]; /* 0x08 */ 1590 U32 Reserved1; /* 0x10 */ 1591 U32 Reserved2; /* 0x14 */ 1592 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1593 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t; 1594 1595 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT 1596 { 1597 U64 EnclosureLogicalID; /* 0x00 */ 1598 U32 Reserved1; /* 0x08 */ 1599 U32 Reserved2; /* 0x0C */ 1600 U16 SlotNumber; /* 0x10 */ 1601 U16 Reserved3; /* 0x12 */ 1602 U32 Reserved4; /* 0x14 */ 1603 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1604 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1605 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t; 1606 1607 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME 1608 { 1609 U64 DeviceName; /* 0x00 */ 1610 U8 LUN[8]; /* 0x08 */ 1611 U32 Reserved1; /* 0x10 */ 1612 U32 Reserved2; /* 0x14 */ 1613 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1614 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t; 1615 1616 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE 1617 { 1618 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1619 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1620 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1621 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1622 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1623 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t; 1624 1625 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 1626 { 1627 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1628 U32 Reserved1; /* 0x04 */ 1629 U32 Reserved2; /* 0x08 */ 1630 U32 Reserved3; /* 0x0C */ 1631 U32 Reserved4; /* 0x10 */ 1632 U32 Reserved5; /* 0x14 */ 1633 U32 Reserved6; /* 0x18 */ 1634 U8 ReqBootDeviceForm; /* 0x1C */ 1635 U8 Reserved7; /* 0x1D */ 1636 U16 Reserved8; /* 0x1E */ 1637 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */ 1638 U8 ReqAltBootDeviceForm; /* 0x38 */ 1639 U8 Reserved9; /* 0x39 */ 1640 U16 Reserved10; /* 0x3A */ 1641 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */ 1642 U8 CurrentBootDeviceForm; /* 0x58 */ 1643 U8 Reserved11; /* 0x59 */ 1644 U16 Reserved12; /* 0x5A */ 1645 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */ 1646 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2, 1647 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t; 1648 1649 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1650 1651 /* values for BIOS Page 2 BootDeviceForm fields */ 1652 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1653 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1654 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1655 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1656 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1657 1658 /* BIOS Page 3 */ 1659 1660 #define MPI2_BIOSPAGE3_NUM_ADAPTER (4) 1661 1662 typedef struct _MPI2_ADAPTER_INFO 1663 { 1664 U8 PciBusNumber; /* 0x00 */ 1665 U8 PciDeviceAndFunctionNumber; /* 0x01 */ 1666 U16 AdapterFlags; /* 0x02 */ 1667 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO, 1668 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t; 1669 1670 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1671 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1672 1673 typedef struct _MPI2_ADAPTER_ORDER_AUX 1674 { 1675 U64 WWID; /* 0x00 */ 1676 U32 Reserved1; /* 0x08 */ 1677 U32 Reserved2; /* 0x0C */ 1678 } MPI2_ADAPTER_ORDER_AUX, MPI2_POINTER PTR_MPI2_ADAPTER_ORDER_AUX, 1679 Mpi2AdapterOrderAux_t, MPI2_POINTER pMpi2AdapterOrderAux_t; 1680 1681 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 1682 { 1683 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1684 U32 GlobalFlags; /* 0x04 */ 1685 U32 BiosVersion; /* 0x08 */ 1686 MPI2_ADAPTER_INFO AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x0C */ 1687 U32 Reserved1; /* 0x1C */ 1688 MPI2_ADAPTER_ORDER_AUX AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x20 */ /* MPI v2.5 and newer */ 1689 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3, 1690 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t; 1691 1692 #define MPI2_BIOSPAGE3_PAGEVERSION (0x01) 1693 1694 /* values for BIOS Page 3 GlobalFlags */ 1695 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1696 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1697 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1698 1699 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1700 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1701 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1702 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1703 1704 /* BIOS Page 4 */ 1705 1706 /* 1707 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1708 * one and check the value returned for NumPhys at runtime. 1709 */ 1710 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1711 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1712 #endif 1713 1714 typedef struct _MPI2_BIOS4_ENTRY 1715 { 1716 U64 ReassignmentWWID; /* 0x00 */ 1717 U64 ReassignmentDeviceName; /* 0x08 */ 1718 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY, 1719 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t; 1720 1721 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 1722 { 1723 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1724 U8 NumPhys; /* 0x04 */ 1725 U8 Reserved1; /* 0x05 */ 1726 U16 Reserved2; /* 0x06 */ 1727 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */ 1728 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4, 1729 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t; 1730 1731 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1732 1733 /**************************************************************************** 1734 * RAID Volume Config Pages 1735 ****************************************************************************/ 1736 1737 /* RAID Volume Page 0 */ 1738 1739 typedef struct _MPI2_RAIDVOL0_PHYS_DISK 1740 { 1741 U8 RAIDSetNum; /* 0x00 */ 1742 U8 PhysDiskMap; /* 0x01 */ 1743 U8 PhysDiskNum; /* 0x02 */ 1744 U8 Reserved; /* 0x03 */ 1745 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK, 1746 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t; 1747 1748 /* defines for the PhysDiskMap field */ 1749 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1750 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1751 1752 typedef struct _MPI2_RAIDVOL0_SETTINGS 1753 { 1754 U16 Settings; /* 0x00 */ 1755 U8 HotSparePool; /* 0x01 */ 1756 U8 Reserved; /* 0x02 */ 1757 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS, 1758 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t; 1759 1760 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1761 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1762 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1763 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1764 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1765 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1766 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1767 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1768 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1769 1770 /* RAID Volume Page 0 VolumeSettings defines */ 1771 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1772 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1773 1774 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1775 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1776 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1777 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1778 1779 /* 1780 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1781 * one and check the value returned for NumPhysDisks at runtime. 1782 */ 1783 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1784 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1785 #endif 1786 1787 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 1788 { 1789 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1790 U16 DevHandle; /* 0x04 */ 1791 U8 VolumeState; /* 0x06 */ 1792 U8 VolumeType; /* 0x07 */ 1793 U32 VolumeStatusFlags; /* 0x08 */ 1794 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */ 1795 U64 MaxLBA; /* 0x10 */ 1796 U32 StripeSize; /* 0x18 */ 1797 U16 BlockSize; /* 0x1C */ 1798 U16 Reserved1; /* 0x1E */ 1799 U8 SupportedPhysDisks; /* 0x20 */ 1800 U8 ResyncRate; /* 0x21 */ 1801 U16 DataScrubDuration; /* 0x22 */ 1802 U8 NumPhysDisks; /* 0x24 */ 1803 U8 Reserved2; /* 0x25 */ 1804 U8 Reserved3; /* 0x26 */ 1805 U8 InactiveStatus; /* 0x27 */ 1806 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */ 1807 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1808 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t; 1809 1810 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1811 1812 /* values for RAID VolumeState */ 1813 #define MPI2_RAID_VOL_STATE_MISSING (0x00) 1814 #define MPI2_RAID_VOL_STATE_FAILED (0x01) 1815 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1816 #define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1817 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1818 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1819 1820 /* values for RAID VolumeType */ 1821 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1822 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1823 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1824 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1825 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1826 1827 /* values for RAID Volume Page 0 VolumeStatusFlags field */ 1828 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1829 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1830 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1831 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1832 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1833 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1834 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1835 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1836 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1837 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1838 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1839 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1840 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1841 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1842 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1843 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1844 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1845 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1846 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1847 1848 /* values for RAID Volume Page 0 SupportedPhysDisks field */ 1849 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1850 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1851 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1852 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1853 1854 /* values for RAID Volume Page 0 InactiveStatus field */ 1855 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1856 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1857 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1858 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1859 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1860 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1861 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1862 1863 /* RAID Volume Page 1 */ 1864 1865 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 1866 { 1867 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1868 U16 DevHandle; /* 0x04 */ 1869 U16 Reserved0; /* 0x06 */ 1870 U8 GUID[24]; /* 0x08 */ 1871 U8 Name[16]; /* 0x20 */ 1872 U64 WWID; /* 0x30 */ 1873 U32 Reserved1; /* 0x38 */ 1874 U32 Reserved2; /* 0x3C */ 1875 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1876 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t; 1877 1878 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1879 1880 /**************************************************************************** 1881 * RAID Physical Disk Config Pages 1882 ****************************************************************************/ 1883 1884 /* RAID Physical Disk Page 0 */ 1885 1886 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS 1887 { 1888 U16 Reserved1; /* 0x00 */ 1889 U8 HotSparePool; /* 0x02 */ 1890 U8 Reserved2; /* 0x03 */ 1891 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1892 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t; 1893 1894 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1895 1896 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA 1897 { 1898 U8 VendorID[8]; /* 0x00 */ 1899 U8 ProductID[16]; /* 0x08 */ 1900 U8 ProductRevLevel[4]; /* 0x18 */ 1901 U8 SerialNum[32]; /* 0x1C */ 1902 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1903 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1904 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t; 1905 1906 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 1907 { 1908 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1909 U16 DevHandle; /* 0x04 */ 1910 U8 Reserved1; /* 0x06 */ 1911 U8 PhysDiskNum; /* 0x07 */ 1912 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */ 1913 U32 Reserved2; /* 0x0C */ 1914 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */ 1915 U32 Reserved3; /* 0x4C */ 1916 U8 PhysDiskState; /* 0x50 */ 1917 U8 OfflineReason; /* 0x51 */ 1918 U8 IncompatibleReason; /* 0x52 */ 1919 U8 PhysDiskAttributes; /* 0x53 */ 1920 U32 PhysDiskStatusFlags; /* 0x54 */ 1921 U64 DeviceMaxLBA; /* 0x58 */ 1922 U64 HostMaxLBA; /* 0x60 */ 1923 U64 CoercedMaxLBA; /* 0x68 */ 1924 U16 BlockSize; /* 0x70 */ 1925 U16 Reserved5; /* 0x72 */ 1926 U32 Reserved6; /* 0x74 */ 1927 } MPI2_CONFIG_PAGE_RD_PDISK_0, 1928 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1929 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t; 1930 1931 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1932 1933 /* PhysDiskState defines */ 1934 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1935 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1936 #define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1937 #define MPI2_RAID_PD_STATE_ONLINE (0x03) 1938 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1939 #define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1940 #define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1941 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1942 1943 /* OfflineReason defines */ 1944 #define MPI2_PHYSDISK0_ONLINE (0x00) 1945 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 1946 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 1947 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 1948 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 1949 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 1950 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 1951 1952 /* IncompatibleReason defines */ 1953 #define MPI2_PHYSDISK0_COMPATIBLE (0x00) 1954 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 1955 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 1956 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 1957 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 1958 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 1959 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 1960 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 1961 1962 /* PhysDiskAttributes defines */ 1963 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 1964 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 1965 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 1966 1967 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 1968 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 1969 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 1970 1971 /* PhysDiskStatusFlags defines */ 1972 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 1973 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 1974 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 1975 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 1976 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 1977 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 1978 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 1979 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 1980 1981 /* RAID Physical Disk Page 1 */ 1982 1983 /* 1984 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1985 * one and check the value returned for NumPhysDiskPaths at runtime. 1986 */ 1987 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 1988 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 1989 #endif 1990 1991 typedef struct _MPI2_RAIDPHYSDISK1_PATH 1992 { 1993 U16 DevHandle; /* 0x00 */ 1994 U16 Reserved1; /* 0x02 */ 1995 U64 WWID; /* 0x04 */ 1996 U64 OwnerWWID; /* 0x0C */ 1997 U8 OwnerIdentifier; /* 0x14 */ 1998 U8 Reserved2; /* 0x15 */ 1999 U16 Flags; /* 0x16 */ 2000 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH, 2001 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t; 2002 2003 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 2004 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 2005 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 2006 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 2007 2008 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 2009 { 2010 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2011 U8 NumPhysDiskPaths; /* 0x04 */ 2012 U8 PhysDiskNum; /* 0x05 */ 2013 U16 Reserved1; /* 0x06 */ 2014 U32 Reserved2; /* 0x08 */ 2015 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */ 2016 } MPI2_CONFIG_PAGE_RD_PDISK_1, 2017 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 2018 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t; 2019 2020 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 2021 2022 /**************************************************************************** 2023 * values for fields used by several types of SAS Config Pages 2024 ****************************************************************************/ 2025 2026 /* values for NegotiatedLinkRates fields */ 2027 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 2028 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 2029 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 2030 /* link rates used for Negotiated Physical and Logical Link Rate */ 2031 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 2032 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 2033 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 2034 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 2035 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 2036 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 2037 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 2038 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 2039 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 2040 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 2041 #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B) 2042 #define MPI26_SAS_NEG_LINK_RATE_22_5 (0x0C) 2043 2044 /* values for AttachedPhyInfo fields */ 2045 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 2046 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 2047 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 2048 2049 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 2050 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 2051 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 2052 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 2053 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 2054 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 2055 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 2056 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 2057 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 2058 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 2059 2060 /* values for PhyInfo fields */ 2061 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 2062 2063 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 2064 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 2065 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 2066 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 2067 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 2068 2069 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 2070 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 2071 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 2072 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 2073 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 2074 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 2075 2076 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 2077 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 2078 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 2079 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 2080 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 2081 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 2082 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 2083 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 2084 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 2085 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 2086 2087 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 2088 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 2089 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 2090 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 2091 2092 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 2093 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 2094 2095 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 2096 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 2097 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 2098 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 2099 2100 /* values for SAS ProgrammedLinkRate fields */ 2101 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 2102 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 2103 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 2104 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 2105 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 2106 #define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0) 2107 #define MPI26_SAS_PRATE_MAX_RATE_22_5 (0xC0) 2108 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 2109 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 2110 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 2111 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 2112 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 2113 #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B) 2114 #define MPI26_SAS_PRATE_MIN_RATE_22_5 (0x0C) 2115 2116 /* values for SAS HwLinkRate fields */ 2117 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 2118 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 2119 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 2120 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 2121 #define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0) 2122 #define MPI26_SAS_HWRATE_MAX_RATE_22_5 (0xC0) 2123 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 2124 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 2125 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 2126 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 2127 #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B) 2128 #define MPI26_SAS_HWRATE_MIN_RATE_22_5 (0x0C) 2129 2130 /**************************************************************************** 2131 * SAS IO Unit Config Pages 2132 ****************************************************************************/ 2133 2134 /* SAS IO Unit Page 0 */ 2135 2136 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA 2137 { 2138 U8 Port; /* 0x00 */ 2139 U8 PortFlags; /* 0x01 */ 2140 U8 PhyFlags; /* 0x02 */ 2141 U8 NegotiatedLinkRate; /* 0x03 */ 2142 U32 ControllerPhyDeviceInfo;/* 0x04 */ 2143 U16 AttachedDevHandle; /* 0x08 */ 2144 U16 ControllerDevHandle; /* 0x0A */ 2145 U32 DiscoveryStatus; /* 0x0C */ 2146 U32 Reserved; /* 0x10 */ 2147 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 2148 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t; 2149 2150 /* 2151 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2152 * one and check the value returned for NumPhys at runtime. 2153 */ 2154 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX 2155 #define MPI2_SAS_IOUNIT0_PHY_MAX (1) 2156 #endif 2157 2158 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 2159 { 2160 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2161 U32 Reserved1; /* 0x08 */ 2162 U8 NumPhys; /* 0x0C */ 2163 U8 Reserved2; /* 0x0D */ 2164 U16 Reserved3; /* 0x0E */ 2165 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */ 2166 } MPI2_CONFIG_PAGE_SASIOUNIT_0, 2167 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 2168 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t; 2169 2170 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 2171 2172 /* values for SAS IO Unit Page 0 PortFlags */ 2173 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 2174 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 2175 2176 /* values for SAS IO Unit Page 0 PhyFlags */ 2177 #define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2178 #define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2179 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 2180 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 2181 2182 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2183 2184 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 2185 2186 /* values for SAS IO Unit Page 0 DiscoveryStatus */ 2187 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2188 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2189 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 2190 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2191 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2192 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2193 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2194 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 2195 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2196 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2197 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 2198 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2199 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2200 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2201 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2202 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2203 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2204 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2205 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2206 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 2207 2208 /* SAS IO Unit Page 1 */ 2209 2210 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA 2211 { 2212 U8 Port; /* 0x00 */ 2213 U8 PortFlags; /* 0x01 */ 2214 U8 PhyFlags; /* 0x02 */ 2215 U8 MaxMinLinkRate; /* 0x03 */ 2216 U32 ControllerPhyDeviceInfo; /* 0x04 */ 2217 U16 MaxTargetPortConnectTime; /* 0x08 */ 2218 U16 Reserved1; /* 0x0A */ 2219 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 2220 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t; 2221 2222 /* 2223 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2224 * one and check the value returned for NumPhys at runtime. 2225 */ 2226 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX 2227 #define MPI2_SAS_IOUNIT1_PHY_MAX (1) 2228 #endif 2229 2230 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 2231 { 2232 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2233 U16 ControlFlags; /* 0x08 */ 2234 U16 SASNarrowMaxQueueDepth; /* 0x0A */ 2235 U16 AdditionalControlFlags; /* 0x0C */ 2236 U16 SASWideMaxQueueDepth; /* 0x0E */ 2237 U8 NumPhys; /* 0x10 */ 2238 U8 SATAMaxQDepth; /* 0x11 */ 2239 U8 ReportDeviceMissingDelay; /* 0x12 */ 2240 U8 IODeviceMissingDelay; /* 0x13 */ 2241 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */ 2242 } MPI2_CONFIG_PAGE_SASIOUNIT_1, 2243 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 2244 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t; 2245 2246 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 2247 2248 /* values for SAS IO Unit Page 1 ControlFlags */ 2249 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2250 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2251 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */ 2252 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2253 2254 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2255 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2256 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 2257 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 2258 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 2259 2260 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2261 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2262 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2263 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2264 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 2265 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2266 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2267 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */ 2268 2269 /* values for SAS IO Unit Page 1 AdditionalControlFlags */ 2270 #define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 2271 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2272 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2273 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 2274 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2275 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2276 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2277 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2278 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2279 2280 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2281 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2282 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2283 2284 /* values for SAS IO Unit Page 1 PortFlags */ 2285 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2286 2287 /* values for SAS IO Unit Page 1 PhyFlags */ 2288 #define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2289 #define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2290 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 2291 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2292 2293 /* values for SAS IO Unit Page 1 MaxMinLinkRate */ 2294 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 2295 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 2296 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 2297 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 2298 #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0) 2299 #define MPI26_SASIOUNIT1_MAX_RATE_22_5 (0xC0) 2300 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 2301 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 2302 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 2303 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 2304 #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B) 2305 #define MPI26_SASIOUNIT1_MIN_RATE_22_5 (0x0C) 2306 2307 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2308 2309 /* SAS IO Unit Page 4 (for MPI v2.5 and earlier) */ 2310 2311 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP 2312 { 2313 U8 MaxTargetSpinup; /* 0x00 */ 2314 U8 SpinupDelay; /* 0x01 */ 2315 U8 SpinupFlags; /* 0x02 */ 2316 U8 Reserved1; /* 0x03 */ 2317 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2318 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t; 2319 2320 /* defines for SAS IO Unit Page 4 SpinupFlags */ 2321 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01) 2322 2323 /* 2324 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2325 * one and check the value returned for NumPhys at runtime. 2326 */ 2327 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX 2328 #define MPI2_SAS_IOUNIT4_PHY_MAX (4) 2329 #endif 2330 2331 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 2332 { 2333 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2334 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 2335 U32 Reserved1; /* 0x18 */ 2336 U32 Reserved2; /* 0x1C */ 2337 U32 Reserved3; /* 0x20 */ 2338 U8 BootDeviceWaitTime; /* 0x24 */ 2339 U8 SATADeviceWaitTime; /* 0x25 */ 2340 U16 Reserved5; /* 0x26 */ 2341 U8 NumPhys; /* 0x28 */ 2342 U8 PEInitialSpinupDelay; /* 0x29 */ 2343 U8 PEReplyDelay; /* 0x2A */ 2344 U8 Flags; /* 0x2B */ 2345 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */ 2346 } MPI2_CONFIG_PAGE_SASIOUNIT_4, 2347 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 2348 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t; 2349 2350 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 2351 2352 /* defines for Flags field */ 2353 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 2354 2355 /* defines for PHY field */ 2356 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 2357 2358 /* SAS IO Unit Page 5 */ 2359 2360 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 2361 { 2362 U8 ControlFlags; /* 0x00 */ 2363 U8 PortWidthModGroup; /* 0x01 */ 2364 U16 InactivityTimerExponent; /* 0x02 */ 2365 U8 SATAPartialTimeout; /* 0x04 */ 2366 U8 Reserved2; /* 0x05 */ 2367 U8 SATASlumberTimeout; /* 0x06 */ 2368 U8 Reserved3; /* 0x07 */ 2369 U8 SASPartialTimeout; /* 0x08 */ 2370 U8 Reserved4; /* 0x09 */ 2371 U8 SASSlumberTimeout; /* 0x0A */ 2372 U8 Reserved5; /* 0x0B */ 2373 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2374 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2375 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t; 2376 2377 /* defines for ControlFlags field */ 2378 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 2379 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 2380 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 2381 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 2382 2383 /* defines for PortWidthModeGroup field */ 2384 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 2385 2386 /* defines for InactivityTimerExponent field */ 2387 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 2388 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 2389 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 2390 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 2391 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 2392 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 2393 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 2394 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 2395 2396 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 2397 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 2398 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 2399 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 2400 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 2401 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 2402 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 2403 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 2404 2405 /* 2406 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2407 * one and check the value returned for NumPhys at runtime. 2408 */ 2409 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX 2410 #define MPI2_SAS_IOUNIT5_PHY_MAX (1) 2411 #endif 2412 2413 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 2414 { 2415 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2416 U8 NumPhys; /* 0x08 */ 2417 U8 Reserved1; /* 0x09 */ 2418 U16 Reserved2; /* 0x0A */ 2419 U32 Reserved3; /* 0x0C */ 2420 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */ 2421 } MPI2_CONFIG_PAGE_SASIOUNIT_5, 2422 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 2423 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t; 2424 2425 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 2426 2427 /* SAS IO Unit Page 6 */ 2428 2429 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2430 { 2431 U8 CurrentStatus; /* 0x00 */ 2432 U8 CurrentModulation; /* 0x01 */ 2433 U8 CurrentUtilization; /* 0x02 */ 2434 U8 Reserved1; /* 0x03 */ 2435 U32 Reserved2; /* 0x04 */ 2436 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2437 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2438 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 2439 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t; 2440 2441 /* defines for CurrentStatus field */ 2442 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 2443 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 2444 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 2445 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 2446 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 2447 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 2448 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 2449 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 2450 2451 /* defines for CurrentModulation field */ 2452 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 2453 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 2454 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 2455 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 2456 2457 /* 2458 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2459 * one and check the value returned for NumGroups at runtime. 2460 */ 2461 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 2462 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 2463 #endif 2464 2465 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 2466 { 2467 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2468 U32 Reserved1; /* 0x08 */ 2469 U32 Reserved2; /* 0x0C */ 2470 U8 NumGroups; /* 0x10 */ 2471 U8 Reserved3; /* 0x11 */ 2472 U16 Reserved4; /* 0x12 */ 2473 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2474 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */ 2475 } MPI2_CONFIG_PAGE_SASIOUNIT_6, 2476 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 2477 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t; 2478 2479 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 2480 2481 /* SAS IO Unit Page 7 */ 2482 2483 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2484 { 2485 U8 Flags; /* 0x00 */ 2486 U8 Reserved1; /* 0x01 */ 2487 U16 Reserved2; /* 0x02 */ 2488 U8 Threshold75Pct; /* 0x04 */ 2489 U8 Threshold50Pct; /* 0x05 */ 2490 U8 Threshold25Pct; /* 0x06 */ 2491 U8 Reserved3; /* 0x07 */ 2492 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2493 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2494 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2495 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2496 2497 /* defines for Flags field */ 2498 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2499 2500 /* 2501 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2502 * one and check the value returned for NumGroups at runtime. 2503 */ 2504 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2505 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2506 #endif 2507 2508 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 2509 { 2510 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2511 U8 SamplingInterval; /* 0x08 */ 2512 U8 WindowLength; /* 0x09 */ 2513 U16 Reserved1; /* 0x0A */ 2514 U32 Reserved2; /* 0x0C */ 2515 U32 Reserved3; /* 0x10 */ 2516 U8 NumGroups; /* 0x14 */ 2517 U8 Reserved4; /* 0x15 */ 2518 U16 Reserved5; /* 0x16 */ 2519 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2520 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */ 2521 } MPI2_CONFIG_PAGE_SASIOUNIT_7, 2522 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2523 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t; 2524 2525 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2526 2527 /* SAS IO Unit Page 8 */ 2528 2529 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 2530 { 2531 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2532 U32 Reserved1; /* 0x08 */ 2533 U32 PowerManagementCapabilities; /* 0x0C */ 2534 U8 TxRxSleepStatus; /* 0x10 */ /* reserved in MPI 2.0 */ 2535 U8 Reserved2; /* 0x11 */ 2536 U16 Reserved3; /* 0x12 */ 2537 } MPI2_CONFIG_PAGE_SASIOUNIT_8, 2538 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2539 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t; 2540 2541 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2542 2543 /* defines for PowerManagementCapabilities field */ 2544 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000) 2545 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 2546 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 2547 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 2548 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 2549 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010) 2550 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 2551 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 2552 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 2553 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 2554 2555 /* defines for TxRxSleepStatus field */ 2556 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00) 2557 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01) 2558 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02) 2559 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03) 2560 2561 /* SAS IO Unit Page 16 */ 2562 2563 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 2564 { 2565 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2566 U64 TimeStamp; /* 0x08 */ 2567 U32 Reserved1; /* 0x10 */ 2568 U32 Reserved2; /* 0x14 */ 2569 U32 FastPathPendedRequests; /* 0x18 */ 2570 U32 FastPathUnPendedRequests; /* 0x1C */ 2571 U32 FastPathHostRequestStarts; /* 0x20 */ 2572 U32 FastPathFirmwareRequestStarts; /* 0x24 */ 2573 U32 FastPathHostCompletions; /* 0x28 */ 2574 U32 FastPathFirmwareCompletions; /* 0x2C */ 2575 U32 NonFastPathRequestStarts; /* 0x30 */ 2576 U32 NonFastPathHostCompletions; /* 0x30 */ 2577 } MPI2_CONFIG_PAGE_SASIOUNIT16, 2578 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT16, 2579 Mpi2SasIOUnitPage16_t, MPI2_POINTER pMpi2SasIOUnitPage16_t; 2580 2581 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00) 2582 2583 /**************************************************************************** 2584 * SAS Expander Config Pages 2585 ****************************************************************************/ 2586 2587 /* SAS Expander Page 0 */ 2588 2589 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 2590 { 2591 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2592 U8 PhysicalPort; /* 0x08 */ 2593 U8 ReportGenLength; /* 0x09 */ 2594 U16 EnclosureHandle; /* 0x0A */ 2595 U64 SASAddress; /* 0x0C */ 2596 U32 DiscoveryStatus; /* 0x14 */ 2597 U16 DevHandle; /* 0x18 */ 2598 U16 ParentDevHandle; /* 0x1A */ 2599 U16 ExpanderChangeCount; /* 0x1C */ 2600 U16 ExpanderRouteIndexes; /* 0x1E */ 2601 U8 NumPhys; /* 0x20 */ 2602 U8 SASLevel; /* 0x21 */ 2603 U16 Flags; /* 0x22 */ 2604 U16 STPBusInactivityTimeLimit; /* 0x24 */ 2605 U16 STPMaxConnectTimeLimit; /* 0x26 */ 2606 U16 STP_SMP_NexusLossTime; /* 0x28 */ 2607 U16 MaxNumRoutedSasAddresses; /* 0x2A */ 2608 U64 ActiveZoneManagerSASAddress;/* 0x2C */ 2609 U16 ZoneLockInactivityLimit; /* 0x34 */ 2610 U16 Reserved1; /* 0x36 */ 2611 U8 TimeToReducedFunc; /* 0x38 */ 2612 U8 InitialTimeToReducedFunc; /* 0x39 */ 2613 U8 MaxReducedFuncTime; /* 0x3A */ 2614 U8 Reserved2; /* 0x3B */ 2615 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2616 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t; 2617 2618 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2619 2620 /* values for SAS Expander Page 0 DiscoveryStatus field */ 2621 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2622 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2623 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2624 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2625 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2626 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2627 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2628 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2629 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2630 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2631 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2632 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2633 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2634 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2635 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2636 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2637 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2638 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2639 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2640 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2641 2642 /* values for SAS Expander Page 0 Flags field */ 2643 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2644 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2645 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2646 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2647 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2648 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2649 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2650 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2651 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2652 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2653 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2654 2655 /* SAS Expander Page 1 */ 2656 2657 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 2658 { 2659 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2660 U8 PhysicalPort; /* 0x08 */ 2661 U8 Reserved1; /* 0x09 */ 2662 U16 Reserved2; /* 0x0A */ 2663 U8 NumPhys; /* 0x0C */ 2664 U8 Phy; /* 0x0D */ 2665 U16 NumTableEntriesProgrammed; /* 0x0E */ 2666 U8 ProgrammedLinkRate; /* 0x10 */ 2667 U8 HwLinkRate; /* 0x11 */ 2668 U16 AttachedDevHandle; /* 0x12 */ 2669 U32 PhyInfo; /* 0x14 */ 2670 U32 AttachedDeviceInfo; /* 0x18 */ 2671 U16 ExpanderDevHandle; /* 0x1C */ 2672 U8 ChangeCount; /* 0x1E */ 2673 U8 NegotiatedLinkRate; /* 0x1F */ 2674 U8 PhyIdentifier; /* 0x20 */ 2675 U8 AttachedPhyIdentifier; /* 0x21 */ 2676 U8 Reserved3; /* 0x22 */ 2677 U8 DiscoveryInfo; /* 0x23 */ 2678 U32 AttachedPhyInfo; /* 0x24 */ 2679 U8 ZoneGroup; /* 0x28 */ 2680 U8 SelfConfigStatus; /* 0x29 */ 2681 U16 Reserved4; /* 0x2A */ 2682 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2683 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t; 2684 2685 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2686 2687 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2688 2689 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2690 2691 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2692 2693 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */ 2694 2695 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2696 2697 /* values for SAS Expander Page 1 DiscoveryInfo field */ 2698 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2699 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2700 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2701 2702 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2703 2704 /**************************************************************************** 2705 * SAS Device Config Pages 2706 ****************************************************************************/ 2707 2708 /* SAS Device Page 0 */ 2709 2710 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 2711 { 2712 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2713 U16 Slot; /* 0x08 */ 2714 U16 EnclosureHandle; /* 0x0A */ 2715 U64 SASAddress; /* 0x0C */ 2716 U16 ParentDevHandle; /* 0x14 */ 2717 U8 PhyNum; /* 0x16 */ 2718 U8 AccessStatus; /* 0x17 */ 2719 U16 DevHandle; /* 0x18 */ 2720 U8 AttachedPhyIdentifier; /* 0x1A */ 2721 U8 ZoneGroup; /* 0x1B */ 2722 U32 DeviceInfo; /* 0x1C */ 2723 U16 Flags; /* 0x20 */ 2724 U8 PhysicalPort; /* 0x22 */ 2725 U8 MaxPortConnections; /* 0x23 */ 2726 U64 DeviceName; /* 0x24 */ 2727 U8 PortGroups; /* 0x2C */ 2728 U8 DmaGroup; /* 0x2D */ 2729 U8 ControlGroup; /* 0x2E */ 2730 U8 EnclosureLevel; /* 0x2F */ 2731 U8 ConnectorName[4]; /* 0x30 */ 2732 U32 Reserved3; /* 0x34 */ 2733 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2734 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t; 2735 2736 #define MPI2_SASDEVICE0_PAGEVERSION (0x09) 2737 2738 /* values for SAS Device Page 0 AccessStatus field */ 2739 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2740 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2741 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2742 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2743 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2744 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2745 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2746 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2747 /* specific values for SATA Init failures */ 2748 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2749 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2750 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2751 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2752 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2753 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2754 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2755 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2756 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2757 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2758 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2759 2760 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2761 2762 /* values for SAS Device Page 0 Flags field */ 2763 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 2764 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000) 2765 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000) 2766 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2767 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2768 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2769 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2770 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2771 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2772 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2773 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2774 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2775 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2776 #define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE (0x0004) 2777 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002) 2778 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2779 2780 /* SAS Device Page 1 */ 2781 2782 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 2783 { 2784 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2785 U32 Reserved1; /* 0x08 */ 2786 U64 SASAddress; /* 0x0C */ 2787 U32 Reserved2; /* 0x14 */ 2788 U16 DevHandle; /* 0x18 */ 2789 U16 Reserved3; /* 0x1A */ 2790 U8 InitialRegDeviceFIS[20];/* 0x1C */ 2791 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2792 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t; 2793 2794 #define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2795 2796 /**************************************************************************** 2797 * SAS PHY Config Pages 2798 ****************************************************************************/ 2799 2800 /* SAS PHY Page 0 */ 2801 2802 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 2803 { 2804 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2805 U16 OwnerDevHandle; /* 0x08 */ 2806 U16 Reserved1; /* 0x0A */ 2807 U16 AttachedDevHandle; /* 0x0C */ 2808 U8 AttachedPhyIdentifier; /* 0x0E */ 2809 U8 Reserved2; /* 0x0F */ 2810 U32 AttachedPhyInfo; /* 0x10 */ 2811 U8 ProgrammedLinkRate; /* 0x14 */ 2812 U8 HwLinkRate; /* 0x15 */ 2813 U8 ChangeCount; /* 0x16 */ 2814 U8 Flags; /* 0x17 */ 2815 U32 PhyInfo; /* 0x18 */ 2816 U8 NegotiatedLinkRate; /* 0x1C */ 2817 U8 Reserved3; /* 0x1D */ 2818 U16 Reserved4; /* 0x1E */ 2819 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2820 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t; 2821 2822 #define MPI2_SASPHY0_PAGEVERSION (0x03) 2823 2824 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2825 2826 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2827 2828 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2829 2830 /* values for SAS PHY Page 0 Flags field */ 2831 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2832 2833 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2834 2835 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2836 2837 /* SAS PHY Page 1 */ 2838 2839 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 2840 { 2841 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2842 U32 Reserved1; /* 0x08 */ 2843 U32 InvalidDwordCount; /* 0x0C */ 2844 U32 RunningDisparityErrorCount; /* 0x10 */ 2845 U32 LossDwordSynchCount; /* 0x14 */ 2846 U32 PhyResetProblemCount; /* 0x18 */ 2847 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 2848 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t; 2849 2850 #define MPI2_SASPHY1_PAGEVERSION (0x01) 2851 2852 /* SAS PHY Page 2 */ 2853 2854 typedef struct _MPI2_SASPHY2_PHY_EVENT 2855 { 2856 U8 PhyEventCode; /* 0x00 */ 2857 U8 Reserved1; /* 0x01 */ 2858 U16 Reserved2; /* 0x02 */ 2859 U32 PhyEventInfo; /* 0x04 */ 2860 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT, 2861 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t; 2862 2863 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 2864 2865 /* 2866 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2867 * one and check the value returned for NumPhyEvents at runtime. 2868 */ 2869 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX 2870 #define MPI2_SASPHY2_PHY_EVENT_MAX (1) 2871 #endif 2872 2873 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 2874 { 2875 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2876 U32 Reserved1; /* 0x08 */ 2877 U8 NumPhyEvents; /* 0x0C */ 2878 U8 Reserved2; /* 0x0D */ 2879 U16 Reserved3; /* 0x0E */ 2880 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */ 2881 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 2882 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t; 2883 2884 #define MPI2_SASPHY2_PAGEVERSION (0x00) 2885 2886 /* SAS PHY Page 3 */ 2887 2888 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG 2889 { 2890 U8 PhyEventCode; /* 0x00 */ 2891 U8 Reserved1; /* 0x01 */ 2892 U16 Reserved2; /* 0x02 */ 2893 U8 CounterType; /* 0x04 */ 2894 U8 ThresholdWindow; /* 0x05 */ 2895 U8 TimeUnits; /* 0x06 */ 2896 U8 Reserved3; /* 0x07 */ 2897 U32 EventThreshold; /* 0x08 */ 2898 U16 ThresholdFlags; /* 0x0C */ 2899 U16 Reserved4; /* 0x0E */ 2900 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 2901 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t; 2902 2903 /* values for PhyEventCode field */ 2904 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2905 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2906 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2907 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2908 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2909 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 2910 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 2911 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 2912 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 2913 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 2914 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 2915 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 2916 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 2917 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 2918 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 2919 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 2920 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 2921 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 2922 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 2923 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 2924 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 2925 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 2926 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 2927 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 2928 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 2929 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 2930 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 2931 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 2932 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 2933 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 2934 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 2935 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 2936 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 2937 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 2938 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 2939 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 2940 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 2941 /* Following codes are product specific and in MPI v2.6 and later */ 2942 #define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3) 2943 #define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4) 2944 #define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5) 2945 #define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6) 2946 #define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7) 2947 #define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8) 2948 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9) 2949 #define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA) 2950 #define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB) 2951 #define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC) 2952 2953 /* values for the CounterType field */ 2954 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 2955 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 2956 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 2957 2958 /* values for the TimeUnits field */ 2959 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 2960 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 2961 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 2962 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 2963 2964 /* values for the ThresholdFlags field */ 2965 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 2966 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 2967 2968 /* 2969 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2970 * one and check the value returned for NumPhyEvents at runtime. 2971 */ 2972 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX 2973 #define MPI2_SASPHY3_PHY_EVENT_MAX (1) 2974 #endif 2975 2976 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 2977 { 2978 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2979 U32 Reserved1; /* 0x08 */ 2980 U8 NumPhyEvents; /* 0x0C */ 2981 U8 Reserved2; /* 0x0D */ 2982 U16 Reserved3; /* 0x0E */ 2983 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */ 2984 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 2985 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t; 2986 2987 #define MPI2_SASPHY3_PAGEVERSION (0x00) 2988 2989 /* SAS PHY Page 4 */ 2990 2991 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 2992 { 2993 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2994 U16 Reserved1; /* 0x08 */ 2995 U8 Reserved2; /* 0x0A */ 2996 U8 Flags; /* 0x0B */ 2997 U8 InitialFrame[28]; /* 0x0C */ 2998 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 2999 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t; 3000 3001 #define MPI2_SASPHY4_PAGEVERSION (0x00) 3002 3003 /* values for the Flags field */ 3004 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 3005 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 3006 3007 /**************************************************************************** 3008 * SAS Port Config Pages 3009 ****************************************************************************/ 3010 3011 /* SAS Port Page 0 */ 3012 3013 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 3014 { 3015 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3016 U8 PortNumber; /* 0x08 */ 3017 U8 PhysicalPort; /* 0x09 */ 3018 U8 PortWidth; /* 0x0A */ 3019 U8 PhysicalPortWidth; /* 0x0B */ 3020 U8 ZoneGroup; /* 0x0C */ 3021 U8 Reserved1; /* 0x0D */ 3022 U16 Reserved2; /* 0x0E */ 3023 U64 SASAddress; /* 0x10 */ 3024 U32 DeviceInfo; /* 0x18 */ 3025 U32 Reserved3; /* 0x1C */ 3026 U32 Reserved4; /* 0x20 */ 3027 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 3028 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t; 3029 3030 #define MPI2_SASPORT0_PAGEVERSION (0x00) 3031 3032 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 3033 3034 /**************************************************************************** 3035 * SAS Enclosure Config Pages 3036 ****************************************************************************/ 3037 3038 /* SAS Enclosure Page 0, Enclosure Page 0 */ 3039 3040 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 3041 { 3042 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3043 U32 Reserved1; /* 0x08 */ 3044 U64 EnclosureLogicalID; /* 0x0C */ 3045 U16 Flags; /* 0x14 */ 3046 U16 EnclosureHandle; /* 0x16 */ 3047 U16 NumSlots; /* 0x18 */ 3048 U16 StartSlot; /* 0x1A */ 3049 U8 ChassisSlot; /* 0x1C */ 3050 U8 EnclosureLevel; /* 0x1D */ 3051 U16 SEPDevHandle; /* 0x1E */ 3052 U8 OEMRD; /* 0x20 */ 3053 U8 Reserved1a; /* 0x21 */ 3054 U16 Reserved2; /* 0x22 */ 3055 U32 Reserved3; /* 0x24 */ 3056 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3057 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3058 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t, 3059 MPI26_CONFIG_PAGE_ENCLOSURE_0, 3060 MPI2_POINTER PTR_MPI26_CONFIG_PAGE_ENCLOSURE_0, 3061 Mpi26EnclosurePage0_t, MPI2_POINTER pMpi26EnclosurePage0_t; 3062 3063 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x04) 3064 3065 /* values for SAS Enclosure Page 0 Flags field */ 3066 #define MPI26_SAS_ENCLS0_FLAGS_OEMRD_VALID (0x0080) 3067 #define MPI26_SAS_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040) 3068 #define MPI2_SAS_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3069 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3070 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3071 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3072 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3073 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3074 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3075 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3076 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3077 3078 #define MPI26_ENCLOSURE0_PAGEVERSION (0x04) 3079 3080 /* Values for Enclosure Page 0 Flags field */ 3081 #define MPI26_ENCLS0_FLAGS_OEMRD_VALID (0x0080) 3082 #define MPI26_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040) 3083 #define MPI26_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3084 #define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3085 #define MPI26_ENCLS0_FLAGS_MNG_MASK (0x000F) 3086 #define MPI26_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3087 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3088 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3089 #define MPI26_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3090 #define MPI26_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3091 #define MPI26_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3092 3093 /**************************************************************************** 3094 * Log Config Page 3095 ****************************************************************************/ 3096 3097 /* Log Page 0 */ 3098 3099 /* 3100 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3101 * one and check the value returned for NumLogEntries at runtime. 3102 */ 3103 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 3104 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 3105 #endif 3106 3107 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 3108 3109 typedef struct _MPI2_LOG_0_ENTRY 3110 { 3111 U64 TimeStamp; /* 0x00 */ 3112 U32 Reserved1; /* 0x08 */ 3113 U16 LogSequence; /* 0x0C */ 3114 U16 LogEntryQualifier; /* 0x0E */ 3115 U8 VP_ID; /* 0x10 */ 3116 U8 VF_ID; /* 0x11 */ 3117 U16 Reserved2; /* 0x12 */ 3118 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */ 3119 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY, 3120 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t; 3121 3122 /* values for Log Page 0 LogEntry LogEntryQualifier field */ 3123 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3124 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3125 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 3126 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 3127 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 3128 3129 typedef struct _MPI2_CONFIG_PAGE_LOG_0 3130 { 3131 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3132 U32 Reserved1; /* 0x08 */ 3133 U32 Reserved2; /* 0x0C */ 3134 U16 NumLogEntries; /* 0x10 */ 3135 U16 Reserved3; /* 0x12 */ 3136 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */ 3137 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0, 3138 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t; 3139 3140 #define MPI2_LOG_0_PAGEVERSION (0x02) 3141 3142 /**************************************************************************** 3143 * RAID Config Page 3144 ****************************************************************************/ 3145 3146 /* RAID Page 0 */ 3147 3148 /* 3149 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3150 * one and check the value returned for NumElements at runtime. 3151 */ 3152 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 3153 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 3154 #endif 3155 3156 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT 3157 { 3158 U16 ElementFlags; /* 0x00 */ 3159 U16 VolDevHandle; /* 0x02 */ 3160 U8 HotSparePool; /* 0x04 */ 3161 U8 PhysDiskNum; /* 0x05 */ 3162 U16 PhysDiskDevHandle; /* 0x06 */ 3163 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3164 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3165 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t; 3166 3167 /* values for the ElementFlags field */ 3168 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 3169 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 3170 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 3171 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 3172 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 3173 3174 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 3175 { 3176 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3177 U8 NumHotSpares; /* 0x08 */ 3178 U8 NumPhysDisks; /* 0x09 */ 3179 U8 NumVolumes; /* 0x0A */ 3180 U8 ConfigNum; /* 0x0B */ 3181 U32 Flags; /* 0x0C */ 3182 U8 ConfigGUID[24]; /* 0x10 */ 3183 U32 Reserved1; /* 0x28 */ 3184 U8 NumElements; /* 0x2C */ 3185 U8 Reserved2; /* 0x2D */ 3186 U16 Reserved3; /* 0x2E */ 3187 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */ 3188 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3189 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3190 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t; 3191 3192 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 3193 3194 /* values for RAID Configuration Page 0 Flags field */ 3195 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 3196 3197 /**************************************************************************** 3198 * Driver Persistent Mapping Config Pages 3199 ****************************************************************************/ 3200 3201 /* Driver Persistent Mapping Page 0 */ 3202 3203 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY 3204 { 3205 U64 PhysicalIdentifier; /* 0x00 */ 3206 U16 MappingInformation; /* 0x08 */ 3207 U16 DeviceIndex; /* 0x0A */ 3208 U32 PhysicalBitsMapping; /* 0x0C */ 3209 U32 Reserved1; /* 0x10 */ 3210 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3211 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3212 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t; 3213 3214 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 3215 { 3216 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3217 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */ 3218 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3219 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3220 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t; 3221 3222 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 3223 3224 /* values for Driver Persistent Mapping Page 0 MappingInformation field */ 3225 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 3226 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 3227 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 3228 3229 /**************************************************************************** 3230 * Ethernet Config Pages 3231 ****************************************************************************/ 3232 3233 /* Ethernet Page 0 */ 3234 3235 /* IP address (union of IPv4 and IPv6) */ 3236 typedef union _MPI2_ETHERNET_IP_ADDR 3237 { 3238 U32 IPv4Addr; 3239 U32 IPv6Addr[4]; 3240 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR, 3241 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t; 3242 3243 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 3244 3245 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 3246 { 3247 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3248 U8 NumInterfaces; /* 0x08 */ 3249 U8 Reserved0; /* 0x09 */ 3250 U16 Reserved1; /* 0x0A */ 3251 U32 Status; /* 0x0C */ 3252 U8 MediaState; /* 0x10 */ 3253 U8 Reserved2; /* 0x11 */ 3254 U16 Reserved3; /* 0x12 */ 3255 U8 MacAddress[6]; /* 0x14 */ 3256 U8 Reserved4; /* 0x1A */ 3257 U8 Reserved5; /* 0x1B */ 3258 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */ 3259 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */ 3260 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */ 3261 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */ 3262 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */ 3263 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */ 3264 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 3265 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 3266 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t; 3267 3268 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 3269 3270 /* values for Ethernet Page 0 Status field */ 3271 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 3272 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 3273 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 3274 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 3275 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 3276 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 3277 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 3278 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 3279 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 3280 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 3281 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 3282 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 3283 3284 /* values for Ethernet Page 0 MediaState field */ 3285 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 3286 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 3287 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 3288 3289 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 3290 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 3291 #define MPI2_ETHPG0_MS_10MBIT (0x01) 3292 #define MPI2_ETHPG0_MS_100MBIT (0x02) 3293 #define MPI2_ETHPG0_MS_1GBIT (0x03) 3294 3295 /* Ethernet Page 1 */ 3296 3297 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 3298 { 3299 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3300 U32 Reserved0; /* 0x08 */ 3301 U32 Flags; /* 0x0C */ 3302 U8 MediaState; /* 0x10 */ 3303 U8 Reserved1; /* 0x11 */ 3304 U16 Reserved2; /* 0x12 */ 3305 U8 MacAddress[6]; /* 0x14 */ 3306 U8 Reserved3; /* 0x1A */ 3307 U8 Reserved4; /* 0x1B */ 3308 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */ 3309 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */ 3310 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */ 3311 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */ 3312 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */ 3313 U32 Reserved5; /* 0x6C */ 3314 U32 Reserved6; /* 0x70 */ 3315 U32 Reserved7; /* 0x74 */ 3316 U32 Reserved8; /* 0x78 */ 3317 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 3318 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 3319 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t; 3320 3321 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 3322 3323 /* values for Ethernet Page 1 Flags field */ 3324 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 3325 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 3326 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 3327 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 3328 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 3329 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 3330 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 3331 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 3332 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 3333 3334 /* values for Ethernet Page 1 MediaState field */ 3335 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 3336 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 3337 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 3338 3339 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 3340 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 3341 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 3342 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 3343 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 3344 3345 /**************************************************************************** 3346 * Extended Manufacturing Config Pages 3347 ****************************************************************************/ 3348 3349 /* 3350 * Generic structure to use for product-specific extended manufacturing pages 3351 * (currently Extended Manufacturing Page 40 through Extended Manufacturing 3352 * Page 60). 3353 */ 3354 3355 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS 3356 { 3357 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3358 U32 ProductSpecificInfo; /* 0x08 */ 3359 } MPI2_CONFIG_PAGE_EXT_MAN_PS, 3360 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 3361 Mpi2ExtManufacturingPagePS_t, MPI2_POINTER pMpi2ExtManufacturingPagePS_t; 3362 3363 /* PageVersion should be provided by product-specific code */ 3364 3365 /**************************************************************************** 3366 * values for fields used by several types of PCIe Config Pages 3367 ****************************************************************************/ 3368 3369 /* values for NegotiatedLinkRates fields */ 3370 #define MPI26_PCIE_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 3371 /* link rates used for Negotiated Physical Link Rate */ 3372 #define MPI26_PCIE_NEG_LINK_RATE_UNKNOWN (0x00) 3373 #define MPI26_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01) 3374 #define MPI26_PCIE_NEG_LINK_RATE_2_5 (0x02) 3375 #define MPI26_PCIE_NEG_LINK_RATE_5_0 (0x03) 3376 #define MPI26_PCIE_NEG_LINK_RATE_8_0 (0x04) 3377 #define MPI26_PCIE_NEG_LINK_RATE_16_0 (0x05) 3378 3379 /**************************************************************************** 3380 * PCIe IO Unit Config Pages (MPI v2.6 and later) 3381 ****************************************************************************/ 3382 3383 /* PCIe IO Unit Page 0 */ 3384 3385 typedef struct _MPI26_PCIE_IO_UNIT0_PHY_DATA 3386 { 3387 U8 Link; /* 0x00 */ 3388 U8 LinkFlags; /* 0x01 */ 3389 U8 PhyFlags; /* 0x02 */ 3390 U8 NegotiatedLinkRate; /* 0x03 */ 3391 U32 ControllerPhyDeviceInfo;/* 0x04 */ 3392 U16 AttachedDevHandle; /* 0x08 */ 3393 U16 ControllerDevHandle; /* 0x0A */ 3394 U32 EnumerationStatus; /* 0x0C */ 3395 U32 Reserved1; /* 0x10 */ 3396 } MPI26_PCIE_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI26_PCIE_IO_UNIT0_PHY_DATA, 3397 Mpi26PCIeIOUnit0PhyData_t, MPI2_POINTER pMpi26PCIeIOUnit0PhyData_t; 3398 3399 /* 3400 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3401 * one and check the value returned for NumPhys at runtime. 3402 */ 3403 #ifndef MPI26_PCIE_IOUNIT0_PHY_MAX 3404 #define MPI26_PCIE_IOUNIT0_PHY_MAX (1) 3405 #endif 3406 3407 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_0 3408 { 3409 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3410 U32 Reserved1; /* 0x08 */ 3411 U8 NumPhys; /* 0x0C */ 3412 U8 InitStatus; /* 0x0D */ 3413 U16 Reserved3; /* 0x0E */ 3414 MPI26_PCIE_IO_UNIT0_PHY_DATA PhyData[MPI26_PCIE_IOUNIT0_PHY_MAX]; /* 0x10 */ 3415 } MPI26_CONFIG_PAGE_PIOUNIT_0, 3416 MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PIOUNIT_0, 3417 Mpi26PCIeIOUnitPage0_t, MPI2_POINTER pMpi26PCIeIOUnitPage0_t; 3418 3419 #define MPI26_PCIEIOUNITPAGE0_PAGEVERSION (0x00) 3420 3421 /* values for PCIe IO Unit Page 0 LinkFlags */ 3422 #define MPI26_PCIEIOUNIT0_LINKFLAGS_ENUMERATION_IN_PROGRESS (0x08) 3423 3424 /* values for PCIe IO Unit Page 0 PhyFlags */ 3425 #define MPI26_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 3426 3427 /* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3428 3429 /* see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo values */ 3430 3431 /* values for PCIe IO Unit Page 0 EnumerationStatus */ 3432 #define MPI26_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000) 3433 #define MPI26_PCIEIOUNIT0_ES_MAX_DEVICES_EXCEEDED (0x20000000) 3434 3435 /* PCIe IO Unit Page 1 */ 3436 3437 typedef struct _MPI26_PCIE_IO_UNIT1_PHY_DATA 3438 { 3439 U8 Link; /* 0x00 */ 3440 U8 LinkFlags; /* 0x01 */ 3441 U8 PhyFlags; /* 0x02 */ 3442 U8 MaxMinLinkRate; /* 0x03 */ 3443 U32 ControllerPhyDeviceInfo; /* 0x04 */ 3444 U32 Reserved1; /* 0x08 */ 3445 } MPI26_PCIE_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI26_PCIE_IO_UNIT1_PHY_DATA, 3446 Mpi26PCIeIOUnit1PhyData_t, MPI2_POINTER pMpi26PCIeIOUnit1PhyData_t; 3447 3448 /* values for LinkFlags */ 3449 #define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK (0x00) 3450 #define MPI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN (0x01) 3451 #define MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN (0x02) 3452 3453 /* 3454 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3455 * one and check the value returned for NumPhys at runtime. 3456 */ 3457 #ifndef MPI26_PCIE_IOUNIT1_PHY_MAX 3458 #define MPI26_PCIE_IOUNIT1_PHY_MAX (1) 3459 #endif 3460 3461 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1 3462 { 3463 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3464 U16 ControlFlags; /* 0x08 */ 3465 U16 Reserved; /* 0x0A */ 3466 U16 AdditionalControlFlags; /* 0x0C */ 3467 U16 NVMeMaxQueueDepth; /* 0x0E */ 3468 U8 NumPhys; /* 0x10 */ 3469 U8 DMDReportPCIe; /* 0x11 */ 3470 U16 Reserved2; /* 0x12 */ 3471 MPI26_PCIE_IO_UNIT1_PHY_DATA PhyData[MPI26_PCIE_IOUNIT1_PHY_MAX];/* 0x14 */ 3472 } MPI26_CONFIG_PAGE_PIOUNIT_1, 3473 MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PIOUNIT_1, 3474 Mpi26PCIeIOUnitPage1_t, MPI2_POINTER pMpi26PCIeIOUnitPage1_t; 3475 3476 #define MPI26_PCIEIOUNITPAGE1_PAGEVERSION (0x00) 3477 3478 /* values for PCIe IO Unit Page 1 PhyFlags */ 3479 #define MPI26_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 3480 #define MPI26_PCIEIOUNIT1_PHYFLAGS_ENDPOINT_ONLY (0x01) 3481 3482 /* values for PCIe IO Unit Page 1 MaxMinLinkRate */ 3483 #define MPI26_PCIEIOUNIT1_MAX_RATE_MASK (0xF0) 3484 #define MPI26_PCIEIOUNIT1_MAX_RATE_SHIFT (4) 3485 #define MPI26_PCIEIOUNIT1_MAX_RATE_2_5 (0x20) 3486 #define MPI26_PCIEIOUNIT1_MAX_RATE_5_0 (0x30) 3487 #define MPI26_PCIEIOUNIT1_MAX_RATE_8_0 (0x40) 3488 #define MPI26_PCIEIOUNIT1_MAX_RATE_16_0 (0x50) 3489 3490 /* values for PCIe IO Unit Page 1 DMDReportPCIe */ 3491 #define MPI26_PCIEIOUNIT1_DMD_REPORT_UNITS_MASK (0x80) 3492 #define MPI26_PCIEIOUNIT1_DMD_REPORT_UNITS_1_SEC (0x00) 3493 #define MPI26_PCIEIOUNIT1_DMD_REPORT_UNITS_16_SEC (0x80) 3494 #define MPI26_PCIEIOUNIT1_DMD_REPORT_DELAY_TIME_MASK (0x7F) 3495 3496 /* see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo values */ 3497 3498 /**************************************************************************** 3499 * PCIe Switch Config Pages (MPI v2.6 and later) 3500 ****************************************************************************/ 3501 3502 /* PCIe Switch Page 0 */ 3503 3504 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_0 3505 { 3506 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3507 U8 PhysicalPort; /* 0x08 */ 3508 U8 Reserved1; /* 0x09 */ 3509 U16 Reserved2; /* 0x0A */ 3510 U16 DevHandle; /* 0x0C */ 3511 U16 ParentDevHandle; /* 0x0E */ 3512 U8 NumPorts; /* 0x10 */ 3513 U8 PCIeLevel; /* 0x11 */ 3514 U16 Reserved3; /* 0x12 */ 3515 U32 Reserved4; /* 0x14 */ 3516 U32 Reserved5; /* 0x18 */ 3517 U32 Reserved6; /* 0x1C */ 3518 } MPI26_CONFIG_PAGE_PSWITCH_0, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PSWITCH_0, 3519 Mpi26PCIeSwitchPage0_t, MPI2_POINTER pMpi26PCIeSwitchPage0_t; 3520 3521 #define MPI26_PCIESWITCH0_PAGEVERSION (0x00) 3522 3523 /* PCIe Switch Page 1 */ 3524 3525 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_1 3526 { 3527 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3528 U8 PhysicalPort; /* 0x08 */ 3529 U8 Reserved1; /* 0x09 */ 3530 U16 Reserved2; /* 0x0A */ 3531 U8 NumPorts; /* 0x0C */ 3532 U8 PortNum; /* 0x0D */ 3533 U16 AttachedDevHandle; /* 0x0E */ 3534 U16 SwitchDevHandle; /* 0x10 */ 3535 U8 NegotiatedPortWidth; /* 0x12 */ 3536 U8 NegotiatedLinkRate; /* 0x13 */ 3537 U16 Flags; /* 0x14 */ 3538 U16 Reserved4; /* 0x16 */ 3539 U32 Reserved5; /* 0x18 */ 3540 } MPI26_CONFIG_PAGE_PSWITCH_1, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PSWITCH_1, 3541 Mpi26PCIeSwitchPage1_t, MPI2_POINTER pMpi26PCIeSwitchPage1_t; 3542 3543 #define MPI26_PCIESWITCH1_PAGEVERSION (0x00) 3544 3545 /* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3546 3547 /* defines for the Flags field */ 3548 #define MPI26_PCIESWITCH1_2_RETIMER_PRESENCE (0x0002) 3549 #define MPI26_PCIESWITCH1_RETIMER_PRESENCE (0x0001) 3550 3551 /**************************************************************************** 3552 * PCIe Device Config Pages (MPI v2.6 and later) 3553 ****************************************************************************/ 3554 3555 /* PCIe Device Page 0 */ 3556 3557 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0 3558 { 3559 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3560 U16 Slot; /* 0x08 */ 3561 U16 EnclosureHandle; /* 0x0A */ 3562 U64 WWID; /* 0x0C */ 3563 U16 ParentDevHandle; /* 0x14 */ 3564 U8 PortNum; /* 0x16 */ 3565 U8 AccessStatus; /* 0x17 */ 3566 U16 DevHandle; /* 0x18 */ 3567 U8 PhysicalPort; /* 0x1A */ 3568 U8 Reserved1; /* 0x1B */ 3569 U32 DeviceInfo; /* 0x1C */ 3570 U32 Flags; /* 0x20 */ 3571 U8 SupportedLinkRates; /* 0x24 */ 3572 U8 MaxPortWidth; /* 0x25 */ 3573 U8 NegotiatedPortWidth; /* 0x26 */ 3574 U8 NegotiatedLinkRate; /* 0x27 */ 3575 U8 EnclosureLevel; /* 0x28 */ 3576 U8 Reserved2; /* 0x29 */ 3577 U16 Reserved3; /* 0x2A */ 3578 U8 ConnectorName[4]; /* 0x2C */ 3579 U32 Reserved4; /* 0x30 */ 3580 U32 Reserved5; /* 0x34 */ 3581 } MPI26_CONFIG_PAGE_PCIEDEV_0, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIEDEV_0, 3582 Mpi26PCIeDevicePage0_t, MPI2_POINTER pMpi26PCIeDevicePage0_t; 3583 3584 #define MPI26_PCIEDEVICE0_PAGEVERSION (0x01) 3585 3586 /* values for PCIe Device Page 0 AccessStatus field */ 3587 #define MPI26_PCIEDEV0_ASTATUS_NO_ERRORS (0x00) 3588 #define MPI26_PCIEDEV0_ASTATUS_NEEDS_INITIALIZATION (0x04) 3589 #define MPI26_PCIEDEV0_ASTATUS_CAPABILITY_FAILED (0x02) 3590 #define MPI26_PCIEDEV0_ASTATUS_DEVICE_BLOCKED (0x07) 3591 #define MPI26_PCIEDEV0_ASTATUS_MEMORY_SPACE_ACCESS_FAILED (0x08) 3592 #define MPI26_PCIEDEV0_ASTATUS_UNSUPPORTED_DEVICE (0x09) 3593 #define MPI26_PCIEDEV0_ASTATUS_MSIX_REQUIRED (0x0A) 3594 #define MPI26_PCIEDEV0_ASTATUS_UNKNOWN (0x10) 3595 3596 #define MPI26_PCIEDEV0_ASTATUS_NVME_READY_TIMEOUT (0x30) 3597 #define MPI26_PCIEDEV0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x31) 3598 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDENTIFY_FAILED (0x32) 3599 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCONFIG_FAILED (0x33) 3600 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCREATION_FAILED (0x34) 3601 #define MPI26_PCIEDEV0_ASTATUS_NVME_EVENTCFG_FAILED (0x35) 3602 #define MPI26_PCIEDEV0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x36) 3603 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDLE_TIMEOUT (0x37) 3604 #define MPI26_PCIEDEV0_ASTATUS_NVME_FAILURE_STATUS (0x38) 3605 3606 #define MPI26_PCIEDEV0_ASTATUS_INIT_FAIL_MAX (0x3F) 3607 3608 /* see mpi2_pci.h for the MPI26_PCIE_DEVINFO_ defines used for the DeviceInfo field */ 3609 3610 /* values for PCIe Device Page 0 Flags field */ 3611 #define MPI26_PCIEDEV0_FLAGS_2_RETIMER_PRESENCE (0x00020000) 3612 #define MPI26_PCIEDEV0_FLAGS_RETIMER_PRESENCE (0x00010000) 3613 #define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE (0x00008000) 3614 #define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH (0x00004000) 3615 #define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE (0x00002000) 3616 #define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION (0x00000400) 3617 #define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION (0x00000200) 3618 #define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE (0x00000100) 3619 #define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED (0x00000080) 3620 #define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED (0x00000040) 3621 #define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED (0x00000020) 3622 #define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED (0x00000010) 3623 #define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID (0x00000002) 3624 #define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT (0x00000001) 3625 3626 /* values for PCIe Device Page 0 SupportedLinkRates field */ 3627 #define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED (0x08) 3628 #define MPI26_PCIEDEV0_LINK_RATE_8_0_SUPPORTED (0x04) 3629 #define MPI26_PCIEDEV0_LINK_RATE_5_0_SUPPORTED (0x02) 3630 #define MPI26_PCIEDEV0_LINK_RATE_2_5_SUPPORTED (0x01) 3631 3632 /* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3633 3634 /* PCIe Device Page 2 */ 3635 3636 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2 3637 { 3638 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3639 U16 DevHandle; /* 0x08 */ 3640 U8 ControllerResetTO; /* 0x0A */ 3641 U8 Reserved1; /* 0x0B */ 3642 U32 MaximumDataTransferSize;/* 0x0C */ 3643 U32 Capabilities; /* 0x10 */ 3644 U16 NOIOB; /* 0x14 */ 3645 U16 Reserved2; /* 0x16 */ 3646 } MPI26_CONFIG_PAGE_PCIEDEV_2, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIEDEV_2, 3647 Mpi26PCIeDevicePage2_t, MPI2_POINTER pMpi26PCIeDevicePage2_t; 3648 3649 #define MPI26_PCIEDEVICE2_PAGEVERSION (0x01) 3650 3651 /* defines for PCIe Device Page 2 Capabilities field */ 3652 #define MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN (0x00000008) 3653 #define MPI26_PCIEDEV2_CAP_SGL_FORMAT (0x00000004) 3654 #define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT (0x00000002) 3655 #define MPI26_PCIEDEV2_CAP_SGL_SUPPORT (0x00000001) 3656 3657 /* Defines for the NOIOB field */ 3658 #define MPI26_PCIEDEV2_NOIOB_UNSUPPORTED (0x0000) 3659 3660 /**************************************************************************** 3661 * PCIe Link Config Pages (MPI v2.6 and later) 3662 ****************************************************************************/ 3663 3664 /* PCIe Link Page 1 */ 3665 3666 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_1 3667 { 3668 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3669 U8 Link; /* 0x08 */ 3670 U8 Reserved1; /* 0x09 */ 3671 U16 Reserved2; /* 0x0A */ 3672 U32 CorrectableErrorCount; /* 0x0C */ 3673 U16 NonFatalErrorCount; /* 0x10 */ 3674 U16 Reserved3; /* 0x12 */ 3675 U16 FatalErrorCount; /* 0x14 */ 3676 U16 Reserved4; /* 0x16 */ 3677 } MPI26_CONFIG_PAGE_PCIELINK_1, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_1, 3678 Mpi26PcieLinkPage1_t, MPI2_POINTER pMpi26PcieLinkPage1_t; 3679 3680 #define MPI26_PCIELINK1_PAGEVERSION (0x00) 3681 3682 /* PCIe Link Page 2 */ 3683 3684 typedef struct _MPI26_PCIELINK2_LINK_EVENT 3685 { 3686 U8 LinkEventCode; /* 0x00 */ 3687 U8 Reserved1; /* 0x01 */ 3688 U16 Reserved2; /* 0x02 */ 3689 U32 LinkEventInfo; /* 0x04 */ 3690 } MPI26_PCIELINK2_LINK_EVENT, MPI2_POINTER PTR_MPI26_PCIELINK2_LINK_EVENT, 3691 Mpi26PcieLink2LinkEvent_t, MPI2_POINTER pMpi26PcieLink2LinkEvent_t; 3692 3693 /* use MPI26_PCIELINK3_EVTCODE_ for the LinkEventCode field */ 3694 3695 /* 3696 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3697 * one and check the value returned for NumLinkEvents at runtime. 3698 */ 3699 #ifndef MPI26_PCIELINK2_LINK_EVENT_MAX 3700 #define MPI26_PCIELINK2_LINK_EVENT_MAX (1) 3701 #endif 3702 3703 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_2 3704 { 3705 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3706 U8 Link; /* 0x08 */ 3707 U8 Reserved1; /* 0x09 */ 3708 U16 Reserved2; /* 0x0A */ 3709 U8 NumLinkEvents; /* 0x0C */ 3710 U8 Reserved3; /* 0x0D */ 3711 U16 Reserved4; /* 0x0E */ 3712 MPI26_PCIELINK2_LINK_EVENT LinkEvent[MPI26_PCIELINK2_LINK_EVENT_MAX]; /* 0x10 */ 3713 } MPI26_CONFIG_PAGE_PCIELINK_2, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_2, 3714 Mpi26PcieLinkPage2_t, MPI2_POINTER pMpi26PcieLinkPage2_t; 3715 3716 #define MPI26_PCIELINK2_PAGEVERSION (0x00) 3717 3718 /* PCIe Link Page 3 */ 3719 3720 typedef struct _MPI26_PCIELINK3_LINK_EVENT_CONFIG 3721 { 3722 U8 LinkEventCode; /* 0x00 */ 3723 U8 Reserved1; /* 0x01 */ 3724 U16 Reserved2; /* 0x02 */ 3725 U8 CounterType; /* 0x04 */ 3726 U8 ThresholdWindow; /* 0x05 */ 3727 U8 TimeUnits; /* 0x06 */ 3728 U8 Reserved3; /* 0x07 */ 3729 U32 EventThreshold; /* 0x08 */ 3730 U16 ThresholdFlags; /* 0x0C */ 3731 U16 Reserved4; /* 0x0E */ 3732 } MPI26_PCIELINK3_LINK_EVENT_CONFIG, MPI2_POINTER PTR_MPI26_PCIELINK3_LINK_EVENT_CONFIG, 3733 Mpi26PcieLink3LinkEventConfig_t, MPI2_POINTER pMpi26PcieLink3LinkEventConfig_t; 3734 3735 /* values for LinkEventCode field */ 3736 #define MPI26_PCIELINK3_EVTCODE_NO_EVENT (0x00) 3737 #define MPI26_PCIELINK3_EVTCODE_CORRECTABLE_ERROR_RECEIVED (0x01) 3738 #define MPI26_PCIELINK3_EVTCODE_NON_FATAL_ERROR_RECEIVED (0x02) 3739 #define MPI26_PCIELINK3_EVTCODE_FATAL_ERROR_RECEIVED (0x03) 3740 #define MPI26_PCIELINK3_EVTCODE_DATA_LINK_ERROR_DETECTED (0x04) 3741 #define MPI26_PCIELINK3_EVTCODE_TRANSACTION_LAYER_ERROR_DETECTED (0x05) 3742 #define MPI26_PCIELINK3_EVTCODE_TLP_ECRC_ERROR_DETECTED (0x06) 3743 #define MPI26_PCIELINK3_EVTCODE_POISONED_TLP (0x07) 3744 #define MPI26_PCIELINK3_EVTCODE_RECEIVED_NAK_DLLP (0x08) 3745 #define MPI26_PCIELINK3_EVTCODE_SENT_NAK_DLLP (0x09) 3746 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RECOVERY_STATE (0x0A) 3747 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RXL0S_STATE (0x0B) 3748 #define MPI26_PCIELINK3_EVTCODE_LTSSM_TXL0S_STATE (0x0C) 3749 #define MPI26_PCIELINK3_EVTCODE_LTSSM_L1_STATE (0x0D) 3750 #define MPI26_PCIELINK3_EVTCODE_LTSSM_DISABLED_STATE (0x0E) 3751 #define MPI26_PCIELINK3_EVTCODE_LTSSM_HOT_RESET_STATE (0x0F) 3752 #define MPI26_PCIELINK3_EVTCODE_SYSTEM_ERROR (0x10) 3753 #define MPI26_PCIELINK3_EVTCODE_DECODE_ERROR (0x11) 3754 #define MPI26_PCIELINK3_EVTCODE_DISPARITY_ERROR (0x12) 3755 3756 /* values for the CounterType field */ 3757 #define MPI26_PCIELINK3_COUNTER_TYPE_WRAPPING (0x00) 3758 #define MPI26_PCIELINK3_COUNTER_TYPE_SATURATING (0x01) 3759 #define MPI26_PCIELINK3_COUNTER_TYPE_PEAK_VALUE (0x02) 3760 3761 /* values for the TimeUnits field */ 3762 #define MPI26_PCIELINK3_TM_UNITS_10_MICROSECONDS (0x00) 3763 #define MPI26_PCIELINK3_TM_UNITS_100_MICROSECONDS (0x01) 3764 #define MPI26_PCIELINK3_TM_UNITS_1_MILLISECOND (0x02) 3765 #define MPI26_PCIELINK3_TM_UNITS_10_MILLISECONDS (0x03) 3766 3767 /* values for the ThresholdFlags field */ 3768 #define MPI26_PCIELINK3_TFLAGS_EVENT_NOTIFY (0x0001) 3769 3770 /* 3771 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3772 * one and check the value returned for NumLinkEvents at runtime. 3773 */ 3774 #ifndef MPI26_PCIELINK3_LINK_EVENT_MAX 3775 #define MPI26_PCIELINK3_LINK_EVENT_MAX (1) 3776 #endif 3777 3778 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_3 3779 { 3780 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3781 U8 Link; /* 0x08 */ 3782 U8 Reserved1; /* 0x09 */ 3783 U16 Reserved2; /* 0x0A */ 3784 U8 NumLinkEvents; /* 0x0C */ 3785 U8 Reserved3; /* 0x0D */ 3786 U16 Reserved4; /* 0x0E */ 3787 MPI26_PCIELINK3_LINK_EVENT_CONFIG LinkEventConfig[MPI26_PCIELINK3_LINK_EVENT_MAX]; /* 0x10 */ 3788 } MPI26_CONFIG_PAGE_PCIELINK_3, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_3, 3789 Mpi26PcieLinkPage3_t, MPI2_POINTER pMpi26PcieLinkPage3_t; 3790 3791 #define MPI26_PCIELINK3_PAGEVERSION (0x00) 3792 3793 #endif 3794