1 /*- 2 * Copyright 2000-2020 Broadcom Inc. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. Neither the name of the author nor the names of any co-contributors 13 * may be used to endorse or promote products derived from this software 14 * without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD 29 * 30 * $FreeBSD$ 31 */ 32 33 /* 34 * Copyright 2000-2020 Broadcom Inc. All rights reserved. 35 * 36 * 37 * Name: mpi2_cnfg.h 38 * Title: MPI Configuration messages and pages 39 * Creation Date: November 10, 2006 40 * 41 * mpi2_cnfg.h Version: 02.00.45 42 * 43 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 44 * prefix are for use only on MPI v2.5 products, and must not be used 45 * with MPI v2.0 products. Unless otherwise noted, names beginning with 46 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 47 * 48 * Version History 49 * --------------- 50 * 51 * Date Version Description 52 * -------- -------- ------------------------------------------------------ 53 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 54 * 06-04-07 02.00.01 Added defines for SAS IO Unit Page 2 PhyFlags. 55 * Added Manufacturing Page 11. 56 * Added MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE 57 * define. 58 * 06-26-07 02.00.02 Adding generic structure for product-specific 59 * Manufacturing pages: MPI2_CONFIG_PAGE_MANUFACTURING_PS. 60 * Rework of BIOS Page 2 configuration page. 61 * Fixed MPI2_BIOSPAGE2_BOOT_DEVICE to be a union of the 62 * forms. 63 * Added configuration pages IOC Page 8 and Driver 64 * Persistent Mapping Page 0. 65 * 08-31-07 02.00.03 Modified configuration pages dealing with Integrated 66 * RAID (Manufacturing Page 4, RAID Volume Pages 0 and 1, 67 * RAID Physical Disk Pages 0 and 1, RAID Configuration 68 * Page 0). 69 * Added new value for AccessStatus field of SAS Device 70 * Page 0 (_SATA_NEEDS_INITIALIZATION). 71 * 10-31-07 02.00.04 Added missing SEPDevHandle field to 72 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 73 * 12-18-07 02.00.05 Modified IO Unit Page 0 to use 32-bit version fields for 74 * NVDATA. 75 * Modified IOC Page 7 to use masks and added field for 76 * SASBroadcastPrimitiveMasks. 77 * Added MPI2_CONFIG_PAGE_BIOS_4. 78 * Added MPI2_CONFIG_PAGE_LOG_0. 79 * 02-29-08 02.00.06 Modified various names to make them 32-character unique. 80 * Added SAS Device IDs. 81 * Updated Integrated RAID configuration pages including 82 * Manufacturing Page 4, IOC Page 6, and RAID Configuration 83 * Page 0. 84 * 05-21-08 02.00.07 Added define MPI2_MANPAGE4_MIX_SSD_SAS_SATA. 85 * Added define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION. 86 * Fixed define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING. 87 * Added missing MaxNumRoutedSasAddresses field to 88 * MPI2_CONFIG_PAGE_EXPANDER_0. 89 * Added SAS Port Page 0. 90 * Modified structure layout for 91 * MPI2_CONFIG_PAGE_DRIVER_MAPPING_0. 92 * 06-27-08 02.00.08 Changed MPI2_CONFIG_PAGE_RD_PDISK_1 to use 93 * MPI2_RAID_PHYS_DISK1_PATH_MAX to size the array. 94 * 10-02-08 02.00.09 Changed MPI2_RAID_PGAD_CONFIGNUM_MASK from 0x0000FFFF 95 * to 0x000000FF. 96 * Added two new values for the Physical Disk Coercion Size 97 * bits in the Flags field of Manufacturing Page 4. 98 * Added product-specific Manufacturing pages 16 to 31. 99 * Modified Flags bits for controlling write cache on SATA 100 * drives in IO Unit Page 1. 101 * Added new bit to AdditionalControlFlags of SAS IO Unit 102 * Page 1 to control Invalid Topology Correction. 103 * Added additional defines for RAID Volume Page 0 104 * VolumeStatusFlags field. 105 * Modified meaning of RAID Volume Page 0 VolumeSettings 106 * define for auto-configure of hot-swap drives. 107 * Added SupportedPhysDisks field to RAID Volume Page 1 and 108 * added related defines. 109 * Added PhysDiskAttributes field (and related defines) to 110 * RAID Physical Disk Page 0. 111 * Added MPI2_SAS_PHYINFO_PHY_VACANT define. 112 * Added three new DiscoveryStatus bits for SAS IO Unit 113 * Page 0 and SAS Expander Page 0. 114 * Removed multiplexing information from SAS IO Unit pages. 115 * Added BootDeviceWaitTime field to SAS IO Unit Page 4. 116 * Removed Zone Address Resolved bit from PhyInfo and from 117 * Expander Page 0 Flags field. 118 * Added two new AccessStatus values to SAS Device Page 0 119 * for indicating routing problems. Added 3 reserved words 120 * to this page. 121 * 01-19-09 02.00.10 Fixed defines for GPIOVal field of IO Unit Page 3. 122 * Inserted missing reserved field into structure for IOC 123 * Page 6. 124 * Added more pending task bits to RAID Volume Page 0 125 * VolumeStatusFlags defines. 126 * Added MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED define. 127 * Added a new DiscoveryStatus bit for SAS IO Unit Page 0 128 * and SAS Expander Page 0 to flag a downstream initiator 129 * when in simplified routing mode. 130 * Removed SATA Init Failure defines for DiscoveryStatus 131 * fields of SAS IO Unit Page 0 and SAS Expander Page 0. 132 * Added MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED define. 133 * Added PortGroups, DmaGroup, and ControlGroup fields to 134 * SAS Device Page 0. 135 * 05-06-09 02.00.11 Added structures and defines for IO Unit Page 5 and IO 136 * Unit Page 6. 137 * Added expander reduced functionality data to SAS 138 * Expander Page 0. 139 * Added SAS PHY Page 2 and SAS PHY Page 3. 140 * 07-30-09 02.00.12 Added IO Unit Page 7. 141 * Added new device ids. 142 * Added SAS IO Unit Page 5. 143 * Added partial and slumber power management capable flags 144 * to SAS Device Page 0 Flags field. 145 * Added PhyInfo defines for power condition. 146 * Added Ethernet configuration pages. 147 * 10-28-09 02.00.13 Added MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY. 148 * Added SAS PHY Page 4 structure and defines. 149 * 02-10-10 02.00.14 Modified the comments for the configuration page 150 * structures that contain an array of data. The host 151 * should use the "count" field in the page data (e.g. the 152 * NumPhys field) to determine the number of valid elements 153 * in the array. 154 * Added/modified some MPI2_MFGPAGE_DEVID_SAS defines. 155 * Added PowerManagementCapabilities to IO Unit Page 7. 156 * Added PortWidthModGroup field to 157 * MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS. 158 * Added MPI2_CONFIG_PAGE_SASIOUNIT_6 and related defines. 159 * Added MPI2_CONFIG_PAGE_SASIOUNIT_7 and related defines. 160 * Added MPI2_CONFIG_PAGE_SASIOUNIT_8 and related defines. 161 * 05-12-10 02.00.15 Added MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT 162 * define. 163 * Added MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE define. 164 * Added MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY define. 165 * 08-11-10 02.00.16 Removed IO Unit Page 1 device path (multi-pathing) 166 * defines. 167 * 11-10-10 02.00.17 Added ReceptacleID field (replacing Reserved1) to 168 * MPI2_MANPAGE7_CONNECTOR_INFO and reworked defines for 169 * the Pinout field. 170 * Added BoardTemperature and BoardTemperatureUnits fields 171 * to MPI2_CONFIG_PAGE_IO_UNIT_7. 172 * Added MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING define 173 * and MPI2_CONFIG_PAGE_EXT_MAN_PS structure. 174 * 02-23-11 02.00.18 Added ProxyVF_ID field to MPI2_CONFIG_REQUEST. 175 * Added IO Unit Page 8, IO Unit Page 9, 176 * and IO Unit Page 10. 177 * Added SASNotifyPrimitiveMasks field to 178 * MPI2_CONFIG_PAGE_IOC_7. 179 * 03-09-11 02.00.19 Fixed IO Unit Page 10 (to match the spec). 180 * 05-25-11 02.00.20 Cleaned up a few comments. 181 * 08-24-11 02.00.21 Marked the IO Unit Page 7 PowerManagementCapabilities 182 * for PCIe link as obsolete. 183 * Added SpinupFlags field containing a Disable Spin-up bit 184 * to the MPI2_SAS_IOUNIT4_SPINUP_GROUP fields of SAS IO 185 * Unit Page 4. 186 * 11-18-11 02.00.22 Added define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT. 187 * Added UEFIVersion field to BIOS Page 1 and defined new 188 * BiosOptions bits. 189 * Incorporating additions for MPI v2.5. 190 * 11-27-12 02.00.23 Added MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER. 191 * Added MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID. 192 * 12-20-12 02.00.24 Marked MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION as 193 * obsolete for MPI v2.5 and later. 194 * Added some defines for 12G SAS speeds. 195 * 04-09-13 02.00.25 Added MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK. 196 * Fixed MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS to 197 * match the specification. 198 * 08-19-13 02.00.26 Added reserved words to MPI2_CONFIG_PAGE_IO_UNIT_7 for 199 * future use. 200 * 12-05-13 02.00.27 Added MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL for 201 * MPI2_CONFIG_PAGE_MAN_7. 202 * Added EnclosureLevel and ConnectorName fields to 203 * MPI2_CONFIG_PAGE_SAS_DEV_0. 204 * Added MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID for 205 * MPI2_CONFIG_PAGE_SAS_DEV_0. 206 * Added EnclosureLevel field to 207 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 208 * Added MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID for 209 * MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0. 210 * 01-08-14 02.00.28 Added more defines for the BiosOptions field of 211 * MPI2_CONFIG_PAGE_BIOS_1. 212 * 06-13-14 02.00.29 Added SSUTimeout field to MPI2_CONFIG_PAGE_BIOS_1, and 213 * more defines for the BiosOptions field. 214 * 11-18-14 02.00.30 Updated copyright information. 215 * Added MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG. 216 * Added AdapterOrderAux fields to BIOS Page 3. 217 * 03-16-15 02.00.31 Updated for MPI v2.6. 218 * Added BoardPowerRequirement, PCISlotPowerAllocation, and 219 * Flags field to IO Unit Page 7. 220 * Added IO Unit Page 11. 221 * Added new SAS Phy Event codes 222 * Added PCIe configuration pages. 223 * 03-19-15 02.00.32 Fixed PCIe Link Config page structure names to be 224 * unique in first 32 characters. 225 * 05-25-15 02.00.33 Added more defines for the BiosOptions field of 226 * MPI2_CONFIG_PAGE_BIOS_1. 227 * 08-25-15 02.00.34 Added PCIe Device Page 2 SGL format capability. 228 * 12-18-15 02.00.35 Added SATADeviceWaitTime to SAS IO Unit Page 4. 229 * 01-21-16 02.00.36 Added/modified MPI2_MFGPAGE_DEVID_SAS defines. 230 * Added Link field to PCIe Link Pages 231 * Added EnclosureLevel and ConnectorName to PCIe 232 * Device Page 0. 233 * Added define for PCIE IoUnit page 1 max rate shift. 234 * Added comment for reserved ExtPageTypes. 235 * Added SAS 4 22.5 gbs speed support. 236 * Added PCIe 4 16.0 GT/sec speec support. 237 * Removed AHCI support. 238 * Removed SOP support. 239 * Added NegotiatedLinkRate and NegotiatedPortWidth to 240 * PCIe device page 0. 241 * 04-10-16 02.00.37 Fixed MPI2_MFGPAGE_DEVID_SAS3616/3708 defines 242 * 07-01-16 02.00.38 Added Manufacturing page 7 Connector types. 243 * Changed declaration of ConnectorName in PCIe DevicePage0 244 * to match SAS DevicePage 0. 245 * Added SATADeviceWaitTime to IO Unit Page 11. 246 * Added MPI26_MFGPAGE_DEVID_SAS4008 247 * Added x16 PCIe width to IO Unit Page 7 248 * Added LINKFLAGS to control SRIS in PCIe IO Unit page 1 249 * phy data. 250 * Added InitStatus to PCIe IO Unit Page 1 header. 251 * 09-01-16 02.00.39 Added MPI26_CONFIG_PAGE_ENCLOSURE_0 and related defines. 252 * Added MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE and 253 * MPI26_ENCLOS_PGAD_FORM_HANDLE page address formats. 254 * 02-02-17 02.00.40 Added MPI2_MANPAGE7_SLOT_UNKNOWN. 255 * Added ChassisSlot field to SAS Enclosure Page 0. 256 * Added ChassisSlot Valid bit (bit 5) to the Flags field 257 * in SAS Enclosure Page 0. 258 * 06-13-17 02.00.41 Added MPI26_MFGPAGE_DEVID_SAS3816 and 259 * MPI26_MFGPAGE_DEVID_SAS3916 defines. 260 * Removed MPI26_MFGPAGE_DEVID_SAS4008 define. 261 * Added MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN define. 262 * Renamed PI26_PCIEIOUNIT1_LINKFLAGS_EN_SRIS to 263 * PI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN. 264 * Renamed MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SRIS to 265 * MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK. 266 * 09-29-17 02.00.42 Added ControllerResetTO field to PCIe Device Page 2. 267 * Added NOIOB field to PCIe Device Page 2. 268 * Added MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN to 269 * the Capabilities field of PCIe Device Page 2. 270 * 07-22-18 02.00.43 Added defines for SAS3916 and SAS3816. 271 * Added WRiteCache defines to IO Unit Page 1. 272 * Added MaxEnclosureLevel to BIOS Page 1. 273 * Added OEMRD to SAS Enclosure Page 1. 274 * Added DMDReportPCIe to PCIe IO Unit Page 1. 275 * Added Flags field and flags for Retimers to 276 * PCIe Switch Page 1. 277 * 08-02-18 02.00.44 Added Slotx2, Slotx4 to ManPage 7. 278 * 08-15-18 02.00.45 Added ProductSpecific field at end of IOC Page 1 279 * -------------------------------------------------------------------------- 280 */ 281 282 #ifndef MPI2_CNFG_H 283 #define MPI2_CNFG_H 284 285 /***************************************************************************** 286 * Configuration Page Header and defines 287 *****************************************************************************/ 288 289 /* Config Page Header */ 290 typedef struct _MPI2_CONFIG_PAGE_HEADER 291 { 292 U8 PageVersion; /* 0x00 */ 293 U8 PageLength; /* 0x01 */ 294 U8 PageNumber; /* 0x02 */ 295 U8 PageType; /* 0x03 */ 296 } MPI2_CONFIG_PAGE_HEADER, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER, 297 Mpi2ConfigPageHeader_t, MPI2_POINTER pMpi2ConfigPageHeader_t; 298 299 typedef union _MPI2_CONFIG_PAGE_HEADER_UNION 300 { 301 MPI2_CONFIG_PAGE_HEADER Struct; 302 U8 Bytes[4]; 303 U16 Word16[2]; 304 U32 Word32; 305 } MPI2_CONFIG_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_HEADER_UNION, 306 Mpi2ConfigPageHeaderUnion, MPI2_POINTER pMpi2ConfigPageHeaderUnion; 307 308 /* Extended Config Page Header */ 309 typedef struct _MPI2_CONFIG_EXTENDED_PAGE_HEADER 310 { 311 U8 PageVersion; /* 0x00 */ 312 U8 Reserved1; /* 0x01 */ 313 U8 PageNumber; /* 0x02 */ 314 U8 PageType; /* 0x03 */ 315 U16 ExtPageLength; /* 0x04 */ 316 U8 ExtPageType; /* 0x06 */ 317 U8 Reserved2; /* 0x07 */ 318 } MPI2_CONFIG_EXTENDED_PAGE_HEADER, 319 MPI2_POINTER PTR_MPI2_CONFIG_EXTENDED_PAGE_HEADER, 320 Mpi2ConfigExtendedPageHeader_t, MPI2_POINTER pMpi2ConfigExtendedPageHeader_t; 321 322 typedef union _MPI2_CONFIG_EXT_PAGE_HEADER_UNION 323 { 324 MPI2_CONFIG_PAGE_HEADER Struct; 325 MPI2_CONFIG_EXTENDED_PAGE_HEADER Ext; 326 U8 Bytes[8]; 327 U16 Word16[4]; 328 U32 Word32[2]; 329 } MPI2_CONFIG_EXT_PAGE_HEADER_UNION, MPI2_POINTER PTR_MPI2_CONFIG_EXT_PAGE_HEADER_UNION, 330 Mpi2ConfigPageExtendedHeaderUnion, MPI2_POINTER pMpi2ConfigPageExtendedHeaderUnion; 331 332 333 /* PageType field values */ 334 #define MPI2_CONFIG_PAGEATTR_READ_ONLY (0x00) 335 #define MPI2_CONFIG_PAGEATTR_CHANGEABLE (0x10) 336 #define MPI2_CONFIG_PAGEATTR_PERSISTENT (0x20) 337 #define MPI2_CONFIG_PAGEATTR_MASK (0xF0) 338 339 #define MPI2_CONFIG_PAGETYPE_IO_UNIT (0x00) 340 #define MPI2_CONFIG_PAGETYPE_IOC (0x01) 341 #define MPI2_CONFIG_PAGETYPE_BIOS (0x02) 342 #define MPI2_CONFIG_PAGETYPE_RAID_VOLUME (0x08) 343 #define MPI2_CONFIG_PAGETYPE_MANUFACTURING (0x09) 344 #define MPI2_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A) 345 #define MPI2_CONFIG_PAGETYPE_EXTENDED (0x0F) 346 #define MPI2_CONFIG_PAGETYPE_MASK (0x0F) 347 348 #define MPI2_CONFIG_TYPENUM_MASK (0x0FFF) 349 350 351 /* ExtPageType field values */ 352 #define MPI2_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10) 353 #define MPI2_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11) 354 #define MPI2_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12) 355 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PHY (0x13) 356 #define MPI2_CONFIG_EXTPAGETYPE_LOG (0x14) 357 #define MPI2_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15) 358 #define MPI2_CONFIG_EXTPAGETYPE_RAID_CONFIG (0x16) 359 #define MPI2_CONFIG_EXTPAGETYPE_DRIVER_MAPPING (0x17) 360 #define MPI2_CONFIG_EXTPAGETYPE_SAS_PORT (0x18) 361 #define MPI2_CONFIG_EXTPAGETYPE_ETHERNET (0x19) 362 #define MPI2_CONFIG_EXTPAGETYPE_EXT_MANUFACTURING (0x1A) 363 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_IO_UNIT (0x1B) /* MPI v2.6 and later */ 364 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_SWITCH (0x1C) /* MPI v2.6 and later */ 365 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_DEVICE (0x1D) /* MPI v2.6 and later */ 366 #define MPI2_CONFIG_EXTPAGETYPE_PCIE_LINK (0x1E) /* MPI v2.6 and later */ 367 /* Product specific reserved values 0xE0 - 0xEF */ 368 /* Vendor specific reserved values 0xF0 - 0xFF */ 369 370 371 /***************************************************************************** 372 * PageAddress defines 373 *****************************************************************************/ 374 375 /* RAID Volume PageAddress format */ 376 #define MPI2_RAID_VOLUME_PGAD_FORM_MASK (0xF0000000) 377 #define MPI2_RAID_VOLUME_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 378 #define MPI2_RAID_VOLUME_PGAD_FORM_HANDLE (0x10000000) 379 380 #define MPI2_RAID_VOLUME_PGAD_HANDLE_MASK (0x0000FFFF) 381 382 383 /* RAID Physical Disk PageAddress format */ 384 #define MPI2_PHYSDISK_PGAD_FORM_MASK (0xF0000000) 385 #define MPI2_PHYSDISK_PGAD_FORM_GET_NEXT_PHYSDISKNUM (0x00000000) 386 #define MPI2_PHYSDISK_PGAD_FORM_PHYSDISKNUM (0x10000000) 387 #define MPI2_PHYSDISK_PGAD_FORM_DEVHANDLE (0x20000000) 388 389 #define MPI2_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF) 390 #define MPI2_PHYSDISK_PGAD_DEVHANDLE_MASK (0x0000FFFF) 391 392 393 /* SAS Expander PageAddress format */ 394 #define MPI2_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 395 #define MPI2_SAS_EXPAND_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 396 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL_PHY_NUM (0x10000000) 397 #define MPI2_SAS_EXPAND_PGAD_FORM_HNDL (0x20000000) 398 399 #define MPI2_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 400 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 401 #define MPI2_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 402 403 404 /* SAS Device PageAddress format */ 405 #define MPI2_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000) 406 #define MPI2_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 407 #define MPI2_SAS_DEVICE_PGAD_FORM_HANDLE (0x20000000) 408 409 #define MPI2_SAS_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 410 411 412 /* SAS PHY PageAddress format */ 413 #define MPI2_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 414 #define MPI2_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 415 #define MPI2_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x10000000) 416 417 #define MPI2_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 418 #define MPI2_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF) 419 420 421 /* SAS Port PageAddress format */ 422 #define MPI2_SASPORT_PGAD_FORM_MASK (0xF0000000) 423 #define MPI2_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 424 #define MPI2_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 425 426 #define MPI2_SASPORT_PGAD_PORTNUMBER_MASK (0x00000FFF) 427 428 429 /* SAS Enclosure PageAddress format */ 430 #define MPI2_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000) 431 #define MPI2_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 432 #define MPI2_SAS_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 433 434 #define MPI2_SAS_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 435 436 /* Enclosure PageAddress format */ 437 #define MPI26_ENCLOS_PGAD_FORM_MASK (0xF0000000) 438 #define MPI26_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 439 #define MPI26_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 440 441 #define MPI26_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 442 443 /* RAID Configuration PageAddress format */ 444 #define MPI2_RAID_PGAD_FORM_MASK (0xF0000000) 445 #define MPI2_RAID_PGAD_FORM_GET_NEXT_CONFIGNUM (0x00000000) 446 #define MPI2_RAID_PGAD_FORM_CONFIGNUM (0x10000000) 447 #define MPI2_RAID_PGAD_FORM_ACTIVE_CONFIG (0x20000000) 448 449 #define MPI2_RAID_PGAD_CONFIGNUM_MASK (0x000000FF) 450 451 452 /* Driver Persistent Mapping PageAddress format */ 453 #define MPI2_DPM_PGAD_FORM_MASK (0xF0000000) 454 #define MPI2_DPM_PGAD_FORM_ENTRY_RANGE (0x00000000) 455 456 #define MPI2_DPM_PGAD_ENTRY_COUNT_MASK (0x0FFF0000) 457 #define MPI2_DPM_PGAD_ENTRY_COUNT_SHIFT (16) 458 #define MPI2_DPM_PGAD_START_ENTRY_MASK (0x0000FFFF) 459 460 461 /* Ethernet PageAddress format */ 462 #define MPI2_ETHERNET_PGAD_FORM_MASK (0xF0000000) 463 #define MPI2_ETHERNET_PGAD_FORM_IF_NUM (0x00000000) 464 465 #define MPI2_ETHERNET_PGAD_IF_NUMBER_MASK (0x000000FF) 466 467 468 /* PCIe Switch PageAddress format */ 469 #define MPI26_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000) 470 #define MPI26_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HNDL (0x00000000) 471 #define MPI26_PCIE_SWITCH_PGAD_FORM_HNDL_PORTNUM (0x10000000) 472 #define MPI26_PCIE_SWITCH_EXPAND_PGAD_FORM_HNDL (0x20000000) 473 474 #define MPI26_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF) 475 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000) 476 #define MPI26_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) 477 478 479 /* PCIe Device PageAddress format */ 480 #define MPI26_PCIE_DEVICE_PGAD_FORM_MASK (0xF0000000) 481 #define MPI26_PCIE_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 482 #define MPI26_PCIE_DEVICE_PGAD_FORM_HANDLE (0x20000000) 483 484 #define MPI26_PCIE_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 485 486 /* PCIe Link PageAddress format */ 487 #define MPI26_PCIE_LINK_PGAD_FORM_MASK (0xF0000000) 488 #define MPI26_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) 489 #define MPI26_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) 490 491 #define MPI26_PCIE_DEVICE_PGAD_LINKNUM_MASK (0x000000FF) 492 493 494 495 /**************************************************************************** 496 * Configuration messages 497 ****************************************************************************/ 498 499 /* Configuration Request Message */ 500 typedef struct _MPI2_CONFIG_REQUEST 501 { 502 U8 Action; /* 0x00 */ 503 U8 SGLFlags; /* 0x01 */ 504 U8 ChainOffset; /* 0x02 */ 505 U8 Function; /* 0x03 */ 506 U16 ExtPageLength; /* 0x04 */ 507 U8 ExtPageType; /* 0x06 */ 508 U8 MsgFlags; /* 0x07 */ 509 U8 VP_ID; /* 0x08 */ 510 U8 VF_ID; /* 0x09 */ 511 U16 Reserved1; /* 0x0A */ 512 U8 Reserved2; /* 0x0C */ 513 U8 ProxyVF_ID; /* 0x0D */ 514 U16 Reserved4; /* 0x0E */ 515 U32 Reserved3; /* 0x10 */ 516 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 517 U32 PageAddress; /* 0x18 */ 518 MPI2_SGE_IO_UNION PageBufferSGE; /* 0x1C */ 519 } MPI2_CONFIG_REQUEST, MPI2_POINTER PTR_MPI2_CONFIG_REQUEST, 520 Mpi2ConfigRequest_t, MPI2_POINTER pMpi2ConfigRequest_t; 521 522 /* values for the Action field */ 523 #define MPI2_CONFIG_ACTION_PAGE_HEADER (0x00) 524 #define MPI2_CONFIG_ACTION_PAGE_READ_CURRENT (0x01) 525 #define MPI2_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02) 526 #define MPI2_CONFIG_ACTION_PAGE_DEFAULT (0x03) 527 #define MPI2_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04) 528 #define MPI2_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05) 529 #define MPI2_CONFIG_ACTION_PAGE_READ_NVRAM (0x06) 530 #define MPI2_CONFIG_ACTION_PAGE_GET_CHANGEABLE (0x07) 531 532 /* use MPI2_SGLFLAGS_ defines from mpi2.h for the SGLFlags field */ 533 534 535 /* Config Reply Message */ 536 typedef struct _MPI2_CONFIG_REPLY 537 { 538 U8 Action; /* 0x00 */ 539 U8 SGLFlags; /* 0x01 */ 540 U8 MsgLength; /* 0x02 */ 541 U8 Function; /* 0x03 */ 542 U16 ExtPageLength; /* 0x04 */ 543 U8 ExtPageType; /* 0x06 */ 544 U8 MsgFlags; /* 0x07 */ 545 U8 VP_ID; /* 0x08 */ 546 U8 VF_ID; /* 0x09 */ 547 U16 Reserved1; /* 0x0A */ 548 U16 Reserved2; /* 0x0C */ 549 U16 IOCStatus; /* 0x0E */ 550 U32 IOCLogInfo; /* 0x10 */ 551 MPI2_CONFIG_PAGE_HEADER Header; /* 0x14 */ 552 } MPI2_CONFIG_REPLY, MPI2_POINTER PTR_MPI2_CONFIG_REPLY, 553 Mpi2ConfigReply_t, MPI2_POINTER pMpi2ConfigReply_t; 554 555 556 557 /***************************************************************************** 558 * 559 * C o n f i g u r a t i o n P a g e s 560 * 561 *****************************************************************************/ 562 563 /**************************************************************************** 564 * Manufacturing Config pages 565 ****************************************************************************/ 566 567 #define MPI2_MFGPAGE_VENDORID_LSI (0x1000) 568 569 /* MPI v2.0 SAS products */ 570 #define MPI2_MFGPAGE_DEVID_SAS2004 (0x0070) 571 #define MPI2_MFGPAGE_DEVID_SAS2008 (0x0072) 572 #define MPI2_MFGPAGE_DEVID_SAS2108_1 (0x0074) 573 #define MPI2_MFGPAGE_DEVID_SAS2108_2 (0x0076) 574 #define MPI2_MFGPAGE_DEVID_SAS2108_3 (0x0077) 575 #define MPI2_MFGPAGE_DEVID_SAS2116_1 (0x0064) 576 #define MPI2_MFGPAGE_DEVID_SAS2116_2 (0x0065) 577 578 #define MPI2_MFGPAGE_DEVID_SSS6200 (0x007E) 579 580 #define MPI2_MFGPAGE_DEVID_SAS2208_1 (0x0080) 581 #define MPI2_MFGPAGE_DEVID_SAS2208_2 (0x0081) 582 #define MPI2_MFGPAGE_DEVID_SAS2208_3 (0x0082) 583 #define MPI2_MFGPAGE_DEVID_SAS2208_4 (0x0083) 584 #define MPI2_MFGPAGE_DEVID_SAS2208_5 (0x0084) 585 #define MPI2_MFGPAGE_DEVID_SAS2208_6 (0x0085) 586 #define MPI2_MFGPAGE_DEVID_SAS2308_1 (0x0086) 587 #define MPI2_MFGPAGE_DEVID_SAS2308_2 (0x0087) 588 #define MPI2_MFGPAGE_DEVID_SAS2308_3 (0x006E) 589 590 /* MPI v2.5 SAS products */ 591 #define MPI25_MFGPAGE_DEVID_SAS3004 (0x0096) 592 #define MPI25_MFGPAGE_DEVID_SAS3008 (0x0097) 593 #define MPI25_MFGPAGE_DEVID_SAS3108_1 (0x0090) 594 #define MPI25_MFGPAGE_DEVID_SAS3108_2 (0x0091) 595 #define MPI25_MFGPAGE_DEVID_SAS3108_5 (0x0094) 596 #define MPI25_MFGPAGE_DEVID_SAS3108_6 (0x0095) 597 598 /* MPI v2.6 SAS Products */ 599 #define MPI26_MFGPAGE_DEVID_SAS3216 (0x00C9) 600 #define MPI26_MFGPAGE_DEVID_SAS3224 (0x00C4) 601 #define MPI26_MFGPAGE_DEVID_SAS3316_1 (0x00C5) 602 #define MPI26_MFGPAGE_DEVID_SAS3316_2 (0x00C6) 603 #define MPI26_MFGPAGE_DEVID_SAS3316_3 (0x00C7) 604 #define MPI26_MFGPAGE_DEVID_SAS3316_4 (0x00C8) 605 #define MPI26_MFGPAGE_DEVID_SAS3324_1 (0x00C0) 606 #define MPI26_MFGPAGE_DEVID_SAS3324_2 (0x00C1) 607 #define MPI26_MFGPAGE_DEVID_SAS3324_3 (0x00C2) 608 #define MPI26_MFGPAGE_DEVID_SAS3324_4 (0x00C3) 609 610 #define MPI26_MFGPAGE_DEVID_SAS3516 (0x00AA) 611 #define MPI26_MFGPAGE_DEVID_SAS3516_1 (0x00AB) 612 #define MPI26_MFGPAGE_DEVID_SAS3416 (0x00AC) 613 #define MPI26_MFGPAGE_DEVID_SAS3508 (0x00AD) 614 #define MPI26_MFGPAGE_DEVID_SAS3508_1 (0x00AE) 615 #define MPI26_MFGPAGE_DEVID_SAS3408 (0x00AF) 616 617 #define MPI26_MFGPAGE_DEVID_SAS3716 (0x00D0) 618 #define MPI26_MFGPAGE_DEVID_SAS3616 (0x00D1) 619 #define MPI26_MFGPAGE_DEVID_SAS3708 (0x00D2) 620 621 #define MPI26_MFGPAGE_DEVID_SEC_MASK_SAS3916 (0x0003) 622 #define MPI26_MFGPAGE_DEVID_INVALID0_SAS3916 (0x00E0) 623 #define MPI26_MFGPAGE_DEVID_CFG_SEC_SAS3916 (0x00E1) 624 #define MPI26_MFGPAGE_DEVID_HARD_SEC_SAS3916 (0x00E2) 625 #define MPI26_MFGPAGE_DEVID_INVALID1_SAS3916 (0x00E3) 626 627 #define MPI26_MFGPAGE_DEVID_SEC_MASK_SAS3816 (0x0003) 628 #define MPI26_MFGPAGE_DEVID_INVALID0_SAS3816 (0x00E4) 629 #define MPI26_MFGPAGE_DEVID_CFG_SEC_SAS3816 (0x00E5) 630 #define MPI26_MFGPAGE_DEVID_HARD_SEC_SAS3816 (0x00E6) 631 #define MPI26_MFGPAGE_DEVID_INVALID1_SAS3816 (0x00E7) 632 633 634 /* Manufacturing Page 0 */ 635 636 typedef struct _MPI2_CONFIG_PAGE_MAN_0 637 { 638 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 639 U8 ChipName[16]; /* 0x04 */ 640 U8 ChipRevision[8]; /* 0x14 */ 641 U8 BoardName[16]; /* 0x1C */ 642 U8 BoardAssembly[16]; /* 0x2C */ 643 U8 BoardTracerNumber[16]; /* 0x3C */ 644 } MPI2_CONFIG_PAGE_MAN_0, 645 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_0, 646 Mpi2ManufacturingPage0_t, MPI2_POINTER pMpi2ManufacturingPage0_t; 647 648 #define MPI2_MANUFACTURING0_PAGEVERSION (0x00) 649 650 651 /* Manufacturing Page 1 */ 652 653 typedef struct _MPI2_CONFIG_PAGE_MAN_1 654 { 655 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 656 U8 VPD[256]; /* 0x04 */ 657 } MPI2_CONFIG_PAGE_MAN_1, 658 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_1, 659 Mpi2ManufacturingPage1_t, MPI2_POINTER pMpi2ManufacturingPage1_t; 660 661 #define MPI2_MANUFACTURING1_PAGEVERSION (0x00) 662 663 664 typedef struct _MPI2_CHIP_REVISION_ID 665 { 666 U16 DeviceID; /* 0x00 */ 667 U8 PCIRevisionID; /* 0x02 */ 668 U8 Reserved; /* 0x03 */ 669 } MPI2_CHIP_REVISION_ID, MPI2_POINTER PTR_MPI2_CHIP_REVISION_ID, 670 Mpi2ChipRevisionId_t, MPI2_POINTER pMpi2ChipRevisionId_t; 671 672 673 /* Manufacturing Page 2 */ 674 675 /* 676 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 677 * one and check Header.PageLength at runtime. 678 */ 679 #ifndef MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS 680 #define MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS (1) 681 #endif 682 683 typedef struct _MPI2_CONFIG_PAGE_MAN_2 684 { 685 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 686 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 687 U32 HwSettings[MPI2_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 0x08 */ 688 } MPI2_CONFIG_PAGE_MAN_2, 689 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_2, 690 Mpi2ManufacturingPage2_t, MPI2_POINTER pMpi2ManufacturingPage2_t; 691 692 #define MPI2_MANUFACTURING2_PAGEVERSION (0x00) 693 694 695 /* Manufacturing Page 3 */ 696 697 /* 698 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 699 * one and check Header.PageLength at runtime. 700 */ 701 #ifndef MPI2_MAN_PAGE_3_INFO_WORDS 702 #define MPI2_MAN_PAGE_3_INFO_WORDS (1) 703 #endif 704 705 typedef struct _MPI2_CONFIG_PAGE_MAN_3 706 { 707 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 708 MPI2_CHIP_REVISION_ID ChipId; /* 0x04 */ 709 U32 Info[MPI2_MAN_PAGE_3_INFO_WORDS];/* 0x08 */ 710 } MPI2_CONFIG_PAGE_MAN_3, 711 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_3, 712 Mpi2ManufacturingPage3_t, MPI2_POINTER pMpi2ManufacturingPage3_t; 713 714 #define MPI2_MANUFACTURING3_PAGEVERSION (0x00) 715 716 717 /* Manufacturing Page 4 */ 718 719 typedef struct _MPI2_MANPAGE4_PWR_SAVE_SETTINGS 720 { 721 U8 PowerSaveFlags; /* 0x00 */ 722 U8 InternalOperationsSleepTime; /* 0x01 */ 723 U8 InternalOperationsRunTime; /* 0x02 */ 724 U8 HostIdleTime; /* 0x03 */ 725 } MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 726 MPI2_POINTER PTR_MPI2_MANPAGE4_PWR_SAVE_SETTINGS, 727 Mpi2ManPage4PwrSaveSettings_t, MPI2_POINTER pMpi2ManPage4PwrSaveSettings_t; 728 729 /* defines for the PowerSaveFlags field */ 730 #define MPI2_MANPAGE4_MASK_POWERSAVE_MODE (0x03) 731 #define MPI2_MANPAGE4_POWERSAVE_MODE_DISABLED (0x00) 732 #define MPI2_MANPAGE4_CUSTOM_POWERSAVE_MODE (0x01) 733 #define MPI2_MANPAGE4_FULL_POWERSAVE_MODE (0x02) 734 735 typedef struct _MPI2_CONFIG_PAGE_MAN_4 736 { 737 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 738 U32 Reserved1; /* 0x04 */ 739 U32 Flags; /* 0x08 */ 740 U8 InquirySize; /* 0x0C */ 741 U8 Reserved2; /* 0x0D */ 742 U16 Reserved3; /* 0x0E */ 743 U8 InquiryData[56]; /* 0x10 */ 744 U32 RAID0VolumeSettings; /* 0x48 */ 745 U32 RAID1EVolumeSettings; /* 0x4C */ 746 U32 RAID1VolumeSettings; /* 0x50 */ 747 U32 RAID10VolumeSettings; /* 0x54 */ 748 U32 Reserved4; /* 0x58 */ 749 U32 Reserved5; /* 0x5C */ 750 MPI2_MANPAGE4_PWR_SAVE_SETTINGS PowerSaveSettings; /* 0x60 */ 751 U8 MaxOCEDisks; /* 0x64 */ 752 U8 ResyncRate; /* 0x65 */ 753 U16 DataScrubDuration; /* 0x66 */ 754 U8 MaxHotSpares; /* 0x68 */ 755 U8 MaxPhysDisksPerVol; /* 0x69 */ 756 U8 MaxPhysDisks; /* 0x6A */ 757 U8 MaxVolumes; /* 0x6B */ 758 } MPI2_CONFIG_PAGE_MAN_4, 759 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_4, 760 Mpi2ManufacturingPage4_t, MPI2_POINTER pMpi2ManufacturingPage4_t; 761 762 #define MPI2_MANUFACTURING4_PAGEVERSION (0x0A) 763 764 /* Manufacturing Page 4 Flags field */ 765 #define MPI2_MANPAGE4_METADATA_SIZE_MASK (0x00030000) 766 #define MPI2_MANPAGE4_METADATA_512MB (0x00000000) 767 768 #define MPI2_MANPAGE4_MIX_SSD_SAS_SATA (0x00008000) 769 #define MPI2_MANPAGE4_MIX_SSD_AND_NON_SSD (0x00004000) 770 #define MPI2_MANPAGE4_HIDE_PHYSDISK_NON_IR (0x00002000) 771 772 #define MPI2_MANPAGE4_MASK_PHYSDISK_COERCION (0x00001C00) 773 #define MPI2_MANPAGE4_PHYSDISK_COERCION_1GB (0x00000000) 774 #define MPI2_MANPAGE4_PHYSDISK_128MB_COERCION (0x00000400) 775 #define MPI2_MANPAGE4_PHYSDISK_ADAPTIVE_COERCION (0x00000800) 776 #define MPI2_MANPAGE4_PHYSDISK_ZERO_COERCION (0x00000C00) 777 778 #define MPI2_MANPAGE4_MASK_BAD_BLOCK_MARKING (0x00000300) 779 #define MPI2_MANPAGE4_DEFAULT_BAD_BLOCK_MARKING (0x00000000) 780 #define MPI2_MANPAGE4_TABLE_BAD_BLOCK_MARKING (0x00000100) 781 #define MPI2_MANPAGE4_WRITE_LONG_BAD_BLOCK_MARKING (0x00000200) 782 783 #define MPI2_MANPAGE4_FORCE_OFFLINE_FAILOVER (0x00000080) 784 #define MPI2_MANPAGE4_RAID10_DISABLE (0x00000040) 785 #define MPI2_MANPAGE4_RAID1E_DISABLE (0x00000020) 786 #define MPI2_MANPAGE4_RAID1_DISABLE (0x00000010) 787 #define MPI2_MANPAGE4_RAID0_DISABLE (0x00000008) 788 #define MPI2_MANPAGE4_IR_MODEPAGE8_DISABLE (0x00000004) 789 #define MPI2_MANPAGE4_IM_RESYNC_CACHE_ENABLE (0x00000002) 790 #define MPI2_MANPAGE4_IR_NO_MIX_SAS_SATA (0x00000001) 791 792 793 /* Manufacturing Page 5 */ 794 795 /* 796 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 797 * one and check the value returned for NumPhys at runtime. 798 */ 799 #ifndef MPI2_MAN_PAGE_5_PHY_ENTRIES 800 #define MPI2_MAN_PAGE_5_PHY_ENTRIES (1) 801 #endif 802 803 typedef struct _MPI2_MANUFACTURING5_ENTRY 804 { 805 U64 WWID; /* 0x00 */ 806 U64 DeviceName; /* 0x08 */ 807 } MPI2_MANUFACTURING5_ENTRY, MPI2_POINTER PTR_MPI2_MANUFACTURING5_ENTRY, 808 Mpi2Manufacturing5Entry_t, MPI2_POINTER pMpi2Manufacturing5Entry_t; 809 810 typedef struct _MPI2_CONFIG_PAGE_MAN_5 811 { 812 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 813 U8 NumPhys; /* 0x04 */ 814 U8 Reserved1; /* 0x05 */ 815 U16 Reserved2; /* 0x06 */ 816 U32 Reserved3; /* 0x08 */ 817 U32 Reserved4; /* 0x0C */ 818 MPI2_MANUFACTURING5_ENTRY Phy[MPI2_MAN_PAGE_5_PHY_ENTRIES];/* 0x08 */ 819 } MPI2_CONFIG_PAGE_MAN_5, 820 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_5, 821 Mpi2ManufacturingPage5_t, MPI2_POINTER pMpi2ManufacturingPage5_t; 822 823 #define MPI2_MANUFACTURING5_PAGEVERSION (0x03) 824 825 826 /* Manufacturing Page 6 */ 827 828 typedef struct _MPI2_CONFIG_PAGE_MAN_6 829 { 830 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 831 U32 ProductSpecificInfo;/* 0x04 */ 832 } MPI2_CONFIG_PAGE_MAN_6, 833 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_6, 834 Mpi2ManufacturingPage6_t, MPI2_POINTER pMpi2ManufacturingPage6_t; 835 836 #define MPI2_MANUFACTURING6_PAGEVERSION (0x00) 837 838 839 /* Manufacturing Page 7 */ 840 841 typedef struct _MPI2_MANPAGE7_CONNECTOR_INFO 842 { 843 U32 Pinout; /* 0x00 */ 844 U8 Connector[16]; /* 0x04 */ 845 U8 Location; /* 0x14 */ 846 U8 ReceptacleID; /* 0x15 */ 847 U16 Slot; /* 0x16 */ 848 U16 Slotx4; /* 0x18 */ 849 U16 Slotx2; /* 0x1A */ 850 } MPI2_MANPAGE7_CONNECTOR_INFO, MPI2_POINTER PTR_MPI2_MANPAGE7_CONNECTOR_INFO, 851 Mpi2ManPage7ConnectorInfo_t, MPI2_POINTER pMpi2ManPage7ConnectorInfo_t; 852 853 /* defines for the Pinout field */ 854 #define MPI2_MANPAGE7_PINOUT_LANE_MASK (0x0000FF00) 855 #define MPI2_MANPAGE7_PINOUT_LANE_SHIFT (8) 856 857 #define MPI2_MANPAGE7_PINOUT_TYPE_MASK (0x000000FF) 858 #define MPI2_MANPAGE7_PINOUT_TYPE_UNKNOWN (0x00) 859 #define MPI2_MANPAGE7_PINOUT_SATA_SINGLE (0x01) 860 #define MPI2_MANPAGE7_PINOUT_SFF_8482 (0x02) 861 #define MPI2_MANPAGE7_PINOUT_SFF_8486 (0x03) 862 #define MPI2_MANPAGE7_PINOUT_SFF_8484 (0x04) 863 #define MPI2_MANPAGE7_PINOUT_SFF_8087 (0x05) 864 #define MPI2_MANPAGE7_PINOUT_SFF_8643_4I (0x06) 865 #define MPI2_MANPAGE7_PINOUT_SFF_8643_8I (0x07) 866 #define MPI2_MANPAGE7_PINOUT_SFF_8470 (0x08) 867 #define MPI2_MANPAGE7_PINOUT_SFF_8088 (0x09) 868 #define MPI2_MANPAGE7_PINOUT_SFF_8644_4X (0x0A) 869 #define MPI2_MANPAGE7_PINOUT_SFF_8644_8X (0x0B) 870 #define MPI2_MANPAGE7_PINOUT_SFF_8644_16X (0x0C) 871 #define MPI2_MANPAGE7_PINOUT_SFF_8436 (0x0D) 872 #define MPI2_MANPAGE7_PINOUT_SFF_8088_A (0x0E) 873 #define MPI2_MANPAGE7_PINOUT_SFF_8643_16i (0x0F) 874 #define MPI2_MANPAGE7_PINOUT_SFF_8654_4i (0x10) 875 #define MPI2_MANPAGE7_PINOUT_SFF_8654_8i (0x11) 876 #define MPI2_MANPAGE7_PINOUT_SFF_8611_4i (0x12) 877 #define MPI2_MANPAGE7_PINOUT_SFF_8611_8i (0x13) 878 879 /* defines for the Location field */ 880 #define MPI2_MANPAGE7_LOCATION_UNKNOWN (0x01) 881 #define MPI2_MANPAGE7_LOCATION_INTERNAL (0x02) 882 #define MPI2_MANPAGE7_LOCATION_EXTERNAL (0x04) 883 #define MPI2_MANPAGE7_LOCATION_SWITCHABLE (0x08) 884 #define MPI2_MANPAGE7_LOCATION_AUTO (0x10) 885 #define MPI2_MANPAGE7_LOCATION_NOT_PRESENT (0x20) 886 #define MPI2_MANPAGE7_LOCATION_NOT_CONNECTED (0x80) 887 888 /* defines for the Slot field */ 889 #define MPI2_MANPAGE7_SLOT_UNKNOWN (0xFFFF) 890 891 /* 892 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 893 * one and check the value returned for NumPhys at runtime. 894 */ 895 #ifndef MPI2_MANPAGE7_CONNECTOR_INFO_MAX 896 #define MPI2_MANPAGE7_CONNECTOR_INFO_MAX (1) 897 #endif 898 899 typedef struct _MPI2_CONFIG_PAGE_MAN_7 900 { 901 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 902 U32 Reserved1; /* 0x04 */ 903 U32 Reserved2; /* 0x08 */ 904 U32 Flags; /* 0x0C */ 905 U8 EnclosureName[16]; /* 0x10 */ 906 U8 NumPhys; /* 0x20 */ 907 U8 Reserved3; /* 0x21 */ 908 U16 Reserved4; /* 0x22 */ 909 MPI2_MANPAGE7_CONNECTOR_INFO ConnectorInfo[MPI2_MANPAGE7_CONNECTOR_INFO_MAX]; /* 0x24 */ 910 } MPI2_CONFIG_PAGE_MAN_7, 911 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_7, 912 Mpi2ManufacturingPage7_t, MPI2_POINTER pMpi2ManufacturingPage7_t; 913 914 #define MPI2_MANUFACTURING7_PAGEVERSION (0x01) 915 916 /* defines for the Flags field */ 917 #define MPI2_MANPAGE7_FLAG_BASE_ENCLOSURE_LEVEL (0x00000008) 918 #define MPI2_MANPAGE7_FLAG_EVENTREPLAY_SLOT_ORDER (0x00000002) 919 #define MPI2_MANPAGE7_FLAG_USE_SLOT_INFO (0x00000001) 920 921 922 /* 923 * Generic structure to use for product-specific manufacturing pages 924 * (currently Manufacturing Page 8 through Manufacturing Page 31). 925 */ 926 927 typedef struct _MPI2_CONFIG_PAGE_MAN_PS 928 { 929 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 930 U32 ProductSpecificInfo;/* 0x04 */ 931 } MPI2_CONFIG_PAGE_MAN_PS, 932 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_MAN_PS, 933 Mpi2ManufacturingPagePS_t, MPI2_POINTER pMpi2ManufacturingPagePS_t; 934 935 #define MPI2_MANUFACTURING8_PAGEVERSION (0x00) 936 #define MPI2_MANUFACTURING9_PAGEVERSION (0x00) 937 #define MPI2_MANUFACTURING10_PAGEVERSION (0x00) 938 #define MPI2_MANUFACTURING11_PAGEVERSION (0x00) 939 #define MPI2_MANUFACTURING12_PAGEVERSION (0x00) 940 #define MPI2_MANUFACTURING13_PAGEVERSION (0x00) 941 #define MPI2_MANUFACTURING14_PAGEVERSION (0x00) 942 #define MPI2_MANUFACTURING15_PAGEVERSION (0x00) 943 #define MPI2_MANUFACTURING16_PAGEVERSION (0x00) 944 #define MPI2_MANUFACTURING17_PAGEVERSION (0x00) 945 #define MPI2_MANUFACTURING18_PAGEVERSION (0x00) 946 #define MPI2_MANUFACTURING19_PAGEVERSION (0x00) 947 #define MPI2_MANUFACTURING20_PAGEVERSION (0x00) 948 #define MPI2_MANUFACTURING21_PAGEVERSION (0x00) 949 #define MPI2_MANUFACTURING22_PAGEVERSION (0x00) 950 #define MPI2_MANUFACTURING23_PAGEVERSION (0x00) 951 #define MPI2_MANUFACTURING24_PAGEVERSION (0x00) 952 #define MPI2_MANUFACTURING25_PAGEVERSION (0x00) 953 #define MPI2_MANUFACTURING26_PAGEVERSION (0x00) 954 #define MPI2_MANUFACTURING27_PAGEVERSION (0x00) 955 #define MPI2_MANUFACTURING28_PAGEVERSION (0x00) 956 #define MPI2_MANUFACTURING29_PAGEVERSION (0x00) 957 #define MPI2_MANUFACTURING30_PAGEVERSION (0x00) 958 #define MPI2_MANUFACTURING31_PAGEVERSION (0x00) 959 960 961 /**************************************************************************** 962 * IO Unit Config Pages 963 ****************************************************************************/ 964 965 /* IO Unit Page 0 */ 966 967 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_0 968 { 969 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 970 U64 UniqueValue; /* 0x04 */ 971 MPI2_VERSION_UNION NvdataVersionDefault; /* 0x08 */ 972 MPI2_VERSION_UNION NvdataVersionPersistent; /* 0x0A */ 973 } MPI2_CONFIG_PAGE_IO_UNIT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_0, 974 Mpi2IOUnitPage0_t, MPI2_POINTER pMpi2IOUnitPage0_t; 975 976 #define MPI2_IOUNITPAGE0_PAGEVERSION (0x02) 977 978 979 /* IO Unit Page 1 */ 980 981 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_1 982 { 983 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 984 U32 Flags; /* 0x04 */ 985 } MPI2_CONFIG_PAGE_IO_UNIT_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_1, 986 Mpi2IOUnitPage1_t, MPI2_POINTER pMpi2IOUnitPage1_t; 987 988 #define MPI2_IOUNITPAGE1_PAGEVERSION (0x04) 989 990 /* IO Unit Page 1 Flags defines */ 991 #define MPI26_IOUNITPAGE1_NVME_WRITE_CACHE_MASK (0x00030000) 992 #define MPI26_IOUNITPAGE1_NVME_WRITE_CACHE_ENABLE (0x00000000) 993 #define MPI26_IOUNITPAGE1_NVME_WRITE_CACHE_DISABLE (0x00010000) 994 #define MPI26_IOUNITPAGE1_NVME_WRITE_CACHE_NO_CHANGE (0x00020000) 995 #define MPI2_IOUNITPAGE1_ATA_SECURITY_FREEZE_LOCK (0x00004000) 996 #define MPI25_IOUNITPAGE1_NEW_DEVICE_FAST_PATH_DISABLE (0x00002000) 997 #define MPI25_IOUNITPAGE1_DISABLE_FAST_PATH (0x00001000) 998 #define MPI2_IOUNITPAGE1_ENABLE_HOST_BASED_DISCOVERY (0x00000800) 999 #define MPI2_IOUNITPAGE1_MASK_SATA_WRITE_CACHE (0x00000600) 1000 #define MPI2_IOUNITPAGE1_SATA_WRITE_CACHE_SHIFT (9) 1001 #define MPI2_IOUNITPAGE1_ENABLE_SATA_WRITE_CACHE (0x00000000) 1002 #define MPI2_IOUNITPAGE1_DISABLE_SATA_WRITE_CACHE (0x00000200) 1003 #define MPI2_IOUNITPAGE1_UNCHANGED_SATA_WRITE_CACHE (0x00000400) 1004 #define MPI2_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100) 1005 #define MPI2_IOUNITPAGE1_DISABLE_IR (0x00000040) 1006 #define MPI2_IOUNITPAGE1_DISABLE_TASK_SET_FULL_HANDLING (0x00000020) 1007 #define MPI2_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004) 1008 1009 1010 /* IO Unit Page 3 */ 1011 1012 /* 1013 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1014 * one and check the value returned for GPIOCount at runtime. 1015 */ 1016 #ifndef MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX 1017 #define MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1) 1018 #endif 1019 1020 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_3 1021 { 1022 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1023 U8 GPIOCount; /* 0x04 */ 1024 U8 Reserved1; /* 0x05 */ 1025 U16 Reserved2; /* 0x06 */ 1026 U16 GPIOVal[MPI2_IO_UNIT_PAGE_3_GPIO_VAL_MAX];/* 0x08 */ 1027 } MPI2_CONFIG_PAGE_IO_UNIT_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_3, 1028 Mpi2IOUnitPage3_t, MPI2_POINTER pMpi2IOUnitPage3_t; 1029 1030 #define MPI2_IOUNITPAGE3_PAGEVERSION (0x01) 1031 1032 /* defines for IO Unit Page 3 GPIOVal field */ 1033 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFFFC) 1034 #define MPI2_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2) 1035 #define MPI2_IOUNITPAGE3_GPIO_SETTING_OFF (0x0000) 1036 #define MPI2_IOUNITPAGE3_GPIO_SETTING_ON (0x0001) 1037 1038 1039 /* IO Unit Page 5 */ 1040 1041 /* 1042 * Upper layer code (drivers, utilities, etc.) should leave this define set to 1043 * one and check the value returned for NumDmaEngines at runtime. 1044 */ 1045 #ifndef MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES 1046 #define MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES (1) 1047 #endif 1048 1049 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_5 1050 { 1051 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1052 U64 RaidAcceleratorBufferBaseAddress; /* 0x04 */ 1053 U64 RaidAcceleratorBufferSize; /* 0x0C */ 1054 U64 RaidAcceleratorControlBaseAddress; /* 0x14 */ 1055 U8 RAControlSize; /* 0x1C */ 1056 U8 NumDmaEngines; /* 0x1D */ 1057 U8 RAMinControlSize; /* 0x1E */ 1058 U8 RAMaxControlSize; /* 0x1F */ 1059 U32 Reserved1; /* 0x20 */ 1060 U32 Reserved2; /* 0x24 */ 1061 U32 Reserved3; /* 0x28 */ 1062 U32 DmaEngineCapabilities[MPI2_IOUNITPAGE5_DMAENGINE_ENTRIES]; /* 0x2C */ 1063 } MPI2_CONFIG_PAGE_IO_UNIT_5, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_5, 1064 Mpi2IOUnitPage5_t, MPI2_POINTER pMpi2IOUnitPage5_t; 1065 1066 #define MPI2_IOUNITPAGE5_PAGEVERSION (0x00) 1067 1068 /* defines for IO Unit Page 5 DmaEngineCapabilities field */ 1069 #define MPI2_IOUNITPAGE5_DMA_CAP_MASK_MAX_REQUESTS (0xFFFF0000) 1070 #define MPI2_IOUNITPAGE5_DMA_CAP_SHIFT_MAX_REQUESTS (16) 1071 1072 #define MPI2_IOUNITPAGE5_DMA_CAP_EEDP (0x0008) 1073 #define MPI2_IOUNITPAGE5_DMA_CAP_PARITY_GENERATION (0x0004) 1074 #define MPI2_IOUNITPAGE5_DMA_CAP_HASHING (0x0002) 1075 #define MPI2_IOUNITPAGE5_DMA_CAP_ENCRYPTION (0x0001) 1076 1077 1078 /* IO Unit Page 6 */ 1079 1080 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_6 1081 { 1082 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1083 U16 Flags; /* 0x04 */ 1084 U8 RAHostControlSize; /* 0x06 */ 1085 U8 Reserved0; /* 0x07 */ 1086 U64 RaidAcceleratorHostControlBaseAddress; /* 0x08 */ 1087 U32 Reserved1; /* 0x10 */ 1088 U32 Reserved2; /* 0x14 */ 1089 U32 Reserved3; /* 0x18 */ 1090 } MPI2_CONFIG_PAGE_IO_UNIT_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_6, 1091 Mpi2IOUnitPage6_t, MPI2_POINTER pMpi2IOUnitPage6_t; 1092 1093 #define MPI2_IOUNITPAGE6_PAGEVERSION (0x00) 1094 1095 /* defines for IO Unit Page 6 Flags field */ 1096 #define MPI2_IOUNITPAGE6_FLAGS_ENABLE_RAID_ACCELERATOR (0x0001) 1097 1098 1099 /* IO Unit Page 7 */ 1100 1101 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_7 1102 { 1103 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1104 U8 CurrentPowerMode; /* 0x04 */ /* reserved in MPI 2.0 */ 1105 U8 PreviousPowerMode; /* 0x05 */ /* reserved in MPI 2.0 */ 1106 U8 PCIeWidth; /* 0x06 */ 1107 U8 PCIeSpeed; /* 0x07 */ 1108 U32 ProcessorState; /* 0x08 */ 1109 U32 PowerManagementCapabilities; /* 0x0C */ 1110 U16 IOCTemperature; /* 0x10 */ 1111 U8 IOCTemperatureUnits; /* 0x12 */ 1112 U8 IOCSpeed; /* 0x13 */ 1113 U16 BoardTemperature; /* 0x14 */ 1114 U8 BoardTemperatureUnits; /* 0x16 */ 1115 U8 Reserved3; /* 0x17 */ 1116 U32 BoardPowerRequirement; /* 0x18 */ /* reserved prior to MPI v2.6 */ 1117 U32 PCISlotPowerAllocation; /* 0x1C */ /* reserved prior to MPI v2.6 */ 1118 U8 Flags; /* 0x20 */ /* reserved prior to MPI v2.6 */ 1119 U8 Reserved6; /* 0x21 */ 1120 U16 Reserved7; /* 0x22 */ 1121 U32 Reserved8; /* 0x24 */ 1122 } MPI2_CONFIG_PAGE_IO_UNIT_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_7, 1123 Mpi2IOUnitPage7_t, MPI2_POINTER pMpi2IOUnitPage7_t; 1124 1125 #define MPI2_IOUNITPAGE7_PAGEVERSION (0x05) 1126 1127 /* defines for IO Unit Page 7 CurrentPowerMode and PreviousPowerMode fields */ 1128 #define MPI25_IOUNITPAGE7_PM_INIT_MASK (0xC0) 1129 #define MPI25_IOUNITPAGE7_PM_INIT_UNAVAILABLE (0x00) 1130 #define MPI25_IOUNITPAGE7_PM_INIT_HOST (0x40) 1131 #define MPI25_IOUNITPAGE7_PM_INIT_IO_UNIT (0x80) 1132 #define MPI25_IOUNITPAGE7_PM_INIT_PCIE_DPA (0xC0) 1133 1134 #define MPI25_IOUNITPAGE7_PM_MODE_MASK (0x07) 1135 #define MPI25_IOUNITPAGE7_PM_MODE_UNAVAILABLE (0x00) 1136 #define MPI25_IOUNITPAGE7_PM_MODE_UNKNOWN (0x01) 1137 #define MPI25_IOUNITPAGE7_PM_MODE_FULL_POWER (0x04) 1138 #define MPI25_IOUNITPAGE7_PM_MODE_REDUCED_POWER (0x05) 1139 #define MPI25_IOUNITPAGE7_PM_MODE_STANDBY (0x06) 1140 1141 1142 /* defines for IO Unit Page 7 PCIeWidth field */ 1143 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X1 (0x01) 1144 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X2 (0x02) 1145 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X4 (0x04) 1146 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X8 (0x08) 1147 #define MPI2_IOUNITPAGE7_PCIE_WIDTH_X16 (0x10) 1148 1149 /* defines for IO Unit Page 7 PCIeSpeed field */ 1150 #define MPI2_IOUNITPAGE7_PCIE_SPEED_2_5_GBPS (0x00) 1151 #define MPI2_IOUNITPAGE7_PCIE_SPEED_5_0_GBPS (0x01) 1152 #define MPI2_IOUNITPAGE7_PCIE_SPEED_8_0_GBPS (0x02) 1153 #define MPI2_IOUNITPAGE7_PCIE_SPEED_16_0_GBPS (0x03) 1154 1155 /* defines for IO Unit Page 7 ProcessorState field */ 1156 #define MPI2_IOUNITPAGE7_PSTATE_MASK_SECOND (0x0000000F) 1157 #define MPI2_IOUNITPAGE7_PSTATE_SHIFT_SECOND (0) 1158 1159 #define MPI2_IOUNITPAGE7_PSTATE_NOT_PRESENT (0x00) 1160 #define MPI2_IOUNITPAGE7_PSTATE_DISABLED (0x01) 1161 #define MPI2_IOUNITPAGE7_PSTATE_ENABLED (0x02) 1162 1163 /* defines for IO Unit Page 7 PowerManagementCapabilities field */ 1164 #define MPI25_IOUNITPAGE7_PMCAP_DPA_FULL_PWR_MODE (0x00400000) 1165 #define MPI25_IOUNITPAGE7_PMCAP_DPA_REDUCED_PWR_MODE (0x00200000) 1166 #define MPI25_IOUNITPAGE7_PMCAP_DPA_STANDBY_MODE (0x00100000) 1167 #define MPI25_IOUNITPAGE7_PMCAP_HOST_FULL_PWR_MODE (0x00040000) 1168 #define MPI25_IOUNITPAGE7_PMCAP_HOST_REDUCED_PWR_MODE (0x00020000) 1169 #define MPI25_IOUNITPAGE7_PMCAP_HOST_STANDBY_MODE (0x00010000) 1170 #define MPI25_IOUNITPAGE7_PMCAP_IO_FULL_PWR_MODE (0x00004000) 1171 #define MPI25_IOUNITPAGE7_PMCAP_IO_REDUCED_PWR_MODE (0x00002000) 1172 #define MPI25_IOUNITPAGE7_PMCAP_IO_STANDBY_MODE (0x00001000) 1173 #define MPI2_IOUNITPAGE7_PMCAP_HOST_12_5_PCT_IOCSPEED (0x00000400) 1174 #define MPI2_IOUNITPAGE7_PMCAP_HOST_25_0_PCT_IOCSPEED (0x00000200) 1175 #define MPI2_IOUNITPAGE7_PMCAP_HOST_50_0_PCT_IOCSPEED (0x00000100) 1176 #define MPI25_IOUNITPAGE7_PMCAP_IO_12_5_PCT_IOCSPEED (0x00000040) 1177 #define MPI25_IOUNITPAGE7_PMCAP_IO_25_0_PCT_IOCSPEED (0x00000020) 1178 #define MPI25_IOUNITPAGE7_PMCAP_IO_50_0_PCT_IOCSPEED (0x00000010) 1179 #define MPI2_IOUNITPAGE7_PMCAP_HOST_WIDTH_CHANGE_PCIE (0x00000008) /* obsolete */ 1180 #define MPI2_IOUNITPAGE7_PMCAP_HOST_SPEED_CHANGE_PCIE (0x00000004) /* obsolete */ 1181 #define MPI25_IOUNITPAGE7_PMCAP_IO_WIDTH_CHANGE_PCIE (0x00000002) /* obsolete */ 1182 #define MPI25_IOUNITPAGE7_PMCAP_IO_SPEED_CHANGE_PCIE (0x00000001) /* obsolete */ 1183 1184 /* obsolete names for the PowerManagementCapabilities bits (above) */ 1185 #define MPI2_IOUNITPAGE7_PMCAP_12_5_PCT_IOCSPEED (0x00000400) 1186 #define MPI2_IOUNITPAGE7_PMCAP_25_0_PCT_IOCSPEED (0x00000200) 1187 #define MPI2_IOUNITPAGE7_PMCAP_50_0_PCT_IOCSPEED (0x00000100) 1188 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_WIDTH_CHANGE (0x00000008) /* obsolete */ 1189 #define MPI2_IOUNITPAGE7_PMCAP_PCIE_SPEED_CHANGE (0x00000004) /* obsolete */ 1190 1191 1192 /* defines for IO Unit Page 7 IOCTemperatureUnits field */ 1193 #define MPI2_IOUNITPAGE7_IOC_TEMP_NOT_PRESENT (0x00) 1194 #define MPI2_IOUNITPAGE7_IOC_TEMP_FAHRENHEIT (0x01) 1195 #define MPI2_IOUNITPAGE7_IOC_TEMP_CELSIUS (0x02) 1196 1197 /* defines for IO Unit Page 7 IOCSpeed field */ 1198 #define MPI2_IOUNITPAGE7_IOC_SPEED_FULL (0x01) 1199 #define MPI2_IOUNITPAGE7_IOC_SPEED_HALF (0x02) 1200 #define MPI2_IOUNITPAGE7_IOC_SPEED_QUARTER (0x04) 1201 #define MPI2_IOUNITPAGE7_IOC_SPEED_EIGHTH (0x08) 1202 1203 /* defines for IO Unit Page 7 BoardTemperatureUnits field */ 1204 #define MPI2_IOUNITPAGE7_BOARD_TEMP_NOT_PRESENT (0x00) 1205 #define MPI2_IOUNITPAGE7_BOARD_TEMP_FAHRENHEIT (0x01) 1206 #define MPI2_IOUNITPAGE7_BOARD_TEMP_CELSIUS (0x02) 1207 1208 /* defines for IO Unit Page 7 Flags field */ 1209 #define MPI2_IOUNITPAGE7_FLAG_CABLE_POWER_EXC (0x01) 1210 1211 1212 /* IO Unit Page 8 */ 1213 1214 #define MPI2_IOUNIT8_NUM_THRESHOLDS (4) 1215 1216 typedef struct _MPI2_IOUNIT8_SENSOR 1217 { 1218 U16 Flags; /* 0x00 */ 1219 U16 Reserved1; /* 0x02 */ 1220 U16 Threshold[MPI2_IOUNIT8_NUM_THRESHOLDS]; /* 0x04 */ 1221 U32 Reserved2; /* 0x0C */ 1222 U32 Reserved3; /* 0x10 */ 1223 U32 Reserved4; /* 0x14 */ 1224 } MPI2_IOUNIT8_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT8_SENSOR, 1225 Mpi2IOUnit8Sensor_t, MPI2_POINTER pMpi2IOUnit8Sensor_t; 1226 1227 /* defines for IO Unit Page 8 Sensor Flags field */ 1228 #define MPI2_IOUNIT8_SENSOR_FLAGS_T3_ENABLE (0x0008) 1229 #define MPI2_IOUNIT8_SENSOR_FLAGS_T2_ENABLE (0x0004) 1230 #define MPI2_IOUNIT8_SENSOR_FLAGS_T1_ENABLE (0x0002) 1231 #define MPI2_IOUNIT8_SENSOR_FLAGS_T0_ENABLE (0x0001) 1232 1233 /* 1234 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1235 * one and check the value returned for NumSensors at runtime. 1236 */ 1237 #ifndef MPI2_IOUNITPAGE8_SENSOR_ENTRIES 1238 #define MPI2_IOUNITPAGE8_SENSOR_ENTRIES (1) 1239 #endif 1240 1241 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_8 1242 { 1243 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1244 U32 Reserved1; /* 0x04 */ 1245 U32 Reserved2; /* 0x08 */ 1246 U8 NumSensors; /* 0x0C */ 1247 U8 PollingInterval; /* 0x0D */ 1248 U16 Reserved3; /* 0x0E */ 1249 MPI2_IOUNIT8_SENSOR Sensor[MPI2_IOUNITPAGE8_SENSOR_ENTRIES];/* 0x10 */ 1250 } MPI2_CONFIG_PAGE_IO_UNIT_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_8, 1251 Mpi2IOUnitPage8_t, MPI2_POINTER pMpi2IOUnitPage8_t; 1252 1253 #define MPI2_IOUNITPAGE8_PAGEVERSION (0x00) 1254 1255 1256 /* IO Unit Page 9 */ 1257 1258 typedef struct _MPI2_IOUNIT9_SENSOR 1259 { 1260 U16 CurrentTemperature; /* 0x00 */ 1261 U16 Reserved1; /* 0x02 */ 1262 U8 Flags; /* 0x04 */ 1263 U8 Reserved2; /* 0x05 */ 1264 U16 Reserved3; /* 0x06 */ 1265 U32 Reserved4; /* 0x08 */ 1266 U32 Reserved5; /* 0x0C */ 1267 } MPI2_IOUNIT9_SENSOR, MPI2_POINTER PTR_MPI2_IOUNIT9_SENSOR, 1268 Mpi2IOUnit9Sensor_t, MPI2_POINTER pMpi2IOUnit9Sensor_t; 1269 1270 /* defines for IO Unit Page 9 Sensor Flags field */ 1271 #define MPI2_IOUNIT9_SENSOR_FLAGS_TEMP_VALID (0x01) 1272 1273 /* 1274 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1275 * one and check the value returned for NumSensors at runtime. 1276 */ 1277 #ifndef MPI2_IOUNITPAGE9_SENSOR_ENTRIES 1278 #define MPI2_IOUNITPAGE9_SENSOR_ENTRIES (1) 1279 #endif 1280 1281 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_9 1282 { 1283 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1284 U32 Reserved1; /* 0x04 */ 1285 U32 Reserved2; /* 0x08 */ 1286 U8 NumSensors; /* 0x0C */ 1287 U8 Reserved4; /* 0x0D */ 1288 U16 Reserved3; /* 0x0E */ 1289 MPI2_IOUNIT9_SENSOR Sensor[MPI2_IOUNITPAGE9_SENSOR_ENTRIES];/* 0x10 */ 1290 } MPI2_CONFIG_PAGE_IO_UNIT_9, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_9, 1291 Mpi2IOUnitPage9_t, MPI2_POINTER pMpi2IOUnitPage9_t; 1292 1293 #define MPI2_IOUNITPAGE9_PAGEVERSION (0x00) 1294 1295 1296 /* IO Unit Page 10 */ 1297 1298 typedef struct _MPI2_IOUNIT10_FUNCTION 1299 { 1300 U8 CreditPercent; /* 0x00 */ 1301 U8 Reserved1; /* 0x01 */ 1302 U16 Reserved2; /* 0x02 */ 1303 } MPI2_IOUNIT10_FUNCTION, MPI2_POINTER PTR_MPI2_IOUNIT10_FUNCTION, 1304 Mpi2IOUnit10Function_t, MPI2_POINTER pMpi2IOUnit10Function_t; 1305 1306 /* 1307 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1308 * one and check the value returned for NumFunctions at runtime. 1309 */ 1310 #ifndef MPI2_IOUNITPAGE10_FUNCTION_ENTRIES 1311 #define MPI2_IOUNITPAGE10_FUNCTION_ENTRIES (1) 1312 #endif 1313 1314 typedef struct _MPI2_CONFIG_PAGE_IO_UNIT_10 1315 { 1316 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1317 U8 NumFunctions; /* 0x04 */ 1318 U8 Reserved1; /* 0x05 */ 1319 U16 Reserved2; /* 0x06 */ 1320 U32 Reserved3; /* 0x08 */ 1321 U32 Reserved4; /* 0x0C */ 1322 MPI2_IOUNIT10_FUNCTION Function[MPI2_IOUNITPAGE10_FUNCTION_ENTRIES]; /* 0x10 */ 1323 } MPI2_CONFIG_PAGE_IO_UNIT_10, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IO_UNIT_10, 1324 Mpi2IOUnitPage10_t, MPI2_POINTER pMpi2IOUnitPage10_t; 1325 1326 #define MPI2_IOUNITPAGE10_PAGEVERSION (0x01) 1327 1328 1329 /* IO Unit Page 11 (for MPI v2.6 and later) */ 1330 1331 typedef struct _MPI26_IOUNIT11_SPINUP_GROUP 1332 { 1333 U8 MaxTargetSpinup; /* 0x00 */ 1334 U8 SpinupDelay; /* 0x01 */ 1335 U8 SpinupFlags; /* 0x02 */ 1336 U8 Reserved1; /* 0x03 */ 1337 } MPI26_IOUNIT11_SPINUP_GROUP, MPI2_POINTER PTR_MPI26_IOUNIT11_SPINUP_GROUP, 1338 Mpi26IOUnit11SpinupGroup_t, MPI2_POINTER pMpi26IOUnit11SpinupGroup_t; 1339 1340 /* defines for IO Unit Page 11 SpinupFlags */ 1341 #define MPI26_IOUNITPAGE11_SPINUP_DISABLE_FLAG (0x01) 1342 1343 1344 /* 1345 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1346 * four and check the value returned for NumPhys at runtime. 1347 */ 1348 #ifndef MPI26_IOUNITPAGE11_PHY_MAX 1349 #define MPI26_IOUNITPAGE11_PHY_MAX (4) 1350 #endif 1351 1352 typedef struct _MPI26_CONFIG_PAGE_IO_UNIT_11 1353 { 1354 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1355 U32 Reserved1; /* 0x04 */ 1356 MPI26_IOUNIT11_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 1357 U32 Reserved2; /* 0x18 */ 1358 U32 Reserved3; /* 0x1C */ 1359 U32 Reserved4; /* 0x20 */ 1360 U8 BootDeviceWaitTime; /* 0x24 */ 1361 U8 SATADeviceWaitTime; /* 0x25 */ 1362 U16 Reserved6; /* 0x26 */ 1363 U8 NumPhys; /* 0x28 */ 1364 U8 PEInitialSpinupDelay; /* 0x29 */ 1365 U8 PEReplyDelay; /* 0x2A */ 1366 U8 Flags; /* 0x2B */ 1367 U8 PHY[MPI26_IOUNITPAGE11_PHY_MAX];/* 0x2C */ 1368 } MPI26_CONFIG_PAGE_IO_UNIT_11, 1369 MPI2_POINTER PTR_MPI26_CONFIG_PAGE_IO_UNIT_11, 1370 Mpi26IOUnitPage11_t, MPI2_POINTER pMpi26IOUnitPage11_t; 1371 1372 #define MPI26_IOUNITPAGE11_PAGEVERSION (0x00) 1373 1374 /* defines for Flags field */ 1375 #define MPI26_IOUNITPAGE11_FLAGS_AUTO_PORTENABLE (0x01) 1376 1377 /* defines for PHY field */ 1378 #define MPI26_IOUNITPAGE11_PHY_SPINUP_GROUP_MASK (0x03) 1379 1380 1381 1382 /**************************************************************************** 1383 * IOC Config Pages 1384 ****************************************************************************/ 1385 1386 /* IOC Page 0 */ 1387 1388 typedef struct _MPI2_CONFIG_PAGE_IOC_0 1389 { 1390 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1391 U32 Reserved1; /* 0x04 */ 1392 U32 Reserved2; /* 0x08 */ 1393 U16 VendorID; /* 0x0C */ 1394 U16 DeviceID; /* 0x0E */ 1395 U8 RevisionID; /* 0x10 */ 1396 U8 Reserved3; /* 0x11 */ 1397 U16 Reserved4; /* 0x12 */ 1398 U32 ClassCode; /* 0x14 */ 1399 U16 SubsystemVendorID; /* 0x18 */ 1400 U16 SubsystemID; /* 0x1A */ 1401 } MPI2_CONFIG_PAGE_IOC_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_0, 1402 Mpi2IOCPage0_t, MPI2_POINTER pMpi2IOCPage0_t; 1403 1404 #define MPI2_IOCPAGE0_PAGEVERSION (0x02) 1405 1406 1407 /* IOC Page 1 */ 1408 1409 typedef struct _MPI2_CONFIG_PAGE_IOC_1 1410 { 1411 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1412 U32 Flags; /* 0x04 */ 1413 U32 CoalescingTimeout; /* 0x08 */ 1414 U8 CoalescingDepth; /* 0x0C */ 1415 U8 PCISlotNum; /* 0x0D */ 1416 U8 PCIBusNum; /* 0x0E */ 1417 U8 PCIDomainSegment; /* 0x0F */ 1418 U32 Reserved1; /* 0x10 */ 1419 U32 ProductSpecific; /* 0x14 */ 1420 } MPI2_CONFIG_PAGE_IOC_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_1, 1421 Mpi2IOCPage1_t, MPI2_POINTER pMpi2IOCPage1_t; 1422 1423 #define MPI2_IOCPAGE1_PAGEVERSION (0x05) 1424 1425 /* defines for IOC Page 1 Flags field */ 1426 #define MPI2_IOCPAGE1_REPLY_COALESCING (0x00000001) 1427 1428 #define MPI2_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF) 1429 #define MPI2_IOCPAGE1_PCIBUSNUM_UNKNOWN (0xFF) 1430 #define MPI2_IOCPAGE1_PCIDOMAIN_UNKNOWN (0xFF) 1431 1432 /* IOC Page 6 */ 1433 1434 typedef struct _MPI2_CONFIG_PAGE_IOC_6 1435 { 1436 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1437 U32 CapabilitiesFlags; /* 0x04 */ 1438 U8 MaxDrivesRAID0; /* 0x08 */ 1439 U8 MaxDrivesRAID1; /* 0x09 */ 1440 U8 MaxDrivesRAID1E; /* 0x0A */ 1441 U8 MaxDrivesRAID10; /* 0x0B */ 1442 U8 MinDrivesRAID0; /* 0x0C */ 1443 U8 MinDrivesRAID1; /* 0x0D */ 1444 U8 MinDrivesRAID1E; /* 0x0E */ 1445 U8 MinDrivesRAID10; /* 0x0F */ 1446 U32 Reserved1; /* 0x10 */ 1447 U8 MaxGlobalHotSpares; /* 0x14 */ 1448 U8 MaxPhysDisks; /* 0x15 */ 1449 U8 MaxVolumes; /* 0x16 */ 1450 U8 MaxConfigs; /* 0x17 */ 1451 U8 MaxOCEDisks; /* 0x18 */ 1452 U8 Reserved2; /* 0x19 */ 1453 U16 Reserved3; /* 0x1A */ 1454 U32 SupportedStripeSizeMapRAID0; /* 0x1C */ 1455 U32 SupportedStripeSizeMapRAID1E; /* 0x20 */ 1456 U32 SupportedStripeSizeMapRAID10; /* 0x24 */ 1457 U32 Reserved4; /* 0x28 */ 1458 U32 Reserved5; /* 0x2C */ 1459 U16 DefaultMetadataSize; /* 0x30 */ 1460 U16 Reserved6; /* 0x32 */ 1461 U16 MaxBadBlockTableEntries; /* 0x34 */ 1462 U16 Reserved7; /* 0x36 */ 1463 U32 IRNvsramVersion; /* 0x38 */ 1464 } MPI2_CONFIG_PAGE_IOC_6, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_6, 1465 Mpi2IOCPage6_t, MPI2_POINTER pMpi2IOCPage6_t; 1466 1467 #define MPI2_IOCPAGE6_PAGEVERSION (0x05) 1468 1469 /* defines for IOC Page 6 CapabilitiesFlags */ 1470 #define MPI2_IOCPAGE6_CAP_FLAGS_4K_SECTORS_SUPPORT (0x00000020) 1471 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID10_SUPPORT (0x00000010) 1472 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1_SUPPORT (0x00000008) 1473 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID1E_SUPPORT (0x00000004) 1474 #define MPI2_IOCPAGE6_CAP_FLAGS_RAID0_SUPPORT (0x00000002) 1475 #define MPI2_IOCPAGE6_CAP_FLAGS_GLOBAL_HOT_SPARE (0x00000001) 1476 1477 1478 /* IOC Page 7 */ 1479 1480 #define MPI2_IOCPAGE7_EVENTMASK_WORDS (4) 1481 1482 typedef struct _MPI2_CONFIG_PAGE_IOC_7 1483 { 1484 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1485 U32 Reserved1; /* 0x04 */ 1486 U32 EventMasks[MPI2_IOCPAGE7_EVENTMASK_WORDS];/* 0x08 */ 1487 U16 SASBroadcastPrimitiveMasks; /* 0x18 */ 1488 U16 SASNotifyPrimitiveMasks; /* 0x1A */ 1489 U32 Reserved3; /* 0x1C */ 1490 } MPI2_CONFIG_PAGE_IOC_7, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_7, 1491 Mpi2IOCPage7_t, MPI2_POINTER pMpi2IOCPage7_t; 1492 1493 #define MPI2_IOCPAGE7_PAGEVERSION (0x02) 1494 1495 1496 /* IOC Page 8 */ 1497 1498 typedef struct _MPI2_CONFIG_PAGE_IOC_8 1499 { 1500 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1501 U8 NumDevsPerEnclosure; /* 0x04 */ 1502 U8 Reserved1; /* 0x05 */ 1503 U16 Reserved2; /* 0x06 */ 1504 U16 MaxPersistentEntries; /* 0x08 */ 1505 U16 MaxNumPhysicalMappedIDs; /* 0x0A */ 1506 U16 Flags; /* 0x0C */ 1507 U16 Reserved3; /* 0x0E */ 1508 U16 IRVolumeMappingFlags; /* 0x10 */ 1509 U16 Reserved4; /* 0x12 */ 1510 U32 Reserved5; /* 0x14 */ 1511 } MPI2_CONFIG_PAGE_IOC_8, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_IOC_8, 1512 Mpi2IOCPage8_t, MPI2_POINTER pMpi2IOCPage8_t; 1513 1514 #define MPI2_IOCPAGE8_PAGEVERSION (0x00) 1515 1516 /* defines for IOC Page 8 Flags field */ 1517 #define MPI2_IOCPAGE8_FLAGS_DA_START_SLOT_1 (0x00000020) 1518 #define MPI2_IOCPAGE8_FLAGS_RESERVED_TARGETID_0 (0x00000010) 1519 1520 #define MPI2_IOCPAGE8_FLAGS_MASK_MAPPING_MODE (0x0000000E) 1521 #define MPI2_IOCPAGE8_FLAGS_DEVICE_PERSISTENCE_MAPPING (0x00000000) 1522 #define MPI2_IOCPAGE8_FLAGS_ENCLOSURE_SLOT_MAPPING (0x00000002) 1523 1524 #define MPI2_IOCPAGE8_FLAGS_DISABLE_PERSISTENT_MAPPING (0x00000001) 1525 #define MPI2_IOCPAGE8_FLAGS_ENABLE_PERSISTENT_MAPPING (0x00000000) 1526 1527 /* defines for IOC Page 8 IRVolumeMappingFlags */ 1528 #define MPI2_IOCPAGE8_IRFLAGS_MASK_VOLUME_MAPPING_MODE (0x00000003) 1529 #define MPI2_IOCPAGE8_IRFLAGS_LOW_VOLUME_MAPPING (0x00000000) 1530 #define MPI2_IOCPAGE8_IRFLAGS_HIGH_VOLUME_MAPPING (0x00000001) 1531 1532 1533 /**************************************************************************** 1534 * BIOS Config Pages 1535 ****************************************************************************/ 1536 1537 /* BIOS Page 1 */ 1538 1539 typedef struct _MPI2_CONFIG_PAGE_BIOS_1 1540 { 1541 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1542 U32 BiosOptions; /* 0x04 */ 1543 U32 IOCSettings; /* 0x08 */ 1544 U8 SSUTimeout; /* 0x0C */ 1545 U8 MaxEnclosureLevel; /* 0x0D */ 1546 U16 Reserved2; /* 0x0E */ 1547 U32 DeviceSettings; /* 0x10 */ 1548 U16 NumberOfDevices; /* 0x14 */ 1549 U16 UEFIVersion; /* 0x16 */ 1550 U16 IOTimeoutBlockDevicesNonRM; /* 0x18 */ 1551 U16 IOTimeoutSequential; /* 0x1A */ 1552 U16 IOTimeoutOther; /* 0x1C */ 1553 U16 IOTimeoutBlockDevicesRM; /* 0x1E */ 1554 } MPI2_CONFIG_PAGE_BIOS_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_1, 1555 Mpi2BiosPage1_t, MPI2_POINTER pMpi2BiosPage1_t; 1556 1557 #define MPI2_BIOSPAGE1_PAGEVERSION (0x07) 1558 1559 /* values for BIOS Page 1 BiosOptions field */ 1560 #define MPI2_BIOSPAGE1_OPTIONS_BOOT_LIST_ADD_ALT_BOOT_DEVICE (0x00008000) 1561 #define MPI2_BIOSPAGE1_OPTIONS_ADVANCED_CONFIG (0x00004000) 1562 1563 #define MPI2_BIOSPAGE1_OPTIONS_PNS_MASK (0x00003800) 1564 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PBDHL (0x00000000) 1565 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ENCSLOSURE (0x00000800) 1566 #define MPI2_BIOSPAGE1_OPTIONS_PNS_LWWID (0x00001000) 1567 #define MPI2_BIOSPAGE1_OPTIONS_PNS_PSENS (0x00001800) 1568 #define MPI2_BIOSPAGE1_OPTIONS_PNS_ESPHY (0x00002000) 1569 1570 #define MPI2_BIOSPAGE1_OPTIONS_X86_DISABLE_BIOS (0x00000400) 1571 1572 #define MPI2_BIOSPAGE1_OPTIONS_MASK_REGISTRATION_UEFI_BSD (0x00000300) 1573 #define MPI2_BIOSPAGE1_OPTIONS_USE_BIT0_REGISTRATION_UEFI_BSD (0x00000000) 1574 #define MPI2_BIOSPAGE1_OPTIONS_FULL_REGISTRATION_UEFI_BSD (0x00000100) 1575 #define MPI2_BIOSPAGE1_OPTIONS_ADAPTER_REGISTRATION_UEFI_BSD (0x00000200) 1576 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_REGISTRATION_UEFI_BSD (0x00000300) 1577 1578 #define MPI2_BIOSPAGE1_OPTIONS_MASK_OEM_ID (0x000000F0) 1579 #define MPI2_BIOSPAGE1_OPTIONS_LSI_OEM_ID (0x00000000) 1580 1581 #define MPI2_BIOSPAGE1_OPTIONS_MASK_UEFI_HII_REGISTRATION (0x00000006) 1582 #define MPI2_BIOSPAGE1_OPTIONS_ENABLE_UEFI_HII (0x00000000) 1583 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_UEFI_HII (0x00000002) 1584 #define MPI2_BIOSPAGE1_OPTIONS_VERSION_CHECK_UEFI_HII (0x00000004) 1585 1586 #define MPI2_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001) 1587 1588 /* values for BIOS Page 1 IOCSettings field */ 1589 #define MPI2_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000) 1590 #define MPI2_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000) 1591 #define MPI2_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000) 1592 1593 #define MPI2_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0) 1594 #define MPI2_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000) 1595 #define MPI2_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040) 1596 #define MPI2_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080) 1597 1598 #define MPI2_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030) 1599 #define MPI2_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000) 1600 #define MPI2_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010) 1601 #define MPI2_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020) 1602 #define MPI2_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030) 1603 1604 #define MPI2_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008) 1605 1606 /* values for BIOS Page 1 DeviceSettings field */ 1607 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SMART_POLLING (0x00000010) 1608 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008) 1609 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004) 1610 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002) 1611 #define MPI2_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001) 1612 1613 /* defines for BIOS Page 1 UEFIVersion field */ 1614 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_MASK (0xFF00) 1615 #define MPI2_BIOSPAGE1_UEFI_VER_MAJOR_SHIFT (8) 1616 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_MASK (0x00FF) 1617 #define MPI2_BIOSPAGE1_UEFI_VER_MINOR_SHIFT (0) 1618 1619 1620 1621 /* BIOS Page 2 */ 1622 1623 typedef struct _MPI2_BOOT_DEVICE_ADAPTER_ORDER 1624 { 1625 U32 Reserved1; /* 0x00 */ 1626 U32 Reserved2; /* 0x04 */ 1627 U32 Reserved3; /* 0x08 */ 1628 U32 Reserved4; /* 0x0C */ 1629 U32 Reserved5; /* 0x10 */ 1630 U32 Reserved6; /* 0x14 */ 1631 } MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1632 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ADAPTER_ORDER, 1633 Mpi2BootDeviceAdapterOrder_t, MPI2_POINTER pMpi2BootDeviceAdapterOrder_t; 1634 1635 typedef struct _MPI2_BOOT_DEVICE_SAS_WWID 1636 { 1637 U64 SASAddress; /* 0x00 */ 1638 U8 LUN[8]; /* 0x08 */ 1639 U32 Reserved1; /* 0x10 */ 1640 U32 Reserved2; /* 0x14 */ 1641 } MPI2_BOOT_DEVICE_SAS_WWID, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_SAS_WWID, 1642 Mpi2BootDeviceSasWwid_t, MPI2_POINTER pMpi2BootDeviceSasWwid_t; 1643 1644 typedef struct _MPI2_BOOT_DEVICE_ENCLOSURE_SLOT 1645 { 1646 U64 EnclosureLogicalID; /* 0x00 */ 1647 U32 Reserved1; /* 0x08 */ 1648 U32 Reserved2; /* 0x0C */ 1649 U16 SlotNumber; /* 0x10 */ 1650 U16 Reserved3; /* 0x12 */ 1651 U32 Reserved4; /* 0x14 */ 1652 } MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1653 MPI2_POINTER PTR_MPI2_BOOT_DEVICE_ENCLOSURE_SLOT, 1654 Mpi2BootDeviceEnclosureSlot_t, MPI2_POINTER pMpi2BootDeviceEnclosureSlot_t; 1655 1656 typedef struct _MPI2_BOOT_DEVICE_DEVICE_NAME 1657 { 1658 U64 DeviceName; /* 0x00 */ 1659 U8 LUN[8]; /* 0x08 */ 1660 U32 Reserved1; /* 0x10 */ 1661 U32 Reserved2; /* 0x14 */ 1662 } MPI2_BOOT_DEVICE_DEVICE_NAME, MPI2_POINTER PTR_MPI2_BOOT_DEVICE_DEVICE_NAME, 1663 Mpi2BootDeviceDeviceName_t, MPI2_POINTER pMpi2BootDeviceDeviceName_t; 1664 1665 typedef union _MPI2_MPI2_BIOSPAGE2_BOOT_DEVICE 1666 { 1667 MPI2_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder; 1668 MPI2_BOOT_DEVICE_SAS_WWID SasWwid; 1669 MPI2_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot; 1670 MPI2_BOOT_DEVICE_DEVICE_NAME DeviceName; 1671 } MPI2_BIOSPAGE2_BOOT_DEVICE, MPI2_POINTER PTR_MPI2_BIOSPAGE2_BOOT_DEVICE, 1672 Mpi2BiosPage2BootDevice_t, MPI2_POINTER pMpi2BiosPage2BootDevice_t; 1673 1674 typedef struct _MPI2_CONFIG_PAGE_BIOS_2 1675 { 1676 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1677 U32 Reserved1; /* 0x04 */ 1678 U32 Reserved2; /* 0x08 */ 1679 U32 Reserved3; /* 0x0C */ 1680 U32 Reserved4; /* 0x10 */ 1681 U32 Reserved5; /* 0x14 */ 1682 U32 Reserved6; /* 0x18 */ 1683 U8 ReqBootDeviceForm; /* 0x1C */ 1684 U8 Reserved7; /* 0x1D */ 1685 U16 Reserved8; /* 0x1E */ 1686 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedBootDevice; /* 0x20 */ 1687 U8 ReqAltBootDeviceForm; /* 0x38 */ 1688 U8 Reserved9; /* 0x39 */ 1689 U16 Reserved10; /* 0x3A */ 1690 MPI2_BIOSPAGE2_BOOT_DEVICE RequestedAltBootDevice; /* 0x3C */ 1691 U8 CurrentBootDeviceForm; /* 0x58 */ 1692 U8 Reserved11; /* 0x59 */ 1693 U16 Reserved12; /* 0x5A */ 1694 MPI2_BIOSPAGE2_BOOT_DEVICE CurrentBootDevice; /* 0x58 */ 1695 } MPI2_CONFIG_PAGE_BIOS_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_2, 1696 Mpi2BiosPage2_t, MPI2_POINTER pMpi2BiosPage2_t; 1697 1698 #define MPI2_BIOSPAGE2_PAGEVERSION (0x04) 1699 1700 /* values for BIOS Page 2 BootDeviceForm fields */ 1701 #define MPI2_BIOSPAGE2_FORM_MASK (0x0F) 1702 #define MPI2_BIOSPAGE2_FORM_NO_DEVICE_SPECIFIED (0x00) 1703 #define MPI2_BIOSPAGE2_FORM_SAS_WWID (0x05) 1704 #define MPI2_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06) 1705 #define MPI2_BIOSPAGE2_FORM_DEVICE_NAME (0x07) 1706 1707 1708 /* BIOS Page 3 */ 1709 1710 #define MPI2_BIOSPAGE3_NUM_ADAPTER (4) 1711 1712 typedef struct _MPI2_ADAPTER_INFO 1713 { 1714 U8 PciBusNumber; /* 0x00 */ 1715 U8 PciDeviceAndFunctionNumber; /* 0x01 */ 1716 U16 AdapterFlags; /* 0x02 */ 1717 } MPI2_ADAPTER_INFO, MPI2_POINTER PTR_MPI2_ADAPTER_INFO, 1718 Mpi2AdapterInfo_t, MPI2_POINTER pMpi2AdapterInfo_t; 1719 1720 #define MPI2_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001) 1721 #define MPI2_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002) 1722 1723 typedef struct _MPI2_ADAPTER_ORDER_AUX 1724 { 1725 U64 WWID; /* 0x00 */ 1726 U32 Reserved1; /* 0x08 */ 1727 U32 Reserved2; /* 0x0C */ 1728 } MPI2_ADAPTER_ORDER_AUX, MPI2_POINTER PTR_MPI2_ADAPTER_ORDER_AUX, 1729 Mpi2AdapterOrderAux_t, MPI2_POINTER pMpi2AdapterOrderAux_t; 1730 1731 typedef struct _MPI2_CONFIG_PAGE_BIOS_3 1732 { 1733 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1734 U32 GlobalFlags; /* 0x04 */ 1735 U32 BiosVersion; /* 0x08 */ 1736 MPI2_ADAPTER_INFO AdapterOrder[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x0C */ 1737 U32 Reserved1; /* 0x1C */ 1738 MPI2_ADAPTER_ORDER_AUX AdapterOrderAux[MPI2_BIOSPAGE3_NUM_ADAPTER]; /* 0x20 */ /* MPI v2.5 and newer */ 1739 } MPI2_CONFIG_PAGE_BIOS_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_3, 1740 Mpi2BiosPage3_t, MPI2_POINTER pMpi2BiosPage3_t; 1741 1742 #define MPI2_BIOSPAGE3_PAGEVERSION (0x01) 1743 1744 /* values for BIOS Page 3 GlobalFlags */ 1745 #define MPI2_BIOSPAGE3_FLAGS_PAUSE_ON_ERROR (0x00000002) 1746 #define MPI2_BIOSPAGE3_FLAGS_VERBOSE_ENABLE (0x00000004) 1747 #define MPI2_BIOSPAGE3_FLAGS_HOOK_INT_40_DISABLE (0x00000010) 1748 1749 #define MPI2_BIOSPAGE3_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0) 1750 #define MPI2_BIOSPAGE3_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000) 1751 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DISPLAY (0x00000020) 1752 #define MPI2_BIOSPAGE3_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040) 1753 1754 1755 /* BIOS Page 4 */ 1756 1757 /* 1758 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1759 * one and check the value returned for NumPhys at runtime. 1760 */ 1761 #ifndef MPI2_BIOS_PAGE_4_PHY_ENTRIES 1762 #define MPI2_BIOS_PAGE_4_PHY_ENTRIES (1) 1763 #endif 1764 1765 typedef struct _MPI2_BIOS4_ENTRY 1766 { 1767 U64 ReassignmentWWID; /* 0x00 */ 1768 U64 ReassignmentDeviceName; /* 0x08 */ 1769 } MPI2_BIOS4_ENTRY, MPI2_POINTER PTR_MPI2_BIOS4_ENTRY, 1770 Mpi2MBios4Entry_t, MPI2_POINTER pMpi2Bios4Entry_t; 1771 1772 typedef struct _MPI2_CONFIG_PAGE_BIOS_4 1773 { 1774 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1775 U8 NumPhys; /* 0x04 */ 1776 U8 Reserved1; /* 0x05 */ 1777 U16 Reserved2; /* 0x06 */ 1778 MPI2_BIOS4_ENTRY Phy[MPI2_BIOS_PAGE_4_PHY_ENTRIES]; /* 0x08 */ 1779 } MPI2_CONFIG_PAGE_BIOS_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_BIOS_4, 1780 Mpi2BiosPage4_t, MPI2_POINTER pMpi2BiosPage4_t; 1781 1782 #define MPI2_BIOSPAGE4_PAGEVERSION (0x01) 1783 1784 1785 /**************************************************************************** 1786 * RAID Volume Config Pages 1787 ****************************************************************************/ 1788 1789 /* RAID Volume Page 0 */ 1790 1791 typedef struct _MPI2_RAIDVOL0_PHYS_DISK 1792 { 1793 U8 RAIDSetNum; /* 0x00 */ 1794 U8 PhysDiskMap; /* 0x01 */ 1795 U8 PhysDiskNum; /* 0x02 */ 1796 U8 Reserved; /* 0x03 */ 1797 } MPI2_RAIDVOL0_PHYS_DISK, MPI2_POINTER PTR_MPI2_RAIDVOL0_PHYS_DISK, 1798 Mpi2RaidVol0PhysDisk_t, MPI2_POINTER pMpi2RaidVol0PhysDisk_t; 1799 1800 /* defines for the PhysDiskMap field */ 1801 #define MPI2_RAIDVOL0_PHYSDISK_PRIMARY (0x01) 1802 #define MPI2_RAIDVOL0_PHYSDISK_SECONDARY (0x02) 1803 1804 typedef struct _MPI2_RAIDVOL0_SETTINGS 1805 { 1806 U16 Settings; /* 0x00 */ 1807 U8 HotSparePool; /* 0x01 */ 1808 U8 Reserved; /* 0x02 */ 1809 } MPI2_RAIDVOL0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDVOL0_SETTINGS, 1810 Mpi2RaidVol0Settings_t, MPI2_POINTER pMpi2RaidVol0Settings_t; 1811 1812 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */ 1813 #define MPI2_RAID_HOT_SPARE_POOL_0 (0x01) 1814 #define MPI2_RAID_HOT_SPARE_POOL_1 (0x02) 1815 #define MPI2_RAID_HOT_SPARE_POOL_2 (0x04) 1816 #define MPI2_RAID_HOT_SPARE_POOL_3 (0x08) 1817 #define MPI2_RAID_HOT_SPARE_POOL_4 (0x10) 1818 #define MPI2_RAID_HOT_SPARE_POOL_5 (0x20) 1819 #define MPI2_RAID_HOT_SPARE_POOL_6 (0x40) 1820 #define MPI2_RAID_HOT_SPARE_POOL_7 (0x80) 1821 1822 /* RAID Volume Page 0 VolumeSettings defines */ 1823 #define MPI2_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0008) 1824 #define MPI2_RAIDVOL0_SETTING_AUTO_CONFIG_HSWAP_DISABLE (0x0004) 1825 1826 #define MPI2_RAIDVOL0_SETTING_MASK_WRITE_CACHING (0x0003) 1827 #define MPI2_RAIDVOL0_SETTING_UNCHANGED (0x0000) 1828 #define MPI2_RAIDVOL0_SETTING_DISABLE_WRITE_CACHING (0x0001) 1829 #define MPI2_RAIDVOL0_SETTING_ENABLE_WRITE_CACHING (0x0002) 1830 1831 /* 1832 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 1833 * one and check the value returned for NumPhysDisks at runtime. 1834 */ 1835 #ifndef MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX 1836 #define MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX (1) 1837 #endif 1838 1839 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_0 1840 { 1841 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1842 U16 DevHandle; /* 0x04 */ 1843 U8 VolumeState; /* 0x06 */ 1844 U8 VolumeType; /* 0x07 */ 1845 U32 VolumeStatusFlags; /* 0x08 */ 1846 MPI2_RAIDVOL0_SETTINGS VolumeSettings; /* 0x0C */ 1847 U64 MaxLBA; /* 0x10 */ 1848 U32 StripeSize; /* 0x18 */ 1849 U16 BlockSize; /* 0x1C */ 1850 U16 Reserved1; /* 0x1E */ 1851 U8 SupportedPhysDisks; /* 0x20 */ 1852 U8 ResyncRate; /* 0x21 */ 1853 U16 DataScrubDuration; /* 0x22 */ 1854 U8 NumPhysDisks; /* 0x24 */ 1855 U8 Reserved2; /* 0x25 */ 1856 U8 Reserved3; /* 0x26 */ 1857 U8 InactiveStatus; /* 0x27 */ 1858 MPI2_RAIDVOL0_PHYS_DISK PhysDisk[MPI2_RAID_VOL_PAGE_0_PHYSDISK_MAX]; /* 0x28 */ 1859 } MPI2_CONFIG_PAGE_RAID_VOL_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_0, 1860 Mpi2RaidVolPage0_t, MPI2_POINTER pMpi2RaidVolPage0_t; 1861 1862 #define MPI2_RAIDVOLPAGE0_PAGEVERSION (0x0A) 1863 1864 /* values for RAID VolumeState */ 1865 #define MPI2_RAID_VOL_STATE_MISSING (0x00) 1866 #define MPI2_RAID_VOL_STATE_FAILED (0x01) 1867 #define MPI2_RAID_VOL_STATE_INITIALIZING (0x02) 1868 #define MPI2_RAID_VOL_STATE_ONLINE (0x03) 1869 #define MPI2_RAID_VOL_STATE_DEGRADED (0x04) 1870 #define MPI2_RAID_VOL_STATE_OPTIMAL (0x05) 1871 1872 /* values for RAID VolumeType */ 1873 #define MPI2_RAID_VOL_TYPE_RAID0 (0x00) 1874 #define MPI2_RAID_VOL_TYPE_RAID1E (0x01) 1875 #define MPI2_RAID_VOL_TYPE_RAID1 (0x02) 1876 #define MPI2_RAID_VOL_TYPE_RAID10 (0x05) 1877 #define MPI2_RAID_VOL_TYPE_UNKNOWN (0xFF) 1878 1879 /* values for RAID Volume Page 0 VolumeStatusFlags field */ 1880 #define MPI2_RAIDVOL0_STATUS_FLAG_PENDING_RESYNC (0x02000000) 1881 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKG_INIT_PENDING (0x01000000) 1882 #define MPI2_RAIDVOL0_STATUS_FLAG_MDC_PENDING (0x00800000) 1883 #define MPI2_RAIDVOL0_STATUS_FLAG_USER_CONSIST_PENDING (0x00400000) 1884 #define MPI2_RAIDVOL0_STATUS_FLAG_MAKE_DATA_CONSISTENT (0x00200000) 1885 #define MPI2_RAIDVOL0_STATUS_FLAG_DATA_SCRUB (0x00100000) 1886 #define MPI2_RAIDVOL0_STATUS_FLAG_CONSISTENCY_CHECK (0x00080000) 1887 #define MPI2_RAIDVOL0_STATUS_FLAG_CAPACITY_EXPANSION (0x00040000) 1888 #define MPI2_RAIDVOL0_STATUS_FLAG_BACKGROUND_INIT (0x00020000) 1889 #define MPI2_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x00010000) 1890 #define MPI2_RAIDVOL0_STATUS_FLAG_VOL_NOT_CONSISTENT (0x00000080) 1891 #define MPI2_RAIDVOL0_STATUS_FLAG_OCE_ALLOWED (0x00000040) 1892 #define MPI2_RAIDVOL0_STATUS_FLAG_BGI_COMPLETE (0x00000020) 1893 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_OFFSET_MIRROR (0x00000000) 1894 #define MPI2_RAIDVOL0_STATUS_FLAG_1E_ADJACENT_MIRROR (0x00000010) 1895 #define MPI2_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x00000008) 1896 #define MPI2_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x00000004) 1897 #define MPI2_RAIDVOL0_STATUS_FLAG_QUIESCED (0x00000002) 1898 #define MPI2_RAIDVOL0_STATUS_FLAG_ENABLED (0x00000001) 1899 1900 /* values for RAID Volume Page 0 SupportedPhysDisks field */ 1901 #define MPI2_RAIDVOL0_SUPPORT_SOLID_STATE_DISKS (0x08) 1902 #define MPI2_RAIDVOL0_SUPPORT_HARD_DISKS (0x04) 1903 #define MPI2_RAIDVOL0_SUPPORT_SAS_PROTOCOL (0x02) 1904 #define MPI2_RAIDVOL0_SUPPORT_SATA_PROTOCOL (0x01) 1905 1906 /* values for RAID Volume Page 0 InactiveStatus field */ 1907 #define MPI2_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00) 1908 #define MPI2_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01) 1909 #define MPI2_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02) 1910 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03) 1911 #define MPI2_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04) 1912 #define MPI2_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05) 1913 #define MPI2_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06) 1914 1915 1916 /* RAID Volume Page 1 */ 1917 1918 typedef struct _MPI2_CONFIG_PAGE_RAID_VOL_1 1919 { 1920 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1921 U16 DevHandle; /* 0x04 */ 1922 U16 Reserved0; /* 0x06 */ 1923 U8 GUID[24]; /* 0x08 */ 1924 U8 Name[16]; /* 0x20 */ 1925 U64 WWID; /* 0x30 */ 1926 U32 Reserved1; /* 0x38 */ 1927 U32 Reserved2; /* 0x3C */ 1928 } MPI2_CONFIG_PAGE_RAID_VOL_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_VOL_1, 1929 Mpi2RaidVolPage1_t, MPI2_POINTER pMpi2RaidVolPage1_t; 1930 1931 #define MPI2_RAIDVOLPAGE1_PAGEVERSION (0x03) 1932 1933 1934 /**************************************************************************** 1935 * RAID Physical Disk Config Pages 1936 ****************************************************************************/ 1937 1938 /* RAID Physical Disk Page 0 */ 1939 1940 typedef struct _MPI2_RAIDPHYSDISK0_SETTINGS 1941 { 1942 U16 Reserved1; /* 0x00 */ 1943 U8 HotSparePool; /* 0x02 */ 1944 U8 Reserved2; /* 0x03 */ 1945 } MPI2_RAIDPHYSDISK0_SETTINGS, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_SETTINGS, 1946 Mpi2RaidPhysDisk0Settings_t, MPI2_POINTER pMpi2RaidPhysDisk0Settings_t; 1947 1948 /* use MPI2_RAID_HOT_SPARE_POOL_ defines for the HotSparePool field */ 1949 1950 typedef struct _MPI2_RAIDPHYSDISK0_INQUIRY_DATA 1951 { 1952 U8 VendorID[8]; /* 0x00 */ 1953 U8 ProductID[16]; /* 0x08 */ 1954 U8 ProductRevLevel[4]; /* 0x18 */ 1955 U8 SerialNum[32]; /* 0x1C */ 1956 } MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1957 MPI2_POINTER PTR_MPI2_RAIDPHYSDISK0_INQUIRY_DATA, 1958 Mpi2RaidPhysDisk0InquiryData_t, MPI2_POINTER pMpi2RaidPhysDisk0InquiryData_t; 1959 1960 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_0 1961 { 1962 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1963 U16 DevHandle; /* 0x04 */ 1964 U8 Reserved1; /* 0x06 */ 1965 U8 PhysDiskNum; /* 0x07 */ 1966 MPI2_RAIDPHYSDISK0_SETTINGS PhysDiskSettings; /* 0x08 */ 1967 U32 Reserved2; /* 0x0C */ 1968 MPI2_RAIDPHYSDISK0_INQUIRY_DATA InquiryData; /* 0x10 */ 1969 U32 Reserved3; /* 0x4C */ 1970 U8 PhysDiskState; /* 0x50 */ 1971 U8 OfflineReason; /* 0x51 */ 1972 U8 IncompatibleReason; /* 0x52 */ 1973 U8 PhysDiskAttributes; /* 0x53 */ 1974 U32 PhysDiskStatusFlags; /* 0x54 */ 1975 U64 DeviceMaxLBA; /* 0x58 */ 1976 U64 HostMaxLBA; /* 0x60 */ 1977 U64 CoercedMaxLBA; /* 0x68 */ 1978 U16 BlockSize; /* 0x70 */ 1979 U16 Reserved5; /* 0x72 */ 1980 U32 Reserved6; /* 0x74 */ 1981 } MPI2_CONFIG_PAGE_RD_PDISK_0, 1982 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_0, 1983 Mpi2RaidPhysDiskPage0_t, MPI2_POINTER pMpi2RaidPhysDiskPage0_t; 1984 1985 #define MPI2_RAIDPHYSDISKPAGE0_PAGEVERSION (0x05) 1986 1987 /* PhysDiskState defines */ 1988 #define MPI2_RAID_PD_STATE_NOT_CONFIGURED (0x00) 1989 #define MPI2_RAID_PD_STATE_NOT_COMPATIBLE (0x01) 1990 #define MPI2_RAID_PD_STATE_OFFLINE (0x02) 1991 #define MPI2_RAID_PD_STATE_ONLINE (0x03) 1992 #define MPI2_RAID_PD_STATE_HOT_SPARE (0x04) 1993 #define MPI2_RAID_PD_STATE_DEGRADED (0x05) 1994 #define MPI2_RAID_PD_STATE_REBUILDING (0x06) 1995 #define MPI2_RAID_PD_STATE_OPTIMAL (0x07) 1996 1997 /* OfflineReason defines */ 1998 #define MPI2_PHYSDISK0_ONLINE (0x00) 1999 #define MPI2_PHYSDISK0_OFFLINE_MISSING (0x01) 2000 #define MPI2_PHYSDISK0_OFFLINE_FAILED (0x03) 2001 #define MPI2_PHYSDISK0_OFFLINE_INITIALIZING (0x04) 2002 #define MPI2_PHYSDISK0_OFFLINE_REQUESTED (0x05) 2003 #define MPI2_PHYSDISK0_OFFLINE_FAILED_REQUESTED (0x06) 2004 #define MPI2_PHYSDISK0_OFFLINE_OTHER (0xFF) 2005 2006 /* IncompatibleReason defines */ 2007 #define MPI2_PHYSDISK0_COMPATIBLE (0x00) 2008 #define MPI2_PHYSDISK0_INCOMPATIBLE_PROTOCOL (0x01) 2009 #define MPI2_PHYSDISK0_INCOMPATIBLE_BLOCKSIZE (0x02) 2010 #define MPI2_PHYSDISK0_INCOMPATIBLE_MAX_LBA (0x03) 2011 #define MPI2_PHYSDISK0_INCOMPATIBLE_SATA_EXTENDED_CMD (0x04) 2012 #define MPI2_PHYSDISK0_INCOMPATIBLE_REMOVEABLE_MEDIA (0x05) 2013 #define MPI2_PHYSDISK0_INCOMPATIBLE_MEDIA_TYPE (0x06) 2014 #define MPI2_PHYSDISK0_INCOMPATIBLE_UNKNOWN (0xFF) 2015 2016 /* PhysDiskAttributes defines */ 2017 #define MPI2_PHYSDISK0_ATTRIB_MEDIA_MASK (0x0C) 2018 #define MPI2_PHYSDISK0_ATTRIB_SOLID_STATE_DRIVE (0x08) 2019 #define MPI2_PHYSDISK0_ATTRIB_HARD_DISK_DRIVE (0x04) 2020 2021 #define MPI2_PHYSDISK0_ATTRIB_PROTOCOL_MASK (0x03) 2022 #define MPI2_PHYSDISK0_ATTRIB_SAS_PROTOCOL (0x02) 2023 #define MPI2_PHYSDISK0_ATTRIB_SATA_PROTOCOL (0x01) 2024 2025 /* PhysDiskStatusFlags defines */ 2026 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_CERTIFIED (0x00000040) 2027 #define MPI2_PHYSDISK0_STATUS_FLAG_OCE_TARGET (0x00000020) 2028 #define MPI2_PHYSDISK0_STATUS_FLAG_WRITE_CACHE_ENABLED (0x00000010) 2029 #define MPI2_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00000000) 2030 #define MPI2_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x00000008) 2031 #define MPI2_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x00000004) 2032 #define MPI2_PHYSDISK0_STATUS_FLAG_QUIESCED (0x00000002) 2033 #define MPI2_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x00000001) 2034 2035 2036 /* RAID Physical Disk Page 1 */ 2037 2038 /* 2039 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2040 * one and check the value returned for NumPhysDiskPaths at runtime. 2041 */ 2042 #ifndef MPI2_RAID_PHYS_DISK1_PATH_MAX 2043 #define MPI2_RAID_PHYS_DISK1_PATH_MAX (1) 2044 #endif 2045 2046 typedef struct _MPI2_RAIDPHYSDISK1_PATH 2047 { 2048 U16 DevHandle; /* 0x00 */ 2049 U16 Reserved1; /* 0x02 */ 2050 U64 WWID; /* 0x04 */ 2051 U64 OwnerWWID; /* 0x0C */ 2052 U8 OwnerIdentifier; /* 0x14 */ 2053 U8 Reserved2; /* 0x15 */ 2054 U16 Flags; /* 0x16 */ 2055 } MPI2_RAIDPHYSDISK1_PATH, MPI2_POINTER PTR_MPI2_RAIDPHYSDISK1_PATH, 2056 Mpi2RaidPhysDisk1Path_t, MPI2_POINTER pMpi2RaidPhysDisk1Path_t; 2057 2058 /* RAID Physical Disk Page 1 Physical Disk Path Flags field defines */ 2059 #define MPI2_RAID_PHYSDISK1_FLAG_PRIMARY (0x0004) 2060 #define MPI2_RAID_PHYSDISK1_FLAG_BROKEN (0x0002) 2061 #define MPI2_RAID_PHYSDISK1_FLAG_INVALID (0x0001) 2062 2063 typedef struct _MPI2_CONFIG_PAGE_RD_PDISK_1 2064 { 2065 MPI2_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2066 U8 NumPhysDiskPaths; /* 0x04 */ 2067 U8 PhysDiskNum; /* 0x05 */ 2068 U16 Reserved1; /* 0x06 */ 2069 U32 Reserved2; /* 0x08 */ 2070 MPI2_RAIDPHYSDISK1_PATH PhysicalDiskPath[MPI2_RAID_PHYS_DISK1_PATH_MAX];/* 0x0C */ 2071 } MPI2_CONFIG_PAGE_RD_PDISK_1, 2072 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RD_PDISK_1, 2073 Mpi2RaidPhysDiskPage1_t, MPI2_POINTER pMpi2RaidPhysDiskPage1_t; 2074 2075 #define MPI2_RAIDPHYSDISKPAGE1_PAGEVERSION (0x02) 2076 2077 2078 /**************************************************************************** 2079 * values for fields used by several types of SAS Config Pages 2080 ****************************************************************************/ 2081 2082 /* values for NegotiatedLinkRates fields */ 2083 #define MPI2_SAS_NEG_LINK_RATE_MASK_LOGICAL (0xF0) 2084 #define MPI2_SAS_NEG_LINK_RATE_SHIFT_LOGICAL (4) 2085 #define MPI2_SAS_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 2086 /* link rates used for Negotiated Physical and Logical Link Rate */ 2087 #define MPI2_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 2088 #define MPI2_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 2089 #define MPI2_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 2090 #define MPI2_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 2091 #define MPI2_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 2092 #define MPI2_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 2093 #define MPI2_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 2094 #define MPI2_SAS_NEG_LINK_RATE_1_5 (0x08) 2095 #define MPI2_SAS_NEG_LINK_RATE_3_0 (0x09) 2096 #define MPI2_SAS_NEG_LINK_RATE_6_0 (0x0A) 2097 #define MPI25_SAS_NEG_LINK_RATE_12_0 (0x0B) 2098 #define MPI26_SAS_NEG_LINK_RATE_22_5 (0x0C) 2099 2100 2101 /* values for AttachedPhyInfo fields */ 2102 #define MPI2_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 2103 #define MPI2_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 2104 #define MPI2_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 2105 2106 #define MPI2_SAS_APHYINFO_REASON_MASK (0x0000000F) 2107 #define MPI2_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 2108 #define MPI2_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 2109 #define MPI2_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 2110 #define MPI2_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 2111 #define MPI2_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 2112 #define MPI2_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 2113 #define MPI2_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 2114 #define MPI2_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 2115 #define MPI2_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 2116 2117 2118 /* values for PhyInfo fields */ 2119 #define MPI2_SAS_PHYINFO_PHY_VACANT (0x80000000) 2120 2121 #define MPI2_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 2122 #define MPI2_SAS_PHYINFO_SHIFT_PHY_POWER_CONDITION (27) 2123 #define MPI2_SAS_PHYINFO_PHY_POWER_ACTIVE (0x00000000) 2124 #define MPI2_SAS_PHYINFO_PHY_POWER_PARTIAL (0x08000000) 2125 #define MPI2_SAS_PHYINFO_PHY_POWER_SLUMBER (0x10000000) 2126 2127 #define MPI2_SAS_PHYINFO_CHANGED_REQ_INSIDE_ZPSDS (0x04000000) 2128 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT (0x02000000) 2129 #define MPI2_SAS_PHYINFO_REQ_INSIDE_ZPSDS (0x01000000) 2130 #define MPI2_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 2131 #define MPI2_SAS_PHYINFO_INSIDE_ZPSDS (0x00200000) 2132 #define MPI2_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 2133 2134 #define MPI2_SAS_PHYINFO_REASON_MASK (0x000F0000) 2135 #define MPI2_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 2136 #define MPI2_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 2137 #define MPI2_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 2138 #define MPI2_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 2139 #define MPI2_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 2140 #define MPI2_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 2141 #define MPI2_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 2142 #define MPI2_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 2143 #define MPI2_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 2144 2145 #define MPI2_SAS_PHYINFO_MULTIPLEXING_SUPPORTED (0x00008000) 2146 #define MPI2_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 2147 #define MPI2_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 2148 #define MPI2_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 2149 2150 #define MPI2_SAS_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00) 2151 #define MPI2_SAS_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8) 2152 2153 #define MPI2_SAS_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0) 2154 #define MPI2_SAS_PHYINFO_DIRECT_ROUTING (0x00000000) 2155 #define MPI2_SAS_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010) 2156 #define MPI2_SAS_PHYINFO_TABLE_ROUTING (0x00000020) 2157 2158 2159 /* values for SAS ProgrammedLinkRate fields */ 2160 #define MPI2_SAS_PRATE_MAX_RATE_MASK (0xF0) 2161 #define MPI2_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 2162 #define MPI2_SAS_PRATE_MAX_RATE_1_5 (0x80) 2163 #define MPI2_SAS_PRATE_MAX_RATE_3_0 (0x90) 2164 #define MPI2_SAS_PRATE_MAX_RATE_6_0 (0xA0) 2165 #define MPI25_SAS_PRATE_MAX_RATE_12_0 (0xB0) 2166 #define MPI26_SAS_PRATE_MAX_RATE_22_5 (0xC0) 2167 #define MPI2_SAS_PRATE_MIN_RATE_MASK (0x0F) 2168 #define MPI2_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 2169 #define MPI2_SAS_PRATE_MIN_RATE_1_5 (0x08) 2170 #define MPI2_SAS_PRATE_MIN_RATE_3_0 (0x09) 2171 #define MPI2_SAS_PRATE_MIN_RATE_6_0 (0x0A) 2172 #define MPI25_SAS_PRATE_MIN_RATE_12_0 (0x0B) 2173 #define MPI26_SAS_PRATE_MIN_RATE_22_5 (0x0C) 2174 2175 2176 /* values for SAS HwLinkRate fields */ 2177 #define MPI2_SAS_HWRATE_MAX_RATE_MASK (0xF0) 2178 #define MPI2_SAS_HWRATE_MAX_RATE_1_5 (0x80) 2179 #define MPI2_SAS_HWRATE_MAX_RATE_3_0 (0x90) 2180 #define MPI2_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 2181 #define MPI25_SAS_HWRATE_MAX_RATE_12_0 (0xB0) 2182 #define MPI26_SAS_HWRATE_MAX_RATE_22_5 (0xC0) 2183 #define MPI2_SAS_HWRATE_MIN_RATE_MASK (0x0F) 2184 #define MPI2_SAS_HWRATE_MIN_RATE_1_5 (0x08) 2185 #define MPI2_SAS_HWRATE_MIN_RATE_3_0 (0x09) 2186 #define MPI2_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 2187 #define MPI25_SAS_HWRATE_MIN_RATE_12_0 (0x0B) 2188 #define MPI26_SAS_HWRATE_MIN_RATE_22_5 (0x0C) 2189 2190 2191 2192 /**************************************************************************** 2193 * SAS IO Unit Config Pages 2194 ****************************************************************************/ 2195 2196 /* SAS IO Unit Page 0 */ 2197 2198 typedef struct _MPI2_SAS_IO_UNIT0_PHY_DATA 2199 { 2200 U8 Port; /* 0x00 */ 2201 U8 PortFlags; /* 0x01 */ 2202 U8 PhyFlags; /* 0x02 */ 2203 U8 NegotiatedLinkRate; /* 0x03 */ 2204 U32 ControllerPhyDeviceInfo;/* 0x04 */ 2205 U16 AttachedDevHandle; /* 0x08 */ 2206 U16 ControllerDevHandle; /* 0x0A */ 2207 U32 DiscoveryStatus; /* 0x0C */ 2208 U32 Reserved; /* 0x10 */ 2209 } MPI2_SAS_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT0_PHY_DATA, 2210 Mpi2SasIOUnit0PhyData_t, MPI2_POINTER pMpi2SasIOUnit0PhyData_t; 2211 2212 /* 2213 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2214 * one and check the value returned for NumPhys at runtime. 2215 */ 2216 #ifndef MPI2_SAS_IOUNIT0_PHY_MAX 2217 #define MPI2_SAS_IOUNIT0_PHY_MAX (1) 2218 #endif 2219 2220 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_0 2221 { 2222 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2223 U32 Reserved1; /* 0x08 */ 2224 U8 NumPhys; /* 0x0C */ 2225 U8 Reserved2; /* 0x0D */ 2226 U16 Reserved3; /* 0x0E */ 2227 MPI2_SAS_IO_UNIT0_PHY_DATA PhyData[MPI2_SAS_IOUNIT0_PHY_MAX]; /* 0x10 */ 2228 } MPI2_CONFIG_PAGE_SASIOUNIT_0, 2229 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_0, 2230 Mpi2SasIOUnitPage0_t, MPI2_POINTER pMpi2SasIOUnitPage0_t; 2231 2232 #define MPI2_SASIOUNITPAGE0_PAGEVERSION (0x05) 2233 2234 /* values for SAS IO Unit Page 0 PortFlags */ 2235 #define MPI2_SASIOUNIT0_PORTFLAGS_DISCOVERY_IN_PROGRESS (0x08) 2236 #define MPI2_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG (0x01) 2237 2238 /* values for SAS IO Unit Page 0 PhyFlags */ 2239 #define MPI2_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2240 #define MPI2_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2241 #define MPI2_SASIOUNIT0_PHYFLAGS_ZONING_ENABLED (0x10) 2242 #define MPI2_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 2243 2244 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2245 2246 /* see mpi2_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */ 2247 2248 /* values for SAS IO Unit Page 0 DiscoveryStatus */ 2249 #define MPI2_SASIOUNIT0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2250 #define MPI2_SASIOUNIT0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2251 #define MPI2_SASIOUNIT0_DS_MAX_DEVICES_EXCEED (0x20000000) 2252 #define MPI2_SASIOUNIT0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2253 #define MPI2_SASIOUNIT0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2254 #define MPI2_SASIOUNIT0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2255 #define MPI2_SASIOUNIT0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2256 #define MPI2_SASIOUNIT0_DS_MULTI_PORT_DOMAIN (0x00002000) 2257 #define MPI2_SASIOUNIT0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2258 #define MPI2_SASIOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800) 2259 #define MPI2_SASIOUNIT0_DS_TABLE_LINK (0x00000400) 2260 #define MPI2_SASIOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200) 2261 #define MPI2_SASIOUNIT0_DS_SMP_CRC_ERROR (0x00000100) 2262 #define MPI2_SASIOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080) 2263 #define MPI2_SASIOUNIT0_DS_INDEX_NOT_EXIST (0x00000040) 2264 #define MPI2_SASIOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2265 #define MPI2_SASIOUNIT0_DS_SMP_TIMEOUT (0x00000010) 2266 #define MPI2_SASIOUNIT0_DS_MULTIPLE_PORTS (0x00000004) 2267 #define MPI2_SASIOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2268 #define MPI2_SASIOUNIT0_DS_LOOP_DETECTED (0x00000001) 2269 2270 2271 /* SAS IO Unit Page 1 */ 2272 2273 typedef struct _MPI2_SAS_IO_UNIT1_PHY_DATA 2274 { 2275 U8 Port; /* 0x00 */ 2276 U8 PortFlags; /* 0x01 */ 2277 U8 PhyFlags; /* 0x02 */ 2278 U8 MaxMinLinkRate; /* 0x03 */ 2279 U32 ControllerPhyDeviceInfo; /* 0x04 */ 2280 U16 MaxTargetPortConnectTime; /* 0x08 */ 2281 U16 Reserved1; /* 0x0A */ 2282 } MPI2_SAS_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI2_SAS_IO_UNIT1_PHY_DATA, 2283 Mpi2SasIOUnit1PhyData_t, MPI2_POINTER pMpi2SasIOUnit1PhyData_t; 2284 2285 /* 2286 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2287 * one and check the value returned for NumPhys at runtime. 2288 */ 2289 #ifndef MPI2_SAS_IOUNIT1_PHY_MAX 2290 #define MPI2_SAS_IOUNIT1_PHY_MAX (1) 2291 #endif 2292 2293 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_1 2294 { 2295 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2296 U16 ControlFlags; /* 0x08 */ 2297 U16 SASNarrowMaxQueueDepth; /* 0x0A */ 2298 U16 AdditionalControlFlags; /* 0x0C */ 2299 U16 SASWideMaxQueueDepth; /* 0x0E */ 2300 U8 NumPhys; /* 0x10 */ 2301 U8 SATAMaxQDepth; /* 0x11 */ 2302 U8 ReportDeviceMissingDelay; /* 0x12 */ 2303 U8 IODeviceMissingDelay; /* 0x13 */ 2304 MPI2_SAS_IO_UNIT1_PHY_DATA PhyData[MPI2_SAS_IOUNIT1_PHY_MAX]; /* 0x14 */ 2305 } MPI2_CONFIG_PAGE_SASIOUNIT_1, 2306 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_1, 2307 Mpi2SasIOUnitPage1_t, MPI2_POINTER pMpi2SasIOUnitPage1_t; 2308 2309 #define MPI2_SASIOUNITPAGE1_PAGEVERSION (0x09) 2310 2311 /* values for SAS IO Unit Page 1 ControlFlags */ 2312 #define MPI2_SASIOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000) 2313 #define MPI2_SASIOUNIT1_CONTROL_SATA_3_0_MAX (0x4000) 2314 #define MPI2_SASIOUNIT1_CONTROL_SATA_1_5_MAX (0x2000) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */ 2315 #define MPI2_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2316 2317 #define MPI2_SASIOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600) 2318 #define MPI2_SASIOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9) 2319 #define MPI2_SASIOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x0) 2320 #define MPI2_SASIOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x1) 2321 #define MPI2_SASIOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x2) 2322 2323 #define MPI2_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2324 #define MPI2_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2325 #define MPI2_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2326 #define MPI2_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2327 #define MPI2_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 2328 #define MPI2_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2329 #define MPI2_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2330 #define MPI2_SASIOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001) /* MPI v2.0 only. Obsolete in MPI v2.5 and later. */ 2331 2332 /* values for SAS IO Unit Page 1 AdditionalControlFlags */ 2333 #define MPI2_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 2334 #define MPI2_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2335 #define MPI2_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2336 #define MPI2_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 2337 #define MPI2_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2338 #define MPI2_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2339 #define MPI2_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2340 #define MPI2_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2341 #define MPI2_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2342 2343 /* defines for SAS IO Unit Page 1 ReportDeviceMissingDelay */ 2344 #define MPI2_SASIOUNIT1_REPORT_MISSING_TIMEOUT_MASK (0x7F) 2345 #define MPI2_SASIOUNIT1_REPORT_MISSING_UNIT_16 (0x80) 2346 2347 /* values for SAS IO Unit Page 1 PortFlags */ 2348 #define MPI2_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2349 2350 /* values for SAS IO Unit Page 1 PhyFlags */ 2351 #define MPI2_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2352 #define MPI2_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2353 #define MPI2_SASIOUNIT1_PHYFLAGS_ZONING_ENABLE (0x10) 2354 #define MPI2_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2355 2356 /* values for SAS IO Unit Page 1 MaxMinLinkRate */ 2357 #define MPI2_SASIOUNIT1_MAX_RATE_MASK (0xF0) 2358 #define MPI2_SASIOUNIT1_MAX_RATE_1_5 (0x80) 2359 #define MPI2_SASIOUNIT1_MAX_RATE_3_0 (0x90) 2360 #define MPI2_SASIOUNIT1_MAX_RATE_6_0 (0xA0) 2361 #define MPI25_SASIOUNIT1_MAX_RATE_12_0 (0xB0) 2362 #define MPI26_SASIOUNIT1_MAX_RATE_22_5 (0xC0) 2363 #define MPI2_SASIOUNIT1_MIN_RATE_MASK (0x0F) 2364 #define MPI2_SASIOUNIT1_MIN_RATE_1_5 (0x08) 2365 #define MPI2_SASIOUNIT1_MIN_RATE_3_0 (0x09) 2366 #define MPI2_SASIOUNIT1_MIN_RATE_6_0 (0x0A) 2367 #define MPI25_SASIOUNIT1_MIN_RATE_12_0 (0x0B) 2368 #define MPI26_SASIOUNIT1_MIN_RATE_22_5 (0x0C) 2369 2370 /* see mpi2_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */ 2371 2372 2373 /* SAS IO Unit Page 4 (for MPI v2.5 and earlier) */ 2374 2375 typedef struct _MPI2_SAS_IOUNIT4_SPINUP_GROUP 2376 { 2377 U8 MaxTargetSpinup; /* 0x00 */ 2378 U8 SpinupDelay; /* 0x01 */ 2379 U8 SpinupFlags; /* 0x02 */ 2380 U8 Reserved1; /* 0x03 */ 2381 } MPI2_SAS_IOUNIT4_SPINUP_GROUP, MPI2_POINTER PTR_MPI2_SAS_IOUNIT4_SPINUP_GROUP, 2382 Mpi2SasIOUnit4SpinupGroup_t, MPI2_POINTER pMpi2SasIOUnit4SpinupGroup_t; 2383 2384 /* defines for SAS IO Unit Page 4 SpinupFlags */ 2385 #define MPI2_SASIOUNIT4_SPINUP_DISABLE_FLAG (0x01) 2386 2387 2388 /* 2389 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2390 * one and check the value returned for NumPhys at runtime. 2391 */ 2392 #ifndef MPI2_SAS_IOUNIT4_PHY_MAX 2393 #define MPI2_SAS_IOUNIT4_PHY_MAX (4) 2394 #endif 2395 2396 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_4 2397 { 2398 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2399 MPI2_SAS_IOUNIT4_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 2400 U32 Reserved1; /* 0x18 */ 2401 U32 Reserved2; /* 0x1C */ 2402 U32 Reserved3; /* 0x20 */ 2403 U8 BootDeviceWaitTime; /* 0x24 */ 2404 U8 SATADeviceWaitTime; /* 0x25 */ 2405 U16 Reserved5; /* 0x26 */ 2406 U8 NumPhys; /* 0x28 */ 2407 U8 PEInitialSpinupDelay; /* 0x29 */ 2408 U8 PEReplyDelay; /* 0x2A */ 2409 U8 Flags; /* 0x2B */ 2410 U8 PHY[MPI2_SAS_IOUNIT4_PHY_MAX]; /* 0x2C */ 2411 } MPI2_CONFIG_PAGE_SASIOUNIT_4, 2412 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_4, 2413 Mpi2SasIOUnitPage4_t, MPI2_POINTER pMpi2SasIOUnitPage4_t; 2414 2415 #define MPI2_SASIOUNITPAGE4_PAGEVERSION (0x02) 2416 2417 /* defines for Flags field */ 2418 #define MPI2_SASIOUNIT4_FLAGS_AUTO_PORTENABLE (0x01) 2419 2420 /* defines for PHY field */ 2421 #define MPI2_SASIOUNIT4_PHY_SPINUP_GROUP_MASK (0x03) 2422 2423 2424 /* SAS IO Unit Page 5 */ 2425 2426 typedef struct _MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS 2427 { 2428 U8 ControlFlags; /* 0x00 */ 2429 U8 PortWidthModGroup; /* 0x01 */ 2430 U16 InactivityTimerExponent; /* 0x02 */ 2431 U8 SATAPartialTimeout; /* 0x04 */ 2432 U8 Reserved2; /* 0x05 */ 2433 U8 SATASlumberTimeout; /* 0x06 */ 2434 U8 Reserved3; /* 0x07 */ 2435 U8 SASPartialTimeout; /* 0x08 */ 2436 U8 Reserved4; /* 0x09 */ 2437 U8 SASSlumberTimeout; /* 0x0A */ 2438 U8 Reserved5; /* 0x0B */ 2439 } MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2440 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS, 2441 Mpi2SasIOUnit5PhyPmSettings_t, MPI2_POINTER pMpi2SasIOUnit5PhyPmSettings_t; 2442 2443 /* defines for ControlFlags field */ 2444 #define MPI2_SASIOUNIT5_CONTROL_SAS_SLUMBER_ENABLE (0x08) 2445 #define MPI2_SASIOUNIT5_CONTROL_SAS_PARTIAL_ENABLE (0x04) 2446 #define MPI2_SASIOUNIT5_CONTROL_SATA_SLUMBER_ENABLE (0x02) 2447 #define MPI2_SASIOUNIT5_CONTROL_SATA_PARTIAL_ENABLE (0x01) 2448 2449 /* defines for PortWidthModeGroup field */ 2450 #define MPI2_SASIOUNIT5_PWMG_DISABLE (0xFF) 2451 2452 /* defines for InactivityTimerExponent field */ 2453 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_SLUMBER (0x7000) 2454 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_SLUMBER (12) 2455 #define MPI2_SASIOUNIT5_ITE_MASK_SAS_PARTIAL (0x0700) 2456 #define MPI2_SASIOUNIT5_ITE_SHIFT_SAS_PARTIAL (8) 2457 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_SLUMBER (0x0070) 2458 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_SLUMBER (4) 2459 #define MPI2_SASIOUNIT5_ITE_MASK_SATA_PARTIAL (0x0007) 2460 #define MPI2_SASIOUNIT5_ITE_SHIFT_SATA_PARTIAL (0) 2461 2462 #define MPI2_SASIOUNIT5_ITE_TEN_SECONDS (7) 2463 #define MPI2_SASIOUNIT5_ITE_ONE_SECOND (6) 2464 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MILLISECONDS (5) 2465 #define MPI2_SASIOUNIT5_ITE_TEN_MILLISECONDS (4) 2466 #define MPI2_SASIOUNIT5_ITE_ONE_MILLISECOND (3) 2467 #define MPI2_SASIOUNIT5_ITE_HUNDRED_MICROSECONDS (2) 2468 #define MPI2_SASIOUNIT5_ITE_TEN_MICROSECONDS (1) 2469 #define MPI2_SASIOUNIT5_ITE_ONE_MICROSECOND (0) 2470 2471 /* 2472 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2473 * one and check the value returned for NumPhys at runtime. 2474 */ 2475 #ifndef MPI2_SAS_IOUNIT5_PHY_MAX 2476 #define MPI2_SAS_IOUNIT5_PHY_MAX (1) 2477 #endif 2478 2479 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_5 2480 { 2481 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2482 U8 NumPhys; /* 0x08 */ 2483 U8 Reserved1; /* 0x09 */ 2484 U16 Reserved2; /* 0x0A */ 2485 U32 Reserved3; /* 0x0C */ 2486 MPI2_SAS_IO_UNIT5_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI2_SAS_IOUNIT5_PHY_MAX]; /* 0x10 */ 2487 } MPI2_CONFIG_PAGE_SASIOUNIT_5, 2488 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_5, 2489 Mpi2SasIOUnitPage5_t, MPI2_POINTER pMpi2SasIOUnitPage5_t; 2490 2491 #define MPI2_SASIOUNITPAGE5_PAGEVERSION (0x01) 2492 2493 2494 /* SAS IO Unit Page 6 */ 2495 2496 typedef struct _MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2497 { 2498 U8 CurrentStatus; /* 0x00 */ 2499 U8 CurrentModulation; /* 0x01 */ 2500 U8 CurrentUtilization; /* 0x02 */ 2501 U8 Reserved1; /* 0x03 */ 2502 U32 Reserved2; /* 0x04 */ 2503 } MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2504 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS, 2505 Mpi2SasIOUnit6PortWidthModGroupStatus_t, 2506 MPI2_POINTER pMpi2SasIOUnit6PortWidthModGroupStatus_t; 2507 2508 /* defines for CurrentStatus field */ 2509 #define MPI2_SASIOUNIT6_STATUS_UNAVAILABLE (0x00) 2510 #define MPI2_SASIOUNIT6_STATUS_UNCONFIGURED (0x01) 2511 #define MPI2_SASIOUNIT6_STATUS_INVALID_CONFIG (0x02) 2512 #define MPI2_SASIOUNIT6_STATUS_LINK_DOWN (0x03) 2513 #define MPI2_SASIOUNIT6_STATUS_OBSERVATION_ONLY (0x04) 2514 #define MPI2_SASIOUNIT6_STATUS_INACTIVE (0x05) 2515 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_IOUNIT (0x06) 2516 #define MPI2_SASIOUNIT6_STATUS_ACTIVE_HOST (0x07) 2517 2518 /* defines for CurrentModulation field */ 2519 #define MPI2_SASIOUNIT6_MODULATION_25_PERCENT (0x00) 2520 #define MPI2_SASIOUNIT6_MODULATION_50_PERCENT (0x01) 2521 #define MPI2_SASIOUNIT6_MODULATION_75_PERCENT (0x02) 2522 #define MPI2_SASIOUNIT6_MODULATION_100_PERCENT (0x03) 2523 2524 /* 2525 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2526 * one and check the value returned for NumGroups at runtime. 2527 */ 2528 #ifndef MPI2_SAS_IOUNIT6_GROUP_MAX 2529 #define MPI2_SAS_IOUNIT6_GROUP_MAX (1) 2530 #endif 2531 2532 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_6 2533 { 2534 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2535 U32 Reserved1; /* 0x08 */ 2536 U32 Reserved2; /* 0x0C */ 2537 U8 NumGroups; /* 0x10 */ 2538 U8 Reserved3; /* 0x11 */ 2539 U16 Reserved4; /* 0x12 */ 2540 MPI2_SAS_IO_UNIT6_PORT_WIDTH_MOD_GROUP_STATUS 2541 PortWidthModulationGroupStatus[MPI2_SAS_IOUNIT6_GROUP_MAX]; /* 0x14 */ 2542 } MPI2_CONFIG_PAGE_SASIOUNIT_6, 2543 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_6, 2544 Mpi2SasIOUnitPage6_t, MPI2_POINTER pMpi2SasIOUnitPage6_t; 2545 2546 #define MPI2_SASIOUNITPAGE6_PAGEVERSION (0x00) 2547 2548 2549 /* SAS IO Unit Page 7 */ 2550 2551 typedef struct _MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2552 { 2553 U8 Flags; /* 0x00 */ 2554 U8 Reserved1; /* 0x01 */ 2555 U16 Reserved2; /* 0x02 */ 2556 U8 Threshold75Pct; /* 0x04 */ 2557 U8 Threshold50Pct; /* 0x05 */ 2558 U8 Threshold25Pct; /* 0x06 */ 2559 U8 Reserved3; /* 0x07 */ 2560 } MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2561 MPI2_POINTER PTR_MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS, 2562 Mpi2SasIOUnit7PortWidthModGroupSettings_t, 2563 MPI2_POINTER pMpi2SasIOUnit7PortWidthModGroupSettings_t; 2564 2565 /* defines for Flags field */ 2566 #define MPI2_SASIOUNIT7_FLAGS_ENABLE_PORT_WIDTH_MODULATION (0x01) 2567 2568 2569 /* 2570 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2571 * one and check the value returned for NumGroups at runtime. 2572 */ 2573 #ifndef MPI2_SAS_IOUNIT7_GROUP_MAX 2574 #define MPI2_SAS_IOUNIT7_GROUP_MAX (1) 2575 #endif 2576 2577 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_7 2578 { 2579 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2580 U8 SamplingInterval; /* 0x08 */ 2581 U8 WindowLength; /* 0x09 */ 2582 U16 Reserved1; /* 0x0A */ 2583 U32 Reserved2; /* 0x0C */ 2584 U32 Reserved3; /* 0x10 */ 2585 U8 NumGroups; /* 0x14 */ 2586 U8 Reserved4; /* 0x15 */ 2587 U16 Reserved5; /* 0x16 */ 2588 MPI2_SAS_IO_UNIT7_PORT_WIDTH_MOD_GROUP_SETTINGS 2589 PortWidthModulationGroupSettings[MPI2_SAS_IOUNIT7_GROUP_MAX]; /* 0x18 */ 2590 } MPI2_CONFIG_PAGE_SASIOUNIT_7, 2591 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_7, 2592 Mpi2SasIOUnitPage7_t, MPI2_POINTER pMpi2SasIOUnitPage7_t; 2593 2594 #define MPI2_SASIOUNITPAGE7_PAGEVERSION (0x00) 2595 2596 2597 /* SAS IO Unit Page 8 */ 2598 2599 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT_8 2600 { 2601 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2602 U32 Reserved1; /* 0x08 */ 2603 U32 PowerManagementCapabilities; /* 0x0C */ 2604 U8 TxRxSleepStatus; /* 0x10 */ /* reserved in MPI 2.0 */ 2605 U8 Reserved2; /* 0x11 */ 2606 U16 Reserved3; /* 0x12 */ 2607 } MPI2_CONFIG_PAGE_SASIOUNIT_8, 2608 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT_8, 2609 Mpi2SasIOUnitPage8_t, MPI2_POINTER pMpi2SasIOUnitPage8_t; 2610 2611 #define MPI2_SASIOUNITPAGE8_PAGEVERSION (0x00) 2612 2613 /* defines for PowerManagementCapabilities field */ 2614 #define MPI2_SASIOUNIT8_PM_HOST_PORT_WIDTH_MOD (0x00001000) 2615 #define MPI2_SASIOUNIT8_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 2616 #define MPI2_SASIOUNIT8_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 2617 #define MPI2_SASIOUNIT8_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 2618 #define MPI2_SASIOUNIT8_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 2619 #define MPI2_SASIOUNIT8_PM_IOUNIT_PORT_WIDTH_MOD (0x00000010) 2620 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 2621 #define MPI2_SASIOUNIT8_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 2622 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 2623 #define MPI2_SASIOUNIT8_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 2624 2625 /* defines for TxRxSleepStatus field */ 2626 #define MPI25_SASIOUNIT8_TXRXSLEEP_UNSUPPORTED (0x00) 2627 #define MPI25_SASIOUNIT8_TXRXSLEEP_DISENGAGED (0x01) 2628 #define MPI25_SASIOUNIT8_TXRXSLEEP_ACTIVE (0x02) 2629 #define MPI25_SASIOUNIT8_TXRXSLEEP_SHUTDOWN (0x03) 2630 2631 2632 2633 /* SAS IO Unit Page 16 */ 2634 2635 typedef struct _MPI2_CONFIG_PAGE_SASIOUNIT16 2636 { 2637 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2638 U64 TimeStamp; /* 0x08 */ 2639 U32 Reserved1; /* 0x10 */ 2640 U32 Reserved2; /* 0x14 */ 2641 U32 FastPathPendedRequests; /* 0x18 */ 2642 U32 FastPathUnPendedRequests; /* 0x1C */ 2643 U32 FastPathHostRequestStarts; /* 0x20 */ 2644 U32 FastPathFirmwareRequestStarts; /* 0x24 */ 2645 U32 FastPathHostCompletions; /* 0x28 */ 2646 U32 FastPathFirmwareCompletions; /* 0x2C */ 2647 U32 NonFastPathRequestStarts; /* 0x30 */ 2648 U32 NonFastPathHostCompletions; /* 0x30 */ 2649 } MPI2_CONFIG_PAGE_SASIOUNIT16, 2650 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SASIOUNIT16, 2651 Mpi2SasIOUnitPage16_t, MPI2_POINTER pMpi2SasIOUnitPage16_t; 2652 2653 #define MPI2_SASIOUNITPAGE16_PAGEVERSION (0x00) 2654 2655 2656 /**************************************************************************** 2657 * SAS Expander Config Pages 2658 ****************************************************************************/ 2659 2660 /* SAS Expander Page 0 */ 2661 2662 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_0 2663 { 2664 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2665 U8 PhysicalPort; /* 0x08 */ 2666 U8 ReportGenLength; /* 0x09 */ 2667 U16 EnclosureHandle; /* 0x0A */ 2668 U64 SASAddress; /* 0x0C */ 2669 U32 DiscoveryStatus; /* 0x14 */ 2670 U16 DevHandle; /* 0x18 */ 2671 U16 ParentDevHandle; /* 0x1A */ 2672 U16 ExpanderChangeCount; /* 0x1C */ 2673 U16 ExpanderRouteIndexes; /* 0x1E */ 2674 U8 NumPhys; /* 0x20 */ 2675 U8 SASLevel; /* 0x21 */ 2676 U16 Flags; /* 0x22 */ 2677 U16 STPBusInactivityTimeLimit; /* 0x24 */ 2678 U16 STPMaxConnectTimeLimit; /* 0x26 */ 2679 U16 STP_SMP_NexusLossTime; /* 0x28 */ 2680 U16 MaxNumRoutedSasAddresses; /* 0x2A */ 2681 U64 ActiveZoneManagerSASAddress;/* 0x2C */ 2682 U16 ZoneLockInactivityLimit; /* 0x34 */ 2683 U16 Reserved1; /* 0x36 */ 2684 U8 TimeToReducedFunc; /* 0x38 */ 2685 U8 InitialTimeToReducedFunc; /* 0x39 */ 2686 U8 MaxReducedFuncTime; /* 0x3A */ 2687 U8 Reserved2; /* 0x3B */ 2688 } MPI2_CONFIG_PAGE_EXPANDER_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_0, 2689 Mpi2ExpanderPage0_t, MPI2_POINTER pMpi2ExpanderPage0_t; 2690 2691 #define MPI2_SASEXPANDER0_PAGEVERSION (0x06) 2692 2693 /* values for SAS Expander Page 0 DiscoveryStatus field */ 2694 #define MPI2_SAS_EXPANDER0_DS_MAX_ENCLOSURES_EXCEED (0x80000000) 2695 #define MPI2_SAS_EXPANDER0_DS_MAX_EXPANDERS_EXCEED (0x40000000) 2696 #define MPI2_SAS_EXPANDER0_DS_MAX_DEVICES_EXCEED (0x20000000) 2697 #define MPI2_SAS_EXPANDER0_DS_MAX_TOPO_PHYS_EXCEED (0x10000000) 2698 #define MPI2_SAS_EXPANDER0_DS_DOWNSTREAM_INITIATOR (0x08000000) 2699 #define MPI2_SAS_EXPANDER0_DS_MULTI_SUBTRACTIVE_SUBTRACTIVE (0x00008000) 2700 #define MPI2_SAS_EXPANDER0_DS_EXP_MULTI_SUBTRACTIVE (0x00004000) 2701 #define MPI2_SAS_EXPANDER0_DS_MULTI_PORT_DOMAIN (0x00002000) 2702 #define MPI2_SAS_EXPANDER0_DS_TABLE_TO_SUBTRACTIVE_LINK (0x00001000) 2703 #define MPI2_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800) 2704 #define MPI2_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400) 2705 #define MPI2_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200) 2706 #define MPI2_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100) 2707 #define MPI2_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080) 2708 #define MPI2_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040) 2709 #define MPI2_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020) 2710 #define MPI2_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010) 2711 #define MPI2_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004) 2712 #define MPI2_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002) 2713 #define MPI2_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001) 2714 2715 /* values for SAS Expander Page 0 Flags field */ 2716 #define MPI2_SAS_EXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2717 #define MPI2_SAS_EXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2718 #define MPI2_SAS_EXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2719 #define MPI2_SAS_EXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2720 #define MPI2_SAS_EXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2721 #define MPI2_SAS_EXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2722 #define MPI2_SAS_EXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2723 #define MPI2_SAS_EXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2724 #define MPI2_SAS_EXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2725 #define MPI2_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2726 #define MPI2_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2727 2728 2729 /* SAS Expander Page 1 */ 2730 2731 typedef struct _MPI2_CONFIG_PAGE_EXPANDER_1 2732 { 2733 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2734 U8 PhysicalPort; /* 0x08 */ 2735 U8 Reserved1; /* 0x09 */ 2736 U16 Reserved2; /* 0x0A */ 2737 U8 NumPhys; /* 0x0C */ 2738 U8 Phy; /* 0x0D */ 2739 U16 NumTableEntriesProgrammed; /* 0x0E */ 2740 U8 ProgrammedLinkRate; /* 0x10 */ 2741 U8 HwLinkRate; /* 0x11 */ 2742 U16 AttachedDevHandle; /* 0x12 */ 2743 U32 PhyInfo; /* 0x14 */ 2744 U32 AttachedDeviceInfo; /* 0x18 */ 2745 U16 ExpanderDevHandle; /* 0x1C */ 2746 U8 ChangeCount; /* 0x1E */ 2747 U8 NegotiatedLinkRate; /* 0x1F */ 2748 U8 PhyIdentifier; /* 0x20 */ 2749 U8 AttachedPhyIdentifier; /* 0x21 */ 2750 U8 Reserved3; /* 0x22 */ 2751 U8 DiscoveryInfo; /* 0x23 */ 2752 U32 AttachedPhyInfo; /* 0x24 */ 2753 U8 ZoneGroup; /* 0x28 */ 2754 U8 SelfConfigStatus; /* 0x29 */ 2755 U16 Reserved4; /* 0x2A */ 2756 } MPI2_CONFIG_PAGE_EXPANDER_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXPANDER_1, 2757 Mpi2ExpanderPage1_t, MPI2_POINTER pMpi2ExpanderPage1_t; 2758 2759 #define MPI2_SASEXPANDER1_PAGEVERSION (0x02) 2760 2761 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2762 2763 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2764 2765 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2766 2767 /* see mpi2_sas.h for the MPI2_SAS_DEVICE_INFO_ defines used for the AttachedDeviceInfo field */ 2768 2769 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2770 2771 /* values for SAS Expander Page 1 DiscoveryInfo field */ 2772 #define MPI2_SAS_EXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2773 #define MPI2_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2774 #define MPI2_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2775 2776 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2777 2778 2779 /**************************************************************************** 2780 * SAS Device Config Pages 2781 ****************************************************************************/ 2782 2783 /* SAS Device Page 0 */ 2784 2785 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_0 2786 { 2787 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2788 U16 Slot; /* 0x08 */ 2789 U16 EnclosureHandle; /* 0x0A */ 2790 U64 SASAddress; /* 0x0C */ 2791 U16 ParentDevHandle; /* 0x14 */ 2792 U8 PhyNum; /* 0x16 */ 2793 U8 AccessStatus; /* 0x17 */ 2794 U16 DevHandle; /* 0x18 */ 2795 U8 AttachedPhyIdentifier; /* 0x1A */ 2796 U8 ZoneGroup; /* 0x1B */ 2797 U32 DeviceInfo; /* 0x1C */ 2798 U16 Flags; /* 0x20 */ 2799 U8 PhysicalPort; /* 0x22 */ 2800 U8 MaxPortConnections; /* 0x23 */ 2801 U64 DeviceName; /* 0x24 */ 2802 U8 PortGroups; /* 0x2C */ 2803 U8 DmaGroup; /* 0x2D */ 2804 U8 ControlGroup; /* 0x2E */ 2805 U8 EnclosureLevel; /* 0x2F */ 2806 U8 ConnectorName[4]; /* 0x30 */ 2807 U32 Reserved3; /* 0x34 */ 2808 } MPI2_CONFIG_PAGE_SAS_DEV_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_0, 2809 Mpi2SasDevicePage0_t, MPI2_POINTER pMpi2SasDevicePage0_t; 2810 2811 #define MPI2_SASDEVICE0_PAGEVERSION (0x09) 2812 2813 /* values for SAS Device Page 0 AccessStatus field */ 2814 #define MPI2_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00) 2815 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01) 2816 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02) 2817 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_AFFILIATION_CONFLICT (0x03) 2818 #define MPI2_SAS_DEVICE0_ASTATUS_SATA_NEEDS_INITIALIZATION (0x04) 2819 #define MPI2_SAS_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x05) 2820 #define MPI2_SAS_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x06) 2821 #define MPI2_SAS_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x07) 2822 /* specific values for SATA Init failures */ 2823 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UNKNOWN (0x10) 2824 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x11) 2825 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_DIAG (0x12) 2826 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x13) 2827 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x14) 2828 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_PIO_SN (0x15) 2829 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MDMA_SN (0x16) 2830 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_UDMA_SN (0x17) 2831 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x18) 2832 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x19) 2833 #define MPI2_SAS_DEVICE0_ASTATUS_SIF_MAX (0x1F) 2834 2835 /* see mpi2_sas.h for values for SAS Device Page 0 DeviceInfo values */ 2836 2837 /* values for SAS Device Page 0 Flags field */ 2838 #define MPI2_SAS_DEVICE0_FLAGS_UNAUTHORIZED_DEVICE (0x8000) 2839 #define MPI25_SAS_DEVICE0_FLAGS_ENABLED_FAST_PATH (0x4000) 2840 #define MPI25_SAS_DEVICE0_FLAGS_FAST_PATH_CAPABLE (0x2000) 2841 #define MPI2_SAS_DEVICE0_FLAGS_SLUMBER_PM_CAPABLE (0x1000) 2842 #define MPI2_SAS_DEVICE0_FLAGS_PARTIAL_PM_CAPABLE (0x0800) 2843 #define MPI2_SAS_DEVICE0_FLAGS_SATA_ASYNCHRONOUS_NOTIFY (0x0400) 2844 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200) 2845 #define MPI2_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100) 2846 #define MPI2_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080) 2847 #define MPI2_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040) 2848 #define MPI2_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020) 2849 #define MPI2_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010) 2850 #define MPI2_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008) 2851 #define MPI2_SAS_DEVICE0_FLAGS_PERSIST_CAPABLE (0x0004) 2852 #define MPI2_SAS_DEVICE0_FLAGS_ENCL_LEVEL_VALID (0x0002) 2853 #define MPI2_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 2854 2855 /* SAS Device Page 1 */ 2856 2857 typedef struct _MPI2_CONFIG_PAGE_SAS_DEV_1 2858 { 2859 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2860 U32 Reserved1; /* 0x08 */ 2861 U64 SASAddress; /* 0x0C */ 2862 U32 Reserved2; /* 0x14 */ 2863 U16 DevHandle; /* 0x18 */ 2864 U16 Reserved3; /* 0x1A */ 2865 U8 InitialRegDeviceFIS[20];/* 0x1C */ 2866 } MPI2_CONFIG_PAGE_SAS_DEV_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_DEV_1, 2867 Mpi2SasDevicePage1_t, MPI2_POINTER pMpi2SasDevicePage1_t; 2868 2869 #define MPI2_SASDEVICE1_PAGEVERSION (0x01) 2870 2871 2872 /**************************************************************************** 2873 * SAS PHY Config Pages 2874 ****************************************************************************/ 2875 2876 /* SAS PHY Page 0 */ 2877 2878 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_0 2879 { 2880 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2881 U16 OwnerDevHandle; /* 0x08 */ 2882 U16 Reserved1; /* 0x0A */ 2883 U16 AttachedDevHandle; /* 0x0C */ 2884 U8 AttachedPhyIdentifier; /* 0x0E */ 2885 U8 Reserved2; /* 0x0F */ 2886 U32 AttachedPhyInfo; /* 0x10 */ 2887 U8 ProgrammedLinkRate; /* 0x14 */ 2888 U8 HwLinkRate; /* 0x15 */ 2889 U8 ChangeCount; /* 0x16 */ 2890 U8 Flags; /* 0x17 */ 2891 U32 PhyInfo; /* 0x18 */ 2892 U8 NegotiatedLinkRate; /* 0x1C */ 2893 U8 Reserved3; /* 0x1D */ 2894 U16 Reserved4; /* 0x1E */ 2895 } MPI2_CONFIG_PAGE_SAS_PHY_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_0, 2896 Mpi2SasPhyPage0_t, MPI2_POINTER pMpi2SasPhyPage0_t; 2897 2898 #define MPI2_SASPHY0_PAGEVERSION (0x03) 2899 2900 /* use MPI2_SAS_APHYINFO_ defines for AttachedPhyInfo field */ 2901 2902 /* use MPI2_SAS_PRATE_ defines for the ProgrammedLinkRate field */ 2903 2904 /* use MPI2_SAS_HWRATE_ defines for the HwLinkRate field */ 2905 2906 /* values for SAS PHY Page 0 Flags field */ 2907 #define MPI2_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2908 2909 /* use MPI2_SAS_PHYINFO_ for the PhyInfo field */ 2910 2911 /* use MPI2_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 2912 2913 2914 /* SAS PHY Page 1 */ 2915 2916 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_1 2917 { 2918 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2919 U32 Reserved1; /* 0x08 */ 2920 U32 InvalidDwordCount; /* 0x0C */ 2921 U32 RunningDisparityErrorCount; /* 0x10 */ 2922 U32 LossDwordSynchCount; /* 0x14 */ 2923 U32 PhyResetProblemCount; /* 0x18 */ 2924 } MPI2_CONFIG_PAGE_SAS_PHY_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_1, 2925 Mpi2SasPhyPage1_t, MPI2_POINTER pMpi2SasPhyPage1_t; 2926 2927 #define MPI2_SASPHY1_PAGEVERSION (0x01) 2928 2929 2930 /* SAS PHY Page 2 */ 2931 2932 typedef struct _MPI2_SASPHY2_PHY_EVENT 2933 { 2934 U8 PhyEventCode; /* 0x00 */ 2935 U8 Reserved1; /* 0x01 */ 2936 U16 Reserved2; /* 0x02 */ 2937 U32 PhyEventInfo; /* 0x04 */ 2938 } MPI2_SASPHY2_PHY_EVENT, MPI2_POINTER PTR_MPI2_SASPHY2_PHY_EVENT, 2939 Mpi2SasPhy2PhyEvent_t, MPI2_POINTER pMpi2SasPhy2PhyEvent_t; 2940 2941 /* use MPI2_SASPHY3_EVENT_CODE_ for the PhyEventCode field */ 2942 2943 2944 /* 2945 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 2946 * one and check the value returned for NumPhyEvents at runtime. 2947 */ 2948 #ifndef MPI2_SASPHY2_PHY_EVENT_MAX 2949 #define MPI2_SASPHY2_PHY_EVENT_MAX (1) 2950 #endif 2951 2952 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_2 2953 { 2954 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 2955 U32 Reserved1; /* 0x08 */ 2956 U8 NumPhyEvents; /* 0x0C */ 2957 U8 Reserved2; /* 0x0D */ 2958 U16 Reserved3; /* 0x0E */ 2959 MPI2_SASPHY2_PHY_EVENT PhyEvent[MPI2_SASPHY2_PHY_EVENT_MAX]; /* 0x10 */ 2960 } MPI2_CONFIG_PAGE_SAS_PHY_2, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_2, 2961 Mpi2SasPhyPage2_t, MPI2_POINTER pMpi2SasPhyPage2_t; 2962 2963 #define MPI2_SASPHY2_PAGEVERSION (0x00) 2964 2965 2966 /* SAS PHY Page 3 */ 2967 2968 typedef struct _MPI2_SASPHY3_PHY_EVENT_CONFIG 2969 { 2970 U8 PhyEventCode; /* 0x00 */ 2971 U8 Reserved1; /* 0x01 */ 2972 U16 Reserved2; /* 0x02 */ 2973 U8 CounterType; /* 0x04 */ 2974 U8 ThresholdWindow; /* 0x05 */ 2975 U8 TimeUnits; /* 0x06 */ 2976 U8 Reserved3; /* 0x07 */ 2977 U32 EventThreshold; /* 0x08 */ 2978 U16 ThresholdFlags; /* 0x0C */ 2979 U16 Reserved4; /* 0x0E */ 2980 } MPI2_SASPHY3_PHY_EVENT_CONFIG, MPI2_POINTER PTR_MPI2_SASPHY3_PHY_EVENT_CONFIG, 2981 Mpi2SasPhy3PhyEventConfig_t, MPI2_POINTER pMpi2SasPhy3PhyEventConfig_t; 2982 2983 /* values for PhyEventCode field */ 2984 #define MPI2_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2985 #define MPI2_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2986 #define MPI2_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2987 #define MPI2_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2988 #define MPI2_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2989 #define MPI2_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 2990 #define MPI2_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 2991 #define MPI2_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 2992 #define MPI2_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 2993 #define MPI2_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 2994 #define MPI2_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 2995 #define MPI2_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 2996 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 2997 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 2998 #define MPI2_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 2999 #define MPI2_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 3000 #define MPI2_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 3001 #define MPI2_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 3002 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 3003 #define MPI2_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 3004 #define MPI2_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 3005 #define MPI2_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 3006 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 3007 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 3008 #define MPI2_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 3009 #define MPI2_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 3010 #define MPI2_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 3011 #define MPI2_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 3012 #define MPI2_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 3013 #define MPI2_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 3014 #define MPI2_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 3015 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 3016 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 3017 #define MPI2_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 3018 #define MPI2_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 3019 #define MPI2_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 3020 #define MPI2_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 3021 /* Following codes are product specific and in MPI v2.6 and later */ 3022 #define MPI2_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3) 3023 #define MPI2_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4) 3024 #define MPI2_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5) 3025 #define MPI2_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6) 3026 #define MPI2_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7) 3027 #define MPI2_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8) 3028 #define MPI2_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9) 3029 #define MPI2_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA) 3030 #define MPI2_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB) 3031 #define MPI2_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC) 3032 3033 /* values for the CounterType field */ 3034 #define MPI2_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 3035 #define MPI2_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 3036 #define MPI2_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 3037 3038 /* values for the TimeUnits field */ 3039 #define MPI2_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 3040 #define MPI2_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 3041 #define MPI2_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 3042 #define MPI2_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 3043 3044 /* values for the ThresholdFlags field */ 3045 #define MPI2_SASPHY3_TFLAGS_PHY_RESET (0x0002) 3046 #define MPI2_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 3047 3048 /* 3049 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3050 * one and check the value returned for NumPhyEvents at runtime. 3051 */ 3052 #ifndef MPI2_SASPHY3_PHY_EVENT_MAX 3053 #define MPI2_SASPHY3_PHY_EVENT_MAX (1) 3054 #endif 3055 3056 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_3 3057 { 3058 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3059 U32 Reserved1; /* 0x08 */ 3060 U8 NumPhyEvents; /* 0x0C */ 3061 U8 Reserved2; /* 0x0D */ 3062 U16 Reserved3; /* 0x0E */ 3063 MPI2_SASPHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI2_SASPHY3_PHY_EVENT_MAX]; /* 0x10 */ 3064 } MPI2_CONFIG_PAGE_SAS_PHY_3, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_3, 3065 Mpi2SasPhyPage3_t, MPI2_POINTER pMpi2SasPhyPage3_t; 3066 3067 #define MPI2_SASPHY3_PAGEVERSION (0x00) 3068 3069 3070 /* SAS PHY Page 4 */ 3071 3072 typedef struct _MPI2_CONFIG_PAGE_SAS_PHY_4 3073 { 3074 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3075 U16 Reserved1; /* 0x08 */ 3076 U8 Reserved2; /* 0x0A */ 3077 U8 Flags; /* 0x0B */ 3078 U8 InitialFrame[28]; /* 0x0C */ 3079 } MPI2_CONFIG_PAGE_SAS_PHY_4, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PHY_4, 3080 Mpi2SasPhyPage4_t, MPI2_POINTER pMpi2SasPhyPage4_t; 3081 3082 #define MPI2_SASPHY4_PAGEVERSION (0x00) 3083 3084 /* values for the Flags field */ 3085 #define MPI2_SASPHY4_FLAGS_FRAME_VALID (0x02) 3086 #define MPI2_SASPHY4_FLAGS_SATA_FRAME (0x01) 3087 3088 3089 3090 3091 /**************************************************************************** 3092 * SAS Port Config Pages 3093 ****************************************************************************/ 3094 3095 /* SAS Port Page 0 */ 3096 3097 typedef struct _MPI2_CONFIG_PAGE_SAS_PORT_0 3098 { 3099 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3100 U8 PortNumber; /* 0x08 */ 3101 U8 PhysicalPort; /* 0x09 */ 3102 U8 PortWidth; /* 0x0A */ 3103 U8 PhysicalPortWidth; /* 0x0B */ 3104 U8 ZoneGroup; /* 0x0C */ 3105 U8 Reserved1; /* 0x0D */ 3106 U16 Reserved2; /* 0x0E */ 3107 U64 SASAddress; /* 0x10 */ 3108 U32 DeviceInfo; /* 0x18 */ 3109 U32 Reserved3; /* 0x1C */ 3110 U32 Reserved4; /* 0x20 */ 3111 } MPI2_CONFIG_PAGE_SAS_PORT_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_PORT_0, 3112 Mpi2SasPortPage0_t, MPI2_POINTER pMpi2SasPortPage0_t; 3113 3114 #define MPI2_SASPORT0_PAGEVERSION (0x00) 3115 3116 /* see mpi2_sas.h for values for SAS Port Page 0 DeviceInfo values */ 3117 3118 3119 /**************************************************************************** 3120 * SAS Enclosure Config Pages 3121 ****************************************************************************/ 3122 3123 /* SAS Enclosure Page 0, Enclosure Page 0 */ 3124 3125 typedef struct _MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0 3126 { 3127 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3128 U32 Reserved1; /* 0x08 */ 3129 U64 EnclosureLogicalID; /* 0x0C */ 3130 U16 Flags; /* 0x14 */ 3131 U16 EnclosureHandle; /* 0x16 */ 3132 U16 NumSlots; /* 0x18 */ 3133 U16 StartSlot; /* 0x1A */ 3134 U8 ChassisSlot; /* 0x1C */ 3135 U8 EnclosureLevel; /* 0x1D */ 3136 U16 SEPDevHandle; /* 0x1E */ 3137 U8 OEMRD; /* 0x20 */ 3138 U8 Reserved1a; /* 0x21 */ 3139 U16 Reserved2; /* 0x22 */ 3140 U32 Reserved3; /* 0x24 */ 3141 } MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3142 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_SAS_ENCLOSURE_0, 3143 Mpi2SasEnclosurePage0_t, MPI2_POINTER pMpi2SasEnclosurePage0_t, 3144 MPI26_CONFIG_PAGE_ENCLOSURE_0, 3145 MPI2_POINTER PTR_MPI26_CONFIG_PAGE_ENCLOSURE_0, 3146 Mpi26EnclosurePage0_t, MPI2_POINTER pMpi26EnclosurePage0_t; 3147 3148 #define MPI2_SASENCLOSURE0_PAGEVERSION (0x04) 3149 3150 /* values for SAS Enclosure Page 0 Flags field */ 3151 #define MPI26_SAS_ENCLS0_FLAGS_OEMRD_VALID (0x0080) 3152 #define MPI26_SAS_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040) 3153 #define MPI2_SAS_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3154 #define MPI2_SAS_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3155 #define MPI2_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F) 3156 #define MPI2_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3157 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3158 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3159 #define MPI2_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3160 #define MPI2_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3161 #define MPI2_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3162 3163 #define MPI26_ENCLOSURE0_PAGEVERSION (0x04) 3164 3165 /* Values for Enclosure Page 0 Flags field */ 3166 #define MPI26_ENCLS0_FLAGS_OEMRD_VALID (0x0080) 3167 #define MPI26_ENCLS0_FLAGS_OEMRD_COLLECTING (0x0040) 3168 #define MPI26_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3169 #define MPI26_ENCLS0_FLAGS_ENCL_LEVEL_VALID (0x0010) 3170 #define MPI26_ENCLS0_FLAGS_MNG_MASK (0x000F) 3171 #define MPI26_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3172 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3173 #define MPI26_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002) 3174 #define MPI26_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003) 3175 #define MPI26_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004) 3176 #define MPI26_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005) 3177 3178 /**************************************************************************** 3179 * Log Config Page 3180 ****************************************************************************/ 3181 3182 /* Log Page 0 */ 3183 3184 /* 3185 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3186 * one and check the value returned for NumLogEntries at runtime. 3187 */ 3188 #ifndef MPI2_LOG_0_NUM_LOG_ENTRIES 3189 #define MPI2_LOG_0_NUM_LOG_ENTRIES (1) 3190 #endif 3191 3192 #define MPI2_LOG_0_LOG_DATA_LENGTH (0x1C) 3193 3194 typedef struct _MPI2_LOG_0_ENTRY 3195 { 3196 U64 TimeStamp; /* 0x00 */ 3197 U32 Reserved1; /* 0x08 */ 3198 U16 LogSequence; /* 0x0C */ 3199 U16 LogEntryQualifier; /* 0x0E */ 3200 U8 VP_ID; /* 0x10 */ 3201 U8 VF_ID; /* 0x11 */ 3202 U16 Reserved2; /* 0x12 */ 3203 U8 LogData[MPI2_LOG_0_LOG_DATA_LENGTH];/* 0x14 */ 3204 } MPI2_LOG_0_ENTRY, MPI2_POINTER PTR_MPI2_LOG_0_ENTRY, 3205 Mpi2Log0Entry_t, MPI2_POINTER pMpi2Log0Entry_t; 3206 3207 /* values for Log Page 0 LogEntry LogEntryQualifier field */ 3208 #define MPI2_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000) 3209 #define MPI2_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001) 3210 #define MPI2_LOG_0_ENTRY_QUAL_TIMESTAMP_UPDATE (0x0002) 3211 #define MPI2_LOG_0_ENTRY_QUAL_MIN_IMPLEMENT_SPEC (0x8000) 3212 #define MPI2_LOG_0_ENTRY_QUAL_MAX_IMPLEMENT_SPEC (0xFFFF) 3213 3214 typedef struct _MPI2_CONFIG_PAGE_LOG_0 3215 { 3216 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3217 U32 Reserved1; /* 0x08 */ 3218 U32 Reserved2; /* 0x0C */ 3219 U16 NumLogEntries; /* 0x10 */ 3220 U16 Reserved3; /* 0x12 */ 3221 MPI2_LOG_0_ENTRY LogEntry[MPI2_LOG_0_NUM_LOG_ENTRIES]; /* 0x14 */ 3222 } MPI2_CONFIG_PAGE_LOG_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_LOG_0, 3223 Mpi2LogPage0_t, MPI2_POINTER pMpi2LogPage0_t; 3224 3225 #define MPI2_LOG_0_PAGEVERSION (0x02) 3226 3227 3228 /**************************************************************************** 3229 * RAID Config Page 3230 ****************************************************************************/ 3231 3232 /* RAID Page 0 */ 3233 3234 /* 3235 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3236 * one and check the value returned for NumElements at runtime. 3237 */ 3238 #ifndef MPI2_RAIDCONFIG0_MAX_ELEMENTS 3239 #define MPI2_RAIDCONFIG0_MAX_ELEMENTS (1) 3240 #endif 3241 3242 typedef struct _MPI2_RAIDCONFIG0_CONFIG_ELEMENT 3243 { 3244 U16 ElementFlags; /* 0x00 */ 3245 U16 VolDevHandle; /* 0x02 */ 3246 U8 HotSparePool; /* 0x04 */ 3247 U8 PhysDiskNum; /* 0x05 */ 3248 U16 PhysDiskDevHandle; /* 0x06 */ 3249 } MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3250 MPI2_POINTER PTR_MPI2_RAIDCONFIG0_CONFIG_ELEMENT, 3251 Mpi2RaidConfig0ConfigElement_t, MPI2_POINTER pMpi2RaidConfig0ConfigElement_t; 3252 3253 /* values for the ElementFlags field */ 3254 #define MPI2_RAIDCONFIG0_EFLAGS_MASK_ELEMENT_TYPE (0x000F) 3255 #define MPI2_RAIDCONFIG0_EFLAGS_VOLUME_ELEMENT (0x0000) 3256 #define MPI2_RAIDCONFIG0_EFLAGS_VOL_PHYS_DISK_ELEMENT (0x0001) 3257 #define MPI2_RAIDCONFIG0_EFLAGS_HOT_SPARE_ELEMENT (0x0002) 3258 #define MPI2_RAIDCONFIG0_EFLAGS_OCE_ELEMENT (0x0003) 3259 3260 3261 typedef struct _MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0 3262 { 3263 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3264 U8 NumHotSpares; /* 0x08 */ 3265 U8 NumPhysDisks; /* 0x09 */ 3266 U8 NumVolumes; /* 0x0A */ 3267 U8 ConfigNum; /* 0x0B */ 3268 U32 Flags; /* 0x0C */ 3269 U8 ConfigGUID[24]; /* 0x10 */ 3270 U32 Reserved1; /* 0x28 */ 3271 U8 NumElements; /* 0x2C */ 3272 U8 Reserved2; /* 0x2D */ 3273 U16 Reserved3; /* 0x2E */ 3274 MPI2_RAIDCONFIG0_CONFIG_ELEMENT ConfigElement[MPI2_RAIDCONFIG0_MAX_ELEMENTS]; /* 0x30 */ 3275 } MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3276 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_RAID_CONFIGURATION_0, 3277 Mpi2RaidConfigurationPage0_t, MPI2_POINTER pMpi2RaidConfigurationPage0_t; 3278 3279 #define MPI2_RAIDCONFIG0_PAGEVERSION (0x00) 3280 3281 /* values for RAID Configuration Page 0 Flags field */ 3282 #define MPI2_RAIDCONFIG0_FLAG_FOREIGN_CONFIG (0x00000001) 3283 3284 3285 /**************************************************************************** 3286 * Driver Persistent Mapping Config Pages 3287 ****************************************************************************/ 3288 3289 /* Driver Persistent Mapping Page 0 */ 3290 3291 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY 3292 { 3293 U64 PhysicalIdentifier; /* 0x00 */ 3294 U16 MappingInformation; /* 0x08 */ 3295 U16 DeviceIndex; /* 0x0A */ 3296 U32 PhysicalBitsMapping; /* 0x0C */ 3297 U32 Reserved1; /* 0x10 */ 3298 } MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3299 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY, 3300 Mpi2DriverMap0Entry_t, MPI2_POINTER pMpi2DriverMap0Entry_t; 3301 3302 typedef struct _MPI2_CONFIG_PAGE_DRIVER_MAPPING_0 3303 { 3304 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3305 MPI2_CONFIG_PAGE_DRIVER_MAP0_ENTRY Entry; /* 0x08 */ 3306 } MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3307 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_DRIVER_MAPPING_0, 3308 Mpi2DriverMappingPage0_t, MPI2_POINTER pMpi2DriverMappingPage0_t; 3309 3310 #define MPI2_DRIVERMAPPING0_PAGEVERSION (0x00) 3311 3312 /* values for Driver Persistent Mapping Page 0 MappingInformation field */ 3313 #define MPI2_DRVMAP0_MAPINFO_SLOT_MASK (0x07F0) 3314 #define MPI2_DRVMAP0_MAPINFO_SLOT_SHIFT (4) 3315 #define MPI2_DRVMAP0_MAPINFO_MISSING_MASK (0x000F) 3316 3317 3318 /**************************************************************************** 3319 * Ethernet Config Pages 3320 ****************************************************************************/ 3321 3322 /* Ethernet Page 0 */ 3323 3324 /* IP address (union of IPv4 and IPv6) */ 3325 typedef union _MPI2_ETHERNET_IP_ADDR 3326 { 3327 U32 IPv4Addr; 3328 U32 IPv6Addr[4]; 3329 } MPI2_ETHERNET_IP_ADDR, MPI2_POINTER PTR_MPI2_ETHERNET_IP_ADDR, 3330 Mpi2EthernetIpAddr_t, MPI2_POINTER pMpi2EthernetIpAddr_t; 3331 3332 #define MPI2_ETHERNET_HOST_NAME_LENGTH (32) 3333 3334 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_0 3335 { 3336 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3337 U8 NumInterfaces; /* 0x08 */ 3338 U8 Reserved0; /* 0x09 */ 3339 U16 Reserved1; /* 0x0A */ 3340 U32 Status; /* 0x0C */ 3341 U8 MediaState; /* 0x10 */ 3342 U8 Reserved2; /* 0x11 */ 3343 U16 Reserved3; /* 0x12 */ 3344 U8 MacAddress[6]; /* 0x14 */ 3345 U8 Reserved4; /* 0x1A */ 3346 U8 Reserved5; /* 0x1B */ 3347 MPI2_ETHERNET_IP_ADDR IpAddress; /* 0x1C */ 3348 MPI2_ETHERNET_IP_ADDR SubnetMask; /* 0x2C */ 3349 MPI2_ETHERNET_IP_ADDR GatewayIpAddress; /* 0x3C */ 3350 MPI2_ETHERNET_IP_ADDR DNS1IpAddress; /* 0x4C */ 3351 MPI2_ETHERNET_IP_ADDR DNS2IpAddress; /* 0x5C */ 3352 MPI2_ETHERNET_IP_ADDR DhcpIpAddress; /* 0x6C */ 3353 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 3354 } MPI2_CONFIG_PAGE_ETHERNET_0, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_0, 3355 Mpi2EthernetPage0_t, MPI2_POINTER pMpi2EthernetPage0_t; 3356 3357 #define MPI2_ETHERNETPAGE0_PAGEVERSION (0x00) 3358 3359 /* values for Ethernet Page 0 Status field */ 3360 #define MPI2_ETHPG0_STATUS_IPV6_CAPABLE (0x80000000) 3361 #define MPI2_ETHPG0_STATUS_IPV4_CAPABLE (0x40000000) 3362 #define MPI2_ETHPG0_STATUS_CONSOLE_CONNECTED (0x20000000) 3363 #define MPI2_ETHPG0_STATUS_DEFAULT_IF (0x00000100) 3364 #define MPI2_ETHPG0_STATUS_FW_DWNLD_ENABLED (0x00000080) 3365 #define MPI2_ETHPG0_STATUS_TELNET_ENABLED (0x00000040) 3366 #define MPI2_ETHPG0_STATUS_SSH2_ENABLED (0x00000020) 3367 #define MPI2_ETHPG0_STATUS_DHCP_CLIENT_ENABLED (0x00000010) 3368 #define MPI2_ETHPG0_STATUS_IPV6_ENABLED (0x00000008) 3369 #define MPI2_ETHPG0_STATUS_IPV4_ENABLED (0x00000004) 3370 #define MPI2_ETHPG0_STATUS_IPV6_ADDRESSES (0x00000002) 3371 #define MPI2_ETHPG0_STATUS_ETH_IF_ENABLED (0x00000001) 3372 3373 /* values for Ethernet Page 0 MediaState field */ 3374 #define MPI2_ETHPG0_MS_DUPLEX_MASK (0x80) 3375 #define MPI2_ETHPG0_MS_HALF_DUPLEX (0x00) 3376 #define MPI2_ETHPG0_MS_FULL_DUPLEX (0x80) 3377 3378 #define MPI2_ETHPG0_MS_CONNECT_SPEED_MASK (0x07) 3379 #define MPI2_ETHPG0_MS_NOT_CONNECTED (0x00) 3380 #define MPI2_ETHPG0_MS_10MBIT (0x01) 3381 #define MPI2_ETHPG0_MS_100MBIT (0x02) 3382 #define MPI2_ETHPG0_MS_1GBIT (0x03) 3383 3384 3385 /* Ethernet Page 1 */ 3386 3387 typedef struct _MPI2_CONFIG_PAGE_ETHERNET_1 3388 { 3389 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3390 U32 Reserved0; /* 0x08 */ 3391 U32 Flags; /* 0x0C */ 3392 U8 MediaState; /* 0x10 */ 3393 U8 Reserved1; /* 0x11 */ 3394 U16 Reserved2; /* 0x12 */ 3395 U8 MacAddress[6]; /* 0x14 */ 3396 U8 Reserved3; /* 0x1A */ 3397 U8 Reserved4; /* 0x1B */ 3398 MPI2_ETHERNET_IP_ADDR StaticIpAddress; /* 0x1C */ 3399 MPI2_ETHERNET_IP_ADDR StaticSubnetMask; /* 0x2C */ 3400 MPI2_ETHERNET_IP_ADDR StaticGatewayIpAddress; /* 0x3C */ 3401 MPI2_ETHERNET_IP_ADDR StaticDNS1IpAddress; /* 0x4C */ 3402 MPI2_ETHERNET_IP_ADDR StaticDNS2IpAddress; /* 0x5C */ 3403 U32 Reserved5; /* 0x6C */ 3404 U32 Reserved6; /* 0x70 */ 3405 U32 Reserved7; /* 0x74 */ 3406 U32 Reserved8; /* 0x78 */ 3407 U8 HostName[MPI2_ETHERNET_HOST_NAME_LENGTH];/* 0x7C */ 3408 } MPI2_CONFIG_PAGE_ETHERNET_1, MPI2_POINTER PTR_MPI2_CONFIG_PAGE_ETHERNET_1, 3409 Mpi2EthernetPage1_t, MPI2_POINTER pMpi2EthernetPage1_t; 3410 3411 #define MPI2_ETHERNETPAGE1_PAGEVERSION (0x00) 3412 3413 /* values for Ethernet Page 1 Flags field */ 3414 #define MPI2_ETHPG1_FLAG_SET_DEFAULT_IF (0x00000100) 3415 #define MPI2_ETHPG1_FLAG_ENABLE_FW_DOWNLOAD (0x00000080) 3416 #define MPI2_ETHPG1_FLAG_ENABLE_TELNET (0x00000040) 3417 #define MPI2_ETHPG1_FLAG_ENABLE_SSH2 (0x00000020) 3418 #define MPI2_ETHPG1_FLAG_ENABLE_DHCP_CLIENT (0x00000010) 3419 #define MPI2_ETHPG1_FLAG_ENABLE_IPV6 (0x00000008) 3420 #define MPI2_ETHPG1_FLAG_ENABLE_IPV4 (0x00000004) 3421 #define MPI2_ETHPG1_FLAG_USE_IPV6_ADDRESSES (0x00000002) 3422 #define MPI2_ETHPG1_FLAG_ENABLE_ETH_IF (0x00000001) 3423 3424 /* values for Ethernet Page 1 MediaState field */ 3425 #define MPI2_ETHPG1_MS_DUPLEX_MASK (0x80) 3426 #define MPI2_ETHPG1_MS_HALF_DUPLEX (0x00) 3427 #define MPI2_ETHPG1_MS_FULL_DUPLEX (0x80) 3428 3429 #define MPI2_ETHPG1_MS_DATA_RATE_MASK (0x07) 3430 #define MPI2_ETHPG1_MS_DATA_RATE_AUTO (0x00) 3431 #define MPI2_ETHPG1_MS_DATA_RATE_10MBIT (0x01) 3432 #define MPI2_ETHPG1_MS_DATA_RATE_100MBIT (0x02) 3433 #define MPI2_ETHPG1_MS_DATA_RATE_1GBIT (0x03) 3434 3435 3436 /**************************************************************************** 3437 * Extended Manufacturing Config Pages 3438 ****************************************************************************/ 3439 3440 /* 3441 * Generic structure to use for product-specific extended manufacturing pages 3442 * (currently Extended Manufacturing Page 40 through Extended Manufacturing 3443 * Page 60). 3444 */ 3445 3446 typedef struct _MPI2_CONFIG_PAGE_EXT_MAN_PS 3447 { 3448 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3449 U32 ProductSpecificInfo; /* 0x08 */ 3450 } MPI2_CONFIG_PAGE_EXT_MAN_PS, 3451 MPI2_POINTER PTR_MPI2_CONFIG_PAGE_EXT_MAN_PS, 3452 Mpi2ExtManufacturingPagePS_t, MPI2_POINTER pMpi2ExtManufacturingPagePS_t; 3453 3454 /* PageVersion should be provided by product-specific code */ 3455 3456 3457 /**************************************************************************** 3458 * values for fields used by several types of PCIe Config Pages 3459 ****************************************************************************/ 3460 3461 /* values for NegotiatedLinkRates fields */ 3462 #define MPI26_PCIE_NEG_LINK_RATE_MASK_PHYSICAL (0x0F) 3463 /* link rates used for Negotiated Physical Link Rate */ 3464 #define MPI26_PCIE_NEG_LINK_RATE_UNKNOWN (0x00) 3465 #define MPI26_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01) 3466 #define MPI26_PCIE_NEG_LINK_RATE_2_5 (0x02) 3467 #define MPI26_PCIE_NEG_LINK_RATE_5_0 (0x03) 3468 #define MPI26_PCIE_NEG_LINK_RATE_8_0 (0x04) 3469 #define MPI26_PCIE_NEG_LINK_RATE_16_0 (0x05) 3470 3471 3472 /**************************************************************************** 3473 * PCIe IO Unit Config Pages (MPI v2.6 and later) 3474 ****************************************************************************/ 3475 3476 /* PCIe IO Unit Page 0 */ 3477 3478 typedef struct _MPI26_PCIE_IO_UNIT0_PHY_DATA 3479 { 3480 U8 Link; /* 0x00 */ 3481 U8 LinkFlags; /* 0x01 */ 3482 U8 PhyFlags; /* 0x02 */ 3483 U8 NegotiatedLinkRate; /* 0x03 */ 3484 U32 ControllerPhyDeviceInfo;/* 0x04 */ 3485 U16 AttachedDevHandle; /* 0x08 */ 3486 U16 ControllerDevHandle; /* 0x0A */ 3487 U32 EnumerationStatus; /* 0x0C */ 3488 U32 Reserved1; /* 0x10 */ 3489 } MPI26_PCIE_IO_UNIT0_PHY_DATA, MPI2_POINTER PTR_MPI26_PCIE_IO_UNIT0_PHY_DATA, 3490 Mpi26PCIeIOUnit0PhyData_t, MPI2_POINTER pMpi26PCIeIOUnit0PhyData_t; 3491 3492 /* 3493 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3494 * one and check the value returned for NumPhys at runtime. 3495 */ 3496 #ifndef MPI26_PCIE_IOUNIT0_PHY_MAX 3497 #define MPI26_PCIE_IOUNIT0_PHY_MAX (1) 3498 #endif 3499 3500 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_0 3501 { 3502 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3503 U32 Reserved1; /* 0x08 */ 3504 U8 NumPhys; /* 0x0C */ 3505 U8 InitStatus; /* 0x0D */ 3506 U16 Reserved3; /* 0x0E */ 3507 MPI26_PCIE_IO_UNIT0_PHY_DATA PhyData[MPI26_PCIE_IOUNIT0_PHY_MAX]; /* 0x10 */ 3508 } MPI26_CONFIG_PAGE_PIOUNIT_0, 3509 MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PIOUNIT_0, 3510 Mpi26PCIeIOUnitPage0_t, MPI2_POINTER pMpi26PCIeIOUnitPage0_t; 3511 3512 #define MPI26_PCIEIOUNITPAGE0_PAGEVERSION (0x00) 3513 3514 /* values for PCIe IO Unit Page 0 LinkFlags */ 3515 #define MPI26_PCIEIOUNIT0_LINKFLAGS_ENUMERATION_IN_PROGRESS (0x08) 3516 3517 /* values for PCIe IO Unit Page 0 PhyFlags */ 3518 #define MPI26_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 3519 3520 /* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3521 3522 /* see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo values */ 3523 3524 /* values for PCIe IO Unit Page 0 EnumerationStatus */ 3525 #define MPI26_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000) 3526 #define MPI26_PCIEIOUNIT0_ES_MAX_DEVICES_EXCEEDED (0x20000000) 3527 3528 3529 /* PCIe IO Unit Page 1 */ 3530 3531 typedef struct _MPI26_PCIE_IO_UNIT1_PHY_DATA 3532 { 3533 U8 Link; /* 0x00 */ 3534 U8 LinkFlags; /* 0x01 */ 3535 U8 PhyFlags; /* 0x02 */ 3536 U8 MaxMinLinkRate; /* 0x03 */ 3537 U32 ControllerPhyDeviceInfo; /* 0x04 */ 3538 U32 Reserved1; /* 0x08 */ 3539 } MPI26_PCIE_IO_UNIT1_PHY_DATA, MPI2_POINTER PTR_MPI26_PCIE_IO_UNIT1_PHY_DATA, 3540 Mpi26PCIeIOUnit1PhyData_t, MPI2_POINTER pMpi26PCIeIOUnit1PhyData_t; 3541 3542 /* values for LinkFlags */ 3543 #define MPI26_PCIEIOUNIT1_LINKFLAGS_DIS_SEPARATE_REFCLK (0x00) 3544 #define MPI26_PCIEIOUNIT1_LINKFLAGS_SRIS_EN (0x01) 3545 #define MPI26_PCIEIOUNIT1_LINKFLAGS_SRNS_EN (0x02) 3546 3547 /* 3548 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3549 * one and check the value returned for NumPhys at runtime. 3550 */ 3551 #ifndef MPI26_PCIE_IOUNIT1_PHY_MAX 3552 #define MPI26_PCIE_IOUNIT1_PHY_MAX (1) 3553 #endif 3554 3555 typedef struct _MPI26_CONFIG_PAGE_PIOUNIT_1 3556 { 3557 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3558 U16 ControlFlags; /* 0x08 */ 3559 U16 Reserved; /* 0x0A */ 3560 U16 AdditionalControlFlags; /* 0x0C */ 3561 U16 NVMeMaxQueueDepth; /* 0x0E */ 3562 U8 NumPhys; /* 0x10 */ 3563 U8 DMDReportPCIe; /* 0x11 */ 3564 U16 Reserved2; /* 0x12 */ 3565 MPI26_PCIE_IO_UNIT1_PHY_DATA PhyData[MPI26_PCIE_IOUNIT1_PHY_MAX];/* 0x14 */ 3566 } MPI26_CONFIG_PAGE_PIOUNIT_1, 3567 MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PIOUNIT_1, 3568 Mpi26PCIeIOUnitPage1_t, MPI2_POINTER pMpi26PCIeIOUnitPage1_t; 3569 3570 #define MPI26_PCIEIOUNITPAGE1_PAGEVERSION (0x00) 3571 3572 /* values for PCIe IO Unit Page 1 PhyFlags */ 3573 #define MPI26_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 3574 #define MPI26_PCIEIOUNIT1_PHYFLAGS_ENDPOINT_ONLY (0x01) 3575 3576 /* values for PCIe IO Unit Page 1 MaxMinLinkRate */ 3577 #define MPI26_PCIEIOUNIT1_MAX_RATE_MASK (0xF0) 3578 #define MPI26_PCIEIOUNIT1_MAX_RATE_SHIFT (4) 3579 #define MPI26_PCIEIOUNIT1_MAX_RATE_2_5 (0x20) 3580 #define MPI26_PCIEIOUNIT1_MAX_RATE_5_0 (0x30) 3581 #define MPI26_PCIEIOUNIT1_MAX_RATE_8_0 (0x40) 3582 #define MPI26_PCIEIOUNIT1_MAX_RATE_16_0 (0x50) 3583 3584 /* values for PCIe IO Unit Page 1 DMDReportPCIe */ 3585 #define MPI26_PCIEIOUNIT1_DMD_REPORT_UNITS_MASK (0x80) 3586 #define MPI26_PCIEIOUNIT1_DMD_REPORT_UNITS_1_SEC (0x00) 3587 #define MPI26_PCIEIOUNIT1_DMD_REPORT_UNITS_16_SEC (0x80) 3588 #define MPI26_PCIEIOUNIT1_DMD_REPORT_DELAY_TIME_MASK (0x7F) 3589 3590 3591 /* see mpi2_pci.h for values for PCIe IO Unit Page 0 ControllerPhyDeviceInfo values */ 3592 3593 3594 /**************************************************************************** 3595 * PCIe Switch Config Pages (MPI v2.6 and later) 3596 ****************************************************************************/ 3597 3598 /* PCIe Switch Page 0 */ 3599 3600 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_0 3601 { 3602 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3603 U8 PhysicalPort; /* 0x08 */ 3604 U8 Reserved1; /* 0x09 */ 3605 U16 Reserved2; /* 0x0A */ 3606 U16 DevHandle; /* 0x0C */ 3607 U16 ParentDevHandle; /* 0x0E */ 3608 U8 NumPorts; /* 0x10 */ 3609 U8 PCIeLevel; /* 0x11 */ 3610 U16 Reserved3; /* 0x12 */ 3611 U32 Reserved4; /* 0x14 */ 3612 U32 Reserved5; /* 0x18 */ 3613 U32 Reserved6; /* 0x1C */ 3614 } MPI26_CONFIG_PAGE_PSWITCH_0, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PSWITCH_0, 3615 Mpi26PCIeSwitchPage0_t, MPI2_POINTER pMpi26PCIeSwitchPage0_t; 3616 3617 #define MPI26_PCIESWITCH0_PAGEVERSION (0x00) 3618 3619 3620 /* PCIe Switch Page 1 */ 3621 3622 typedef struct _MPI26_CONFIG_PAGE_PSWITCH_1 3623 { 3624 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3625 U8 PhysicalPort; /* 0x08 */ 3626 U8 Reserved1; /* 0x09 */ 3627 U16 Reserved2; /* 0x0A */ 3628 U8 NumPorts; /* 0x0C */ 3629 U8 PortNum; /* 0x0D */ 3630 U16 AttachedDevHandle; /* 0x0E */ 3631 U16 SwitchDevHandle; /* 0x10 */ 3632 U8 NegotiatedPortWidth; /* 0x12 */ 3633 U8 NegotiatedLinkRate; /* 0x13 */ 3634 U16 Flags; /* 0x14 */ 3635 U16 Reserved4; /* 0x16 */ 3636 U32 Reserved5; /* 0x18 */ 3637 } MPI26_CONFIG_PAGE_PSWITCH_1, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PSWITCH_1, 3638 Mpi26PCIeSwitchPage1_t, MPI2_POINTER pMpi26PCIeSwitchPage1_t; 3639 3640 #define MPI26_PCIESWITCH1_PAGEVERSION (0x00) 3641 3642 /* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3643 3644 /* defines for the Flags field */ 3645 #define MPI26_PCIESWITCH1_2_RETIMER_PRESENCE (0x0002) 3646 #define MPI26_PCIESWITCH1_RETIMER_PRESENCE (0x0001) 3647 3648 3649 3650 /**************************************************************************** 3651 * PCIe Device Config Pages (MPI v2.6 and later) 3652 ****************************************************************************/ 3653 3654 /* PCIe Device Page 0 */ 3655 3656 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_0 3657 { 3658 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3659 U16 Slot; /* 0x08 */ 3660 U16 EnclosureHandle; /* 0x0A */ 3661 U64 WWID; /* 0x0C */ 3662 U16 ParentDevHandle; /* 0x14 */ 3663 U8 PortNum; /* 0x16 */ 3664 U8 AccessStatus; /* 0x17 */ 3665 U16 DevHandle; /* 0x18 */ 3666 U8 PhysicalPort; /* 0x1A */ 3667 U8 Reserved1; /* 0x1B */ 3668 U32 DeviceInfo; /* 0x1C */ 3669 U32 Flags; /* 0x20 */ 3670 U8 SupportedLinkRates; /* 0x24 */ 3671 U8 MaxPortWidth; /* 0x25 */ 3672 U8 NegotiatedPortWidth; /* 0x26 */ 3673 U8 NegotiatedLinkRate; /* 0x27 */ 3674 U8 EnclosureLevel; /* 0x28 */ 3675 U8 Reserved2; /* 0x29 */ 3676 U16 Reserved3; /* 0x2A */ 3677 U8 ConnectorName[4]; /* 0x2C */ 3678 U32 Reserved4; /* 0x30 */ 3679 U32 Reserved5; /* 0x34 */ 3680 } MPI26_CONFIG_PAGE_PCIEDEV_0, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIEDEV_0, 3681 Mpi26PCIeDevicePage0_t, MPI2_POINTER pMpi26PCIeDevicePage0_t; 3682 3683 #define MPI26_PCIEDEVICE0_PAGEVERSION (0x01) 3684 3685 /* values for PCIe Device Page 0 AccessStatus field */ 3686 #define MPI26_PCIEDEV0_ASTATUS_NO_ERRORS (0x00) 3687 #define MPI26_PCIEDEV0_ASTATUS_NEEDS_INITIALIZATION (0x04) 3688 #define MPI26_PCIEDEV0_ASTATUS_CAPABILITY_FAILED (0x02) 3689 #define MPI26_PCIEDEV0_ASTATUS_DEVICE_BLOCKED (0x07) 3690 #define MPI26_PCIEDEV0_ASTATUS_MEMORY_SPACE_ACCESS_FAILED (0x08) 3691 #define MPI26_PCIEDEV0_ASTATUS_UNSUPPORTED_DEVICE (0x09) 3692 #define MPI26_PCIEDEV0_ASTATUS_MSIX_REQUIRED (0x0A) 3693 #define MPI26_PCIEDEV0_ASTATUS_UNKNOWN (0x10) 3694 3695 #define MPI26_PCIEDEV0_ASTATUS_NVME_READY_TIMEOUT (0x30) 3696 #define MPI26_PCIEDEV0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x31) 3697 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDENTIFY_FAILED (0x32) 3698 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCONFIG_FAILED (0x33) 3699 #define MPI26_PCIEDEV0_ASTATUS_NVME_QCREATION_FAILED (0x34) 3700 #define MPI26_PCIEDEV0_ASTATUS_NVME_EVENTCFG_FAILED (0x35) 3701 #define MPI26_PCIEDEV0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x36) 3702 #define MPI26_PCIEDEV0_ASTATUS_NVME_IDLE_TIMEOUT (0x37) 3703 #define MPI26_PCIEDEV0_ASTATUS_NVME_FAILURE_STATUS (0x38) 3704 3705 #define MPI26_PCIEDEV0_ASTATUS_INIT_FAIL_MAX (0x3F) 3706 3707 /* see mpi2_pci.h for the MPI26_PCIE_DEVINFO_ defines used for the DeviceInfo field */ 3708 3709 /* values for PCIe Device Page 0 Flags field */ 3710 #define MPI26_PCIEDEV0_FLAGS_2_RETIMER_PRESENCE (0x00020000) 3711 #define MPI26_PCIEDEV0_FLAGS_RETIMER_PRESENCE (0x00010000) 3712 #define MPI26_PCIEDEV0_FLAGS_UNAUTHORIZED_DEVICE (0x00008000) 3713 #define MPI26_PCIEDEV0_FLAGS_ENABLED_FAST_PATH (0x00004000) 3714 #define MPI26_PCIEDEV0_FLAGS_FAST_PATH_CAPABLE (0x00002000) 3715 #define MPI26_PCIEDEV0_FLAGS_ASYNCHRONOUS_NOTIFICATION (0x00000400) 3716 #define MPI26_PCIEDEV0_FLAGS_ATA_SW_PRESERVATION (0x00000200) 3717 #define MPI26_PCIEDEV0_FLAGS_UNSUPPORTED_DEVICE (0x00000100) 3718 #define MPI26_PCIEDEV0_FLAGS_ATA_48BIT_LBA_SUPPORTED (0x00000080) 3719 #define MPI26_PCIEDEV0_FLAGS_ATA_SMART_SUPPORTED (0x00000040) 3720 #define MPI26_PCIEDEV0_FLAGS_ATA_NCQ_SUPPORTED (0x00000020) 3721 #define MPI26_PCIEDEV0_FLAGS_ATA_FUA_SUPPORTED (0x00000010) 3722 #define MPI26_PCIEDEV0_FLAGS_ENCL_LEVEL_VALID (0x00000002) 3723 #define MPI26_PCIEDEV0_FLAGS_DEVICE_PRESENT (0x00000001) 3724 3725 /* values for PCIe Device Page 0 SupportedLinkRates field */ 3726 #define MPI26_PCIEDEV0_LINK_RATE_16_0_SUPPORTED (0x08) 3727 #define MPI26_PCIEDEV0_LINK_RATE_8_0_SUPPORTED (0x04) 3728 #define MPI26_PCIEDEV0_LINK_RATE_5_0_SUPPORTED (0x02) 3729 #define MPI26_PCIEDEV0_LINK_RATE_2_5_SUPPORTED (0x01) 3730 3731 /* use MPI26_PCIE_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field */ 3732 3733 3734 /* PCIe Device Page 2 */ 3735 3736 typedef struct _MPI26_CONFIG_PAGE_PCIEDEV_2 3737 { 3738 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3739 U16 DevHandle; /* 0x08 */ 3740 U8 ControllerResetTO; /* 0x0A */ 3741 U8 Reserved1; /* 0x0B */ 3742 U32 MaximumDataTransferSize;/* 0x0C */ 3743 U32 Capabilities; /* 0x10 */ 3744 U16 NOIOB; /* 0x14 */ 3745 U16 Reserved2; /* 0x16 */ 3746 } MPI26_CONFIG_PAGE_PCIEDEV_2, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIEDEV_2, 3747 Mpi26PCIeDevicePage2_t, MPI2_POINTER pMpi26PCIeDevicePage2_t; 3748 3749 #define MPI26_PCIEDEVICE2_PAGEVERSION (0x01) 3750 3751 /* defines for PCIe Device Page 2 Capabilities field */ 3752 #define MPI26_PCIEDEV2_CAP_DATA_BLK_ALIGN_AND_GRAN (0x00000008) 3753 #define MPI26_PCIEDEV2_CAP_SGL_FORMAT (0x00000004) 3754 #define MPI26_PCIEDEV2_CAP_BIT_BUCKET_SUPPORT (0x00000002) 3755 #define MPI26_PCIEDEV2_CAP_SGL_SUPPORT (0x00000001) 3756 3757 /* Defines for the NOIOB field */ 3758 #define MPI26_PCIEDEV2_NOIOB_UNSUPPORTED (0x0000) 3759 3760 3761 /**************************************************************************** 3762 * PCIe Link Config Pages (MPI v2.6 and later) 3763 ****************************************************************************/ 3764 3765 /* PCIe Link Page 1 */ 3766 3767 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_1 3768 { 3769 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3770 U8 Link; /* 0x08 */ 3771 U8 Reserved1; /* 0x09 */ 3772 U16 Reserved2; /* 0x0A */ 3773 U32 CorrectableErrorCount; /* 0x0C */ 3774 U16 NonFatalErrorCount; /* 0x10 */ 3775 U16 Reserved3; /* 0x12 */ 3776 U16 FatalErrorCount; /* 0x14 */ 3777 U16 Reserved4; /* 0x16 */ 3778 } MPI26_CONFIG_PAGE_PCIELINK_1, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_1, 3779 Mpi26PcieLinkPage1_t, MPI2_POINTER pMpi26PcieLinkPage1_t; 3780 3781 #define MPI26_PCIELINK1_PAGEVERSION (0x00) 3782 3783 /* PCIe Link Page 2 */ 3784 3785 typedef struct _MPI26_PCIELINK2_LINK_EVENT 3786 { 3787 U8 LinkEventCode; /* 0x00 */ 3788 U8 Reserved1; /* 0x01 */ 3789 U16 Reserved2; /* 0x02 */ 3790 U32 LinkEventInfo; /* 0x04 */ 3791 } MPI26_PCIELINK2_LINK_EVENT, MPI2_POINTER PTR_MPI26_PCIELINK2_LINK_EVENT, 3792 Mpi26PcieLink2LinkEvent_t, MPI2_POINTER pMpi26PcieLink2LinkEvent_t; 3793 3794 /* use MPI26_PCIELINK3_EVTCODE_ for the LinkEventCode field */ 3795 3796 3797 /* 3798 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3799 * one and check the value returned for NumLinkEvents at runtime. 3800 */ 3801 #ifndef MPI26_PCIELINK2_LINK_EVENT_MAX 3802 #define MPI26_PCIELINK2_LINK_EVENT_MAX (1) 3803 #endif 3804 3805 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_2 3806 { 3807 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3808 U8 Link; /* 0x08 */ 3809 U8 Reserved1; /* 0x09 */ 3810 U16 Reserved2; /* 0x0A */ 3811 U8 NumLinkEvents; /* 0x0C */ 3812 U8 Reserved3; /* 0x0D */ 3813 U16 Reserved4; /* 0x0E */ 3814 MPI26_PCIELINK2_LINK_EVENT LinkEvent[MPI26_PCIELINK2_LINK_EVENT_MAX]; /* 0x10 */ 3815 } MPI26_CONFIG_PAGE_PCIELINK_2, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_2, 3816 Mpi26PcieLinkPage2_t, MPI2_POINTER pMpi26PcieLinkPage2_t; 3817 3818 #define MPI26_PCIELINK2_PAGEVERSION (0x00) 3819 3820 3821 /* PCIe Link Page 3 */ 3822 3823 typedef struct _MPI26_PCIELINK3_LINK_EVENT_CONFIG 3824 { 3825 U8 LinkEventCode; /* 0x00 */ 3826 U8 Reserved1; /* 0x01 */ 3827 U16 Reserved2; /* 0x02 */ 3828 U8 CounterType; /* 0x04 */ 3829 U8 ThresholdWindow; /* 0x05 */ 3830 U8 TimeUnits; /* 0x06 */ 3831 U8 Reserved3; /* 0x07 */ 3832 U32 EventThreshold; /* 0x08 */ 3833 U16 ThresholdFlags; /* 0x0C */ 3834 U16 Reserved4; /* 0x0E */ 3835 } MPI26_PCIELINK3_LINK_EVENT_CONFIG, MPI2_POINTER PTR_MPI26_PCIELINK3_LINK_EVENT_CONFIG, 3836 Mpi26PcieLink3LinkEventConfig_t, MPI2_POINTER pMpi26PcieLink3LinkEventConfig_t; 3837 3838 /* values for LinkEventCode field */ 3839 #define MPI26_PCIELINK3_EVTCODE_NO_EVENT (0x00) 3840 #define MPI26_PCIELINK3_EVTCODE_CORRECTABLE_ERROR_RECEIVED (0x01) 3841 #define MPI26_PCIELINK3_EVTCODE_NON_FATAL_ERROR_RECEIVED (0x02) 3842 #define MPI26_PCIELINK3_EVTCODE_FATAL_ERROR_RECEIVED (0x03) 3843 #define MPI26_PCIELINK3_EVTCODE_DATA_LINK_ERROR_DETECTED (0x04) 3844 #define MPI26_PCIELINK3_EVTCODE_TRANSACTION_LAYER_ERROR_DETECTED (0x05) 3845 #define MPI26_PCIELINK3_EVTCODE_TLP_ECRC_ERROR_DETECTED (0x06) 3846 #define MPI26_PCIELINK3_EVTCODE_POISONED_TLP (0x07) 3847 #define MPI26_PCIELINK3_EVTCODE_RECEIVED_NAK_DLLP (0x08) 3848 #define MPI26_PCIELINK3_EVTCODE_SENT_NAK_DLLP (0x09) 3849 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RECOVERY_STATE (0x0A) 3850 #define MPI26_PCIELINK3_EVTCODE_LTSSM_RXL0S_STATE (0x0B) 3851 #define MPI26_PCIELINK3_EVTCODE_LTSSM_TXL0S_STATE (0x0C) 3852 #define MPI26_PCIELINK3_EVTCODE_LTSSM_L1_STATE (0x0D) 3853 #define MPI26_PCIELINK3_EVTCODE_LTSSM_DISABLED_STATE (0x0E) 3854 #define MPI26_PCIELINK3_EVTCODE_LTSSM_HOT_RESET_STATE (0x0F) 3855 #define MPI26_PCIELINK3_EVTCODE_SYSTEM_ERROR (0x10) 3856 #define MPI26_PCIELINK3_EVTCODE_DECODE_ERROR (0x11) 3857 #define MPI26_PCIELINK3_EVTCODE_DISPARITY_ERROR (0x12) 3858 3859 /* values for the CounterType field */ 3860 #define MPI26_PCIELINK3_COUNTER_TYPE_WRAPPING (0x00) 3861 #define MPI26_PCIELINK3_COUNTER_TYPE_SATURATING (0x01) 3862 #define MPI26_PCIELINK3_COUNTER_TYPE_PEAK_VALUE (0x02) 3863 3864 /* values for the TimeUnits field */ 3865 #define MPI26_PCIELINK3_TM_UNITS_10_MICROSECONDS (0x00) 3866 #define MPI26_PCIELINK3_TM_UNITS_100_MICROSECONDS (0x01) 3867 #define MPI26_PCIELINK3_TM_UNITS_1_MILLISECOND (0x02) 3868 #define MPI26_PCIELINK3_TM_UNITS_10_MILLISECONDS (0x03) 3869 3870 /* values for the ThresholdFlags field */ 3871 #define MPI26_PCIELINK3_TFLAGS_EVENT_NOTIFY (0x0001) 3872 3873 /* 3874 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to 3875 * one and check the value returned for NumLinkEvents at runtime. 3876 */ 3877 #ifndef MPI26_PCIELINK3_LINK_EVENT_MAX 3878 #define MPI26_PCIELINK3_LINK_EVENT_MAX (1) 3879 #endif 3880 3881 typedef struct _MPI26_CONFIG_PAGE_PCIELINK_3 3882 { 3883 MPI2_CONFIG_EXTENDED_PAGE_HEADER Header; /* 0x00 */ 3884 U8 Link; /* 0x08 */ 3885 U8 Reserved1; /* 0x09 */ 3886 U16 Reserved2; /* 0x0A */ 3887 U8 NumLinkEvents; /* 0x0C */ 3888 U8 Reserved3; /* 0x0D */ 3889 U16 Reserved4; /* 0x0E */ 3890 MPI26_PCIELINK3_LINK_EVENT_CONFIG LinkEventConfig[MPI26_PCIELINK3_LINK_EVENT_MAX]; /* 0x10 */ 3891 } MPI26_CONFIG_PAGE_PCIELINK_3, MPI2_POINTER PTR_MPI26_CONFIG_PAGE_PCIELINK_3, 3892 Mpi26PcieLinkPage3_t, MPI2_POINTER pMpi26PcieLinkPage3_t; 3893 3894 #define MPI26_PCIELINK3_PAGEVERSION (0x00) 3895 3896 3897 #endif 3898 3899