1 /*- 2 * Copyright (c) 2012-2015 LSI Corp. 3 * Copyright (c) 2013-2016 Avago Technologies 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * Copyright (c) 2000-2015 LSI Corporation. 37 * Copyright (c) 2013-2016 Avago Technologies 38 * All rights reserved. 39 * 40 * 41 * Name: mpi2.h 42 * Title: MPI Message independent structures and definitions 43 * including System Interface Register Set and 44 * scatter/gather formats. 45 * Creation Date: June 21, 2006 46 * 47 * mpi2.h Version: 02.00.46 48 * 49 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 50 * prefix are for use only on MPI v2.5 products, and must not be used 51 * with MPI v2.0 products. Unless otherwise noted, names beginning with 52 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 53 * 54 * Version History 55 * --------------- 56 * 57 * Date Version Description 58 * -------- -------- ------------------------------------------------------ 59 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 60 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. 61 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. 62 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. 63 * Moved ReplyPostHostIndex register to offset 0x6C of the 64 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for 65 * MPI2_REPLY_POST_HOST_INDEX_OFFSET. 66 * Added union of request descriptors. 67 * Added union of reply descriptors. 68 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. 69 * Added define for MPI2_VERSION_02_00. 70 * Fixed the size of the FunctionDependent5 field in the 71 * MPI2_DEFAULT_REPLY structure. 72 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. 73 * Removed the MPI-defined Fault Codes and extended the 74 * product specific codes up to 0xEFFF. 75 * Added a sixth key value for the WriteSequence register 76 * and changed the flush value to 0x0. 77 * Added message function codes for Diagnostic Buffer Post 78 * and Diagnsotic Release. 79 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED 80 * Moved MPI2_VERSION_UNION from mpi2_ioc.h. 81 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. 82 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. 83 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. 84 * Added #defines for marking a reply descriptor as unused. 85 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. 86 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. 87 * Moved LUN field defines from mpi2_init.h. 88 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. 89 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT. 90 * In all request and reply descriptors, replaced VF_ID 91 * field with MSIxIndex field. 92 * Removed DevHandle field from 93 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 94 * bytes reserved. 95 * Added RAID Accelerator functionality. 96 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT. 97 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT. 98 * Added MSI-x index mask and shift for Reply Post Host 99 * Index register. 100 * Added function code for Host Based Discovery Action. 101 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT. 102 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL. 103 * Added defines for product-specific range of message 104 * function codes, 0xF0 to 0xFF. 105 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT. 106 * Added alternative defines for the SGE Direction bit. 107 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT. 108 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT. 109 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define. 110 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT. 111 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE. 112 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT. 113 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT. 114 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT. 115 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT. 116 * Incorporating additions for MPI v2.5. 117 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT. 118 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT. 119 * Added Hard Reset delay timings. 120 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT. 121 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT. 122 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT. 123 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT. 124 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET. 125 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT. 126 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT. 127 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT. 128 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT. 129 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT. 130 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT. 131 * 11-18-14 02.00.36 Updated copyright information. 132 * Bumped MPI2_HEADER_VERSION_UNIT. 133 * 03-16-15 02.00.37 Updated for MPI v2.6. 134 * Bumped MPI2_HEADER_VERSION_UNIT. 135 * Added Scratchpad registers and 136 * AtomicRequestDescriptorPost register to 137 * MPI2_SYSTEM_INTERFACE_REGS. 138 * Added MPI2_DIAG_SBR_RELOAD. 139 * Added MPI2_IOCSTATUS_INSUFFICIENT_POWER. 140 * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT. 141 * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT 142 * 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT. 143 * Added V7 HostDiagnostic register defines 144 * 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT 145 * 01-01-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT 146 * 04-05-16 02.00.43 Modified MPI26_DIAG_BOOT_DEVICE_SELECT defines 147 * to be unique within first 32 characters. 148 * Removed AHCI support. 149 * Removed SOP support. 150 * Bumped MPI2_HEADER_VERSION_UNIT. 151 * 04-10-16 02.00.44 Bumped MPI2_HEADER_VERSION_UNIT. 152 * 07-06-16 02.00.45 Bumped MPI2_HEADER_VERSION_UNIT. 153 * 09-02-16 02.00.46 Bumped MPI2_HEADER_VERSION_UNIT. 154 * -------------------------------------------------------------------------- 155 */ 156 157 #ifndef MPI2_H 158 #define MPI2_H 159 160 161 /***************************************************************************** 162 * 163 * MPI Version Definitions 164 * 165 *****************************************************************************/ 166 167 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 168 #define MPI2_VERSION_MAJOR_SHIFT (8) 169 #define MPI2_VERSION_MINOR_MASK (0x00FF) 170 #define MPI2_VERSION_MINOR_SHIFT (0) 171 172 /* major version for all MPI v2.x */ 173 #define MPI2_VERSION_MAJOR (0x02) 174 175 /* minor version for MPI v2.0 compatible products */ 176 #define MPI2_VERSION_MINOR (0x00) 177 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 178 MPI2_VERSION_MINOR) 179 #define MPI2_VERSION_02_00 (0x0200) 180 181 182 /* minor version for MPI v2.5 compatible products */ 183 #define MPI25_VERSION_MINOR (0x05) 184 #define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 185 MPI25_VERSION_MINOR) 186 #define MPI2_VERSION_02_05 (0x0205) 187 188 189 /* minor version for MPI v2.6 compatible products */ 190 #define MPI26_VERSION_MINOR (0x06) 191 #define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 192 MPI26_VERSION_MINOR) 193 #define MPI2_VERSION_02_06 (0x0206) 194 195 196 /* Unit and Dev versioning for this MPI header set */ 197 #define MPI2_HEADER_VERSION_UNIT (0x2E) 198 #define MPI2_HEADER_VERSION_DEV (0x00) 199 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 200 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 201 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 202 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 203 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 204 205 206 /***************************************************************************** 207 * 208 * IOC State Definitions 209 * 210 *****************************************************************************/ 211 212 #define MPI2_IOC_STATE_RESET (0x00000000) 213 #define MPI2_IOC_STATE_READY (0x10000000) 214 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000) 215 #define MPI2_IOC_STATE_FAULT (0x40000000) 216 217 #define MPI2_IOC_STATE_MASK (0xF0000000) 218 #define MPI2_IOC_STATE_SHIFT (28) 219 220 /* Fault state range for prodcut specific codes */ 221 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) 222 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) 223 224 225 /***************************************************************************** 226 * 227 * System Interface Register Definitions 228 * 229 *****************************************************************************/ 230 231 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS 232 { 233 U32 Doorbell; /* 0x00 */ 234 U32 WriteSequence; /* 0x04 */ 235 U32 HostDiagnostic; /* 0x08 */ 236 U32 Reserved1; /* 0x0C */ 237 U32 DiagRWData; /* 0x10 */ 238 U32 DiagRWAddressLow; /* 0x14 */ 239 U32 DiagRWAddressHigh; /* 0x18 */ 240 U32 Reserved2[5]; /* 0x1C */ 241 U32 HostInterruptStatus; /* 0x30 */ 242 U32 HostInterruptMask; /* 0x34 */ 243 U32 DCRData; /* 0x38 */ 244 U32 DCRAddress; /* 0x3C */ 245 U32 Reserved3[2]; /* 0x40 */ 246 U32 ReplyFreeHostIndex; /* 0x48 */ 247 U32 Reserved4[8]; /* 0x4C */ 248 U32 ReplyPostHostIndex; /* 0x6C */ 249 U32 Reserved5; /* 0x70 */ 250 U32 HCBSize; /* 0x74 */ 251 U32 HCBAddressLow; /* 0x78 */ 252 U32 HCBAddressHigh; /* 0x7C */ 253 U32 Reserved6[12]; /* 0x80 */ 254 U32 Scratchpad[4]; /* 0xB0 */ 255 U32 RequestDescriptorPostLow; /* 0xC0 */ 256 U32 RequestDescriptorPostHigh; /* 0xC4 */ 257 U32 AtomicRequestDescriptorPost;/* 0xC8 */ /* MPI v2.6 and later; reserved in earlier versions */ 258 U32 Reserved7[13]; /* 0xCC */ 259 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS, 260 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t; 261 262 /* 263 * Defines for working with the Doorbell register. 264 */ 265 #define MPI2_DOORBELL_OFFSET (0x00000000) 266 267 /* IOC --> System values */ 268 #define MPI2_DOORBELL_USED (0x08000000) 269 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) 270 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24) 271 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) 272 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) 273 274 /* System --> IOC values */ 275 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) 276 #define MPI2_DOORBELL_FUNCTION_SHIFT (24) 277 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 278 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) 279 280 281 /* 282 * Defines for the WriteSequence register 283 */ 284 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 285 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) 286 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 287 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 288 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 289 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 290 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 291 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 292 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 293 294 /* 295 * Defines for the HostDiagnostic register 296 */ 297 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 298 299 #define MPI2_DIAG_SBR_RELOAD (0x00002000) 300 301 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 302 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) 303 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) 304 305 /* Defines for V7A/V7R HostDiagnostic Register */ 306 #define MPI26_DIAG_BOOT_DEVICE_SEL_64FLASH (0x00000000) 307 #define MPI26_DIAG_BOOT_DEVICE_SEL_64HCDW (0x00000800) 308 #define MPI26_DIAG_BOOT_DEVICE_SEL_32FLASH (0x00001000) 309 #define MPI26_DIAG_BOOT_DEVICE_SEL_32HCDW (0x00001800) 310 311 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 312 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) 313 #define MPI2_DIAG_HCB_MODE (0x00000100) 314 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) 315 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) 316 #define MPI2_DIAG_RESET_HISTORY (0x00000020) 317 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) 318 #define MPI2_DIAG_RESET_ADAPTER (0x00000004) 319 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) 320 321 /* 322 * Offsets for DiagRWData and address 323 */ 324 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) 325 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) 326 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) 327 328 /* 329 * Defines for the HostInterruptStatus register 330 */ 331 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 332 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) 333 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS 334 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) 335 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) 336 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) 337 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS 338 339 /* 340 * Defines for the HostInterruptMask register 341 */ 342 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 343 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000) 344 #define MPI2_HIM_REPLY_INT_MASK (0x00000008) 345 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK 346 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) 347 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK 348 349 /* 350 * Offsets for DCRData and address 351 */ 352 #define MPI2_DCR_DATA_OFFSET (0x00000038) 353 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) 354 355 /* 356 * Offset for the Reply Free Queue 357 */ 358 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) 359 360 /* 361 * Defines for the Reply Descriptor Post Queue 362 */ 363 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 364 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) 365 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) 366 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24) 367 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /* MPI v2.5 only */ 368 369 370 /* 371 * Defines for the HCBSize and address 372 */ 373 #define MPI2_HCB_SIZE_OFFSET (0x00000074) 374 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) 375 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) 376 377 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) 378 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) 379 380 /* 381 * Offsets for the Scratchpad registers 382 */ 383 #define MPI26_SCRATCHPAD0_OFFSET (0x000000B0) 384 #define MPI26_SCRATCHPAD1_OFFSET (0x000000B4) 385 #define MPI26_SCRATCHPAD2_OFFSET (0x000000B8) 386 #define MPI26_SCRATCHPAD3_OFFSET (0x000000BC) 387 388 /* 389 * Offsets for the Request Descriptor Post Queue 390 */ 391 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) 392 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) 393 #define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8) 394 395 396 /* Hard Reset delay timings */ 397 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000) 398 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000) 399 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000) 400 401 /***************************************************************************** 402 * 403 * Message Descriptors 404 * 405 *****************************************************************************/ 406 407 /* Request Descriptors */ 408 409 /* Default Request Descriptor */ 410 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR 411 { 412 U8 RequestFlags; /* 0x00 */ 413 U8 MSIxIndex; /* 0x01 */ 414 U16 SMID; /* 0x02 */ 415 U16 LMID; /* 0x04 */ 416 U16 DescriptorTypeDependent; /* 0x06 */ 417 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 418 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 419 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 420 421 /* defines for the RequestFlags field */ 422 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E) 423 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1) /* use carefully; values below are pre-shifted left */ 424 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 425 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 426 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 427 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 428 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 429 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C) 430 #define MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED (0x10) 431 432 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 433 434 435 /* High Priority Request Descriptor */ 436 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR 437 { 438 U8 RequestFlags; /* 0x00 */ 439 U8 MSIxIndex; /* 0x01 */ 440 U16 SMID; /* 0x02 */ 441 U16 LMID; /* 0x04 */ 442 U16 Reserved1; /* 0x06 */ 443 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 444 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 445 Mpi2HighPriorityRequestDescriptor_t, 446 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 447 448 449 /* SCSI IO Request Descriptor */ 450 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR 451 { 452 U8 RequestFlags; /* 0x00 */ 453 U8 MSIxIndex; /* 0x01 */ 454 U16 SMID; /* 0x02 */ 455 U16 LMID; /* 0x04 */ 456 U16 DevHandle; /* 0x06 */ 457 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 458 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 459 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 460 461 462 /* SCSI Target Request Descriptor */ 463 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR 464 { 465 U8 RequestFlags; /* 0x00 */ 466 U8 MSIxIndex; /* 0x01 */ 467 U16 SMID; /* 0x02 */ 468 U16 LMID; /* 0x04 */ 469 U16 IoIndex; /* 0x06 */ 470 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 471 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 472 Mpi2SCSITargetRequestDescriptor_t, 473 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 474 475 476 /* RAID Accelerator Request Descriptor */ 477 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR 478 { 479 U8 RequestFlags; /* 0x00 */ 480 U8 MSIxIndex; /* 0x01 */ 481 U16 SMID; /* 0x02 */ 482 U16 LMID; /* 0x04 */ 483 U16 Reserved; /* 0x06 */ 484 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 485 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 486 Mpi2RAIDAcceleratorRequestDescriptor_t, 487 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 488 489 490 /* Fast Path SCSI IO Request Descriptor */ 491 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR 492 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 493 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 494 Mpi25FastPathSCSIIORequestDescriptor_t, 495 MPI2_POINTER pMpi25FastPathSCSIIORequestDescriptor_t; 496 497 498 /* PCIe Encapsulated Request Descriptor */ 499 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR 500 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR, 501 MPI2_POINTER PTR_MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR, 502 Mpi26PCIeEncapsulatedRequestDescriptor_t, 503 MPI2_POINTER pMpi26PCIeEncapsulatedRequestDescriptor_t; 504 505 506 /* union of Request Descriptors */ 507 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION 508 { 509 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 510 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 511 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 512 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 513 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 514 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO; 515 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR PCIeEncapsulated; 516 U64 Words; 517 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION, 518 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t; 519 520 521 /* Atomic Request Descriptors */ 522 523 /* 524 * All Atomic Request Descriptors have the same format, so the following 525 * structure is used for all Atomic Request Descriptors: 526 * Atomic Default Request Descriptor 527 * Atomic High Priority Request Descriptor 528 * Atomic SCSI IO Request Descriptor 529 * Atomic SCSI Target Request Descriptor 530 * Atomic RAID Accelerator Request Descriptor 531 * Atomic Fast Path SCSI IO Request Descriptor 532 * Atomic PCIe Encapsulated Request Descriptor 533 */ 534 535 /* Atomic Request Descriptor */ 536 typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR 537 { 538 U8 RequestFlags; /* 0x00 */ 539 U8 MSIxIndex; /* 0x01 */ 540 U16 SMID; /* 0x02 */ 541 } MPI26_ATOMIC_REQUEST_DESCRIPTOR, 542 MPI2_POINTER PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR, 543 Mpi26AtomicRequestDescriptor_t, MPI2_POINTER pMpi26AtomicRequestDescriptor_t; 544 545 /* for the RequestFlags field, use the same defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR */ 546 547 548 /* Reply Descriptors */ 549 550 /* Default Reply Descriptor */ 551 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR 552 { 553 U8 ReplyFlags; /* 0x00 */ 554 U8 MSIxIndex; /* 0x01 */ 555 U16 DescriptorTypeDependent1; /* 0x02 */ 556 U32 DescriptorTypeDependent2; /* 0x04 */ 557 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 558 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 559 560 /* defines for the ReplyFlags field */ 561 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 562 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 563 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 564 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 565 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 566 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 567 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06) 568 #define MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS (0x08) 569 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 570 571 /* values for marking a reply descriptor as unused */ 572 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 573 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 574 575 /* Address Reply Descriptor */ 576 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR 577 { 578 U8 ReplyFlags; /* 0x00 */ 579 U8 MSIxIndex; /* 0x01 */ 580 U16 SMID; /* 0x02 */ 581 U32 ReplyFrameAddress; /* 0x04 */ 582 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 583 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 584 585 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) 586 587 588 /* SCSI IO Success Reply Descriptor */ 589 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 590 { 591 U8 ReplyFlags; /* 0x00 */ 592 U8 MSIxIndex; /* 0x01 */ 593 U16 SMID; /* 0x02 */ 594 U16 TaskTag; /* 0x04 */ 595 U16 Reserved1; /* 0x06 */ 596 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 597 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 598 Mpi2SCSIIOSuccessReplyDescriptor_t, 599 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 600 601 602 /* TargetAssist Success Reply Descriptor */ 603 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR 604 { 605 U8 ReplyFlags; /* 0x00 */ 606 U8 MSIxIndex; /* 0x01 */ 607 U16 SMID; /* 0x02 */ 608 U8 SequenceNumber; /* 0x04 */ 609 U8 Reserved1; /* 0x05 */ 610 U16 IoIndex; /* 0x06 */ 611 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 612 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 613 Mpi2TargetAssistSuccessReplyDescriptor_t, 614 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 615 616 617 /* Target Command Buffer Reply Descriptor */ 618 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 619 { 620 U8 ReplyFlags; /* 0x00 */ 621 U8 MSIxIndex; /* 0x01 */ 622 U8 VP_ID; /* 0x02 */ 623 U8 Flags; /* 0x03 */ 624 U16 InitiatorDevHandle; /* 0x04 */ 625 U16 IoIndex; /* 0x06 */ 626 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 627 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 628 Mpi2TargetCommandBufferReplyDescriptor_t, 629 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 630 631 /* defines for Flags field */ 632 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) 633 634 635 /* RAID Accelerator Success Reply Descriptor */ 636 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 637 { 638 U8 ReplyFlags; /* 0x00 */ 639 U8 MSIxIndex; /* 0x01 */ 640 U16 SMID; /* 0x02 */ 641 U32 Reserved; /* 0x04 */ 642 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 643 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 644 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 645 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 646 647 648 /* Fast Path SCSI IO Success Reply Descriptor */ 649 typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 650 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 651 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 652 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t, 653 MPI2_POINTER pMpi25FastPathSCSIIOSuccessReplyDescriptor_t; 654 655 656 /* PCIe Encapsulated Success Reply Descriptor */ 657 typedef MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 658 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR, 659 MPI2_POINTER PTR_MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR, 660 Mpi26PCIeEncapsulatedSuccessReplyDescriptor_t, 661 MPI2_POINTER pMpi26PCIeEncapsulatedSuccessReplyDescriptor_t; 662 663 664 /* union of Reply Descriptors */ 665 typedef union _MPI2_REPLY_DESCRIPTORS_UNION 666 { 667 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 668 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 669 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 670 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 671 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 672 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 673 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess; 674 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR PCIeEncapsulatedSuccess; 675 U64 Words; 676 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 677 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 678 679 680 681 /***************************************************************************** 682 * 683 * Message Functions 684 * 685 *****************************************************************************/ 686 687 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 688 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 689 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 690 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 691 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 692 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 693 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 694 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 695 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 696 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 697 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 698 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 699 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 700 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 701 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 702 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 703 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 704 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 705 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 706 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ /* for MPI v2.5 and earlier */ 707 #define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B) /* IO Unit Control */ /* for MPI v2.6 and later */ 708 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 709 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 710 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 711 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 712 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 713 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 714 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 715 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 716 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) /* Send Host Message */ 717 #define MPI2_FUNCTION_NVME_ENCAPSULATED (0x33) /* NVMe Encapsulated (MPI v2.6) */ 718 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 719 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 720 721 722 723 /* Doorbell functions */ 724 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 725 #define MPI2_FUNCTION_HANDSHAKE (0x42) 726 727 728 /***************************************************************************** 729 * 730 * IOC Status Values 731 * 732 *****************************************************************************/ 733 734 /* mask for IOCStatus status value */ 735 #define MPI2_IOCSTATUS_MASK (0x7FFF) 736 737 /**************************************************************************** 738 * Common IOCStatus values for all replies 739 ****************************************************************************/ 740 741 #define MPI2_IOCSTATUS_SUCCESS (0x0000) 742 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) 743 #define MPI2_IOCSTATUS_BUSY (0x0002) 744 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003) 745 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) 746 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005) 747 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 748 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 749 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 750 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 751 #define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A) /* MPI v2.6 and later */ 752 753 /**************************************************************************** 754 * Config IOCStatus values 755 ****************************************************************************/ 756 757 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 758 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 759 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 760 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 761 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 762 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 763 764 /**************************************************************************** 765 * SCSI IO Reply 766 ****************************************************************************/ 767 768 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 769 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 770 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 771 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 772 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 773 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 774 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 775 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 776 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 777 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 778 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 779 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 780 781 /**************************************************************************** 782 * For use by SCSI Initiator and SCSI Target end-to-end data protection 783 ****************************************************************************/ 784 785 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 786 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 787 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 788 789 /**************************************************************************** 790 * SCSI Target values 791 ****************************************************************************/ 792 793 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 794 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) 795 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 796 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 797 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 798 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 799 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 800 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 801 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 802 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 803 804 /**************************************************************************** 805 * Serial Attached SCSI values 806 ****************************************************************************/ 807 808 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 809 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 810 811 /**************************************************************************** 812 * Diagnostic Buffer Post / Diagnostic Release values 813 ****************************************************************************/ 814 815 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 816 817 /**************************************************************************** 818 * RAID Accelerator values 819 ****************************************************************************/ 820 821 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) 822 823 /**************************************************************************** 824 * IOCStatus flag to indicate that log info is available 825 ****************************************************************************/ 826 827 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 828 829 /**************************************************************************** 830 * IOCLogInfo Types 831 ****************************************************************************/ 832 833 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) 834 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28) 835 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0) 836 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) 837 #define MPI2_IOCLOGINFO_TYPE_FC (0x2) 838 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3) 839 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) 840 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 841 842 843 /***************************************************************************** 844 * 845 * Standard Message Structures 846 * 847 *****************************************************************************/ 848 849 /**************************************************************************** 850 * Request Message Header for all request messages 851 ****************************************************************************/ 852 853 typedef struct _MPI2_REQUEST_HEADER 854 { 855 U16 FunctionDependent1; /* 0x00 */ 856 U8 ChainOffset; /* 0x02 */ 857 U8 Function; /* 0x03 */ 858 U16 FunctionDependent2; /* 0x04 */ 859 U8 FunctionDependent3; /* 0x06 */ 860 U8 MsgFlags; /* 0x07 */ 861 U8 VP_ID; /* 0x08 */ 862 U8 VF_ID; /* 0x09 */ 863 U16 Reserved1; /* 0x0A */ 864 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER, 865 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t; 866 867 868 /**************************************************************************** 869 * Default Reply 870 ****************************************************************************/ 871 872 typedef struct _MPI2_DEFAULT_REPLY 873 { 874 U16 FunctionDependent1; /* 0x00 */ 875 U8 MsgLength; /* 0x02 */ 876 U8 Function; /* 0x03 */ 877 U16 FunctionDependent2; /* 0x04 */ 878 U8 FunctionDependent3; /* 0x06 */ 879 U8 MsgFlags; /* 0x07 */ 880 U8 VP_ID; /* 0x08 */ 881 U8 VF_ID; /* 0x09 */ 882 U16 Reserved1; /* 0x0A */ 883 U16 FunctionDependent5; /* 0x0C */ 884 U16 IOCStatus; /* 0x0E */ 885 U32 IOCLogInfo; /* 0x10 */ 886 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY, 887 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t; 888 889 890 /* common version structure/union used in messages and configuration pages */ 891 892 typedef struct _MPI2_VERSION_STRUCT 893 { 894 U8 Dev; /* 0x00 */ 895 U8 Unit; /* 0x01 */ 896 U8 Minor; /* 0x02 */ 897 U8 Major; /* 0x03 */ 898 } MPI2_VERSION_STRUCT; 899 900 typedef union _MPI2_VERSION_UNION 901 { 902 MPI2_VERSION_STRUCT Struct; 903 U32 Word; 904 } MPI2_VERSION_UNION; 905 906 907 /* LUN field defines, common to many structures */ 908 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 909 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 910 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 911 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 912 #define MPI2_LUN_LEVEL_1_WORD (0xFF00) 913 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) 914 915 916 /***************************************************************************** 917 * 918 * Fusion-MPT MPI Scatter Gather Elements 919 * 920 *****************************************************************************/ 921 922 /**************************************************************************** 923 * MPI Simple Element structures 924 ****************************************************************************/ 925 926 typedef struct _MPI2_SGE_SIMPLE32 927 { 928 U32 FlagsLength; 929 U32 Address; 930 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32, 931 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t; 932 933 typedef struct _MPI2_SGE_SIMPLE64 934 { 935 U32 FlagsLength; 936 U64 Address; 937 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64, 938 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t; 939 940 typedef struct _MPI2_SGE_SIMPLE_UNION 941 { 942 U32 FlagsLength; 943 union 944 { 945 U32 Address32; 946 U64 Address64; 947 } u; 948 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 949 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 950 951 952 /**************************************************************************** 953 * MPI Chain Element structures - for MPI v2.0 products only 954 ****************************************************************************/ 955 956 typedef struct _MPI2_SGE_CHAIN32 957 { 958 U16 Length; 959 U8 NextChainOffset; 960 U8 Flags; 961 U32 Address; 962 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32, 963 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t; 964 965 typedef struct _MPI2_SGE_CHAIN64 966 { 967 U16 Length; 968 U8 NextChainOffset; 969 U8 Flags; 970 U64 Address; 971 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64, 972 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t; 973 974 typedef struct _MPI2_SGE_CHAIN_UNION 975 { 976 U16 Length; 977 U8 NextChainOffset; 978 U8 Flags; 979 union 980 { 981 U32 Address32; 982 U64 Address64; 983 } u; 984 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 985 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 986 987 988 /**************************************************************************** 989 * MPI Transaction Context Element structures - for MPI v2.0 products only 990 ****************************************************************************/ 991 992 typedef struct _MPI2_SGE_TRANSACTION32 993 { 994 U8 Reserved; 995 U8 ContextSize; 996 U8 DetailsLength; 997 U8 Flags; 998 U32 TransactionContext[1]; 999 U32 TransactionDetails[1]; 1000 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32, 1001 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t; 1002 1003 typedef struct _MPI2_SGE_TRANSACTION64 1004 { 1005 U8 Reserved; 1006 U8 ContextSize; 1007 U8 DetailsLength; 1008 U8 Flags; 1009 U32 TransactionContext[2]; 1010 U32 TransactionDetails[1]; 1011 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64, 1012 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t; 1013 1014 typedef struct _MPI2_SGE_TRANSACTION96 1015 { 1016 U8 Reserved; 1017 U8 ContextSize; 1018 U8 DetailsLength; 1019 U8 Flags; 1020 U32 TransactionContext[3]; 1021 U32 TransactionDetails[1]; 1022 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96, 1023 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t; 1024 1025 typedef struct _MPI2_SGE_TRANSACTION128 1026 { 1027 U8 Reserved; 1028 U8 ContextSize; 1029 U8 DetailsLength; 1030 U8 Flags; 1031 U32 TransactionContext[4]; 1032 U32 TransactionDetails[1]; 1033 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128, 1034 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128; 1035 1036 typedef struct _MPI2_SGE_TRANSACTION_UNION 1037 { 1038 U8 Reserved; 1039 U8 ContextSize; 1040 U8 DetailsLength; 1041 U8 Flags; 1042 union 1043 { 1044 U32 TransactionContext32[1]; 1045 U32 TransactionContext64[2]; 1046 U32 TransactionContext96[3]; 1047 U32 TransactionContext128[4]; 1048 } u; 1049 U32 TransactionDetails[1]; 1050 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION, 1051 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t; 1052 1053 1054 /**************************************************************************** 1055 * MPI SGE union for IO SGL's - for MPI v2.0 products only 1056 ****************************************************************************/ 1057 1058 typedef struct _MPI2_MPI_SGE_IO_UNION 1059 { 1060 union 1061 { 1062 MPI2_SGE_SIMPLE_UNION Simple; 1063 MPI2_SGE_CHAIN_UNION Chain; 1064 } u; 1065 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION, 1066 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t; 1067 1068 1069 /**************************************************************************** 1070 * MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only 1071 ****************************************************************************/ 1072 1073 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION 1074 { 1075 union 1076 { 1077 MPI2_SGE_SIMPLE_UNION Simple; 1078 MPI2_SGE_TRANSACTION_UNION Transaction; 1079 } u; 1080 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION, 1081 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t; 1082 1083 1084 /**************************************************************************** 1085 * All MPI SGE types union 1086 ****************************************************************************/ 1087 1088 typedef struct _MPI2_MPI_SGE_UNION 1089 { 1090 union 1091 { 1092 MPI2_SGE_SIMPLE_UNION Simple; 1093 MPI2_SGE_CHAIN_UNION Chain; 1094 MPI2_SGE_TRANSACTION_UNION Transaction; 1095 } u; 1096 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION, 1097 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t; 1098 1099 1100 /**************************************************************************** 1101 * MPI SGE field definition and masks 1102 ****************************************************************************/ 1103 1104 /* Flags field bit definitions */ 1105 1106 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) 1107 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) 1108 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 1109 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) 1110 #define MPI2_SGE_FLAGS_DIRECTION (0x04) 1111 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) 1112 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01) 1113 1114 #define MPI2_SGE_FLAGS_SHIFT (24) 1115 1116 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) 1117 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 1118 1119 /* Element Type */ 1120 1121 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) /* for MPI v2.0 products only */ 1122 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 1123 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) /* for MPI v2.0 products only */ 1124 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) 1125 1126 /* Address location */ 1127 1128 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 1129 1130 /* Direction */ 1131 1132 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) 1133 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) 1134 1135 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST) 1136 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC) 1137 1138 /* Address Size */ 1139 1140 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1141 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1142 1143 /* Context Size */ 1144 1145 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) 1146 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) 1147 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) 1148 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) 1149 1150 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 1151 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) 1152 1153 /**************************************************************************** 1154 * MPI SGE operation Macros 1155 ****************************************************************************/ 1156 1157 /* SIMPLE FlagsLength manipulations... */ 1158 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) 1159 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT) 1160 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) 1161 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) 1162 1163 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l)) 1164 1165 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) 1166 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) 1167 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l) 1168 1169 /* CAUTION - The following are READ-MODIFY-WRITE! */ 1170 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f) 1171 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l) 1172 1173 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT) 1174 1175 1176 /***************************************************************************** 1177 * 1178 * Fusion-MPT IEEE Scatter Gather Elements 1179 * 1180 *****************************************************************************/ 1181 1182 /**************************************************************************** 1183 * IEEE Simple Element structures 1184 ****************************************************************************/ 1185 1186 /* MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */ 1187 typedef struct _MPI2_IEEE_SGE_SIMPLE32 1188 { 1189 U32 Address; 1190 U32 FlagsLength; 1191 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 1192 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 1193 1194 typedef struct _MPI2_IEEE_SGE_SIMPLE64 1195 { 1196 U64 Address; 1197 U32 Length; 1198 U16 Reserved1; 1199 U8 Reserved2; 1200 U8 Flags; 1201 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 1202 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 1203 1204 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION 1205 { 1206 MPI2_IEEE_SGE_SIMPLE32 Simple32; 1207 MPI2_IEEE_SGE_SIMPLE64 Simple64; 1208 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 1209 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 1210 1211 1212 /**************************************************************************** 1213 * IEEE Chain Element structures 1214 ****************************************************************************/ 1215 1216 /* MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */ 1217 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 1218 1219 /* MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */ 1220 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 1221 1222 typedef union _MPI2_IEEE_SGE_CHAIN_UNION 1223 { 1224 MPI2_IEEE_SGE_CHAIN32 Chain32; 1225 MPI2_IEEE_SGE_CHAIN64 Chain64; 1226 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 1227 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 1228 1229 /* MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */ 1230 typedef struct _MPI25_IEEE_SGE_CHAIN64 1231 { 1232 U64 Address; 1233 U32 Length; 1234 U16 Reserved1; 1235 U8 NextChainOffset; 1236 U8 Flags; 1237 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, 1238 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t; 1239 1240 1241 /**************************************************************************** 1242 * All IEEE SGE types union 1243 ****************************************************************************/ 1244 1245 /* MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */ 1246 typedef struct _MPI2_IEEE_SGE_UNION 1247 { 1248 union 1249 { 1250 MPI2_IEEE_SGE_SIMPLE_UNION Simple; 1251 MPI2_IEEE_SGE_CHAIN_UNION Chain; 1252 } u; 1253 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION, 1254 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t; 1255 1256 1257 /**************************************************************************** 1258 * IEEE SGE union for IO SGL's 1259 ****************************************************************************/ 1260 1261 typedef union _MPI25_SGE_IO_UNION 1262 { 1263 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple; 1264 MPI25_IEEE_SGE_CHAIN64 IeeeChain; 1265 } MPI25_SGE_IO_UNION, MPI2_POINTER PTR_MPI25_SGE_IO_UNION, 1266 Mpi25SGEIOUnion_t, MPI2_POINTER pMpi25SGEIOUnion_t; 1267 1268 1269 /**************************************************************************** 1270 * IEEE SGE field definitions and masks 1271 ****************************************************************************/ 1272 1273 /* Flags field bit definitions */ 1274 1275 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1276 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1277 1278 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1279 1280 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1281 1282 /* Element Type */ 1283 1284 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1285 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1286 1287 /* Next Segment Format */ 1288 1289 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C) 1290 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00) 1291 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08) 1292 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10) 1293 1294 /* Data Location Address Space */ 1295 1296 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1297 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5 and later, use in IEEE Simple or Chain element */ 1298 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* use in IEEE Simple Element only */ 1299 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1300 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5, use in IEEE Simple or Chain element */ 1301 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) /* use in MPI v2.0 IEEE Chain Element only */ 1302 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */ 1303 1304 #define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02) /* for MPI v2.6 only */ 1305 1306 /**************************************************************************** 1307 * IEEE SGE operation Macros 1308 ****************************************************************************/ 1309 1310 /* SIMPLE FlagsLength manipulations... */ 1311 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) 1312 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT) 1313 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) 1314 1315 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l)) 1316 1317 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) 1318 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) 1319 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l) 1320 1321 /* CAUTION - The following are READ-MODIFY-WRITE! */ 1322 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f) 1323 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l) 1324 1325 1326 1327 /***************************************************************************** 1328 * 1329 * Fusion-MPT MPI/IEEE Scatter Gather Unions 1330 * 1331 *****************************************************************************/ 1332 1333 typedef union _MPI2_SIMPLE_SGE_UNION 1334 { 1335 MPI2_SGE_SIMPLE_UNION MpiSimple; 1336 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1337 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION, 1338 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t; 1339 1340 1341 typedef union _MPI2_SGE_IO_UNION 1342 { 1343 MPI2_SGE_SIMPLE_UNION MpiSimple; 1344 MPI2_SGE_CHAIN_UNION MpiChain; 1345 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1346 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1347 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 1348 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 1349 1350 1351 /**************************************************************************** 1352 * 1353 * Values for SGLFlags field, used in many request messages with an SGL 1354 * 1355 ****************************************************************************/ 1356 1357 /* values for MPI SGL Data Location Address Space subfield */ 1358 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) 1359 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) 1360 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) 1361 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.5 and earlier */ 1362 #define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.6 */ 1363 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) /* only for MPI v2.5 and earlier */ 1364 /* values for SGL Type subfield */ 1365 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) 1366 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) 1367 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) /* MPI v2.0 products only */ 1368 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) 1369 1370 1371 #endif 1372 1373