1 /*- 2 * Copyright 2000-2020 Broadcom Inc. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. Neither the name of the author nor the names of any co-contributors 13 * may be used to endorse or promote products derived from this software 14 * without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD 29 */ 30 31 /* 32 * Copyright 2000-2020 Broadcom Inc. All rights reserved. 33 * 34 * 35 * Name: mpi2.h 36 * Title: MPI Message independent structures and definitions 37 * including System Interface Register Set and 38 * scatter/gather formats. 39 * Creation Date: June 21, 2006 40 * 41 * mpi2.h Version: 02.00.52 42 * 43 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 44 * prefix are for use only on MPI v2.5 products, and must not be used 45 * with MPI v2.0 products. Unless otherwise noted, names beginning with 46 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 47 * 48 * Version History 49 * --------------- 50 * 51 * Date Version Description 52 * -------- -------- ------------------------------------------------------ 53 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 54 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. 55 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. 56 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. 57 * Moved ReplyPostHostIndex register to offset 0x6C of the 58 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for 59 * MPI2_REPLY_POST_HOST_INDEX_OFFSET. 60 * Added union of request descriptors. 61 * Added union of reply descriptors. 62 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. 63 * Added define for MPI2_VERSION_02_00. 64 * Fixed the size of the FunctionDependent5 field in the 65 * MPI2_DEFAULT_REPLY structure. 66 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. 67 * Removed the MPI-defined Fault Codes and extended the 68 * product specific codes up to 0xEFFF. 69 * Added a sixth key value for the WriteSequence register 70 * and changed the flush value to 0x0. 71 * Added message function codes for Diagnostic Buffer Post 72 * and Diagnsotic Release. 73 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED 74 * Moved MPI2_VERSION_UNION from mpi2_ioc.h. 75 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. 76 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. 77 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. 78 * Added #defines for marking a reply descriptor as unused. 79 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. 80 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. 81 * Moved LUN field defines from mpi2_init.h. 82 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. 83 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT. 84 * In all request and reply descriptors, replaced VF_ID 85 * field with MSIxIndex field. 86 * Removed DevHandle field from 87 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 88 * bytes reserved. 89 * Added RAID Accelerator functionality. 90 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT. 91 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT. 92 * Added MSI-x index mask and shift for Reply Post Host 93 * Index register. 94 * Added function code for Host Based Discovery Action. 95 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT. 96 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL. 97 * Added defines for product-specific range of message 98 * function codes, 0xF0 to 0xFF. 99 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT. 100 * Added alternative defines for the SGE Direction bit. 101 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT. 102 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT. 103 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define. 104 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT. 105 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE. 106 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT. 107 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT. 108 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT. 109 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT. 110 * Incorporating additions for MPI v2.5. 111 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT. 112 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT. 113 * Added Hard Reset delay timings. 114 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT. 115 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT. 116 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT. 117 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT. 118 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET. 119 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT. 120 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT. 121 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT. 122 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT. 123 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT. 124 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT. 125 * 11-18-14 02.00.36 Updated copyright information. 126 * Bumped MPI2_HEADER_VERSION_UNIT. 127 * 03-16-15 02.00.37 Updated for MPI v2.6. 128 * Bumped MPI2_HEADER_VERSION_UNIT. 129 * Added Scratchpad registers and 130 * AtomicRequestDescriptorPost register to 131 * MPI2_SYSTEM_INTERFACE_REGS. 132 * Added MPI2_DIAG_SBR_RELOAD. 133 * Added MPI2_IOCSTATUS_INSUFFICIENT_POWER. 134 * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT. 135 * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT 136 * 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT. 137 * Added V7 HostDiagnostic register defines 138 * 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT 139 * 01-01-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT 140 * 04-05-16 02.00.43 Modified MPI26_DIAG_BOOT_DEVICE_SELECT defines 141 * to be unique within first 32 characters. 142 * Removed AHCI support. 143 * Removed SOP support. 144 * Bumped MPI2_HEADER_VERSION_UNIT. 145 * 04-10-16 02.00.44 Bumped MPI2_HEADER_VERSION_UNIT. 146 * 07-06-16 02.00.45 Bumped MPI2_HEADER_VERSION_UNIT. 147 * 09-02-16 02.00.46 Bumped MPI2_HEADER_VERSION_UNIT. 148 * 11-23-16 02.00.47 Bumped MPI2_HEADER_VERSION_UNIT. 149 * 02-03-17 02.00.48 Bumped MPI2_HEADER_VERSION_UNIT. 150 * 06-13-17 02.00.49 Bumped MPI2_HEADER_VERSION_UNIT. 151 * 09-29-17 02.00.50 Bumped MPI2_HEADER_VERSION_UNIT. 152 * 07-22-18 02.00.51 Added SECURE_BOOT define. 153 * Bumped MPI2_HEADER_VERSION_UNIT 154 * 08-15-18 02.00.52 Bumped MPI2_HEADER_VERSION_UNIT. 155 * -------------------------------------------------------------------------- 156 */ 157 158 #ifndef MPI2_H 159 #define MPI2_H 160 161 /***************************************************************************** 162 * 163 * MPI Version Definitions 164 * 165 *****************************************************************************/ 166 167 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 168 #define MPI2_VERSION_MAJOR_SHIFT (8) 169 #define MPI2_VERSION_MINOR_MASK (0x00FF) 170 #define MPI2_VERSION_MINOR_SHIFT (0) 171 172 /* major version for all MPI v2.x */ 173 #define MPI2_VERSION_MAJOR (0x02) 174 175 /* minor version for MPI v2.0 compatible products */ 176 #define MPI2_VERSION_MINOR (0x00) 177 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 178 MPI2_VERSION_MINOR) 179 #define MPI2_VERSION_02_00 (0x0200) 180 181 /* minor version for MPI v2.5 compatible products */ 182 #define MPI25_VERSION_MINOR (0x05) 183 #define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 184 MPI25_VERSION_MINOR) 185 #define MPI2_VERSION_02_05 (0x0205) 186 187 /* minor version for MPI v2.6 compatible products */ 188 #define MPI26_VERSION_MINOR (0x06) 189 #define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 190 MPI26_VERSION_MINOR) 191 #define MPI2_VERSION_02_06 (0x0206) 192 193 /* Unit and Dev versioning for this MPI header set */ 194 #define MPI2_HEADER_VERSION_UNIT (0x34) 195 #define MPI2_HEADER_VERSION_DEV (0x00) 196 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 197 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 198 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 199 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 200 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 201 202 /***************************************************************************** 203 * 204 * IOC State Definitions 205 * 206 *****************************************************************************/ 207 208 #define MPI2_IOC_STATE_RESET (0x00000000) 209 #define MPI2_IOC_STATE_READY (0x10000000) 210 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000) 211 #define MPI2_IOC_STATE_FAULT (0x40000000) 212 213 #define MPI2_IOC_STATE_MASK (0xF0000000) 214 #define MPI2_IOC_STATE_SHIFT (28) 215 216 /* Fault state range for prodcut specific codes */ 217 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) 218 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) 219 220 /***************************************************************************** 221 * 222 * System Interface Register Definitions 223 * 224 *****************************************************************************/ 225 226 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS 227 { 228 U32 Doorbell; /* 0x00 */ 229 U32 WriteSequence; /* 0x04 */ 230 U32 HostDiagnostic; /* 0x08 */ 231 U32 Reserved1; /* 0x0C */ 232 U32 DiagRWData; /* 0x10 */ 233 U32 DiagRWAddressLow; /* 0x14 */ 234 U32 DiagRWAddressHigh; /* 0x18 */ 235 U32 Reserved2[5]; /* 0x1C */ 236 U32 HostInterruptStatus; /* 0x30 */ 237 U32 HostInterruptMask; /* 0x34 */ 238 U32 DCRData; /* 0x38 */ 239 U32 DCRAddress; /* 0x3C */ 240 U32 Reserved3[2]; /* 0x40 */ 241 U32 ReplyFreeHostIndex; /* 0x48 */ 242 U32 Reserved4[8]; /* 0x4C */ 243 U32 ReplyPostHostIndex; /* 0x6C */ 244 U32 Reserved5; /* 0x70 */ 245 U32 HCBSize; /* 0x74 */ 246 U32 HCBAddressLow; /* 0x78 */ 247 U32 HCBAddressHigh; /* 0x7C */ 248 U32 Reserved6[12]; /* 0x80 */ 249 U32 Scratchpad[4]; /* 0xB0 */ 250 U32 RequestDescriptorPostLow; /* 0xC0 */ 251 U32 RequestDescriptorPostHigh; /* 0xC4 */ 252 U32 AtomicRequestDescriptorPost;/* 0xC8 */ /* MPI v2.6 and later; reserved in earlier versions */ 253 U32 Reserved7[13]; /* 0xCC */ 254 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS, 255 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t; 256 257 /* 258 * Defines for working with the Doorbell register. 259 */ 260 #define MPI2_DOORBELL_OFFSET (0x00000000) 261 262 /* IOC --> System values */ 263 #define MPI2_DOORBELL_USED (0x08000000) 264 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) 265 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24) 266 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) 267 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) 268 269 /* System --> IOC values */ 270 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) 271 #define MPI2_DOORBELL_FUNCTION_SHIFT (24) 272 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 273 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) 274 275 /* 276 * Defines for the WriteSequence register 277 */ 278 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 279 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) 280 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 281 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 282 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 283 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 284 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 285 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 286 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 287 288 /* 289 * Defines for the HostDiagnostic register 290 */ 291 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 292 293 #define MPI26_DIAG_SECURE_BOOT (0x80000000) 294 295 #define MPI2_DIAG_SBR_RELOAD (0x00002000) 296 297 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 298 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) 299 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) 300 301 /* Defines for V7A/V7R HostDiagnostic Register */ 302 #define MPI26_DIAG_BOOT_DEVICE_SEL_64FLASH (0x00000000) 303 #define MPI26_DIAG_BOOT_DEVICE_SEL_64HCDW (0x00000800) 304 #define MPI26_DIAG_BOOT_DEVICE_SEL_32FLASH (0x00001000) 305 #define MPI26_DIAG_BOOT_DEVICE_SEL_32HCDW (0x00001800) 306 307 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 308 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) 309 #define MPI2_DIAG_HCB_MODE (0x00000100) 310 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) 311 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) 312 #define MPI2_DIAG_RESET_HISTORY (0x00000020) 313 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) 314 #define MPI2_DIAG_RESET_ADAPTER (0x00000004) 315 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) 316 317 /* 318 * Offsets for DiagRWData and address 319 */ 320 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) 321 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) 322 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) 323 324 /* 325 * Defines for the HostInterruptStatus register 326 */ 327 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 328 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) 329 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS 330 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) 331 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) 332 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) 333 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS 334 335 /* 336 * Defines for the HostInterruptMask register 337 */ 338 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 339 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000) 340 #define MPI2_HIM_REPLY_INT_MASK (0x00000008) 341 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK 342 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) 343 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK 344 345 /* 346 * Offsets for DCRData and address 347 */ 348 #define MPI2_DCR_DATA_OFFSET (0x00000038) 349 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) 350 351 /* 352 * Offset for the Reply Free Queue 353 */ 354 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) 355 356 /* 357 * Defines for the Reply Descriptor Post Queue 358 */ 359 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 360 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) 361 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) 362 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24) 363 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /* MPI v2.5 only */ 364 365 /* 366 * Defines for the HCBSize and address 367 */ 368 #define MPI2_HCB_SIZE_OFFSET (0x00000074) 369 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) 370 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) 371 372 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) 373 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) 374 375 /* 376 * Offsets for the Scratchpad registers 377 */ 378 #define MPI26_SCRATCHPAD0_OFFSET (0x000000B0) 379 #define MPI26_SCRATCHPAD1_OFFSET (0x000000B4) 380 #define MPI26_SCRATCHPAD2_OFFSET (0x000000B8) 381 #define MPI26_SCRATCHPAD3_OFFSET (0x000000BC) 382 383 /* 384 * Offsets for the Request Descriptor Post Queue 385 */ 386 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) 387 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) 388 #define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8) 389 390 /* Hard Reset delay timings */ 391 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000) 392 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000) 393 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000) 394 395 /***************************************************************************** 396 * 397 * Message Descriptors 398 * 399 *****************************************************************************/ 400 401 /* Request Descriptors */ 402 403 /* Default Request Descriptor */ 404 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR 405 { 406 U8 RequestFlags; /* 0x00 */ 407 U8 MSIxIndex; /* 0x01 */ 408 U16 SMID; /* 0x02 */ 409 U16 LMID; /* 0x04 */ 410 U16 DescriptorTypeDependent; /* 0x06 */ 411 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 412 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 413 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 414 415 /* defines for the RequestFlags field */ 416 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E) 417 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1) /* use carefully; values below are pre-shifted left */ 418 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 419 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 420 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 421 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 422 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 423 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C) 424 #define MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED (0x10) 425 426 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 427 428 /* High Priority Request Descriptor */ 429 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR 430 { 431 U8 RequestFlags; /* 0x00 */ 432 U8 MSIxIndex; /* 0x01 */ 433 U16 SMID; /* 0x02 */ 434 U16 LMID; /* 0x04 */ 435 U16 Reserved1; /* 0x06 */ 436 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 437 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 438 Mpi2HighPriorityRequestDescriptor_t, 439 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 440 441 /* SCSI IO Request Descriptor */ 442 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR 443 { 444 U8 RequestFlags; /* 0x00 */ 445 U8 MSIxIndex; /* 0x01 */ 446 U16 SMID; /* 0x02 */ 447 U16 LMID; /* 0x04 */ 448 U16 DevHandle; /* 0x06 */ 449 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 450 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 451 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 452 453 /* SCSI Target Request Descriptor */ 454 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR 455 { 456 U8 RequestFlags; /* 0x00 */ 457 U8 MSIxIndex; /* 0x01 */ 458 U16 SMID; /* 0x02 */ 459 U16 LMID; /* 0x04 */ 460 U16 IoIndex; /* 0x06 */ 461 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 462 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 463 Mpi2SCSITargetRequestDescriptor_t, 464 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 465 466 /* RAID Accelerator Request Descriptor */ 467 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR 468 { 469 U8 RequestFlags; /* 0x00 */ 470 U8 MSIxIndex; /* 0x01 */ 471 U16 SMID; /* 0x02 */ 472 U16 LMID; /* 0x04 */ 473 U16 Reserved; /* 0x06 */ 474 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 475 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 476 Mpi2RAIDAcceleratorRequestDescriptor_t, 477 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 478 479 /* Fast Path SCSI IO Request Descriptor */ 480 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR 481 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 482 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 483 Mpi25FastPathSCSIIORequestDescriptor_t, 484 MPI2_POINTER pMpi25FastPathSCSIIORequestDescriptor_t; 485 486 /* PCIe Encapsulated Request Descriptor */ 487 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR 488 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR, 489 MPI2_POINTER PTR_MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR, 490 Mpi26PCIeEncapsulatedRequestDescriptor_t, 491 MPI2_POINTER pMpi26PCIeEncapsulatedRequestDescriptor_t; 492 493 /* union of Request Descriptors */ 494 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION 495 { 496 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 497 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 498 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 499 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 500 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 501 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO; 502 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR PCIeEncapsulated; 503 U64 Words; 504 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION, 505 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t; 506 507 /* Atomic Request Descriptors */ 508 509 /* 510 * All Atomic Request Descriptors have the same format, so the following 511 * structure is used for all Atomic Request Descriptors: 512 * Atomic Default Request Descriptor 513 * Atomic High Priority Request Descriptor 514 * Atomic SCSI IO Request Descriptor 515 * Atomic SCSI Target Request Descriptor 516 * Atomic RAID Accelerator Request Descriptor 517 * Atomic Fast Path SCSI IO Request Descriptor 518 * Atomic PCIe Encapsulated Request Descriptor 519 */ 520 521 /* Atomic Request Descriptor */ 522 typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR 523 { 524 U8 RequestFlags; /* 0x00 */ 525 U8 MSIxIndex; /* 0x01 */ 526 U16 SMID; /* 0x02 */ 527 } MPI26_ATOMIC_REQUEST_DESCRIPTOR, 528 MPI2_POINTER PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR, 529 Mpi26AtomicRequestDescriptor_t, MPI2_POINTER pMpi26AtomicRequestDescriptor_t; 530 531 /* for the RequestFlags field, use the same defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR */ 532 533 /* Reply Descriptors */ 534 535 /* Default Reply Descriptor */ 536 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR 537 { 538 U8 ReplyFlags; /* 0x00 */ 539 U8 MSIxIndex; /* 0x01 */ 540 U16 DescriptorTypeDependent1; /* 0x02 */ 541 U32 DescriptorTypeDependent2; /* 0x04 */ 542 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 543 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 544 545 /* defines for the ReplyFlags field */ 546 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 547 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 548 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 549 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 550 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 551 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 552 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06) 553 #define MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS (0x08) 554 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 555 556 /* values for marking a reply descriptor as unused */ 557 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 558 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 559 560 /* Address Reply Descriptor */ 561 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR 562 { 563 U8 ReplyFlags; /* 0x00 */ 564 U8 MSIxIndex; /* 0x01 */ 565 U16 SMID; /* 0x02 */ 566 U32 ReplyFrameAddress; /* 0x04 */ 567 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 568 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 569 570 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) 571 572 /* SCSI IO Success Reply Descriptor */ 573 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 574 { 575 U8 ReplyFlags; /* 0x00 */ 576 U8 MSIxIndex; /* 0x01 */ 577 U16 SMID; /* 0x02 */ 578 U16 TaskTag; /* 0x04 */ 579 U16 Reserved1; /* 0x06 */ 580 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 581 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 582 Mpi2SCSIIOSuccessReplyDescriptor_t, 583 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 584 585 /* TargetAssist Success Reply Descriptor */ 586 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR 587 { 588 U8 ReplyFlags; /* 0x00 */ 589 U8 MSIxIndex; /* 0x01 */ 590 U16 SMID; /* 0x02 */ 591 U8 SequenceNumber; /* 0x04 */ 592 U8 Reserved1; /* 0x05 */ 593 U16 IoIndex; /* 0x06 */ 594 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 595 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 596 Mpi2TargetAssistSuccessReplyDescriptor_t, 597 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 598 599 /* Target Command Buffer Reply Descriptor */ 600 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 601 { 602 U8 ReplyFlags; /* 0x00 */ 603 U8 MSIxIndex; /* 0x01 */ 604 U8 VP_ID; /* 0x02 */ 605 U8 Flags; /* 0x03 */ 606 U16 InitiatorDevHandle; /* 0x04 */ 607 U16 IoIndex; /* 0x06 */ 608 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 609 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 610 Mpi2TargetCommandBufferReplyDescriptor_t, 611 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 612 613 /* defines for Flags field */ 614 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) 615 616 /* RAID Accelerator Success Reply Descriptor */ 617 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 618 { 619 U8 ReplyFlags; /* 0x00 */ 620 U8 MSIxIndex; /* 0x01 */ 621 U16 SMID; /* 0x02 */ 622 U32 Reserved; /* 0x04 */ 623 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 624 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 625 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 626 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 627 628 /* Fast Path SCSI IO Success Reply Descriptor */ 629 typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 630 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 631 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 632 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t, 633 MPI2_POINTER pMpi25FastPathSCSIIOSuccessReplyDescriptor_t; 634 635 /* PCIe Encapsulated Success Reply Descriptor */ 636 typedef MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 637 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR, 638 MPI2_POINTER PTR_MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR, 639 Mpi26PCIeEncapsulatedSuccessReplyDescriptor_t, 640 MPI2_POINTER pMpi26PCIeEncapsulatedSuccessReplyDescriptor_t; 641 642 /* union of Reply Descriptors */ 643 typedef union _MPI2_REPLY_DESCRIPTORS_UNION 644 { 645 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 646 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 647 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 648 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 649 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 650 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 651 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess; 652 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR PCIeEncapsulatedSuccess; 653 U64 Words; 654 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 655 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 656 657 /***************************************************************************** 658 * 659 * Message Functions 660 * 661 *****************************************************************************/ 662 663 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 664 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 665 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 666 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 667 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 668 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 669 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 670 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 671 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 672 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 673 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 674 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 675 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 676 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 677 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 678 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 679 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 680 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 681 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 682 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ /* for MPI v2.5 and earlier */ 683 #define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B) /* IO Unit Control */ /* for MPI v2.6 and later */ 684 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 685 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 686 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 687 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 688 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 689 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 690 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 691 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 692 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) /* Send Host Message */ 693 #define MPI2_FUNCTION_NVME_ENCAPSULATED (0x33) /* NVMe Encapsulated (MPI v2.6) */ 694 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 695 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 696 697 /* Doorbell functions */ 698 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 699 #define MPI2_FUNCTION_HANDSHAKE (0x42) 700 701 /***************************************************************************** 702 * 703 * IOC Status Values 704 * 705 *****************************************************************************/ 706 707 /* mask for IOCStatus status value */ 708 #define MPI2_IOCSTATUS_MASK (0x7FFF) 709 710 /**************************************************************************** 711 * Common IOCStatus values for all replies 712 ****************************************************************************/ 713 714 #define MPI2_IOCSTATUS_SUCCESS (0x0000) 715 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) 716 #define MPI2_IOCSTATUS_BUSY (0x0002) 717 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003) 718 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) 719 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005) 720 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 721 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 722 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 723 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 724 #define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A) /* MPI v2.6 and later */ 725 726 /**************************************************************************** 727 * Config IOCStatus values 728 ****************************************************************************/ 729 730 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 731 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 732 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 733 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 734 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 735 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 736 737 /**************************************************************************** 738 * SCSI IO Reply 739 ****************************************************************************/ 740 741 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 742 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 743 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 744 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 745 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 746 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 747 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 748 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 749 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 750 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 751 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 752 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 753 754 /**************************************************************************** 755 * For use by SCSI Initiator and SCSI Target end-to-end data protection 756 ****************************************************************************/ 757 758 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 759 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 760 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 761 762 /**************************************************************************** 763 * SCSI Target values 764 ****************************************************************************/ 765 766 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 767 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) 768 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 769 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 770 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 771 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 772 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 773 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 774 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 775 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 776 777 /**************************************************************************** 778 * Serial Attached SCSI values 779 ****************************************************************************/ 780 781 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 782 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 783 784 /**************************************************************************** 785 * Diagnostic Buffer Post / Diagnostic Release values 786 ****************************************************************************/ 787 788 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 789 790 /**************************************************************************** 791 * RAID Accelerator values 792 ****************************************************************************/ 793 794 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) 795 796 /**************************************************************************** 797 * IOCStatus flag to indicate that log info is available 798 ****************************************************************************/ 799 800 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 801 802 /**************************************************************************** 803 * IOCLogInfo Types 804 ****************************************************************************/ 805 806 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) 807 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28) 808 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0) 809 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) 810 #define MPI2_IOCLOGINFO_TYPE_FC (0x2) 811 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3) 812 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) 813 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 814 815 /***************************************************************************** 816 * 817 * Standard Message Structures 818 * 819 *****************************************************************************/ 820 821 /**************************************************************************** 822 * Request Message Header for all request messages 823 ****************************************************************************/ 824 825 typedef struct _MPI2_REQUEST_HEADER 826 { 827 U16 FunctionDependent1; /* 0x00 */ 828 U8 ChainOffset; /* 0x02 */ 829 U8 Function; /* 0x03 */ 830 U16 FunctionDependent2; /* 0x04 */ 831 U8 FunctionDependent3; /* 0x06 */ 832 U8 MsgFlags; /* 0x07 */ 833 U8 VP_ID; /* 0x08 */ 834 U8 VF_ID; /* 0x09 */ 835 U16 Reserved1; /* 0x0A */ 836 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER, 837 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t; 838 839 /**************************************************************************** 840 * Default Reply 841 ****************************************************************************/ 842 843 typedef struct _MPI2_DEFAULT_REPLY 844 { 845 U16 FunctionDependent1; /* 0x00 */ 846 U8 MsgLength; /* 0x02 */ 847 U8 Function; /* 0x03 */ 848 U16 FunctionDependent2; /* 0x04 */ 849 U8 FunctionDependent3; /* 0x06 */ 850 U8 MsgFlags; /* 0x07 */ 851 U8 VP_ID; /* 0x08 */ 852 U8 VF_ID; /* 0x09 */ 853 U16 Reserved1; /* 0x0A */ 854 U16 FunctionDependent5; /* 0x0C */ 855 U16 IOCStatus; /* 0x0E */ 856 U32 IOCLogInfo; /* 0x10 */ 857 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY, 858 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t; 859 860 /* common version structure/union used in messages and configuration pages */ 861 862 typedef struct _MPI2_VERSION_STRUCT 863 { 864 U8 Dev; /* 0x00 */ 865 U8 Unit; /* 0x01 */ 866 U8 Minor; /* 0x02 */ 867 U8 Major; /* 0x03 */ 868 } MPI2_VERSION_STRUCT; 869 870 typedef union _MPI2_VERSION_UNION 871 { 872 MPI2_VERSION_STRUCT Struct; 873 U32 Word; 874 } MPI2_VERSION_UNION; 875 876 /* LUN field defines, common to many structures */ 877 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 878 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 879 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 880 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 881 #define MPI2_LUN_LEVEL_1_WORD (0xFF00) 882 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) 883 884 /***************************************************************************** 885 * 886 * Fusion-MPT MPI Scatter Gather Elements 887 * 888 *****************************************************************************/ 889 890 /**************************************************************************** 891 * MPI Simple Element structures 892 ****************************************************************************/ 893 894 typedef struct _MPI2_SGE_SIMPLE32 895 { 896 U32 FlagsLength; 897 U32 Address; 898 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32, 899 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t; 900 901 typedef struct _MPI2_SGE_SIMPLE64 902 { 903 U32 FlagsLength; 904 U64 Address; 905 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64, 906 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t; 907 908 typedef struct _MPI2_SGE_SIMPLE_UNION 909 { 910 U32 FlagsLength; 911 union 912 { 913 U32 Address32; 914 U64 Address64; 915 } u; 916 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 917 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 918 919 /**************************************************************************** 920 * MPI Chain Element structures - for MPI v2.0 products only 921 ****************************************************************************/ 922 923 typedef struct _MPI2_SGE_CHAIN32 924 { 925 U16 Length; 926 U8 NextChainOffset; 927 U8 Flags; 928 U32 Address; 929 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32, 930 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t; 931 932 typedef struct _MPI2_SGE_CHAIN64 933 { 934 U16 Length; 935 U8 NextChainOffset; 936 U8 Flags; 937 U64 Address; 938 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64, 939 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t; 940 941 typedef struct _MPI2_SGE_CHAIN_UNION 942 { 943 U16 Length; 944 U8 NextChainOffset; 945 U8 Flags; 946 union 947 { 948 U32 Address32; 949 U64 Address64; 950 } u; 951 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 952 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 953 954 /**************************************************************************** 955 * MPI Transaction Context Element structures - for MPI v2.0 products only 956 ****************************************************************************/ 957 958 typedef struct _MPI2_SGE_TRANSACTION32 959 { 960 U8 Reserved; 961 U8 ContextSize; 962 U8 DetailsLength; 963 U8 Flags; 964 U32 TransactionContext[1]; 965 U32 TransactionDetails[1]; 966 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32, 967 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t; 968 969 typedef struct _MPI2_SGE_TRANSACTION64 970 { 971 U8 Reserved; 972 U8 ContextSize; 973 U8 DetailsLength; 974 U8 Flags; 975 U32 TransactionContext[2]; 976 U32 TransactionDetails[1]; 977 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64, 978 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t; 979 980 typedef struct _MPI2_SGE_TRANSACTION96 981 { 982 U8 Reserved; 983 U8 ContextSize; 984 U8 DetailsLength; 985 U8 Flags; 986 U32 TransactionContext[3]; 987 U32 TransactionDetails[1]; 988 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96, 989 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t; 990 991 typedef struct _MPI2_SGE_TRANSACTION128 992 { 993 U8 Reserved; 994 U8 ContextSize; 995 U8 DetailsLength; 996 U8 Flags; 997 U32 TransactionContext[4]; 998 U32 TransactionDetails[1]; 999 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128, 1000 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128; 1001 1002 typedef struct _MPI2_SGE_TRANSACTION_UNION 1003 { 1004 U8 Reserved; 1005 U8 ContextSize; 1006 U8 DetailsLength; 1007 U8 Flags; 1008 union 1009 { 1010 U32 TransactionContext32[1]; 1011 U32 TransactionContext64[2]; 1012 U32 TransactionContext96[3]; 1013 U32 TransactionContext128[4]; 1014 } u; 1015 U32 TransactionDetails[1]; 1016 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION, 1017 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t; 1018 1019 /**************************************************************************** 1020 * MPI SGE union for IO SGL's - for MPI v2.0 products only 1021 ****************************************************************************/ 1022 1023 typedef struct _MPI2_MPI_SGE_IO_UNION 1024 { 1025 union 1026 { 1027 MPI2_SGE_SIMPLE_UNION Simple; 1028 MPI2_SGE_CHAIN_UNION Chain; 1029 } u; 1030 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION, 1031 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t; 1032 1033 /**************************************************************************** 1034 * MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only 1035 ****************************************************************************/ 1036 1037 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION 1038 { 1039 union 1040 { 1041 MPI2_SGE_SIMPLE_UNION Simple; 1042 MPI2_SGE_TRANSACTION_UNION Transaction; 1043 } u; 1044 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION, 1045 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t; 1046 1047 /**************************************************************************** 1048 * All MPI SGE types union 1049 ****************************************************************************/ 1050 1051 typedef struct _MPI2_MPI_SGE_UNION 1052 { 1053 union 1054 { 1055 MPI2_SGE_SIMPLE_UNION Simple; 1056 MPI2_SGE_CHAIN_UNION Chain; 1057 MPI2_SGE_TRANSACTION_UNION Transaction; 1058 } u; 1059 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION, 1060 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t; 1061 1062 /**************************************************************************** 1063 * MPI SGE field definition and masks 1064 ****************************************************************************/ 1065 1066 /* Flags field bit definitions */ 1067 1068 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) 1069 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) 1070 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 1071 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) 1072 #define MPI2_SGE_FLAGS_DIRECTION (0x04) 1073 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) 1074 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01) 1075 1076 #define MPI2_SGE_FLAGS_SHIFT (24) 1077 1078 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) 1079 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 1080 1081 /* Element Type */ 1082 1083 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) /* for MPI v2.0 products only */ 1084 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 1085 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) /* for MPI v2.0 products only */ 1086 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) 1087 1088 /* Address location */ 1089 1090 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 1091 1092 /* Direction */ 1093 1094 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) 1095 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) 1096 1097 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST) 1098 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC) 1099 1100 /* Address Size */ 1101 1102 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1103 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1104 1105 /* Context Size */ 1106 1107 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) 1108 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) 1109 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) 1110 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) 1111 1112 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 1113 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) 1114 1115 /**************************************************************************** 1116 * MPI SGE operation Macros 1117 ****************************************************************************/ 1118 1119 /* SIMPLE FlagsLength manipulations... */ 1120 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) 1121 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT) 1122 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) 1123 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) 1124 1125 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l)) 1126 1127 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) 1128 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) 1129 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l) 1130 1131 /* CAUTION - The following are READ-MODIFY-WRITE! */ 1132 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f) 1133 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l) 1134 1135 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT) 1136 1137 /***************************************************************************** 1138 * 1139 * Fusion-MPT IEEE Scatter Gather Elements 1140 * 1141 *****************************************************************************/ 1142 1143 /**************************************************************************** 1144 * IEEE Simple Element structures 1145 ****************************************************************************/ 1146 1147 /* MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */ 1148 typedef struct _MPI2_IEEE_SGE_SIMPLE32 1149 { 1150 U32 Address; 1151 U32 FlagsLength; 1152 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 1153 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 1154 1155 typedef struct _MPI2_IEEE_SGE_SIMPLE64 1156 { 1157 U64 Address; 1158 U32 Length; 1159 U16 Reserved1; 1160 U8 Reserved2; 1161 U8 Flags; 1162 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 1163 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 1164 1165 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION 1166 { 1167 MPI2_IEEE_SGE_SIMPLE32 Simple32; 1168 MPI2_IEEE_SGE_SIMPLE64 Simple64; 1169 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 1170 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 1171 1172 /**************************************************************************** 1173 * IEEE Chain Element structures 1174 ****************************************************************************/ 1175 1176 /* MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */ 1177 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 1178 1179 /* MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */ 1180 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 1181 1182 typedef union _MPI2_IEEE_SGE_CHAIN_UNION 1183 { 1184 MPI2_IEEE_SGE_CHAIN32 Chain32; 1185 MPI2_IEEE_SGE_CHAIN64 Chain64; 1186 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 1187 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 1188 1189 /* MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */ 1190 typedef struct _MPI25_IEEE_SGE_CHAIN64 1191 { 1192 U64 Address; 1193 U32 Length; 1194 U16 Reserved1; 1195 U8 NextChainOffset; 1196 U8 Flags; 1197 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, 1198 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t; 1199 1200 /**************************************************************************** 1201 * All IEEE SGE types union 1202 ****************************************************************************/ 1203 1204 /* MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */ 1205 typedef struct _MPI2_IEEE_SGE_UNION 1206 { 1207 union 1208 { 1209 MPI2_IEEE_SGE_SIMPLE_UNION Simple; 1210 MPI2_IEEE_SGE_CHAIN_UNION Chain; 1211 } u; 1212 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION, 1213 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t; 1214 1215 /**************************************************************************** 1216 * IEEE SGE union for IO SGL's 1217 ****************************************************************************/ 1218 1219 typedef union _MPI25_SGE_IO_UNION 1220 { 1221 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple; 1222 MPI25_IEEE_SGE_CHAIN64 IeeeChain; 1223 } MPI25_SGE_IO_UNION, MPI2_POINTER PTR_MPI25_SGE_IO_UNION, 1224 Mpi25SGEIOUnion_t, MPI2_POINTER pMpi25SGEIOUnion_t; 1225 1226 /**************************************************************************** 1227 * IEEE SGE field definitions and masks 1228 ****************************************************************************/ 1229 1230 /* Flags field bit definitions */ 1231 1232 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1233 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1234 1235 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1236 1237 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1238 1239 /* Element Type */ 1240 1241 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1242 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1243 1244 /* Next Segment Format */ 1245 1246 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C) 1247 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00) 1248 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08) 1249 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10) 1250 1251 /* Data Location Address Space */ 1252 1253 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1254 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5 and later, use in IEEE Simple or Chain element */ 1255 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* use in IEEE Simple Element only */ 1256 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1257 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5, use in IEEE Simple or Chain element */ 1258 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) /* use in MPI v2.0 IEEE Chain Element only */ 1259 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */ 1260 1261 #define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02) /* for MPI v2.6 only */ 1262 1263 /**************************************************************************** 1264 * IEEE SGE operation Macros 1265 ****************************************************************************/ 1266 1267 /* SIMPLE FlagsLength manipulations... */ 1268 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) 1269 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT) 1270 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) 1271 1272 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l)) 1273 1274 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) 1275 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) 1276 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l) 1277 1278 /* CAUTION - The following are READ-MODIFY-WRITE! */ 1279 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f) 1280 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l) 1281 1282 /***************************************************************************** 1283 * 1284 * Fusion-MPT MPI/IEEE Scatter Gather Unions 1285 * 1286 *****************************************************************************/ 1287 1288 typedef union _MPI2_SIMPLE_SGE_UNION 1289 { 1290 MPI2_SGE_SIMPLE_UNION MpiSimple; 1291 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1292 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION, 1293 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t; 1294 1295 typedef union _MPI2_SGE_IO_UNION 1296 { 1297 MPI2_SGE_SIMPLE_UNION MpiSimple; 1298 MPI2_SGE_CHAIN_UNION MpiChain; 1299 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1300 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1301 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 1302 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 1303 1304 /**************************************************************************** 1305 * 1306 * Values for SGLFlags field, used in many request messages with an SGL 1307 * 1308 ****************************************************************************/ 1309 1310 /* values for MPI SGL Data Location Address Space subfield */ 1311 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) 1312 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) 1313 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) 1314 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.5 and earlier */ 1315 #define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.6 */ 1316 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) /* only for MPI v2.5 and earlier */ 1317 /* values for SGL Type subfield */ 1318 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) 1319 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) 1320 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) /* MPI v2.0 products only */ 1321 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) 1322 1323 #endif 1324