1 /*- 2 * Copyright 2000-2020 Broadcom Inc. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 3. Neither the name of the author nor the names of any co-contributors 13 * may be used to endorse or promote products derived from this software 14 * without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * Broadcom Inc. (LSI) MPT-Fusion Host Adapter FreeBSD 29 * 30 * $FreeBSD$ 31 */ 32 33 /* 34 * Copyright 2000-2020 Broadcom Inc. All rights reserved. 35 * 36 * 37 * Name: mpi2.h 38 * Title: MPI Message independent structures and definitions 39 * including System Interface Register Set and 40 * scatter/gather formats. 41 * Creation Date: June 21, 2006 42 * 43 * mpi2.h Version: 02.00.52 44 * 45 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 46 * prefix are for use only on MPI v2.5 products, and must not be used 47 * with MPI v2.0 products. Unless otherwise noted, names beginning with 48 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 49 * 50 * Version History 51 * --------------- 52 * 53 * Date Version Description 54 * -------- -------- ------------------------------------------------------ 55 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 56 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. 57 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. 58 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. 59 * Moved ReplyPostHostIndex register to offset 0x6C of the 60 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for 61 * MPI2_REPLY_POST_HOST_INDEX_OFFSET. 62 * Added union of request descriptors. 63 * Added union of reply descriptors. 64 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. 65 * Added define for MPI2_VERSION_02_00. 66 * Fixed the size of the FunctionDependent5 field in the 67 * MPI2_DEFAULT_REPLY structure. 68 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. 69 * Removed the MPI-defined Fault Codes and extended the 70 * product specific codes up to 0xEFFF. 71 * Added a sixth key value for the WriteSequence register 72 * and changed the flush value to 0x0. 73 * Added message function codes for Diagnostic Buffer Post 74 * and Diagnsotic Release. 75 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED 76 * Moved MPI2_VERSION_UNION from mpi2_ioc.h. 77 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. 78 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. 79 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. 80 * Added #defines for marking a reply descriptor as unused. 81 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. 82 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. 83 * Moved LUN field defines from mpi2_init.h. 84 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. 85 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT. 86 * In all request and reply descriptors, replaced VF_ID 87 * field with MSIxIndex field. 88 * Removed DevHandle field from 89 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 90 * bytes reserved. 91 * Added RAID Accelerator functionality. 92 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT. 93 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT. 94 * Added MSI-x index mask and shift for Reply Post Host 95 * Index register. 96 * Added function code for Host Based Discovery Action. 97 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT. 98 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL. 99 * Added defines for product-specific range of message 100 * function codes, 0xF0 to 0xFF. 101 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT. 102 * Added alternative defines for the SGE Direction bit. 103 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT. 104 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT. 105 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define. 106 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT. 107 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE. 108 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT. 109 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT. 110 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT. 111 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT. 112 * Incorporating additions for MPI v2.5. 113 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT. 114 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT. 115 * Added Hard Reset delay timings. 116 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT. 117 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT. 118 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT. 119 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT. 120 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET. 121 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT. 122 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT. 123 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT. 124 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT. 125 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT. 126 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT. 127 * 11-18-14 02.00.36 Updated copyright information. 128 * Bumped MPI2_HEADER_VERSION_UNIT. 129 * 03-16-15 02.00.37 Updated for MPI v2.6. 130 * Bumped MPI2_HEADER_VERSION_UNIT. 131 * Added Scratchpad registers and 132 * AtomicRequestDescriptorPost register to 133 * MPI2_SYSTEM_INTERFACE_REGS. 134 * Added MPI2_DIAG_SBR_RELOAD. 135 * Added MPI2_IOCSTATUS_INSUFFICIENT_POWER. 136 * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT. 137 * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT 138 * 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT. 139 * Added V7 HostDiagnostic register defines 140 * 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT 141 * 01-01-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT 142 * 04-05-16 02.00.43 Modified MPI26_DIAG_BOOT_DEVICE_SELECT defines 143 * to be unique within first 32 characters. 144 * Removed AHCI support. 145 * Removed SOP support. 146 * Bumped MPI2_HEADER_VERSION_UNIT. 147 * 04-10-16 02.00.44 Bumped MPI2_HEADER_VERSION_UNIT. 148 * 07-06-16 02.00.45 Bumped MPI2_HEADER_VERSION_UNIT. 149 * 09-02-16 02.00.46 Bumped MPI2_HEADER_VERSION_UNIT. 150 * 11-23-16 02.00.47 Bumped MPI2_HEADER_VERSION_UNIT. 151 * 02-03-17 02.00.48 Bumped MPI2_HEADER_VERSION_UNIT. 152 * 06-13-17 02.00.49 Bumped MPI2_HEADER_VERSION_UNIT. 153 * 09-29-17 02.00.50 Bumped MPI2_HEADER_VERSION_UNIT. 154 * 07-22-18 02.00.51 Added SECURE_BOOT define. 155 * Bumped MPI2_HEADER_VERSION_UNIT 156 * 08-15-18 02.00.52 Bumped MPI2_HEADER_VERSION_UNIT. 157 * -------------------------------------------------------------------------- 158 */ 159 160 #ifndef MPI2_H 161 #define MPI2_H 162 163 /***************************************************************************** 164 * 165 * MPI Version Definitions 166 * 167 *****************************************************************************/ 168 169 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 170 #define MPI2_VERSION_MAJOR_SHIFT (8) 171 #define MPI2_VERSION_MINOR_MASK (0x00FF) 172 #define MPI2_VERSION_MINOR_SHIFT (0) 173 174 /* major version for all MPI v2.x */ 175 #define MPI2_VERSION_MAJOR (0x02) 176 177 /* minor version for MPI v2.0 compatible products */ 178 #define MPI2_VERSION_MINOR (0x00) 179 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 180 MPI2_VERSION_MINOR) 181 #define MPI2_VERSION_02_00 (0x0200) 182 183 /* minor version for MPI v2.5 compatible products */ 184 #define MPI25_VERSION_MINOR (0x05) 185 #define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 186 MPI25_VERSION_MINOR) 187 #define MPI2_VERSION_02_05 (0x0205) 188 189 /* minor version for MPI v2.6 compatible products */ 190 #define MPI26_VERSION_MINOR (0x06) 191 #define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 192 MPI26_VERSION_MINOR) 193 #define MPI2_VERSION_02_06 (0x0206) 194 195 /* Unit and Dev versioning for this MPI header set */ 196 #define MPI2_HEADER_VERSION_UNIT (0x34) 197 #define MPI2_HEADER_VERSION_DEV (0x00) 198 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 199 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 200 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 201 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 202 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 203 204 /***************************************************************************** 205 * 206 * IOC State Definitions 207 * 208 *****************************************************************************/ 209 210 #define MPI2_IOC_STATE_RESET (0x00000000) 211 #define MPI2_IOC_STATE_READY (0x10000000) 212 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000) 213 #define MPI2_IOC_STATE_FAULT (0x40000000) 214 215 #define MPI2_IOC_STATE_MASK (0xF0000000) 216 #define MPI2_IOC_STATE_SHIFT (28) 217 218 /* Fault state range for prodcut specific codes */ 219 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) 220 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) 221 222 /***************************************************************************** 223 * 224 * System Interface Register Definitions 225 * 226 *****************************************************************************/ 227 228 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS 229 { 230 U32 Doorbell; /* 0x00 */ 231 U32 WriteSequence; /* 0x04 */ 232 U32 HostDiagnostic; /* 0x08 */ 233 U32 Reserved1; /* 0x0C */ 234 U32 DiagRWData; /* 0x10 */ 235 U32 DiagRWAddressLow; /* 0x14 */ 236 U32 DiagRWAddressHigh; /* 0x18 */ 237 U32 Reserved2[5]; /* 0x1C */ 238 U32 HostInterruptStatus; /* 0x30 */ 239 U32 HostInterruptMask; /* 0x34 */ 240 U32 DCRData; /* 0x38 */ 241 U32 DCRAddress; /* 0x3C */ 242 U32 Reserved3[2]; /* 0x40 */ 243 U32 ReplyFreeHostIndex; /* 0x48 */ 244 U32 Reserved4[8]; /* 0x4C */ 245 U32 ReplyPostHostIndex; /* 0x6C */ 246 U32 Reserved5; /* 0x70 */ 247 U32 HCBSize; /* 0x74 */ 248 U32 HCBAddressLow; /* 0x78 */ 249 U32 HCBAddressHigh; /* 0x7C */ 250 U32 Reserved6[12]; /* 0x80 */ 251 U32 Scratchpad[4]; /* 0xB0 */ 252 U32 RequestDescriptorPostLow; /* 0xC0 */ 253 U32 RequestDescriptorPostHigh; /* 0xC4 */ 254 U32 AtomicRequestDescriptorPost;/* 0xC8 */ /* MPI v2.6 and later; reserved in earlier versions */ 255 U32 Reserved7[13]; /* 0xCC */ 256 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS, 257 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t; 258 259 /* 260 * Defines for working with the Doorbell register. 261 */ 262 #define MPI2_DOORBELL_OFFSET (0x00000000) 263 264 /* IOC --> System values */ 265 #define MPI2_DOORBELL_USED (0x08000000) 266 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) 267 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24) 268 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) 269 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) 270 271 /* System --> IOC values */ 272 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) 273 #define MPI2_DOORBELL_FUNCTION_SHIFT (24) 274 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 275 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) 276 277 /* 278 * Defines for the WriteSequence register 279 */ 280 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 281 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) 282 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 283 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 284 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 285 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 286 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 287 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 288 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 289 290 /* 291 * Defines for the HostDiagnostic register 292 */ 293 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 294 295 #define MPI26_DIAG_SECURE_BOOT (0x80000000) 296 297 #define MPI2_DIAG_SBR_RELOAD (0x00002000) 298 299 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 300 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) 301 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) 302 303 /* Defines for V7A/V7R HostDiagnostic Register */ 304 #define MPI26_DIAG_BOOT_DEVICE_SEL_64FLASH (0x00000000) 305 #define MPI26_DIAG_BOOT_DEVICE_SEL_64HCDW (0x00000800) 306 #define MPI26_DIAG_BOOT_DEVICE_SEL_32FLASH (0x00001000) 307 #define MPI26_DIAG_BOOT_DEVICE_SEL_32HCDW (0x00001800) 308 309 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 310 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) 311 #define MPI2_DIAG_HCB_MODE (0x00000100) 312 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) 313 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) 314 #define MPI2_DIAG_RESET_HISTORY (0x00000020) 315 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) 316 #define MPI2_DIAG_RESET_ADAPTER (0x00000004) 317 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) 318 319 /* 320 * Offsets for DiagRWData and address 321 */ 322 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) 323 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) 324 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) 325 326 /* 327 * Defines for the HostInterruptStatus register 328 */ 329 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 330 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) 331 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS 332 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) 333 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) 334 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) 335 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS 336 337 /* 338 * Defines for the HostInterruptMask register 339 */ 340 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 341 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000) 342 #define MPI2_HIM_REPLY_INT_MASK (0x00000008) 343 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK 344 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) 345 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK 346 347 /* 348 * Offsets for DCRData and address 349 */ 350 #define MPI2_DCR_DATA_OFFSET (0x00000038) 351 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) 352 353 /* 354 * Offset for the Reply Free Queue 355 */ 356 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) 357 358 /* 359 * Defines for the Reply Descriptor Post Queue 360 */ 361 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 362 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) 363 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) 364 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24) 365 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /* MPI v2.5 only */ 366 367 /* 368 * Defines for the HCBSize and address 369 */ 370 #define MPI2_HCB_SIZE_OFFSET (0x00000074) 371 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) 372 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) 373 374 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) 375 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) 376 377 /* 378 * Offsets for the Scratchpad registers 379 */ 380 #define MPI26_SCRATCHPAD0_OFFSET (0x000000B0) 381 #define MPI26_SCRATCHPAD1_OFFSET (0x000000B4) 382 #define MPI26_SCRATCHPAD2_OFFSET (0x000000B8) 383 #define MPI26_SCRATCHPAD3_OFFSET (0x000000BC) 384 385 /* 386 * Offsets for the Request Descriptor Post Queue 387 */ 388 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) 389 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) 390 #define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8) 391 392 /* Hard Reset delay timings */ 393 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000) 394 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000) 395 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000) 396 397 /***************************************************************************** 398 * 399 * Message Descriptors 400 * 401 *****************************************************************************/ 402 403 /* Request Descriptors */ 404 405 /* Default Request Descriptor */ 406 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR 407 { 408 U8 RequestFlags; /* 0x00 */ 409 U8 MSIxIndex; /* 0x01 */ 410 U16 SMID; /* 0x02 */ 411 U16 LMID; /* 0x04 */ 412 U16 DescriptorTypeDependent; /* 0x06 */ 413 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 414 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 415 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 416 417 /* defines for the RequestFlags field */ 418 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E) 419 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1) /* use carefully; values below are pre-shifted left */ 420 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 421 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 422 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 423 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 424 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 425 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C) 426 #define MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED (0x10) 427 428 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 429 430 /* High Priority Request Descriptor */ 431 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR 432 { 433 U8 RequestFlags; /* 0x00 */ 434 U8 MSIxIndex; /* 0x01 */ 435 U16 SMID; /* 0x02 */ 436 U16 LMID; /* 0x04 */ 437 U16 Reserved1; /* 0x06 */ 438 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 439 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 440 Mpi2HighPriorityRequestDescriptor_t, 441 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 442 443 /* SCSI IO Request Descriptor */ 444 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR 445 { 446 U8 RequestFlags; /* 0x00 */ 447 U8 MSIxIndex; /* 0x01 */ 448 U16 SMID; /* 0x02 */ 449 U16 LMID; /* 0x04 */ 450 U16 DevHandle; /* 0x06 */ 451 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 452 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 453 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 454 455 /* SCSI Target Request Descriptor */ 456 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR 457 { 458 U8 RequestFlags; /* 0x00 */ 459 U8 MSIxIndex; /* 0x01 */ 460 U16 SMID; /* 0x02 */ 461 U16 LMID; /* 0x04 */ 462 U16 IoIndex; /* 0x06 */ 463 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 464 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 465 Mpi2SCSITargetRequestDescriptor_t, 466 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 467 468 /* RAID Accelerator Request Descriptor */ 469 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR 470 { 471 U8 RequestFlags; /* 0x00 */ 472 U8 MSIxIndex; /* 0x01 */ 473 U16 SMID; /* 0x02 */ 474 U16 LMID; /* 0x04 */ 475 U16 Reserved; /* 0x06 */ 476 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 477 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 478 Mpi2RAIDAcceleratorRequestDescriptor_t, 479 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 480 481 /* Fast Path SCSI IO Request Descriptor */ 482 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR 483 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 484 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 485 Mpi25FastPathSCSIIORequestDescriptor_t, 486 MPI2_POINTER pMpi25FastPathSCSIIORequestDescriptor_t; 487 488 /* PCIe Encapsulated Request Descriptor */ 489 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR 490 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR, 491 MPI2_POINTER PTR_MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR, 492 Mpi26PCIeEncapsulatedRequestDescriptor_t, 493 MPI2_POINTER pMpi26PCIeEncapsulatedRequestDescriptor_t; 494 495 /* union of Request Descriptors */ 496 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION 497 { 498 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 499 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 500 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 501 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 502 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 503 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO; 504 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR PCIeEncapsulated; 505 U64 Words; 506 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION, 507 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t; 508 509 /* Atomic Request Descriptors */ 510 511 /* 512 * All Atomic Request Descriptors have the same format, so the following 513 * structure is used for all Atomic Request Descriptors: 514 * Atomic Default Request Descriptor 515 * Atomic High Priority Request Descriptor 516 * Atomic SCSI IO Request Descriptor 517 * Atomic SCSI Target Request Descriptor 518 * Atomic RAID Accelerator Request Descriptor 519 * Atomic Fast Path SCSI IO Request Descriptor 520 * Atomic PCIe Encapsulated Request Descriptor 521 */ 522 523 /* Atomic Request Descriptor */ 524 typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR 525 { 526 U8 RequestFlags; /* 0x00 */ 527 U8 MSIxIndex; /* 0x01 */ 528 U16 SMID; /* 0x02 */ 529 } MPI26_ATOMIC_REQUEST_DESCRIPTOR, 530 MPI2_POINTER PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR, 531 Mpi26AtomicRequestDescriptor_t, MPI2_POINTER pMpi26AtomicRequestDescriptor_t; 532 533 /* for the RequestFlags field, use the same defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR */ 534 535 /* Reply Descriptors */ 536 537 /* Default Reply Descriptor */ 538 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR 539 { 540 U8 ReplyFlags; /* 0x00 */ 541 U8 MSIxIndex; /* 0x01 */ 542 U16 DescriptorTypeDependent1; /* 0x02 */ 543 U32 DescriptorTypeDependent2; /* 0x04 */ 544 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 545 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 546 547 /* defines for the ReplyFlags field */ 548 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 549 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 550 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 551 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 552 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 553 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 554 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06) 555 #define MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS (0x08) 556 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 557 558 /* values for marking a reply descriptor as unused */ 559 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 560 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 561 562 /* Address Reply Descriptor */ 563 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR 564 { 565 U8 ReplyFlags; /* 0x00 */ 566 U8 MSIxIndex; /* 0x01 */ 567 U16 SMID; /* 0x02 */ 568 U32 ReplyFrameAddress; /* 0x04 */ 569 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 570 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 571 572 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) 573 574 /* SCSI IO Success Reply Descriptor */ 575 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 576 { 577 U8 ReplyFlags; /* 0x00 */ 578 U8 MSIxIndex; /* 0x01 */ 579 U16 SMID; /* 0x02 */ 580 U16 TaskTag; /* 0x04 */ 581 U16 Reserved1; /* 0x06 */ 582 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 583 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 584 Mpi2SCSIIOSuccessReplyDescriptor_t, 585 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 586 587 /* TargetAssist Success Reply Descriptor */ 588 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR 589 { 590 U8 ReplyFlags; /* 0x00 */ 591 U8 MSIxIndex; /* 0x01 */ 592 U16 SMID; /* 0x02 */ 593 U8 SequenceNumber; /* 0x04 */ 594 U8 Reserved1; /* 0x05 */ 595 U16 IoIndex; /* 0x06 */ 596 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 597 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 598 Mpi2TargetAssistSuccessReplyDescriptor_t, 599 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 600 601 /* Target Command Buffer Reply Descriptor */ 602 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 603 { 604 U8 ReplyFlags; /* 0x00 */ 605 U8 MSIxIndex; /* 0x01 */ 606 U8 VP_ID; /* 0x02 */ 607 U8 Flags; /* 0x03 */ 608 U16 InitiatorDevHandle; /* 0x04 */ 609 U16 IoIndex; /* 0x06 */ 610 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 611 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 612 Mpi2TargetCommandBufferReplyDescriptor_t, 613 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 614 615 /* defines for Flags field */ 616 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) 617 618 /* RAID Accelerator Success Reply Descriptor */ 619 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 620 { 621 U8 ReplyFlags; /* 0x00 */ 622 U8 MSIxIndex; /* 0x01 */ 623 U16 SMID; /* 0x02 */ 624 U32 Reserved; /* 0x04 */ 625 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 626 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 627 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 628 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 629 630 /* Fast Path SCSI IO Success Reply Descriptor */ 631 typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 632 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 633 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 634 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t, 635 MPI2_POINTER pMpi25FastPathSCSIIOSuccessReplyDescriptor_t; 636 637 /* PCIe Encapsulated Success Reply Descriptor */ 638 typedef MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 639 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR, 640 MPI2_POINTER PTR_MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR, 641 Mpi26PCIeEncapsulatedSuccessReplyDescriptor_t, 642 MPI2_POINTER pMpi26PCIeEncapsulatedSuccessReplyDescriptor_t; 643 644 /* union of Reply Descriptors */ 645 typedef union _MPI2_REPLY_DESCRIPTORS_UNION 646 { 647 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 648 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 649 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 650 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 651 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 652 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 653 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess; 654 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR PCIeEncapsulatedSuccess; 655 U64 Words; 656 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 657 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 658 659 /***************************************************************************** 660 * 661 * Message Functions 662 * 663 *****************************************************************************/ 664 665 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 666 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 667 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 668 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 669 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 670 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 671 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 672 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 673 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 674 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 675 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 676 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 677 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 678 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 679 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 680 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 681 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 682 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 683 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 684 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ /* for MPI v2.5 and earlier */ 685 #define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B) /* IO Unit Control */ /* for MPI v2.6 and later */ 686 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 687 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 688 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 689 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 690 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 691 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 692 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 693 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 694 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) /* Send Host Message */ 695 #define MPI2_FUNCTION_NVME_ENCAPSULATED (0x33) /* NVMe Encapsulated (MPI v2.6) */ 696 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 697 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 698 699 /* Doorbell functions */ 700 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 701 #define MPI2_FUNCTION_HANDSHAKE (0x42) 702 703 /***************************************************************************** 704 * 705 * IOC Status Values 706 * 707 *****************************************************************************/ 708 709 /* mask for IOCStatus status value */ 710 #define MPI2_IOCSTATUS_MASK (0x7FFF) 711 712 /**************************************************************************** 713 * Common IOCStatus values for all replies 714 ****************************************************************************/ 715 716 #define MPI2_IOCSTATUS_SUCCESS (0x0000) 717 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) 718 #define MPI2_IOCSTATUS_BUSY (0x0002) 719 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003) 720 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) 721 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005) 722 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 723 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 724 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 725 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 726 #define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A) /* MPI v2.6 and later */ 727 728 /**************************************************************************** 729 * Config IOCStatus values 730 ****************************************************************************/ 731 732 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 733 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 734 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 735 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 736 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 737 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 738 739 /**************************************************************************** 740 * SCSI IO Reply 741 ****************************************************************************/ 742 743 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 744 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 745 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 746 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 747 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 748 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 749 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 750 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 751 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 752 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 753 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 754 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 755 756 /**************************************************************************** 757 * For use by SCSI Initiator and SCSI Target end-to-end data protection 758 ****************************************************************************/ 759 760 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 761 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 762 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 763 764 /**************************************************************************** 765 * SCSI Target values 766 ****************************************************************************/ 767 768 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 769 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) 770 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 771 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 772 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 773 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 774 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 775 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 776 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 777 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 778 779 /**************************************************************************** 780 * Serial Attached SCSI values 781 ****************************************************************************/ 782 783 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 784 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 785 786 /**************************************************************************** 787 * Diagnostic Buffer Post / Diagnostic Release values 788 ****************************************************************************/ 789 790 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 791 792 /**************************************************************************** 793 * RAID Accelerator values 794 ****************************************************************************/ 795 796 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) 797 798 /**************************************************************************** 799 * IOCStatus flag to indicate that log info is available 800 ****************************************************************************/ 801 802 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 803 804 /**************************************************************************** 805 * IOCLogInfo Types 806 ****************************************************************************/ 807 808 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) 809 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28) 810 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0) 811 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) 812 #define MPI2_IOCLOGINFO_TYPE_FC (0x2) 813 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3) 814 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) 815 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 816 817 /***************************************************************************** 818 * 819 * Standard Message Structures 820 * 821 *****************************************************************************/ 822 823 /**************************************************************************** 824 * Request Message Header for all request messages 825 ****************************************************************************/ 826 827 typedef struct _MPI2_REQUEST_HEADER 828 { 829 U16 FunctionDependent1; /* 0x00 */ 830 U8 ChainOffset; /* 0x02 */ 831 U8 Function; /* 0x03 */ 832 U16 FunctionDependent2; /* 0x04 */ 833 U8 FunctionDependent3; /* 0x06 */ 834 U8 MsgFlags; /* 0x07 */ 835 U8 VP_ID; /* 0x08 */ 836 U8 VF_ID; /* 0x09 */ 837 U16 Reserved1; /* 0x0A */ 838 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER, 839 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t; 840 841 /**************************************************************************** 842 * Default Reply 843 ****************************************************************************/ 844 845 typedef struct _MPI2_DEFAULT_REPLY 846 { 847 U16 FunctionDependent1; /* 0x00 */ 848 U8 MsgLength; /* 0x02 */ 849 U8 Function; /* 0x03 */ 850 U16 FunctionDependent2; /* 0x04 */ 851 U8 FunctionDependent3; /* 0x06 */ 852 U8 MsgFlags; /* 0x07 */ 853 U8 VP_ID; /* 0x08 */ 854 U8 VF_ID; /* 0x09 */ 855 U16 Reserved1; /* 0x0A */ 856 U16 FunctionDependent5; /* 0x0C */ 857 U16 IOCStatus; /* 0x0E */ 858 U32 IOCLogInfo; /* 0x10 */ 859 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY, 860 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t; 861 862 /* common version structure/union used in messages and configuration pages */ 863 864 typedef struct _MPI2_VERSION_STRUCT 865 { 866 U8 Dev; /* 0x00 */ 867 U8 Unit; /* 0x01 */ 868 U8 Minor; /* 0x02 */ 869 U8 Major; /* 0x03 */ 870 } MPI2_VERSION_STRUCT; 871 872 typedef union _MPI2_VERSION_UNION 873 { 874 MPI2_VERSION_STRUCT Struct; 875 U32 Word; 876 } MPI2_VERSION_UNION; 877 878 /* LUN field defines, common to many structures */ 879 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 880 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 881 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 882 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 883 #define MPI2_LUN_LEVEL_1_WORD (0xFF00) 884 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) 885 886 /***************************************************************************** 887 * 888 * Fusion-MPT MPI Scatter Gather Elements 889 * 890 *****************************************************************************/ 891 892 /**************************************************************************** 893 * MPI Simple Element structures 894 ****************************************************************************/ 895 896 typedef struct _MPI2_SGE_SIMPLE32 897 { 898 U32 FlagsLength; 899 U32 Address; 900 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32, 901 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t; 902 903 typedef struct _MPI2_SGE_SIMPLE64 904 { 905 U32 FlagsLength; 906 U64 Address; 907 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64, 908 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t; 909 910 typedef struct _MPI2_SGE_SIMPLE_UNION 911 { 912 U32 FlagsLength; 913 union 914 { 915 U32 Address32; 916 U64 Address64; 917 } u; 918 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 919 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 920 921 /**************************************************************************** 922 * MPI Chain Element structures - for MPI v2.0 products only 923 ****************************************************************************/ 924 925 typedef struct _MPI2_SGE_CHAIN32 926 { 927 U16 Length; 928 U8 NextChainOffset; 929 U8 Flags; 930 U32 Address; 931 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32, 932 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t; 933 934 typedef struct _MPI2_SGE_CHAIN64 935 { 936 U16 Length; 937 U8 NextChainOffset; 938 U8 Flags; 939 U64 Address; 940 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64, 941 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t; 942 943 typedef struct _MPI2_SGE_CHAIN_UNION 944 { 945 U16 Length; 946 U8 NextChainOffset; 947 U8 Flags; 948 union 949 { 950 U32 Address32; 951 U64 Address64; 952 } u; 953 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 954 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 955 956 /**************************************************************************** 957 * MPI Transaction Context Element structures - for MPI v2.0 products only 958 ****************************************************************************/ 959 960 typedef struct _MPI2_SGE_TRANSACTION32 961 { 962 U8 Reserved; 963 U8 ContextSize; 964 U8 DetailsLength; 965 U8 Flags; 966 U32 TransactionContext[1]; 967 U32 TransactionDetails[1]; 968 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32, 969 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t; 970 971 typedef struct _MPI2_SGE_TRANSACTION64 972 { 973 U8 Reserved; 974 U8 ContextSize; 975 U8 DetailsLength; 976 U8 Flags; 977 U32 TransactionContext[2]; 978 U32 TransactionDetails[1]; 979 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64, 980 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t; 981 982 typedef struct _MPI2_SGE_TRANSACTION96 983 { 984 U8 Reserved; 985 U8 ContextSize; 986 U8 DetailsLength; 987 U8 Flags; 988 U32 TransactionContext[3]; 989 U32 TransactionDetails[1]; 990 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96, 991 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t; 992 993 typedef struct _MPI2_SGE_TRANSACTION128 994 { 995 U8 Reserved; 996 U8 ContextSize; 997 U8 DetailsLength; 998 U8 Flags; 999 U32 TransactionContext[4]; 1000 U32 TransactionDetails[1]; 1001 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128, 1002 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128; 1003 1004 typedef struct _MPI2_SGE_TRANSACTION_UNION 1005 { 1006 U8 Reserved; 1007 U8 ContextSize; 1008 U8 DetailsLength; 1009 U8 Flags; 1010 union 1011 { 1012 U32 TransactionContext32[1]; 1013 U32 TransactionContext64[2]; 1014 U32 TransactionContext96[3]; 1015 U32 TransactionContext128[4]; 1016 } u; 1017 U32 TransactionDetails[1]; 1018 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION, 1019 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t; 1020 1021 /**************************************************************************** 1022 * MPI SGE union for IO SGL's - for MPI v2.0 products only 1023 ****************************************************************************/ 1024 1025 typedef struct _MPI2_MPI_SGE_IO_UNION 1026 { 1027 union 1028 { 1029 MPI2_SGE_SIMPLE_UNION Simple; 1030 MPI2_SGE_CHAIN_UNION Chain; 1031 } u; 1032 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION, 1033 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t; 1034 1035 /**************************************************************************** 1036 * MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only 1037 ****************************************************************************/ 1038 1039 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION 1040 { 1041 union 1042 { 1043 MPI2_SGE_SIMPLE_UNION Simple; 1044 MPI2_SGE_TRANSACTION_UNION Transaction; 1045 } u; 1046 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION, 1047 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t; 1048 1049 /**************************************************************************** 1050 * All MPI SGE types union 1051 ****************************************************************************/ 1052 1053 typedef struct _MPI2_MPI_SGE_UNION 1054 { 1055 union 1056 { 1057 MPI2_SGE_SIMPLE_UNION Simple; 1058 MPI2_SGE_CHAIN_UNION Chain; 1059 MPI2_SGE_TRANSACTION_UNION Transaction; 1060 } u; 1061 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION, 1062 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t; 1063 1064 /**************************************************************************** 1065 * MPI SGE field definition and masks 1066 ****************************************************************************/ 1067 1068 /* Flags field bit definitions */ 1069 1070 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) 1071 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) 1072 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 1073 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) 1074 #define MPI2_SGE_FLAGS_DIRECTION (0x04) 1075 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) 1076 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01) 1077 1078 #define MPI2_SGE_FLAGS_SHIFT (24) 1079 1080 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) 1081 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 1082 1083 /* Element Type */ 1084 1085 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) /* for MPI v2.0 products only */ 1086 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 1087 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) /* for MPI v2.0 products only */ 1088 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) 1089 1090 /* Address location */ 1091 1092 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 1093 1094 /* Direction */ 1095 1096 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) 1097 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) 1098 1099 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST) 1100 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC) 1101 1102 /* Address Size */ 1103 1104 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1105 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1106 1107 /* Context Size */ 1108 1109 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) 1110 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) 1111 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) 1112 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) 1113 1114 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 1115 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) 1116 1117 /**************************************************************************** 1118 * MPI SGE operation Macros 1119 ****************************************************************************/ 1120 1121 /* SIMPLE FlagsLength manipulations... */ 1122 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) 1123 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT) 1124 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) 1125 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) 1126 1127 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l)) 1128 1129 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) 1130 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) 1131 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l) 1132 1133 /* CAUTION - The following are READ-MODIFY-WRITE! */ 1134 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f) 1135 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l) 1136 1137 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT) 1138 1139 /***************************************************************************** 1140 * 1141 * Fusion-MPT IEEE Scatter Gather Elements 1142 * 1143 *****************************************************************************/ 1144 1145 /**************************************************************************** 1146 * IEEE Simple Element structures 1147 ****************************************************************************/ 1148 1149 /* MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */ 1150 typedef struct _MPI2_IEEE_SGE_SIMPLE32 1151 { 1152 U32 Address; 1153 U32 FlagsLength; 1154 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 1155 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 1156 1157 typedef struct _MPI2_IEEE_SGE_SIMPLE64 1158 { 1159 U64 Address; 1160 U32 Length; 1161 U16 Reserved1; 1162 U8 Reserved2; 1163 U8 Flags; 1164 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 1165 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 1166 1167 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION 1168 { 1169 MPI2_IEEE_SGE_SIMPLE32 Simple32; 1170 MPI2_IEEE_SGE_SIMPLE64 Simple64; 1171 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 1172 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 1173 1174 /**************************************************************************** 1175 * IEEE Chain Element structures 1176 ****************************************************************************/ 1177 1178 /* MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */ 1179 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 1180 1181 /* MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */ 1182 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 1183 1184 typedef union _MPI2_IEEE_SGE_CHAIN_UNION 1185 { 1186 MPI2_IEEE_SGE_CHAIN32 Chain32; 1187 MPI2_IEEE_SGE_CHAIN64 Chain64; 1188 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 1189 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 1190 1191 /* MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */ 1192 typedef struct _MPI25_IEEE_SGE_CHAIN64 1193 { 1194 U64 Address; 1195 U32 Length; 1196 U16 Reserved1; 1197 U8 NextChainOffset; 1198 U8 Flags; 1199 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, 1200 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t; 1201 1202 /**************************************************************************** 1203 * All IEEE SGE types union 1204 ****************************************************************************/ 1205 1206 /* MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */ 1207 typedef struct _MPI2_IEEE_SGE_UNION 1208 { 1209 union 1210 { 1211 MPI2_IEEE_SGE_SIMPLE_UNION Simple; 1212 MPI2_IEEE_SGE_CHAIN_UNION Chain; 1213 } u; 1214 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION, 1215 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t; 1216 1217 /**************************************************************************** 1218 * IEEE SGE union for IO SGL's 1219 ****************************************************************************/ 1220 1221 typedef union _MPI25_SGE_IO_UNION 1222 { 1223 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple; 1224 MPI25_IEEE_SGE_CHAIN64 IeeeChain; 1225 } MPI25_SGE_IO_UNION, MPI2_POINTER PTR_MPI25_SGE_IO_UNION, 1226 Mpi25SGEIOUnion_t, MPI2_POINTER pMpi25SGEIOUnion_t; 1227 1228 /**************************************************************************** 1229 * IEEE SGE field definitions and masks 1230 ****************************************************************************/ 1231 1232 /* Flags field bit definitions */ 1233 1234 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1235 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1236 1237 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1238 1239 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1240 1241 /* Element Type */ 1242 1243 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1244 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1245 1246 /* Next Segment Format */ 1247 1248 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C) 1249 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00) 1250 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08) 1251 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10) 1252 1253 /* Data Location Address Space */ 1254 1255 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1256 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5 and later, use in IEEE Simple or Chain element */ 1257 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* use in IEEE Simple Element only */ 1258 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1259 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5, use in IEEE Simple or Chain element */ 1260 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) /* use in MPI v2.0 IEEE Chain Element only */ 1261 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */ 1262 1263 #define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02) /* for MPI v2.6 only */ 1264 1265 /**************************************************************************** 1266 * IEEE SGE operation Macros 1267 ****************************************************************************/ 1268 1269 /* SIMPLE FlagsLength manipulations... */ 1270 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) 1271 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT) 1272 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) 1273 1274 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l)) 1275 1276 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) 1277 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) 1278 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l) 1279 1280 /* CAUTION - The following are READ-MODIFY-WRITE! */ 1281 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f) 1282 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l) 1283 1284 /***************************************************************************** 1285 * 1286 * Fusion-MPT MPI/IEEE Scatter Gather Unions 1287 * 1288 *****************************************************************************/ 1289 1290 typedef union _MPI2_SIMPLE_SGE_UNION 1291 { 1292 MPI2_SGE_SIMPLE_UNION MpiSimple; 1293 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1294 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION, 1295 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t; 1296 1297 typedef union _MPI2_SGE_IO_UNION 1298 { 1299 MPI2_SGE_SIMPLE_UNION MpiSimple; 1300 MPI2_SGE_CHAIN_UNION MpiChain; 1301 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1302 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1303 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 1304 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 1305 1306 /**************************************************************************** 1307 * 1308 * Values for SGLFlags field, used in many request messages with an SGL 1309 * 1310 ****************************************************************************/ 1311 1312 /* values for MPI SGL Data Location Address Space subfield */ 1313 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) 1314 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) 1315 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) 1316 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.5 and earlier */ 1317 #define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.6 */ 1318 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) /* only for MPI v2.5 and earlier */ 1319 /* values for SGL Type subfield */ 1320 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) 1321 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) 1322 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) /* MPI v2.0 products only */ 1323 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) 1324 1325 #endif 1326