1 /*- 2 * Copyright (c) 2012-2015 LSI Corp. 3 * Copyright (c) 2013-2016 Avago Technologies 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. Neither the name of the author nor the names of any co-contributors 15 * may be used to endorse or promote products derived from this software 16 * without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * Avago Technologies (LSI) MPT-Fusion Host Adapter FreeBSD 31 * 32 * $FreeBSD$ 33 */ 34 35 /* 36 * Copyright (c) 2000-2015 LSI Corporation. 37 * Copyright (c) 2013-2016 Avago Technologies 38 * All rights reserved. 39 * 40 * 41 * Name: mpi2.h 42 * Title: MPI Message independent structures and definitions 43 * including System Interface Register Set and 44 * scatter/gather formats. 45 * Creation Date: June 21, 2006 46 * 47 * mpi2.h Version: 02.00.48 48 * 49 * NOTE: Names (typedefs, defines, etc.) beginning with an MPI25 or Mpi25 50 * prefix are for use only on MPI v2.5 products, and must not be used 51 * with MPI v2.0 products. Unless otherwise noted, names beginning with 52 * MPI2 or Mpi2 are for use with both MPI v2.0 and MPI v2.5 products. 53 * 54 * Version History 55 * --------------- 56 * 57 * Date Version Description 58 * -------- -------- ------------------------------------------------------ 59 * 04-30-07 02.00.00 Corresponds to Fusion-MPT MPI Specification Rev A. 60 * 06-04-07 02.00.01 Bumped MPI2_HEADER_VERSION_UNIT. 61 * 06-26-07 02.00.02 Bumped MPI2_HEADER_VERSION_UNIT. 62 * 08-31-07 02.00.03 Bumped MPI2_HEADER_VERSION_UNIT. 63 * Moved ReplyPostHostIndex register to offset 0x6C of the 64 * MPI2_SYSTEM_INTERFACE_REGS and modified the define for 65 * MPI2_REPLY_POST_HOST_INDEX_OFFSET. 66 * Added union of request descriptors. 67 * Added union of reply descriptors. 68 * 10-31-07 02.00.04 Bumped MPI2_HEADER_VERSION_UNIT. 69 * Added define for MPI2_VERSION_02_00. 70 * Fixed the size of the FunctionDependent5 field in the 71 * MPI2_DEFAULT_REPLY structure. 72 * 12-18-07 02.00.05 Bumped MPI2_HEADER_VERSION_UNIT. 73 * Removed the MPI-defined Fault Codes and extended the 74 * product specific codes up to 0xEFFF. 75 * Added a sixth key value for the WriteSequence register 76 * and changed the flush value to 0x0. 77 * Added message function codes for Diagnostic Buffer Post 78 * and Diagnsotic Release. 79 * New IOCStatus define: MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED 80 * Moved MPI2_VERSION_UNION from mpi2_ioc.h. 81 * 02-29-08 02.00.06 Bumped MPI2_HEADER_VERSION_UNIT. 82 * 03-03-08 02.00.07 Bumped MPI2_HEADER_VERSION_UNIT. 83 * 05-21-08 02.00.08 Bumped MPI2_HEADER_VERSION_UNIT. 84 * Added #defines for marking a reply descriptor as unused. 85 * 06-27-08 02.00.09 Bumped MPI2_HEADER_VERSION_UNIT. 86 * 10-02-08 02.00.10 Bumped MPI2_HEADER_VERSION_UNIT. 87 * Moved LUN field defines from mpi2_init.h. 88 * 01-19-09 02.00.11 Bumped MPI2_HEADER_VERSION_UNIT. 89 * 05-06-09 02.00.12 Bumped MPI2_HEADER_VERSION_UNIT. 90 * In all request and reply descriptors, replaced VF_ID 91 * field with MSIxIndex field. 92 * Removed DevHandle field from 93 * MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR and made those 94 * bytes reserved. 95 * Added RAID Accelerator functionality. 96 * 07-30-09 02.00.13 Bumped MPI2_HEADER_VERSION_UNIT. 97 * 10-28-09 02.00.14 Bumped MPI2_HEADER_VERSION_UNIT. 98 * Added MSI-x index mask and shift for Reply Post Host 99 * Index register. 100 * Added function code for Host Based Discovery Action. 101 * 02-10-10 02.00.15 Bumped MPI2_HEADER_VERSION_UNIT. 102 * Added define for MPI2_FUNCTION_PWR_MGMT_CONTROL. 103 * Added defines for product-specific range of message 104 * function codes, 0xF0 to 0xFF. 105 * 05-12-10 02.00.16 Bumped MPI2_HEADER_VERSION_UNIT. 106 * Added alternative defines for the SGE Direction bit. 107 * 08-11-10 02.00.17 Bumped MPI2_HEADER_VERSION_UNIT. 108 * 11-10-10 02.00.18 Bumped MPI2_HEADER_VERSION_UNIT. 109 * Added MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR define. 110 * 02-23-11 02.00.19 Bumped MPI2_HEADER_VERSION_UNIT. 111 * Added MPI2_FUNCTION_SEND_HOST_MESSAGE. 112 * 03-09-11 02.00.20 Bumped MPI2_HEADER_VERSION_UNIT. 113 * 05-25-11 02.00.21 Bumped MPI2_HEADER_VERSION_UNIT. 114 * 08-24-11 02.00.22 Bumped MPI2_HEADER_VERSION_UNIT. 115 * 11-18-11 02.00.23 Bumped MPI2_HEADER_VERSION_UNIT. 116 * Incorporating additions for MPI v2.5. 117 * 02-06-12 02.00.24 Bumped MPI2_HEADER_VERSION_UNIT. 118 * 03-29-12 02.00.25 Bumped MPI2_HEADER_VERSION_UNIT. 119 * Added Hard Reset delay timings. 120 * 07-10-12 02.00.26 Bumped MPI2_HEADER_VERSION_UNIT. 121 * 07-26-12 02.00.27 Bumped MPI2_HEADER_VERSION_UNIT. 122 * 11-27-12 02.00.28 Bumped MPI2_HEADER_VERSION_UNIT. 123 * 12-20-12 02.00.29 Bumped MPI2_HEADER_VERSION_UNIT. 124 * Added MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET. 125 * 04-09-13 02.00.30 Bumped MPI2_HEADER_VERSION_UNIT. 126 * 04-17-13 02.00.31 Bumped MPI2_HEADER_VERSION_UNIT. 127 * 08-19-13 02.00.32 Bumped MPI2_HEADER_VERSION_UNIT. 128 * 12-05-13 02.00.33 Bumped MPI2_HEADER_VERSION_UNIT. 129 * 01-08-14 02.00.34 Bumped MPI2_HEADER_VERSION_UNIT. 130 * 06-13-14 02.00.35 Bumped MPI2_HEADER_VERSION_UNIT. 131 * 11-18-14 02.00.36 Updated copyright information. 132 * Bumped MPI2_HEADER_VERSION_UNIT. 133 * 03-16-15 02.00.37 Updated for MPI v2.6. 134 * Bumped MPI2_HEADER_VERSION_UNIT. 135 * Added Scratchpad registers and 136 * AtomicRequestDescriptorPost register to 137 * MPI2_SYSTEM_INTERFACE_REGS. 138 * Added MPI2_DIAG_SBR_RELOAD. 139 * Added MPI2_IOCSTATUS_INSUFFICIENT_POWER. 140 * 03-19-15 02.00.38 Bumped MPI2_HEADER_VERSION_UNIT. 141 * 05-25-15 02.00.39 Bumped MPI2_HEADER_VERSION_UNIT 142 * 08-25-15 02.00.40 Bumped MPI2_HEADER_VERSION_UNIT. 143 * Added V7 HostDiagnostic register defines 144 * 12-15-15 02.00.41 Bumped MPI_HEADER_VERSION_UNIT 145 * 01-01-16 02.00.42 Bumped MPI_HEADER_VERSION_UNIT 146 * 04-05-16 02.00.43 Modified MPI26_DIAG_BOOT_DEVICE_SELECT defines 147 * to be unique within first 32 characters. 148 * Removed AHCI support. 149 * Removed SOP support. 150 * Bumped MPI2_HEADER_VERSION_UNIT. 151 * 04-10-16 02.00.44 Bumped MPI2_HEADER_VERSION_UNIT. 152 * 07-06-16 02.00.45 Bumped MPI2_HEADER_VERSION_UNIT. 153 * 09-02-16 02.00.46 Bumped MPI2_HEADER_VERSION_UNIT. 154 * 11-23-16 02.00.47 Bumped MPI2_HEADER_VERSION_UNIT. 155 * 02-03-17 02.00.48 Bumped MPI2_HEADER_VERSION_UNIT. 156 * -------------------------------------------------------------------------- 157 */ 158 159 #ifndef MPI2_H 160 #define MPI2_H 161 162 163 /***************************************************************************** 164 * 165 * MPI Version Definitions 166 * 167 *****************************************************************************/ 168 169 #define MPI2_VERSION_MAJOR_MASK (0xFF00) 170 #define MPI2_VERSION_MAJOR_SHIFT (8) 171 #define MPI2_VERSION_MINOR_MASK (0x00FF) 172 #define MPI2_VERSION_MINOR_SHIFT (0) 173 174 /* major version for all MPI v2.x */ 175 #define MPI2_VERSION_MAJOR (0x02) 176 177 /* minor version for MPI v2.0 compatible products */ 178 #define MPI2_VERSION_MINOR (0x00) 179 #define MPI2_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 180 MPI2_VERSION_MINOR) 181 #define MPI2_VERSION_02_00 (0x0200) 182 183 184 /* minor version for MPI v2.5 compatible products */ 185 #define MPI25_VERSION_MINOR (0x05) 186 #define MPI25_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 187 MPI25_VERSION_MINOR) 188 #define MPI2_VERSION_02_05 (0x0205) 189 190 191 /* minor version for MPI v2.6 compatible products */ 192 #define MPI26_VERSION_MINOR (0x06) 193 #define MPI26_VERSION ((MPI2_VERSION_MAJOR << MPI2_VERSION_MAJOR_SHIFT) | \ 194 MPI26_VERSION_MINOR) 195 #define MPI2_VERSION_02_06 (0x0206) 196 197 198 /* Unit and Dev versioning for this MPI header set */ 199 #define MPI2_HEADER_VERSION_UNIT (0x30) 200 #define MPI2_HEADER_VERSION_DEV (0x00) 201 #define MPI2_HEADER_VERSION_UNIT_MASK (0xFF00) 202 #define MPI2_HEADER_VERSION_UNIT_SHIFT (8) 203 #define MPI2_HEADER_VERSION_DEV_MASK (0x00FF) 204 #define MPI2_HEADER_VERSION_DEV_SHIFT (0) 205 #define MPI2_HEADER_VERSION ((MPI2_HEADER_VERSION_UNIT << 8) | MPI2_HEADER_VERSION_DEV) 206 207 208 /***************************************************************************** 209 * 210 * IOC State Definitions 211 * 212 *****************************************************************************/ 213 214 #define MPI2_IOC_STATE_RESET (0x00000000) 215 #define MPI2_IOC_STATE_READY (0x10000000) 216 #define MPI2_IOC_STATE_OPERATIONAL (0x20000000) 217 #define MPI2_IOC_STATE_FAULT (0x40000000) 218 219 #define MPI2_IOC_STATE_MASK (0xF0000000) 220 #define MPI2_IOC_STATE_SHIFT (28) 221 222 /* Fault state range for prodcut specific codes */ 223 #define MPI2_FAULT_PRODUCT_SPECIFIC_MIN (0x0000) 224 #define MPI2_FAULT_PRODUCT_SPECIFIC_MAX (0xEFFF) 225 226 227 /***************************************************************************** 228 * 229 * System Interface Register Definitions 230 * 231 *****************************************************************************/ 232 233 typedef volatile struct _MPI2_SYSTEM_INTERFACE_REGS 234 { 235 U32 Doorbell; /* 0x00 */ 236 U32 WriteSequence; /* 0x04 */ 237 U32 HostDiagnostic; /* 0x08 */ 238 U32 Reserved1; /* 0x0C */ 239 U32 DiagRWData; /* 0x10 */ 240 U32 DiagRWAddressLow; /* 0x14 */ 241 U32 DiagRWAddressHigh; /* 0x18 */ 242 U32 Reserved2[5]; /* 0x1C */ 243 U32 HostInterruptStatus; /* 0x30 */ 244 U32 HostInterruptMask; /* 0x34 */ 245 U32 DCRData; /* 0x38 */ 246 U32 DCRAddress; /* 0x3C */ 247 U32 Reserved3[2]; /* 0x40 */ 248 U32 ReplyFreeHostIndex; /* 0x48 */ 249 U32 Reserved4[8]; /* 0x4C */ 250 U32 ReplyPostHostIndex; /* 0x6C */ 251 U32 Reserved5; /* 0x70 */ 252 U32 HCBSize; /* 0x74 */ 253 U32 HCBAddressLow; /* 0x78 */ 254 U32 HCBAddressHigh; /* 0x7C */ 255 U32 Reserved6[12]; /* 0x80 */ 256 U32 Scratchpad[4]; /* 0xB0 */ 257 U32 RequestDescriptorPostLow; /* 0xC0 */ 258 U32 RequestDescriptorPostHigh; /* 0xC4 */ 259 U32 AtomicRequestDescriptorPost;/* 0xC8 */ /* MPI v2.6 and later; reserved in earlier versions */ 260 U32 Reserved7[13]; /* 0xCC */ 261 } MPI2_SYSTEM_INTERFACE_REGS, MPI2_POINTER PTR_MPI2_SYSTEM_INTERFACE_REGS, 262 Mpi2SystemInterfaceRegs_t, MPI2_POINTER pMpi2SystemInterfaceRegs_t; 263 264 /* 265 * Defines for working with the Doorbell register. 266 */ 267 #define MPI2_DOORBELL_OFFSET (0x00000000) 268 269 /* IOC --> System values */ 270 #define MPI2_DOORBELL_USED (0x08000000) 271 #define MPI2_DOORBELL_WHO_INIT_MASK (0x07000000) 272 #define MPI2_DOORBELL_WHO_INIT_SHIFT (24) 273 #define MPI2_DOORBELL_FAULT_CODE_MASK (0x0000FFFF) 274 #define MPI2_DOORBELL_DATA_MASK (0x0000FFFF) 275 276 /* System --> IOC values */ 277 #define MPI2_DOORBELL_FUNCTION_MASK (0xFF000000) 278 #define MPI2_DOORBELL_FUNCTION_SHIFT (24) 279 #define MPI2_DOORBELL_ADD_DWORDS_MASK (0x00FF0000) 280 #define MPI2_DOORBELL_ADD_DWORDS_SHIFT (16) 281 282 283 /* 284 * Defines for the WriteSequence register 285 */ 286 #define MPI2_WRITE_SEQUENCE_OFFSET (0x00000004) 287 #define MPI2_WRSEQ_KEY_VALUE_MASK (0x0000000F) 288 #define MPI2_WRSEQ_FLUSH_KEY_VALUE (0x0) 289 #define MPI2_WRSEQ_1ST_KEY_VALUE (0xF) 290 #define MPI2_WRSEQ_2ND_KEY_VALUE (0x4) 291 #define MPI2_WRSEQ_3RD_KEY_VALUE (0xB) 292 #define MPI2_WRSEQ_4TH_KEY_VALUE (0x2) 293 #define MPI2_WRSEQ_5TH_KEY_VALUE (0x7) 294 #define MPI2_WRSEQ_6TH_KEY_VALUE (0xD) 295 296 /* 297 * Defines for the HostDiagnostic register 298 */ 299 #define MPI2_HOST_DIAGNOSTIC_OFFSET (0x00000008) 300 301 #define MPI2_DIAG_SBR_RELOAD (0x00002000) 302 303 #define MPI2_DIAG_BOOT_DEVICE_SELECT_MASK (0x00001800) 304 #define MPI2_DIAG_BOOT_DEVICE_SELECT_DEFAULT (0x00000000) 305 #define MPI2_DIAG_BOOT_DEVICE_SELECT_HCDW (0x00000800) 306 307 /* Defines for V7A/V7R HostDiagnostic Register */ 308 #define MPI26_DIAG_BOOT_DEVICE_SEL_64FLASH (0x00000000) 309 #define MPI26_DIAG_BOOT_DEVICE_SEL_64HCDW (0x00000800) 310 #define MPI26_DIAG_BOOT_DEVICE_SEL_32FLASH (0x00001000) 311 #define MPI26_DIAG_BOOT_DEVICE_SEL_32HCDW (0x00001800) 312 313 #define MPI2_DIAG_CLEAR_FLASH_BAD_SIG (0x00000400) 314 #define MPI2_DIAG_FORCE_HCB_ON_RESET (0x00000200) 315 #define MPI2_DIAG_HCB_MODE (0x00000100) 316 #define MPI2_DIAG_DIAG_WRITE_ENABLE (0x00000080) 317 #define MPI2_DIAG_FLASH_BAD_SIG (0x00000040) 318 #define MPI2_DIAG_RESET_HISTORY (0x00000020) 319 #define MPI2_DIAG_DIAG_RW_ENABLE (0x00000010) 320 #define MPI2_DIAG_RESET_ADAPTER (0x00000004) 321 #define MPI2_DIAG_HOLD_IOC_RESET (0x00000002) 322 323 /* 324 * Offsets for DiagRWData and address 325 */ 326 #define MPI2_DIAG_RW_DATA_OFFSET (0x00000010) 327 #define MPI2_DIAG_RW_ADDRESS_LOW_OFFSET (0x00000014) 328 #define MPI2_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00000018) 329 330 /* 331 * Defines for the HostInterruptStatus register 332 */ 333 #define MPI2_HOST_INTERRUPT_STATUS_OFFSET (0x00000030) 334 #define MPI2_HIS_SYS2IOC_DB_STATUS (0x80000000) 335 #define MPI2_HIS_IOP_DOORBELL_STATUS MPI2_HIS_SYS2IOC_DB_STATUS 336 #define MPI2_HIS_RESET_IRQ_STATUS (0x40000000) 337 #define MPI2_HIS_REPLY_DESCRIPTOR_INTERRUPT (0x00000008) 338 #define MPI2_HIS_IOC2SYS_DB_STATUS (0x00000001) 339 #define MPI2_HIS_DOORBELL_INTERRUPT MPI2_HIS_IOC2SYS_DB_STATUS 340 341 /* 342 * Defines for the HostInterruptMask register 343 */ 344 #define MPI2_HOST_INTERRUPT_MASK_OFFSET (0x00000034) 345 #define MPI2_HIM_RESET_IRQ_MASK (0x40000000) 346 #define MPI2_HIM_REPLY_INT_MASK (0x00000008) 347 #define MPI2_HIM_RIM MPI2_HIM_REPLY_INT_MASK 348 #define MPI2_HIM_IOC2SYS_DB_MASK (0x00000001) 349 #define MPI2_HIM_DIM MPI2_HIM_IOC2SYS_DB_MASK 350 351 /* 352 * Offsets for DCRData and address 353 */ 354 #define MPI2_DCR_DATA_OFFSET (0x00000038) 355 #define MPI2_DCR_ADDRESS_OFFSET (0x0000003C) 356 357 /* 358 * Offset for the Reply Free Queue 359 */ 360 #define MPI2_REPLY_FREE_HOST_INDEX_OFFSET (0x00000048) 361 362 /* 363 * Defines for the Reply Descriptor Post Queue 364 */ 365 #define MPI2_REPLY_POST_HOST_INDEX_OFFSET (0x0000006C) 366 #define MPI2_REPLY_POST_HOST_INDEX_MASK (0x00FFFFFF) 367 #define MPI2_RPHI_MSIX_INDEX_MASK (0xFF000000) 368 #define MPI2_RPHI_MSIX_INDEX_SHIFT (24) 369 #define MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET (0x0000030C) /* MPI v2.5 only */ 370 371 372 /* 373 * Defines for the HCBSize and address 374 */ 375 #define MPI2_HCB_SIZE_OFFSET (0x00000074) 376 #define MPI2_HCB_SIZE_SIZE_MASK (0xFFFFF000) 377 #define MPI2_HCB_SIZE_HCB_ENABLE (0x00000001) 378 379 #define MPI2_HCB_ADDRESS_LOW_OFFSET (0x00000078) 380 #define MPI2_HCB_ADDRESS_HIGH_OFFSET (0x0000007C) 381 382 /* 383 * Offsets for the Scratchpad registers 384 */ 385 #define MPI26_SCRATCHPAD0_OFFSET (0x000000B0) 386 #define MPI26_SCRATCHPAD1_OFFSET (0x000000B4) 387 #define MPI26_SCRATCHPAD2_OFFSET (0x000000B8) 388 #define MPI26_SCRATCHPAD3_OFFSET (0x000000BC) 389 390 /* 391 * Offsets for the Request Descriptor Post Queue 392 */ 393 #define MPI2_REQUEST_DESCRIPTOR_POST_LOW_OFFSET (0x000000C0) 394 #define MPI2_REQUEST_DESCRIPTOR_POST_HIGH_OFFSET (0x000000C4) 395 #define MPI26_ATOMIC_REQUEST_DESCRIPTOR_POST_OFFSET (0x000000C8) 396 397 398 /* Hard Reset delay timings */ 399 #define MPI2_HARD_RESET_PCIE_FIRST_READ_DELAY_MICRO_SEC (50000) 400 #define MPI2_HARD_RESET_PCIE_RESET_READ_WINDOW_MICRO_SEC (255000) 401 #define MPI2_HARD_RESET_PCIE_SECOND_READ_DELAY_MICRO_SEC (256000) 402 403 /***************************************************************************** 404 * 405 * Message Descriptors 406 * 407 *****************************************************************************/ 408 409 /* Request Descriptors */ 410 411 /* Default Request Descriptor */ 412 typedef struct _MPI2_DEFAULT_REQUEST_DESCRIPTOR 413 { 414 U8 RequestFlags; /* 0x00 */ 415 U8 MSIxIndex; /* 0x01 */ 416 U16 SMID; /* 0x02 */ 417 U16 LMID; /* 0x04 */ 418 U16 DescriptorTypeDependent; /* 0x06 */ 419 } MPI2_DEFAULT_REQUEST_DESCRIPTOR, 420 MPI2_POINTER PTR_MPI2_DEFAULT_REQUEST_DESCRIPTOR, 421 Mpi2DefaultRequestDescriptor_t, MPI2_POINTER pMpi2DefaultRequestDescriptor_t; 422 423 /* defines for the RequestFlags field */ 424 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_MASK (0x1E) 425 #define MPI2_REQ_DESCRIPT_FLAGS_TYPE_RSHIFT (1) /* use carefully; values below are pre-shifted left */ 426 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO (0x00) 427 #define MPI2_REQ_DESCRIPT_FLAGS_SCSI_TARGET (0x02) 428 #define MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY (0x06) 429 #define MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE (0x08) 430 #define MPI2_REQ_DESCRIPT_FLAGS_RAID_ACCELERATOR (0x0A) 431 #define MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO (0x0C) 432 #define MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED (0x10) 433 434 #define MPI2_REQ_DESCRIPT_FLAGS_IOC_FIFO_MARKER (0x01) 435 436 437 /* High Priority Request Descriptor */ 438 typedef struct _MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR 439 { 440 U8 RequestFlags; /* 0x00 */ 441 U8 MSIxIndex; /* 0x01 */ 442 U16 SMID; /* 0x02 */ 443 U16 LMID; /* 0x04 */ 444 U16 Reserved1; /* 0x06 */ 445 } MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 446 MPI2_POINTER PTR_MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR, 447 Mpi2HighPriorityRequestDescriptor_t, 448 MPI2_POINTER pMpi2HighPriorityRequestDescriptor_t; 449 450 451 /* SCSI IO Request Descriptor */ 452 typedef struct _MPI2_SCSI_IO_REQUEST_DESCRIPTOR 453 { 454 U8 RequestFlags; /* 0x00 */ 455 U8 MSIxIndex; /* 0x01 */ 456 U16 SMID; /* 0x02 */ 457 U16 LMID; /* 0x04 */ 458 U16 DevHandle; /* 0x06 */ 459 } MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 460 MPI2_POINTER PTR_MPI2_SCSI_IO_REQUEST_DESCRIPTOR, 461 Mpi2SCSIIORequestDescriptor_t, MPI2_POINTER pMpi2SCSIIORequestDescriptor_t; 462 463 464 /* SCSI Target Request Descriptor */ 465 typedef struct _MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR 466 { 467 U8 RequestFlags; /* 0x00 */ 468 U8 MSIxIndex; /* 0x01 */ 469 U16 SMID; /* 0x02 */ 470 U16 LMID; /* 0x04 */ 471 U16 IoIndex; /* 0x06 */ 472 } MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 473 MPI2_POINTER PTR_MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR, 474 Mpi2SCSITargetRequestDescriptor_t, 475 MPI2_POINTER pMpi2SCSITargetRequestDescriptor_t; 476 477 478 /* RAID Accelerator Request Descriptor */ 479 typedef struct _MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR 480 { 481 U8 RequestFlags; /* 0x00 */ 482 U8 MSIxIndex; /* 0x01 */ 483 U16 SMID; /* 0x02 */ 484 U16 LMID; /* 0x04 */ 485 U16 Reserved; /* 0x06 */ 486 } MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 487 MPI2_POINTER PTR_MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR, 488 Mpi2RAIDAcceleratorRequestDescriptor_t, 489 MPI2_POINTER pMpi2RAIDAcceleratorRequestDescriptor_t; 490 491 492 /* Fast Path SCSI IO Request Descriptor */ 493 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR 494 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 495 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR, 496 Mpi25FastPathSCSIIORequestDescriptor_t, 497 MPI2_POINTER pMpi25FastPathSCSIIORequestDescriptor_t; 498 499 500 /* PCIe Encapsulated Request Descriptor */ 501 typedef MPI2_SCSI_IO_REQUEST_DESCRIPTOR 502 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR, 503 MPI2_POINTER PTR_MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR, 504 Mpi26PCIeEncapsulatedRequestDescriptor_t, 505 MPI2_POINTER pMpi26PCIeEncapsulatedRequestDescriptor_t; 506 507 508 /* union of Request Descriptors */ 509 typedef union _MPI2_REQUEST_DESCRIPTOR_UNION 510 { 511 MPI2_DEFAULT_REQUEST_DESCRIPTOR Default; 512 MPI2_HIGH_PRIORITY_REQUEST_DESCRIPTOR HighPriority; 513 MPI2_SCSI_IO_REQUEST_DESCRIPTOR SCSIIO; 514 MPI2_SCSI_TARGET_REQUEST_DESCRIPTOR SCSITarget; 515 MPI2_RAID_ACCEL_REQUEST_DESCRIPTOR RAIDAccelerator; 516 MPI25_FP_SCSI_IO_REQUEST_DESCRIPTOR FastPathSCSIIO; 517 MPI26_PCIE_ENCAPSULATED_REQUEST_DESCRIPTOR PCIeEncapsulated; 518 U64 Words; 519 } MPI2_REQUEST_DESCRIPTOR_UNION, MPI2_POINTER PTR_MPI2_REQUEST_DESCRIPTOR_UNION, 520 Mpi2RequestDescriptorUnion_t, MPI2_POINTER pMpi2RequestDescriptorUnion_t; 521 522 523 /* Atomic Request Descriptors */ 524 525 /* 526 * All Atomic Request Descriptors have the same format, so the following 527 * structure is used for all Atomic Request Descriptors: 528 * Atomic Default Request Descriptor 529 * Atomic High Priority Request Descriptor 530 * Atomic SCSI IO Request Descriptor 531 * Atomic SCSI Target Request Descriptor 532 * Atomic RAID Accelerator Request Descriptor 533 * Atomic Fast Path SCSI IO Request Descriptor 534 * Atomic PCIe Encapsulated Request Descriptor 535 */ 536 537 /* Atomic Request Descriptor */ 538 typedef struct _MPI26_ATOMIC_REQUEST_DESCRIPTOR 539 { 540 U8 RequestFlags; /* 0x00 */ 541 U8 MSIxIndex; /* 0x01 */ 542 U16 SMID; /* 0x02 */ 543 } MPI26_ATOMIC_REQUEST_DESCRIPTOR, 544 MPI2_POINTER PTR_MPI26_ATOMIC_REQUEST_DESCRIPTOR, 545 Mpi26AtomicRequestDescriptor_t, MPI2_POINTER pMpi26AtomicRequestDescriptor_t; 546 547 /* for the RequestFlags field, use the same defines as MPI2_DEFAULT_REQUEST_DESCRIPTOR */ 548 549 550 /* Reply Descriptors */ 551 552 /* Default Reply Descriptor */ 553 typedef struct _MPI2_DEFAULT_REPLY_DESCRIPTOR 554 { 555 U8 ReplyFlags; /* 0x00 */ 556 U8 MSIxIndex; /* 0x01 */ 557 U16 DescriptorTypeDependent1; /* 0x02 */ 558 U32 DescriptorTypeDependent2; /* 0x04 */ 559 } MPI2_DEFAULT_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY_DESCRIPTOR, 560 Mpi2DefaultReplyDescriptor_t, MPI2_POINTER pMpi2DefaultReplyDescriptor_t; 561 562 /* defines for the ReplyFlags field */ 563 #define MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK (0x0F) 564 #define MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS (0x00) 565 #define MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY (0x01) 566 #define MPI2_RPY_DESCRIPT_FLAGS_TARGETASSIST_SUCCESS (0x02) 567 #define MPI2_RPY_DESCRIPT_FLAGS_TARGET_COMMAND_BUFFER (0x03) 568 #define MPI2_RPY_DESCRIPT_FLAGS_RAID_ACCELERATOR_SUCCESS (0x05) 569 #define MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS (0x06) 570 #define MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS (0x08) 571 #define MPI2_RPY_DESCRIPT_FLAGS_UNUSED (0x0F) 572 573 /* values for marking a reply descriptor as unused */ 574 #define MPI2_RPY_DESCRIPT_UNUSED_WORD0_MARK (0xFFFFFFFF) 575 #define MPI2_RPY_DESCRIPT_UNUSED_WORD1_MARK (0xFFFFFFFF) 576 577 /* Address Reply Descriptor */ 578 typedef struct _MPI2_ADDRESS_REPLY_DESCRIPTOR 579 { 580 U8 ReplyFlags; /* 0x00 */ 581 U8 MSIxIndex; /* 0x01 */ 582 U16 SMID; /* 0x02 */ 583 U32 ReplyFrameAddress; /* 0x04 */ 584 } MPI2_ADDRESS_REPLY_DESCRIPTOR, MPI2_POINTER PTR_MPI2_ADDRESS_REPLY_DESCRIPTOR, 585 Mpi2AddressReplyDescriptor_t, MPI2_POINTER pMpi2AddressReplyDescriptor_t; 586 587 #define MPI2_ADDRESS_REPLY_SMID_INVALID (0x00) 588 589 590 /* SCSI IO Success Reply Descriptor */ 591 typedef struct _MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 592 { 593 U8 ReplyFlags; /* 0x00 */ 594 U8 MSIxIndex; /* 0x01 */ 595 U16 SMID; /* 0x02 */ 596 U16 TaskTag; /* 0x04 */ 597 U16 Reserved1; /* 0x06 */ 598 } MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 599 MPI2_POINTER PTR_MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 600 Mpi2SCSIIOSuccessReplyDescriptor_t, 601 MPI2_POINTER pMpi2SCSIIOSuccessReplyDescriptor_t; 602 603 604 /* TargetAssist Success Reply Descriptor */ 605 typedef struct _MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR 606 { 607 U8 ReplyFlags; /* 0x00 */ 608 U8 MSIxIndex; /* 0x01 */ 609 U16 SMID; /* 0x02 */ 610 U8 SequenceNumber; /* 0x04 */ 611 U8 Reserved1; /* 0x05 */ 612 U16 IoIndex; /* 0x06 */ 613 } MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 614 MPI2_POINTER PTR_MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR, 615 Mpi2TargetAssistSuccessReplyDescriptor_t, 616 MPI2_POINTER pMpi2TargetAssistSuccessReplyDescriptor_t; 617 618 619 /* Target Command Buffer Reply Descriptor */ 620 typedef struct _MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 621 { 622 U8 ReplyFlags; /* 0x00 */ 623 U8 MSIxIndex; /* 0x01 */ 624 U8 VP_ID; /* 0x02 */ 625 U8 Flags; /* 0x03 */ 626 U16 InitiatorDevHandle; /* 0x04 */ 627 U16 IoIndex; /* 0x06 */ 628 } MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 629 MPI2_POINTER PTR_MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 630 Mpi2TargetCommandBufferReplyDescriptor_t, 631 MPI2_POINTER pMpi2TargetCommandBufferReplyDescriptor_t; 632 633 /* defines for Flags field */ 634 #define MPI2_RPY_DESCRIPT_TCB_FLAGS_PHYNUM_MASK (0x3F) 635 636 637 /* RAID Accelerator Success Reply Descriptor */ 638 typedef struct _MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 639 { 640 U8 ReplyFlags; /* 0x00 */ 641 U8 MSIxIndex; /* 0x01 */ 642 U16 SMID; /* 0x02 */ 643 U32 Reserved; /* 0x04 */ 644 } MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 645 MPI2_POINTER PTR_MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR, 646 Mpi2RAIDAcceleratorSuccessReplyDescriptor_t, 647 MPI2_POINTER pMpi2RAIDAcceleratorSuccessReplyDescriptor_t; 648 649 650 /* Fast Path SCSI IO Success Reply Descriptor */ 651 typedef MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR 652 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 653 MPI2_POINTER PTR_MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR, 654 Mpi25FastPathSCSIIOSuccessReplyDescriptor_t, 655 MPI2_POINTER pMpi25FastPathSCSIIOSuccessReplyDescriptor_t; 656 657 658 /* PCIe Encapsulated Success Reply Descriptor */ 659 typedef MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR 660 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR, 661 MPI2_POINTER PTR_MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR, 662 Mpi26PCIeEncapsulatedSuccessReplyDescriptor_t, 663 MPI2_POINTER pMpi26PCIeEncapsulatedSuccessReplyDescriptor_t; 664 665 666 /* union of Reply Descriptors */ 667 typedef union _MPI2_REPLY_DESCRIPTORS_UNION 668 { 669 MPI2_DEFAULT_REPLY_DESCRIPTOR Default; 670 MPI2_ADDRESS_REPLY_DESCRIPTOR AddressReply; 671 MPI2_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR SCSIIOSuccess; 672 MPI2_TARGETASSIST_SUCCESS_REPLY_DESCRIPTOR TargetAssistSuccess; 673 MPI2_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 674 MPI2_RAID_ACCELERATOR_SUCCESS_REPLY_DESCRIPTOR RAIDAcceleratorSuccess; 675 MPI25_FP_SCSI_IO_SUCCESS_REPLY_DESCRIPTOR FastPathSCSIIOSuccess; 676 MPI26_PCIE_ENCAPSULATED_SUCCESS_REPLY_DESCRIPTOR PCIeEncapsulatedSuccess; 677 U64 Words; 678 } MPI2_REPLY_DESCRIPTORS_UNION, MPI2_POINTER PTR_MPI2_REPLY_DESCRIPTORS_UNION, 679 Mpi2ReplyDescriptorsUnion_t, MPI2_POINTER pMpi2ReplyDescriptorsUnion_t; 680 681 682 683 /***************************************************************************** 684 * 685 * Message Functions 686 * 687 *****************************************************************************/ 688 689 #define MPI2_FUNCTION_SCSI_IO_REQUEST (0x00) /* SCSI IO */ 690 #define MPI2_FUNCTION_SCSI_TASK_MGMT (0x01) /* SCSI Task Management */ 691 #define MPI2_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 692 #define MPI2_FUNCTION_IOC_FACTS (0x03) /* IOC Facts */ 693 #define MPI2_FUNCTION_CONFIG (0x04) /* Configuration */ 694 #define MPI2_FUNCTION_PORT_FACTS (0x05) /* Port Facts */ 695 #define MPI2_FUNCTION_PORT_ENABLE (0x06) /* Port Enable */ 696 #define MPI2_FUNCTION_EVENT_NOTIFICATION (0x07) /* Event Notification */ 697 #define MPI2_FUNCTION_EVENT_ACK (0x08) /* Event Acknowledge */ 698 #define MPI2_FUNCTION_FW_DOWNLOAD (0x09) /* FW Download */ 699 #define MPI2_FUNCTION_TARGET_ASSIST (0x0B) /* Target Assist */ 700 #define MPI2_FUNCTION_TARGET_STATUS_SEND (0x0C) /* Target Status Send */ 701 #define MPI2_FUNCTION_TARGET_MODE_ABORT (0x0D) /* Target Mode Abort */ 702 #define MPI2_FUNCTION_FW_UPLOAD (0x12) /* FW Upload */ 703 #define MPI2_FUNCTION_RAID_ACTION (0x15) /* RAID Action */ 704 #define MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH (0x16) /* SCSI IO RAID Passthrough */ 705 #define MPI2_FUNCTION_TOOLBOX (0x17) /* Toolbox */ 706 #define MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR (0x18) /* SCSI Enclosure Processor */ 707 #define MPI2_FUNCTION_SMP_PASSTHROUGH (0x1A) /* SMP Passthrough */ 708 #define MPI2_FUNCTION_SAS_IO_UNIT_CONTROL (0x1B) /* SAS IO Unit Control */ /* for MPI v2.5 and earlier */ 709 #define MPI2_FUNCTION_IO_UNIT_CONTROL (0x1B) /* IO Unit Control */ /* for MPI v2.6 and later */ 710 #define MPI2_FUNCTION_SATA_PASSTHROUGH (0x1C) /* SATA Passthrough */ 711 #define MPI2_FUNCTION_DIAG_BUFFER_POST (0x1D) /* Diagnostic Buffer Post */ 712 #define MPI2_FUNCTION_DIAG_RELEASE (0x1E) /* Diagnostic Release */ 713 #define MPI2_FUNCTION_TARGET_CMD_BUF_BASE_POST (0x24) /* Target Command Buffer Post Base */ 714 #define MPI2_FUNCTION_TARGET_CMD_BUF_LIST_POST (0x25) /* Target Command Buffer Post List */ 715 #define MPI2_FUNCTION_RAID_ACCELERATOR (0x2C) /* RAID Accelerator */ 716 #define MPI2_FUNCTION_HOST_BASED_DISCOVERY_ACTION (0x2F) /* Host Based Discovery Action */ 717 #define MPI2_FUNCTION_PWR_MGMT_CONTROL (0x30) /* Power Management Control */ 718 #define MPI2_FUNCTION_SEND_HOST_MESSAGE (0x31) /* Send Host Message */ 719 #define MPI2_FUNCTION_NVME_ENCAPSULATED (0x33) /* NVMe Encapsulated (MPI v2.6) */ 720 #define MPI2_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* beginning of product-specific range */ 721 #define MPI2_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* end of product-specific range */ 722 723 724 725 /* Doorbell functions */ 726 #define MPI2_FUNCTION_IOC_MESSAGE_UNIT_RESET (0x40) 727 #define MPI2_FUNCTION_HANDSHAKE (0x42) 728 729 730 /***************************************************************************** 731 * 732 * IOC Status Values 733 * 734 *****************************************************************************/ 735 736 /* mask for IOCStatus status value */ 737 #define MPI2_IOCSTATUS_MASK (0x7FFF) 738 739 /**************************************************************************** 740 * Common IOCStatus values for all replies 741 ****************************************************************************/ 742 743 #define MPI2_IOCSTATUS_SUCCESS (0x0000) 744 #define MPI2_IOCSTATUS_INVALID_FUNCTION (0x0001) 745 #define MPI2_IOCSTATUS_BUSY (0x0002) 746 #define MPI2_IOCSTATUS_INVALID_SGL (0x0003) 747 #define MPI2_IOCSTATUS_INTERNAL_ERROR (0x0004) 748 #define MPI2_IOCSTATUS_INVALID_VPID (0x0005) 749 #define MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 750 #define MPI2_IOCSTATUS_INVALID_FIELD (0x0007) 751 #define MPI2_IOCSTATUS_INVALID_STATE (0x0008) 752 #define MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED (0x0009) 753 #define MPI2_IOCSTATUS_INSUFFICIENT_POWER (0x000A) /* MPI v2.6 and later */ 754 755 /**************************************************************************** 756 * Config IOCStatus values 757 ****************************************************************************/ 758 759 #define MPI2_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 760 #define MPI2_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 761 #define MPI2_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 762 #define MPI2_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 763 #define MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 764 #define MPI2_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 765 766 /**************************************************************************** 767 * SCSI IO Reply 768 ****************************************************************************/ 769 770 #define MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 771 #define MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 772 #define MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 773 #define MPI2_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 774 #define MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 775 #define MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 776 #define MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 777 #define MPI2_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 778 #define MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 779 #define MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 780 #define MPI2_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 781 #define MPI2_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 782 783 /**************************************************************************** 784 * For use by SCSI Initiator and SCSI Target end-to-end data protection 785 ****************************************************************************/ 786 787 #define MPI2_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 788 #define MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 789 #define MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 790 791 /**************************************************************************** 792 * SCSI Target values 793 ****************************************************************************/ 794 795 #define MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 796 #define MPI2_IOCSTATUS_TARGET_ABORTED (0x0063) 797 #define MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 798 #define MPI2_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 799 #define MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 800 #define MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 801 #define MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 802 #define MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 803 #define MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 804 #define MPI2_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 805 806 /**************************************************************************** 807 * Serial Attached SCSI values 808 ****************************************************************************/ 809 810 #define MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 811 #define MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 812 813 /**************************************************************************** 814 * Diagnostic Buffer Post / Diagnostic Release values 815 ****************************************************************************/ 816 817 #define MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 818 819 /**************************************************************************** 820 * RAID Accelerator values 821 ****************************************************************************/ 822 823 #define MPI2_IOCSTATUS_RAID_ACCEL_ERROR (0x00B0) 824 825 /**************************************************************************** 826 * IOCStatus flag to indicate that log info is available 827 ****************************************************************************/ 828 829 #define MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE (0x8000) 830 831 /**************************************************************************** 832 * IOCLogInfo Types 833 ****************************************************************************/ 834 835 #define MPI2_IOCLOGINFO_TYPE_MASK (0xF0000000) 836 #define MPI2_IOCLOGINFO_TYPE_SHIFT (28) 837 #define MPI2_IOCLOGINFO_TYPE_NONE (0x0) 838 #define MPI2_IOCLOGINFO_TYPE_SCSI (0x1) 839 #define MPI2_IOCLOGINFO_TYPE_FC (0x2) 840 #define MPI2_IOCLOGINFO_TYPE_SAS (0x3) 841 #define MPI2_IOCLOGINFO_TYPE_ISCSI (0x4) 842 #define MPI2_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 843 844 845 /***************************************************************************** 846 * 847 * Standard Message Structures 848 * 849 *****************************************************************************/ 850 851 /**************************************************************************** 852 * Request Message Header for all request messages 853 ****************************************************************************/ 854 855 typedef struct _MPI2_REQUEST_HEADER 856 { 857 U16 FunctionDependent1; /* 0x00 */ 858 U8 ChainOffset; /* 0x02 */ 859 U8 Function; /* 0x03 */ 860 U16 FunctionDependent2; /* 0x04 */ 861 U8 FunctionDependent3; /* 0x06 */ 862 U8 MsgFlags; /* 0x07 */ 863 U8 VP_ID; /* 0x08 */ 864 U8 VF_ID; /* 0x09 */ 865 U16 Reserved1; /* 0x0A */ 866 } MPI2_REQUEST_HEADER, MPI2_POINTER PTR_MPI2_REQUEST_HEADER, 867 MPI2RequestHeader_t, MPI2_POINTER pMPI2RequestHeader_t; 868 869 870 /**************************************************************************** 871 * Default Reply 872 ****************************************************************************/ 873 874 typedef struct _MPI2_DEFAULT_REPLY 875 { 876 U16 FunctionDependent1; /* 0x00 */ 877 U8 MsgLength; /* 0x02 */ 878 U8 Function; /* 0x03 */ 879 U16 FunctionDependent2; /* 0x04 */ 880 U8 FunctionDependent3; /* 0x06 */ 881 U8 MsgFlags; /* 0x07 */ 882 U8 VP_ID; /* 0x08 */ 883 U8 VF_ID; /* 0x09 */ 884 U16 Reserved1; /* 0x0A */ 885 U16 FunctionDependent5; /* 0x0C */ 886 U16 IOCStatus; /* 0x0E */ 887 U32 IOCLogInfo; /* 0x10 */ 888 } MPI2_DEFAULT_REPLY, MPI2_POINTER PTR_MPI2_DEFAULT_REPLY, 889 MPI2DefaultReply_t, MPI2_POINTER pMPI2DefaultReply_t; 890 891 892 /* common version structure/union used in messages and configuration pages */ 893 894 typedef struct _MPI2_VERSION_STRUCT 895 { 896 U8 Dev; /* 0x00 */ 897 U8 Unit; /* 0x01 */ 898 U8 Minor; /* 0x02 */ 899 U8 Major; /* 0x03 */ 900 } MPI2_VERSION_STRUCT; 901 902 typedef union _MPI2_VERSION_UNION 903 { 904 MPI2_VERSION_STRUCT Struct; 905 U32 Word; 906 } MPI2_VERSION_UNION; 907 908 909 /* LUN field defines, common to many structures */ 910 #define MPI2_LUN_FIRST_LEVEL_ADDRESSING (0x0000FFFF) 911 #define MPI2_LUN_SECOND_LEVEL_ADDRESSING (0xFFFF0000) 912 #define MPI2_LUN_THIRD_LEVEL_ADDRESSING (0x0000FFFF) 913 #define MPI2_LUN_FOURTH_LEVEL_ADDRESSING (0xFFFF0000) 914 #define MPI2_LUN_LEVEL_1_WORD (0xFF00) 915 #define MPI2_LUN_LEVEL_1_DWORD (0x0000FF00) 916 917 918 /***************************************************************************** 919 * 920 * Fusion-MPT MPI Scatter Gather Elements 921 * 922 *****************************************************************************/ 923 924 /**************************************************************************** 925 * MPI Simple Element structures 926 ****************************************************************************/ 927 928 typedef struct _MPI2_SGE_SIMPLE32 929 { 930 U32 FlagsLength; 931 U32 Address; 932 } MPI2_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_SGE_SIMPLE32, 933 Mpi2SGESimple32_t, MPI2_POINTER pMpi2SGESimple32_t; 934 935 typedef struct _MPI2_SGE_SIMPLE64 936 { 937 U32 FlagsLength; 938 U64 Address; 939 } MPI2_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_SGE_SIMPLE64, 940 Mpi2SGESimple64_t, MPI2_POINTER pMpi2SGESimple64_t; 941 942 typedef struct _MPI2_SGE_SIMPLE_UNION 943 { 944 U32 FlagsLength; 945 union 946 { 947 U32 Address32; 948 U64 Address64; 949 } u; 950 } MPI2_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_SIMPLE_UNION, 951 Mpi2SGESimpleUnion_t, MPI2_POINTER pMpi2SGESimpleUnion_t; 952 953 954 /**************************************************************************** 955 * MPI Chain Element structures - for MPI v2.0 products only 956 ****************************************************************************/ 957 958 typedef struct _MPI2_SGE_CHAIN32 959 { 960 U16 Length; 961 U8 NextChainOffset; 962 U8 Flags; 963 U32 Address; 964 } MPI2_SGE_CHAIN32, MPI2_POINTER PTR_MPI2_SGE_CHAIN32, 965 Mpi2SGEChain32_t, MPI2_POINTER pMpi2SGEChain32_t; 966 967 typedef struct _MPI2_SGE_CHAIN64 968 { 969 U16 Length; 970 U8 NextChainOffset; 971 U8 Flags; 972 U64 Address; 973 } MPI2_SGE_CHAIN64, MPI2_POINTER PTR_MPI2_SGE_CHAIN64, 974 Mpi2SGEChain64_t, MPI2_POINTER pMpi2SGEChain64_t; 975 976 typedef struct _MPI2_SGE_CHAIN_UNION 977 { 978 U16 Length; 979 U8 NextChainOffset; 980 U8 Flags; 981 union 982 { 983 U32 Address32; 984 U64 Address64; 985 } u; 986 } MPI2_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_SGE_CHAIN_UNION, 987 Mpi2SGEChainUnion_t, MPI2_POINTER pMpi2SGEChainUnion_t; 988 989 990 /**************************************************************************** 991 * MPI Transaction Context Element structures - for MPI v2.0 products only 992 ****************************************************************************/ 993 994 typedef struct _MPI2_SGE_TRANSACTION32 995 { 996 U8 Reserved; 997 U8 ContextSize; 998 U8 DetailsLength; 999 U8 Flags; 1000 U32 TransactionContext[1]; 1001 U32 TransactionDetails[1]; 1002 } MPI2_SGE_TRANSACTION32, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION32, 1003 Mpi2SGETransaction32_t, MPI2_POINTER pMpi2SGETransaction32_t; 1004 1005 typedef struct _MPI2_SGE_TRANSACTION64 1006 { 1007 U8 Reserved; 1008 U8 ContextSize; 1009 U8 DetailsLength; 1010 U8 Flags; 1011 U32 TransactionContext[2]; 1012 U32 TransactionDetails[1]; 1013 } MPI2_SGE_TRANSACTION64, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION64, 1014 Mpi2SGETransaction64_t, MPI2_POINTER pMpi2SGETransaction64_t; 1015 1016 typedef struct _MPI2_SGE_TRANSACTION96 1017 { 1018 U8 Reserved; 1019 U8 ContextSize; 1020 U8 DetailsLength; 1021 U8 Flags; 1022 U32 TransactionContext[3]; 1023 U32 TransactionDetails[1]; 1024 } MPI2_SGE_TRANSACTION96, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION96, 1025 Mpi2SGETransaction96_t, MPI2_POINTER pMpi2SGETransaction96_t; 1026 1027 typedef struct _MPI2_SGE_TRANSACTION128 1028 { 1029 U8 Reserved; 1030 U8 ContextSize; 1031 U8 DetailsLength; 1032 U8 Flags; 1033 U32 TransactionContext[4]; 1034 U32 TransactionDetails[1]; 1035 } MPI2_SGE_TRANSACTION128, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION128, 1036 Mpi2SGETransaction_t128, MPI2_POINTER pMpi2SGETransaction_t128; 1037 1038 typedef struct _MPI2_SGE_TRANSACTION_UNION 1039 { 1040 U8 Reserved; 1041 U8 ContextSize; 1042 U8 DetailsLength; 1043 U8 Flags; 1044 union 1045 { 1046 U32 TransactionContext32[1]; 1047 U32 TransactionContext64[2]; 1048 U32 TransactionContext96[3]; 1049 U32 TransactionContext128[4]; 1050 } u; 1051 U32 TransactionDetails[1]; 1052 } MPI2_SGE_TRANSACTION_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANSACTION_UNION, 1053 Mpi2SGETransactionUnion_t, MPI2_POINTER pMpi2SGETransactionUnion_t; 1054 1055 1056 /**************************************************************************** 1057 * MPI SGE union for IO SGL's - for MPI v2.0 products only 1058 ****************************************************************************/ 1059 1060 typedef struct _MPI2_MPI_SGE_IO_UNION 1061 { 1062 union 1063 { 1064 MPI2_SGE_SIMPLE_UNION Simple; 1065 MPI2_SGE_CHAIN_UNION Chain; 1066 } u; 1067 } MPI2_MPI_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_IO_UNION, 1068 Mpi2MpiSGEIOUnion_t, MPI2_POINTER pMpi2MpiSGEIOUnion_t; 1069 1070 1071 /**************************************************************************** 1072 * MPI SGE union for SGL's with Simple and Transaction elements - for MPI v2.0 products only 1073 ****************************************************************************/ 1074 1075 typedef struct _MPI2_SGE_TRANS_SIMPLE_UNION 1076 { 1077 union 1078 { 1079 MPI2_SGE_SIMPLE_UNION Simple; 1080 MPI2_SGE_TRANSACTION_UNION Transaction; 1081 } u; 1082 } MPI2_SGE_TRANS_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_SGE_TRANS_SIMPLE_UNION, 1083 Mpi2SGETransSimpleUnion_t, MPI2_POINTER pMpi2SGETransSimpleUnion_t; 1084 1085 1086 /**************************************************************************** 1087 * All MPI SGE types union 1088 ****************************************************************************/ 1089 1090 typedef struct _MPI2_MPI_SGE_UNION 1091 { 1092 union 1093 { 1094 MPI2_SGE_SIMPLE_UNION Simple; 1095 MPI2_SGE_CHAIN_UNION Chain; 1096 MPI2_SGE_TRANSACTION_UNION Transaction; 1097 } u; 1098 } MPI2_MPI_SGE_UNION, MPI2_POINTER PTR_MPI2_MPI_SGE_UNION, 1099 Mpi2MpiSgeUnion_t, MPI2_POINTER pMpi2MpiSgeUnion_t; 1100 1101 1102 /**************************************************************************** 1103 * MPI SGE field definition and masks 1104 ****************************************************************************/ 1105 1106 /* Flags field bit definitions */ 1107 1108 #define MPI2_SGE_FLAGS_LAST_ELEMENT (0x80) 1109 #define MPI2_SGE_FLAGS_END_OF_BUFFER (0x40) 1110 #define MPI2_SGE_FLAGS_ELEMENT_TYPE_MASK (0x30) 1111 #define MPI2_SGE_FLAGS_LOCAL_ADDRESS (0x08) 1112 #define MPI2_SGE_FLAGS_DIRECTION (0x04) 1113 #define MPI2_SGE_FLAGS_ADDRESS_SIZE (0x02) 1114 #define MPI2_SGE_FLAGS_END_OF_LIST (0x01) 1115 1116 #define MPI2_SGE_FLAGS_SHIFT (24) 1117 1118 #define MPI2_SGE_LENGTH_MASK (0x00FFFFFF) 1119 #define MPI2_SGE_CHAIN_LENGTH_MASK (0x0000FFFF) 1120 1121 /* Element Type */ 1122 1123 #define MPI2_SGE_FLAGS_TRANSACTION_ELEMENT (0x00) /* for MPI v2.0 products only */ 1124 #define MPI2_SGE_FLAGS_SIMPLE_ELEMENT (0x10) 1125 #define MPI2_SGE_FLAGS_CHAIN_ELEMENT (0x30) /* for MPI v2.0 products only */ 1126 #define MPI2_SGE_FLAGS_ELEMENT_MASK (0x30) 1127 1128 /* Address location */ 1129 1130 #define MPI2_SGE_FLAGS_SYSTEM_ADDRESS (0x00) 1131 1132 /* Direction */ 1133 1134 #define MPI2_SGE_FLAGS_IOC_TO_HOST (0x00) 1135 #define MPI2_SGE_FLAGS_HOST_TO_IOC (0x04) 1136 1137 #define MPI2_SGE_FLAGS_DEST (MPI2_SGE_FLAGS_IOC_TO_HOST) 1138 #define MPI2_SGE_FLAGS_SOURCE (MPI2_SGE_FLAGS_HOST_TO_IOC) 1139 1140 /* Address Size */ 1141 1142 #define MPI2_SGE_FLAGS_32_BIT_ADDRESSING (0x00) 1143 #define MPI2_SGE_FLAGS_64_BIT_ADDRESSING (0x02) 1144 1145 /* Context Size */ 1146 1147 #define MPI2_SGE_FLAGS_32_BIT_CONTEXT (0x00) 1148 #define MPI2_SGE_FLAGS_64_BIT_CONTEXT (0x02) 1149 #define MPI2_SGE_FLAGS_96_BIT_CONTEXT (0x04) 1150 #define MPI2_SGE_FLAGS_128_BIT_CONTEXT (0x06) 1151 1152 #define MPI2_SGE_CHAIN_OFFSET_MASK (0x00FF0000) 1153 #define MPI2_SGE_CHAIN_OFFSET_SHIFT (16) 1154 1155 /**************************************************************************** 1156 * MPI SGE operation Macros 1157 ****************************************************************************/ 1158 1159 /* SIMPLE FlagsLength manipulations... */ 1160 #define MPI2_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_SGE_FLAGS_SHIFT) 1161 #define MPI2_SGE_GET_FLAGS(f) (((f) & ~MPI2_SGE_LENGTH_MASK) >> MPI2_SGE_FLAGS_SHIFT) 1162 #define MPI2_SGE_LENGTH(f) ((f) & MPI2_SGE_LENGTH_MASK) 1163 #define MPI2_SGE_CHAIN_LENGTH(f) ((f) & MPI2_SGE_CHAIN_LENGTH_MASK) 1164 1165 #define MPI2_SGE_SET_FLAGS_LENGTH(f,l) (MPI2_SGE_SET_FLAGS(f) | MPI2_SGE_LENGTH(l)) 1166 1167 #define MPI2_pSGE_GET_FLAGS(psg) MPI2_SGE_GET_FLAGS((psg)->FlagsLength) 1168 #define MPI2_pSGE_GET_LENGTH(psg) MPI2_SGE_LENGTH((psg)->FlagsLength) 1169 #define MPI2_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_SGE_SET_FLAGS_LENGTH(f,l) 1170 1171 /* CAUTION - The following are READ-MODIFY-WRITE! */ 1172 #define MPI2_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_SGE_SET_FLAGS(f) 1173 #define MPI2_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_SGE_LENGTH(l) 1174 1175 #define MPI2_GET_CHAIN_OFFSET(x) ((x & MPI2_SGE_CHAIN_OFFSET_MASK) >> MPI2_SGE_CHAIN_OFFSET_SHIFT) 1176 1177 1178 /***************************************************************************** 1179 * 1180 * Fusion-MPT IEEE Scatter Gather Elements 1181 * 1182 *****************************************************************************/ 1183 1184 /**************************************************************************** 1185 * IEEE Simple Element structures 1186 ****************************************************************************/ 1187 1188 /* MPI2_IEEE_SGE_SIMPLE32 is for MPI v2.0 products only */ 1189 typedef struct _MPI2_IEEE_SGE_SIMPLE32 1190 { 1191 U32 Address; 1192 U32 FlagsLength; 1193 } MPI2_IEEE_SGE_SIMPLE32, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE32, 1194 Mpi2IeeeSgeSimple32_t, MPI2_POINTER pMpi2IeeeSgeSimple32_t; 1195 1196 typedef struct _MPI2_IEEE_SGE_SIMPLE64 1197 { 1198 U64 Address; 1199 U32 Length; 1200 U16 Reserved1; 1201 U8 Reserved2; 1202 U8 Flags; 1203 } MPI2_IEEE_SGE_SIMPLE64, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE64, 1204 Mpi2IeeeSgeSimple64_t, MPI2_POINTER pMpi2IeeeSgeSimple64_t; 1205 1206 typedef union _MPI2_IEEE_SGE_SIMPLE_UNION 1207 { 1208 MPI2_IEEE_SGE_SIMPLE32 Simple32; 1209 MPI2_IEEE_SGE_SIMPLE64 Simple64; 1210 } MPI2_IEEE_SGE_SIMPLE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_SIMPLE_UNION, 1211 Mpi2IeeeSgeSimpleUnion_t, MPI2_POINTER pMpi2IeeeSgeSimpleUnion_t; 1212 1213 1214 /**************************************************************************** 1215 * IEEE Chain Element structures 1216 ****************************************************************************/ 1217 1218 /* MPI2_IEEE_SGE_CHAIN32 is for MPI v2.0 products only */ 1219 typedef MPI2_IEEE_SGE_SIMPLE32 MPI2_IEEE_SGE_CHAIN32; 1220 1221 /* MPI2_IEEE_SGE_CHAIN64 is for MPI v2.0 products only */ 1222 typedef MPI2_IEEE_SGE_SIMPLE64 MPI2_IEEE_SGE_CHAIN64; 1223 1224 typedef union _MPI2_IEEE_SGE_CHAIN_UNION 1225 { 1226 MPI2_IEEE_SGE_CHAIN32 Chain32; 1227 MPI2_IEEE_SGE_CHAIN64 Chain64; 1228 } MPI2_IEEE_SGE_CHAIN_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_CHAIN_UNION, 1229 Mpi2IeeeSgeChainUnion_t, MPI2_POINTER pMpi2IeeeSgeChainUnion_t; 1230 1231 /* MPI25_IEEE_SGE_CHAIN64 is for MPI v2.5 and later */ 1232 typedef struct _MPI25_IEEE_SGE_CHAIN64 1233 { 1234 U64 Address; 1235 U32 Length; 1236 U16 Reserved1; 1237 U8 NextChainOffset; 1238 U8 Flags; 1239 } MPI25_IEEE_SGE_CHAIN64, MPI2_POINTER PTR_MPI25_IEEE_SGE_CHAIN64, 1240 Mpi25IeeeSgeChain64_t, MPI2_POINTER pMpi25IeeeSgeChain64_t; 1241 1242 1243 /**************************************************************************** 1244 * All IEEE SGE types union 1245 ****************************************************************************/ 1246 1247 /* MPI2_IEEE_SGE_UNION is for MPI v2.0 products only */ 1248 typedef struct _MPI2_IEEE_SGE_UNION 1249 { 1250 union 1251 { 1252 MPI2_IEEE_SGE_SIMPLE_UNION Simple; 1253 MPI2_IEEE_SGE_CHAIN_UNION Chain; 1254 } u; 1255 } MPI2_IEEE_SGE_UNION, MPI2_POINTER PTR_MPI2_IEEE_SGE_UNION, 1256 Mpi2IeeeSgeUnion_t, MPI2_POINTER pMpi2IeeeSgeUnion_t; 1257 1258 1259 /**************************************************************************** 1260 * IEEE SGE union for IO SGL's 1261 ****************************************************************************/ 1262 1263 typedef union _MPI25_SGE_IO_UNION 1264 { 1265 MPI2_IEEE_SGE_SIMPLE64 IeeeSimple; 1266 MPI25_IEEE_SGE_CHAIN64 IeeeChain; 1267 } MPI25_SGE_IO_UNION, MPI2_POINTER PTR_MPI25_SGE_IO_UNION, 1268 Mpi25SGEIOUnion_t, MPI2_POINTER pMpi25SGEIOUnion_t; 1269 1270 1271 /**************************************************************************** 1272 * IEEE SGE field definitions and masks 1273 ****************************************************************************/ 1274 1275 /* Flags field bit definitions */ 1276 1277 #define MPI2_IEEE_SGE_FLAGS_ELEMENT_TYPE_MASK (0x80) 1278 #define MPI25_IEEE_SGE_FLAGS_END_OF_LIST (0x40) 1279 1280 #define MPI2_IEEE32_SGE_FLAGS_SHIFT (24) 1281 1282 #define MPI2_IEEE32_SGE_LENGTH_MASK (0x00FFFFFF) 1283 1284 /* Element Type */ 1285 1286 #define MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT (0x00) 1287 #define MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT (0x80) 1288 1289 /* Next Segment Format */ 1290 1291 #define MPI26_IEEE_SGE_FLAGS_NSF_MASK (0x1C) 1292 #define MPI26_IEEE_SGE_FLAGS_NSF_MPI_IEEE (0x00) 1293 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP (0x08) 1294 #define MPI26_IEEE_SGE_FLAGS_NSF_NVME_SGL (0x10) 1295 1296 /* Data Location Address Space */ 1297 1298 #define MPI2_IEEE_SGE_FLAGS_ADDR_MASK (0x03) 1299 #define MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR (0x00) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5 and later, use in IEEE Simple or Chain element */ 1300 #define MPI2_IEEE_SGE_FLAGS_IOCDDR_ADDR (0x01) /* use in IEEE Simple Element only */ 1301 #define MPI2_IEEE_SGE_FLAGS_IOCPLB_ADDR (0x02) 1302 #define MPI2_IEEE_SGE_FLAGS_IOCPLBNTA_ADDR (0x03) /* for MPI v2.0, use in IEEE Simple Element only; for MPI v2.5, use in IEEE Simple or Chain element */ 1303 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR (0x03) /* use in MPI v2.0 IEEE Chain Element only */ 1304 #define MPI2_IEEE_SGE_FLAGS_SYSTEMPLBCPI_ADDR (MPI2_IEEE_SGE_FLAGS_SYSTEMPLBPCI_ADDR) /* typo in name */ 1305 1306 #define MPI26_IEEE_SGE_FLAGS_IOCCTL_ADDR (0x02) /* for MPI v2.6 only */ 1307 1308 /**************************************************************************** 1309 * IEEE SGE operation Macros 1310 ****************************************************************************/ 1311 1312 /* SIMPLE FlagsLength manipulations... */ 1313 #define MPI2_IEEE32_SGE_SET_FLAGS(f) ((U32)(f) << MPI2_IEEE32_SGE_FLAGS_SHIFT) 1314 #define MPI2_IEEE32_SGE_GET_FLAGS(f) (((f) & ~MPI2_IEEE32_SGE_LENGTH_MASK) >> MPI2_IEEE32_SGE_FLAGS_SHIFT) 1315 #define MPI2_IEEE32_SGE_LENGTH(f) ((f) & MPI2_IEEE32_SGE_LENGTH_MASK) 1316 1317 #define MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f, l) (MPI2_IEEE32_SGE_SET_FLAGS(f) | MPI2_IEEE32_SGE_LENGTH(l)) 1318 1319 #define MPI2_IEEE32_pSGE_GET_FLAGS(psg) MPI2_IEEE32_SGE_GET_FLAGS((psg)->FlagsLength) 1320 #define MPI2_IEEE32_pSGE_GET_LENGTH(psg) MPI2_IEEE32_SGE_LENGTH((psg)->FlagsLength) 1321 #define MPI2_IEEE32_pSGE_SET_FLAGS_LENGTH(psg,f,l) (psg)->FlagsLength = MPI2_IEEE32_SGE_SET_FLAGS_LENGTH(f,l) 1322 1323 /* CAUTION - The following are READ-MODIFY-WRITE! */ 1324 #define MPI2_IEEE32_pSGE_SET_FLAGS(psg,f) (psg)->FlagsLength |= MPI2_IEEE32_SGE_SET_FLAGS(f) 1325 #define MPI2_IEEE32_pSGE_SET_LENGTH(psg,l) (psg)->FlagsLength |= MPI2_IEEE32_SGE_LENGTH(l) 1326 1327 1328 1329 /***************************************************************************** 1330 * 1331 * Fusion-MPT MPI/IEEE Scatter Gather Unions 1332 * 1333 *****************************************************************************/ 1334 1335 typedef union _MPI2_SIMPLE_SGE_UNION 1336 { 1337 MPI2_SGE_SIMPLE_UNION MpiSimple; 1338 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1339 } MPI2_SIMPLE_SGE_UNION, MPI2_POINTER PTR_MPI2_SIMPLE_SGE_UNION, 1340 Mpi2SimpleSgeUntion_t, MPI2_POINTER pMpi2SimpleSgeUntion_t; 1341 1342 1343 typedef union _MPI2_SGE_IO_UNION 1344 { 1345 MPI2_SGE_SIMPLE_UNION MpiSimple; 1346 MPI2_SGE_CHAIN_UNION MpiChain; 1347 MPI2_IEEE_SGE_SIMPLE_UNION IeeeSimple; 1348 MPI2_IEEE_SGE_CHAIN_UNION IeeeChain; 1349 } MPI2_SGE_IO_UNION, MPI2_POINTER PTR_MPI2_SGE_IO_UNION, 1350 Mpi2SGEIOUnion_t, MPI2_POINTER pMpi2SGEIOUnion_t; 1351 1352 1353 /**************************************************************************** 1354 * 1355 * Values for SGLFlags field, used in many request messages with an SGL 1356 * 1357 ****************************************************************************/ 1358 1359 /* values for MPI SGL Data Location Address Space subfield */ 1360 #define MPI2_SGLFLAGS_ADDRESS_SPACE_MASK (0x0C) 1361 #define MPI2_SGLFLAGS_SYSTEM_ADDRESS_SPACE (0x00) 1362 #define MPI2_SGLFLAGS_IOCDDR_ADDRESS_SPACE (0x04) 1363 #define MPI2_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.5 and earlier */ 1364 #define MPI26_SGLFLAGS_IOCPLB_ADDRESS_SPACE (0x08) /* only for MPI v2.6 */ 1365 #define MPI2_SGLFLAGS_IOCPLBNTA_ADDRESS_SPACE (0x0C) /* only for MPI v2.5 and earlier */ 1366 /* values for SGL Type subfield */ 1367 #define MPI2_SGLFLAGS_SGL_TYPE_MASK (0x03) 1368 #define MPI2_SGLFLAGS_SGL_TYPE_MPI (0x00) 1369 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE32 (0x01) /* MPI v2.0 products only */ 1370 #define MPI2_SGLFLAGS_SGL_TYPE_IEEE64 (0x02) 1371 1372 1373 #endif 1374 1375