1 /* 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020-2023, Broadcom Inc. All rights reserved. 5 * Support: <fbsd-storage-driver.pdl@broadcom.com> 6 * 7 * Authors: Sumit Saxena <sumit.saxena@broadcom.com> 8 * Chandrakanth Patil <chandrakanth.patil@broadcom.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are 12 * met: 13 * 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation and/or other 18 * materials provided with the distribution. 19 * 3. Neither the name of the Broadcom Inc. nor the names of its contributors 20 * may be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 * The views and conclusions contained in the software and documentation are 36 * those of the authors and should not be interpreted as representing 37 * official policies,either expressed or implied, of the FreeBSD Project. 38 * 39 * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 40 * 41 * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD 42 */ 43 44 #include "mpi3mr.h" 45 #include "mpi3mr_cam.h" 46 #include "mpi3mr_app.h" 47 48 static int sc_ids; 49 static int mpi3mr_pci_probe(device_t); 50 static int mpi3mr_pci_attach(device_t); 51 static int mpi3mr_pci_detach(device_t); 52 static int mpi3mr_pci_suspend(device_t); 53 static int mpi3mr_pci_resume(device_t); 54 static int mpi3mr_setup_resources(struct mpi3mr_softc *sc); 55 static void mpi3mr_release_resources(struct mpi3mr_softc *); 56 static void mpi3mr_teardown_irqs(struct mpi3mr_softc *sc); 57 58 extern void mpi3mr_watchdog_thread(void *arg); 59 60 static device_method_t mpi3mr_methods[] = { 61 DEVMETHOD(device_probe, mpi3mr_pci_probe), 62 DEVMETHOD(device_attach, mpi3mr_pci_attach), 63 DEVMETHOD(device_detach, mpi3mr_pci_detach), 64 DEVMETHOD(device_suspend, mpi3mr_pci_suspend), 65 DEVMETHOD(device_resume, mpi3mr_pci_resume), 66 DEVMETHOD(bus_print_child, bus_generic_print_child), 67 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 68 { 0, 0 } 69 }; 70 71 char fmt_os_ver[16]; 72 73 SYSCTL_NODE(_hw, OID_AUTO, mpi3mr, CTLFLAG_RD, 0, "MPI3MR Driver Parameters"); 74 MALLOC_DEFINE(M_MPI3MR, "mpi3mrbuf", "Buffers for the MPI3MR driver"); 75 76 static driver_t mpi3mr_pci_driver = { 77 "mpi3mr", 78 mpi3mr_methods, 79 sizeof(struct mpi3mr_softc) 80 }; 81 82 struct mpi3mr_ident { 83 uint16_t vendor; 84 uint16_t device; 85 uint16_t subvendor; 86 uint16_t subdevice; 87 u_int flags; 88 const char *desc; 89 } mpi3mr_identifiers[] = { 90 { MPI3_MFGPAGE_VENDORID_BROADCOM, MPI3_MFGPAGE_DEVID_SAS4116, 91 0xffff, 0xffff, 0, "Broadcom MPIMR 3.0 controller" }, 92 { 0 } 93 }; 94 95 DRIVER_MODULE(mpi3mr, pci, mpi3mr_pci_driver, 0, 0); 96 MODULE_PNP_INFO("U16:vendor;U16:device;U16:subvendor;U16:subdevice;D:#", pci, 97 mpi3mr, mpi3mr_identifiers, nitems(mpi3mr_identifiers) - 1); 98 99 MODULE_DEPEND(mpi3mr, cam, 1, 1, 1); 100 101 /* 102 * mpi3mr_setup_sysctl: setup sysctl values for mpi3mr 103 * input: Adapter instance soft state 104 * 105 * Setup sysctl entries for mpi3mr driver. 106 */ 107 static void 108 mpi3mr_setup_sysctl(struct mpi3mr_softc *sc) 109 { 110 struct sysctl_ctx_list *sysctl_ctx = NULL; 111 struct sysctl_oid *sysctl_tree = NULL; 112 char tmpstr[80], tmpstr2[80]; 113 114 /* 115 * Setup the sysctl variable so the user can change the debug level 116 * on the fly. 117 */ 118 snprintf(tmpstr, sizeof(tmpstr), "MPI3MR controller %d", 119 device_get_unit(sc->mpi3mr_dev)); 120 snprintf(tmpstr2, sizeof(tmpstr2), "%d", device_get_unit(sc->mpi3mr_dev)); 121 122 sysctl_ctx = device_get_sysctl_ctx(sc->mpi3mr_dev); 123 if (sysctl_ctx != NULL) 124 sysctl_tree = device_get_sysctl_tree(sc->mpi3mr_dev); 125 126 if (sysctl_tree == NULL) { 127 sysctl_ctx_init(&sc->sysctl_ctx); 128 sc->sysctl_tree = SYSCTL_ADD_NODE(&sc->sysctl_ctx, 129 SYSCTL_STATIC_CHILDREN(_hw_mpi3mr), OID_AUTO, tmpstr2, 130 CTLFLAG_RD, 0, tmpstr); 131 if (sc->sysctl_tree == NULL) 132 return; 133 sysctl_ctx = &sc->sysctl_ctx; 134 sysctl_tree = sc->sysctl_tree; 135 } 136 137 SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 138 OID_AUTO, "driver_version", CTLFLAG_RD, MPI3MR_DRIVER_VERSION, 139 strlen(MPI3MR_DRIVER_VERSION), "driver version"); 140 141 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 142 OID_AUTO, "fw_outstanding", CTLFLAG_RD, 143 &sc->fw_outstanding.val_rdonly, 0, "FW outstanding commands"); 144 145 SYSCTL_ADD_INT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 146 OID_AUTO, "io_cmds_highwater", CTLFLAG_RD, 147 &sc->io_cmds_highwater, 0, "Max FW outstanding commands"); 148 149 SYSCTL_ADD_STRING(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 150 OID_AUTO, "firmware_version", CTLFLAG_RD, sc->fw_version, 151 strlen(sc->fw_version), "firmware version"); 152 153 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 154 OID_AUTO, "mpi3mr_debug", CTLFLAG_RW, &sc->mpi3mr_debug, 0, 155 "Driver debug level"); 156 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 157 OID_AUTO, "reset", CTLFLAG_RW, &sc->reset.type, 0, 158 "Soft reset(1)/Diag reset(2)"); 159 SYSCTL_ADD_UINT(sysctl_ctx, SYSCTL_CHILDREN(sysctl_tree), 160 OID_AUTO, "iot_enable", CTLFLAG_RW, &sc->iot_enable, 0, 161 "IO throttling enable at driver level(for debug purpose)"); 162 } 163 164 /* 165 * mpi3mr_get_tunables: get tunable parameters. 166 * input: Adapter instance soft state 167 * 168 * Get tunable parameters. This will help to debug driver at boot time. 169 */ 170 static void 171 mpi3mr_get_tunables(struct mpi3mr_softc *sc) 172 { 173 char tmpstr[80]; 174 175 sc->mpi3mr_debug = 176 (MPI3MR_ERROR | MPI3MR_INFO | MPI3MR_FAULT); 177 178 sc->reset_in_progress = 0; 179 sc->reset.type = 0; 180 sc->iot_enable = 1; 181 /* 182 * Grab the global variables. 183 */ 184 TUNABLE_INT_FETCH("hw.mpi3mr.debug_level", &sc->mpi3mr_debug); 185 TUNABLE_INT_FETCH("hw.mpi3mr.ctrl_reset", &sc->reset.type); 186 TUNABLE_INT_FETCH("hw.mpi3mr.iot_enable", &sc->iot_enable); 187 188 /* Grab the unit-instance variables */ 189 snprintf(tmpstr, sizeof(tmpstr), "dev.mpi3mr.%d.debug_level", 190 device_get_unit(sc->mpi3mr_dev)); 191 TUNABLE_INT_FETCH(tmpstr, &sc->mpi3mr_debug); 192 193 snprintf(tmpstr, sizeof(tmpstr), "dev.mpi3mr.%d.reset", 194 device_get_unit(sc->mpi3mr_dev)); 195 TUNABLE_INT_FETCH(tmpstr, &sc->reset.type); 196 197 snprintf(tmpstr, sizeof(tmpstr), "dev.mpi3mr.%d.iot_enable", 198 device_get_unit(sc->mpi3mr_dev)); 199 TUNABLE_INT_FETCH(tmpstr, &sc->iot_enable); 200 } 201 202 static struct mpi3mr_ident * 203 mpi3mr_find_ident(device_t dev) 204 { 205 struct mpi3mr_ident *m; 206 207 for (m = mpi3mr_identifiers; m->vendor != 0; m++) { 208 if (m->vendor != pci_get_vendor(dev)) 209 continue; 210 if (m->device != pci_get_device(dev)) 211 continue; 212 if ((m->subvendor != 0xffff) && 213 (m->subvendor != pci_get_subvendor(dev))) 214 continue; 215 if ((m->subdevice != 0xffff) && 216 (m->subdevice != pci_get_subdevice(dev))) 217 continue; 218 return (m); 219 } 220 221 return (NULL); 222 } 223 224 static int 225 mpi3mr_pci_probe(device_t dev) 226 { 227 static u_int8_t first_ctrl = 1; 228 struct mpi3mr_ident *id; 229 char raw_os_ver[16]; 230 231 if ((id = mpi3mr_find_ident(dev)) != NULL) { 232 if (first_ctrl) { 233 first_ctrl = 0; 234 MPI3MR_OS_VERSION(raw_os_ver, fmt_os_ver); 235 printf("mpi3mr: Loading Broadcom mpi3mr driver version: %s OS version: %s\n", 236 MPI3MR_DRIVER_VERSION, fmt_os_ver); 237 } 238 device_set_desc(dev, id->desc); 239 device_set_desc(dev, id->desc); 240 return (BUS_PROBE_DEFAULT); 241 } 242 return (ENXIO); 243 } 244 245 static void 246 mpi3mr_release_resources(struct mpi3mr_softc *sc) 247 { 248 if (sc->mpi3mr_parent_dmat != NULL) { 249 bus_dma_tag_destroy(sc->mpi3mr_parent_dmat); 250 } 251 252 if (sc->mpi3mr_regs_resource != NULL) { 253 bus_release_resource(sc->mpi3mr_dev, SYS_RES_MEMORY, 254 sc->mpi3mr_regs_rid, sc->mpi3mr_regs_resource); 255 } 256 } 257 258 static int mpi3mr_setup_resources(struct mpi3mr_softc *sc) 259 { 260 bus_dma_template_t t; 261 int i; 262 device_t dev = sc->mpi3mr_dev; 263 264 pci_enable_busmaster(dev); 265 266 for (i = 0; i < PCI_MAXMAPS_0; i++) { 267 sc->mpi3mr_regs_rid = PCIR_BAR(i); 268 269 if ((sc->mpi3mr_regs_resource = bus_alloc_resource_any(dev, 270 SYS_RES_MEMORY, &sc->mpi3mr_regs_rid, RF_ACTIVE)) != NULL) 271 break; 272 } 273 274 if (sc->mpi3mr_regs_resource == NULL) { 275 mpi3mr_printf(sc, "Cannot allocate PCI registers\n"); 276 return (ENXIO); 277 } 278 279 sc->mpi3mr_btag = rman_get_bustag(sc->mpi3mr_regs_resource); 280 sc->mpi3mr_bhandle = rman_get_bushandle(sc->mpi3mr_regs_resource); 281 282 /* 283 * XXX Perhaps we should move this to after we read iocfacts and use 284 * that to create the proper parent tag. However, to get the iocfacts 285 * we need to have a dmatag for both the admin queue and the iocfacts 286 * DMA transfer. So for now, we just create a 'no restriction' tag and 287 * use sc->dma_loaddr for all the other tag_create calls to get the 288 * right value. It would be nice if one could retroactively adjust a 289 * created tag. The Linux driver effectively does this by setting the 290 * dma_mask on the device. 291 */ 292 /* Allocate the parent DMA tag */ 293 bus_dma_template_init(&t, bus_get_dma_tag(dev)); 294 if (bus_dma_template_tag(&t, &sc->mpi3mr_parent_dmat)) { 295 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate parent DMA tag\n"); 296 return (ENOMEM); 297 } 298 299 sc->max_msix_vectors = pci_msix_count(dev); 300 301 return 0; 302 } 303 304 static int 305 mpi3mr_startup(struct mpi3mr_softc *sc) 306 { 307 sc->mpi3mr_flags &= ~MPI3MR_FLAGS_PORT_ENABLE_DONE; 308 mpi3mr_issue_port_enable(sc, 1); 309 return (0); 310 } 311 312 /* Run through any late-start handlers. */ 313 static void 314 mpi3mr_ich_startup(void *arg) 315 { 316 struct mpi3mr_softc *sc; 317 int error; 318 319 sc = (struct mpi3mr_softc *)arg; 320 mpi3mr_dprint(sc, MPI3MR_XINFO, "%s entry\n", __func__); 321 322 mtx_lock(&sc->mpi3mr_mtx); 323 324 mpi3mr_startup(sc); 325 326 mtx_unlock(&sc->mpi3mr_mtx); 327 328 error = mpi3mr_kproc_create(mpi3mr_watchdog_thread, sc, 329 &sc->watchdog_thread, 0, 0, "mpi3mr_watchdog%d", 330 device_get_unit(sc->mpi3mr_dev)); 331 332 if (error) 333 device_printf(sc->mpi3mr_dev, "Error %d starting OCR thread\n", error); 334 335 mpi3mr_dprint(sc, MPI3MR_XINFO, "disestablish config intrhook\n"); 336 config_intrhook_disestablish(&sc->mpi3mr_ich); 337 sc->mpi3mr_ich.ich_arg = NULL; 338 339 mpi3mr_dprint(sc, MPI3MR_XINFO, "%s exit\n", __func__); 340 } 341 342 /** 343 * mpi3mr_ctrl_security_status -Check controller secure status 344 * @pdev: PCI device instance 345 * 346 * Read the Device Serial Number capability from PCI config 347 * space and decide whether the controller is secure or not. 348 * 349 * Return: 0 on success, non-zero on failure. 350 */ 351 static int 352 mpi3mr_ctrl_security_status(device_t dev) 353 { 354 int dev_serial_num, retval = 0; 355 uint32_t cap_data, ctrl_status, debug_status; 356 /* Check if Device serial number extended capability is supported */ 357 if (pci_find_extcap(dev, PCIZ_SERNUM, &dev_serial_num) != 0) { 358 device_printf(dev, 359 "PCIZ_SERNUM is not supported\n"); 360 return -1; 361 } 362 363 cap_data = pci_read_config(dev, dev_serial_num + 4, 4); 364 365 debug_status = cap_data & MPI3MR_CTLR_SECURE_DBG_STATUS_MASK; 366 ctrl_status = cap_data & MPI3MR_CTLR_SECURITY_STATUS_MASK; 367 368 switch (ctrl_status) { 369 case MPI3MR_INVALID_DEVICE: 370 device_printf(dev, 371 "Invalid (Non secure) controller is detected: DID: 0x%x: SVID: 0x%x: SDID: 0x%x\n", 372 pci_get_device(dev), pci_get_subvendor(dev), 373 pci_get_subdevice(dev)); 374 retval = -1; 375 break; 376 case MPI3MR_CONFIG_SECURE_DEVICE: 377 if (!debug_status) 378 device_printf(dev, "Config secure controller is detected\n"); 379 break; 380 case MPI3MR_HARD_SECURE_DEVICE: 381 device_printf(dev, "Hard secure controller is detected\n"); 382 break; 383 case MPI3MR_TAMPERED_DEVICE: 384 device_printf(dev, 385 "Tampered (Non secure) controller is detected: DID: 0x%x: SVID: 0x%x: SDID: 0x%x\n", 386 pci_get_device(dev), pci_get_subvendor(dev), 387 pci_get_subdevice(dev)); 388 retval = -1; 389 break; 390 default: 391 retval = -1; 392 break; 393 } 394 395 if (!retval && debug_status) { 396 device_printf(dev, 397 "Secure Debug (Non secure) controller is detected: DID: 0x%x: SVID: 0x%x: SDID: 0x%x\n", 398 pci_get_device(dev), pci_get_subvendor(dev), 399 pci_get_subdevice(dev)); 400 retval = -1; 401 } 402 403 return retval; 404 } 405 /* 406 * mpi3mr_pci_attach - PCI entry point 407 * @dev: pointer to device struct 408 * 409 * This function does the setup of PCI and registers, allocates controller resources, 410 * initializes mutexes, linked lists and registers interrupts, CAM and initializes 411 * the controller. 412 * 413 * Return: 0 on success and proper error codes on failure 414 */ 415 static int 416 mpi3mr_pci_attach(device_t dev) 417 { 418 struct mpi3mr_softc *sc; 419 int error; 420 421 sc = device_get_softc(dev); 422 bzero(sc, sizeof(*sc)); 423 sc->mpi3mr_dev = dev; 424 425 /* Don't load driver for Non-Secure controllers */ 426 if (mpi3mr_ctrl_security_status(dev)) { 427 sc->secure_ctrl = false; 428 return 0; 429 } 430 431 sc->secure_ctrl = true; 432 433 if ((error = mpi3mr_setup_resources(sc)) != 0) 434 goto load_failed; 435 436 sc->id = sc_ids++; 437 mpi3mr_atomic_set(&sc->fw_outstanding, 0); 438 mpi3mr_atomic_set(&sc->pend_ioctls, 0); 439 sc->admin_req = NULL; 440 sc->admin_reply = NULL; 441 sprintf(sc->driver_name, "%s", MPI3MR_DRIVER_NAME); 442 sprintf(sc->name, "%s%d", sc->driver_name, sc->id); 443 444 sc->mpi3mr_dev = dev; 445 mpi3mr_get_tunables(sc); 446 447 if ((error = mpi3mr_initialize_ioc(sc, MPI3MR_INIT_TYPE_INIT)) != 0) { 448 mpi3mr_dprint(sc, MPI3MR_ERROR, "FW initialization failed\n"); 449 goto load_failed; 450 } 451 452 if ((error = mpi3mr_alloc_requests(sc)) != 0) { 453 mpi3mr_dprint(sc, MPI3MR_ERROR, "Command frames allocation failed\n"); 454 goto load_failed; 455 } 456 457 if ((error = mpi3mr_cam_attach(sc)) != 0) { 458 mpi3mr_dprint(sc, MPI3MR_ERROR, "CAM attach failed\n"); 459 goto load_failed; 460 } 461 462 sc->mpi3mr_ich.ich_func = mpi3mr_ich_startup; 463 sc->mpi3mr_ich.ich_arg = sc; 464 if (config_intrhook_establish(&sc->mpi3mr_ich) != 0) { 465 mpi3mr_dprint(sc, MPI3MR_ERROR, 466 "Cannot establish MPI3MR ICH config hook\n"); 467 error = EINVAL; 468 } 469 470 mpi3mr_dprint(sc, MPI3MR_INFO, "allocating ioctl dma buffers\n"); 471 mpi3mr_alloc_ioctl_dma_memory(sc); 472 473 if ((error = mpi3mr_app_attach(sc)) != 0) { 474 mpi3mr_dprint(sc, MPI3MR_ERROR, "APP/IOCTL attach failed\n"); 475 goto load_failed; 476 } 477 478 mpi3mr_setup_sysctl(sc); 479 480 return 0; 481 482 load_failed: 483 mpi3mr_cleanup_interrupts(sc); 484 mpi3mr_free_mem(sc); 485 mpi3mr_app_detach(sc); 486 mpi3mr_cam_detach(sc); 487 mpi3mr_destory_mtx(sc); 488 mpi3mr_release_resources(sc); 489 return error; 490 } 491 492 void mpi3mr_cleanup_interrupts(struct mpi3mr_softc *sc) 493 { 494 mpi3mr_disable_interrupts(sc); 495 496 mpi3mr_teardown_irqs(sc); 497 498 if (sc->irq_ctx) { 499 free(sc->irq_ctx, M_MPI3MR); 500 sc->irq_ctx = NULL; 501 } 502 503 if (sc->msix_enable) 504 pci_release_msi(sc->mpi3mr_dev); 505 506 sc->msix_count = 0; 507 508 } 509 510 int mpi3mr_setup_irqs(struct mpi3mr_softc *sc) 511 { 512 device_t dev; 513 int error; 514 int i, rid, initial_rid; 515 struct mpi3mr_irq_context *irq_ctx; 516 struct irq_info *irq_info; 517 518 dev = sc->mpi3mr_dev; 519 error = -1; 520 521 if (sc->msix_enable) 522 initial_rid = 1; 523 else 524 initial_rid = 0; 525 526 for (i = 0; i < sc->msix_count; i++) { 527 irq_ctx = &sc->irq_ctx[i]; 528 irq_ctx->msix_index = i; 529 irq_ctx->sc = sc; 530 irq_info = &irq_ctx->irq_info; 531 rid = i + initial_rid; 532 irq_info->irq_rid = rid; 533 irq_info->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 534 &irq_info->irq_rid, RF_ACTIVE); 535 if (irq_info->irq == NULL) { 536 mpi3mr_dprint(sc, MPI3MR_ERROR, 537 "Cannot allocate interrupt RID %d\n", rid); 538 sc->msix_count = i; 539 break; 540 } 541 error = bus_setup_intr(dev, irq_info->irq, 542 INTR_MPSAFE | INTR_TYPE_CAM, NULL, mpi3mr_isr, 543 irq_ctx, &irq_info->intrhand); 544 if (error) { 545 mpi3mr_dprint(sc, MPI3MR_ERROR, 546 "Cannot setup interrupt RID %d\n", rid); 547 sc->msix_count = i; 548 break; 549 } 550 } 551 552 mpi3mr_dprint(sc, MPI3MR_INFO, "Set up %d MSI-x interrupts\n", sc->msix_count); 553 554 return (error); 555 556 } 557 558 static void 559 mpi3mr_teardown_irqs(struct mpi3mr_softc *sc) 560 { 561 struct irq_info *irq_info; 562 int i; 563 564 for (i = 0; i < sc->msix_count; i++) { 565 irq_info = &sc->irq_ctx[i].irq_info; 566 if (irq_info->irq != NULL) { 567 bus_teardown_intr(sc->mpi3mr_dev, irq_info->irq, 568 irq_info->intrhand); 569 bus_release_resource(sc->mpi3mr_dev, SYS_RES_IRQ, 570 irq_info->irq_rid, irq_info->irq); 571 } 572 } 573 574 } 575 576 /* 577 * Allocate, but don't assign interrupts early. Doing it before requesting 578 * the IOCFacts message informs the firmware that we want to do MSI-X 579 * multiqueue. We might not use all of the available messages, but there's 580 * no reason to re-alloc if we don't. 581 */ 582 int 583 mpi3mr_alloc_interrupts(struct mpi3mr_softc *sc, U16 setup_one) 584 { 585 int error, msgs; 586 U16 num_queues; 587 588 error = 0; 589 msgs = 0; 590 591 mpi3mr_cleanup_interrupts(sc); 592 593 if (setup_one) { 594 msgs = 1; 595 } else { 596 msgs = min(sc->max_msix_vectors, sc->cpu_count); 597 num_queues = min(sc->facts.max_op_reply_q, sc->facts.max_op_req_q); 598 msgs = min(msgs, num_queues); 599 600 mpi3mr_dprint(sc, MPI3MR_INFO, "Supported MSI-x count: %d " 601 " CPU count: %d Requested MSI-x count: %d\n", 602 sc->max_msix_vectors, 603 sc->cpu_count, msgs); 604 } 605 606 if (msgs != 0) { 607 error = pci_alloc_msix(sc->mpi3mr_dev, &msgs); 608 if (error) { 609 mpi3mr_dprint(sc, MPI3MR_ERROR, 610 "Could not allocate MSI-x interrupts Error: %x\n", error); 611 goto out_failed; 612 } else 613 sc->msix_enable = 1; 614 } 615 616 sc->msix_count = msgs; 617 sc->irq_ctx = malloc(sizeof(struct mpi3mr_irq_context) * msgs, 618 M_MPI3MR, M_NOWAIT | M_ZERO); 619 620 if (!sc->irq_ctx) { 621 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot alloc memory for interrupt info\n"); 622 error = -1; 623 goto out_failed; 624 } 625 626 mpi3mr_dprint(sc, MPI3MR_XINFO, "Allocated %d MSI-x interrupts\n", msgs); 627 628 return error; 629 out_failed: 630 mpi3mr_cleanup_interrupts(sc); 631 return (error); 632 } 633 634 static int 635 mpi3mr_pci_detach(device_t dev) 636 { 637 struct mpi3mr_softc *sc; 638 int i = 0; 639 640 sc = device_get_softc(dev); 641 642 if (!sc->secure_ctrl) 643 return 0; 644 645 646 if (sc->sysctl_tree != NULL) 647 sysctl_ctx_free(&sc->sysctl_ctx); 648 649 mtx_lock(&sc->reset_mutex); 650 sc->mpi3mr_flags |= MPI3MR_FLAGS_SHUTDOWN; 651 if (sc->watchdog_thread_active) 652 wakeup(&sc->watchdog_chan); 653 mtx_unlock(&sc->reset_mutex); 654 655 while (sc->reset_in_progress && (i < PEND_IOCTLS_COMP_WAIT_TIME)) { 656 i++; 657 if (!(i % 5)) { 658 mpi3mr_dprint(sc, MPI3MR_INFO, 659 "[%2d]waiting for reset to be finished from %s\n", i, __func__); 660 } 661 pause("mpi3mr_shutdown", hz); 662 } 663 664 i = 0; 665 while (sc->watchdog_thread_active && (i < 180)) { 666 i++; 667 if (!(i % 5)) { 668 mpi3mr_dprint(sc, MPI3MR_INFO, 669 "[%2d]waiting for " 670 "mpi3mr_reset thread to quit reset %d\n", i, 671 sc->watchdog_thread_active); 672 } 673 pause("mpi3mr_shutdown", hz); 674 } 675 676 i = 0; 677 while (mpi3mr_atomic_read(&sc->pend_ioctls) && (i < 180)) { 678 i++; 679 if (!(i % 5)) { 680 mpi3mr_dprint(sc, MPI3MR_INFO, 681 "[%2d]waiting for IOCTL to be finished from %s\n", i, __func__); 682 } 683 pause("mpi3mr_shutdown", hz); 684 } 685 686 mpi3mr_cleanup_ioc(sc); 687 mpi3mr_cleanup_event_taskq(sc); 688 mpi3mr_app_detach(sc); 689 mpi3mr_cam_detach(sc); 690 mpi3mr_cleanup_interrupts(sc); 691 mpi3mr_destory_mtx(sc); 692 mpi3mr_free_mem(sc); 693 mpi3mr_release_resources(sc); 694 sc_ids--; 695 return (0); 696 } 697 698 static int 699 mpi3mr_pci_suspend(device_t dev) 700 { 701 return (EINVAL); 702 } 703 704 static int 705 mpi3mr_pci_resume(device_t dev) 706 { 707 return (EINVAL); 708 } 709