1 /* 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020-2023, Broadcom Inc. All rights reserved. 5 * Support: <fbsd-storage-driver.pdl@broadcom.com> 6 * 7 * Authors: Sumit Saxena <sumit.saxena@broadcom.com> 8 * Chandrakanth Patil <chandrakanth.patil@broadcom.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are 12 * met: 13 * 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation and/or other 18 * materials provided with the distribution. 19 * 3. Neither the name of the Broadcom Inc. nor the names of its contributors 20 * may be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 * The views and conclusions contained in the software and documentation are 36 * those of the authors and should not be interpreted as representing 37 * official policies,either expressed or implied, of the FreeBSD Project. 38 * 39 * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 40 * 41 * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD 42 */ 43 44 #include "mpi3mr.h" 45 46 #ifndef _MPI3MR_APP_H_ 47 #define _MPI3MR_APP_H_ 48 49 #define MPI3MR_IOCTL_ADPTYPE_AVGFAMILY 1 50 #define MPI3MR_IOCTL_VERSION 0x06 51 52 #define MPI3MRDRVCMD _IOWR('B', 1, struct mpi3mr_ioctl_drvcmd) 53 #define MPI3MRMPTCMD _IOWR('B', 2, struct mpi3mr_ioctl_mptcmd) 54 55 #define MPI3MR_IOCTL_DEFAULT_TIMEOUT (10) 56 #define PEND_IOCTLS_COMP_WAIT_TIME (10) 57 58 #define MPI3MR_IOCTL_LOGDATA_MAX_ENTRIES 400 59 #define MPI3MR_IOCTL_LOGDATA_ENTRY_HEADER_SZ 0x5 60 61 #define GET_IOC_STATUS(ioc_status) \ 62 ioc_status & MPI3_IOCSTATUS_STATUS_MASK 63 64 /* Encapsulated NVMe command definitions */ 65 #define MPI3MR_NVME_PRP_SIZE 8 66 #define MPI3MR_NVME_CMD_PRP1_OFFSET 24 67 #define MPI3MR_NVME_CMD_PRP2_OFFSET 32 68 #define MPI3MR_NVME_CMD_SGL_OFFSET 24 69 #define MPI3MR_NVME_DATA_FORMAT_PRP 0 70 #define MPI3MR_NVME_DATA_FORMAT_SGL1 1 71 #define MPI3MR_NVME_DATA_FORMAT_SGL2 2 72 73 #define MPI3MR_NVMESGL_DATA_SEGMENT 0x00 74 #define MPI3MR_NVMESGL_LAST_SEGMENT 0x03 75 76 int mpi3mr_app_attach(struct mpi3mr_softc *); 77 void mpi3mr_app_detach(struct mpi3mr_softc *); 78 static struct mpi3mr_mgmt_info mpi3mr_mgmt_info; 79 80 enum mpi3mr_ioctl_adp_state { 81 MPI3MR_IOCTL_ADP_STATE_UNKNOWN = 0, 82 MPI3MR_IOCTL_ADP_STATE_OPERATIONAL = 1, 83 MPI3MR_IOCTL_ADP_STATE_FAULT = 2, 84 MPI3MR_IOCTL_ADP_STATE_IN_RESET = 3, 85 MPI3MR_IOCTL_ADP_STATE_UNRECOVERABLE = 4, 86 }; 87 88 enum mpi3mr_ioctl_data_dir { 89 MPI3MR_APP_DDN, 90 MPI3MR_APP_DDI, 91 MPI3MR_APP_DDO, 92 }; 93 94 enum mpi3mr_ioctl_drvcmds_opcode { 95 MPI3MR_DRVRIOCTL_OPCODE_UNKNOWN = 0, 96 MPI3MR_DRVRIOCTL_OPCODE_ADPINFO = 1, 97 MPI3MR_DRVRIOCTL_OPCODE_ADPRESET = 2, 98 MPI3MR_DRVRIOCTL_OPCODE_TGTDEVINFO = 3, 99 MPI3MR_DRVRIOCTL_OPCODE_ALLTGTDEVINFO = 4, 100 MPI3MR_DRVRIOCTL_OPCODE_GETCHGCNT = 5, 101 MPI3MR_DRVRIOCTL_OPCODE_LOGDATAENABLE = 6, 102 MPI3MR_DRVRIOCTL_OPCODE_PELENABLE = 7, 103 MPI3MR_DRVRIOCTL_OPCODE_GETLOGDATA = 8, 104 MPI3MR_DRVRIOCTL_OPCODE_GETPCIINFO = 100, 105 }; 106 107 enum mpi3mr_ioctl_mpibuffer_type { 108 MPI3MR_IOCTL_BUFTYPE_UNKNOWN, 109 MPI3MR_IOCTL_BUFTYPE_RAIDMGMT_CMD, 110 MPI3MR_IOCTL_BUFTYPE_RAIDMGMT_RESP, 111 MPI3MR_IOCTL_BUFTYPE_DATA_IN, 112 MPI3MR_IOCTL_BUFTYPE_DATA_OUT, 113 MPI3MR_IOCTL_BUFTYPE_MPI_REPLY, 114 MPI3MR_IOCTL_BUFTYPE_ERR_RESPONSE, 115 }; 116 117 enum mpi3mr_ioctl_mpireply_type { 118 MPI3MR_IOCTL_MPI_REPLY_BUFTYPE_UNKNOWN, 119 MPI3MR_IOCTL_MPI_REPLY_BUFTYPE_STATUS, 120 MPI3MR_IOCTL_MPI_REPLY_BUFTYPE_ADDRESS, 121 }; 122 123 enum mpi3mr_ioctl_reset_type { 124 MPI3MR_IOCTL_ADPRESET_UNKNOWN, 125 MPI3MR_IOCTL_ADPRESET_SOFT, 126 MPI3MR_IOCTL_ADPRESET_DIAG_FAULT, 127 }; 128 129 struct mpi3mr_ioctl_drvcmd { 130 U8 mrioc_id; 131 U8 opcode; 132 U16 rsvd1; 133 U32 rsvd2; 134 void *data_in_buf; 135 void *data_out_buf; 136 U32 data_in_size; 137 U32 data_out_size; 138 }; 139 140 struct mpi3mr_ioctl_adpinfo { 141 U32 adp_type; 142 U32 rsvd1; 143 U32 pci_dev_id; 144 U32 pci_dev_hw_rev; 145 U32 pci_subsys_dev_id; 146 U32 pci_subsys_ven_id; 147 U32 pci_dev:5; 148 U32 pci_func:3; 149 U32 pci_bus:8; 150 U32 rsvd2:16; 151 U32 pci_seg_id; 152 U32 ioctl_ver; 153 U8 adp_state; 154 U8 rsvd3; 155 U16 rsvd4; 156 U32 rsvd5[2]; 157 Mpi3DriverInfoLayout_t driver_info; 158 }; 159 160 struct mpi3mr_ioctl_pciinfo { 161 U32 config_space[64]; 162 }; 163 164 struct mpi3mr_ioctl_tgtinfo { 165 U32 target_id; 166 U8 bus_id; 167 U8 rsvd1; 168 U16 rsvd2; 169 U16 dev_handle; 170 U16 persistent_id; 171 U32 seq_num; 172 }; 173 174 struct mpi3mr_device_map_info { 175 U16 handle; 176 U16 per_id; 177 U32 target_id; 178 U8 bus_id; 179 U8 rsvd1; 180 U16 rsvd2; 181 }; 182 183 struct mpi3mr_ioctl_all_tgtinfo { 184 U16 num_devices; 185 U16 rsvd1; 186 U32 rsvd2; 187 struct mpi3mr_device_map_info dmi[1]; 188 }; 189 190 struct mpi3mr_ioctl_chgcnt { 191 U16 change_count; 192 U16 rsvd; 193 }; 194 195 struct mpi3mr_ioctl_adpreset { 196 U8 reset_type; 197 U8 rsvd1; 198 U16 rsvd2; 199 }; 200 201 struct mpi3mr_ioctl_mptcmd { 202 U8 mrioc_id; 203 U8 rsvd1; 204 U16 timeout; 205 U16 rsvd2; 206 U16 mpi_msg_size; 207 void *mpi_msg_buf; 208 void *buf_entry_list; 209 U32 buf_entry_list_size; 210 }; 211 212 struct mpi3mr_buf_entry { 213 U8 buf_type; 214 U8 rsvd1; 215 U16 rsvd2; 216 U32 buf_len; 217 void *buffer; 218 }; 219 220 struct mpi3mr_ioctl_buf_entry_list { 221 U8 num_of_buf_entries; 222 U8 rsvd1; 223 U16 rsvd2; 224 U32 rsvd3; 225 struct mpi3mr_buf_entry buf_entry[1]; 226 }; 227 228 struct mpi3mr_ioctl_mpt_dma_buffer { 229 void *user_buf; 230 void *kern_buf; 231 U32 user_buf_len; 232 U32 kern_buf_len; 233 bus_addr_t kern_buf_dma; 234 bus_dma_tag_t kern_buf_dmatag; 235 bus_dmamap_t kern_buf_dmamap; 236 U8 data_dir; 237 U16 num_dma_desc; 238 struct dma_memory_desc *dma_desc; 239 }; 240 241 struct mpi3mr_ioctl_mpirepbuf { 242 U8 mpirep_type; 243 U8 rsvd1; 244 U16 rsvd2; 245 U8 repbuf[1]; 246 }; 247 248 struct mpi3mr_nvme_pt_sge { 249 U64 base_addr; 250 U32 length; 251 U16 rsvd; 252 U8 rsvd1; 253 U8 sub_type:4; 254 U8 type:4; 255 }; 256 257 struct mpi3mr_log_data_entry { 258 U8 valid_entry; 259 U8 rsvd1; 260 U16 rsvd2; 261 U8 data[1]; 262 }; 263 264 struct mpi3mr_ioctl_logdata_enable { 265 U16 max_entries; 266 U16 rsvd; 267 }; 268 269 struct mpi3mr_ioctl_pel_enable { 270 U16 pel_locale; 271 U8 pel_class; 272 U8 rsvd; 273 }; 274 275 int 276 mpi3mr_pel_abort(struct mpi3mr_softc *sc); 277 void 278 mpi3mr_pel_getseq_complete(struct mpi3mr_softc *sc, 279 struct mpi3mr_drvr_cmd *drvr_cmd); 280 void 281 mpi3mr_issue_pel_wait(struct mpi3mr_softc *sc, 282 struct mpi3mr_drvr_cmd *drvr_cmd); 283 void 284 mpi3mr_pel_wait_complete(struct mpi3mr_softc *sc, 285 struct mpi3mr_drvr_cmd *drvr_cmd); 286 void 287 mpi3mr_send_pel_getseq(struct mpi3mr_softc *sc, 288 struct mpi3mr_drvr_cmd *drvr_cmd); 289 void 290 mpi3mr_app_send_aen(struct mpi3mr_softc *sc); 291 292 #endif /* !_MPI3MR_API_H_ */ 293