1 /* 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020-2024, Broadcom Inc. All rights reserved. 5 * Support: <fbsd-storage-driver.pdl@broadcom.com> 6 * 7 * Authors: Sumit Saxena <sumit.saxena@broadcom.com> 8 * Chandrakanth Patil <chandrakanth.patil@broadcom.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are 12 * met: 13 * 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation and/or other 18 * materials provided with the distribution. 19 * 3. Neither the name of the Broadcom Inc. nor the names of its contributors 20 * may be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 * The views and conclusions contained in the software and documentation are 36 * those of the authors and should not be interpreted as representing 37 * official policies,either expressed or implied, of the FreeBSD Project. 38 * 39 * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 40 * 41 * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD 42 */ 43 44 #ifndef _MPI3MRVAR_H 45 #define _MPI3MRVAR_H 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/module.h> 52 #include <sys/bus.h> 53 #include <sys/conf.h> 54 #include <sys/malloc.h> 55 #include <sys/sysctl.h> 56 #include <sys/uio.h> 57 #include <sys/selinfo.h> 58 #include <sys/poll.h> 59 60 #include <sys/lock.h> 61 #include <sys/mutex.h> 62 #include <sys/endian.h> 63 #include <sys/sysent.h> 64 #include <sys/taskqueue.h> 65 #include <sys/smp.h> 66 67 #include <machine/bus.h> 68 #include <machine/resource.h> 69 #include <sys/rman.h> 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pci_private.h> 74 75 #include <cam/cam.h> 76 #include <cam/cam_ccb.h> 77 #include <cam/cam_debug.h> 78 #include <cam/cam_sim.h> 79 #include <cam/cam_xpt_sim.h> 80 #include <cam/cam_xpt_periph.h> 81 #include <cam/cam_periph.h> 82 #include <cam/scsi/scsi_all.h> 83 #include <cam/scsi/scsi_message.h> 84 85 #include <cam/scsi/smp_all.h> 86 #include <sys/queue.h> 87 #include <sys/kthread.h> 88 #include "mpi/mpi30_api.h" 89 90 #define MPI3MR_DRIVER_VERSION "8.10.0.1.0" 91 #define MPI3MR_DRIVER_RELDATE "19th Mar 2024" 92 93 #define MPI3MR_DRIVER_NAME "mpi3mr" 94 95 #define MPI3MR_NAME_LENGTH 32 96 #define IOCNAME "%s: " 97 98 #define SAS4116_CHIP_REV_A0 0 99 #define SAS4116_CHIP_REV_B0 1 100 101 #define MPI3MR_SG_DEPTH (MPI3MR_4K_PGSZ/sizeof(Mpi3SGESimple_t)) 102 #define MPI3MR_MAX_SECTORS 2048 103 #define MPI3MR_MAX_CMDS_LUN 7 104 #define MPI3MR_MAX_CDB_LENGTH 16 105 #define MPI3MR_MAX_LUN 16895 106 107 #define MPI3MR_SATA_QDEPTH 32 108 #define MPI3MR_SAS_QDEPTH 64 109 #define MPI3MR_RAID_QDEPTH 128 110 #define MPI3MR_NVME_QDEPTH 128 111 112 #define MPI3MR_4K_PGSZ 4096 113 #define MPI3MR_AREQQ_SIZE (2 * MPI3MR_4K_PGSZ) 114 #define MPI3MR_AREPQ_SIZE (4 * MPI3MR_4K_PGSZ) 115 #define MPI3MR_AREQ_FRAME_SZ 128 116 #define MPI3MR_AREP_FRAME_SZ 16 117 118 #define MPI3MR_OPREQQ_SIZE (8 * MPI3MR_4K_PGSZ) 119 #define MPI3MR_OPREPQ_SIZE (4 * MPI3MR_4K_PGSZ) 120 121 /* Operational queue management definitions */ 122 #define MPI3MR_OP_REQ_Q_QD 512 123 #define MPI3MR_OP_REP_Q_QD 1024 124 #define MPI3MR_OP_REP_Q_QD_A0 4096 125 126 #define MPI3MR_THRESHOLD_REPLY_COUNT 100 127 128 #define MPI3MR_CHAINSGE_SIZE MPI3MR_4K_PGSZ 129 130 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 131 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 132 MPI3_SGE_FLAGS_END_OF_LIST) 133 134 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 135 #define MPI3MR_HOSTTAG_INITCMDS 1 136 #define MPI3MR_HOSTTAG_IOCTLCMDS 2 137 #define MPI3MR_HOSTTAG_PELABORT 3 138 #define MPI3MR_HOSTTAG_PELWAIT 4 139 #define MPI3MR_HOSTTAG_TMS 5 140 141 #define MAX_MGMT_ADAPTERS 8 142 #define MPI3MR_WAIT_BEFORE_CTRL_RESET 5 143 144 #define MPI3MR_RESET_REASON_OSTYPE_FREEBSD 0x4 145 #define MPI3MR_RESET_REASON_OSTYPE_SHIFT 28 146 #define MPI3MR_RESET_REASON_IOCNUM_SHIFT 20 147 148 struct mpi3mr_mgmt_info { 149 uint16_t count; 150 struct mpi3mr_softc *sc_ptr[MAX_MGMT_ADAPTERS]; 151 int max_index; 152 }; 153 154 extern char fmt_os_ver[16]; 155 156 #define MPI3MR_OS_VERSION(raw_os_ver, fmt_os_ver) sprintf(raw_os_ver, "%d", __FreeBSD_version); \ 157 sprintf(fmt_os_ver, "%c%c.%c%c.%c%c%c",\ 158 raw_os_ver[0], raw_os_ver[1], raw_os_ver[2],\ 159 raw_os_ver[3], raw_os_ver[4], raw_os_ver[5],\ 160 raw_os_ver[6]); 161 #define MPI3MR_NUM_DEVRMCMD 1 162 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_TMS + 1) 163 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 164 MPI3MR_NUM_DEVRMCMD - 1) 165 #define MPI3MR_INTERNALCMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 166 167 #define MPI3MR_NUM_EVTACKCMD 4 168 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1) 169 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \ 170 MPI3MR_NUM_EVTACKCMD - 1) 171 172 /* command/controller interaction timeout definitions in seconds */ 173 #define MPI3MR_INTADMCMD_TIMEOUT 60 174 #define MPI3MR_PORTENABLE_TIMEOUT 300 175 #define MPI3MR_ABORTTM_TIMEOUT 60 176 #define MPI3MR_RESETTM_TIMEOUT 60 177 #define MPI3MR_TSUPDATE_INTERVAL 900 178 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 179 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 180 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 181 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180 182 #define MPI3MR_RESET_ACK_TIMEOUT 30 183 #define MPI3MR_MUR_TIMEOUT 120 184 185 #define MPI3MR_CMD_NOTUSED 0x8000 186 #define MPI3MR_CMD_COMPLETE 0x0001 187 #define MPI3MR_CMD_PENDING 0x0002 188 #define MPI3MR_CMD_REPLYVALID 0x0004 189 #define MPI3MR_CMD_RESET 0x0008 190 191 #define MPI3MR_NUM_EVTREPLIES 64 192 #define MPI3MR_SENSEBUF_SZ 256 193 #define MPI3MR_SENSEBUF_FACTOR 3 194 #define MPI3MR_CHAINBUF_FACTOR 3 195 196 #define MPT3SAS_HOSTPGSZ_4KEXP 12 197 198 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 199 200 /* Controller Reset related definitions */ 201 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 202 #define MPI3MR_MAX_SHUTDOWN_RETRY_COUNT 2 203 204 /* ResponseCode values */ 205 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 206 #define MPI3MR_RSP_TM_COMPLETE 0x00 207 #define MPI3MR_RSP_INVALID_FRAME 0x02 208 #define MPI3MR_RSP_TM_NOT_SUPPORTED 0x04 209 #define MPI3MR_RSP_TM_FAILED 0x05 210 #define MPI3MR_RSP_TM_SUCCEEDED 0x08 211 #define MPI3MR_RSP_TM_INVALID_LUN 0x09 212 #define MPI3MR_RSP_TM_OVERLAPPED_TAG 0x0A 213 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 214 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 215 216 /* Definitions for the controller security status*/ 217 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 218 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 219 220 #define MPI3MR_INVALID_DEVICE 0x00 221 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04 222 #define MPI3MR_HARD_SECURE_DEVICE 0x08 223 #define MPI3MR_TAMPERED_DEVICE 0x0C 224 225 #define MPI3MR_DEFAULT_MDTS (128 * 1024) 226 #define MPI3MR_DEFAULT_PGSZEXP (12) 227 #define MPI3MR_MAX_IOCTL_TRANSFER_SIZE (1024 * 1024) 228 229 #define MPI3MR_DEVRMHS_RETRYCOUNT 3 230 #define MPI3MR_PELCMDS_RETRYCOUNT 3 231 232 #define MPI3MR_PERIODIC_DELAY 1 /* 1 second heartbeat/watchdog check */ 233 234 struct completion { 235 unsigned int done; 236 struct mtx lock; 237 }; 238 239 typedef union { 240 volatile unsigned int val; 241 unsigned int val_rdonly; 242 } mpi3mr_atomic_t; 243 244 #define mpi3mr_atomic_read(v) atomic_load_acq_int(&(v)->val) 245 #define mpi3mr_atomic_set(v,i) atomic_store_rel_int(&(v)->val, i) 246 #define mpi3mr_atomic_dec(v) atomic_subtract_int(&(v)->val, 1) 247 #define mpi3mr_atomic_inc(v) atomic_add_int(&(v)->val, 1) 248 #define mpi3mr_atomic_add(v, u) atomic_add_int(&(v)->val, u) 249 #define mpi3mr_atomic_sub(v, u) atomic_subtract_int(&(v)->val, u) 250 251 /* IOCTL data transfer sge*/ 252 #define MPI3MR_NUM_IOCTL_SGE 256 253 #define MPI3MR_IOCTL_SGE_SIZE (8 * 1024) 254 255 struct dma_memory_desc { 256 U32 size; 257 void *addr; 258 bus_dma_tag_t tag; 259 bus_dmamap_t dmamap; 260 bus_addr_t dma_addr; 261 }; 262 263 enum mpi3mr_iocstate { 264 MRIOC_STATE_READY = 1, 265 MRIOC_STATE_RESET, 266 MRIOC_STATE_FAULT, 267 MRIOC_STATE_BECOMING_READY, 268 MRIOC_STATE_RESET_REQUESTED, 269 MRIOC_STATE_UNRECOVERABLE, 270 MRIOC_STATE_COUNT, 271 }; 272 273 /* Init type definitions */ 274 enum mpi3mr_init_type { 275 MPI3MR_INIT_TYPE_INIT = 0, 276 MPI3MR_INIT_TYPE_RESET, 277 MPI3MR_INIT_TYPE_RESUME, 278 }; 279 280 /* Reset reason code definitions*/ 281 enum mpi3mr_reset_reason { 282 MPI3MR_RESET_FROM_BRINGUP = 1, 283 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 284 MPI3MR_RESET_FROM_IOCTL = 3, 285 MPI3MR_RESET_FROM_EH_HOS = 4, 286 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 287 MPI3MR_RESET_FROM_IOCTL_TIMEOUT = 6, 288 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 289 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 290 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 291 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 292 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 293 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 294 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 295 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 296 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 297 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 298 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 299 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 300 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 301 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 302 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 303 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 304 MPI3MR_RESET_FROM_SYSFS = 23, 305 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24, 306 MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT = 25, 307 MPI3MR_RESET_FROM_SCSIIO_TIMEOUT = 26, 308 MPI3MR_RESET_FROM_FIRMWARE = 27, 309 MPI3MR_DEFAULT_RESET_REASON = 28, 310 MPI3MR_RESET_REASON_COUNT, 311 }; 312 313 struct mpi3mr_compimg_ver 314 { 315 U16 build_num; 316 U16 cust_id; 317 U8 ph_minor; 318 U8 ph_major; 319 U8 gen_minor; 320 U8 gen_major; 321 }; 322 323 struct mpi3mr_ioc_facts 324 { 325 U32 ioc_capabilities; 326 struct mpi3mr_compimg_ver fw_ver; 327 U32 mpi_version; 328 U16 max_reqs; 329 U16 product_id; 330 U16 op_req_sz; 331 U16 reply_sz; 332 U16 exceptions; 333 U16 max_perids; 334 U16 max_pds; 335 U16 max_sasexpanders; 336 U16 max_sasinitiators; 337 U16 max_enclosures; 338 U16 max_pcieswitches; 339 U16 max_nvme; 340 U16 max_vds; 341 U16 max_hpds; 342 U16 max_advhpds; 343 U16 max_raidpds; 344 U16 min_devhandle; 345 U16 max_devhandle; 346 U16 max_op_req_q; 347 U16 max_op_reply_q; 348 U16 shutdown_timeout; 349 U8 ioc_num; 350 U8 who_init; 351 U16 max_msix_vectors; 352 U8 personality; 353 U8 dma_mask; 354 U8 protocol_flags; 355 U8 sge_mod_mask; 356 U8 sge_mod_value; 357 U8 sge_mod_shift; 358 U8 max_dev_per_tg; 359 U16 max_io_throttle_group; 360 U16 io_throttle_data_length; 361 U16 io_throttle_low; 362 U16 io_throttle_high; 363 }; 364 365 struct mpi3mr_op_req_queue { 366 U16 ci; 367 U16 pi; 368 U16 num_reqs; 369 U8 qid; 370 U8 reply_qid; 371 U32 qsz; 372 void *q_base; 373 bus_dma_tag_t q_base_tag; 374 bus_dmamap_t q_base_dmamap; 375 bus_addr_t q_base_phys; 376 struct mtx q_lock; 377 }; 378 379 struct mpi3mr_op_reply_queue { 380 U16 ci; 381 U8 ephase; 382 U8 qid; 383 U16 num_replies; 384 U32 qsz; 385 bus_dma_tag_t q_base_tag; 386 bus_dmamap_t q_base_dmamap; 387 void *q_base; 388 bus_addr_t q_base_phys; 389 mpi3mr_atomic_t pend_ios; 390 bool in_use; 391 struct mtx q_lock; 392 }; 393 394 struct irq_info { 395 MPI3_REPLY_DESCRIPTORS_UNION *post_queue; 396 bus_dma_tag_t buffer_dmat; 397 struct resource *irq; 398 void *intrhand; 399 int irq_rid; 400 }; 401 402 struct mpi3mr_irq_context { 403 struct mpi3mr_softc *sc; 404 U16 msix_index; 405 struct mpi3mr_op_reply_queue *op_reply_q; 406 char name[MPI3MR_NAME_LENGTH]; 407 struct irq_info irq_info; 408 }; 409 410 MALLOC_DECLARE(M_MPI3MR); 411 SYSCTL_DECL(_hw_mpi3mr); 412 413 typedef struct mpi3mr_drvr_cmd DRVR_CMD; 414 typedef void (*DRVR_CMD_CALLBACK)(struct mpi3mr_softc *mrioc, DRVR_CMD *drvrcmd); 415 struct mpi3mr_drvr_cmd { 416 struct mtx lock; 417 struct completion completion; 418 void *reply; 419 U8 *sensebuf; 420 U8 iou_rc; 421 U16 state; 422 U16 dev_handle; 423 U16 ioc_status; 424 U32 ioc_loginfo; 425 U8 is_waiting; 426 U8 is_senseprst; 427 U8 retry_count; 428 U16 host_tag; 429 DRVR_CMD_CALLBACK callback; 430 }; 431 432 struct mpi3mr_cmd; 433 typedef void mpi3mr_evt_callback_t(struct mpi3mr_softc *, uintptr_t, 434 Mpi3EventNotificationReply_t *reply); 435 typedef void mpi3mr_cmd_callback_t(struct mpi3mr_softc *, 436 struct mpi3mr_cmd *cmd); 437 438 #define MPI3MR_IOVEC_COUNT 2 439 440 enum mpi3mr_data_xfer_direction { 441 MPI3MR_READ = 1, 442 MPI3MR_WRITE, 443 }; 444 445 enum mpi3mr_cmd_state { 446 MPI3MR_CMD_STATE_FREE = 1, 447 MPI3MR_CMD_STATE_BUSY, 448 MPI3MR_CMD_STATE_IN_QUEUE, 449 MPI3MR_CMD_STATE_IN_TM, 450 }; 451 452 enum mpi3mr_target_state { 453 MPI3MR_DEV_CREATED = 1, 454 MPI3MR_DEV_REMOVE_HS_COMPLETED = 2, 455 }; 456 457 struct mpi3mr_cmd { 458 TAILQ_ENTRY(mpi3mr_cmd) next; 459 struct mpi3mr_softc *sc; 460 union ccb *ccb; 461 void *data; 462 u_int length; 463 struct mpi3mr_target *targ; 464 u_int data_dir; 465 u_int state; 466 bus_dmamap_t dmamap; 467 struct scsi_sense_data *sense; 468 struct callout callout; 469 bool callout_owner; 470 U16 hosttag; 471 U8 req_qidx; 472 Mpi3SCSIIORequest_t io_request; 473 }; 474 475 struct mpi3mr_chain { 476 bus_dmamap_t buf_dmamap; 477 void *buf; 478 bus_addr_t buf_phys; 479 }; 480 481 struct mpi3mr_event_handle { 482 TAILQ_ENTRY(mpi3mr_event_handle) eh_list; 483 mpi3mr_evt_callback_t *callback; 484 void *data; 485 uint8_t mask[16]; 486 }; 487 488 struct mpi3mr_fw_event_work { 489 U16 event; 490 void *event_data; 491 TAILQ_ENTRY(mpi3mr_fw_event_work) ev_link; 492 U8 send_ack; 493 U8 process_event; 494 U32 event_context; 495 U16 event_data_size; 496 }; 497 498 /** 499 * struct delayed_dev_rmhs_node - Delayed device removal node 500 * 501 * @list: list head 502 * @handle: Device handle 503 * @iou_rc: IO Unit Control Reason Code 504 */ 505 struct delayed_dev_rmhs_node { 506 TAILQ_ENTRY(delayed_dev_rmhs_node) list; 507 U16 handle; 508 U8 iou_rc; 509 }; 510 511 /** 512 * struct delayed_evtack_node - Delayed event ack node 513 * 514 * @list: list head 515 * @event: MPI3 event ID 516 * @event_ctx: Event context 517 */ 518 struct delayed_evtack_node { 519 TAILQ_ENTRY(delayed_evtack_node) list; 520 U8 event; 521 U32 event_ctx; 522 }; 523 524 /* Reset types */ 525 enum reset_type { 526 MPI3MR_NO_RESET, 527 MPI3MR_TRIGGER_SOFT_RESET, 528 }; 529 530 struct mpi3mr_reset { 531 u_int type; 532 U32 reason; 533 int status; 534 bool ioctl_reset_snapdump; 535 }; 536 537 struct mpi3mr_softc { 538 device_t mpi3mr_dev; 539 struct cdev *mpi3mr_cdev; 540 u_int mpi3mr_flags; 541 #define MPI3MR_FLAGS_SHUTDOWN (1 << 0) 542 #define MPI3MR_FLAGS_DIAGRESET (1 << 1) 543 #define MPI3MR_FLAGS_ATTACH_DONE (1 << 2) 544 #define MPI3MR_FLAGS_PORT_ENABLE_DONE (1 << 3) 545 U8 id; 546 int cpu_count; 547 char name[MPI3MR_NAME_LENGTH]; 548 char driver_name[MPI3MR_NAME_LENGTH]; 549 int bars; 550 bus_addr_t dma_loaddr; 551 u_int mpi3mr_debug; 552 struct mpi3mr_reset reset; 553 int max_msix_vectors; 554 int msix_count; 555 bool msix_enable; 556 int io_cmds_highwater; 557 int max_chains; 558 uint32_t chain_frame_size; 559 struct sysctl_ctx_list sysctl_ctx; 560 struct sysctl_oid *sysctl_tree; 561 char fw_version[32]; 562 struct mpi3mr_chain *chains; 563 struct callout periodic; 564 struct callout device_check_callout; 565 566 struct mpi3mr_cam_softc *cam_sc; 567 struct mpi3mr_cmd **cmd_list; 568 TAILQ_HEAD(, mpi3mr_cmd) cmd_list_head; 569 struct mtx cmd_pool_lock; 570 571 struct resource *mpi3mr_regs_resource; 572 bus_space_handle_t mpi3mr_bhandle; 573 bus_space_tag_t mpi3mr_btag; 574 int mpi3mr_regs_rid; 575 576 bus_dma_tag_t mpi3mr_parent_dmat; 577 bus_dma_tag_t buffer_dmat; 578 579 int num_reqs; 580 int num_replies; 581 int num_chains; 582 583 TAILQ_HEAD(, mpi3mr_event_handle) event_list; 584 struct mpi3mr_event_handle *mpi3mr_log_eh; 585 struct intr_config_hook mpi3mr_ich; 586 587 struct mtx mpi3mr_mtx; 588 struct mtx io_lock; 589 U8 intr_enabled; 590 TAILQ_HEAD(, delayed_dev_rmhs_node) delayed_rmhs_list; 591 TAILQ_HEAD(, delayed_evtack_node) delayed_evtack_cmds_list; 592 593 U16 num_admin_reqs; 594 U32 admin_req_q_sz; 595 U16 admin_req_pi; 596 U16 admin_req_ci; 597 bus_dma_tag_t admin_req_tag; 598 bus_dmamap_t admin_req_dmamap; 599 bus_addr_t admin_req_phys; 600 U8 *admin_req; 601 struct mtx admin_req_lock; 602 603 U16 num_admin_replies; 604 U32 admin_reply_q_sz; 605 U16 admin_reply_ci; 606 U8 admin_reply_ephase; 607 bus_dma_tag_t admin_reply_tag; 608 bus_dmamap_t admin_reply_dmamap; 609 bus_addr_t admin_reply_phys; 610 U8 *admin_reply; 611 struct mtx admin_reply_lock; 612 bool admin_in_use; 613 614 U32 num_reply_bufs; 615 bus_dma_tag_t reply_buf_tag; 616 bus_dmamap_t reply_buf_dmamap; 617 bus_addr_t reply_buf_phys; 618 U8 *reply_buf; 619 bus_addr_t reply_buf_dma_max_address; 620 bus_addr_t reply_buf_dma_min_address; 621 622 U16 reply_free_q_sz; 623 bus_dma_tag_t reply_free_q_tag; 624 bus_dmamap_t reply_free_q_dmamap; 625 bus_addr_t reply_free_q_phys; 626 U64 *reply_free_q; 627 struct mtx reply_free_q_lock; 628 U32 reply_free_q_host_index; 629 630 U32 num_sense_bufs; 631 bus_dma_tag_t sense_buf_tag; 632 bus_dmamap_t sense_buf_dmamap; 633 bus_addr_t sense_buf_phys; 634 U8 *sense_buf; 635 636 U16 sense_buf_q_sz; 637 bus_dma_tag_t sense_buf_q_tag; 638 bus_dmamap_t sense_buf_q_dmamap; 639 bus_addr_t sense_buf_q_phys; 640 U64 *sense_buf_q; 641 struct mtx sense_buf_q_lock; 642 U32 sense_buf_q_host_index; 643 644 void *nvme_encap_prp_list; 645 bus_addr_t nvme_encap_prp_list_dma; 646 bus_dma_tag_t nvme_encap_prp_list_dmatag; 647 bus_dmamap_t nvme_encap_prp_list_dma_dmamap; 648 U32 nvme_encap_prp_sz; 649 650 U32 ready_timeout; 651 652 struct mpi3mr_irq_context *irq_ctx; 653 654 U16 num_queues; /* Number of request/reply queues */ 655 struct mpi3mr_op_req_queue *op_req_q; 656 struct mpi3mr_op_reply_queue *op_reply_q; 657 U16 num_hosttag_op_req_q; 658 659 struct mpi3mr_drvr_cmd init_cmds; 660 struct mpi3mr_ioc_facts facts; 661 U16 reply_sz; 662 U16 op_reply_sz; 663 664 U32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 665 666 char fwevt_worker_name[MPI3MR_NAME_LENGTH]; 667 struct workqueue_struct *fwevt_worker_thread; 668 struct mtx fwevt_lock; 669 struct mtx target_lock; 670 671 U16 max_host_ios; 672 bus_dma_tag_t chain_sgl_list_tag; 673 struct mpi3mr_chain *chain_sgl_list; 674 U16 chain_bitmap_sz; 675 void *chain_bitmap; 676 struct mtx chain_buf_lock; 677 U16 chain_buf_count; 678 679 struct mpi3mr_drvr_cmd ioctl_cmds; 680 struct mpi3mr_drvr_cmd host_tm_cmds; 681 struct mpi3mr_drvr_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 682 struct mpi3mr_drvr_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD]; 683 684 U16 devrem_bitmap_sz; 685 void *devrem_bitmap; 686 687 U16 dev_handle_bitmap_sz; 688 void *removepend_bitmap; 689 690 U16 evtack_cmds_bitmap_sz; 691 void *evtack_cmds_bitmap; 692 693 U32 ts_update_counter; 694 U8 reset_in_progress; 695 U8 unrecoverable; 696 U8 block_ioctls; 697 U8 in_prep_ciactv_rst; 698 U16 prep_ciactv_rst_counter; 699 struct mtx reset_mutex; 700 701 U8 prepare_for_reset; 702 U16 prepare_for_reset_timeout_counter; 703 704 U16 diagsave_timeout; 705 int logging_level; 706 U16 flush_io_count; 707 708 Mpi3DriverInfoLayout_t driver_info; 709 710 U16 change_count; 711 712 U8 *log_data_buffer; 713 U16 log_data_buffer_index; 714 U16 log_data_entry_size; 715 716 U8 pel_wait_pend; 717 U8 pel_abort_requested; 718 U8 pel_class; 719 U16 pel_locale; 720 721 struct mpi3mr_drvr_cmd pel_cmds; 722 struct mpi3mr_drvr_cmd pel_abort_cmd; 723 U32 newest_seqnum; 724 void *pel_seq_number; 725 bus_addr_t pel_seq_number_dma; 726 bus_dma_tag_t pel_seq_num_dmatag; 727 bus_dmamap_t pel_seq_num_dmamap; 728 U32 pel_seq_number_sz; 729 730 struct selinfo mpi3mr_select; 731 U32 mpi3mr_poll_waiting; 732 U32 mpi3mr_aen_triggered; 733 734 U16 wait_for_port_enable; 735 U16 track_mapping_events; 736 U16 pending_map_events; 737 mpi3mr_atomic_t fw_outstanding; 738 mpi3mr_atomic_t pend_ioctls; 739 struct proc *watchdog_thread; 740 void *watchdog_chan; 741 void *tm_chan; 742 u_int8_t remove_in_progress; 743 u_int8_t watchdog_thread_active; 744 u_int8_t do_timedout_reset; 745 bool allow_ios; 746 bool secure_ctrl; 747 mpi3mr_atomic_t pend_large_data_sz; 748 749 u_int32_t io_throttle_data_length; 750 u_int32_t io_throttle_high; 751 u_int32_t io_throttle_low; 752 u_int16_t num_io_throttle_group; 753 u_int iot_enable; 754 struct mpi3mr_throttle_group_info *throttle_groups; 755 756 struct dma_memory_desc ioctl_sge[MPI3MR_NUM_IOCTL_SGE]; 757 struct dma_memory_desc ioctl_chain_sge; 758 struct dma_memory_desc ioctl_resp_sge; 759 bool ioctl_sges_allocated; 760 }; 761 762 static __inline uint64_t 763 mpi3mr_regread64(struct mpi3mr_softc *sc, uint32_t offset) 764 { 765 return bus_space_read_8(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset); 766 } 767 768 static __inline void 769 mpi3mr_regwrite64(struct mpi3mr_softc *sc, uint32_t offset, uint64_t val) 770 { 771 bus_space_write_8(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset, val); 772 } 773 774 static __inline uint32_t 775 mpi3mr_regread(struct mpi3mr_softc *sc, uint32_t offset) 776 { 777 return bus_space_read_4(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset); 778 } 779 780 static __inline void 781 mpi3mr_regwrite(struct mpi3mr_softc *sc, uint32_t offset, uint32_t val) 782 { 783 bus_space_write_4(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset, val); 784 } 785 786 #define MPI3MR_INFO (1 << 0) /* Basic info */ 787 #define MPI3MR_FAULT (1 << 1) /* Hardware faults */ 788 #define MPI3MR_EVENT (1 << 2) /* Event data from the controller */ 789 #define MPI3MR_LOG (1 << 3) /* Log data from the controller */ 790 #define MPI3MR_RECOVERY (1 << 4) /* Command error recovery tracing */ 791 #define MPI3MR_ERROR (1 << 5) /* Fatal driver/OS APIs failure */ 792 #define MPI3MR_XINFO (1 << 6) /* Additional info logs*/ 793 #define MPI3MR_TRACE (1 << 7) /* Trace functions */ 794 #define MPI3MR_IOT (1 << 8) /* IO throttling related debugs */ 795 #define MPI3MR_DEBUG_TM (1 << 9) /* Task management related debugs */ 796 #define MPI3MR_DEBUG_IOCTL (1 << 10) /* IOCTL related debugs */ 797 798 #define mpi3mr_printf(sc, args...) \ 799 device_printf((sc)->mpi3mr_dev, ##args) 800 801 #define mpi3mr_print_field(sc, msg, args...) \ 802 printf("\t" msg, ##args) 803 804 #define mpi3mr_vprintf(sc, args...) \ 805 do { \ 806 if (bootverbose) \ 807 mpi3mr_printf(sc, ##args); \ 808 } while (0) 809 810 #define mpi3mr_dprint(sc, level, msg, args...) \ 811 do { \ 812 if ((sc)->mpi3mr_debug & (level)) \ 813 device_printf((sc)->mpi3mr_dev, msg, ##args); \ 814 } while (0) 815 816 #define MPI3MR_PRINTFIELD_START(sc, tag...) \ 817 mpi3mr_printf((sc), ##tag); \ 818 mpi3mr_print_field((sc), ":\n") 819 #define MPI3MR_PRINTFIELD_END(sc, tag) \ 820 mpi3mr_printf((sc), tag "\n") 821 #define MPI3MR_PRINTFIELD(sc, facts, attr, fmt) \ 822 mpi3mr_print_field((sc), #attr ": " #fmt "\n", (facts)->attr) 823 824 #define mpi3mr_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 825 kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 826 #define mpi3mr_kproc_exit(arg) kproc_exit(arg) 827 828 #if defined(CAM_PRIORITY_XPT) 829 #define MPI3MR_PRIORITY_XPT CAM_PRIORITY_XPT 830 #else 831 #define MPI3MR_PRIORITY_XPT 5 832 #endif 833 834 static __inline void 835 mpi3mr_clear_bit(int b, volatile void *p) 836 { 837 atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 838 } 839 840 static __inline void 841 mpi3mr_set_bit(int b, volatile void *p) 842 { 843 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 844 } 845 846 static __inline int 847 mpi3mr_test_bit(int b, volatile void *p) 848 { 849 return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f)); 850 } 851 852 static __inline int 853 mpi3mr_test_and_set_bit(int b, volatile void *p) 854 { 855 int ret = ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f)); 856 857 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 858 return ret; 859 } 860 861 static __inline int 862 mpi3mr_find_first_zero_bit(void *p, int bit_count) 863 { 864 int i, sz, j=0; 865 U8 *loc; 866 867 sz = bit_count % 8 ? (bit_count / 8 + 1) : (bit_count / 8); 868 loc = malloc(sz, M_MPI3MR, M_NOWAIT | M_ZERO); 869 870 memcpy(loc, p, sz); 871 872 for (i = 0; i < sz; i++) { 873 j = 0; 874 while (j < 8) { 875 if (!((loc[i] >> j) & 0x1)) 876 goto out; 877 j++; 878 } 879 } 880 out: 881 free(loc, M_MPI3MR); 882 return (i + j); 883 } 884 885 #define MPI3MR_DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) 886 887 void 888 init_completion(struct completion *completion); 889 890 void 891 complete(struct completion *completion); 892 893 void wait_for_completion_timeout(struct completion *completion, 894 U32 timeout); 895 void wait_for_completion_timeout_tm(struct completion *completion, 896 U32 timeout, struct mpi3mr_softc *sc); 897 void mpi3mr_add_sg_single(void *paddr, U8 flags, U32 length, 898 bus_addr_t dma_addr); 899 void mpi3mr_enable_interrupts(struct mpi3mr_softc *sc); 900 void mpi3mr_disable_interrupts(struct mpi3mr_softc *sc); 901 void mpi3mr_memaddr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 902 int mpi3mr_submit_admin_cmd(struct mpi3mr_softc *mrioc, void *admin_req, 903 U16 admin_req_sz); 904 int mpi3mr_submit_io(struct mpi3mr_softc *mrioc, 905 struct mpi3mr_op_req_queue *op_req_q, U8 *req); 906 int 907 mpi3mr_alloc_interrupts(struct mpi3mr_softc *sc, U16 setup_one); 908 909 void mpi3mr_cleanup_ioc(struct mpi3mr_softc *sc); 910 int mpi3mr_initialize_ioc(struct mpi3mr_softc *sc, U8 reason); 911 void mpi3mr_build_zero_len_sge(void *paddr); 912 int mpi3mr_issue_event_notification(struct mpi3mr_softc *sc); 913 int 914 mpi3mr_register_events(struct mpi3mr_softc *sc); 915 void mpi3mr_process_op_reply_desc(struct mpi3mr_softc *sc, 916 Mpi3DefaultReplyDescriptor_t *reply_desc, U64 *reply_dma); 917 struct mpi3mr_cmd * 918 mpi3mr_get_command(struct mpi3mr_softc *sc); 919 void 920 mpi3mr_release_command(struct mpi3mr_cmd *cmd); 921 int 922 mpi3mr_complete_io_cmd(struct mpi3mr_softc *sc, 923 struct mpi3mr_irq_context *irq_context); 924 int 925 mpi3mr_cam_detach(struct mpi3mr_softc *sc); 926 int 927 mpi3mr_cam_attach(struct mpi3mr_softc *sc); 928 struct mpi3mr_target * 929 mpi3mr_find_target_by_per_id(struct mpi3mr_cam_softc *cam_sc, 930 uint16_t per_id); 931 struct mpi3mr_target * 932 mpi3mr_find_target_by_dev_handle(struct mpi3mr_cam_softc *cam_sc, 933 uint16_t dev_handle); 934 int mpi3mr_create_device(struct mpi3mr_softc *sc, 935 Mpi3DevicePage0_t *dev_pg0); 936 void 937 mpi3mr_unmap_request(struct mpi3mr_softc *sc, struct mpi3mr_cmd *cmd); 938 void 939 init_completion(struct completion *completion); 940 void 941 complete(struct completion *completion); 942 void wait_for_completion_timeout(struct completion *completion, 943 U32 timeout); 944 void 945 poll_for_command_completion(struct mpi3mr_softc *sc, 946 struct mpi3mr_drvr_cmd *cmd, U16 wait); 947 int 948 mpi3mr_alloc_requests(struct mpi3mr_softc *sc); 949 void 950 mpi3mr_watchdog(void *arg); 951 int mpi3mr_issue_port_enable(struct mpi3mr_softc *mrioc, U8 async); 952 void 953 mpi3mr_isr(void *privdata); 954 int 955 mpi3mr_alloc_msix_queues(struct mpi3mr_softc *sc); 956 void 957 mpi3mr_destory_mtx(struct mpi3mr_softc *sc); 958 void 959 mpi3mr_free_mem(struct mpi3mr_softc *sc); 960 void 961 mpi3mr_cleanup_interrupts(struct mpi3mr_softc *sc); 962 int mpi3mr_setup_irqs(struct mpi3mr_softc *sc); 963 void mpi3mr_cleanup_event_taskq(struct mpi3mr_softc *sc); 964 void 965 mpi3mr_hexdump(void *buf, int sz, int format); 966 int mpi3mr_soft_reset_handler(struct mpi3mr_softc *sc, 967 U16 reset_reason, bool snapdump); 968 void 969 mpi3mrsas_release_simq_reinit(struct mpi3mr_cam_softc *cam_sc); 970 void 971 mpi3mr_watchdog_thread(void *arg); 972 void mpi3mr_add_device(struct mpi3mr_softc *sc, U16 per_id); 973 int mpi3mr_remove_device(struct mpi3mr_softc *sc, U16 handle); 974 int 975 mpi3mrsas_register_events(struct mpi3mr_softc *sc); 976 int mpi3mr_process_event_ack(struct mpi3mr_softc *sc, U8 event, 977 U32 event_ctx); 978 int mpi3mr_remove_device_from_os(struct mpi3mr_softc *sc, U16 handle); 979 void mpi3mr_remove_device_from_list(struct mpi3mr_softc *sc, struct mpi3mr_target *target, 980 bool must_delete); 981 void mpi3mr_update_device(struct mpi3mr_softc *mrioc, 982 struct mpi3mr_target *tgtdev, Mpi3DevicePage0_t *dev_pg0, bool is_added); 983 void mpi3mr_app_save_logdata(struct mpi3mr_softc *sc, char *event_data, U16 event_data_size); 984 void mpi3mr_set_io_divert_for_all_vd_in_tg(struct mpi3mr_softc *sc, 985 struct mpi3mr_throttle_group_info *tg, U8 divert_value); 986 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_softc *sc); 987 void mpi3mr_poll_pend_io_completions(struct mpi3mr_softc *sc); 988 void int_to_lun(unsigned int lun, U8 *req_lun); 989 void trigger_reset_from_watchdog(struct mpi3mr_softc *sc, U8 reset_type, U16 reset_reason); 990 void mpi3mr_alloc_ioctl_dma_memory(struct mpi3mr_softc *sc); 991 #endif /*MPI3MR_H_INCLUDED*/ 992