1 /* 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2020-2024, Broadcom Inc. All rights reserved. 5 * Support: <fbsd-storage-driver.pdl@broadcom.com> 6 * 7 * Authors: Sumit Saxena <sumit.saxena@broadcom.com> 8 * Chandrakanth Patil <chandrakanth.patil@broadcom.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are 12 * met: 13 * 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation and/or other 18 * materials provided with the distribution. 19 * 3. Neither the name of the Broadcom Inc. nor the names of its contributors 20 * may be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 * The views and conclusions contained in the software and documentation are 36 * those of the authors and should not be interpreted as representing 37 * official policies,either expressed or implied, of the FreeBSD Project. 38 * 39 * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 40 * 41 * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD 42 */ 43 44 #ifndef _MPI3MRVAR_H 45 #define _MPI3MRVAR_H 46 47 #include <sys/types.h> 48 #include <sys/param.h> 49 #include <sys/systm.h> 50 #include <sys/kernel.h> 51 #include <sys/module.h> 52 #include <sys/bus.h> 53 #include <sys/conf.h> 54 #include <sys/malloc.h> 55 #include <sys/sysctl.h> 56 #include <sys/uio.h> 57 #include <sys/selinfo.h> 58 #include <sys/poll.h> 59 60 #include <sys/lock.h> 61 #include <sys/mutex.h> 62 #include <sys/endian.h> 63 #include <sys/sysent.h> 64 #include <sys/taskqueue.h> 65 #include <sys/smp.h> 66 67 #include <machine/bus.h> 68 #include <machine/resource.h> 69 #include <sys/rman.h> 70 71 #include <dev/pci/pcireg.h> 72 #include <dev/pci/pcivar.h> 73 #include <dev/pci/pci_private.h> 74 75 #include <cam/cam.h> 76 #include <cam/cam_ccb.h> 77 #include <cam/cam_debug.h> 78 #include <cam/cam_sim.h> 79 #include <cam/cam_xpt_sim.h> 80 #include <cam/cam_xpt_periph.h> 81 #include <cam/cam_periph.h> 82 #include <cam/scsi/scsi_all.h> 83 #include <cam/scsi/scsi_message.h> 84 85 #include <cam/scsi/smp_all.h> 86 #include <sys/queue.h> 87 #include <sys/kthread.h> 88 #include "mpi/mpi30_api.h" 89 90 #define MPI3MR_DRIVER_VERSION "8.10.0.1.0" 91 #define MPI3MR_DRIVER_RELDATE "19th Mar 2024" 92 93 #define MPI3MR_DRIVER_NAME "mpi3mr" 94 95 #define MPI3MR_NAME_LENGTH 32 96 #define IOCNAME "%s: " 97 98 #define MPI3MR_DEFAULT_MAX_IO_SIZE (1 * 1024 * 1024) 99 100 #define SAS4116_CHIP_REV_A0 0 101 #define SAS4116_CHIP_REV_B0 1 102 103 #define MPI3MR_MAX_SECTORS 2048 104 #define MPI3MR_MAX_CMDS_LUN 7 105 #define MPI3MR_MAX_CDB_LENGTH 16 106 #define MPI3MR_MAX_LUN 16895 107 108 #define MPI3MR_SATA_QDEPTH 32 109 #define MPI3MR_SAS_QDEPTH 64 110 #define MPI3MR_RAID_QDEPTH 128 111 #define MPI3MR_NVME_QDEPTH 128 112 113 /* Definitions for internal SGL and Chain SGL buffers */ 114 #define MPI3MR_4K_PGSZ 4096 115 #define MPI3MR_PAGE_SIZE_4K 4096 116 #define MPI3MR_DEFAULT_SGL_ENTRIES 256 117 #define MPI3MR_MAX_SGL_ENTRIES 2048 118 119 #define MPI3MR_AREQQ_SIZE (2 * MPI3MR_4K_PGSZ) 120 #define MPI3MR_AREPQ_SIZE (4 * MPI3MR_4K_PGSZ) 121 #define MPI3MR_AREQ_FRAME_SZ 128 122 #define MPI3MR_AREP_FRAME_SZ 16 123 124 #define MPI3MR_OPREQQ_SIZE (8 * MPI3MR_4K_PGSZ) 125 #define MPI3MR_OPREPQ_SIZE (4 * MPI3MR_4K_PGSZ) 126 127 /* Operational queue management definitions */ 128 #define MPI3MR_OP_REQ_Q_QD 512 129 #define MPI3MR_OP_REP_Q_QD 1024 130 #define MPI3MR_OP_REP_Q_QD_A0 4096 131 132 #define MPI3MR_THRESHOLD_REPLY_COUNT 100 133 134 #define MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST \ 135 (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | MPI3_SGE_FLAGS_DLAS_SYSTEM | \ 136 MPI3_SGE_FLAGS_END_OF_LIST) 137 138 #define MPI3MR_HOSTTAG_INVALID 0xFFFF 139 #define MPI3MR_HOSTTAG_INITCMDS 1 140 #define MPI3MR_HOSTTAG_IOCTLCMDS 2 141 #define MPI3MR_HOSTTAG_PELABORT 3 142 #define MPI3MR_HOSTTAG_PELWAIT 4 143 #define MPI3MR_HOSTTAG_TMS 5 144 145 #define MAX_MGMT_ADAPTERS 8 146 #define MPI3MR_WAIT_BEFORE_CTRL_RESET 5 147 148 #define MPI3MR_RESET_REASON_OSTYPE_FREEBSD 0x4 149 #define MPI3MR_RESET_REASON_OSTYPE_SHIFT 28 150 #define MPI3MR_RESET_REASON_IOCNUM_SHIFT 20 151 152 struct mpi3mr_mgmt_info { 153 uint16_t count; 154 struct mpi3mr_softc *sc_ptr[MAX_MGMT_ADAPTERS]; 155 int max_index; 156 }; 157 158 extern char fmt_os_ver[16]; 159 160 #define MPI3MR_OS_VERSION(raw_os_ver, fmt_os_ver) sprintf(raw_os_ver, "%d", __FreeBSD_version); \ 161 sprintf(fmt_os_ver, "%c%c.%c%c.%c%c%c",\ 162 raw_os_ver[0], raw_os_ver[1], raw_os_ver[2],\ 163 raw_os_ver[3], raw_os_ver[4], raw_os_ver[5],\ 164 raw_os_ver[6]); 165 #define MPI3MR_NUM_DEVRMCMD 1 166 #define MPI3MR_HOSTTAG_DEVRMCMD_MIN (MPI3MR_HOSTTAG_TMS + 1) 167 #define MPI3MR_HOSTTAG_DEVRMCMD_MAX (MPI3MR_HOSTTAG_DEVRMCMD_MIN + \ 168 MPI3MR_NUM_DEVRMCMD - 1) 169 #define MPI3MR_INTERNALCMDS_RESVD MPI3MR_HOSTTAG_DEVRMCMD_MAX 170 171 #define MPI3MR_NUM_EVTACKCMD 4 172 #define MPI3MR_HOSTTAG_EVTACKCMD_MIN (MPI3MR_HOSTTAG_DEVRMCMD_MAX + 1) 173 #define MPI3MR_HOSTTAG_EVTACKCMD_MAX (MPI3MR_HOSTTAG_EVTACKCMD_MIN + \ 174 MPI3MR_NUM_EVTACKCMD - 1) 175 176 /* command/controller interaction timeout definitions in seconds */ 177 #define MPI3MR_INTADMCMD_TIMEOUT 60 178 #define MPI3MR_PORTENABLE_TIMEOUT 300 179 #define MPI3MR_ABORTTM_TIMEOUT 60 180 #define MPI3MR_RESETTM_TIMEOUT 60 181 #define MPI3MR_TSUPDATE_INTERVAL 900 182 #define MPI3MR_DEFAULT_SHUTDOWN_TIME 120 183 #define MPI3MR_RAID_ERRREC_RESET_TIMEOUT 180 184 #define MPI3MR_RESET_HOST_IOWAIT_TIMEOUT 5 185 #define MPI3MR_PREPARE_FOR_RESET_TIMEOUT 180 186 #define MPI3MR_RESET_ACK_TIMEOUT 30 187 #define MPI3MR_MUR_TIMEOUT 120 188 189 #define MPI3MR_CMD_NOTUSED 0x8000 190 #define MPI3MR_CMD_COMPLETE 0x0001 191 #define MPI3MR_CMD_PENDING 0x0002 192 #define MPI3MR_CMD_REPLYVALID 0x0004 193 #define MPI3MR_CMD_RESET 0x0008 194 195 #define MPI3MR_NUM_EVTREPLIES 64 196 #define MPI3MR_SENSEBUF_SZ 256 197 #define MPI3MR_SENSEBUF_FACTOR 3 198 #define MPI3MR_CHAINBUF_FACTOR 3 199 200 #define MPT3SAS_HOSTPGSZ_4KEXP 12 201 202 #define MPI3MR_INVALID_DEV_HANDLE 0xFFFF 203 204 /* Controller Reset related definitions */ 205 #define MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT 5 206 #define MPI3MR_MAX_SHUTDOWN_RETRY_COUNT 2 207 208 /* ResponseCode values */ 209 #define MPI3MR_RI_MASK_RESPCODE (0x000000FF) 210 #define MPI3MR_RSP_TM_COMPLETE 0x00 211 #define MPI3MR_RSP_INVALID_FRAME 0x02 212 #define MPI3MR_RSP_TM_NOT_SUPPORTED 0x04 213 #define MPI3MR_RSP_TM_FAILED 0x05 214 #define MPI3MR_RSP_TM_SUCCEEDED 0x08 215 #define MPI3MR_RSP_TM_INVALID_LUN 0x09 216 #define MPI3MR_RSP_TM_OVERLAPPED_TAG 0x0A 217 #define MPI3MR_RSP_IO_QUEUED_ON_IOC \ 218 MPI3_SCSITASKMGMT_RSPCODE_IO_QUEUED_ON_IOC 219 220 /* Definitions for the controller security status*/ 221 #define MPI3MR_CTLR_SECURITY_STATUS_MASK 0x0C 222 #define MPI3MR_CTLR_SECURE_DBG_STATUS_MASK 0x02 223 224 #define MPI3MR_INVALID_DEVICE 0x00 225 #define MPI3MR_CONFIG_SECURE_DEVICE 0x04 226 #define MPI3MR_HARD_SECURE_DEVICE 0x08 227 #define MPI3MR_TAMPERED_DEVICE 0x0C 228 229 #define MPI3MR_DEFAULT_MDTS (128 * 1024) 230 #define MPI3MR_DEFAULT_PGSZEXP (12) 231 #define MPI3MR_MAX_IOCTL_TRANSFER_SIZE (1024 * 1024) 232 233 #define MPI3MR_DEVRMHS_RETRYCOUNT 3 234 #define MPI3MR_PELCMDS_RETRYCOUNT 3 235 236 #define MPI3MR_PERIODIC_DELAY 1 /* 1 second heartbeat/watchdog check */ 237 238 #define WRITE_SAME_32 0x0d 239 240 struct completion { 241 unsigned int done; 242 struct mtx lock; 243 }; 244 245 typedef union { 246 volatile unsigned int val; 247 unsigned int val_rdonly; 248 } mpi3mr_atomic_t; 249 250 #define mpi3mr_atomic_read(v) atomic_load_acq_int(&(v)->val) 251 #define mpi3mr_atomic_set(v,i) atomic_store_rel_int(&(v)->val, i) 252 #define mpi3mr_atomic_dec(v) atomic_subtract_int(&(v)->val, 1) 253 #define mpi3mr_atomic_inc(v) atomic_add_int(&(v)->val, 1) 254 #define mpi3mr_atomic_add(v, u) atomic_add_int(&(v)->val, u) 255 #define mpi3mr_atomic_sub(v, u) atomic_subtract_int(&(v)->val, u) 256 257 /* IOCTL data transfer sge*/ 258 #define MPI3MR_NUM_IOCTL_SGE 256 259 #define MPI3MR_IOCTL_SGE_SIZE (8 * 1024) 260 261 struct dma_memory_desc { 262 U32 size; 263 void *addr; 264 bus_dma_tag_t tag; 265 bus_dmamap_t dmamap; 266 bus_addr_t dma_addr; 267 }; 268 269 enum mpi3mr_iocstate { 270 MRIOC_STATE_READY = 1, 271 MRIOC_STATE_RESET, 272 MRIOC_STATE_FAULT, 273 MRIOC_STATE_BECOMING_READY, 274 MRIOC_STATE_RESET_REQUESTED, 275 MRIOC_STATE_UNRECOVERABLE, 276 MRIOC_STATE_COUNT, 277 }; 278 279 /* Init type definitions */ 280 enum mpi3mr_init_type { 281 MPI3MR_INIT_TYPE_INIT = 0, 282 MPI3MR_INIT_TYPE_RESET, 283 MPI3MR_INIT_TYPE_RESUME, 284 }; 285 286 /* Reset reason code definitions*/ 287 enum mpi3mr_reset_reason { 288 MPI3MR_RESET_FROM_BRINGUP = 1, 289 MPI3MR_RESET_FROM_FAULT_WATCH = 2, 290 MPI3MR_RESET_FROM_IOCTL = 3, 291 MPI3MR_RESET_FROM_EH_HOS = 4, 292 MPI3MR_RESET_FROM_TM_TIMEOUT = 5, 293 MPI3MR_RESET_FROM_IOCTL_TIMEOUT = 6, 294 MPI3MR_RESET_FROM_MUR_FAILURE = 7, 295 MPI3MR_RESET_FROM_CTLR_CLEANUP = 8, 296 MPI3MR_RESET_FROM_CIACTIV_FAULT = 9, 297 MPI3MR_RESET_FROM_PE_TIMEOUT = 10, 298 MPI3MR_RESET_FROM_TSU_TIMEOUT = 11, 299 MPI3MR_RESET_FROM_DELREQQ_TIMEOUT = 12, 300 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT = 13, 301 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT = 14, 302 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT = 15, 303 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT = 16, 304 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT = 17, 305 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT = 18, 306 MPI3MR_RESET_FROM_EVTACK_TIMEOUT = 19, 307 MPI3MR_RESET_FROM_CIACTVRST_TIMER = 20, 308 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT = 21, 309 MPI3MR_RESET_FROM_PELABORT_TIMEOUT = 22, 310 MPI3MR_RESET_FROM_SYSFS = 23, 311 MPI3MR_RESET_FROM_SYSFS_TIMEOUT = 24, 312 MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT = 25, 313 MPI3MR_RESET_FROM_SCSIIO_TIMEOUT = 26, 314 MPI3MR_RESET_FROM_FIRMWARE = 27, 315 MPI3MR_DEFAULT_RESET_REASON = 28, 316 MPI3MR_RESET_REASON_COUNT, 317 }; 318 319 struct mpi3mr_compimg_ver 320 { 321 U16 build_num; 322 U16 cust_id; 323 U8 ph_minor; 324 U8 ph_major; 325 U8 gen_minor; 326 U8 gen_major; 327 }; 328 329 struct mpi3mr_ioc_facts 330 { 331 U32 ioc_capabilities; 332 struct mpi3mr_compimg_ver fw_ver; 333 U32 mpi_version; 334 U16 max_reqs; 335 U16 product_id; 336 U16 op_req_sz; 337 U16 reply_sz; 338 U16 exceptions; 339 U16 max_perids; 340 U16 max_pds; 341 U16 max_sasexpanders; 342 U32 max_data_length; 343 U16 max_sasinitiators; 344 U16 max_enclosures; 345 U16 max_pcieswitches; 346 U16 max_nvme; 347 U16 max_vds; 348 U16 max_hpds; 349 U16 max_advhpds; 350 U16 max_raidpds; 351 U16 min_devhandle; 352 U16 max_devhandle; 353 U16 max_op_req_q; 354 U16 max_op_reply_q; 355 U16 shutdown_timeout; 356 U8 ioc_num; 357 U8 who_init; 358 U16 max_msix_vectors; 359 U8 personality; 360 U8 dma_mask; 361 U8 protocol_flags; 362 U8 sge_mod_mask; 363 U8 sge_mod_value; 364 U8 sge_mod_shift; 365 U8 max_dev_per_tg; 366 U16 max_io_throttle_group; 367 U16 io_throttle_data_length; 368 U16 io_throttle_low; 369 U16 io_throttle_high; 370 }; 371 372 struct mpi3mr_op_req_queue { 373 U16 ci; 374 U16 pi; 375 U16 num_reqs; 376 U8 qid; 377 U8 reply_qid; 378 U32 qsz; 379 void *q_base; 380 bus_dma_tag_t q_base_tag; 381 bus_dmamap_t q_base_dmamap; 382 bus_addr_t q_base_phys; 383 struct mtx q_lock; 384 }; 385 386 struct mpi3mr_op_reply_queue { 387 U16 ci; 388 U8 ephase; 389 U8 qid; 390 U16 num_replies; 391 U32 qsz; 392 bus_dma_tag_t q_base_tag; 393 bus_dmamap_t q_base_dmamap; 394 void *q_base; 395 bus_addr_t q_base_phys; 396 mpi3mr_atomic_t pend_ios; 397 bool in_use; 398 struct mtx q_lock; 399 }; 400 401 struct irq_info { 402 MPI3_REPLY_DESCRIPTORS_UNION *post_queue; 403 bus_dma_tag_t buffer_dmat; 404 struct resource *irq; 405 void *intrhand; 406 int irq_rid; 407 }; 408 409 struct mpi3mr_irq_context { 410 struct mpi3mr_softc *sc; 411 U16 msix_index; 412 struct mpi3mr_op_reply_queue *op_reply_q; 413 char name[MPI3MR_NAME_LENGTH]; 414 struct irq_info irq_info; 415 }; 416 417 MALLOC_DECLARE(M_MPI3MR); 418 SYSCTL_DECL(_hw_mpi3mr); 419 420 typedef struct mpi3mr_drvr_cmd DRVR_CMD; 421 typedef void (*DRVR_CMD_CALLBACK)(struct mpi3mr_softc *mrioc, DRVR_CMD *drvrcmd); 422 struct mpi3mr_drvr_cmd { 423 struct mtx lock; 424 struct completion completion; 425 void *reply; 426 U8 *sensebuf; 427 U8 iou_rc; 428 U16 state; 429 U16 dev_handle; 430 U16 ioc_status; 431 U32 ioc_loginfo; 432 U8 is_waiting; 433 U8 is_senseprst; 434 U8 retry_count; 435 U16 host_tag; 436 DRVR_CMD_CALLBACK callback; 437 }; 438 439 struct mpi3mr_cmd; 440 typedef void mpi3mr_evt_callback_t(struct mpi3mr_softc *, uintptr_t, 441 Mpi3EventNotificationReply_t *reply); 442 typedef void mpi3mr_cmd_callback_t(struct mpi3mr_softc *, 443 struct mpi3mr_cmd *cmd); 444 445 #define MPI3MR_IOVEC_COUNT 2 446 447 enum mpi3mr_data_xfer_direction { 448 MPI3MR_READ = 1, 449 MPI3MR_WRITE, 450 }; 451 452 enum mpi3mr_cmd_state { 453 MPI3MR_CMD_STATE_FREE = 1, 454 MPI3MR_CMD_STATE_BUSY, 455 MPI3MR_CMD_STATE_IN_QUEUE, 456 MPI3MR_CMD_STATE_IN_TM, 457 }; 458 459 enum mpi3mr_target_state { 460 MPI3MR_DEV_CREATED = 1, 461 MPI3MR_DEV_REMOVE_HS_COMPLETED = 2, 462 }; 463 464 struct mpi3mr_cmd { 465 TAILQ_ENTRY(mpi3mr_cmd) next; 466 struct mpi3mr_softc *sc; 467 union ccb *ccb; 468 void *data; 469 u_int length; 470 struct mpi3mr_target *targ; 471 u_int data_dir; 472 u_int state; 473 bus_dmamap_t dmamap; 474 struct scsi_sense_data *sense; 475 struct callout callout; 476 bool callout_owner; 477 U16 hosttag; 478 U8 req_qidx; 479 Mpi3SCSIIORequest_t io_request; 480 }; 481 482 struct mpi3mr_chain { 483 bus_dmamap_t buf_dmamap; 484 void *buf; 485 bus_addr_t buf_phys; 486 }; 487 488 struct mpi3mr_event_handle { 489 TAILQ_ENTRY(mpi3mr_event_handle) eh_list; 490 mpi3mr_evt_callback_t *callback; 491 void *data; 492 uint8_t mask[16]; 493 }; 494 495 struct mpi3mr_fw_event_work { 496 U16 event; 497 void *event_data; 498 TAILQ_ENTRY(mpi3mr_fw_event_work) ev_link; 499 U8 send_ack; 500 U8 process_event; 501 U32 event_context; 502 U16 event_data_size; 503 }; 504 505 /** 506 * struct delayed_dev_rmhs_node - Delayed device removal node 507 * 508 * @list: list head 509 * @handle: Device handle 510 * @iou_rc: IO Unit Control Reason Code 511 */ 512 struct delayed_dev_rmhs_node { 513 TAILQ_ENTRY(delayed_dev_rmhs_node) list; 514 U16 handle; 515 U8 iou_rc; 516 }; 517 518 /** 519 * struct delayed_evtack_node - Delayed event ack node 520 * 521 * @list: list head 522 * @event: MPI3 event ID 523 * @event_ctx: Event context 524 */ 525 struct delayed_evtack_node { 526 TAILQ_ENTRY(delayed_evtack_node) list; 527 U8 event; 528 U32 event_ctx; 529 }; 530 531 /* Reset types */ 532 enum reset_type { 533 MPI3MR_NO_RESET, 534 MPI3MR_TRIGGER_SOFT_RESET, 535 }; 536 537 struct mpi3mr_reset { 538 u_int type; 539 U32 reason; 540 int status; 541 bool ioctl_reset_snapdump; 542 }; 543 544 struct mpi3mr_softc { 545 device_t mpi3mr_dev; 546 struct cdev *mpi3mr_cdev; 547 u_int mpi3mr_flags; 548 #define MPI3MR_FLAGS_SHUTDOWN (1 << 0) 549 #define MPI3MR_FLAGS_DIAGRESET (1 << 1) 550 #define MPI3MR_FLAGS_ATTACH_DONE (1 << 2) 551 #define MPI3MR_FLAGS_PORT_ENABLE_DONE (1 << 3) 552 U8 id; 553 int cpu_count; 554 char name[MPI3MR_NAME_LENGTH]; 555 char driver_name[MPI3MR_NAME_LENGTH]; 556 int bars; 557 bus_addr_t dma_loaddr; 558 u_int mpi3mr_debug; 559 struct mpi3mr_reset reset; 560 int max_msix_vectors; 561 int msix_count; 562 bool msix_enable; 563 int io_cmds_highwater; 564 int max_chains; 565 uint32_t chain_frame_size; 566 struct sysctl_ctx_list sysctl_ctx; 567 struct sysctl_oid *sysctl_tree; 568 char fw_version[32]; 569 struct mpi3mr_chain *chains; 570 struct callout periodic; 571 struct callout device_check_callout; 572 573 struct mpi3mr_cam_softc *cam_sc; 574 struct mpi3mr_cmd **cmd_list; 575 TAILQ_HEAD(, mpi3mr_cmd) cmd_list_head; 576 struct mtx cmd_pool_lock; 577 578 struct resource *mpi3mr_regs_resource; 579 bus_space_handle_t mpi3mr_bhandle; 580 bus_space_tag_t mpi3mr_btag; 581 int mpi3mr_regs_rid; 582 583 bus_dma_tag_t mpi3mr_parent_dmat; 584 bus_dma_tag_t buffer_dmat; 585 586 int num_reqs; 587 int num_replies; 588 int num_chains; 589 590 TAILQ_HEAD(, mpi3mr_event_handle) event_list; 591 struct mpi3mr_event_handle *mpi3mr_log_eh; 592 struct intr_config_hook mpi3mr_ich; 593 594 struct mtx mpi3mr_mtx; 595 struct mtx io_lock; 596 U8 intr_enabled; 597 TAILQ_HEAD(, delayed_dev_rmhs_node) delayed_rmhs_list; 598 TAILQ_HEAD(, delayed_evtack_node) delayed_evtack_cmds_list; 599 600 U16 num_admin_reqs; 601 U32 admin_req_q_sz; 602 U16 admin_req_pi; 603 U16 admin_req_ci; 604 bus_dma_tag_t admin_req_tag; 605 bus_dmamap_t admin_req_dmamap; 606 bus_addr_t admin_req_phys; 607 U8 *admin_req; 608 struct mtx admin_req_lock; 609 610 U16 num_admin_replies; 611 U32 admin_reply_q_sz; 612 U16 admin_reply_ci; 613 U8 admin_reply_ephase; 614 bus_dma_tag_t admin_reply_tag; 615 bus_dmamap_t admin_reply_dmamap; 616 bus_addr_t admin_reply_phys; 617 U8 *admin_reply; 618 struct mtx admin_reply_lock; 619 bool admin_in_use; 620 621 U32 num_reply_bufs; 622 bus_dma_tag_t reply_buf_tag; 623 bus_dmamap_t reply_buf_dmamap; 624 bus_addr_t reply_buf_phys; 625 U8 *reply_buf; 626 bus_addr_t reply_buf_dma_max_address; 627 bus_addr_t reply_buf_dma_min_address; 628 629 U16 reply_free_q_sz; 630 bus_dma_tag_t reply_free_q_tag; 631 bus_dmamap_t reply_free_q_dmamap; 632 bus_addr_t reply_free_q_phys; 633 U64 *reply_free_q; 634 struct mtx reply_free_q_lock; 635 U32 reply_free_q_host_index; 636 637 U32 num_sense_bufs; 638 bus_dma_tag_t sense_buf_tag; 639 bus_dmamap_t sense_buf_dmamap; 640 bus_addr_t sense_buf_phys; 641 U8 *sense_buf; 642 643 U16 sense_buf_q_sz; 644 bus_dma_tag_t sense_buf_q_tag; 645 bus_dmamap_t sense_buf_q_dmamap; 646 bus_addr_t sense_buf_q_phys; 647 U64 *sense_buf_q; 648 struct mtx sense_buf_q_lock; 649 U32 sense_buf_q_host_index; 650 651 void *nvme_encap_prp_list; 652 bus_addr_t nvme_encap_prp_list_dma; 653 bus_dma_tag_t nvme_encap_prp_list_dmatag; 654 bus_dmamap_t nvme_encap_prp_list_dma_dmamap; 655 U32 nvme_encap_prp_sz; 656 657 U32 ready_timeout; 658 659 struct mpi3mr_irq_context *irq_ctx; 660 661 U16 num_queues; /* Number of request/reply queues */ 662 struct mpi3mr_op_req_queue *op_req_q; 663 struct mpi3mr_op_reply_queue *op_reply_q; 664 U16 num_hosttag_op_req_q; 665 666 struct mpi3mr_drvr_cmd init_cmds; 667 struct mpi3mr_ioc_facts facts; 668 U16 reply_sz; 669 U16 op_reply_sz; 670 671 U32 event_masks[MPI3_EVENT_NOTIFY_EVENTMASK_WORDS]; 672 673 char fwevt_worker_name[MPI3MR_NAME_LENGTH]; 674 struct workqueue_struct *fwevt_worker_thread; 675 struct mtx fwevt_lock; 676 struct mtx target_lock; 677 678 U16 max_host_ios; 679 U32 max_sgl_entries; 680 bus_dma_tag_t chain_sgl_list_tag; 681 struct mpi3mr_chain *chain_sgl_list; 682 U16 chain_bitmap_sz; 683 void *chain_bitmap; 684 struct mtx chain_buf_lock; 685 U16 chain_buf_count; 686 687 struct mpi3mr_drvr_cmd ioctl_cmds; 688 struct mpi3mr_drvr_cmd host_tm_cmds; 689 struct mpi3mr_drvr_cmd dev_rmhs_cmds[MPI3MR_NUM_DEVRMCMD]; 690 struct mpi3mr_drvr_cmd evtack_cmds[MPI3MR_NUM_EVTACKCMD]; 691 692 U16 devrem_bitmap_sz; 693 void *devrem_bitmap; 694 695 U16 dev_handle_bitmap_sz; 696 void *removepend_bitmap; 697 698 U16 evtack_cmds_bitmap_sz; 699 void *evtack_cmds_bitmap; 700 701 U32 ts_update_counter; 702 U8 reset_in_progress; 703 U8 unrecoverable; 704 U8 block_ioctls; 705 U8 in_prep_ciactv_rst; 706 U16 prep_ciactv_rst_counter; 707 struct mtx reset_mutex; 708 709 U8 prepare_for_reset; 710 U16 prepare_for_reset_timeout_counter; 711 712 U16 diagsave_timeout; 713 int logging_level; 714 U16 flush_io_count; 715 716 Mpi3DriverInfoLayout_t driver_info; 717 718 U16 change_count; 719 720 U8 *log_data_buffer; 721 U16 log_data_buffer_index; 722 U16 log_data_entry_size; 723 724 U8 pel_wait_pend; 725 U8 pel_abort_requested; 726 U8 pel_class; 727 U16 pel_locale; 728 729 struct mpi3mr_drvr_cmd pel_cmds; 730 struct mpi3mr_drvr_cmd pel_abort_cmd; 731 U32 newest_seqnum; 732 void *pel_seq_number; 733 bus_addr_t pel_seq_number_dma; 734 bus_dma_tag_t pel_seq_num_dmatag; 735 bus_dmamap_t pel_seq_num_dmamap; 736 U32 pel_seq_number_sz; 737 738 struct selinfo mpi3mr_select; 739 U32 mpi3mr_poll_waiting; 740 U32 mpi3mr_aen_triggered; 741 742 U16 wait_for_port_enable; 743 U16 track_mapping_events; 744 U16 pending_map_events; 745 mpi3mr_atomic_t fw_outstanding; 746 mpi3mr_atomic_t pend_ioctls; 747 struct proc *watchdog_thread; 748 void *watchdog_chan; 749 void *tm_chan; 750 u_int8_t remove_in_progress; 751 u_int8_t watchdog_thread_active; 752 u_int8_t do_timedout_reset; 753 bool allow_ios; 754 bool secure_ctrl; 755 mpi3mr_atomic_t pend_large_data_sz; 756 757 u_int32_t io_throttle_data_length; 758 u_int32_t io_throttle_high; 759 u_int32_t io_throttle_low; 760 u_int16_t num_io_throttle_group; 761 u_int iot_enable; 762 struct mpi3mr_throttle_group_info *throttle_groups; 763 764 struct dma_memory_desc ioctl_sge[MPI3MR_NUM_IOCTL_SGE]; 765 struct dma_memory_desc ioctl_chain_sge; 766 struct dma_memory_desc ioctl_resp_sge; 767 bool ioctl_sges_allocated; 768 }; 769 770 static __inline uint64_t 771 mpi3mr_regread64(struct mpi3mr_softc *sc, uint32_t offset) 772 { 773 return bus_space_read_8(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset); 774 } 775 776 static __inline void 777 mpi3mr_regwrite64(struct mpi3mr_softc *sc, uint32_t offset, uint64_t val) 778 { 779 bus_space_write_8(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset, val); 780 } 781 782 static __inline uint32_t 783 mpi3mr_regread(struct mpi3mr_softc *sc, uint32_t offset) 784 { 785 return bus_space_read_4(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset); 786 } 787 788 static __inline void 789 mpi3mr_regwrite(struct mpi3mr_softc *sc, uint32_t offset, uint32_t val) 790 { 791 bus_space_write_4(sc->mpi3mr_btag, sc->mpi3mr_bhandle, offset, val); 792 } 793 794 #define MPI3MR_INFO (1 << 0) /* Basic info */ 795 #define MPI3MR_FAULT (1 << 1) /* Hardware faults */ 796 #define MPI3MR_EVENT (1 << 2) /* Event data from the controller */ 797 #define MPI3MR_LOG (1 << 3) /* Log data from the controller */ 798 #define MPI3MR_RECOVERY (1 << 4) /* Command error recovery tracing */ 799 #define MPI3MR_ERROR (1 << 5) /* Fatal driver/OS APIs failure */ 800 #define MPI3MR_XINFO (1 << 6) /* Additional info logs*/ 801 #define MPI3MR_TRACE (1 << 7) /* Trace functions */ 802 #define MPI3MR_IOT (1 << 8) /* IO throttling related debugs */ 803 #define MPI3MR_DEBUG_TM (1 << 9) /* Task management related debugs */ 804 #define MPI3MR_DEBUG_IOCTL (1 << 10) /* IOCTL related debugs */ 805 806 #define mpi3mr_printf(sc, args...) \ 807 device_printf((sc)->mpi3mr_dev, ##args) 808 809 #define mpi3mr_print_field(sc, msg, args...) \ 810 printf("\t" msg, ##args) 811 812 #define mpi3mr_vprintf(sc, args...) \ 813 do { \ 814 if (bootverbose) \ 815 mpi3mr_printf(sc, ##args); \ 816 } while (0) 817 818 #define mpi3mr_dprint(sc, level, msg, args...) \ 819 do { \ 820 if ((sc)->mpi3mr_debug & (level)) \ 821 device_printf((sc)->mpi3mr_dev, msg, ##args); \ 822 } while (0) 823 824 #define MPI3MR_PRINTFIELD_START(sc, tag...) \ 825 mpi3mr_printf((sc), ##tag); \ 826 mpi3mr_print_field((sc), ":\n") 827 #define MPI3MR_PRINTFIELD_END(sc, tag) \ 828 mpi3mr_printf((sc), tag "\n") 829 #define MPI3MR_PRINTFIELD(sc, facts, attr, fmt) \ 830 mpi3mr_print_field((sc), #attr ": " #fmt "\n", (facts)->attr) 831 832 #define mpi3mr_kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) \ 833 kproc_create(func, farg, proc_ptr, flags, stackpgs, fmtstr, arg) 834 #define mpi3mr_kproc_exit(arg) kproc_exit(arg) 835 836 #if defined(CAM_PRIORITY_XPT) 837 #define MPI3MR_PRIORITY_XPT CAM_PRIORITY_XPT 838 #else 839 #define MPI3MR_PRIORITY_XPT 5 840 #endif 841 842 static __inline void 843 mpi3mr_clear_bit(int b, volatile void *p) 844 { 845 atomic_clear_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 846 } 847 848 static __inline void 849 mpi3mr_set_bit(int b, volatile void *p) 850 { 851 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 852 } 853 854 static __inline int 855 mpi3mr_test_bit(int b, volatile void *p) 856 { 857 return ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f)); 858 } 859 860 static __inline int 861 mpi3mr_test_and_set_bit(int b, volatile void *p) 862 { 863 int ret = ((volatile int *)p)[b >> 5] & (1 << (b & 0x1f)); 864 865 atomic_set_int(((volatile int *)p) + (b >> 5), 1 << (b & 0x1f)); 866 return ret; 867 } 868 869 static __inline int 870 mpi3mr_find_first_zero_bit(void *p, int bit_count) 871 { 872 int i, sz, j=0; 873 U8 *loc; 874 875 sz = bit_count % 8 ? (bit_count / 8 + 1) : (bit_count / 8); 876 loc = malloc(sz, M_MPI3MR, M_NOWAIT | M_ZERO); 877 878 memcpy(loc, p, sz); 879 880 for (i = 0; i < sz; i++) { 881 j = 0; 882 while (j < 8) { 883 if (!((loc[i] >> j) & 0x1)) 884 goto out; 885 j++; 886 } 887 } 888 out: 889 free(loc, M_MPI3MR); 890 return (i + j); 891 } 892 893 #define MPI3MR_DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d)) 894 895 void 896 init_completion(struct completion *completion); 897 898 void 899 complete(struct completion *completion); 900 901 void wait_for_completion_timeout(struct completion *completion, 902 U32 timeout); 903 void wait_for_completion_timeout_tm(struct completion *completion, 904 U32 timeout, struct mpi3mr_softc *sc); 905 void mpi3mr_add_sg_single(void *paddr, U8 flags, U32 length, 906 bus_addr_t dma_addr); 907 void mpi3mr_enable_interrupts(struct mpi3mr_softc *sc); 908 void mpi3mr_disable_interrupts(struct mpi3mr_softc *sc); 909 void mpi3mr_memaddr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error); 910 int mpi3mr_submit_admin_cmd(struct mpi3mr_softc *mrioc, void *admin_req, 911 U16 admin_req_sz); 912 int mpi3mr_submit_io(struct mpi3mr_softc *mrioc, 913 struct mpi3mr_op_req_queue *op_req_q, U8 *req); 914 int 915 mpi3mr_alloc_interrupts(struct mpi3mr_softc *sc, U16 setup_one); 916 917 void mpi3mr_cleanup_ioc(struct mpi3mr_softc *sc); 918 int mpi3mr_initialize_ioc(struct mpi3mr_softc *sc, U8 reason); 919 void mpi3mr_build_zero_len_sge(void *paddr); 920 int mpi3mr_issue_event_notification(struct mpi3mr_softc *sc); 921 int 922 mpi3mr_register_events(struct mpi3mr_softc *sc); 923 void mpi3mr_process_op_reply_desc(struct mpi3mr_softc *sc, 924 Mpi3DefaultReplyDescriptor_t *reply_desc, U64 *reply_dma); 925 struct mpi3mr_cmd * 926 mpi3mr_get_command(struct mpi3mr_softc *sc); 927 void 928 mpi3mr_release_command(struct mpi3mr_cmd *cmd); 929 int 930 mpi3mr_complete_io_cmd(struct mpi3mr_softc *sc, 931 struct mpi3mr_irq_context *irq_context); 932 int 933 mpi3mr_cam_detach(struct mpi3mr_softc *sc); 934 int 935 mpi3mr_cam_attach(struct mpi3mr_softc *sc); 936 struct mpi3mr_target * 937 mpi3mr_find_target_by_per_id(struct mpi3mr_cam_softc *cam_sc, 938 uint16_t per_id); 939 struct mpi3mr_target * 940 mpi3mr_find_target_by_dev_handle(struct mpi3mr_cam_softc *cam_sc, 941 uint16_t dev_handle); 942 int mpi3mr_create_device(struct mpi3mr_softc *sc, 943 Mpi3DevicePage0_t *dev_pg0); 944 void 945 mpi3mr_unmap_request(struct mpi3mr_softc *sc, struct mpi3mr_cmd *cmd); 946 void 947 init_completion(struct completion *completion); 948 void 949 complete(struct completion *completion); 950 void wait_for_completion_timeout(struct completion *completion, 951 U32 timeout); 952 void 953 poll_for_command_completion(struct mpi3mr_softc *sc, 954 struct mpi3mr_drvr_cmd *cmd, U16 wait); 955 int 956 mpi3mr_alloc_requests(struct mpi3mr_softc *sc); 957 void 958 mpi3mr_watchdog(void *arg); 959 int mpi3mr_issue_port_enable(struct mpi3mr_softc *mrioc, U8 async); 960 void 961 mpi3mr_isr(void *privdata); 962 int 963 mpi3mr_alloc_msix_queues(struct mpi3mr_softc *sc); 964 void 965 mpi3mr_destory_mtx(struct mpi3mr_softc *sc); 966 void 967 mpi3mr_free_mem(struct mpi3mr_softc *sc); 968 void 969 mpi3mr_cleanup_interrupts(struct mpi3mr_softc *sc); 970 int mpi3mr_setup_irqs(struct mpi3mr_softc *sc); 971 void mpi3mr_cleanup_event_taskq(struct mpi3mr_softc *sc); 972 void 973 mpi3mr_hexdump(void *buf, int sz, int format); 974 int mpi3mr_soft_reset_handler(struct mpi3mr_softc *sc, 975 U16 reset_reason, bool snapdump); 976 void 977 mpi3mrsas_release_simq_reinit(struct mpi3mr_cam_softc *cam_sc); 978 void 979 mpi3mr_watchdog_thread(void *arg); 980 void mpi3mr_add_device(struct mpi3mr_softc *sc, U16 per_id); 981 int mpi3mr_remove_device(struct mpi3mr_softc *sc, U16 handle); 982 int 983 mpi3mrsas_register_events(struct mpi3mr_softc *sc); 984 int mpi3mr_process_event_ack(struct mpi3mr_softc *sc, U8 event, 985 U32 event_ctx); 986 int mpi3mr_remove_device_from_os(struct mpi3mr_softc *sc, U16 handle); 987 void mpi3mr_remove_device_from_list(struct mpi3mr_softc *sc, struct mpi3mr_target *target, 988 bool must_delete); 989 void mpi3mr_update_device(struct mpi3mr_softc *mrioc, 990 struct mpi3mr_target *tgtdev, Mpi3DevicePage0_t *dev_pg0, bool is_added); 991 void mpi3mr_app_save_logdata(struct mpi3mr_softc *sc, char *event_data, U16 event_data_size); 992 void mpi3mr_set_io_divert_for_all_vd_in_tg(struct mpi3mr_softc *sc, 993 struct mpi3mr_throttle_group_info *tg, U8 divert_value); 994 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_softc *sc); 995 void mpi3mr_poll_pend_io_completions(struct mpi3mr_softc *sc); 996 void int_to_lun(unsigned int lun, U8 *req_lun); 997 void trigger_reset_from_watchdog(struct mpi3mr_softc *sc, U8 reset_type, U16 reset_reason); 998 void mpi3mr_alloc_ioctl_dma_memory(struct mpi3mr_softc *sc); 999 #endif /*MPI3MR_H_INCLUDED*/ 1000