1 /* 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016-2023, Broadcom Inc. All rights reserved. 5 * Support: <fbsd-storage-driver.pdl@broadcom.com> 6 * 7 * Authors: Sumit Saxena <sumit.saxena@broadcom.com> 8 * Chandrakanth Patil <chandrakanth.patil@broadcom.com> 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions are 12 * met: 13 * 14 * 1. Redistributions of source code must retain the above copyright notice, 15 * this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright notice, 17 * this list of conditions and the following disclaimer in the documentation and/or other 18 * materials provided with the distribution. 19 * 3. Neither the name of the Broadcom Inc. nor the names of its contributors 20 * may be used to endorse or promote products derived from this software without 21 * specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 33 * POSSIBILITY OF SUCH DAMAGE. 34 * 35 * The views and conclusions contained in the software and documentation are 36 * those of the authors and should not be interpreted as representing 37 * official policies,either expressed or implied, of the FreeBSD Project. 38 * 39 * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 40 * 41 * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD 42 */ 43 44 #include <sys/types.h> 45 #include <sys/param.h> 46 #include <sys/systm.h> 47 #include <sys/kernel.h> 48 #include <sys/module.h> 49 #include <sys/bus.h> 50 #include <sys/conf.h> 51 #include <sys/malloc.h> 52 #include <sys/sysctl.h> 53 #include <sys/uio.h> 54 55 #include <machine/bus.h> 56 #include <machine/resource.h> 57 #include <sys/rman.h> 58 59 #include <dev/pci/pcireg.h> 60 #include <dev/pci/pcivar.h> 61 #include <dev/pci/pci_private.h> 62 63 #include <cam/cam.h> 64 #include <cam/cam_ccb.h> 65 #include <cam/cam_debug.h> 66 #include <cam/cam_sim.h> 67 #include <cam/cam_xpt_sim.h> 68 #include <cam/cam_xpt_periph.h> 69 #include <cam/cam_periph.h> 70 #include <cam/scsi/scsi_all.h> 71 #include <cam/scsi/scsi_message.h> 72 #include <cam/scsi/smp_all.h> 73 #include <sys/queue.h> 74 #include <sys/kthread.h> 75 #include "mpi3mr.h" 76 #include "mpi3mr_cam.h" 77 #include "mpi3mr_app.h" 78 79 static void mpi3mr_repost_reply_buf(struct mpi3mr_softc *sc, 80 U64 reply_dma); 81 static int mpi3mr_complete_admin_cmd(struct mpi3mr_softc *sc); 82 static void mpi3mr_port_enable_complete(struct mpi3mr_softc *sc, 83 struct mpi3mr_drvr_cmd *drvrcmd); 84 static void mpi3mr_flush_io(struct mpi3mr_softc *sc); 85 static int mpi3mr_issue_reset(struct mpi3mr_softc *sc, U16 reset_type, 86 U32 reset_reason); 87 static void mpi3mr_dev_rmhs_send_tm(struct mpi3mr_softc *sc, U16 handle, 88 struct mpi3mr_drvr_cmd *cmdparam, U8 iou_rc); 89 static void mpi3mr_dev_rmhs_complete_iou(struct mpi3mr_softc *sc, 90 struct mpi3mr_drvr_cmd *drv_cmd); 91 static void mpi3mr_dev_rmhs_complete_tm(struct mpi3mr_softc *sc, 92 struct mpi3mr_drvr_cmd *drv_cmd); 93 static void mpi3mr_send_evt_ack(struct mpi3mr_softc *sc, U8 event, 94 struct mpi3mr_drvr_cmd *cmdparam, U32 event_ctx); 95 static void mpi3mr_print_fault_info(struct mpi3mr_softc *sc); 96 static inline void mpi3mr_set_diagsave(struct mpi3mr_softc *sc); 97 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code); 98 99 void 100 mpi3mr_hexdump(void *buf, int sz, int format) 101 { 102 int i; 103 U32 *buf_loc = (U32 *)buf; 104 105 for (i = 0; i < (sz / sizeof(U32)); i++) { 106 if ((i % format) == 0) { 107 if (i != 0) 108 printf("\n"); 109 printf("%08x: ", (i * 4)); 110 } 111 printf("%08x ", buf_loc[i]); 112 } 113 printf("\n"); 114 } 115 116 void 117 init_completion(struct completion *completion) 118 { 119 completion->done = 0; 120 } 121 122 void 123 complete(struct completion *completion) 124 { 125 completion->done = 1; 126 wakeup(complete); 127 } 128 129 void wait_for_completion_timeout(struct completion *completion, 130 U32 timeout) 131 { 132 U32 count = timeout * 1000; 133 134 while ((completion->done == 0) && count) { 135 DELAY(1000); 136 count--; 137 } 138 139 if (completion->done == 0) { 140 printf("%s: Command is timedout\n", __func__); 141 completion->done = 1; 142 } 143 } 144 void wait_for_completion_timeout_tm(struct completion *completion, 145 U32 timeout, struct mpi3mr_softc *sc) 146 { 147 U32 count = timeout * 1000; 148 149 while ((completion->done == 0) && count) { 150 msleep(&sc->tm_chan, &sc->mpi3mr_mtx, PRIBIO, 151 "TM command", 1 * hz); 152 count--; 153 } 154 155 if (completion->done == 0) { 156 printf("%s: Command is timedout\n", __func__); 157 completion->done = 1; 158 } 159 } 160 161 162 void 163 poll_for_command_completion(struct mpi3mr_softc *sc, 164 struct mpi3mr_drvr_cmd *cmd, U16 wait) 165 { 166 int wait_time = wait * 1000; 167 while (wait_time) { 168 mpi3mr_complete_admin_cmd(sc); 169 if (cmd->state & MPI3MR_CMD_COMPLETE) 170 break; 171 DELAY(1000); 172 wait_time--; 173 } 174 } 175 176 /** 177 * mpi3mr_trigger_snapdump - triggers firmware snapdump 178 * @sc: Adapter instance reference 179 * @reason_code: reason code for the fault. 180 * 181 * This routine will trigger the snapdump and wait for it to 182 * complete or timeout before it returns. 183 * This will be called during initilaization time faults/resets/timeouts 184 * before soft reset invocation. 185 * 186 * Return: None. 187 */ 188 static void 189 mpi3mr_trigger_snapdump(struct mpi3mr_softc *sc, U32 reason_code) 190 { 191 U32 host_diagnostic, timeout = MPI3_SYSIF_DIAG_SAVE_TIMEOUT * 10; 192 193 mpi3mr_dprint(sc, MPI3MR_INFO, "snapdump triggered: reason code: %s\n", 194 mpi3mr_reset_rc_name(reason_code)); 195 196 mpi3mr_set_diagsave(sc); 197 mpi3mr_issue_reset(sc, MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, 198 reason_code); 199 200 do { 201 host_diagnostic = mpi3mr_regread(sc, MPI3_SYSIF_HOST_DIAG_OFFSET); 202 if (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS)) 203 break; 204 DELAY(100 * 1000); 205 } while (--timeout); 206 207 return; 208 } 209 210 /** 211 * mpi3mr_check_rh_fault_ioc - check reset history and fault 212 * controller 213 * @sc: Adapter instance reference 214 * @reason_code, reason code for the fault. 215 * 216 * This routine will fault the controller with 217 * the given reason code if it is not already in the fault or 218 * not asynchronosuly reset. This will be used to handle 219 * initilaization time faults/resets/timeout as in those cases 220 * immediate soft reset invocation is not required. 221 * 222 * Return: None. 223 */ 224 static void mpi3mr_check_rh_fault_ioc(struct mpi3mr_softc *sc, U32 reason_code) 225 { 226 U32 ioc_status; 227 228 if (sc->unrecoverable) { 229 mpi3mr_dprint(sc, MPI3MR_ERROR, "controller is unrecoverable\n"); 230 return; 231 } 232 233 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 234 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) || 235 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) { 236 mpi3mr_print_fault_info(sc); 237 return; 238 } 239 240 mpi3mr_trigger_snapdump(sc, reason_code); 241 242 return; 243 } 244 245 static void * mpi3mr_get_reply_virt_addr(struct mpi3mr_softc *sc, 246 bus_addr_t phys_addr) 247 { 248 if (!phys_addr) 249 return NULL; 250 if ((phys_addr < sc->reply_buf_dma_min_address) || 251 (phys_addr > sc->reply_buf_dma_max_address)) 252 return NULL; 253 254 return sc->reply_buf + (phys_addr - sc->reply_buf_phys); 255 } 256 257 static void * mpi3mr_get_sensebuf_virt_addr(struct mpi3mr_softc *sc, 258 bus_addr_t phys_addr) 259 { 260 if (!phys_addr) 261 return NULL; 262 return sc->sense_buf + (phys_addr - sc->sense_buf_phys); 263 } 264 265 static void mpi3mr_repost_reply_buf(struct mpi3mr_softc *sc, 266 U64 reply_dma) 267 { 268 U32 old_idx = 0; 269 270 mtx_lock_spin(&sc->reply_free_q_lock); 271 old_idx = sc->reply_free_q_host_index; 272 sc->reply_free_q_host_index = ((sc->reply_free_q_host_index == 273 (sc->reply_free_q_sz - 1)) ? 0 : 274 (sc->reply_free_q_host_index + 1)); 275 sc->reply_free_q[old_idx] = reply_dma; 276 mpi3mr_regwrite(sc, MPI3_SYSIF_REPLY_FREE_HOST_INDEX_OFFSET, 277 sc->reply_free_q_host_index); 278 mtx_unlock_spin(&sc->reply_free_q_lock); 279 } 280 281 static void mpi3mr_repost_sense_buf(struct mpi3mr_softc *sc, 282 U64 sense_buf_phys) 283 { 284 U32 old_idx = 0; 285 286 mtx_lock_spin(&sc->sense_buf_q_lock); 287 old_idx = sc->sense_buf_q_host_index; 288 sc->sense_buf_q_host_index = ((sc->sense_buf_q_host_index == 289 (sc->sense_buf_q_sz - 1)) ? 0 : 290 (sc->sense_buf_q_host_index + 1)); 291 sc->sense_buf_q[old_idx] = sense_buf_phys; 292 mpi3mr_regwrite(sc, MPI3_SYSIF_SENSE_BUF_FREE_HOST_INDEX_OFFSET, 293 sc->sense_buf_q_host_index); 294 mtx_unlock_spin(&sc->sense_buf_q_lock); 295 296 } 297 298 void mpi3mr_set_io_divert_for_all_vd_in_tg(struct mpi3mr_softc *sc, 299 struct mpi3mr_throttle_group_info *tg, U8 divert_value) 300 { 301 struct mpi3mr_target *target; 302 303 mtx_lock_spin(&sc->target_lock); 304 TAILQ_FOREACH(target, &sc->cam_sc->tgt_list, tgt_next) { 305 if (target->throttle_group == tg) 306 target->io_divert = divert_value; 307 } 308 mtx_unlock_spin(&sc->target_lock); 309 } 310 311 /** 312 * mpi3mr_submit_admin_cmd - Submit request to admin queue 313 * @mrioc: Adapter reference 314 * @admin_req: MPI3 request 315 * @admin_req_sz: Request size 316 * 317 * Post the MPI3 request into admin request queue and 318 * inform the controller, if the queue is full return 319 * appropriate error. 320 * 321 * Return: 0 on success, non-zero on failure. 322 */ 323 int mpi3mr_submit_admin_cmd(struct mpi3mr_softc *sc, void *admin_req, 324 U16 admin_req_sz) 325 { 326 U16 areq_pi = 0, areq_ci = 0, max_entries = 0; 327 int retval = 0; 328 U8 *areq_entry; 329 330 mtx_lock_spin(&sc->admin_req_lock); 331 areq_pi = sc->admin_req_pi; 332 areq_ci = sc->admin_req_ci; 333 max_entries = sc->num_admin_reqs; 334 335 if (sc->unrecoverable) 336 return -EFAULT; 337 338 if ((areq_ci == (areq_pi + 1)) || ((!areq_ci) && 339 (areq_pi == (max_entries - 1)))) { 340 printf(IOCNAME "AdminReqQ full condition detected\n", 341 sc->name); 342 retval = -EAGAIN; 343 goto out; 344 } 345 areq_entry = (U8 *)sc->admin_req + (areq_pi * 346 MPI3MR_AREQ_FRAME_SZ); 347 memset(areq_entry, 0, MPI3MR_AREQ_FRAME_SZ); 348 memcpy(areq_entry, (U8 *)admin_req, admin_req_sz); 349 350 if (++areq_pi == max_entries) 351 areq_pi = 0; 352 sc->admin_req_pi = areq_pi; 353 354 mpi3mr_regwrite(sc, MPI3_SYSIF_ADMIN_REQ_Q_PI_OFFSET, sc->admin_req_pi); 355 356 out: 357 mtx_unlock_spin(&sc->admin_req_lock); 358 return retval; 359 } 360 361 /** 362 * mpi3mr_check_req_qfull - Check request queue is full or not 363 * @op_req_q: Operational reply queue info 364 * 365 * Return: true when queue full, false otherwise. 366 */ 367 static inline bool 368 mpi3mr_check_req_qfull(struct mpi3mr_op_req_queue *op_req_q) 369 { 370 U16 pi, ci, max_entries; 371 bool is_qfull = false; 372 373 pi = op_req_q->pi; 374 ci = op_req_q->ci; 375 max_entries = op_req_q->num_reqs; 376 377 if ((ci == (pi + 1)) || ((!ci) && (pi == (max_entries - 1)))) 378 is_qfull = true; 379 380 return is_qfull; 381 } 382 383 /** 384 * mpi3mr_submit_io - Post IO command to firmware 385 * @sc: Adapter instance reference 386 * @op_req_q: Operational Request queue reference 387 * @req: MPT request data 388 * 389 * This function submits IO command to firmware. 390 * 391 * Return: Nothing 392 */ 393 int mpi3mr_submit_io(struct mpi3mr_softc *sc, 394 struct mpi3mr_op_req_queue *op_req_q, U8 *req) 395 { 396 U16 pi, max_entries; 397 int retval = 0; 398 U8 *req_entry; 399 U16 req_sz = sc->facts.op_req_sz; 400 struct mpi3mr_irq_context *irq_ctx; 401 402 mtx_lock_spin(&op_req_q->q_lock); 403 404 pi = op_req_q->pi; 405 max_entries = op_req_q->num_reqs; 406 if (mpi3mr_check_req_qfull(op_req_q)) { 407 irq_ctx = &sc->irq_ctx[op_req_q->reply_qid - 1]; 408 mpi3mr_complete_io_cmd(sc, irq_ctx); 409 410 if (mpi3mr_check_req_qfull(op_req_q)) { 411 printf(IOCNAME "OpReqQ full condition detected\n", 412 sc->name); 413 retval = -EBUSY; 414 goto out; 415 } 416 } 417 418 req_entry = (U8 *)op_req_q->q_base + (pi * req_sz); 419 memset(req_entry, 0, req_sz); 420 memcpy(req_entry, req, MPI3MR_AREQ_FRAME_SZ); 421 if (++pi == max_entries) 422 pi = 0; 423 op_req_q->pi = pi; 424 425 mpi3mr_atomic_inc(&sc->op_reply_q[op_req_q->reply_qid - 1].pend_ios); 426 427 mpi3mr_regwrite(sc, MPI3_SYSIF_OPER_REQ_Q_N_PI_OFFSET(op_req_q->qid), op_req_q->pi); 428 if (sc->mpi3mr_debug & MPI3MR_TRACE) { 429 device_printf(sc->mpi3mr_dev, "IO submission: QID:%d PI:0x%x\n", op_req_q->qid, op_req_q->pi); 430 mpi3mr_hexdump(req_entry, MPI3MR_AREQ_FRAME_SZ, 8); 431 } 432 433 out: 434 mtx_unlock_spin(&op_req_q->q_lock); 435 return retval; 436 } 437 438 inline void 439 mpi3mr_add_sg_single(void *paddr, U8 flags, U32 length, 440 bus_addr_t dma_addr) 441 { 442 Mpi3SGESimple_t *sgel = paddr; 443 444 sgel->Flags = flags; 445 sgel->Length = (length); 446 sgel->Address = (U64)dma_addr; 447 } 448 449 void mpi3mr_build_zero_len_sge(void *paddr) 450 { 451 U8 sgl_flags = (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | 452 MPI3_SGE_FLAGS_DLAS_SYSTEM | MPI3_SGE_FLAGS_END_OF_LIST); 453 454 mpi3mr_add_sg_single(paddr, sgl_flags, 0, -1); 455 456 } 457 458 void mpi3mr_enable_interrupts(struct mpi3mr_softc *sc) 459 { 460 sc->intr_enabled = 1; 461 } 462 463 void mpi3mr_disable_interrupts(struct mpi3mr_softc *sc) 464 { 465 sc->intr_enabled = 0; 466 } 467 468 void 469 mpi3mr_memaddr_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 470 { 471 bus_addr_t *addr; 472 473 addr = arg; 474 *addr = segs[0].ds_addr; 475 } 476 477 static int mpi3mr_delete_op_reply_queue(struct mpi3mr_softc *sc, U16 qid) 478 { 479 Mpi3DeleteReplyQueueRequest_t delq_req; 480 struct mpi3mr_op_reply_queue *op_reply_q; 481 int retval = 0; 482 483 484 op_reply_q = &sc->op_reply_q[qid - 1]; 485 486 if (!op_reply_q->qid) 487 { 488 retval = -1; 489 printf(IOCNAME "Issue DelRepQ: called with invalid Reply QID\n", 490 sc->name); 491 goto out; 492 } 493 494 memset(&delq_req, 0, sizeof(delq_req)); 495 496 mtx_lock(&sc->init_cmds.completion.lock); 497 if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { 498 retval = -1; 499 printf(IOCNAME "Issue DelRepQ: Init command is in use\n", 500 sc->name); 501 mtx_unlock(&sc->init_cmds.completion.lock); 502 goto out; 503 } 504 505 if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { 506 retval = -1; 507 printf(IOCNAME "Issue DelRepQ: Init command is in use\n", 508 sc->name); 509 goto out; 510 } 511 sc->init_cmds.state = MPI3MR_CMD_PENDING; 512 sc->init_cmds.is_waiting = 1; 513 sc->init_cmds.callback = NULL; 514 delq_req.HostTag = MPI3MR_HOSTTAG_INITCMDS; 515 delq_req.Function = MPI3_FUNCTION_DELETE_REPLY_QUEUE; 516 delq_req.QueueID = qid; 517 518 init_completion(&sc->init_cmds.completion); 519 retval = mpi3mr_submit_admin_cmd(sc, &delq_req, sizeof(delq_req)); 520 if (retval) { 521 printf(IOCNAME "Issue DelRepQ: Admin Post failed\n", 522 sc->name); 523 goto out_unlock; 524 } 525 wait_for_completion_timeout(&sc->init_cmds.completion, 526 (MPI3MR_INTADMCMD_TIMEOUT)); 527 if (!(sc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 528 printf(IOCNAME "Issue DelRepQ: command timed out\n", 529 sc->name); 530 mpi3mr_check_rh_fault_ioc(sc, 531 MPI3MR_RESET_FROM_DELREPQ_TIMEOUT); 532 sc->unrecoverable = 1; 533 534 retval = -1; 535 goto out_unlock; 536 } 537 if ((sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 538 != MPI3_IOCSTATUS_SUCCESS ) { 539 printf(IOCNAME "Issue DelRepQ: Failed IOCStatus(0x%04x) " 540 " Loginfo(0x%08x) \n" , sc->name, 541 (sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 542 sc->init_cmds.ioc_loginfo); 543 retval = -1; 544 goto out_unlock; 545 } 546 sc->irq_ctx[qid - 1].op_reply_q = NULL; 547 548 if (sc->op_reply_q[qid - 1].q_base_phys != 0) 549 bus_dmamap_unload(sc->op_reply_q[qid - 1].q_base_tag, sc->op_reply_q[qid - 1].q_base_dmamap); 550 if (sc->op_reply_q[qid - 1].q_base != NULL) 551 bus_dmamem_free(sc->op_reply_q[qid - 1].q_base_tag, sc->op_reply_q[qid - 1].q_base, sc->op_reply_q[qid - 1].q_base_dmamap); 552 if (sc->op_reply_q[qid - 1].q_base_tag != NULL) 553 bus_dma_tag_destroy(sc->op_reply_q[qid - 1].q_base_tag); 554 555 sc->op_reply_q[qid - 1].q_base = NULL; 556 sc->op_reply_q[qid - 1].qid = 0; 557 out_unlock: 558 sc->init_cmds.state = MPI3MR_CMD_NOTUSED; 559 mtx_unlock(&sc->init_cmds.completion.lock); 560 out: 561 return retval; 562 } 563 564 /** 565 * mpi3mr_create_op_reply_queue - create operational reply queue 566 * @sc: Adapter instance reference 567 * @qid: operational reply queue id 568 * 569 * Create operatinal reply queue by issuing MPI request 570 * through admin queue. 571 * 572 * Return: 0 on success, non-zero on failure. 573 */ 574 static int mpi3mr_create_op_reply_queue(struct mpi3mr_softc *sc, U16 qid) 575 { 576 Mpi3CreateReplyQueueRequest_t create_req; 577 struct mpi3mr_op_reply_queue *op_reply_q; 578 int retval = 0; 579 char q_lock_name[32]; 580 581 op_reply_q = &sc->op_reply_q[qid - 1]; 582 583 if (op_reply_q->qid) 584 { 585 retval = -1; 586 printf(IOCNAME "CreateRepQ: called for duplicate qid %d\n", 587 sc->name, op_reply_q->qid); 588 return retval; 589 } 590 591 op_reply_q->ci = 0; 592 if (pci_get_revid(sc->mpi3mr_dev) == SAS4116_CHIP_REV_A0) 593 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD_A0; 594 else 595 op_reply_q->num_replies = MPI3MR_OP_REP_Q_QD; 596 597 op_reply_q->qsz = op_reply_q->num_replies * sc->op_reply_sz; 598 op_reply_q->ephase = 1; 599 600 if (!op_reply_q->q_base) { 601 snprintf(q_lock_name, 32, "Reply Queue Lock[%d]", qid); 602 mtx_init(&op_reply_q->q_lock, q_lock_name, NULL, MTX_SPIN); 603 604 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 605 4, 0, /* algnmnt, boundary */ 606 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 607 BUS_SPACE_MAXADDR, /* highaddr */ 608 NULL, NULL, /* filter, filterarg */ 609 op_reply_q->qsz, /* maxsize */ 610 1, /* nsegments */ 611 op_reply_q->qsz, /* maxsegsize */ 612 0, /* flags */ 613 NULL, NULL, /* lockfunc, lockarg */ 614 &op_reply_q->q_base_tag)) { 615 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate Operational reply DMA tag\n"); 616 return (ENOMEM); 617 } 618 619 if (bus_dmamem_alloc(op_reply_q->q_base_tag, (void **)&op_reply_q->q_base, 620 BUS_DMA_NOWAIT, &op_reply_q->q_base_dmamap)) { 621 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate replies memory\n"); 622 return (ENOMEM); 623 } 624 bzero(op_reply_q->q_base, op_reply_q->qsz); 625 bus_dmamap_load(op_reply_q->q_base_tag, op_reply_q->q_base_dmamap, op_reply_q->q_base, op_reply_q->qsz, 626 mpi3mr_memaddr_cb, &op_reply_q->q_base_phys, 0); 627 mpi3mr_dprint(sc, MPI3MR_XINFO, "Operational Reply queue ID: %d phys addr= %#016jx virt_addr: %pa size= %d\n", 628 qid, (uintmax_t)op_reply_q->q_base_phys, op_reply_q->q_base, op_reply_q->qsz); 629 630 if (!op_reply_q->q_base) 631 { 632 retval = -1; 633 printf(IOCNAME "CreateRepQ: memory alloc failed for qid %d\n", 634 sc->name, qid); 635 goto out; 636 } 637 } 638 639 memset(&create_req, 0, sizeof(create_req)); 640 641 mtx_lock(&sc->init_cmds.completion.lock); 642 if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { 643 retval = -1; 644 printf(IOCNAME "CreateRepQ: Init command is in use\n", 645 sc->name); 646 mtx_unlock(&sc->init_cmds.completion.lock); 647 goto out; 648 } 649 650 sc->init_cmds.state = MPI3MR_CMD_PENDING; 651 sc->init_cmds.is_waiting = 1; 652 sc->init_cmds.callback = NULL; 653 create_req.HostTag = MPI3MR_HOSTTAG_INITCMDS; 654 create_req.Function = MPI3_FUNCTION_CREATE_REPLY_QUEUE; 655 create_req.QueueID = qid; 656 create_req.Flags = MPI3_CREATE_REPLY_QUEUE_FLAGS_INT_ENABLE_ENABLE; 657 create_req.MSIxIndex = sc->irq_ctx[qid - 1].msix_index; 658 create_req.BaseAddress = (U64)op_reply_q->q_base_phys; 659 create_req.Size = op_reply_q->num_replies; 660 661 init_completion(&sc->init_cmds.completion); 662 retval = mpi3mr_submit_admin_cmd(sc, &create_req, 663 sizeof(create_req)); 664 if (retval) { 665 printf(IOCNAME "CreateRepQ: Admin Post failed\n", 666 sc->name); 667 goto out_unlock; 668 } 669 670 wait_for_completion_timeout(&sc->init_cmds.completion, 671 MPI3MR_INTADMCMD_TIMEOUT); 672 if (!(sc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 673 printf(IOCNAME "CreateRepQ: command timed out\n", 674 sc->name); 675 mpi3mr_check_rh_fault_ioc(sc, 676 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT); 677 sc->unrecoverable = 1; 678 retval = -1; 679 goto out_unlock; 680 } 681 682 if ((sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 683 != MPI3_IOCSTATUS_SUCCESS ) { 684 printf(IOCNAME "CreateRepQ: Failed IOCStatus(0x%04x) " 685 " Loginfo(0x%08x) \n" , sc->name, 686 (sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 687 sc->init_cmds.ioc_loginfo); 688 retval = -1; 689 goto out_unlock; 690 } 691 op_reply_q->qid = qid; 692 sc->irq_ctx[qid - 1].op_reply_q = op_reply_q; 693 694 out_unlock: 695 sc->init_cmds.state = MPI3MR_CMD_NOTUSED; 696 mtx_unlock(&sc->init_cmds.completion.lock); 697 out: 698 if (retval) { 699 if (op_reply_q->q_base_phys != 0) 700 bus_dmamap_unload(op_reply_q->q_base_tag, op_reply_q->q_base_dmamap); 701 if (op_reply_q->q_base != NULL) 702 bus_dmamem_free(op_reply_q->q_base_tag, op_reply_q->q_base, op_reply_q->q_base_dmamap); 703 if (op_reply_q->q_base_tag != NULL) 704 bus_dma_tag_destroy(op_reply_q->q_base_tag); 705 op_reply_q->q_base = NULL; 706 op_reply_q->qid = 0; 707 } 708 709 return retval; 710 } 711 712 /** 713 * mpi3mr_create_op_req_queue - create operational request queue 714 * @sc: Adapter instance reference 715 * @req_qid: operational request queue id 716 * @reply_qid: Reply queue ID 717 * 718 * Create operatinal request queue by issuing MPI request 719 * through admin queue. 720 * 721 * Return: 0 on success, non-zero on failure. 722 */ 723 static int mpi3mr_create_op_req_queue(struct mpi3mr_softc *sc, U16 req_qid, U8 reply_qid) 724 { 725 Mpi3CreateRequestQueueRequest_t create_req; 726 struct mpi3mr_op_req_queue *op_req_q; 727 int retval = 0; 728 char q_lock_name[32]; 729 730 op_req_q = &sc->op_req_q[req_qid - 1]; 731 732 if (op_req_q->qid) 733 { 734 retval = -1; 735 printf(IOCNAME "CreateReqQ: called for duplicate qid %d\n", 736 sc->name, op_req_q->qid); 737 return retval; 738 } 739 740 op_req_q->ci = 0; 741 op_req_q->pi = 0; 742 op_req_q->num_reqs = MPI3MR_OP_REQ_Q_QD; 743 op_req_q->qsz = op_req_q->num_reqs * sc->facts.op_req_sz; 744 op_req_q->reply_qid = reply_qid; 745 746 if (!op_req_q->q_base) { 747 snprintf(q_lock_name, 32, "Request Queue Lock[%d]", req_qid); 748 mtx_init(&op_req_q->q_lock, q_lock_name, NULL, MTX_SPIN); 749 750 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 751 4, 0, /* algnmnt, boundary */ 752 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 753 BUS_SPACE_MAXADDR, /* highaddr */ 754 NULL, NULL, /* filter, filterarg */ 755 op_req_q->qsz, /* maxsize */ 756 1, /* nsegments */ 757 op_req_q->qsz, /* maxsegsize */ 758 0, /* flags */ 759 NULL, NULL, /* lockfunc, lockarg */ 760 &op_req_q->q_base_tag)) { 761 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate request DMA tag\n"); 762 return (ENOMEM); 763 } 764 765 if (bus_dmamem_alloc(op_req_q->q_base_tag, (void **)&op_req_q->q_base, 766 BUS_DMA_NOWAIT, &op_req_q->q_base_dmamap)) { 767 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate replies memory\n"); 768 return (ENOMEM); 769 } 770 771 bzero(op_req_q->q_base, op_req_q->qsz); 772 773 bus_dmamap_load(op_req_q->q_base_tag, op_req_q->q_base_dmamap, op_req_q->q_base, op_req_q->qsz, 774 mpi3mr_memaddr_cb, &op_req_q->q_base_phys, 0); 775 776 mpi3mr_dprint(sc, MPI3MR_XINFO, "Operational Request QID: %d phys addr= %#016jx virt addr= %pa size= %d associated Reply QID: %d\n", 777 req_qid, (uintmax_t)op_req_q->q_base_phys, op_req_q->q_base, op_req_q->qsz, reply_qid); 778 779 if (!op_req_q->q_base) { 780 retval = -1; 781 printf(IOCNAME "CreateReqQ: memory alloc failed for qid %d\n", 782 sc->name, req_qid); 783 goto out; 784 } 785 } 786 787 memset(&create_req, 0, sizeof(create_req)); 788 789 mtx_lock(&sc->init_cmds.completion.lock); 790 if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { 791 retval = -1; 792 printf(IOCNAME "CreateReqQ: Init command is in use\n", 793 sc->name); 794 mtx_unlock(&sc->init_cmds.completion.lock); 795 goto out; 796 } 797 798 sc->init_cmds.state = MPI3MR_CMD_PENDING; 799 sc->init_cmds.is_waiting = 1; 800 sc->init_cmds.callback = NULL; 801 create_req.HostTag = MPI3MR_HOSTTAG_INITCMDS; 802 create_req.Function = MPI3_FUNCTION_CREATE_REQUEST_QUEUE; 803 create_req.QueueID = req_qid; 804 create_req.Flags = 0; 805 create_req.ReplyQueueID = reply_qid; 806 create_req.BaseAddress = (U64)op_req_q->q_base_phys; 807 create_req.Size = op_req_q->num_reqs; 808 809 init_completion(&sc->init_cmds.completion); 810 retval = mpi3mr_submit_admin_cmd(sc, &create_req, 811 sizeof(create_req)); 812 if (retval) { 813 printf(IOCNAME "CreateReqQ: Admin Post failed\n", 814 sc->name); 815 goto out_unlock; 816 } 817 818 wait_for_completion_timeout(&sc->init_cmds.completion, 819 (MPI3MR_INTADMCMD_TIMEOUT)); 820 821 if (!(sc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 822 printf(IOCNAME "CreateReqQ: command timed out\n", 823 sc->name); 824 mpi3mr_check_rh_fault_ioc(sc, 825 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT); 826 sc->unrecoverable = 1; 827 retval = -1; 828 goto out_unlock; 829 } 830 831 if ((sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 832 != MPI3_IOCSTATUS_SUCCESS ) { 833 printf(IOCNAME "CreateReqQ: Failed IOCStatus(0x%04x) " 834 " Loginfo(0x%08x) \n" , sc->name, 835 (sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 836 sc->init_cmds.ioc_loginfo); 837 retval = -1; 838 goto out_unlock; 839 } 840 op_req_q->qid = req_qid; 841 842 out_unlock: 843 sc->init_cmds.state = MPI3MR_CMD_NOTUSED; 844 mtx_unlock(&sc->init_cmds.completion.lock); 845 out: 846 if (retval) { 847 if (op_req_q->q_base_phys != 0) 848 bus_dmamap_unload(op_req_q->q_base_tag, op_req_q->q_base_dmamap); 849 if (op_req_q->q_base != NULL) 850 bus_dmamem_free(op_req_q->q_base_tag, op_req_q->q_base, op_req_q->q_base_dmamap); 851 if (op_req_q->q_base_tag != NULL) 852 bus_dma_tag_destroy(op_req_q->q_base_tag); 853 op_req_q->q_base = NULL; 854 op_req_q->qid = 0; 855 } 856 return retval; 857 } 858 859 /** 860 * mpi3mr_create_op_queues - create operational queues 861 * @sc: Adapter instance reference 862 * 863 * Create operatinal queues(request queues and reply queues). 864 * Return: 0 on success, non-zero on failure. 865 */ 866 static int mpi3mr_create_op_queues(struct mpi3mr_softc *sc) 867 { 868 int retval = 0; 869 U16 num_queues = 0, i = 0, qid; 870 871 num_queues = min(sc->facts.max_op_reply_q, 872 sc->facts.max_op_req_q); 873 num_queues = min(num_queues, sc->msix_count); 874 875 /* 876 * During reset set the num_queues to the number of queues 877 * that was set before the reset. 878 */ 879 if (sc->num_queues) 880 num_queues = sc->num_queues; 881 882 mpi3mr_dprint(sc, MPI3MR_XINFO, "Trying to create %d Operational Q pairs\n", 883 num_queues); 884 885 if (!sc->op_req_q) { 886 sc->op_req_q = malloc(sizeof(struct mpi3mr_op_req_queue) * 887 num_queues, M_MPI3MR, M_NOWAIT | M_ZERO); 888 889 if (!sc->op_req_q) { 890 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to alloc memory for Request queue info\n"); 891 retval = -1; 892 goto out_failed; 893 } 894 } 895 896 if (!sc->op_reply_q) { 897 sc->op_reply_q = malloc(sizeof(struct mpi3mr_op_reply_queue) * num_queues, 898 M_MPI3MR, M_NOWAIT | M_ZERO); 899 900 if (!sc->op_reply_q) { 901 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to alloc memory for Reply queue info\n"); 902 retval = -1; 903 goto out_failed; 904 } 905 } 906 907 sc->num_hosttag_op_req_q = (sc->max_host_ios + 1) / num_queues; 908 909 /*Operational Request and reply queue ID starts with 1*/ 910 for (i = 0; i < num_queues; i++) { 911 qid = i + 1; 912 if (mpi3mr_create_op_reply_queue(sc, qid)) { 913 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to create Reply queue %d\n", 914 qid); 915 break; 916 } 917 if (mpi3mr_create_op_req_queue(sc, qid, 918 sc->op_reply_q[qid - 1].qid)) { 919 mpi3mr_delete_op_reply_queue(sc, qid); 920 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to create Request queue %d\n", 921 qid); 922 break; 923 } 924 925 } 926 927 /* Not even one queue is created successfully*/ 928 if (i == 0) { 929 retval = -1; 930 goto out_failed; 931 } 932 933 if (!sc->num_queues) { 934 sc->num_queues = i; 935 } else { 936 if (num_queues != i) { 937 mpi3mr_dprint(sc, MPI3MR_ERROR, "Number of queues (%d) post reset are not same as" 938 "queues allocated (%d) during driver init\n", i, num_queues); 939 goto out_failed; 940 } 941 } 942 943 mpi3mr_dprint(sc, MPI3MR_INFO, "Successfully created %d Operational Queue pairs\n", 944 sc->num_queues); 945 mpi3mr_dprint(sc, MPI3MR_INFO, "Request Queue QD: %d Reply queue QD: %d\n", 946 sc->op_req_q[0].num_reqs, sc->op_reply_q[0].num_replies); 947 948 return retval; 949 out_failed: 950 if (sc->op_req_q) { 951 free(sc->op_req_q, M_MPI3MR); 952 sc->op_req_q = NULL; 953 } 954 if (sc->op_reply_q) { 955 free(sc->op_reply_q, M_MPI3MR); 956 sc->op_reply_q = NULL; 957 } 958 return retval; 959 } 960 961 /** 962 * mpi3mr_setup_admin_qpair - Setup admin queue pairs 963 * @sc: Adapter instance reference 964 * 965 * Allocation and setup admin queues(request queues and reply queues). 966 * Return: 0 on success, non-zero on failure. 967 */ 968 static int mpi3mr_setup_admin_qpair(struct mpi3mr_softc *sc) 969 { 970 int retval = 0; 971 U32 num_adm_entries = 0; 972 973 sc->admin_req_q_sz = MPI3MR_AREQQ_SIZE; 974 sc->num_admin_reqs = sc->admin_req_q_sz / MPI3MR_AREQ_FRAME_SZ; 975 sc->admin_req_ci = sc->admin_req_pi = 0; 976 977 sc->admin_reply_q_sz = MPI3MR_AREPQ_SIZE; 978 sc->num_admin_replies = sc->admin_reply_q_sz/ MPI3MR_AREP_FRAME_SZ; 979 sc->admin_reply_ci = 0; 980 sc->admin_reply_ephase = 1; 981 982 if (!sc->admin_req) { 983 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 984 4, 0, /* algnmnt, boundary */ 985 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 986 BUS_SPACE_MAXADDR, /* highaddr */ 987 NULL, NULL, /* filter, filterarg */ 988 sc->admin_req_q_sz, /* maxsize */ 989 1, /* nsegments */ 990 sc->admin_req_q_sz, /* maxsegsize */ 991 0, /* flags */ 992 NULL, NULL, /* lockfunc, lockarg */ 993 &sc->admin_req_tag)) { 994 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate request DMA tag\n"); 995 return (ENOMEM); 996 } 997 998 if (bus_dmamem_alloc(sc->admin_req_tag, (void **)&sc->admin_req, 999 BUS_DMA_NOWAIT, &sc->admin_req_dmamap)) { 1000 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate replies memory\n"); 1001 return (ENOMEM); 1002 } 1003 bzero(sc->admin_req, sc->admin_req_q_sz); 1004 bus_dmamap_load(sc->admin_req_tag, sc->admin_req_dmamap, sc->admin_req, sc->admin_req_q_sz, 1005 mpi3mr_memaddr_cb, &sc->admin_req_phys, 0); 1006 mpi3mr_dprint(sc, MPI3MR_XINFO, "Admin Req queue phys addr= %#016jx size= %d\n", 1007 (uintmax_t)sc->admin_req_phys, sc->admin_req_q_sz); 1008 1009 if (!sc->admin_req) 1010 { 1011 retval = -1; 1012 printf(IOCNAME "Memory alloc for AdminReqQ: failed\n", 1013 sc->name); 1014 goto out_failed; 1015 } 1016 } 1017 1018 if (!sc->admin_reply) { 1019 mtx_init(&sc->admin_reply_lock, "Admin Reply Queue Lock", NULL, MTX_SPIN); 1020 1021 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 1022 4, 0, /* algnmnt, boundary */ 1023 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1024 BUS_SPACE_MAXADDR, /* highaddr */ 1025 NULL, NULL, /* filter, filterarg */ 1026 sc->admin_reply_q_sz, /* maxsize */ 1027 1, /* nsegments */ 1028 sc->admin_reply_q_sz, /* maxsegsize */ 1029 0, /* flags */ 1030 NULL, NULL, /* lockfunc, lockarg */ 1031 &sc->admin_reply_tag)) { 1032 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate reply DMA tag\n"); 1033 return (ENOMEM); 1034 } 1035 1036 if (bus_dmamem_alloc(sc->admin_reply_tag, (void **)&sc->admin_reply, 1037 BUS_DMA_NOWAIT, &sc->admin_reply_dmamap)) { 1038 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate replies memory\n"); 1039 return (ENOMEM); 1040 } 1041 bzero(sc->admin_reply, sc->admin_reply_q_sz); 1042 bus_dmamap_load(sc->admin_reply_tag, sc->admin_reply_dmamap, sc->admin_reply, sc->admin_reply_q_sz, 1043 mpi3mr_memaddr_cb, &sc->admin_reply_phys, 0); 1044 mpi3mr_dprint(sc, MPI3MR_XINFO, "Admin Reply queue phys addr= %#016jx size= %d\n", 1045 (uintmax_t)sc->admin_reply_phys, sc->admin_req_q_sz); 1046 1047 1048 if (!sc->admin_reply) 1049 { 1050 retval = -1; 1051 printf(IOCNAME "Memory alloc for AdminRepQ: failed\n", 1052 sc->name); 1053 goto out_failed; 1054 } 1055 } 1056 1057 num_adm_entries = (sc->num_admin_replies << 16) | 1058 (sc->num_admin_reqs); 1059 mpi3mr_regwrite(sc, MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_OFFSET, num_adm_entries); 1060 mpi3mr_regwrite64(sc, MPI3_SYSIF_ADMIN_REQ_Q_ADDR_LOW_OFFSET, sc->admin_req_phys); 1061 mpi3mr_regwrite64(sc, MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_LOW_OFFSET, sc->admin_reply_phys); 1062 mpi3mr_regwrite(sc, MPI3_SYSIF_ADMIN_REQ_Q_PI_OFFSET, sc->admin_req_pi); 1063 mpi3mr_regwrite(sc, MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET, sc->admin_reply_ci); 1064 1065 return retval; 1066 1067 out_failed: 1068 /* Free Admin reply*/ 1069 if (sc->admin_reply_phys) 1070 bus_dmamap_unload(sc->admin_reply_tag, sc->admin_reply_dmamap); 1071 1072 if (sc->admin_reply != NULL) 1073 bus_dmamem_free(sc->admin_reply_tag, sc->admin_reply, 1074 sc->admin_reply_dmamap); 1075 1076 if (sc->admin_reply_tag != NULL) 1077 bus_dma_tag_destroy(sc->admin_reply_tag); 1078 1079 /* Free Admin request*/ 1080 if (sc->admin_req_phys) 1081 bus_dmamap_unload(sc->admin_req_tag, sc->admin_req_dmamap); 1082 1083 if (sc->admin_req != NULL) 1084 bus_dmamem_free(sc->admin_req_tag, sc->admin_req, 1085 sc->admin_req_dmamap); 1086 1087 if (sc->admin_req_tag != NULL) 1088 bus_dma_tag_destroy(sc->admin_req_tag); 1089 1090 return retval; 1091 } 1092 1093 /** 1094 * mpi3mr_print_fault_info - Display fault information 1095 * @sc: Adapter instance reference 1096 * 1097 * Display the controller fault information if there is a 1098 * controller fault. 1099 * 1100 * Return: Nothing. 1101 */ 1102 static void mpi3mr_print_fault_info(struct mpi3mr_softc *sc) 1103 { 1104 U32 ioc_status, code, code1, code2, code3; 1105 1106 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 1107 1108 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) { 1109 code = mpi3mr_regread(sc, MPI3_SYSIF_FAULT_OFFSET) & 1110 MPI3_SYSIF_FAULT_CODE_MASK; 1111 code1 = mpi3mr_regread(sc, MPI3_SYSIF_FAULT_INFO0_OFFSET); 1112 code2 = mpi3mr_regread(sc, MPI3_SYSIF_FAULT_INFO1_OFFSET); 1113 code3 = mpi3mr_regread(sc, MPI3_SYSIF_FAULT_INFO2_OFFSET); 1114 printf(IOCNAME "fault codes 0x%04x:0x%04x:0x%04x:0x%04x\n", 1115 sc->name, code, code1, code2, code3); 1116 } 1117 } 1118 1119 enum mpi3mr_iocstate mpi3mr_get_iocstate(struct mpi3mr_softc *sc) 1120 { 1121 U32 ioc_status, ioc_control; 1122 U8 ready, enabled; 1123 1124 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 1125 ioc_control = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 1126 1127 if(sc->unrecoverable) 1128 return MRIOC_STATE_UNRECOVERABLE; 1129 if (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) 1130 return MRIOC_STATE_FAULT; 1131 1132 ready = (ioc_status & MPI3_SYSIF_IOC_STATUS_READY); 1133 enabled = (ioc_control & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC); 1134 1135 if (ready && enabled) 1136 return MRIOC_STATE_READY; 1137 if ((!ready) && (!enabled)) 1138 return MRIOC_STATE_RESET; 1139 if ((!ready) && (enabled)) 1140 return MRIOC_STATE_BECOMING_READY; 1141 1142 return MRIOC_STATE_RESET_REQUESTED; 1143 } 1144 1145 static inline void mpi3mr_clear_resethistory(struct mpi3mr_softc *sc) 1146 { 1147 U32 ioc_status; 1148 1149 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 1150 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) 1151 mpi3mr_regwrite(sc, MPI3_SYSIF_IOC_STATUS_OFFSET, ioc_status); 1152 1153 } 1154 1155 /** 1156 * mpi3mr_mur_ioc - Message unit Reset handler 1157 * @sc: Adapter instance reference 1158 * @reset_reason: Reset reason code 1159 * 1160 * Issue Message unit Reset to the controller and wait for it to 1161 * be complete. 1162 * 1163 * Return: 0 on success, -1 on failure. 1164 */ 1165 static int mpi3mr_mur_ioc(struct mpi3mr_softc *sc, U32 reset_reason) 1166 { 1167 U32 ioc_config, timeout, ioc_status; 1168 int retval = -1; 1169 1170 mpi3mr_dprint(sc, MPI3MR_INFO, "Issuing Message Unit Reset(MUR)\n"); 1171 if (sc->unrecoverable) { 1172 mpi3mr_dprint(sc, MPI3MR_ERROR, "IOC is unrecoverable MUR not issued\n"); 1173 return retval; 1174 } 1175 mpi3mr_clear_resethistory(sc); 1176 mpi3mr_regwrite(sc, MPI3_SYSIF_SCRATCHPAD0_OFFSET, reset_reason); 1177 ioc_config = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 1178 ioc_config &= ~MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; 1179 mpi3mr_regwrite(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET, ioc_config); 1180 1181 timeout = MPI3MR_MUR_TIMEOUT * 10; 1182 do { 1183 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 1184 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY)) { 1185 mpi3mr_clear_resethistory(sc); 1186 ioc_config = 1187 mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 1188 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) || 1189 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) || 1190 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC))) { 1191 retval = 0; 1192 break; 1193 } 1194 } 1195 DELAY(100 * 1000); 1196 } while (--timeout); 1197 1198 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 1199 ioc_config = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 1200 1201 mpi3mr_dprint(sc, MPI3MR_INFO, "IOC Status/Config after %s MUR is (0x%x)/(0x%x)\n", 1202 !retval ? "successful":"failed", ioc_status, ioc_config); 1203 return retval; 1204 } 1205 1206 /** 1207 * mpi3mr_bring_ioc_ready - Bring controller to ready state 1208 * @sc: Adapter instance reference 1209 * 1210 * Set Enable IOC bit in IOC configuration register and wait for 1211 * the controller to become ready. 1212 * 1213 * Return: 0 on success, appropriate error on failure. 1214 */ 1215 static int mpi3mr_bring_ioc_ready(struct mpi3mr_softc *sc) 1216 { 1217 U32 ioc_config, timeout; 1218 enum mpi3mr_iocstate current_state; 1219 1220 ioc_config = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 1221 ioc_config |= MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC; 1222 mpi3mr_regwrite(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET, ioc_config); 1223 1224 timeout = sc->ready_timeout * 10; 1225 do { 1226 current_state = mpi3mr_get_iocstate(sc); 1227 if (current_state == MRIOC_STATE_READY) 1228 return 0; 1229 DELAY(100 * 1000); 1230 } while (--timeout); 1231 1232 return -1; 1233 } 1234 1235 static const struct { 1236 enum mpi3mr_iocstate value; 1237 char *name; 1238 } mrioc_states[] = { 1239 { MRIOC_STATE_READY, "ready" }, 1240 { MRIOC_STATE_FAULT, "fault" }, 1241 { MRIOC_STATE_RESET, "reset" }, 1242 { MRIOC_STATE_BECOMING_READY, "becoming ready" }, 1243 { MRIOC_STATE_RESET_REQUESTED, "reset requested" }, 1244 { MRIOC_STATE_COUNT, "Count" }, 1245 }; 1246 1247 static const char *mpi3mr_iocstate_name(enum mpi3mr_iocstate mrioc_state) 1248 { 1249 int i; 1250 char *name = NULL; 1251 1252 for (i = 0; i < MRIOC_STATE_COUNT; i++) { 1253 if (mrioc_states[i].value == mrioc_state){ 1254 name = mrioc_states[i].name; 1255 break; 1256 } 1257 } 1258 return name; 1259 } 1260 1261 /* Reset reason to name mapper structure*/ 1262 static const struct { 1263 enum mpi3mr_reset_reason value; 1264 char *name; 1265 } mpi3mr_reset_reason_codes[] = { 1266 { MPI3MR_RESET_FROM_BRINGUP, "timeout in bringup" }, 1267 { MPI3MR_RESET_FROM_FAULT_WATCH, "fault" }, 1268 { MPI3MR_RESET_FROM_IOCTL, "application" }, 1269 { MPI3MR_RESET_FROM_EH_HOS, "error handling" }, 1270 { MPI3MR_RESET_FROM_TM_TIMEOUT, "TM timeout" }, 1271 { MPI3MR_RESET_FROM_IOCTL_TIMEOUT, "IOCTL timeout" }, 1272 { MPI3MR_RESET_FROM_SCSIIO_TIMEOUT, "SCSIIO timeout" }, 1273 { MPI3MR_RESET_FROM_MUR_FAILURE, "MUR failure" }, 1274 { MPI3MR_RESET_FROM_CTLR_CLEANUP, "timeout in controller cleanup" }, 1275 { MPI3MR_RESET_FROM_CIACTIV_FAULT, "component image activation fault" }, 1276 { MPI3MR_RESET_FROM_PE_TIMEOUT, "port enable timeout" }, 1277 { MPI3MR_RESET_FROM_TSU_TIMEOUT, "time stamp update timeout" }, 1278 { MPI3MR_RESET_FROM_DELREQQ_TIMEOUT, "delete request queue timeout" }, 1279 { MPI3MR_RESET_FROM_DELREPQ_TIMEOUT, "delete reply queue timeout" }, 1280 { 1281 MPI3MR_RESET_FROM_CREATEREPQ_TIMEOUT, 1282 "create request queue timeout" 1283 }, 1284 { 1285 MPI3MR_RESET_FROM_CREATEREQQ_TIMEOUT, 1286 "create reply queue timeout" 1287 }, 1288 { MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT, "IOC facts timeout" }, 1289 { MPI3MR_RESET_FROM_IOCINIT_TIMEOUT, "IOC init timeout" }, 1290 { MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT, "event notify timeout" }, 1291 { MPI3MR_RESET_FROM_EVTACK_TIMEOUT, "event acknowledgment timeout" }, 1292 { 1293 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1294 "component image activation timeout" 1295 }, 1296 { 1297 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT, 1298 "get package version timeout" 1299 }, 1300 { 1301 MPI3MR_RESET_FROM_PELABORT_TIMEOUT, 1302 "persistent event log abort timeout" 1303 }, 1304 { MPI3MR_RESET_FROM_SYSFS, "sysfs invocation" }, 1305 { MPI3MR_RESET_FROM_SYSFS_TIMEOUT, "sysfs TM timeout" }, 1306 { 1307 MPI3MR_RESET_FROM_DIAG_BUFFER_POST_TIMEOUT, 1308 "diagnostic buffer post timeout" 1309 }, 1310 { MPI3MR_RESET_FROM_FIRMWARE, "firmware asynchronus reset" }, 1311 { MPI3MR_RESET_REASON_COUNT, "Reset reason count" }, 1312 }; 1313 1314 /** 1315 * mpi3mr_reset_rc_name - get reset reason code name 1316 * @reason_code: reset reason code value 1317 * 1318 * Map reset reason to an NULL terminated ASCII string 1319 * 1320 * Return: Name corresponding to reset reason value or NULL. 1321 */ 1322 static const char *mpi3mr_reset_rc_name(enum mpi3mr_reset_reason reason_code) 1323 { 1324 int i; 1325 char *name = NULL; 1326 1327 for (i = 0; i < MPI3MR_RESET_REASON_COUNT; i++) { 1328 if (mpi3mr_reset_reason_codes[i].value == reason_code) { 1329 name = mpi3mr_reset_reason_codes[i].name; 1330 break; 1331 } 1332 } 1333 return name; 1334 } 1335 1336 #define MAX_RESET_TYPE 3 1337 /* Reset type to name mapper structure*/ 1338 static const struct { 1339 U16 reset_type; 1340 char *name; 1341 } mpi3mr_reset_types[] = { 1342 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, "soft" }, 1343 { MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, "diag fault" }, 1344 { MAX_RESET_TYPE, "count"} 1345 }; 1346 1347 /** 1348 * mpi3mr_reset_type_name - get reset type name 1349 * @reset_type: reset type value 1350 * 1351 * Map reset type to an NULL terminated ASCII string 1352 * 1353 * Return: Name corresponding to reset type value or NULL. 1354 */ 1355 static const char *mpi3mr_reset_type_name(U16 reset_type) 1356 { 1357 int i; 1358 char *name = NULL; 1359 1360 for (i = 0; i < MAX_RESET_TYPE; i++) { 1361 if (mpi3mr_reset_types[i].reset_type == reset_type) { 1362 name = mpi3mr_reset_types[i].name; 1363 break; 1364 } 1365 } 1366 return name; 1367 } 1368 1369 /** 1370 * mpi3mr_soft_reset_success - Check softreset is success or not 1371 * @ioc_status: IOC status register value 1372 * @ioc_config: IOC config register value 1373 * 1374 * Check whether the soft reset is successful or not based on 1375 * IOC status and IOC config register values. 1376 * 1377 * Return: True when the soft reset is success, false otherwise. 1378 */ 1379 static inline bool 1380 mpi3mr_soft_reset_success(U32 ioc_status, U32 ioc_config) 1381 { 1382 if (!((ioc_status & MPI3_SYSIF_IOC_STATUS_READY) || 1383 (ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT) || 1384 (ioc_config & MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC))) 1385 return true; 1386 return false; 1387 } 1388 1389 /** 1390 * mpi3mr_diagfault_success - Check diag fault is success or not 1391 * @sc: Adapter reference 1392 * @ioc_status: IOC status register value 1393 * 1394 * Check whether the controller hit diag reset fault code. 1395 * 1396 * Return: True when there is diag fault, false otherwise. 1397 */ 1398 static inline bool mpi3mr_diagfault_success(struct mpi3mr_softc *sc, 1399 U32 ioc_status) 1400 { 1401 U32 fault; 1402 1403 if (!(ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) 1404 return false; 1405 fault = mpi3mr_regread(sc, MPI3_SYSIF_FAULT_OFFSET) & MPI3_SYSIF_FAULT_CODE_MASK; 1406 if (fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) 1407 return true; 1408 return false; 1409 } 1410 1411 /** 1412 * mpi3mr_issue_iocfacts - Send IOC Facts 1413 * @sc: Adapter instance reference 1414 * @facts_data: Cached IOC facts data 1415 * 1416 * Issue IOC Facts MPI request through admin queue and wait for 1417 * the completion of it or time out. 1418 * 1419 * Return: 0 on success, non-zero on failures. 1420 */ 1421 static int mpi3mr_issue_iocfacts(struct mpi3mr_softc *sc, 1422 Mpi3IOCFactsData_t *facts_data) 1423 { 1424 Mpi3IOCFactsRequest_t iocfacts_req; 1425 bus_dma_tag_t data_tag = NULL; 1426 bus_dmamap_t data_map = NULL; 1427 bus_addr_t data_phys = 0; 1428 void *data = NULL; 1429 U32 data_len = sizeof(*facts_data); 1430 int retval = 0; 1431 1432 U8 sgl_flags = (MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE | 1433 MPI3_SGE_FLAGS_DLAS_SYSTEM | 1434 MPI3_SGE_FLAGS_END_OF_LIST); 1435 1436 1437 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 1438 4, 0, /* algnmnt, boundary */ 1439 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1440 BUS_SPACE_MAXADDR, /* highaddr */ 1441 NULL, NULL, /* filter, filterarg */ 1442 data_len, /* maxsize */ 1443 1, /* nsegments */ 1444 data_len, /* maxsegsize */ 1445 0, /* flags */ 1446 NULL, NULL, /* lockfunc, lockarg */ 1447 &data_tag)) { 1448 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate request DMA tag\n"); 1449 return (ENOMEM); 1450 } 1451 1452 if (bus_dmamem_alloc(data_tag, (void **)&data, 1453 BUS_DMA_NOWAIT, &data_map)) { 1454 mpi3mr_dprint(sc, MPI3MR_ERROR, "Func: %s line: %d Data DMA mem alloc failed\n", 1455 __func__, __LINE__); 1456 return (ENOMEM); 1457 } 1458 1459 bzero(data, data_len); 1460 bus_dmamap_load(data_tag, data_map, data, data_len, 1461 mpi3mr_memaddr_cb, &data_phys, 0); 1462 mpi3mr_dprint(sc, MPI3MR_XINFO, "Func: %s line: %d IOCfacts data phys addr= %#016jx size= %d\n", 1463 __func__, __LINE__, (uintmax_t)data_phys, data_len); 1464 1465 if (!data) 1466 { 1467 retval = -1; 1468 printf(IOCNAME "Memory alloc for IOCFactsData: failed\n", 1469 sc->name); 1470 goto out; 1471 } 1472 1473 mtx_lock(&sc->init_cmds.completion.lock); 1474 memset(&iocfacts_req, 0, sizeof(iocfacts_req)); 1475 1476 if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { 1477 retval = -1; 1478 printf(IOCNAME "Issue IOCFacts: Init command is in use\n", 1479 sc->name); 1480 mtx_unlock(&sc->init_cmds.completion.lock); 1481 goto out; 1482 } 1483 1484 sc->init_cmds.state = MPI3MR_CMD_PENDING; 1485 sc->init_cmds.is_waiting = 1; 1486 sc->init_cmds.callback = NULL; 1487 iocfacts_req.HostTag = (MPI3MR_HOSTTAG_INITCMDS); 1488 iocfacts_req.Function = MPI3_FUNCTION_IOC_FACTS; 1489 1490 mpi3mr_add_sg_single(&iocfacts_req.SGL, sgl_flags, data_len, 1491 data_phys); 1492 1493 init_completion(&sc->init_cmds.completion); 1494 1495 retval = mpi3mr_submit_admin_cmd(sc, &iocfacts_req, 1496 sizeof(iocfacts_req)); 1497 1498 if (retval) { 1499 printf(IOCNAME "Issue IOCFacts: Admin Post failed\n", 1500 sc->name); 1501 goto out_unlock; 1502 } 1503 1504 wait_for_completion_timeout(&sc->init_cmds.completion, 1505 (MPI3MR_INTADMCMD_TIMEOUT)); 1506 if (!(sc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 1507 printf(IOCNAME "Issue IOCFacts: command timed out\n", 1508 sc->name); 1509 mpi3mr_check_rh_fault_ioc(sc, 1510 MPI3MR_RESET_FROM_IOCFACTS_TIMEOUT); 1511 sc->unrecoverable = 1; 1512 retval = -1; 1513 goto out_unlock; 1514 } 1515 1516 if ((sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 1517 != MPI3_IOCSTATUS_SUCCESS ) { 1518 printf(IOCNAME "Issue IOCFacts: Failed IOCStatus(0x%04x) " 1519 " Loginfo(0x%08x) \n" , sc->name, 1520 (sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 1521 sc->init_cmds.ioc_loginfo); 1522 retval = -1; 1523 goto out_unlock; 1524 } 1525 1526 memcpy(facts_data, (U8 *)data, data_len); 1527 out_unlock: 1528 sc->init_cmds.state = MPI3MR_CMD_NOTUSED; 1529 mtx_unlock(&sc->init_cmds.completion.lock); 1530 1531 out: 1532 if (data_phys != 0) 1533 bus_dmamap_unload(data_tag, data_map); 1534 if (data != NULL) 1535 bus_dmamem_free(data_tag, data, data_map); 1536 if (data_tag != NULL) 1537 bus_dma_tag_destroy(data_tag); 1538 return retval; 1539 } 1540 1541 /** 1542 * mpi3mr_process_factsdata - Process IOC facts data 1543 * @sc: Adapter instance reference 1544 * @facts_data: Cached IOC facts data 1545 * 1546 * Convert IOC facts data into cpu endianness and cache it in 1547 * the driver . 1548 * 1549 * Return: Nothing. 1550 */ 1551 static int mpi3mr_process_factsdata(struct mpi3mr_softc *sc, 1552 Mpi3IOCFactsData_t *facts_data) 1553 { 1554 int retval = 0; 1555 U32 ioc_config, req_sz, facts_flags; 1556 1557 if (le16toh(facts_data->IOCFactsDataLength) != 1558 (sizeof(*facts_data) / 4)) { 1559 mpi3mr_dprint(sc, MPI3MR_INFO, "IOCFacts data length mismatch " 1560 " driver_sz(%ld) firmware_sz(%d) \n", 1561 sizeof(*facts_data), 1562 facts_data->IOCFactsDataLength); 1563 } 1564 1565 ioc_config = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 1566 req_sz = 1 << ((ioc_config & MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ) >> 1567 MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT); 1568 1569 if (facts_data->IOCRequestFrameSize != (req_sz/4)) { 1570 mpi3mr_dprint(sc, MPI3MR_INFO, "IOCFacts data reqFrameSize mismatch " 1571 " hw_size(%d) firmware_sz(%d) \n" , req_sz/4, 1572 facts_data->IOCRequestFrameSize); 1573 } 1574 1575 memset(&sc->facts, 0, sizeof(sc->facts)); 1576 1577 facts_flags = le32toh(facts_data->Flags); 1578 sc->facts.op_req_sz = req_sz; 1579 sc->op_reply_sz = 1 << ((ioc_config & 1580 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ) >> 1581 MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT); 1582 1583 sc->facts.ioc_num = facts_data->IOCNumber; 1584 sc->facts.who_init = facts_data->WhoInit; 1585 sc->facts.max_msix_vectors = facts_data->MaxMSIxVectors; 1586 sc->facts.personality = (facts_flags & 1587 MPI3_IOCFACTS_FLAGS_PERSONALITY_MASK); 1588 sc->facts.dma_mask = (facts_flags & 1589 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_MASK) >> 1590 MPI3_IOCFACTS_FLAGS_DMA_ADDRESS_WIDTH_SHIFT; 1591 sc->facts.protocol_flags = facts_data->ProtocolFlags; 1592 sc->facts.mpi_version = (facts_data->MPIVersion.Word); 1593 sc->facts.max_reqs = (facts_data->MaxOutstandingRequests); 1594 sc->facts.product_id = (facts_data->ProductID); 1595 sc->facts.reply_sz = (facts_data->ReplyFrameSize) * 4; 1596 sc->facts.exceptions = (facts_data->IOCExceptions); 1597 sc->facts.max_perids = (facts_data->MaxPersistentID); 1598 sc->facts.max_vds = (facts_data->MaxVDs); 1599 sc->facts.max_hpds = (facts_data->MaxHostPDs); 1600 sc->facts.max_advhpds = (facts_data->MaxAdvHostPDs); 1601 sc->facts.max_raidpds = (facts_data->MaxRAIDPDs); 1602 sc->facts.max_nvme = (facts_data->MaxNVMe); 1603 sc->facts.max_pcieswitches = 1604 (facts_data->MaxPCIeSwitches); 1605 sc->facts.max_sasexpanders = 1606 (facts_data->MaxSASExpanders); 1607 sc->facts.max_sasinitiators = 1608 (facts_data->MaxSASInitiators); 1609 sc->facts.max_enclosures = (facts_data->MaxEnclosures); 1610 sc->facts.min_devhandle = (facts_data->MinDevHandle); 1611 sc->facts.max_devhandle = (facts_data->MaxDevHandle); 1612 sc->facts.max_op_req_q = 1613 (facts_data->MaxOperationalRequestQueues); 1614 sc->facts.max_op_reply_q = 1615 (facts_data->MaxOperationalReplyQueues); 1616 sc->facts.ioc_capabilities = 1617 (facts_data->IOCCapabilities); 1618 sc->facts.fw_ver.build_num = 1619 (facts_data->FWVersion.BuildNum); 1620 sc->facts.fw_ver.cust_id = 1621 (facts_data->FWVersion.CustomerID); 1622 sc->facts.fw_ver.ph_minor = facts_data->FWVersion.PhaseMinor; 1623 sc->facts.fw_ver.ph_major = facts_data->FWVersion.PhaseMajor; 1624 sc->facts.fw_ver.gen_minor = facts_data->FWVersion.GenMinor; 1625 sc->facts.fw_ver.gen_major = facts_data->FWVersion.GenMajor; 1626 sc->max_msix_vectors = min(sc->max_msix_vectors, 1627 sc->facts.max_msix_vectors); 1628 sc->facts.sge_mod_mask = facts_data->SGEModifierMask; 1629 sc->facts.sge_mod_value = facts_data->SGEModifierValue; 1630 sc->facts.sge_mod_shift = facts_data->SGEModifierShift; 1631 sc->facts.shutdown_timeout = 1632 (facts_data->ShutdownTimeout); 1633 sc->facts.max_dev_per_tg = facts_data->MaxDevicesPerThrottleGroup; 1634 sc->facts.io_throttle_data_length = 1635 facts_data->IOThrottleDataLength; 1636 sc->facts.max_io_throttle_group = 1637 facts_data->MaxIOThrottleGroup; 1638 sc->facts.io_throttle_low = facts_data->IOThrottleLow; 1639 sc->facts.io_throttle_high = facts_data->IOThrottleHigh; 1640 1641 /*Store in 512b block count*/ 1642 if (sc->facts.io_throttle_data_length) 1643 sc->io_throttle_data_length = 1644 (sc->facts.io_throttle_data_length * 2 * 4); 1645 else 1646 /* set the length to 1MB + 1K to disable throttle*/ 1647 sc->io_throttle_data_length = MPI3MR_MAX_SECTORS + 2; 1648 1649 sc->io_throttle_high = (sc->facts.io_throttle_high * 2 * 1024); 1650 sc->io_throttle_low = (sc->facts.io_throttle_low * 2 * 1024); 1651 1652 mpi3mr_dprint(sc, MPI3MR_INFO, "ioc_num(%d), maxopQ(%d), maxopRepQ(%d), maxdh(%d)," 1653 "maxreqs(%d), mindh(%d) maxPDs(%d) maxvectors(%d) maxperids(%d)\n", 1654 sc->facts.ioc_num, sc->facts.max_op_req_q, 1655 sc->facts.max_op_reply_q, sc->facts.max_devhandle, 1656 sc->facts.max_reqs, sc->facts.min_devhandle, 1657 sc->facts.max_pds, sc->facts.max_msix_vectors, 1658 sc->facts.max_perids); 1659 mpi3mr_dprint(sc, MPI3MR_INFO, "SGEModMask 0x%x SGEModVal 0x%x SGEModShift 0x%x\n", 1660 sc->facts.sge_mod_mask, sc->facts.sge_mod_value, 1661 sc->facts.sge_mod_shift); 1662 mpi3mr_dprint(sc, MPI3MR_INFO, 1663 "max_dev_per_throttle_group(%d), max_throttle_groups(%d), io_throttle_data_len(%dKiB), io_throttle_high(%dMiB), io_throttle_low(%dMiB)\n", 1664 sc->facts.max_dev_per_tg, sc->facts.max_io_throttle_group, 1665 sc->facts.io_throttle_data_length * 4, 1666 sc->facts.io_throttle_high, sc->facts.io_throttle_low); 1667 1668 sc->max_host_ios = sc->facts.max_reqs - 1669 (MPI3MR_INTERNALCMDS_RESVD + 1); 1670 1671 return retval; 1672 } 1673 1674 static inline void mpi3mr_setup_reply_free_queues(struct mpi3mr_softc *sc) 1675 { 1676 int i; 1677 bus_addr_t phys_addr; 1678 1679 /* initialize Reply buffer Queue */ 1680 for (i = 0, phys_addr = sc->reply_buf_phys; 1681 i < sc->num_reply_bufs; i++, phys_addr += sc->reply_sz) 1682 sc->reply_free_q[i] = phys_addr; 1683 sc->reply_free_q[i] = (0); 1684 1685 /* initialize Sense Buffer Queue */ 1686 for (i = 0, phys_addr = sc->sense_buf_phys; 1687 i < sc->num_sense_bufs; i++, phys_addr += MPI3MR_SENSEBUF_SZ) 1688 sc->sense_buf_q[i] = phys_addr; 1689 sc->sense_buf_q[i] = (0); 1690 1691 } 1692 1693 static int mpi3mr_reply_dma_alloc(struct mpi3mr_softc *sc) 1694 { 1695 U32 sz; 1696 1697 sc->num_reply_bufs = sc->facts.max_reqs + MPI3MR_NUM_EVTREPLIES; 1698 sc->reply_free_q_sz = sc->num_reply_bufs + 1; 1699 sc->num_sense_bufs = sc->facts.max_reqs / MPI3MR_SENSEBUF_FACTOR; 1700 sc->sense_buf_q_sz = sc->num_sense_bufs + 1; 1701 1702 sz = sc->num_reply_bufs * sc->reply_sz; 1703 1704 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 1705 16, 0, /* algnmnt, boundary */ 1706 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1707 BUS_SPACE_MAXADDR, /* highaddr */ 1708 NULL, NULL, /* filter, filterarg */ 1709 sz, /* maxsize */ 1710 1, /* nsegments */ 1711 sz, /* maxsegsize */ 1712 0, /* flags */ 1713 NULL, NULL, /* lockfunc, lockarg */ 1714 &sc->reply_buf_tag)) { 1715 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate request DMA tag\n"); 1716 return (ENOMEM); 1717 } 1718 1719 if (bus_dmamem_alloc(sc->reply_buf_tag, (void **)&sc->reply_buf, 1720 BUS_DMA_NOWAIT, &sc->reply_buf_dmamap)) { 1721 mpi3mr_dprint(sc, MPI3MR_ERROR, "Func: %s line: %d DMA mem alloc failed\n", 1722 __func__, __LINE__); 1723 return (ENOMEM); 1724 } 1725 1726 bzero(sc->reply_buf, sz); 1727 bus_dmamap_load(sc->reply_buf_tag, sc->reply_buf_dmamap, sc->reply_buf, sz, 1728 mpi3mr_memaddr_cb, &sc->reply_buf_phys, 0); 1729 1730 sc->reply_buf_dma_min_address = sc->reply_buf_phys; 1731 sc->reply_buf_dma_max_address = sc->reply_buf_phys + sz; 1732 mpi3mr_dprint(sc, MPI3MR_XINFO, "reply buf (0x%p): depth(%d), frame_size(%d), " 1733 "pool_size(%d kB), reply_buf_dma(0x%llx)\n", 1734 sc->reply_buf, sc->num_reply_bufs, sc->reply_sz, 1735 (sz / 1024), (unsigned long long)sc->reply_buf_phys); 1736 1737 /* reply free queue, 8 byte align */ 1738 sz = sc->reply_free_q_sz * 8; 1739 1740 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 1741 8, 0, /* algnmnt, boundary */ 1742 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1743 BUS_SPACE_MAXADDR, /* highaddr */ 1744 NULL, NULL, /* filter, filterarg */ 1745 sz, /* maxsize */ 1746 1, /* nsegments */ 1747 sz, /* maxsegsize */ 1748 0, /* flags */ 1749 NULL, NULL, /* lockfunc, lockarg */ 1750 &sc->reply_free_q_tag)) { 1751 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate reply free queue DMA tag\n"); 1752 return (ENOMEM); 1753 } 1754 1755 if (bus_dmamem_alloc(sc->reply_free_q_tag, (void **)&sc->reply_free_q, 1756 BUS_DMA_NOWAIT, &sc->reply_free_q_dmamap)) { 1757 mpi3mr_dprint(sc, MPI3MR_ERROR, "Func: %s line: %d DMA mem alloc failed\n", 1758 __func__, __LINE__); 1759 return (ENOMEM); 1760 } 1761 1762 bzero(sc->reply_free_q, sz); 1763 bus_dmamap_load(sc->reply_free_q_tag, sc->reply_free_q_dmamap, sc->reply_free_q, sz, 1764 mpi3mr_memaddr_cb, &sc->reply_free_q_phys, 0); 1765 1766 mpi3mr_dprint(sc, MPI3MR_XINFO, "reply_free_q (0x%p): depth(%d), frame_size(%d), " 1767 "pool_size(%d kB), reply_free_q_dma(0x%llx)\n", 1768 sc->reply_free_q, sc->reply_free_q_sz, 8, (sz / 1024), 1769 (unsigned long long)sc->reply_free_q_phys); 1770 1771 /* sense buffer pool, 4 byte align */ 1772 sz = sc->num_sense_bufs * MPI3MR_SENSEBUF_SZ; 1773 1774 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 1775 4, 0, /* algnmnt, boundary */ 1776 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1777 BUS_SPACE_MAXADDR, /* highaddr */ 1778 NULL, NULL, /* filter, filterarg */ 1779 sz, /* maxsize */ 1780 1, /* nsegments */ 1781 sz, /* maxsegsize */ 1782 0, /* flags */ 1783 NULL, NULL, /* lockfunc, lockarg */ 1784 &sc->sense_buf_tag)) { 1785 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate Sense buffer DMA tag\n"); 1786 return (ENOMEM); 1787 } 1788 1789 if (bus_dmamem_alloc(sc->sense_buf_tag, (void **)&sc->sense_buf, 1790 BUS_DMA_NOWAIT, &sc->sense_buf_dmamap)) { 1791 mpi3mr_dprint(sc, MPI3MR_ERROR, "Func: %s line: %d DMA mem alloc failed\n", 1792 __func__, __LINE__); 1793 return (ENOMEM); 1794 } 1795 1796 bzero(sc->sense_buf, sz); 1797 bus_dmamap_load(sc->sense_buf_tag, sc->sense_buf_dmamap, sc->sense_buf, sz, 1798 mpi3mr_memaddr_cb, &sc->sense_buf_phys, 0); 1799 1800 mpi3mr_dprint(sc, MPI3MR_XINFO, "sense_buf (0x%p): depth(%d), frame_size(%d), " 1801 "pool_size(%d kB), sense_dma(0x%llx)\n", 1802 sc->sense_buf, sc->num_sense_bufs, MPI3MR_SENSEBUF_SZ, 1803 (sz / 1024), (unsigned long long)sc->sense_buf_phys); 1804 1805 /* sense buffer queue, 8 byte align */ 1806 sz = sc->sense_buf_q_sz * 8; 1807 1808 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 1809 8, 0, /* algnmnt, boundary */ 1810 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1811 BUS_SPACE_MAXADDR, /* highaddr */ 1812 NULL, NULL, /* filter, filterarg */ 1813 sz, /* maxsize */ 1814 1, /* nsegments */ 1815 sz, /* maxsegsize */ 1816 0, /* flags */ 1817 NULL, NULL, /* lockfunc, lockarg */ 1818 &sc->sense_buf_q_tag)) { 1819 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate Sense buffer Queue DMA tag\n"); 1820 return (ENOMEM); 1821 } 1822 1823 if (bus_dmamem_alloc(sc->sense_buf_q_tag, (void **)&sc->sense_buf_q, 1824 BUS_DMA_NOWAIT, &sc->sense_buf_q_dmamap)) { 1825 mpi3mr_dprint(sc, MPI3MR_ERROR, "Func: %s line: %d DMA mem alloc failed\n", 1826 __func__, __LINE__); 1827 return (ENOMEM); 1828 } 1829 1830 bzero(sc->sense_buf_q, sz); 1831 bus_dmamap_load(sc->sense_buf_q_tag, sc->sense_buf_q_dmamap, sc->sense_buf_q, sz, 1832 mpi3mr_memaddr_cb, &sc->sense_buf_q_phys, 0); 1833 1834 mpi3mr_dprint(sc, MPI3MR_XINFO, "sense_buf_q (0x%p): depth(%d), frame_size(%d), " 1835 "pool_size(%d kB), sense_dma(0x%llx)\n", 1836 sc->sense_buf_q, sc->sense_buf_q_sz, 8, (sz / 1024), 1837 (unsigned long long)sc->sense_buf_q_phys); 1838 1839 return 0; 1840 } 1841 1842 static int mpi3mr_reply_alloc(struct mpi3mr_softc *sc) 1843 { 1844 int retval = 0; 1845 U32 i; 1846 1847 if (sc->init_cmds.reply) 1848 goto post_reply_sbuf; 1849 1850 sc->init_cmds.reply = malloc(sc->reply_sz, 1851 M_MPI3MR, M_NOWAIT | M_ZERO); 1852 1853 if (!sc->init_cmds.reply) { 1854 printf(IOCNAME "Cannot allocate memory for init_cmds.reply\n", 1855 sc->name); 1856 goto out_failed; 1857 } 1858 1859 sc->ioctl_cmds.reply = malloc(sc->reply_sz, M_MPI3MR, M_NOWAIT | M_ZERO); 1860 if (!sc->ioctl_cmds.reply) { 1861 printf(IOCNAME "Cannot allocate memory for ioctl_cmds.reply\n", 1862 sc->name); 1863 goto out_failed; 1864 } 1865 1866 sc->host_tm_cmds.reply = malloc(sc->reply_sz, M_MPI3MR, M_NOWAIT | M_ZERO); 1867 if (!sc->host_tm_cmds.reply) { 1868 printf(IOCNAME "Cannot allocate memory for host_tm.reply\n", 1869 sc->name); 1870 goto out_failed; 1871 } 1872 for (i=0; i<MPI3MR_NUM_DEVRMCMD; i++) { 1873 sc->dev_rmhs_cmds[i].reply = malloc(sc->reply_sz, 1874 M_MPI3MR, M_NOWAIT | M_ZERO); 1875 if (!sc->dev_rmhs_cmds[i].reply) { 1876 printf(IOCNAME "Cannot allocate memory for" 1877 " dev_rmhs_cmd[%d].reply\n", 1878 sc->name, i); 1879 goto out_failed; 1880 } 1881 } 1882 1883 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 1884 sc->evtack_cmds[i].reply = malloc(sc->reply_sz, 1885 M_MPI3MR, M_NOWAIT | M_ZERO); 1886 if (!sc->evtack_cmds[i].reply) 1887 goto out_failed; 1888 } 1889 1890 sc->dev_handle_bitmap_sz = MPI3MR_DIV_ROUND_UP(sc->facts.max_devhandle, 8); 1891 1892 sc->removepend_bitmap = malloc(sc->dev_handle_bitmap_sz, 1893 M_MPI3MR, M_NOWAIT | M_ZERO); 1894 if (!sc->removepend_bitmap) { 1895 printf(IOCNAME "Cannot alloc memory for remove pend bitmap\n", 1896 sc->name); 1897 goto out_failed; 1898 } 1899 1900 sc->devrem_bitmap_sz = MPI3MR_DIV_ROUND_UP(MPI3MR_NUM_DEVRMCMD, 8); 1901 sc->devrem_bitmap = malloc(sc->devrem_bitmap_sz, 1902 M_MPI3MR, M_NOWAIT | M_ZERO); 1903 if (!sc->devrem_bitmap) { 1904 printf(IOCNAME "Cannot alloc memory for dev remove bitmap\n", 1905 sc->name); 1906 goto out_failed; 1907 } 1908 1909 sc->evtack_cmds_bitmap_sz = MPI3MR_DIV_ROUND_UP(MPI3MR_NUM_EVTACKCMD, 8); 1910 1911 sc->evtack_cmds_bitmap = malloc(sc->evtack_cmds_bitmap_sz, 1912 M_MPI3MR, M_NOWAIT | M_ZERO); 1913 if (!sc->evtack_cmds_bitmap) 1914 goto out_failed; 1915 1916 if (mpi3mr_reply_dma_alloc(sc)) { 1917 printf(IOCNAME "func:%s line:%d DMA memory allocation failed\n", 1918 sc->name, __func__, __LINE__); 1919 goto out_failed; 1920 } 1921 1922 post_reply_sbuf: 1923 mpi3mr_setup_reply_free_queues(sc); 1924 return retval; 1925 out_failed: 1926 mpi3mr_cleanup_interrupts(sc); 1927 mpi3mr_free_mem(sc); 1928 retval = -1; 1929 return retval; 1930 } 1931 1932 static void 1933 mpi3mr_print_fw_pkg_ver(struct mpi3mr_softc *sc) 1934 { 1935 int retval = 0; 1936 void *fw_pkg_ver = NULL; 1937 bus_dma_tag_t fw_pkg_ver_tag; 1938 bus_dmamap_t fw_pkg_ver_map; 1939 bus_addr_t fw_pkg_ver_dma; 1940 Mpi3CIUploadRequest_t ci_upload; 1941 Mpi3ComponentImageHeader_t *ci_header; 1942 U32 fw_pkg_ver_len = sizeof(*ci_header); 1943 U8 sgl_flags = MPI3MR_SGEFLAGS_SYSTEM_SIMPLE_END_OF_LIST; 1944 1945 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 1946 4, 0, /* algnmnt, boundary */ 1947 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1948 BUS_SPACE_MAXADDR, /* highaddr */ 1949 NULL, NULL, /* filter, filterarg */ 1950 fw_pkg_ver_len, /* maxsize */ 1951 1, /* nsegments */ 1952 fw_pkg_ver_len, /* maxsegsize */ 1953 0, /* flags */ 1954 NULL, NULL, /* lockfunc, lockarg */ 1955 &fw_pkg_ver_tag)) { 1956 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate fw package version request DMA tag\n"); 1957 return; 1958 } 1959 1960 if (bus_dmamem_alloc(fw_pkg_ver_tag, (void **)&fw_pkg_ver, BUS_DMA_NOWAIT, &fw_pkg_ver_map)) { 1961 mpi3mr_dprint(sc, MPI3MR_ERROR, "Func: %s line: %d fw package version DMA mem alloc failed\n", 1962 __func__, __LINE__); 1963 return; 1964 } 1965 1966 bzero(fw_pkg_ver, fw_pkg_ver_len); 1967 1968 bus_dmamap_load(fw_pkg_ver_tag, fw_pkg_ver_map, fw_pkg_ver, fw_pkg_ver_len, mpi3mr_memaddr_cb, &fw_pkg_ver_dma, 0); 1969 1970 mpi3mr_dprint(sc, MPI3MR_XINFO, "Func: %s line: %d fw package version phys addr= %#016jx size= %d\n", 1971 __func__, __LINE__, (uintmax_t)fw_pkg_ver_dma, fw_pkg_ver_len); 1972 1973 if (!fw_pkg_ver) { 1974 mpi3mr_dprint(sc, MPI3MR_ERROR, "Memory alloc for fw package version failed\n"); 1975 goto out; 1976 } 1977 1978 memset(&ci_upload, 0, sizeof(ci_upload)); 1979 mtx_lock(&sc->init_cmds.completion.lock); 1980 if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { 1981 mpi3mr_dprint(sc, MPI3MR_INFO,"Issue CI Header Upload: command is in use\n"); 1982 mtx_unlock(&sc->init_cmds.completion.lock); 1983 goto out; 1984 } 1985 sc->init_cmds.state = MPI3MR_CMD_PENDING; 1986 sc->init_cmds.is_waiting = 1; 1987 sc->init_cmds.callback = NULL; 1988 ci_upload.HostTag = htole16(MPI3MR_HOSTTAG_INITCMDS); 1989 ci_upload.Function = MPI3_FUNCTION_CI_UPLOAD; 1990 ci_upload.MsgFlags = MPI3_CI_UPLOAD_MSGFLAGS_LOCATION_PRIMARY; 1991 ci_upload.ImageOffset = MPI3_IMAGE_HEADER_SIGNATURE0_OFFSET; 1992 ci_upload.SegmentSize = MPI3_IMAGE_HEADER_SIZE; 1993 1994 mpi3mr_add_sg_single(&ci_upload.SGL, sgl_flags, fw_pkg_ver_len, 1995 fw_pkg_ver_dma); 1996 1997 init_completion(&sc->init_cmds.completion); 1998 if ((retval = mpi3mr_submit_admin_cmd(sc, &ci_upload, sizeof(ci_upload)))) { 1999 mpi3mr_dprint(sc, MPI3MR_ERROR, "Issue CI Header Upload: Admin Post failed\n"); 2000 goto out_unlock; 2001 } 2002 wait_for_completion_timeout(&sc->init_cmds.completion, 2003 (MPI3MR_INTADMCMD_TIMEOUT)); 2004 if (!(sc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2005 mpi3mr_dprint(sc, MPI3MR_ERROR, "Issue CI Header Upload: command timed out\n"); 2006 sc->init_cmds.is_waiting = 0; 2007 if (!(sc->init_cmds.state & MPI3MR_CMD_RESET)) 2008 mpi3mr_check_rh_fault_ioc(sc, 2009 MPI3MR_RESET_FROM_GETPKGVER_TIMEOUT); 2010 goto out_unlock; 2011 } 2012 if ((GET_IOC_STATUS(sc->init_cmds.ioc_status)) != MPI3_IOCSTATUS_SUCCESS) { 2013 mpi3mr_dprint(sc, MPI3MR_ERROR, 2014 "Issue CI Header Upload: Failed IOCStatus(0x%04x) Loginfo(0x%08x)\n", 2015 GET_IOC_STATUS(sc->init_cmds.ioc_status), sc->init_cmds.ioc_loginfo); 2016 goto out_unlock; 2017 } 2018 2019 ci_header = (Mpi3ComponentImageHeader_t *) fw_pkg_ver; 2020 mpi3mr_dprint(sc, MPI3MR_XINFO, 2021 "Issue CI Header Upload:EnvVariableOffset(0x%x) \ 2022 HeaderSize(0x%x) Signature1(0x%x)\n", 2023 ci_header->EnvironmentVariableOffset, 2024 ci_header->HeaderSize, 2025 ci_header->Signature1); 2026 mpi3mr_dprint(sc, MPI3MR_INFO, "FW Package Version: %02d.%02d.%02d.%02d\n", 2027 ci_header->ComponentImageVersion.GenMajor, 2028 ci_header->ComponentImageVersion.GenMinor, 2029 ci_header->ComponentImageVersion.PhaseMajor, 2030 ci_header->ComponentImageVersion.PhaseMinor); 2031 out_unlock: 2032 sc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2033 mtx_unlock(&sc->init_cmds.completion.lock); 2034 2035 out: 2036 if (fw_pkg_ver_dma != 0) 2037 bus_dmamap_unload(fw_pkg_ver_tag, fw_pkg_ver_map); 2038 if (fw_pkg_ver) 2039 bus_dmamem_free(fw_pkg_ver_tag, fw_pkg_ver, fw_pkg_ver_map); 2040 if (fw_pkg_ver_tag) 2041 bus_dma_tag_destroy(fw_pkg_ver_tag); 2042 2043 } 2044 2045 /** 2046 * mpi3mr_issue_iocinit - Send IOC Init 2047 * @sc: Adapter instance reference 2048 * 2049 * Issue IOC Init MPI request through admin queue and wait for 2050 * the completion of it or time out. 2051 * 2052 * Return: 0 on success, non-zero on failures. 2053 */ 2054 static int mpi3mr_issue_iocinit(struct mpi3mr_softc *sc) 2055 { 2056 Mpi3IOCInitRequest_t iocinit_req; 2057 Mpi3DriverInfoLayout_t *drvr_info = NULL; 2058 bus_dma_tag_t drvr_info_tag; 2059 bus_dmamap_t drvr_info_map; 2060 bus_addr_t drvr_info_phys; 2061 U32 drvr_info_len = sizeof(*drvr_info); 2062 int retval = 0; 2063 struct timeval now; 2064 uint64_t time_in_msec; 2065 2066 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 2067 4, 0, /* algnmnt, boundary */ 2068 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 2069 BUS_SPACE_MAXADDR, /* highaddr */ 2070 NULL, NULL, /* filter, filterarg */ 2071 drvr_info_len, /* maxsize */ 2072 1, /* nsegments */ 2073 drvr_info_len, /* maxsegsize */ 2074 0, /* flags */ 2075 NULL, NULL, /* lockfunc, lockarg */ 2076 &drvr_info_tag)) { 2077 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate request DMA tag\n"); 2078 return (ENOMEM); 2079 } 2080 2081 if (bus_dmamem_alloc(drvr_info_tag, (void **)&drvr_info, 2082 BUS_DMA_NOWAIT, &drvr_info_map)) { 2083 mpi3mr_dprint(sc, MPI3MR_ERROR, "Func: %s line: %d Data DMA mem alloc failed\n", 2084 __func__, __LINE__); 2085 return (ENOMEM); 2086 } 2087 2088 bzero(drvr_info, drvr_info_len); 2089 bus_dmamap_load(drvr_info_tag, drvr_info_map, drvr_info, drvr_info_len, 2090 mpi3mr_memaddr_cb, &drvr_info_phys, 0); 2091 mpi3mr_dprint(sc, MPI3MR_XINFO, "Func: %s line: %d IOCfacts drvr_info phys addr= %#016jx size= %d\n", 2092 __func__, __LINE__, (uintmax_t)drvr_info_phys, drvr_info_len); 2093 2094 if (!drvr_info) 2095 { 2096 retval = -1; 2097 printf(IOCNAME "Memory alloc for Driver Info failed\n", 2098 sc->name); 2099 goto out; 2100 } 2101 drvr_info->InformationLength = (drvr_info_len); 2102 strcpy(drvr_info->DriverSignature, "Broadcom"); 2103 strcpy(drvr_info->OsName, "FreeBSD"); 2104 strcpy(drvr_info->OsVersion, fmt_os_ver); 2105 strcpy(drvr_info->DriverName, MPI3MR_DRIVER_NAME); 2106 strcpy(drvr_info->DriverVersion, MPI3MR_DRIVER_VERSION); 2107 strcpy(drvr_info->DriverReleaseDate, MPI3MR_DRIVER_RELDATE); 2108 drvr_info->DriverCapabilities = 0; 2109 memcpy((U8 *)&sc->driver_info, (U8 *)drvr_info, sizeof(sc->driver_info)); 2110 2111 memset(&iocinit_req, 0, sizeof(iocinit_req)); 2112 mtx_lock(&sc->init_cmds.completion.lock); 2113 if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { 2114 retval = -1; 2115 printf(IOCNAME "Issue IOCInit: Init command is in use\n", 2116 sc->name); 2117 mtx_unlock(&sc->init_cmds.completion.lock); 2118 goto out; 2119 } 2120 sc->init_cmds.state = MPI3MR_CMD_PENDING; 2121 sc->init_cmds.is_waiting = 1; 2122 sc->init_cmds.callback = NULL; 2123 iocinit_req.HostTag = MPI3MR_HOSTTAG_INITCMDS; 2124 iocinit_req.Function = MPI3_FUNCTION_IOC_INIT; 2125 iocinit_req.MPIVersion.Struct.Dev = MPI3_VERSION_DEV; 2126 iocinit_req.MPIVersion.Struct.Unit = MPI3_VERSION_UNIT; 2127 iocinit_req.MPIVersion.Struct.Major = MPI3_VERSION_MAJOR; 2128 iocinit_req.MPIVersion.Struct.Minor = MPI3_VERSION_MINOR; 2129 iocinit_req.WhoInit = MPI3_WHOINIT_HOST_DRIVER; 2130 iocinit_req.ReplyFreeQueueDepth = sc->reply_free_q_sz; 2131 iocinit_req.ReplyFreeQueueAddress = 2132 sc->reply_free_q_phys; 2133 iocinit_req.SenseBufferLength = MPI3MR_SENSEBUF_SZ; 2134 iocinit_req.SenseBufferFreeQueueDepth = 2135 sc->sense_buf_q_sz; 2136 iocinit_req.SenseBufferFreeQueueAddress = 2137 sc->sense_buf_q_phys; 2138 iocinit_req.DriverInformationAddress = drvr_info_phys; 2139 2140 getmicrotime(&now); 2141 time_in_msec = (now.tv_sec * 1000 + now.tv_usec/1000); 2142 iocinit_req.TimeStamp = htole64(time_in_msec); 2143 2144 init_completion(&sc->init_cmds.completion); 2145 retval = mpi3mr_submit_admin_cmd(sc, &iocinit_req, 2146 sizeof(iocinit_req)); 2147 2148 if (retval) { 2149 printf(IOCNAME "Issue IOCInit: Admin Post failed\n", 2150 sc->name); 2151 goto out_unlock; 2152 } 2153 2154 wait_for_completion_timeout(&sc->init_cmds.completion, 2155 (MPI3MR_INTADMCMD_TIMEOUT)); 2156 if (!(sc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2157 printf(IOCNAME "Issue IOCInit: command timed out\n", 2158 sc->name); 2159 mpi3mr_check_rh_fault_ioc(sc, 2160 MPI3MR_RESET_FROM_IOCINIT_TIMEOUT); 2161 sc->unrecoverable = 1; 2162 retval = -1; 2163 goto out_unlock; 2164 } 2165 2166 if ((sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2167 != MPI3_IOCSTATUS_SUCCESS ) { 2168 printf(IOCNAME "Issue IOCInit: Failed IOCStatus(0x%04x) " 2169 " Loginfo(0x%08x) \n" , sc->name, 2170 (sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2171 sc->init_cmds.ioc_loginfo); 2172 retval = -1; 2173 goto out_unlock; 2174 } 2175 2176 out_unlock: 2177 sc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2178 mtx_unlock(&sc->init_cmds.completion.lock); 2179 2180 out: 2181 if (drvr_info_phys != 0) 2182 bus_dmamap_unload(drvr_info_tag, drvr_info_map); 2183 if (drvr_info != NULL) 2184 bus_dmamem_free(drvr_info_tag, drvr_info, drvr_info_map); 2185 if (drvr_info_tag != NULL) 2186 bus_dma_tag_destroy(drvr_info_tag); 2187 return retval; 2188 } 2189 2190 static void 2191 mpi3mr_display_ioc_info(struct mpi3mr_softc *sc) 2192 { 2193 int i = 0; 2194 char personality[16]; 2195 struct mpi3mr_compimg_ver *fwver = &sc->facts.fw_ver; 2196 2197 switch (sc->facts.personality) { 2198 case MPI3_IOCFACTS_FLAGS_PERSONALITY_EHBA: 2199 strcpy(personality, "Enhanced HBA"); 2200 break; 2201 case MPI3_IOCFACTS_FLAGS_PERSONALITY_RAID_DDR: 2202 strcpy(personality, "RAID"); 2203 break; 2204 default: 2205 strcpy(personality, "Unknown"); 2206 break; 2207 } 2208 2209 mpi3mr_dprint(sc, MPI3MR_INFO, "Current Personality: %s\n", personality); 2210 2211 mpi3mr_dprint(sc, MPI3MR_INFO, "FW Version: %d.%d.%d.%d.%05d-%05d\n", 2212 fwver->gen_major, fwver->gen_minor, fwver->ph_major, 2213 fwver->ph_minor, fwver->cust_id, fwver->build_num); 2214 2215 mpi3mr_dprint(sc, MPI3MR_INFO, "Protocol=("); 2216 2217 if (sc->facts.protocol_flags & 2218 MPI3_IOCFACTS_PROTOCOL_SCSI_INITIATOR) { 2219 printf("Initiator"); 2220 i++; 2221 } 2222 2223 if (sc->facts.protocol_flags & 2224 MPI3_IOCFACTS_PROTOCOL_SCSI_TARGET) { 2225 printf("%sTarget", i ? "," : ""); 2226 i++; 2227 } 2228 2229 if (sc->facts.protocol_flags & 2230 MPI3_IOCFACTS_PROTOCOL_NVME) { 2231 printf("%sNVMe attachment", i ? "," : ""); 2232 i++; 2233 } 2234 i = 0; 2235 printf("), "); 2236 printf("Capabilities=("); 2237 2238 if (sc->facts.ioc_capabilities & 2239 MPI3_IOCFACTS_CAPABILITY_RAID_CAPABLE) { 2240 printf("RAID"); 2241 i++; 2242 } 2243 2244 printf(")\n"); 2245 } 2246 2247 /** 2248 * mpi3mr_unmask_events - Unmask events in event mask bitmap 2249 * @sc: Adapter instance reference 2250 * @event: MPI event ID 2251 * 2252 * Un mask the specific event by resetting the event_mask 2253 * bitmap. 2254 * 2255 * Return: None. 2256 */ 2257 static void mpi3mr_unmask_events(struct mpi3mr_softc *sc, U16 event) 2258 { 2259 U32 desired_event; 2260 2261 if (event >= 128) 2262 return; 2263 2264 desired_event = (1 << (event % 32)); 2265 2266 if (event < 32) 2267 sc->event_masks[0] &= ~desired_event; 2268 else if (event < 64) 2269 sc->event_masks[1] &= ~desired_event; 2270 else if (event < 96) 2271 sc->event_masks[2] &= ~desired_event; 2272 else if (event < 128) 2273 sc->event_masks[3] &= ~desired_event; 2274 } 2275 2276 static void mpi3mr_set_events_mask(struct mpi3mr_softc *sc) 2277 { 2278 int i; 2279 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 2280 sc->event_masks[i] = -1; 2281 2282 mpi3mr_unmask_events(sc, MPI3_EVENT_DEVICE_ADDED); 2283 mpi3mr_unmask_events(sc, MPI3_EVENT_DEVICE_INFO_CHANGED); 2284 mpi3mr_unmask_events(sc, MPI3_EVENT_DEVICE_STATUS_CHANGE); 2285 2286 mpi3mr_unmask_events(sc, MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE); 2287 2288 mpi3mr_unmask_events(sc, MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST); 2289 mpi3mr_unmask_events(sc, MPI3_EVENT_SAS_DISCOVERY); 2290 mpi3mr_unmask_events(sc, MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR); 2291 mpi3mr_unmask_events(sc, MPI3_EVENT_SAS_BROADCAST_PRIMITIVE); 2292 2293 mpi3mr_unmask_events(sc, MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST); 2294 mpi3mr_unmask_events(sc, MPI3_EVENT_PCIE_ENUMERATION); 2295 2296 mpi3mr_unmask_events(sc, MPI3_EVENT_PREPARE_FOR_RESET); 2297 mpi3mr_unmask_events(sc, MPI3_EVENT_CABLE_MGMT); 2298 mpi3mr_unmask_events(sc, MPI3_EVENT_ENERGY_PACK_CHANGE); 2299 } 2300 2301 /** 2302 * mpi3mr_issue_event_notification - Send event notification 2303 * @sc: Adapter instance reference 2304 * 2305 * Issue event notification MPI request through admin queue and 2306 * wait for the completion of it or time out. 2307 * 2308 * Return: 0 on success, non-zero on failures. 2309 */ 2310 int mpi3mr_issue_event_notification(struct mpi3mr_softc *sc) 2311 { 2312 Mpi3EventNotificationRequest_t evtnotify_req; 2313 int retval = 0; 2314 U8 i; 2315 2316 memset(&evtnotify_req, 0, sizeof(evtnotify_req)); 2317 mtx_lock(&sc->init_cmds.completion.lock); 2318 if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { 2319 retval = -1; 2320 printf(IOCNAME "Issue EvtNotify: Init command is in use\n", 2321 sc->name); 2322 mtx_unlock(&sc->init_cmds.completion.lock); 2323 goto out; 2324 } 2325 sc->init_cmds.state = MPI3MR_CMD_PENDING; 2326 sc->init_cmds.is_waiting = 1; 2327 sc->init_cmds.callback = NULL; 2328 evtnotify_req.HostTag = (MPI3MR_HOSTTAG_INITCMDS); 2329 evtnotify_req.Function = MPI3_FUNCTION_EVENT_NOTIFICATION; 2330 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 2331 evtnotify_req.EventMasks[i] = 2332 (sc->event_masks[i]); 2333 init_completion(&sc->init_cmds.completion); 2334 retval = mpi3mr_submit_admin_cmd(sc, &evtnotify_req, 2335 sizeof(evtnotify_req)); 2336 if (retval) { 2337 printf(IOCNAME "Issue EvtNotify: Admin Post failed\n", 2338 sc->name); 2339 goto out_unlock; 2340 } 2341 2342 poll_for_command_completion(sc, 2343 &sc->init_cmds, 2344 (MPI3MR_INTADMCMD_TIMEOUT)); 2345 if (!(sc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2346 printf(IOCNAME "Issue EvtNotify: command timed out\n", 2347 sc->name); 2348 mpi3mr_check_rh_fault_ioc(sc, 2349 MPI3MR_RESET_FROM_EVTNOTIFY_TIMEOUT); 2350 retval = -1; 2351 goto out_unlock; 2352 } 2353 2354 if ((sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2355 != MPI3_IOCSTATUS_SUCCESS ) { 2356 printf(IOCNAME "Issue EvtNotify: Failed IOCStatus(0x%04x) " 2357 " Loginfo(0x%08x) \n" , sc->name, 2358 (sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2359 sc->init_cmds.ioc_loginfo); 2360 retval = -1; 2361 goto out_unlock; 2362 } 2363 2364 out_unlock: 2365 sc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2366 mtx_unlock(&sc->init_cmds.completion.lock); 2367 2368 out: 2369 return retval; 2370 } 2371 2372 int 2373 mpi3mr_register_events(struct mpi3mr_softc *sc) 2374 { 2375 int error; 2376 2377 mpi3mr_set_events_mask(sc); 2378 2379 error = mpi3mr_issue_event_notification(sc); 2380 2381 if (error) { 2382 printf(IOCNAME "Failed to issue event notification %d\n", 2383 sc->name, error); 2384 } 2385 2386 return error; 2387 } 2388 2389 /** 2390 * mpi3mr_process_event_ack - Process event acknowledgment 2391 * @sc: Adapter instance reference 2392 * @event: MPI3 event ID 2393 * @event_ctx: Event context 2394 * 2395 * Send event acknowledgement through admin queue and wait for 2396 * it to complete. 2397 * 2398 * Return: 0 on success, non-zero on failures. 2399 */ 2400 int mpi3mr_process_event_ack(struct mpi3mr_softc *sc, U8 event, 2401 U32 event_ctx) 2402 { 2403 Mpi3EventAckRequest_t evtack_req; 2404 int retval = 0; 2405 2406 memset(&evtack_req, 0, sizeof(evtack_req)); 2407 mtx_lock(&sc->init_cmds.completion.lock); 2408 if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { 2409 retval = -1; 2410 printf(IOCNAME "Issue EvtAck: Init command is in use\n", 2411 sc->name); 2412 mtx_unlock(&sc->init_cmds.completion.lock); 2413 goto out; 2414 } 2415 sc->init_cmds.state = MPI3MR_CMD_PENDING; 2416 sc->init_cmds.is_waiting = 1; 2417 sc->init_cmds.callback = NULL; 2418 evtack_req.HostTag = htole16(MPI3MR_HOSTTAG_INITCMDS); 2419 evtack_req.Function = MPI3_FUNCTION_EVENT_ACK; 2420 evtack_req.Event = event; 2421 evtack_req.EventContext = htole32(event_ctx); 2422 2423 init_completion(&sc->init_cmds.completion); 2424 retval = mpi3mr_submit_admin_cmd(sc, &evtack_req, 2425 sizeof(evtack_req)); 2426 if (retval) { 2427 printf(IOCNAME "Issue EvtAck: Admin Post failed\n", 2428 sc->name); 2429 goto out_unlock; 2430 } 2431 2432 wait_for_completion_timeout(&sc->init_cmds.completion, 2433 (MPI3MR_INTADMCMD_TIMEOUT)); 2434 if (!(sc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 2435 printf(IOCNAME "Issue EvtAck: command timed out\n", 2436 sc->name); 2437 retval = -1; 2438 goto out_unlock; 2439 } 2440 2441 if ((sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK) 2442 != MPI3_IOCSTATUS_SUCCESS ) { 2443 printf(IOCNAME "Issue EvtAck: Failed IOCStatus(0x%04x) " 2444 " Loginfo(0x%08x) \n" , sc->name, 2445 (sc->init_cmds.ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 2446 sc->init_cmds.ioc_loginfo); 2447 retval = -1; 2448 goto out_unlock; 2449 } 2450 2451 out_unlock: 2452 sc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2453 mtx_unlock(&sc->init_cmds.completion.lock); 2454 2455 out: 2456 return retval; 2457 } 2458 2459 2460 static int mpi3mr_alloc_chain_bufs(struct mpi3mr_softc *sc) 2461 { 2462 int retval = 0; 2463 U32 sz, i; 2464 U16 num_chains; 2465 2466 num_chains = sc->max_host_ios; 2467 2468 sc->chain_buf_count = num_chains; 2469 sz = sizeof(struct mpi3mr_chain) * num_chains; 2470 2471 sc->chain_sgl_list = malloc(sz, M_MPI3MR, M_NOWAIT | M_ZERO); 2472 2473 if (!sc->chain_sgl_list) { 2474 printf(IOCNAME "Cannot allocate memory for chain SGL list\n", 2475 sc->name); 2476 retval = -1; 2477 goto out_failed; 2478 } 2479 2480 sz = MPI3MR_CHAINSGE_SIZE; 2481 2482 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 2483 4096, 0, /* algnmnt, boundary */ 2484 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 2485 BUS_SPACE_MAXADDR, /* highaddr */ 2486 NULL, NULL, /* filter, filterarg */ 2487 sz, /* maxsize */ 2488 1, /* nsegments */ 2489 sz, /* maxsegsize */ 2490 0, /* flags */ 2491 NULL, NULL, /* lockfunc, lockarg */ 2492 &sc->chain_sgl_list_tag)) { 2493 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate Chain buffer DMA tag\n"); 2494 return (ENOMEM); 2495 } 2496 2497 for (i = 0; i < num_chains; i++) { 2498 if (bus_dmamem_alloc(sc->chain_sgl_list_tag, (void **)&sc->chain_sgl_list[i].buf, 2499 BUS_DMA_NOWAIT, &sc->chain_sgl_list[i].buf_dmamap)) { 2500 mpi3mr_dprint(sc, MPI3MR_ERROR, "Func: %s line: %d DMA mem alloc failed\n", 2501 __func__, __LINE__); 2502 return (ENOMEM); 2503 } 2504 2505 bzero(sc->chain_sgl_list[i].buf, sz); 2506 bus_dmamap_load(sc->chain_sgl_list_tag, sc->chain_sgl_list[i].buf_dmamap, sc->chain_sgl_list[i].buf, sz, 2507 mpi3mr_memaddr_cb, &sc->chain_sgl_list[i].buf_phys, 0); 2508 mpi3mr_dprint(sc, MPI3MR_XINFO, "Func: %s line: %d phys addr= %#016jx size= %d\n", 2509 __func__, __LINE__, (uintmax_t)sc->chain_sgl_list[i].buf_phys, sz); 2510 } 2511 2512 sc->chain_bitmap_sz = MPI3MR_DIV_ROUND_UP(num_chains, 8); 2513 2514 sc->chain_bitmap = malloc(sc->chain_bitmap_sz, M_MPI3MR, M_NOWAIT | M_ZERO); 2515 if (!sc->chain_bitmap) { 2516 mpi3mr_dprint(sc, MPI3MR_INFO, "Cannot alloc memory for chain bitmap\n"); 2517 retval = -1; 2518 goto out_failed; 2519 } 2520 return retval; 2521 2522 out_failed: 2523 for (i = 0; i < num_chains; i++) { 2524 if (sc->chain_sgl_list[i].buf_phys != 0) 2525 bus_dmamap_unload(sc->chain_sgl_list_tag, sc->chain_sgl_list[i].buf_dmamap); 2526 if (sc->chain_sgl_list[i].buf != NULL) 2527 bus_dmamem_free(sc->chain_sgl_list_tag, sc->chain_sgl_list[i].buf, sc->chain_sgl_list[i].buf_dmamap); 2528 } 2529 if (sc->chain_sgl_list_tag != NULL) 2530 bus_dma_tag_destroy(sc->chain_sgl_list_tag); 2531 return retval; 2532 } 2533 2534 static int mpi3mr_pel_alloc(struct mpi3mr_softc *sc) 2535 { 2536 int retval = 0; 2537 2538 if (!sc->pel_cmds.reply) { 2539 sc->pel_cmds.reply = malloc(sc->reply_sz, M_MPI3MR, M_NOWAIT | M_ZERO); 2540 if (!sc->pel_cmds.reply) { 2541 printf(IOCNAME "Cannot allocate memory for pel_cmds.reply\n", 2542 sc->name); 2543 goto out_failed; 2544 } 2545 } 2546 2547 if (!sc->pel_abort_cmd.reply) { 2548 sc->pel_abort_cmd.reply = malloc(sc->reply_sz, M_MPI3MR, M_NOWAIT | M_ZERO); 2549 if (!sc->pel_abort_cmd.reply) { 2550 printf(IOCNAME "Cannot allocate memory for pel_abort_cmd.reply\n", 2551 sc->name); 2552 goto out_failed; 2553 } 2554 } 2555 2556 if (!sc->pel_seq_number) { 2557 sc->pel_seq_number_sz = sizeof(Mpi3PELSeq_t); 2558 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 2559 4, 0, /* alignment, boundary */ 2560 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 2561 BUS_SPACE_MAXADDR, /* highaddr */ 2562 NULL, NULL, /* filter, filterarg */ 2563 sc->pel_seq_number_sz, /* maxsize */ 2564 1, /* nsegments */ 2565 sc->pel_seq_number_sz, /* maxsegsize */ 2566 0, /* flags */ 2567 NULL, NULL, /* lockfunc, lockarg */ 2568 &sc->pel_seq_num_dmatag)) { 2569 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot create PEL seq number dma memory tag\n"); 2570 retval = -ENOMEM; 2571 goto out_failed; 2572 } 2573 2574 if (bus_dmamem_alloc(sc->pel_seq_num_dmatag, (void **)&sc->pel_seq_number, 2575 BUS_DMA_NOWAIT, &sc->pel_seq_num_dmamap)) { 2576 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate PEL seq number kernel buffer dma memory\n"); 2577 retval = -ENOMEM; 2578 goto out_failed; 2579 } 2580 2581 bzero(sc->pel_seq_number, sc->pel_seq_number_sz); 2582 2583 bus_dmamap_load(sc->pel_seq_num_dmatag, sc->pel_seq_num_dmamap, sc->pel_seq_number, 2584 sc->pel_seq_number_sz, mpi3mr_memaddr_cb, &sc->pel_seq_number_dma, 0); 2585 2586 if (!sc->pel_seq_number) { 2587 printf(IOCNAME "%s:%d Cannot load PEL seq number dma memory for size: %d\n", sc->name, 2588 __func__, __LINE__, sc->pel_seq_number_sz); 2589 retval = -ENOMEM; 2590 goto out_failed; 2591 } 2592 } 2593 2594 out_failed: 2595 return retval; 2596 } 2597 2598 /** 2599 * mpi3mr_validate_fw_update - validate IOCFacts post adapter reset 2600 * @sc: Adapter instance reference 2601 * 2602 * Return zero if the new IOCFacts is compatible with previous values 2603 * else return appropriate error 2604 */ 2605 static int 2606 mpi3mr_validate_fw_update(struct mpi3mr_softc *sc) 2607 { 2608 U16 dev_handle_bitmap_sz; 2609 U8 *removepend_bitmap; 2610 2611 if (sc->facts.reply_sz > sc->reply_sz) { 2612 mpi3mr_dprint(sc, MPI3MR_ERROR, 2613 "Cannot increase reply size from %d to %d\n", 2614 sc->reply_sz, sc->reply_sz); 2615 return -EPERM; 2616 } 2617 2618 if (sc->num_io_throttle_group != sc->facts.max_io_throttle_group) { 2619 mpi3mr_dprint(sc, MPI3MR_ERROR, 2620 "max io throttle group doesn't match old(%d), new(%d)\n", 2621 sc->num_io_throttle_group, 2622 sc->facts.max_io_throttle_group); 2623 return -EPERM; 2624 } 2625 2626 if (sc->facts.max_op_reply_q < sc->num_queues) { 2627 mpi3mr_dprint(sc, MPI3MR_ERROR, 2628 "Cannot reduce number of operational reply queues from %d to %d\n", 2629 sc->num_queues, 2630 sc->facts.max_op_reply_q); 2631 return -EPERM; 2632 } 2633 2634 if (sc->facts.max_op_req_q < sc->num_queues) { 2635 mpi3mr_dprint(sc, MPI3MR_ERROR, 2636 "Cannot reduce number of operational request queues from %d to %d\n", 2637 sc->num_queues, sc->facts.max_op_req_q); 2638 return -EPERM; 2639 } 2640 2641 dev_handle_bitmap_sz = MPI3MR_DIV_ROUND_UP(sc->facts.max_devhandle, 8); 2642 2643 if (dev_handle_bitmap_sz > sc->dev_handle_bitmap_sz) { 2644 removepend_bitmap = realloc(sc->removepend_bitmap, 2645 dev_handle_bitmap_sz, M_MPI3MR, M_NOWAIT); 2646 2647 if (!removepend_bitmap) { 2648 mpi3mr_dprint(sc, MPI3MR_ERROR, 2649 "failed to increase removepend_bitmap sz from: %d to %d\n", 2650 sc->dev_handle_bitmap_sz, dev_handle_bitmap_sz); 2651 return -ENOMEM; 2652 } 2653 2654 memset(removepend_bitmap + sc->dev_handle_bitmap_sz, 0, 2655 dev_handle_bitmap_sz - sc->dev_handle_bitmap_sz); 2656 sc->removepend_bitmap = removepend_bitmap; 2657 mpi3mr_dprint(sc, MPI3MR_INFO, 2658 "increased dev_handle_bitmap_sz from %d to %d\n", 2659 sc->dev_handle_bitmap_sz, dev_handle_bitmap_sz); 2660 sc->dev_handle_bitmap_sz = dev_handle_bitmap_sz; 2661 } 2662 2663 return 0; 2664 } 2665 2666 /* 2667 * mpi3mr_initialize_ioc - Controller initialization 2668 * @dev: pointer to device struct 2669 * 2670 * This function allocates the controller wide resources and brings 2671 * the controller to operational state 2672 * 2673 * Return: 0 on success and proper error codes on failure 2674 */ 2675 int mpi3mr_initialize_ioc(struct mpi3mr_softc *sc, U8 init_type) 2676 { 2677 int retval = 0; 2678 enum mpi3mr_iocstate ioc_state; 2679 U64 ioc_info; 2680 U32 ioc_status, ioc_control, i, timeout; 2681 Mpi3IOCFactsData_t facts_data; 2682 char str[32]; 2683 U32 size; 2684 2685 sc->cpu_count = mp_ncpus; 2686 2687 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 2688 ioc_control = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 2689 ioc_info = mpi3mr_regread64(sc, MPI3_SYSIF_IOC_INFO_LOW_OFFSET); 2690 2691 mpi3mr_dprint(sc, MPI3MR_INFO, "SOD ioc_status: 0x%x ioc_control: 0x%x " 2692 "ioc_info: 0x%lx\n", ioc_status, ioc_control, ioc_info); 2693 2694 /*The timeout value is in 2sec unit, changing it to seconds*/ 2695 sc->ready_timeout = 2696 ((ioc_info & MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK) >> 2697 MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT) * 2; 2698 2699 ioc_state = mpi3mr_get_iocstate(sc); 2700 2701 mpi3mr_dprint(sc, MPI3MR_INFO, "IOC state: %s IOC ready timeout: %d\n", 2702 mpi3mr_iocstate_name(ioc_state), sc->ready_timeout); 2703 2704 if (ioc_state == MRIOC_STATE_BECOMING_READY || 2705 ioc_state == MRIOC_STATE_RESET_REQUESTED) { 2706 timeout = sc->ready_timeout * 10; 2707 do { 2708 DELAY(1000 * 100); 2709 } while (--timeout); 2710 2711 ioc_state = mpi3mr_get_iocstate(sc); 2712 mpi3mr_dprint(sc, MPI3MR_INFO, 2713 "IOC in %s state after waiting for reset time\n", 2714 mpi3mr_iocstate_name(ioc_state)); 2715 } 2716 2717 if (ioc_state == MRIOC_STATE_READY) { 2718 retval = mpi3mr_mur_ioc(sc, MPI3MR_RESET_FROM_BRINGUP); 2719 if (retval) { 2720 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to MU reset IOC, error 0x%x\n", 2721 retval); 2722 } 2723 ioc_state = mpi3mr_get_iocstate(sc); 2724 } 2725 2726 if (ioc_state != MRIOC_STATE_RESET) { 2727 mpi3mr_print_fault_info(sc); 2728 mpi3mr_dprint(sc, MPI3MR_ERROR, "issuing soft reset to bring to reset state\n"); 2729 retval = mpi3mr_issue_reset(sc, 2730 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, 2731 MPI3MR_RESET_FROM_BRINGUP); 2732 if (retval) { 2733 mpi3mr_dprint(sc, MPI3MR_ERROR, 2734 "%s :Failed to soft reset IOC, error 0x%d\n", 2735 __func__, retval); 2736 goto out_failed; 2737 } 2738 } 2739 2740 ioc_state = mpi3mr_get_iocstate(sc); 2741 2742 if (ioc_state != MRIOC_STATE_RESET) { 2743 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot bring IOC to reset state\n"); 2744 goto out_failed; 2745 } 2746 2747 retval = mpi3mr_setup_admin_qpair(sc); 2748 if (retval) { 2749 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to setup Admin queues, error 0x%x\n", 2750 retval); 2751 goto out_failed; 2752 } 2753 2754 retval = mpi3mr_bring_ioc_ready(sc); 2755 if (retval) { 2756 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to bring IOC ready, error 0x%x\n", 2757 retval); 2758 goto out_failed; 2759 } 2760 2761 if (init_type == MPI3MR_INIT_TYPE_INIT) { 2762 retval = mpi3mr_alloc_interrupts(sc, 1); 2763 if (retval) { 2764 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to allocate interrupts, error 0x%x\n", 2765 retval); 2766 goto out_failed; 2767 } 2768 2769 retval = mpi3mr_setup_irqs(sc); 2770 if (retval) { 2771 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to setup ISR, error 0x%x\n", 2772 retval); 2773 goto out_failed; 2774 } 2775 } 2776 2777 mpi3mr_enable_interrupts(sc); 2778 2779 if (init_type == MPI3MR_INIT_TYPE_INIT) { 2780 mtx_init(&sc->mpi3mr_mtx, "SIM lock", NULL, MTX_DEF); 2781 mtx_init(&sc->io_lock, "IO lock", NULL, MTX_DEF); 2782 mtx_init(&sc->admin_req_lock, "Admin Request Queue lock", NULL, MTX_SPIN); 2783 mtx_init(&sc->reply_free_q_lock, "Reply free Queue lock", NULL, MTX_SPIN); 2784 mtx_init(&sc->sense_buf_q_lock, "Sense buffer Queue lock", NULL, MTX_SPIN); 2785 mtx_init(&sc->chain_buf_lock, "Chain buffer lock", NULL, MTX_SPIN); 2786 mtx_init(&sc->cmd_pool_lock, "Command pool lock", NULL, MTX_DEF); 2787 // mtx_init(&sc->fwevt_lock, "Firmware Event lock", NULL, MTX_SPIN); 2788 mtx_init(&sc->fwevt_lock, "Firmware Event lock", NULL, MTX_DEF); 2789 mtx_init(&sc->target_lock, "Target lock", NULL, MTX_SPIN); 2790 mtx_init(&sc->reset_mutex, "Reset lock", NULL, MTX_DEF); 2791 2792 mtx_init(&sc->init_cmds.completion.lock, "Init commands lock", NULL, MTX_DEF); 2793 sc->init_cmds.reply = NULL; 2794 sc->init_cmds.state = MPI3MR_CMD_NOTUSED; 2795 sc->init_cmds.dev_handle = MPI3MR_INVALID_DEV_HANDLE; 2796 sc->init_cmds.host_tag = MPI3MR_HOSTTAG_INITCMDS; 2797 2798 mtx_init(&sc->ioctl_cmds.completion.lock, "IOCTL commands lock", NULL, MTX_DEF); 2799 sc->ioctl_cmds.reply = NULL; 2800 sc->ioctl_cmds.state = MPI3MR_CMD_NOTUSED; 2801 sc->ioctl_cmds.dev_handle = MPI3MR_INVALID_DEV_HANDLE; 2802 sc->ioctl_cmds.host_tag = MPI3MR_HOSTTAG_IOCTLCMDS; 2803 2804 mtx_init(&sc->pel_abort_cmd.completion.lock, "PEL Abort command lock", NULL, MTX_DEF); 2805 sc->pel_abort_cmd.reply = NULL; 2806 sc->pel_abort_cmd.state = MPI3MR_CMD_NOTUSED; 2807 sc->pel_abort_cmd.dev_handle = MPI3MR_INVALID_DEV_HANDLE; 2808 sc->pel_abort_cmd.host_tag = MPI3MR_HOSTTAG_PELABORT; 2809 2810 mtx_init(&sc->host_tm_cmds.completion.lock, "TM commands lock", NULL, MTX_DEF); 2811 sc->host_tm_cmds.reply = NULL; 2812 sc->host_tm_cmds.state = MPI3MR_CMD_NOTUSED; 2813 sc->host_tm_cmds.dev_handle = MPI3MR_INVALID_DEV_HANDLE; 2814 sc->host_tm_cmds.host_tag = MPI3MR_HOSTTAG_TMS; 2815 2816 TAILQ_INIT(&sc->cmd_list_head); 2817 TAILQ_INIT(&sc->event_list); 2818 TAILQ_INIT(&sc->delayed_rmhs_list); 2819 TAILQ_INIT(&sc->delayed_evtack_cmds_list); 2820 2821 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 2822 snprintf(str, 32, "Dev REMHS commands lock[%d]", i); 2823 mtx_init(&sc->dev_rmhs_cmds[i].completion.lock, str, NULL, MTX_DEF); 2824 sc->dev_rmhs_cmds[i].reply = NULL; 2825 sc->dev_rmhs_cmds[i].state = MPI3MR_CMD_NOTUSED; 2826 sc->dev_rmhs_cmds[i].dev_handle = MPI3MR_INVALID_DEV_HANDLE; 2827 sc->dev_rmhs_cmds[i].host_tag = MPI3MR_HOSTTAG_DEVRMCMD_MIN 2828 + i; 2829 } 2830 } 2831 2832 retval = mpi3mr_issue_iocfacts(sc, &facts_data); 2833 if (retval) { 2834 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to Issue IOC Facts, retval: 0x%x\n", 2835 retval); 2836 goto out_failed; 2837 } 2838 2839 retval = mpi3mr_process_factsdata(sc, &facts_data); 2840 if (retval) { 2841 mpi3mr_dprint(sc, MPI3MR_ERROR, "IOC Facts data processing failedi, retval: 0x%x\n", 2842 retval); 2843 goto out_failed; 2844 } 2845 2846 sc->num_io_throttle_group = sc->facts.max_io_throttle_group; 2847 mpi3mr_atomic_set(&sc->pend_large_data_sz, 0); 2848 2849 if (init_type == MPI3MR_INIT_TYPE_RESET) { 2850 retval = mpi3mr_validate_fw_update(sc); 2851 if (retval) 2852 goto out_failed; 2853 } else { 2854 sc->reply_sz = sc->facts.reply_sz; 2855 } 2856 2857 2858 mpi3mr_display_ioc_info(sc); 2859 2860 retval = mpi3mr_reply_alloc(sc); 2861 if (retval) { 2862 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to allocated reply and sense buffers, retval: 0x%x\n", 2863 retval); 2864 goto out_failed; 2865 } 2866 2867 if (init_type == MPI3MR_INIT_TYPE_INIT) { 2868 retval = mpi3mr_alloc_chain_bufs(sc); 2869 if (retval) { 2870 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to allocated chain buffers, retval: 0x%x\n", 2871 retval); 2872 goto out_failed; 2873 } 2874 } 2875 2876 retval = mpi3mr_issue_iocinit(sc); 2877 if (retval) { 2878 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to Issue IOC Init, retval: 0x%x\n", 2879 retval); 2880 goto out_failed; 2881 } 2882 2883 mpi3mr_print_fw_pkg_ver(sc); 2884 2885 sc->reply_free_q_host_index = sc->num_reply_bufs; 2886 mpi3mr_regwrite(sc, MPI3_SYSIF_REPLY_FREE_HOST_INDEX_OFFSET, 2887 sc->reply_free_q_host_index); 2888 2889 sc->sense_buf_q_host_index = sc->num_sense_bufs; 2890 2891 mpi3mr_regwrite(sc, MPI3_SYSIF_SENSE_BUF_FREE_HOST_INDEX_OFFSET, 2892 sc->sense_buf_q_host_index); 2893 2894 if (init_type == MPI3MR_INIT_TYPE_INIT) { 2895 retval = mpi3mr_alloc_interrupts(sc, 0); 2896 if (retval) { 2897 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to allocate interrupts, retval: 0x%x\n", 2898 retval); 2899 goto out_failed; 2900 } 2901 2902 retval = mpi3mr_setup_irqs(sc); 2903 if (retval) { 2904 printf(IOCNAME "Failed to setup ISR, error: 0x%x\n", 2905 sc->name, retval); 2906 goto out_failed; 2907 } 2908 2909 mpi3mr_enable_interrupts(sc); 2910 2911 } else 2912 mpi3mr_enable_interrupts(sc); 2913 2914 retval = mpi3mr_create_op_queues(sc); 2915 2916 if (retval) { 2917 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to create operational queues, error: %d\n", 2918 retval); 2919 goto out_failed; 2920 } 2921 2922 if (!sc->throttle_groups && sc->num_io_throttle_group) { 2923 mpi3mr_dprint(sc, MPI3MR_ERROR, "allocating memory for throttle groups\n"); 2924 size = sizeof(struct mpi3mr_throttle_group_info); 2925 sc->throttle_groups = (struct mpi3mr_throttle_group_info *) 2926 malloc(sc->num_io_throttle_group * 2927 size, M_MPI3MR, M_NOWAIT | M_ZERO); 2928 if (!sc->throttle_groups) 2929 goto out_failed; 2930 } 2931 2932 if (init_type == MPI3MR_INIT_TYPE_RESET) { 2933 mpi3mr_dprint(sc, MPI3MR_INFO, "Re-register events\n"); 2934 retval = mpi3mr_register_events(sc); 2935 if (retval) { 2936 mpi3mr_dprint(sc, MPI3MR_INFO, "Failed to re-register events, retval: 0x%x\n", 2937 retval); 2938 goto out_failed; 2939 } 2940 2941 mpi3mr_dprint(sc, MPI3MR_INFO, "Issuing Port Enable\n"); 2942 retval = mpi3mr_issue_port_enable(sc, 0); 2943 if (retval) { 2944 mpi3mr_dprint(sc, MPI3MR_INFO, "Failed to issue port enable, retval: 0x%x\n", 2945 retval); 2946 goto out_failed; 2947 } 2948 } 2949 retval = mpi3mr_pel_alloc(sc); 2950 if (retval) { 2951 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to allocate memory for PEL, retval: 0x%x\n", 2952 retval); 2953 goto out_failed; 2954 } 2955 2956 return retval; 2957 2958 out_failed: 2959 retval = -1; 2960 return retval; 2961 } 2962 2963 static void mpi3mr_port_enable_complete(struct mpi3mr_softc *sc, 2964 struct mpi3mr_drvr_cmd *drvrcmd) 2965 { 2966 drvrcmd->state = MPI3MR_CMD_NOTUSED; 2967 drvrcmd->callback = NULL; 2968 printf(IOCNAME "Completing Port Enable Request\n", sc->name); 2969 sc->mpi3mr_flags |= MPI3MR_FLAGS_PORT_ENABLE_DONE; 2970 mpi3mr_startup_decrement(sc->cam_sc); 2971 } 2972 2973 int mpi3mr_issue_port_enable(struct mpi3mr_softc *sc, U8 async) 2974 { 2975 Mpi3PortEnableRequest_t pe_req; 2976 int retval = 0; 2977 2978 memset(&pe_req, 0, sizeof(pe_req)); 2979 mtx_lock(&sc->init_cmds.completion.lock); 2980 if (sc->init_cmds.state & MPI3MR_CMD_PENDING) { 2981 retval = -1; 2982 printf(IOCNAME "Issue PortEnable: Init command is in use\n", sc->name); 2983 mtx_unlock(&sc->init_cmds.completion.lock); 2984 goto out; 2985 } 2986 2987 sc->init_cmds.state = MPI3MR_CMD_PENDING; 2988 2989 if (async) { 2990 sc->init_cmds.is_waiting = 0; 2991 sc->init_cmds.callback = mpi3mr_port_enable_complete; 2992 } else { 2993 sc->init_cmds.is_waiting = 1; 2994 sc->init_cmds.callback = NULL; 2995 init_completion(&sc->init_cmds.completion); 2996 } 2997 pe_req.HostTag = MPI3MR_HOSTTAG_INITCMDS; 2998 pe_req.Function = MPI3_FUNCTION_PORT_ENABLE; 2999 3000 printf(IOCNAME "Sending Port Enable Request\n", sc->name); 3001 retval = mpi3mr_submit_admin_cmd(sc, &pe_req, sizeof(pe_req)); 3002 if (retval) { 3003 printf(IOCNAME "Issue PortEnable: Admin Post failed\n", 3004 sc->name); 3005 goto out_unlock; 3006 } 3007 3008 if (!async) { 3009 wait_for_completion_timeout(&sc->init_cmds.completion, 3010 MPI3MR_PORTENABLE_TIMEOUT); 3011 if (!(sc->init_cmds.state & MPI3MR_CMD_COMPLETE)) { 3012 printf(IOCNAME "Issue PortEnable: command timed out\n", 3013 sc->name); 3014 retval = -1; 3015 mpi3mr_check_rh_fault_ioc(sc, MPI3MR_RESET_FROM_PE_TIMEOUT); 3016 goto out_unlock; 3017 } 3018 mpi3mr_port_enable_complete(sc, &sc->init_cmds); 3019 } 3020 out_unlock: 3021 mtx_unlock(&sc->init_cmds.completion.lock); 3022 3023 out: 3024 return retval; 3025 } 3026 3027 void 3028 mpi3mr_watchdog_thread(void *arg) 3029 { 3030 struct mpi3mr_softc *sc; 3031 enum mpi3mr_iocstate ioc_state; 3032 U32 fault, host_diagnostic, ioc_status; 3033 3034 sc = (struct mpi3mr_softc *)arg; 3035 3036 mpi3mr_dprint(sc, MPI3MR_XINFO, "%s\n", __func__); 3037 3038 sc->watchdog_thread_active = 1; 3039 mtx_lock(&sc->reset_mutex); 3040 for (;;) { 3041 /* Sleep for 1 second and check the queue status */ 3042 msleep(&sc->watchdog_chan, &sc->reset_mutex, PRIBIO, 3043 "mpi3mr_watchdog", 1 * hz); 3044 if (sc->mpi3mr_flags & MPI3MR_FLAGS_SHUTDOWN || 3045 (sc->unrecoverable == 1)) { 3046 mpi3mr_dprint(sc, MPI3MR_INFO, 3047 "Exit due to %s from %s\n", 3048 sc->mpi3mr_flags & MPI3MR_FLAGS_SHUTDOWN ? "Shutdown" : 3049 "Hardware critical error", __func__); 3050 break; 3051 } 3052 3053 if ((sc->prepare_for_reset) && 3054 ((sc->prepare_for_reset_timeout_counter++) >= 3055 MPI3MR_PREPARE_FOR_RESET_TIMEOUT)) { 3056 mpi3mr_soft_reset_handler(sc, 3057 MPI3MR_RESET_FROM_CIACTVRST_TIMER, 1); 3058 continue; 3059 } 3060 3061 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 3062 3063 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) { 3064 mpi3mr_soft_reset_handler(sc, MPI3MR_RESET_FROM_FIRMWARE, 0); 3065 continue; 3066 } 3067 3068 ioc_state = mpi3mr_get_iocstate(sc); 3069 if (ioc_state == MRIOC_STATE_FAULT) { 3070 fault = mpi3mr_regread(sc, MPI3_SYSIF_FAULT_OFFSET) & 3071 MPI3_SYSIF_FAULT_CODE_MASK; 3072 3073 host_diagnostic = mpi3mr_regread(sc, MPI3_SYSIF_HOST_DIAG_OFFSET); 3074 if (host_diagnostic & MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS) { 3075 if (!sc->diagsave_timeout) { 3076 mpi3mr_print_fault_info(sc); 3077 mpi3mr_dprint(sc, MPI3MR_INFO, 3078 "diag save in progress\n"); 3079 } 3080 if ((sc->diagsave_timeout++) <= MPI3_SYSIF_DIAG_SAVE_TIMEOUT) 3081 continue; 3082 } 3083 mpi3mr_print_fault_info(sc); 3084 sc->diagsave_timeout = 0; 3085 3086 if ((fault == MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED) || 3087 (fault == MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED)) { 3088 mpi3mr_dprint(sc, MPI3MR_INFO, 3089 "Controller requires system power cycle or complete reset is needed," 3090 "fault code: 0x%x. marking controller as unrecoverable\n", fault); 3091 sc->unrecoverable = 1; 3092 goto out; 3093 } 3094 if ((fault == MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET) 3095 || (fault == MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS) 3096 || (sc->reset_in_progress)) 3097 goto out; 3098 if (fault == MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET) 3099 mpi3mr_soft_reset_handler(sc, 3100 MPI3MR_RESET_FROM_CIACTIV_FAULT, 0); 3101 else 3102 mpi3mr_soft_reset_handler(sc, 3103 MPI3MR_RESET_FROM_FAULT_WATCH, 0); 3104 3105 } 3106 3107 if (sc->reset.type == MPI3MR_TRIGGER_SOFT_RESET) { 3108 mpi3mr_print_fault_info(sc); 3109 mpi3mr_soft_reset_handler(sc, sc->reset.reason, 1); 3110 } 3111 } 3112 out: 3113 mtx_unlock(&sc->reset_mutex); 3114 sc->watchdog_thread_active = 0; 3115 mpi3mr_kproc_exit(0); 3116 } 3117 3118 static void mpi3mr_display_event_data(struct mpi3mr_softc *sc, 3119 Mpi3EventNotificationReply_t *event_rep) 3120 { 3121 char *desc = NULL; 3122 U16 event; 3123 3124 event = event_rep->Event; 3125 3126 switch (event) { 3127 case MPI3_EVENT_LOG_DATA: 3128 desc = "Log Data"; 3129 break; 3130 case MPI3_EVENT_CHANGE: 3131 desc = "Event Change"; 3132 break; 3133 case MPI3_EVENT_GPIO_INTERRUPT: 3134 desc = "GPIO Interrupt"; 3135 break; 3136 case MPI3_EVENT_CABLE_MGMT: 3137 desc = "Cable Management"; 3138 break; 3139 case MPI3_EVENT_ENERGY_PACK_CHANGE: 3140 desc = "Energy Pack Change"; 3141 break; 3142 case MPI3_EVENT_DEVICE_ADDED: 3143 { 3144 Mpi3DevicePage0_t *event_data = 3145 (Mpi3DevicePage0_t *)event_rep->EventData; 3146 mpi3mr_dprint(sc, MPI3MR_EVENT, "Device Added: Dev=0x%04x Form=0x%x Perst id: 0x%x\n", 3147 event_data->DevHandle, event_data->DeviceForm, event_data->PersistentID); 3148 return; 3149 } 3150 case MPI3_EVENT_DEVICE_INFO_CHANGED: 3151 { 3152 Mpi3DevicePage0_t *event_data = 3153 (Mpi3DevicePage0_t *)event_rep->EventData; 3154 mpi3mr_dprint(sc, MPI3MR_EVENT, "Device Info Changed: Dev=0x%04x Form=0x%x\n", 3155 event_data->DevHandle, event_data->DeviceForm); 3156 return; 3157 } 3158 case MPI3_EVENT_DEVICE_STATUS_CHANGE: 3159 { 3160 Mpi3EventDataDeviceStatusChange_t *event_data = 3161 (Mpi3EventDataDeviceStatusChange_t *)event_rep->EventData; 3162 mpi3mr_dprint(sc, MPI3MR_EVENT, "Device Status Change: Dev=0x%04x RC=0x%x\n", 3163 event_data->DevHandle, event_data->ReasonCode); 3164 return; 3165 } 3166 case MPI3_EVENT_SAS_DISCOVERY: 3167 { 3168 Mpi3EventDataSasDiscovery_t *event_data = 3169 (Mpi3EventDataSasDiscovery_t *)event_rep->EventData; 3170 mpi3mr_dprint(sc, MPI3MR_EVENT, "SAS Discovery: (%s)", 3171 (event_data->ReasonCode == MPI3_EVENT_SAS_DISC_RC_STARTED) ? 3172 "start" : "stop"); 3173 if (event_data->DiscoveryStatus && 3174 (sc->mpi3mr_debug & MPI3MR_EVENT)) { 3175 printf("discovery_status(0x%08x)", 3176 event_data->DiscoveryStatus); 3177 3178 } 3179 3180 if (sc->mpi3mr_debug & MPI3MR_EVENT) 3181 printf("\n"); 3182 return; 3183 } 3184 case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE: 3185 desc = "SAS Broadcast Primitive"; 3186 break; 3187 case MPI3_EVENT_SAS_NOTIFY_PRIMITIVE: 3188 desc = "SAS Notify Primitive"; 3189 break; 3190 case MPI3_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE: 3191 desc = "SAS Init Device Status Change"; 3192 break; 3193 case MPI3_EVENT_SAS_INIT_TABLE_OVERFLOW: 3194 desc = "SAS Init Table Overflow"; 3195 break; 3196 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 3197 desc = "SAS Topology Change List"; 3198 break; 3199 case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE: 3200 desc = "Enclosure Device Status Change"; 3201 break; 3202 case MPI3_EVENT_HARD_RESET_RECEIVED: 3203 desc = "Hard Reset Received"; 3204 break; 3205 case MPI3_EVENT_SAS_PHY_COUNTER: 3206 desc = "SAS PHY Counter"; 3207 break; 3208 case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR: 3209 desc = "SAS Device Discovery Error"; 3210 break; 3211 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST: 3212 desc = "PCIE Topology Change List"; 3213 break; 3214 case MPI3_EVENT_PCIE_ENUMERATION: 3215 { 3216 Mpi3EventDataPcieEnumeration_t *event_data = 3217 (Mpi3EventDataPcieEnumeration_t *)event_rep->EventData; 3218 mpi3mr_dprint(sc, MPI3MR_EVENT, "PCIE Enumeration: (%s)", 3219 (event_data->ReasonCode == 3220 MPI3_EVENT_PCIE_ENUM_RC_STARTED) ? "start" : 3221 "stop"); 3222 if (event_data->EnumerationStatus) 3223 mpi3mr_dprint(sc, MPI3MR_EVENT, "enumeration_status(0x%08x)", 3224 event_data->EnumerationStatus); 3225 if (sc->mpi3mr_debug & MPI3MR_EVENT) 3226 printf("\n"); 3227 return; 3228 } 3229 case MPI3_EVENT_PREPARE_FOR_RESET: 3230 desc = "Prepare For Reset"; 3231 break; 3232 } 3233 3234 if (!desc) 3235 return; 3236 3237 mpi3mr_dprint(sc, MPI3MR_EVENT, "%s\n", desc); 3238 } 3239 3240 struct mpi3mr_target * 3241 mpi3mr_find_target_by_per_id(struct mpi3mr_cam_softc *cam_sc, 3242 uint16_t per_id) 3243 { 3244 struct mpi3mr_target *target = NULL; 3245 3246 mtx_lock_spin(&cam_sc->sc->target_lock); 3247 TAILQ_FOREACH(target, &cam_sc->tgt_list, tgt_next) { 3248 if (target->per_id == per_id) 3249 break; 3250 } 3251 3252 mtx_unlock_spin(&cam_sc->sc->target_lock); 3253 return target; 3254 } 3255 3256 struct mpi3mr_target * 3257 mpi3mr_find_target_by_dev_handle(struct mpi3mr_cam_softc *cam_sc, 3258 uint16_t handle) 3259 { 3260 struct mpi3mr_target *target = NULL; 3261 3262 mtx_lock_spin(&cam_sc->sc->target_lock); 3263 TAILQ_FOREACH(target, &cam_sc->tgt_list, tgt_next) { 3264 if (target->dev_handle == handle) 3265 break; 3266 3267 } 3268 mtx_unlock_spin(&cam_sc->sc->target_lock); 3269 return target; 3270 } 3271 3272 void mpi3mr_update_device(struct mpi3mr_softc *sc, 3273 struct mpi3mr_target *tgtdev, Mpi3DevicePage0_t *dev_pg0, 3274 bool is_added) 3275 { 3276 U16 flags = 0; 3277 3278 tgtdev->per_id = (dev_pg0->PersistentID); 3279 tgtdev->dev_handle = (dev_pg0->DevHandle); 3280 tgtdev->dev_type = dev_pg0->DeviceForm; 3281 tgtdev->encl_handle = (dev_pg0->EnclosureHandle); 3282 tgtdev->parent_handle = (dev_pg0->ParentDevHandle); 3283 tgtdev->slot = (dev_pg0->Slot); 3284 tgtdev->qdepth = (dev_pg0->QueueDepth); 3285 tgtdev->wwid = (dev_pg0->WWID); 3286 3287 flags = (dev_pg0->Flags); 3288 tgtdev->is_hidden = (flags & MPI3_DEVICE0_FLAGS_HIDDEN); 3289 if (is_added == true) 3290 tgtdev->io_throttle_enabled = 3291 (flags & MPI3_DEVICE0_FLAGS_IO_THROTTLING_REQUIRED) ? 1 : 0; 3292 3293 switch (dev_pg0->AccessStatus) { 3294 case MPI3_DEVICE0_ASTATUS_NO_ERRORS: 3295 case MPI3_DEVICE0_ASTATUS_PREPARE: 3296 case MPI3_DEVICE0_ASTATUS_NEEDS_INITIALIZATION: 3297 case MPI3_DEVICE0_ASTATUS_DEVICE_MISSING_DELAY: 3298 break; 3299 default: 3300 tgtdev->is_hidden = 1; 3301 break; 3302 } 3303 3304 switch (tgtdev->dev_type) { 3305 case MPI3_DEVICE_DEVFORM_SAS_SATA: 3306 { 3307 Mpi3Device0SasSataFormat_t *sasinf = 3308 &dev_pg0->DeviceSpecific.SasSataFormat; 3309 U16 dev_info = (sasinf->DeviceInfo); 3310 tgtdev->dev_spec.sassata_inf.dev_info = dev_info; 3311 tgtdev->dev_spec.sassata_inf.sas_address = 3312 (sasinf->SASAddress); 3313 if ((dev_info & MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_MASK) != 3314 MPI3_SAS_DEVICE_INFO_DEVICE_TYPE_END_DEVICE) 3315 tgtdev->is_hidden = 1; 3316 else if (!(dev_info & (MPI3_SAS_DEVICE_INFO_STP_SATA_TARGET | 3317 MPI3_SAS_DEVICE_INFO_SSP_TARGET))) 3318 tgtdev->is_hidden = 1; 3319 break; 3320 } 3321 case MPI3_DEVICE_DEVFORM_PCIE: 3322 { 3323 Mpi3Device0PcieFormat_t *pcieinf = 3324 &dev_pg0->DeviceSpecific.PcieFormat; 3325 U16 dev_info = (pcieinf->DeviceInfo); 3326 3327 tgtdev->q_depth = dev_pg0->QueueDepth; 3328 tgtdev->dev_spec.pcie_inf.dev_info = dev_info; 3329 tgtdev->dev_spec.pcie_inf.capb = 3330 (pcieinf->Capabilities); 3331 tgtdev->dev_spec.pcie_inf.mdts = MPI3MR_DEFAULT_MDTS; 3332 if (dev_pg0->AccessStatus == MPI3_DEVICE0_ASTATUS_NO_ERRORS) { 3333 tgtdev->dev_spec.pcie_inf.mdts = 3334 (pcieinf->MaximumDataTransferSize); 3335 tgtdev->dev_spec.pcie_inf.pgsz = pcieinf->PageSize; 3336 tgtdev->dev_spec.pcie_inf.reset_to = 3337 pcieinf->ControllerResetTO; 3338 tgtdev->dev_spec.pcie_inf.abort_to = 3339 pcieinf->NVMeAbortTO; 3340 } 3341 if (tgtdev->dev_spec.pcie_inf.mdts > (1024 * 1024)) 3342 tgtdev->dev_spec.pcie_inf.mdts = (1024 * 1024); 3343 3344 if (((dev_info & MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK) != 3345 MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE) && 3346 ((dev_info & MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK) != 3347 MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SCSI_DEVICE)) 3348 tgtdev->is_hidden = 1; 3349 3350 break; 3351 } 3352 case MPI3_DEVICE_DEVFORM_VD: 3353 { 3354 Mpi3Device0VdFormat_t *vdinf = 3355 &dev_pg0->DeviceSpecific.VdFormat; 3356 struct mpi3mr_throttle_group_info *tg = NULL; 3357 3358 tgtdev->dev_spec.vol_inf.state = vdinf->VdState; 3359 if (vdinf->VdState == MPI3_DEVICE0_VD_STATE_OFFLINE) 3360 tgtdev->is_hidden = 1; 3361 tgtdev->dev_spec.vol_inf.tg_id = vdinf->IOThrottleGroup; 3362 tgtdev->dev_spec.vol_inf.tg_high = 3363 vdinf->IOThrottleGroupHigh * 2048; 3364 tgtdev->dev_spec.vol_inf.tg_low = 3365 vdinf->IOThrottleGroupLow * 2048; 3366 if (vdinf->IOThrottleGroup < sc->num_io_throttle_group) { 3367 tg = sc->throttle_groups + vdinf->IOThrottleGroup; 3368 tg->id = vdinf->IOThrottleGroup; 3369 tg->high = tgtdev->dev_spec.vol_inf.tg_high; 3370 tg->low = tgtdev->dev_spec.vol_inf.tg_low; 3371 if (is_added == true) 3372 tg->fw_qd = tgtdev->q_depth; 3373 tg->modified_qd = tgtdev->q_depth; 3374 } 3375 tgtdev->dev_spec.vol_inf.tg = tg; 3376 tgtdev->throttle_group = tg; 3377 break; 3378 } 3379 default: 3380 goto out; 3381 } 3382 3383 out: 3384 return; 3385 } 3386 3387 int mpi3mr_create_device(struct mpi3mr_softc *sc, 3388 Mpi3DevicePage0_t *dev_pg0) 3389 { 3390 int retval = 0; 3391 struct mpi3mr_target *target = NULL; 3392 U16 per_id = 0; 3393 3394 per_id = dev_pg0->PersistentID; 3395 3396 mtx_lock_spin(&sc->target_lock); 3397 TAILQ_FOREACH(target, &sc->cam_sc->tgt_list, tgt_next) { 3398 if (target->per_id == per_id) { 3399 target->state = MPI3MR_DEV_CREATED; 3400 break; 3401 } 3402 } 3403 mtx_unlock_spin(&sc->target_lock); 3404 3405 if (target) { 3406 mpi3mr_update_device(sc, target, dev_pg0, true); 3407 } else { 3408 target = malloc(sizeof(*target), M_MPI3MR, 3409 M_NOWAIT | M_ZERO); 3410 3411 if (target == NULL) { 3412 retval = -1; 3413 goto out; 3414 } 3415 3416 target->exposed_to_os = 0; 3417 mpi3mr_update_device(sc, target, dev_pg0, true); 3418 mtx_lock_spin(&sc->target_lock); 3419 TAILQ_INSERT_TAIL(&sc->cam_sc->tgt_list, target, tgt_next); 3420 target->state = MPI3MR_DEV_CREATED; 3421 mtx_unlock_spin(&sc->target_lock); 3422 } 3423 out: 3424 return retval; 3425 } 3426 3427 /** 3428 * mpi3mr_dev_rmhs_complete_iou - Device removal IOUC completion 3429 * @sc: Adapter instance reference 3430 * @drv_cmd: Internal command tracker 3431 * 3432 * Issues a target reset TM to the firmware from the device 3433 * removal TM pend list or retry the removal handshake sequence 3434 * based on the IOU control request IOC status. 3435 * 3436 * Return: Nothing 3437 */ 3438 static void mpi3mr_dev_rmhs_complete_iou(struct mpi3mr_softc *sc, 3439 struct mpi3mr_drvr_cmd *drv_cmd) 3440 { 3441 U16 cmd_idx = drv_cmd->host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN; 3442 struct delayed_dev_rmhs_node *delayed_dev_rmhs = NULL; 3443 3444 mpi3mr_dprint(sc, MPI3MR_EVENT, 3445 "%s :dev_rmhs_iouctrl_complete:handle(0x%04x), ioc_status(0x%04x), loginfo(0x%08x)\n", 3446 __func__, drv_cmd->dev_handle, drv_cmd->ioc_status, 3447 drv_cmd->ioc_loginfo); 3448 if (drv_cmd->ioc_status != MPI3_IOCSTATUS_SUCCESS) { 3449 if (drv_cmd->retry_count < MPI3MR_DEVRMHS_RETRYCOUNT) { 3450 drv_cmd->retry_count++; 3451 mpi3mr_dprint(sc, MPI3MR_EVENT, 3452 "%s :dev_rmhs_iouctrl_complete: handle(0x%04x)retrying handshake retry=%d\n", 3453 __func__, drv_cmd->dev_handle, 3454 drv_cmd->retry_count); 3455 mpi3mr_dev_rmhs_send_tm(sc, drv_cmd->dev_handle, 3456 drv_cmd, drv_cmd->iou_rc); 3457 return; 3458 } 3459 mpi3mr_dprint(sc, MPI3MR_ERROR, 3460 "%s :dev removal handshake failed after all retries: handle(0x%04x)\n", 3461 __func__, drv_cmd->dev_handle); 3462 } else { 3463 mpi3mr_dprint(sc, MPI3MR_INFO, 3464 "%s :dev removal handshake completed successfully: handle(0x%04x)\n", 3465 __func__, drv_cmd->dev_handle); 3466 mpi3mr_clear_bit(drv_cmd->dev_handle, sc->removepend_bitmap); 3467 } 3468 3469 if (!TAILQ_EMPTY(&sc->delayed_rmhs_list)) { 3470 delayed_dev_rmhs = TAILQ_FIRST(&sc->delayed_rmhs_list); 3471 drv_cmd->dev_handle = delayed_dev_rmhs->handle; 3472 drv_cmd->retry_count = 0; 3473 drv_cmd->iou_rc = delayed_dev_rmhs->iou_rc; 3474 mpi3mr_dprint(sc, MPI3MR_EVENT, 3475 "%s :dev_rmhs_iouctrl_complete: processing delayed TM: handle(0x%04x)\n", 3476 __func__, drv_cmd->dev_handle); 3477 mpi3mr_dev_rmhs_send_tm(sc, drv_cmd->dev_handle, drv_cmd, 3478 drv_cmd->iou_rc); 3479 TAILQ_REMOVE(&sc->delayed_rmhs_list, delayed_dev_rmhs, list); 3480 free(delayed_dev_rmhs, M_MPI3MR); 3481 return; 3482 } 3483 drv_cmd->state = MPI3MR_CMD_NOTUSED; 3484 drv_cmd->callback = NULL; 3485 drv_cmd->retry_count = 0; 3486 drv_cmd->dev_handle = MPI3MR_INVALID_DEV_HANDLE; 3487 mpi3mr_clear_bit(cmd_idx, sc->devrem_bitmap); 3488 } 3489 3490 /** 3491 * mpi3mr_dev_rmhs_complete_tm - Device removal TM completion 3492 * @sc: Adapter instance reference 3493 * @drv_cmd: Internal command tracker 3494 * 3495 * Issues a target reset TM to the firmware from the device 3496 * removal TM pend list or issue IO Unit control request as 3497 * part of device removal or hidden acknowledgment handshake. 3498 * 3499 * Return: Nothing 3500 */ 3501 static void mpi3mr_dev_rmhs_complete_tm(struct mpi3mr_softc *sc, 3502 struct mpi3mr_drvr_cmd *drv_cmd) 3503 { 3504 Mpi3IoUnitControlRequest_t iou_ctrl; 3505 U16 cmd_idx = drv_cmd->host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN; 3506 Mpi3SCSITaskMgmtReply_t *tm_reply = NULL; 3507 int retval; 3508 3509 if (drv_cmd->state & MPI3MR_CMD_REPLYVALID) 3510 tm_reply = (Mpi3SCSITaskMgmtReply_t *)drv_cmd->reply; 3511 3512 if (tm_reply) 3513 printf(IOCNAME 3514 "dev_rmhs_tr_complete:handle(0x%04x), ioc_status(0x%04x), loginfo(0x%08x), term_count(%d)\n", 3515 sc->name, drv_cmd->dev_handle, drv_cmd->ioc_status, 3516 drv_cmd->ioc_loginfo, 3517 le32toh(tm_reply->TerminationCount)); 3518 3519 printf(IOCNAME "Issuing IOU CTL: handle(0x%04x) dev_rmhs idx(%d)\n", 3520 sc->name, drv_cmd->dev_handle, cmd_idx); 3521 3522 memset(&iou_ctrl, 0, sizeof(iou_ctrl)); 3523 3524 drv_cmd->state = MPI3MR_CMD_PENDING; 3525 drv_cmd->is_waiting = 0; 3526 drv_cmd->callback = mpi3mr_dev_rmhs_complete_iou; 3527 iou_ctrl.Operation = drv_cmd->iou_rc; 3528 iou_ctrl.Param16[0] = htole16(drv_cmd->dev_handle); 3529 iou_ctrl.HostTag = htole16(drv_cmd->host_tag); 3530 iou_ctrl.Function = MPI3_FUNCTION_IO_UNIT_CONTROL; 3531 3532 retval = mpi3mr_submit_admin_cmd(sc, &iou_ctrl, sizeof(iou_ctrl)); 3533 if (retval) { 3534 printf(IOCNAME "Issue DevRmHsTMIOUCTL: Admin post failed\n", 3535 sc->name); 3536 goto out_failed; 3537 } 3538 3539 return; 3540 out_failed: 3541 drv_cmd->state = MPI3MR_CMD_NOTUSED; 3542 drv_cmd->callback = NULL; 3543 drv_cmd->dev_handle = MPI3MR_INVALID_DEV_HANDLE; 3544 drv_cmd->retry_count = 0; 3545 mpi3mr_clear_bit(cmd_idx, sc->devrem_bitmap); 3546 } 3547 3548 /** 3549 * mpi3mr_dev_rmhs_send_tm - Issue TM for device removal 3550 * @sc: Adapter instance reference 3551 * @handle: Device handle 3552 * @cmdparam: Internal command tracker 3553 * @iou_rc: IO Unit reason code 3554 * 3555 * Issues a target reset TM to the firmware or add it to a pend 3556 * list as part of device removal or hidden acknowledgment 3557 * handshake. 3558 * 3559 * Return: Nothing 3560 */ 3561 static void mpi3mr_dev_rmhs_send_tm(struct mpi3mr_softc *sc, U16 handle, 3562 struct mpi3mr_drvr_cmd *cmdparam, U8 iou_rc) 3563 { 3564 Mpi3SCSITaskMgmtRequest_t tm_req; 3565 int retval = 0; 3566 U16 cmd_idx = MPI3MR_NUM_DEVRMCMD; 3567 U8 retrycount = 5; 3568 struct mpi3mr_drvr_cmd *drv_cmd = cmdparam; 3569 struct delayed_dev_rmhs_node *delayed_dev_rmhs = NULL; 3570 struct mpi3mr_target *tgtdev = NULL; 3571 3572 mtx_lock_spin(&sc->target_lock); 3573 TAILQ_FOREACH(tgtdev, &sc->cam_sc->tgt_list, tgt_next) { 3574 if ((tgtdev->dev_handle == handle) && 3575 (iou_rc == MPI3_CTRL_OP_REMOVE_DEVICE)) { 3576 tgtdev->state = MPI3MR_DEV_REMOVE_HS_STARTED; 3577 break; 3578 } 3579 } 3580 mtx_unlock_spin(&sc->target_lock); 3581 3582 if (drv_cmd) 3583 goto issue_cmd; 3584 do { 3585 cmd_idx = mpi3mr_find_first_zero_bit(sc->devrem_bitmap, 3586 MPI3MR_NUM_DEVRMCMD); 3587 if (cmd_idx < MPI3MR_NUM_DEVRMCMD) { 3588 if (!mpi3mr_test_and_set_bit(cmd_idx, sc->devrem_bitmap)) 3589 break; 3590 cmd_idx = MPI3MR_NUM_DEVRMCMD; 3591 } 3592 } while (retrycount--); 3593 3594 if (cmd_idx >= MPI3MR_NUM_DEVRMCMD) { 3595 delayed_dev_rmhs = malloc(sizeof(*delayed_dev_rmhs),M_MPI3MR, 3596 M_ZERO|M_NOWAIT); 3597 3598 if (!delayed_dev_rmhs) 3599 return; 3600 delayed_dev_rmhs->handle = handle; 3601 delayed_dev_rmhs->iou_rc = iou_rc; 3602 TAILQ_INSERT_TAIL(&(sc->delayed_rmhs_list), delayed_dev_rmhs, list); 3603 mpi3mr_dprint(sc, MPI3MR_EVENT, "%s :DevRmHs: tr:handle(0x%04x) is postponed\n", 3604 __func__, handle); 3605 3606 3607 return; 3608 } 3609 drv_cmd = &sc->dev_rmhs_cmds[cmd_idx]; 3610 3611 issue_cmd: 3612 cmd_idx = drv_cmd->host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN; 3613 mpi3mr_dprint(sc, MPI3MR_EVENT, 3614 "%s :Issuing TR TM: for devhandle 0x%04x with dev_rmhs %d\n", 3615 __func__, handle, cmd_idx); 3616 3617 memset(&tm_req, 0, sizeof(tm_req)); 3618 if (drv_cmd->state & MPI3MR_CMD_PENDING) { 3619 mpi3mr_dprint(sc, MPI3MR_EVENT, "%s :Issue TM: Command is in use\n", __func__); 3620 goto out; 3621 } 3622 drv_cmd->state = MPI3MR_CMD_PENDING; 3623 drv_cmd->is_waiting = 0; 3624 drv_cmd->callback = mpi3mr_dev_rmhs_complete_tm; 3625 drv_cmd->dev_handle = handle; 3626 drv_cmd->iou_rc = iou_rc; 3627 tm_req.DevHandle = htole16(handle); 3628 tm_req.TaskType = MPI3_SCSITASKMGMT_TASKTYPE_TARGET_RESET; 3629 tm_req.HostTag = htole16(drv_cmd->host_tag); 3630 tm_req.TaskHostTag = htole16(MPI3MR_HOSTTAG_INVALID); 3631 tm_req.Function = MPI3_FUNCTION_SCSI_TASK_MGMT; 3632 3633 mpi3mr_set_bit(handle, sc->removepend_bitmap); 3634 retval = mpi3mr_submit_admin_cmd(sc, &tm_req, sizeof(tm_req)); 3635 if (retval) { 3636 mpi3mr_dprint(sc, MPI3MR_ERROR, "%s :Issue DevRmHsTM: Admin Post failed\n", 3637 __func__); 3638 goto out_failed; 3639 } 3640 out: 3641 return; 3642 out_failed: 3643 drv_cmd->state = MPI3MR_CMD_NOTUSED; 3644 drv_cmd->callback = NULL; 3645 drv_cmd->dev_handle = MPI3MR_INVALID_DEV_HANDLE; 3646 drv_cmd->retry_count = 0; 3647 mpi3mr_clear_bit(cmd_idx, sc->devrem_bitmap); 3648 } 3649 3650 /** 3651 * mpi3mr_complete_evt_ack - Event ack request completion 3652 * @sc: Adapter instance reference 3653 * @drv_cmd: Internal command tracker 3654 * 3655 * This is the completion handler for non blocking event 3656 * acknowledgment sent to the firmware and this will issue any 3657 * pending event acknowledgment request. 3658 * 3659 * Return: Nothing 3660 */ 3661 static void mpi3mr_complete_evt_ack(struct mpi3mr_softc *sc, 3662 struct mpi3mr_drvr_cmd *drv_cmd) 3663 { 3664 U16 cmd_idx = drv_cmd->host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN; 3665 struct delayed_evtack_node *delayed_evtack = NULL; 3666 3667 if (drv_cmd->ioc_status != MPI3_IOCSTATUS_SUCCESS) { 3668 mpi3mr_dprint(sc, MPI3MR_EVENT, 3669 "%s: Failed IOCStatus(0x%04x) Loginfo(0x%08x)\n", __func__, 3670 (drv_cmd->ioc_status & MPI3_IOCSTATUS_STATUS_MASK), 3671 drv_cmd->ioc_loginfo); 3672 } 3673 3674 if (!TAILQ_EMPTY(&sc->delayed_evtack_cmds_list)) { 3675 delayed_evtack = TAILQ_FIRST(&sc->delayed_evtack_cmds_list); 3676 mpi3mr_dprint(sc, MPI3MR_EVENT, 3677 "%s: processing delayed event ack for event %d\n", 3678 __func__, delayed_evtack->event); 3679 mpi3mr_send_evt_ack(sc, delayed_evtack->event, drv_cmd, 3680 delayed_evtack->event_ctx); 3681 TAILQ_REMOVE(&sc->delayed_evtack_cmds_list, delayed_evtack, list); 3682 free(delayed_evtack, M_MPI3MR); 3683 return; 3684 } 3685 drv_cmd->state = MPI3MR_CMD_NOTUSED; 3686 drv_cmd->callback = NULL; 3687 mpi3mr_clear_bit(cmd_idx, sc->evtack_cmds_bitmap); 3688 } 3689 3690 /** 3691 * mpi3mr_send_evt_ack - Issue event acknwoledgment request 3692 * @sc: Adapter instance reference 3693 * @event: MPI3 event id 3694 * @cmdparam: Internal command tracker 3695 * @event_ctx: Event context 3696 * 3697 * Issues event acknowledgment request to the firmware if there 3698 * is a free command to send the event ack else it to a pend 3699 * list so that it will be processed on a completion of a prior 3700 * event acknowledgment . 3701 * 3702 * Return: Nothing 3703 */ 3704 static void mpi3mr_send_evt_ack(struct mpi3mr_softc *sc, U8 event, 3705 struct mpi3mr_drvr_cmd *cmdparam, U32 event_ctx) 3706 { 3707 Mpi3EventAckRequest_t evtack_req; 3708 int retval = 0; 3709 U8 retrycount = 5; 3710 U16 cmd_idx = MPI3MR_NUM_EVTACKCMD; 3711 struct mpi3mr_drvr_cmd *drv_cmd = cmdparam; 3712 struct delayed_evtack_node *delayed_evtack = NULL; 3713 3714 if (drv_cmd) 3715 goto issue_cmd; 3716 do { 3717 cmd_idx = mpi3mr_find_first_zero_bit(sc->evtack_cmds_bitmap, 3718 MPI3MR_NUM_EVTACKCMD); 3719 if (cmd_idx < MPI3MR_NUM_EVTACKCMD) { 3720 if (!mpi3mr_test_and_set_bit(cmd_idx, 3721 sc->evtack_cmds_bitmap)) 3722 break; 3723 cmd_idx = MPI3MR_NUM_EVTACKCMD; 3724 } 3725 } while (retrycount--); 3726 3727 if (cmd_idx >= MPI3MR_NUM_EVTACKCMD) { 3728 delayed_evtack = malloc(sizeof(*delayed_evtack),M_MPI3MR, 3729 M_ZERO | M_NOWAIT); 3730 if (!delayed_evtack) 3731 return; 3732 delayed_evtack->event = event; 3733 delayed_evtack->event_ctx = event_ctx; 3734 TAILQ_INSERT_TAIL(&(sc->delayed_evtack_cmds_list), delayed_evtack, list); 3735 mpi3mr_dprint(sc, MPI3MR_EVENT, "%s : Event ack for event:%d is postponed\n", 3736 __func__, event); 3737 return; 3738 } 3739 drv_cmd = &sc->evtack_cmds[cmd_idx]; 3740 3741 issue_cmd: 3742 cmd_idx = drv_cmd->host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN; 3743 3744 memset(&evtack_req, 0, sizeof(evtack_req)); 3745 if (drv_cmd->state & MPI3MR_CMD_PENDING) { 3746 mpi3mr_dprint(sc, MPI3MR_EVENT, "%s: Command is in use\n", __func__); 3747 goto out; 3748 } 3749 drv_cmd->state = MPI3MR_CMD_PENDING; 3750 drv_cmd->is_waiting = 0; 3751 drv_cmd->callback = mpi3mr_complete_evt_ack; 3752 evtack_req.HostTag = htole16(drv_cmd->host_tag); 3753 evtack_req.Function = MPI3_FUNCTION_EVENT_ACK; 3754 evtack_req.Event = event; 3755 evtack_req.EventContext = htole32(event_ctx); 3756 retval = mpi3mr_submit_admin_cmd(sc, &evtack_req, 3757 sizeof(evtack_req)); 3758 3759 if (retval) { 3760 mpi3mr_dprint(sc, MPI3MR_ERROR, "%s: Admin Post failed\n", __func__); 3761 goto out_failed; 3762 } 3763 out: 3764 return; 3765 out_failed: 3766 drv_cmd->state = MPI3MR_CMD_NOTUSED; 3767 drv_cmd->callback = NULL; 3768 mpi3mr_clear_bit(cmd_idx, sc->evtack_cmds_bitmap); 3769 } 3770 3771 /* 3772 * mpi3mr_pcietopochg_evt_th - PCIETopologyChange evt tophalf 3773 * @sc: Adapter instance reference 3774 * @event_reply: Event data 3775 * 3776 * Checks for the reason code and based on that either block I/O 3777 * to device, or unblock I/O to the device, or start the device 3778 * removal handshake with reason as remove with the firmware for 3779 * PCIe devices. 3780 * 3781 * Return: Nothing 3782 */ 3783 static void mpi3mr_pcietopochg_evt_th(struct mpi3mr_softc *sc, 3784 Mpi3EventNotificationReply_t *event_reply) 3785 { 3786 Mpi3EventDataPcieTopologyChangeList_t *topo_evt = 3787 (Mpi3EventDataPcieTopologyChangeList_t *) event_reply->EventData; 3788 int i; 3789 U16 handle; 3790 U8 reason_code; 3791 struct mpi3mr_target *tgtdev = NULL; 3792 3793 for (i = 0; i < topo_evt->NumEntries; i++) { 3794 handle = le16toh(topo_evt->PortEntry[i].AttachedDevHandle); 3795 if (!handle) 3796 continue; 3797 reason_code = topo_evt->PortEntry[i].PortStatus; 3798 tgtdev = mpi3mr_find_target_by_dev_handle(sc->cam_sc, handle); 3799 switch (reason_code) { 3800 case MPI3_EVENT_PCIE_TOPO_PS_NOT_RESPONDING: 3801 if (tgtdev) { 3802 tgtdev->dev_removed = 1; 3803 tgtdev->dev_removedelay = 0; 3804 mpi3mr_atomic_set(&tgtdev->block_io, 0); 3805 } 3806 mpi3mr_dev_rmhs_send_tm(sc, handle, NULL, 3807 MPI3_CTRL_OP_REMOVE_DEVICE); 3808 break; 3809 case MPI3_EVENT_PCIE_TOPO_PS_DELAY_NOT_RESPONDING: 3810 if (tgtdev) { 3811 tgtdev->dev_removedelay = 1; 3812 mpi3mr_atomic_inc(&tgtdev->block_io); 3813 } 3814 break; 3815 case MPI3_EVENT_PCIE_TOPO_PS_RESPONDING: 3816 if (tgtdev && 3817 tgtdev->dev_removedelay) { 3818 tgtdev->dev_removedelay = 0; 3819 if (mpi3mr_atomic_read(&tgtdev->block_io) > 0) 3820 mpi3mr_atomic_dec(&tgtdev->block_io); 3821 } 3822 break; 3823 case MPI3_EVENT_PCIE_TOPO_PS_PORT_CHANGED: 3824 default: 3825 break; 3826 } 3827 } 3828 } 3829 3830 /** 3831 * mpi3mr_sastopochg_evt_th - SASTopologyChange evt tophalf 3832 * @sc: Adapter instance reference 3833 * @event_reply: Event data 3834 * 3835 * Checks for the reason code and based on that either block I/O 3836 * to device, or unblock I/O to the device, or start the device 3837 * removal handshake with reason as remove with the firmware for 3838 * SAS/SATA devices. 3839 * 3840 * Return: Nothing 3841 */ 3842 static void mpi3mr_sastopochg_evt_th(struct mpi3mr_softc *sc, 3843 Mpi3EventNotificationReply_t *event_reply) 3844 { 3845 Mpi3EventDataSasTopologyChangeList_t *topo_evt = 3846 (Mpi3EventDataSasTopologyChangeList_t *)event_reply->EventData; 3847 int i; 3848 U16 handle; 3849 U8 reason_code; 3850 struct mpi3mr_target *tgtdev = NULL; 3851 3852 for (i = 0; i < topo_evt->NumEntries; i++) { 3853 handle = le16toh(topo_evt->PhyEntry[i].AttachedDevHandle); 3854 if (!handle) 3855 continue; 3856 reason_code = topo_evt->PhyEntry[i].Status & 3857 MPI3_EVENT_SAS_TOPO_PHY_RC_MASK; 3858 tgtdev = mpi3mr_find_target_by_dev_handle(sc->cam_sc, handle); 3859 switch (reason_code) { 3860 case MPI3_EVENT_SAS_TOPO_PHY_RC_TARG_NOT_RESPONDING: 3861 if (tgtdev) { 3862 tgtdev->dev_removed = 1; 3863 tgtdev->dev_removedelay = 0; 3864 mpi3mr_atomic_set(&tgtdev->block_io, 0); 3865 } 3866 mpi3mr_dev_rmhs_send_tm(sc, handle, NULL, 3867 MPI3_CTRL_OP_REMOVE_DEVICE); 3868 break; 3869 case MPI3_EVENT_SAS_TOPO_PHY_RC_DELAY_NOT_RESPONDING: 3870 if (tgtdev) { 3871 tgtdev->dev_removedelay = 1; 3872 mpi3mr_atomic_inc(&tgtdev->block_io); 3873 } 3874 break; 3875 case MPI3_EVENT_SAS_TOPO_PHY_RC_RESPONDING: 3876 if (tgtdev && 3877 tgtdev->dev_removedelay) { 3878 tgtdev->dev_removedelay = 0; 3879 if (mpi3mr_atomic_read(&tgtdev->block_io) > 0) 3880 mpi3mr_atomic_dec(&tgtdev->block_io); 3881 } 3882 case MPI3_EVENT_SAS_TOPO_PHY_RC_PHY_CHANGED: 3883 default: 3884 break; 3885 } 3886 } 3887 3888 } 3889 /** 3890 * mpi3mr_devstatuschg_evt_th - DeviceStatusChange evt tophalf 3891 * @sc: Adapter instance reference 3892 * @event_reply: Event data 3893 * 3894 * Checks for the reason code and based on that either block I/O 3895 * to device, or unblock I/O to the device, or start the device 3896 * removal handshake with reason as remove/hide acknowledgment 3897 * with the firmware. 3898 * 3899 * Return: Nothing 3900 */ 3901 static void mpi3mr_devstatuschg_evt_th(struct mpi3mr_softc *sc, 3902 Mpi3EventNotificationReply_t *event_reply) 3903 { 3904 U16 dev_handle = 0; 3905 U8 ublock = 0, block = 0, hide = 0, uhide = 0, delete = 0, remove = 0; 3906 struct mpi3mr_target *tgtdev = NULL; 3907 Mpi3EventDataDeviceStatusChange_t *evtdata = 3908 (Mpi3EventDataDeviceStatusChange_t *) event_reply->EventData; 3909 3910 dev_handle = le16toh(evtdata->DevHandle); 3911 3912 switch (evtdata->ReasonCode) { 3913 case MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_STRT: 3914 case MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_STRT: 3915 block = 1; 3916 break; 3917 case MPI3_EVENT_DEV_STAT_RC_HIDDEN: 3918 delete = 1; 3919 hide = 1; 3920 break; 3921 case MPI3_EVENT_DEV_STAT_RC_NOT_HIDDEN: 3922 uhide = 1; 3923 break; 3924 case MPI3_EVENT_DEV_STAT_RC_VD_NOT_RESPONDING: 3925 delete = 1; 3926 remove = 1; 3927 break; 3928 case MPI3_EVENT_DEV_STAT_RC_INT_DEVICE_RESET_CMP: 3929 case MPI3_EVENT_DEV_STAT_RC_INT_IT_NEXUS_RESET_CMP: 3930 ublock = 1; 3931 break; 3932 default: 3933 break; 3934 } 3935 3936 tgtdev = mpi3mr_find_target_by_dev_handle(sc->cam_sc, dev_handle); 3937 3938 if (!tgtdev) { 3939 mpi3mr_dprint(sc, MPI3MR_ERROR, "%s :target with dev_handle:0x%x not found\n", 3940 __func__, dev_handle); 3941 return; 3942 } 3943 3944 if (block) 3945 mpi3mr_atomic_inc(&tgtdev->block_io); 3946 3947 if (hide) 3948 tgtdev->is_hidden = hide; 3949 3950 if (uhide) { 3951 tgtdev->is_hidden = 0; 3952 tgtdev->dev_removed = 0; 3953 } 3954 3955 if (delete) 3956 tgtdev->dev_removed = 1; 3957 3958 if (ublock) { 3959 if (mpi3mr_atomic_read(&tgtdev->block_io) > 0) 3960 mpi3mr_atomic_dec(&tgtdev->block_io); 3961 } 3962 3963 if (remove) { 3964 mpi3mr_dev_rmhs_send_tm(sc, dev_handle, NULL, 3965 MPI3_CTRL_OP_REMOVE_DEVICE); 3966 } 3967 if (hide) 3968 mpi3mr_dev_rmhs_send_tm(sc, dev_handle, NULL, 3969 MPI3_CTRL_OP_HIDDEN_ACK); 3970 } 3971 3972 /** 3973 * mpi3mr_preparereset_evt_th - Prepareforreset evt tophalf 3974 * @sc: Adapter instance reference 3975 * @event_reply: Event data 3976 * 3977 * Blocks and unblocks host level I/O based on the reason code 3978 * 3979 * Return: Nothing 3980 */ 3981 static void mpi3mr_preparereset_evt_th(struct mpi3mr_softc *sc, 3982 Mpi3EventNotificationReply_t *event_reply) 3983 { 3984 Mpi3EventDataPrepareForReset_t *evtdata = 3985 (Mpi3EventDataPrepareForReset_t *)event_reply->EventData; 3986 3987 if (evtdata->ReasonCode == MPI3_EVENT_PREPARE_RESET_RC_START) { 3988 mpi3mr_dprint(sc, MPI3MR_EVENT, "%s :Recieved PrepForReset Event with RC=START\n", 3989 __func__); 3990 if (sc->prepare_for_reset) 3991 return; 3992 sc->prepare_for_reset = 1; 3993 sc->prepare_for_reset_timeout_counter = 0; 3994 } else if (evtdata->ReasonCode == MPI3_EVENT_PREPARE_RESET_RC_ABORT) { 3995 mpi3mr_dprint(sc, MPI3MR_EVENT, "%s :Recieved PrepForReset Event with RC=ABORT\n", 3996 __func__); 3997 sc->prepare_for_reset = 0; 3998 sc->prepare_for_reset_timeout_counter = 0; 3999 } 4000 if ((event_reply->MsgFlags & MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK) 4001 == MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED) 4002 mpi3mr_send_evt_ack(sc, event_reply->Event, NULL, 4003 le32toh(event_reply->EventContext)); 4004 } 4005 4006 /** 4007 * mpi3mr_energypackchg_evt_th - Energypackchange evt tophalf 4008 * @sc: Adapter instance reference 4009 * @event_reply: Event data 4010 * 4011 * Identifies the new shutdown timeout value and update. 4012 * 4013 * Return: Nothing 4014 */ 4015 static void mpi3mr_energypackchg_evt_th(struct mpi3mr_softc *sc, 4016 Mpi3EventNotificationReply_t *event_reply) 4017 { 4018 Mpi3EventDataEnergyPackChange_t *evtdata = 4019 (Mpi3EventDataEnergyPackChange_t *)event_reply->EventData; 4020 U16 shutdown_timeout = le16toh(evtdata->ShutdownTimeout); 4021 4022 if (shutdown_timeout <= 0) { 4023 mpi3mr_dprint(sc, MPI3MR_ERROR, 4024 "%s :Invalid Shutdown Timeout received = %d\n", 4025 __func__, shutdown_timeout); 4026 return; 4027 } 4028 4029 mpi3mr_dprint(sc, MPI3MR_EVENT, 4030 "%s :Previous Shutdown Timeout Value = %d New Shutdown Timeout Value = %d\n", 4031 __func__, sc->facts.shutdown_timeout, shutdown_timeout); 4032 sc->facts.shutdown_timeout = shutdown_timeout; 4033 } 4034 4035 /** 4036 * mpi3mr_cablemgmt_evt_th - Cable mgmt evt tophalf 4037 * @sc: Adapter instance reference 4038 * @event_reply: Event data 4039 * 4040 * Displays Cable manegemt event details. 4041 * 4042 * Return: Nothing 4043 */ 4044 static void mpi3mr_cablemgmt_evt_th(struct mpi3mr_softc *sc, 4045 Mpi3EventNotificationReply_t *event_reply) 4046 { 4047 Mpi3EventDataCableManagement_t *evtdata = 4048 (Mpi3EventDataCableManagement_t *)event_reply->EventData; 4049 4050 switch (evtdata->Status) { 4051 case MPI3_EVENT_CABLE_MGMT_STATUS_INSUFFICIENT_POWER: 4052 { 4053 mpi3mr_dprint(sc, MPI3MR_INFO, "An active cable with ReceptacleID %d cannot be powered.\n" 4054 "Devices connected to this cable are not detected.\n" 4055 "This cable requires %d mW of power.\n", 4056 evtdata->ReceptacleID, 4057 le32toh(evtdata->ActiveCablePowerRequirement)); 4058 break; 4059 } 4060 case MPI3_EVENT_CABLE_MGMT_STATUS_DEGRADED: 4061 { 4062 mpi3mr_dprint(sc, MPI3MR_INFO, "A cable with ReceptacleID %d is not running at optimal speed\n", 4063 evtdata->ReceptacleID); 4064 break; 4065 } 4066 default: 4067 break; 4068 } 4069 } 4070 4071 /** 4072 * mpi3mr_process_events - Event's toph-half handler 4073 * @sc: Adapter instance reference 4074 * @event_reply: Event data 4075 * 4076 * Top half of event processing. 4077 * 4078 * Return: Nothing 4079 */ 4080 static void mpi3mr_process_events(struct mpi3mr_softc *sc, 4081 uintptr_t data, Mpi3EventNotificationReply_t *event_reply) 4082 { 4083 U16 evt_type; 4084 bool ack_req = 0, process_evt_bh = 0; 4085 struct mpi3mr_fw_event_work *fw_event; 4086 U16 sz; 4087 4088 if (sc->mpi3mr_flags & MPI3MR_FLAGS_SHUTDOWN) 4089 goto out; 4090 4091 if ((event_reply->MsgFlags & MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_MASK) 4092 == MPI3_EVENT_NOTIFY_MSGFLAGS_ACK_REQUIRED) 4093 ack_req = 1; 4094 4095 evt_type = event_reply->Event; 4096 4097 switch (evt_type) { 4098 case MPI3_EVENT_DEVICE_ADDED: 4099 { 4100 Mpi3DevicePage0_t *dev_pg0 = 4101 (Mpi3DevicePage0_t *) event_reply->EventData; 4102 if (mpi3mr_create_device(sc, dev_pg0)) 4103 mpi3mr_dprint(sc, MPI3MR_ERROR, 4104 "%s :Failed to add device in the device add event\n", 4105 __func__); 4106 else 4107 process_evt_bh = 1; 4108 break; 4109 } 4110 4111 case MPI3_EVENT_DEVICE_STATUS_CHANGE: 4112 { 4113 process_evt_bh = 1; 4114 mpi3mr_devstatuschg_evt_th(sc, event_reply); 4115 break; 4116 } 4117 case MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST: 4118 { 4119 process_evt_bh = 1; 4120 mpi3mr_sastopochg_evt_th(sc, event_reply); 4121 break; 4122 } 4123 case MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST: 4124 { 4125 process_evt_bh = 1; 4126 mpi3mr_pcietopochg_evt_th(sc, event_reply); 4127 break; 4128 } 4129 case MPI3_EVENT_PREPARE_FOR_RESET: 4130 { 4131 mpi3mr_preparereset_evt_th(sc, event_reply); 4132 ack_req = 0; 4133 break; 4134 } 4135 case MPI3_EVENT_DEVICE_INFO_CHANGED: 4136 case MPI3_EVENT_LOG_DATA: 4137 { 4138 process_evt_bh = 1; 4139 break; 4140 } 4141 case MPI3_EVENT_ENERGY_PACK_CHANGE: 4142 { 4143 mpi3mr_energypackchg_evt_th(sc, event_reply); 4144 break; 4145 } 4146 case MPI3_EVENT_CABLE_MGMT: 4147 { 4148 mpi3mr_cablemgmt_evt_th(sc, event_reply); 4149 break; 4150 } 4151 4152 case MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE: 4153 case MPI3_EVENT_SAS_DISCOVERY: 4154 case MPI3_EVENT_SAS_DEVICE_DISCOVERY_ERROR: 4155 case MPI3_EVENT_SAS_BROADCAST_PRIMITIVE: 4156 case MPI3_EVENT_PCIE_ENUMERATION: 4157 break; 4158 default: 4159 mpi3mr_dprint(sc, MPI3MR_INFO, "%s :Event 0x%02x is not handled by driver\n", 4160 __func__, evt_type); 4161 break; 4162 } 4163 4164 if (process_evt_bh || ack_req) { 4165 fw_event = malloc(sizeof(struct mpi3mr_fw_event_work), M_MPI3MR, 4166 M_ZERO|M_NOWAIT); 4167 4168 if (!fw_event) { 4169 printf("%s: allocate failed for fw_event\n", __func__); 4170 return; 4171 } 4172 4173 sz = le16toh(event_reply->EventDataLength) * 4; 4174 fw_event->event_data = malloc(sz, M_MPI3MR, M_ZERO|M_NOWAIT); 4175 4176 if (!fw_event->event_data) { 4177 printf("%s: allocate failed for event_data\n", __func__); 4178 free(fw_event, M_MPI3MR); 4179 return; 4180 } 4181 4182 bcopy(event_reply->EventData, fw_event->event_data, sz); 4183 fw_event->event = event_reply->Event; 4184 if ((event_reply->Event == MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST || 4185 event_reply->Event == MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST || 4186 event_reply->Event == MPI3_EVENT_ENCL_DEVICE_STATUS_CHANGE ) && 4187 sc->track_mapping_events) 4188 sc->pending_map_events++; 4189 4190 /* 4191 * Events should be processed after Port enable is completed. 4192 */ 4193 if ((event_reply->Event == MPI3_EVENT_SAS_TOPOLOGY_CHANGE_LIST || 4194 event_reply->Event == MPI3_EVENT_PCIE_TOPOLOGY_CHANGE_LIST ) && 4195 !(sc->mpi3mr_flags & MPI3MR_FLAGS_PORT_ENABLE_DONE)) 4196 mpi3mr_startup_increment(sc->cam_sc); 4197 4198 fw_event->send_ack = ack_req; 4199 fw_event->event_context = le32toh(event_reply->EventContext); 4200 fw_event->event_data_size = sz; 4201 fw_event->process_event = process_evt_bh; 4202 4203 mtx_lock(&sc->fwevt_lock); 4204 TAILQ_INSERT_TAIL(&sc->cam_sc->ev_queue, fw_event, ev_link); 4205 taskqueue_enqueue(sc->cam_sc->ev_tq, &sc->cam_sc->ev_task); 4206 mtx_unlock(&sc->fwevt_lock); 4207 4208 } 4209 out: 4210 return; 4211 } 4212 4213 static void mpi3mr_handle_events(struct mpi3mr_softc *sc, uintptr_t data, 4214 Mpi3DefaultReply_t *def_reply) 4215 { 4216 Mpi3EventNotificationReply_t *event_reply = 4217 (Mpi3EventNotificationReply_t *)def_reply; 4218 4219 sc->change_count = event_reply->IOCChangeCount; 4220 mpi3mr_display_event_data(sc, event_reply); 4221 4222 mpi3mr_process_events(sc, data, event_reply); 4223 } 4224 4225 static void mpi3mr_process_admin_reply_desc(struct mpi3mr_softc *sc, 4226 Mpi3DefaultReplyDescriptor_t *reply_desc, U64 *reply_dma) 4227 { 4228 U16 reply_desc_type, host_tag = 0, idx; 4229 U16 ioc_status = MPI3_IOCSTATUS_SUCCESS; 4230 U32 ioc_loginfo = 0; 4231 Mpi3StatusReplyDescriptor_t *status_desc; 4232 Mpi3AddressReplyDescriptor_t *addr_desc; 4233 Mpi3SuccessReplyDescriptor_t *success_desc; 4234 Mpi3DefaultReply_t *def_reply = NULL; 4235 struct mpi3mr_drvr_cmd *cmdptr = NULL; 4236 Mpi3SCSIIOReply_t *scsi_reply; 4237 U8 *sense_buf = NULL; 4238 4239 *reply_dma = 0; 4240 reply_desc_type = reply_desc->ReplyFlags & 4241 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK; 4242 switch (reply_desc_type) { 4243 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS: 4244 status_desc = (Mpi3StatusReplyDescriptor_t *)reply_desc; 4245 host_tag = status_desc->HostTag; 4246 ioc_status = status_desc->IOCStatus; 4247 if (ioc_status & 4248 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 4249 ioc_loginfo = status_desc->IOCLogInfo; 4250 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; 4251 break; 4252 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY: 4253 addr_desc = (Mpi3AddressReplyDescriptor_t *)reply_desc; 4254 *reply_dma = addr_desc->ReplyFrameAddress; 4255 def_reply = mpi3mr_get_reply_virt_addr(sc, *reply_dma); 4256 if (def_reply == NULL) 4257 goto out; 4258 host_tag = def_reply->HostTag; 4259 ioc_status = def_reply->IOCStatus; 4260 if (ioc_status & 4261 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 4262 ioc_loginfo = def_reply->IOCLogInfo; 4263 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; 4264 if (def_reply->Function == MPI3_FUNCTION_SCSI_IO) { 4265 scsi_reply = (Mpi3SCSIIOReply_t *)def_reply; 4266 sense_buf = mpi3mr_get_sensebuf_virt_addr(sc, 4267 scsi_reply->SenseDataBufferAddress); 4268 } 4269 break; 4270 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS: 4271 success_desc = (Mpi3SuccessReplyDescriptor_t *)reply_desc; 4272 host_tag = success_desc->HostTag; 4273 break; 4274 default: 4275 break; 4276 } 4277 switch (host_tag) { 4278 case MPI3MR_HOSTTAG_INITCMDS: 4279 cmdptr = &sc->init_cmds; 4280 break; 4281 case MPI3MR_HOSTTAG_IOCTLCMDS: 4282 cmdptr = &sc->ioctl_cmds; 4283 break; 4284 case MPI3MR_HOSTTAG_TMS: 4285 cmdptr = &sc->host_tm_cmds; 4286 wakeup((void *)&sc->tm_chan); 4287 break; 4288 case MPI3MR_HOSTTAG_PELABORT: 4289 cmdptr = &sc->pel_abort_cmd; 4290 break; 4291 case MPI3MR_HOSTTAG_PELWAIT: 4292 cmdptr = &sc->pel_cmds; 4293 break; 4294 case MPI3MR_HOSTTAG_INVALID: 4295 if (def_reply && def_reply->Function == 4296 MPI3_FUNCTION_EVENT_NOTIFICATION) 4297 mpi3mr_handle_events(sc, *reply_dma ,def_reply); 4298 default: 4299 break; 4300 } 4301 4302 if (host_tag >= MPI3MR_HOSTTAG_DEVRMCMD_MIN && 4303 host_tag <= MPI3MR_HOSTTAG_DEVRMCMD_MAX ) { 4304 idx = host_tag - MPI3MR_HOSTTAG_DEVRMCMD_MIN; 4305 cmdptr = &sc->dev_rmhs_cmds[idx]; 4306 } 4307 4308 if (host_tag >= MPI3MR_HOSTTAG_EVTACKCMD_MIN && 4309 host_tag <= MPI3MR_HOSTTAG_EVTACKCMD_MAX) { 4310 idx = host_tag - MPI3MR_HOSTTAG_EVTACKCMD_MIN; 4311 cmdptr = &sc->evtack_cmds[idx]; 4312 } 4313 4314 if (cmdptr) { 4315 if (cmdptr->state & MPI3MR_CMD_PENDING) { 4316 cmdptr->state |= MPI3MR_CMD_COMPLETE; 4317 cmdptr->ioc_loginfo = ioc_loginfo; 4318 cmdptr->ioc_status = ioc_status; 4319 cmdptr->state &= ~MPI3MR_CMD_PENDING; 4320 if (def_reply) { 4321 cmdptr->state |= MPI3MR_CMD_REPLYVALID; 4322 memcpy((U8 *)cmdptr->reply, (U8 *)def_reply, 4323 sc->reply_sz); 4324 } 4325 if (sense_buf && cmdptr->sensebuf) { 4326 cmdptr->is_senseprst = 1; 4327 memcpy(cmdptr->sensebuf, sense_buf, 4328 MPI3MR_SENSEBUF_SZ); 4329 } 4330 if (cmdptr->is_waiting) { 4331 complete(&cmdptr->completion); 4332 cmdptr->is_waiting = 0; 4333 } else if (cmdptr->callback) 4334 cmdptr->callback(sc, cmdptr); 4335 } 4336 } 4337 out: 4338 if (sense_buf != NULL) 4339 mpi3mr_repost_sense_buf(sc, 4340 scsi_reply->SenseDataBufferAddress); 4341 return; 4342 } 4343 4344 /* 4345 * mpi3mr_complete_admin_cmd: ISR routine for admin commands 4346 * @sc: Adapter's soft instance 4347 * 4348 * This function processes admin command completions. 4349 */ 4350 static int mpi3mr_complete_admin_cmd(struct mpi3mr_softc *sc) 4351 { 4352 U32 exp_phase = sc->admin_reply_ephase; 4353 U32 adm_reply_ci = sc->admin_reply_ci; 4354 U32 num_adm_reply = 0; 4355 U64 reply_dma = 0; 4356 Mpi3DefaultReplyDescriptor_t *reply_desc; 4357 4358 mtx_lock_spin(&sc->admin_reply_lock); 4359 if (sc->admin_in_use == false) { 4360 sc->admin_in_use = true; 4361 mtx_unlock_spin(&sc->admin_reply_lock); 4362 } else { 4363 mtx_unlock_spin(&sc->admin_reply_lock); 4364 return 0; 4365 } 4366 4367 reply_desc = (Mpi3DefaultReplyDescriptor_t *)sc->admin_reply + 4368 adm_reply_ci; 4369 4370 if ((reply_desc->ReplyFlags & 4371 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) { 4372 mtx_lock_spin(&sc->admin_reply_lock); 4373 sc->admin_in_use = false; 4374 mtx_unlock_spin(&sc->admin_reply_lock); 4375 return 0; 4376 } 4377 4378 do { 4379 sc->admin_req_ci = reply_desc->RequestQueueCI; 4380 mpi3mr_process_admin_reply_desc(sc, reply_desc, &reply_dma); 4381 if (reply_dma) 4382 mpi3mr_repost_reply_buf(sc, reply_dma); 4383 num_adm_reply++; 4384 if (++adm_reply_ci == sc->num_admin_replies) { 4385 adm_reply_ci = 0; 4386 exp_phase ^= 1; 4387 } 4388 reply_desc = 4389 (Mpi3DefaultReplyDescriptor_t *)sc->admin_reply + 4390 adm_reply_ci; 4391 if ((reply_desc->ReplyFlags & 4392 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 4393 break; 4394 } while (1); 4395 4396 mpi3mr_regwrite(sc, MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET, adm_reply_ci); 4397 sc->admin_reply_ci = adm_reply_ci; 4398 sc->admin_reply_ephase = exp_phase; 4399 mtx_lock_spin(&sc->admin_reply_lock); 4400 sc->admin_in_use = false; 4401 mtx_unlock_spin(&sc->admin_reply_lock); 4402 return num_adm_reply; 4403 } 4404 4405 static void 4406 mpi3mr_cmd_done(struct mpi3mr_softc *sc, struct mpi3mr_cmd *cmd) 4407 { 4408 mpi3mr_unmap_request(sc, cmd); 4409 4410 mtx_lock(&sc->mpi3mr_mtx); 4411 if (cmd->callout_owner) { 4412 callout_stop(&cmd->callout); 4413 cmd->callout_owner = false; 4414 } 4415 4416 if (sc->unrecoverable) 4417 mpi3mr_set_ccbstatus(cmd->ccb, CAM_DEV_NOT_THERE); 4418 4419 xpt_done(cmd->ccb); 4420 cmd->ccb = NULL; 4421 mtx_unlock(&sc->mpi3mr_mtx); 4422 mpi3mr_release_command(cmd); 4423 } 4424 4425 void mpi3mr_process_op_reply_desc(struct mpi3mr_softc *sc, 4426 Mpi3DefaultReplyDescriptor_t *reply_desc, U64 *reply_dma) 4427 { 4428 U16 reply_desc_type, host_tag = 0; 4429 U16 ioc_status = MPI3_IOCSTATUS_SUCCESS; 4430 U32 ioc_loginfo = 0; 4431 Mpi3StatusReplyDescriptor_t *status_desc = NULL; 4432 Mpi3AddressReplyDescriptor_t *addr_desc = NULL; 4433 Mpi3SuccessReplyDescriptor_t *success_desc = NULL; 4434 Mpi3SCSIIOReply_t *scsi_reply = NULL; 4435 U8 *sense_buf = NULL; 4436 U8 scsi_state = 0, scsi_status = 0, sense_state = 0; 4437 U32 xfer_count = 0, sense_count =0, resp_data = 0; 4438 struct mpi3mr_cmd *cm = NULL; 4439 union ccb *ccb; 4440 struct ccb_scsiio *csio; 4441 struct mpi3mr_cam_softc *cam_sc; 4442 U32 target_id; 4443 U8 *scsi_cdb; 4444 struct mpi3mr_target *target = NULL; 4445 U32 ioc_pend_data_len = 0, tg_pend_data_len = 0, data_len_blks = 0; 4446 struct mpi3mr_throttle_group_info *tg = NULL; 4447 U8 throttle_enabled_dev = 0; 4448 static int ratelimit; 4449 4450 *reply_dma = 0; 4451 reply_desc_type = reply_desc->ReplyFlags & 4452 MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK; 4453 switch (reply_desc_type) { 4454 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS: 4455 status_desc = (Mpi3StatusReplyDescriptor_t *)reply_desc; 4456 host_tag = status_desc->HostTag; 4457 ioc_status = status_desc->IOCStatus; 4458 if (ioc_status & 4459 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 4460 ioc_loginfo = status_desc->IOCLogInfo; 4461 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; 4462 break; 4463 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY: 4464 addr_desc = (Mpi3AddressReplyDescriptor_t *)reply_desc; 4465 *reply_dma = addr_desc->ReplyFrameAddress; 4466 scsi_reply = mpi3mr_get_reply_virt_addr(sc, 4467 *reply_dma); 4468 if (scsi_reply == NULL) { 4469 mpi3mr_dprint(sc, MPI3MR_ERROR, "scsi_reply is NULL, " 4470 "this shouldn't happen, reply_desc: %p\n", 4471 reply_desc); 4472 goto out; 4473 } 4474 4475 host_tag = scsi_reply->HostTag; 4476 ioc_status = scsi_reply->IOCStatus; 4477 scsi_status = scsi_reply->SCSIStatus; 4478 scsi_state = scsi_reply->SCSIState; 4479 sense_state = (scsi_state & MPI3_SCSI_STATE_SENSE_MASK); 4480 xfer_count = scsi_reply->TransferCount; 4481 sense_count = scsi_reply->SenseCount; 4482 resp_data = scsi_reply->ResponseData; 4483 sense_buf = mpi3mr_get_sensebuf_virt_addr(sc, 4484 scsi_reply->SenseDataBufferAddress); 4485 if (ioc_status & 4486 MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL) 4487 ioc_loginfo = scsi_reply->IOCLogInfo; 4488 ioc_status &= MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK; 4489 if (sense_state == MPI3_SCSI_STATE_SENSE_BUFF_Q_EMPTY) 4490 mpi3mr_dprint(sc, MPI3MR_ERROR, "Ran out of sense buffers\n"); 4491 4492 break; 4493 case MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS: 4494 success_desc = (Mpi3SuccessReplyDescriptor_t *)reply_desc; 4495 host_tag = success_desc->HostTag; 4496 4497 default: 4498 break; 4499 } 4500 4501 cm = sc->cmd_list[host_tag]; 4502 4503 if (cm->state == MPI3MR_CMD_STATE_FREE) 4504 goto out; 4505 4506 cam_sc = sc->cam_sc; 4507 ccb = cm->ccb; 4508 csio = &ccb->csio; 4509 target_id = csio->ccb_h.target_id; 4510 4511 scsi_cdb = scsiio_cdb_ptr(csio); 4512 4513 target = mpi3mr_find_target_by_per_id(cam_sc, target_id); 4514 if (sc->iot_enable) { 4515 data_len_blks = csio->dxfer_len >> 9; 4516 4517 if (target) { 4518 tg = target->throttle_group; 4519 throttle_enabled_dev = 4520 target->io_throttle_enabled; 4521 } 4522 4523 if ((data_len_blks >= sc->io_throttle_data_length) && 4524 throttle_enabled_dev) { 4525 mpi3mr_atomic_sub(&sc->pend_large_data_sz, data_len_blks); 4526 ioc_pend_data_len = mpi3mr_atomic_read( 4527 &sc->pend_large_data_sz); 4528 if (tg) { 4529 mpi3mr_atomic_sub(&tg->pend_large_data_sz, 4530 data_len_blks); 4531 tg_pend_data_len = mpi3mr_atomic_read(&tg->pend_large_data_sz); 4532 if (ratelimit % 1000) { 4533 mpi3mr_dprint(sc, MPI3MR_IOT, 4534 "large vd_io completion persist_id(%d), handle(0x%04x), data_len(%d)," 4535 "ioc_pending(%d), tg_pending(%d), ioc_low(%d), tg_low(%d)\n", 4536 target->per_id, 4537 target->dev_handle, 4538 data_len_blks, ioc_pend_data_len, 4539 tg_pend_data_len, 4540 sc->io_throttle_low, 4541 tg->low); 4542 ratelimit++; 4543 } 4544 if (tg->io_divert && ((ioc_pend_data_len <= 4545 sc->io_throttle_low) && 4546 (tg_pend_data_len <= tg->low))) { 4547 tg->io_divert = 0; 4548 mpi3mr_dprint(sc, MPI3MR_IOT, 4549 "VD: Coming out of divert perst_id(%d) tg_id(%d)\n", 4550 target->per_id, tg->id); 4551 mpi3mr_set_io_divert_for_all_vd_in_tg( 4552 sc, tg, 0); 4553 } 4554 } else { 4555 if (ratelimit % 1000) { 4556 mpi3mr_dprint(sc, MPI3MR_IOT, 4557 "large pd_io completion persist_id(%d), handle(0x%04x), data_len(%d), ioc_pending(%d), ioc_low(%d)\n", 4558 target->per_id, 4559 target->dev_handle, 4560 data_len_blks, ioc_pend_data_len, 4561 sc->io_throttle_low); 4562 ratelimit++; 4563 } 4564 4565 if (ioc_pend_data_len <= sc->io_throttle_low) { 4566 target->io_divert = 0; 4567 mpi3mr_dprint(sc, MPI3MR_IOT, 4568 "PD: Coming out of divert perst_id(%d)\n", 4569 target->per_id); 4570 } 4571 } 4572 4573 } else if (target->io_divert) { 4574 ioc_pend_data_len = mpi3mr_atomic_read(&sc->pend_large_data_sz); 4575 if (!tg) { 4576 if (ratelimit % 1000) { 4577 mpi3mr_dprint(sc, MPI3MR_IOT, 4578 "pd_io completion persist_id(%d), handle(0x%04x), data_len(%d), ioc_pending(%d), ioc_low(%d)\n", 4579 target->per_id, 4580 target->dev_handle, 4581 data_len_blks, ioc_pend_data_len, 4582 sc->io_throttle_low); 4583 ratelimit++; 4584 } 4585 4586 if ( ioc_pend_data_len <= sc->io_throttle_low) { 4587 mpi3mr_dprint(sc, MPI3MR_IOT, 4588 "PD: Coming out of divert perst_id(%d)\n", 4589 target->per_id); 4590 target->io_divert = 0; 4591 } 4592 4593 } else if (ioc_pend_data_len <= sc->io_throttle_low) { 4594 tg_pend_data_len = mpi3mr_atomic_read(&tg->pend_large_data_sz); 4595 if (ratelimit % 1000) { 4596 mpi3mr_dprint(sc, MPI3MR_IOT, 4597 "vd_io completion persist_id(%d), handle(0x%04x), data_len(%d)," 4598 "ioc_pending(%d), tg_pending(%d), ioc_low(%d), tg_low(%d)\n", 4599 target->per_id, 4600 target->dev_handle, 4601 data_len_blks, ioc_pend_data_len, 4602 tg_pend_data_len, 4603 sc->io_throttle_low, 4604 tg->low); 4605 ratelimit++; 4606 } 4607 if (tg->io_divert && (tg_pend_data_len <= tg->low)) { 4608 tg->io_divert = 0; 4609 mpi3mr_dprint(sc, MPI3MR_IOT, 4610 "VD: Coming out of divert perst_id(%d) tg_id(%d)\n", 4611 target->per_id, tg->id); 4612 mpi3mr_set_io_divert_for_all_vd_in_tg( 4613 sc, tg, 0); 4614 } 4615 4616 } 4617 } 4618 } 4619 4620 if (success_desc) { 4621 mpi3mr_set_ccbstatus(ccb, CAM_REQ_CMP); 4622 goto out_success; 4623 } 4624 4625 if (ioc_status == MPI3_IOCSTATUS_SCSI_DATA_UNDERRUN 4626 && xfer_count == 0 && (scsi_status == MPI3_SCSI_STATUS_BUSY || 4627 scsi_status == MPI3_SCSI_STATUS_RESERVATION_CONFLICT || 4628 scsi_status == MPI3_SCSI_STATUS_TASK_SET_FULL)) 4629 ioc_status = MPI3_IOCSTATUS_SUCCESS; 4630 4631 if ((sense_state == MPI3_SCSI_STATE_SENSE_VALID) && sense_count 4632 && sense_buf) { 4633 int sense_len, returned_sense_len; 4634 4635 returned_sense_len = min(le32toh(sense_count), 4636 sizeof(struct scsi_sense_data)); 4637 if (returned_sense_len < csio->sense_len) 4638 csio->sense_resid = csio->sense_len - 4639 returned_sense_len; 4640 else 4641 csio->sense_resid = 0; 4642 4643 sense_len = min(returned_sense_len, 4644 csio->sense_len - csio->sense_resid); 4645 bzero(&csio->sense_data, sizeof(csio->sense_data)); 4646 bcopy(sense_buf, &csio->sense_data, sense_len); 4647 ccb->ccb_h.status |= CAM_AUTOSNS_VALID; 4648 } 4649 4650 switch (ioc_status) { 4651 case MPI3_IOCSTATUS_BUSY: 4652 case MPI3_IOCSTATUS_INSUFFICIENT_RESOURCES: 4653 mpi3mr_set_ccbstatus(ccb, CAM_REQUEUE_REQ); 4654 break; 4655 case MPI3_IOCSTATUS_SCSI_DEVICE_NOT_THERE: 4656 /* 4657 * If devinfo is 0 this will be a volume. In that case don't 4658 * tell CAM that the volume is not there. We want volumes to 4659 * be enumerated until they are deleted/removed, not just 4660 * failed. 4661 */ 4662 if (cm->targ->devinfo == 0) 4663 mpi3mr_set_ccbstatus(ccb, CAM_REQ_CMP); 4664 else 4665 mpi3mr_set_ccbstatus(ccb, CAM_DEV_NOT_THERE); 4666 break; 4667 case MPI3_IOCSTATUS_SCSI_TASK_TERMINATED: 4668 case MPI3_IOCSTATUS_SCSI_IOC_TERMINATED: 4669 case MPI3_IOCSTATUS_SCSI_EXT_TERMINATED: 4670 mpi3mr_set_ccbstatus(ccb, CAM_SCSI_BUSY); 4671 mpi3mr_dprint(sc, MPI3MR_TRACE, 4672 "func: %s line:%d tgt %u Hosttag %u loginfo %x\n", 4673 __func__, __LINE__, 4674 target_id, cm->hosttag, 4675 le32toh(scsi_reply->IOCLogInfo)); 4676 mpi3mr_dprint(sc, MPI3MR_TRACE, 4677 "SCSIStatus %x SCSIState %x xfercount %u\n", 4678 scsi_reply->SCSIStatus, scsi_reply->SCSIState, 4679 le32toh(xfer_count)); 4680 break; 4681 case MPI3_IOCSTATUS_SCSI_DATA_OVERRUN: 4682 /* resid is ignored for this condition */ 4683 csio->resid = 0; 4684 mpi3mr_set_ccbstatus(ccb, CAM_DATA_RUN_ERR); 4685 break; 4686 case MPI3_IOCSTATUS_SCSI_DATA_UNDERRUN: 4687 csio->resid = cm->length - le32toh(xfer_count); 4688 case MPI3_IOCSTATUS_SCSI_RECOVERED_ERROR: 4689 case MPI3_IOCSTATUS_SUCCESS: 4690 if ((scsi_reply->IOCStatus & MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK) == 4691 MPI3_IOCSTATUS_SCSI_RECOVERED_ERROR) 4692 mpi3mr_dprint(sc, MPI3MR_XINFO, "func: %s line: %d recovered error\n", __func__, __LINE__); 4693 4694 /* Completion failed at the transport level. */ 4695 if (scsi_reply->SCSIState & (MPI3_SCSI_STATE_NO_SCSI_STATUS | 4696 MPI3_SCSI_STATE_TERMINATED)) { 4697 mpi3mr_set_ccbstatus(ccb, CAM_REQ_CMP_ERR); 4698 break; 4699 } 4700 4701 /* In a modern packetized environment, an autosense failure 4702 * implies that there's not much else that can be done to 4703 * recover the command. 4704 */ 4705 if (scsi_reply->SCSIState & MPI3_SCSI_STATE_SENSE_VALID) { 4706 mpi3mr_set_ccbstatus(ccb, CAM_AUTOSENSE_FAIL); 4707 break; 4708 } 4709 4710 /* 4711 * Intentionally override the normal SCSI status reporting 4712 * for these two cases. These are likely to happen in a 4713 * multi-initiator environment, and we want to make sure that 4714 * CAM retries these commands rather than fail them. 4715 */ 4716 if ((scsi_reply->SCSIStatus == MPI3_SCSI_STATUS_COMMAND_TERMINATED) || 4717 (scsi_reply->SCSIStatus == MPI3_SCSI_STATUS_TASK_ABORTED)) { 4718 mpi3mr_set_ccbstatus(ccb, CAM_REQ_ABORTED); 4719 break; 4720 } 4721 4722 /* Handle normal status and sense */ 4723 csio->scsi_status = scsi_reply->SCSIStatus; 4724 if (scsi_reply->SCSIStatus == MPI3_SCSI_STATUS_GOOD) 4725 mpi3mr_set_ccbstatus(ccb, CAM_REQ_CMP); 4726 else 4727 mpi3mr_set_ccbstatus(ccb, CAM_SCSI_STATUS_ERROR); 4728 4729 if (scsi_reply->SCSIState & MPI3_SCSI_STATE_SENSE_VALID) { 4730 int sense_len, returned_sense_len; 4731 4732 returned_sense_len = min(le32toh(scsi_reply->SenseCount), 4733 sizeof(struct scsi_sense_data)); 4734 if (returned_sense_len < csio->sense_len) 4735 csio->sense_resid = csio->sense_len - 4736 returned_sense_len; 4737 else 4738 csio->sense_resid = 0; 4739 4740 sense_len = min(returned_sense_len, 4741 csio->sense_len - csio->sense_resid); 4742 bzero(&csio->sense_data, sizeof(csio->sense_data)); 4743 bcopy(cm->sense, &csio->sense_data, sense_len); 4744 ccb->ccb_h.status |= CAM_AUTOSNS_VALID; 4745 } 4746 4747 break; 4748 case MPI3_IOCSTATUS_INVALID_SGL: 4749 mpi3mr_set_ccbstatus(ccb, CAM_UNREC_HBA_ERROR); 4750 break; 4751 case MPI3_IOCSTATUS_EEDP_GUARD_ERROR: 4752 case MPI3_IOCSTATUS_EEDP_REF_TAG_ERROR: 4753 case MPI3_IOCSTATUS_EEDP_APP_TAG_ERROR: 4754 case MPI3_IOCSTATUS_SCSI_PROTOCOL_ERROR: 4755 case MPI3_IOCSTATUS_INVALID_FUNCTION: 4756 case MPI3_IOCSTATUS_INTERNAL_ERROR: 4757 case MPI3_IOCSTATUS_INVALID_FIELD: 4758 case MPI3_IOCSTATUS_INVALID_STATE: 4759 case MPI3_IOCSTATUS_SCSI_IO_DATA_ERROR: 4760 case MPI3_IOCSTATUS_SCSI_TASK_MGMT_FAILED: 4761 case MPI3_IOCSTATUS_INSUFFICIENT_POWER: 4762 case MPI3_IOCSTATUS_SCSI_RESIDUAL_MISMATCH: 4763 default: 4764 csio->resid = cm->length; 4765 mpi3mr_set_ccbstatus(ccb, CAM_REQ_CMP_ERR); 4766 break; 4767 } 4768 4769 out_success: 4770 if (mpi3mr_get_ccbstatus(ccb) != CAM_REQ_CMP) { 4771 ccb->ccb_h.status |= CAM_DEV_QFRZN; 4772 xpt_freeze_devq(ccb->ccb_h.path, /*count*/ 1); 4773 } 4774 4775 mpi3mr_atomic_dec(&cm->targ->outstanding); 4776 mpi3mr_cmd_done(sc, cm); 4777 mpi3mr_dprint(sc, MPI3MR_TRACE, "Completion IO path :" 4778 " cdb[0]: %x targetid: 0x%x SMID: %x ioc_status: 0x%x ioc_loginfo: 0x%x scsi_status: 0x%x " 4779 "scsi_state: 0x%x response_data: 0x%x\n", scsi_cdb[0], target_id, host_tag, 4780 ioc_status, ioc_loginfo, scsi_status, scsi_state, resp_data); 4781 mpi3mr_atomic_dec(&sc->fw_outstanding); 4782 out: 4783 4784 if (sense_buf) 4785 mpi3mr_repost_sense_buf(sc, 4786 scsi_reply->SenseDataBufferAddress); 4787 return; 4788 } 4789 4790 /* 4791 * mpi3mr_complete_io_cmd: ISR routine for IO commands 4792 * @sc: Adapter's soft instance 4793 * @irq_ctx: Driver's internal per IRQ structure 4794 * 4795 * This function processes IO command completions. 4796 */ 4797 int mpi3mr_complete_io_cmd(struct mpi3mr_softc *sc, 4798 struct mpi3mr_irq_context *irq_ctx) 4799 { 4800 struct mpi3mr_op_reply_queue *op_reply_q = irq_ctx->op_reply_q; 4801 U32 exp_phase = op_reply_q->ephase; 4802 U32 reply_ci = op_reply_q->ci; 4803 U32 num_op_replies = 0; 4804 U64 reply_dma = 0; 4805 Mpi3DefaultReplyDescriptor_t *reply_desc; 4806 U16 req_qid = 0; 4807 4808 mtx_lock_spin(&op_reply_q->q_lock); 4809 if (op_reply_q->in_use == false) { 4810 op_reply_q->in_use = true; 4811 mtx_unlock_spin(&op_reply_q->q_lock); 4812 } else { 4813 mtx_unlock_spin(&op_reply_q->q_lock); 4814 return 0; 4815 } 4816 4817 reply_desc = (Mpi3DefaultReplyDescriptor_t *)op_reply_q->q_base + reply_ci; 4818 mpi3mr_dprint(sc, MPI3MR_TRACE, "[QID:%d]:reply_desc: (%pa) reply_ci: %x" 4819 " reply_desc->ReplyFlags: 0x%x\n" 4820 "reply_q_base_phys: %#016jx reply_q_base: (%pa) exp_phase: %x\n", 4821 op_reply_q->qid, reply_desc, reply_ci, reply_desc->ReplyFlags, op_reply_q->q_base_phys, 4822 op_reply_q->q_base, exp_phase); 4823 4824 if (((reply_desc->ReplyFlags & 4825 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) || !op_reply_q->qid) { 4826 mtx_lock_spin(&op_reply_q->q_lock); 4827 op_reply_q->in_use = false; 4828 mtx_unlock_spin(&op_reply_q->q_lock); 4829 return 0; 4830 } 4831 4832 do { 4833 req_qid = reply_desc->RequestQueueID; 4834 sc->op_req_q[req_qid - 1].ci = 4835 reply_desc->RequestQueueCI; 4836 4837 mpi3mr_process_op_reply_desc(sc, reply_desc, &reply_dma); 4838 mpi3mr_atomic_dec(&op_reply_q->pend_ios); 4839 if (reply_dma) 4840 mpi3mr_repost_reply_buf(sc, reply_dma); 4841 num_op_replies++; 4842 if (++reply_ci == op_reply_q->num_replies) { 4843 reply_ci = 0; 4844 exp_phase ^= 1; 4845 } 4846 reply_desc = 4847 (Mpi3DefaultReplyDescriptor_t *)op_reply_q->q_base + reply_ci; 4848 if ((reply_desc->ReplyFlags & 4849 MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK) != exp_phase) 4850 break; 4851 } while (1); 4852 4853 4854 mpi3mr_regwrite(sc, MPI3_SYSIF_OPER_REPLY_Q_N_CI_OFFSET(op_reply_q->qid), reply_ci); 4855 op_reply_q->ci = reply_ci; 4856 op_reply_q->ephase = exp_phase; 4857 mtx_lock_spin(&op_reply_q->q_lock); 4858 op_reply_q->in_use = false; 4859 mtx_unlock_spin(&op_reply_q->q_lock); 4860 return num_op_replies; 4861 } 4862 4863 /* 4864 * mpi3mr_isr: Primary ISR function 4865 * privdata: Driver's internal per IRQ structure 4866 * 4867 * This is driver's primary ISR function which is being called whenever any admin/IO 4868 * command completion. 4869 */ 4870 void mpi3mr_isr(void *privdata) 4871 { 4872 struct mpi3mr_irq_context *irq_ctx = (struct mpi3mr_irq_context *)privdata; 4873 struct mpi3mr_softc *sc = irq_ctx->sc; 4874 U16 msi_idx; 4875 4876 if (!irq_ctx) 4877 return; 4878 4879 msi_idx = irq_ctx->msix_index; 4880 4881 if (!sc->intr_enabled) 4882 return; 4883 4884 if (!msi_idx) 4885 mpi3mr_complete_admin_cmd(sc); 4886 4887 if (irq_ctx->op_reply_q && irq_ctx->op_reply_q->qid) { 4888 mpi3mr_complete_io_cmd(sc, irq_ctx); 4889 } 4890 } 4891 4892 /* 4893 * mpi3mr_alloc_requests - Allocates host commands 4894 * @sc: Adapter reference 4895 * 4896 * This function allocates controller supported host commands 4897 * 4898 * Return: 0 on success and proper error codes on failure 4899 */ 4900 int 4901 mpi3mr_alloc_requests(struct mpi3mr_softc *sc) 4902 { 4903 struct mpi3mr_cmd *cmd; 4904 int i, j, nsegs, ret; 4905 4906 nsegs = MPI3MR_SG_DEPTH; 4907 ret = bus_dma_tag_create( sc->mpi3mr_parent_dmat, /* parent */ 4908 1, 0, /* algnmnt, boundary */ 4909 BUS_SPACE_MAXADDR, /* lowaddr */ 4910 BUS_SPACE_MAXADDR, /* highaddr */ 4911 NULL, NULL, /* filter, filterarg */ 4912 MAXPHYS,/* maxsize */ 4913 nsegs, /* nsegments */ 4914 MAXPHYS,/* maxsegsize */ 4915 BUS_DMA_ALLOCNOW, /* flags */ 4916 busdma_lock_mutex, /* lockfunc */ 4917 &sc->io_lock, /* lockarg */ 4918 &sc->buffer_dmat); 4919 if (ret) { 4920 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate buffer DMA tag ret: %d\n", ret); 4921 return (ENOMEM); 4922 } 4923 4924 /* 4925 * sc->cmd_list is an array of struct mpi3mr_cmd pointers. 4926 * Allocate the dynamic array first and then allocate individual 4927 * commands. 4928 */ 4929 sc->cmd_list = malloc(sizeof(struct mpi3mr_cmd *) * sc->max_host_ios, 4930 M_MPI3MR, M_NOWAIT | M_ZERO); 4931 4932 if (!sc->cmd_list) { 4933 device_printf(sc->mpi3mr_dev, "Cannot alloc memory for mpt_cmd_list.\n"); 4934 return (ENOMEM); 4935 } 4936 4937 for (i = 0; i < sc->max_host_ios; i++) { 4938 sc->cmd_list[i] = malloc(sizeof(struct mpi3mr_cmd), 4939 M_MPI3MR, M_NOWAIT | M_ZERO); 4940 if (!sc->cmd_list[i]) { 4941 for (j = 0; j < i; j++) 4942 free(sc->cmd_list[j], M_MPI3MR); 4943 free(sc->cmd_list, M_MPI3MR); 4944 sc->cmd_list = NULL; 4945 return (ENOMEM); 4946 } 4947 } 4948 4949 for (i = 1; i < sc->max_host_ios; i++) { 4950 cmd = sc->cmd_list[i]; 4951 cmd->hosttag = i; 4952 cmd->sc = sc; 4953 cmd->state = MPI3MR_CMD_STATE_BUSY; 4954 callout_init_mtx(&cmd->callout, &sc->mpi3mr_mtx, 0); 4955 cmd->ccb = NULL; 4956 TAILQ_INSERT_TAIL(&(sc->cmd_list_head), cmd, next); 4957 if (bus_dmamap_create(sc->buffer_dmat, 0, &cmd->dmamap)) 4958 return ENOMEM; 4959 } 4960 return (0); 4961 } 4962 4963 /* 4964 * mpi3mr_get_command: Get a coomand structure from free command pool 4965 * @sc: Adapter soft instance 4966 * Return: MPT command reference 4967 * 4968 * This function returns an MPT command to the caller. 4969 */ 4970 struct mpi3mr_cmd * 4971 mpi3mr_get_command(struct mpi3mr_softc *sc) 4972 { 4973 struct mpi3mr_cmd *cmd = NULL; 4974 4975 mtx_lock(&sc->cmd_pool_lock); 4976 if (!TAILQ_EMPTY(&sc->cmd_list_head)) { 4977 cmd = TAILQ_FIRST(&sc->cmd_list_head); 4978 TAILQ_REMOVE(&sc->cmd_list_head, cmd, next); 4979 } else { 4980 goto out; 4981 } 4982 4983 mpi3mr_dprint(sc, MPI3MR_TRACE, "Get command SMID: 0x%x\n", cmd->hosttag); 4984 4985 memset((uint8_t *)&cmd->io_request, 0, MPI3MR_AREQ_FRAME_SZ); 4986 cmd->data_dir = 0; 4987 cmd->ccb = NULL; 4988 cmd->targ = NULL; 4989 cmd->max_segs = 0; 4990 cmd->lun = 0; 4991 cmd->state = MPI3MR_CMD_STATE_BUSY; 4992 cmd->data = NULL; 4993 cmd->length = 0; 4994 cmd->out_len = 0; 4995 out: 4996 mtx_unlock(&sc->cmd_pool_lock); 4997 return cmd; 4998 } 4999 5000 /* 5001 * mpi3mr_release_command: Return a cmd to free command pool 5002 * input: Command packet for return to free command pool 5003 * 5004 * This function returns an MPT command to the free command list. 5005 */ 5006 void 5007 mpi3mr_release_command(struct mpi3mr_cmd *cmd) 5008 { 5009 struct mpi3mr_softc *sc = cmd->sc; 5010 5011 mtx_lock(&sc->cmd_pool_lock); 5012 TAILQ_INSERT_HEAD(&(sc->cmd_list_head), cmd, next); 5013 cmd->state = MPI3MR_CMD_STATE_FREE; 5014 cmd->req_qidx = 0; 5015 mpi3mr_dprint(sc, MPI3MR_TRACE, "Release command SMID: 0x%x\n", cmd->hosttag); 5016 mtx_unlock(&sc->cmd_pool_lock); 5017 5018 return; 5019 } 5020 5021 /** 5022 * mpi3mr_free_ioctl_dma_memory - free memory for ioctl dma 5023 * @sc: Adapter instance reference 5024 * 5025 * Free the DMA memory allocated for IOCTL handling purpose. 5026 * 5027 * Return: None 5028 */ 5029 static void mpi3mr_free_ioctl_dma_memory(struct mpi3mr_softc *sc) 5030 { 5031 U16 i; 5032 struct dma_memory_desc *mem_desc; 5033 5034 for (i=0; i<MPI3MR_NUM_IOCTL_SGE; i++) { 5035 mem_desc = &sc->ioctl_sge[i]; 5036 if (mem_desc->addr && mem_desc->dma_addr) { 5037 bus_dmamap_unload(mem_desc->tag, mem_desc->dmamap); 5038 bus_dmamem_free(mem_desc->tag, mem_desc->addr, mem_desc->dmamap); 5039 mem_desc->addr = NULL; 5040 if (mem_desc->tag != NULL) 5041 bus_dma_tag_destroy(mem_desc->tag); 5042 } 5043 } 5044 5045 mem_desc = &sc->ioctl_chain_sge; 5046 if (mem_desc->addr && mem_desc->dma_addr) { 5047 bus_dmamap_unload(mem_desc->tag, mem_desc->dmamap); 5048 bus_dmamem_free(mem_desc->tag, mem_desc->addr, mem_desc->dmamap); 5049 mem_desc->addr = NULL; 5050 if (mem_desc->tag != NULL) 5051 bus_dma_tag_destroy(mem_desc->tag); 5052 } 5053 5054 mem_desc = &sc->ioctl_resp_sge; 5055 if (mem_desc->addr && mem_desc->dma_addr) { 5056 bus_dmamap_unload(mem_desc->tag, mem_desc->dmamap); 5057 bus_dmamem_free(mem_desc->tag, mem_desc->addr, mem_desc->dmamap); 5058 mem_desc->addr = NULL; 5059 if (mem_desc->tag != NULL) 5060 bus_dma_tag_destroy(mem_desc->tag); 5061 } 5062 5063 sc->ioctl_sges_allocated = false; 5064 } 5065 5066 /** 5067 * mpi3mr_alloc_ioctl_dma_memory - Alloc memory for ioctl dma 5068 * @sc: Adapter instance reference 5069 * 5070 * This function allocates dmaable memory required to handle the 5071 * application issued MPI3 IOCTL requests. 5072 * 5073 * Return: None 5074 */ 5075 void mpi3mr_alloc_ioctl_dma_memory(struct mpi3mr_softc *sc) 5076 { 5077 struct dma_memory_desc *mem_desc; 5078 U16 i; 5079 5080 for (i=0; i<MPI3MR_NUM_IOCTL_SGE; i++) { 5081 mem_desc = &sc->ioctl_sge[i]; 5082 mem_desc->size = MPI3MR_IOCTL_SGE_SIZE; 5083 5084 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 5085 4, 0, /* algnmnt, boundary */ 5086 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 5087 BUS_SPACE_MAXADDR, /* highaddr */ 5088 NULL, NULL, /* filter, filterarg */ 5089 mem_desc->size, /* maxsize */ 5090 1, /* nsegments */ 5091 mem_desc->size, /* maxsegsize */ 5092 0, /* flags */ 5093 NULL, NULL, /* lockfunc, lockarg */ 5094 &mem_desc->tag)) { 5095 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate request DMA tag\n"); 5096 goto out_failed; 5097 } 5098 5099 if (bus_dmamem_alloc(mem_desc->tag, (void **)&mem_desc->addr, 5100 BUS_DMA_NOWAIT, &mem_desc->dmamap)) { 5101 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate replies memory\n"); 5102 goto out_failed; 5103 } 5104 bzero(mem_desc->addr, mem_desc->size); 5105 bus_dmamap_load(mem_desc->tag, mem_desc->dmamap, mem_desc->addr, mem_desc->size, 5106 mpi3mr_memaddr_cb, &mem_desc->dma_addr, 0); 5107 5108 if (!mem_desc->addr) 5109 goto out_failed; 5110 } 5111 5112 mem_desc = &sc->ioctl_chain_sge; 5113 mem_desc->size = MPI3MR_4K_PGSZ; 5114 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 5115 4, 0, /* algnmnt, boundary */ 5116 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 5117 BUS_SPACE_MAXADDR, /* highaddr */ 5118 NULL, NULL, /* filter, filterarg */ 5119 mem_desc->size, /* maxsize */ 5120 1, /* nsegments */ 5121 mem_desc->size, /* maxsegsize */ 5122 0, /* flags */ 5123 NULL, NULL, /* lockfunc, lockarg */ 5124 &mem_desc->tag)) { 5125 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate request DMA tag\n"); 5126 goto out_failed; 5127 } 5128 5129 if (bus_dmamem_alloc(mem_desc->tag, (void **)&mem_desc->addr, 5130 BUS_DMA_NOWAIT, &mem_desc->dmamap)) { 5131 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate replies memory\n"); 5132 goto out_failed; 5133 } 5134 bzero(mem_desc->addr, mem_desc->size); 5135 bus_dmamap_load(mem_desc->tag, mem_desc->dmamap, mem_desc->addr, mem_desc->size, 5136 mpi3mr_memaddr_cb, &mem_desc->dma_addr, 0); 5137 5138 if (!mem_desc->addr) 5139 goto out_failed; 5140 5141 mem_desc = &sc->ioctl_resp_sge; 5142 mem_desc->size = MPI3MR_4K_PGSZ; 5143 if (bus_dma_tag_create(sc->mpi3mr_parent_dmat, /* parent */ 5144 4, 0, /* algnmnt, boundary */ 5145 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 5146 BUS_SPACE_MAXADDR, /* highaddr */ 5147 NULL, NULL, /* filter, filterarg */ 5148 mem_desc->size, /* maxsize */ 5149 1, /* nsegments */ 5150 mem_desc->size, /* maxsegsize */ 5151 0, /* flags */ 5152 NULL, NULL, /* lockfunc, lockarg */ 5153 &mem_desc->tag)) { 5154 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate request DMA tag\n"); 5155 goto out_failed; 5156 } 5157 5158 if (bus_dmamem_alloc(mem_desc->tag, (void **)&mem_desc->addr, 5159 BUS_DMA_NOWAIT, &mem_desc->dmamap)) { 5160 mpi3mr_dprint(sc, MPI3MR_ERROR, "Cannot allocate replies memory\n"); 5161 goto out_failed; 5162 } 5163 bzero(mem_desc->addr, mem_desc->size); 5164 bus_dmamap_load(mem_desc->tag, mem_desc->dmamap, mem_desc->addr, mem_desc->size, 5165 mpi3mr_memaddr_cb, &mem_desc->dma_addr, 0); 5166 5167 if (!mem_desc->addr) 5168 goto out_failed; 5169 5170 sc->ioctl_sges_allocated = true; 5171 5172 return; 5173 out_failed: 5174 printf("cannot allocate DMA memory for the mpt commands" 5175 " from the applications, application interface for MPT command is disabled\n"); 5176 mpi3mr_free_ioctl_dma_memory(sc); 5177 } 5178 5179 void 5180 mpi3mr_destory_mtx(struct mpi3mr_softc *sc) 5181 { 5182 int i; 5183 struct mpi3mr_op_req_queue *op_req_q; 5184 struct mpi3mr_op_reply_queue *op_reply_q; 5185 5186 if (sc->admin_reply) { 5187 if (mtx_initialized(&sc->admin_reply_lock)) 5188 mtx_destroy(&sc->admin_reply_lock); 5189 } 5190 5191 if (sc->op_reply_q) { 5192 for(i = 0; i < sc->num_queues; i++) { 5193 op_reply_q = sc->op_reply_q + i; 5194 if (mtx_initialized(&op_reply_q->q_lock)) 5195 mtx_destroy(&op_reply_q->q_lock); 5196 } 5197 } 5198 5199 if (sc->op_req_q) { 5200 for(i = 0; i < sc->num_queues; i++) { 5201 op_req_q = sc->op_req_q + i; 5202 if (mtx_initialized(&op_req_q->q_lock)) 5203 mtx_destroy(&op_req_q->q_lock); 5204 } 5205 } 5206 5207 if (mtx_initialized(&sc->init_cmds.completion.lock)) 5208 mtx_destroy(&sc->init_cmds.completion.lock); 5209 5210 if (mtx_initialized(&sc->ioctl_cmds.completion.lock)) 5211 mtx_destroy(&sc->ioctl_cmds.completion.lock); 5212 5213 if (mtx_initialized(&sc->host_tm_cmds.completion.lock)) 5214 mtx_destroy(&sc->host_tm_cmds.completion.lock); 5215 5216 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 5217 if (mtx_initialized(&sc->dev_rmhs_cmds[i].completion.lock)) 5218 mtx_destroy(&sc->dev_rmhs_cmds[i].completion.lock); 5219 } 5220 5221 if (mtx_initialized(&sc->reset_mutex)) 5222 mtx_destroy(&sc->reset_mutex); 5223 5224 if (mtx_initialized(&sc->target_lock)) 5225 mtx_destroy(&sc->target_lock); 5226 5227 if (mtx_initialized(&sc->fwevt_lock)) 5228 mtx_destroy(&sc->fwevt_lock); 5229 5230 if (mtx_initialized(&sc->cmd_pool_lock)) 5231 mtx_destroy(&sc->cmd_pool_lock); 5232 5233 if (mtx_initialized(&sc->reply_free_q_lock)) 5234 mtx_destroy(&sc->reply_free_q_lock); 5235 5236 if (mtx_initialized(&sc->sense_buf_q_lock)) 5237 mtx_destroy(&sc->sense_buf_q_lock); 5238 5239 if (mtx_initialized(&sc->chain_buf_lock)) 5240 mtx_destroy(&sc->chain_buf_lock); 5241 5242 if (mtx_initialized(&sc->admin_req_lock)) 5243 mtx_destroy(&sc->admin_req_lock); 5244 5245 if (mtx_initialized(&sc->mpi3mr_mtx)) 5246 mtx_destroy(&sc->mpi3mr_mtx); 5247 } 5248 5249 /** 5250 * mpi3mr_free_mem - Freeup adapter level data structures 5251 * @sc: Adapter reference 5252 * 5253 * Return: Nothing. 5254 */ 5255 void 5256 mpi3mr_free_mem(struct mpi3mr_softc *sc) 5257 { 5258 int i; 5259 struct mpi3mr_op_req_queue *op_req_q; 5260 struct mpi3mr_op_reply_queue *op_reply_q; 5261 struct mpi3mr_irq_context *irq_ctx; 5262 5263 if (sc->cmd_list) { 5264 for (i = 0; i < sc->max_host_ios; i++) { 5265 free(sc->cmd_list[i], M_MPI3MR); 5266 } 5267 free(sc->cmd_list, M_MPI3MR); 5268 sc->cmd_list = NULL; 5269 } 5270 5271 if (sc->pel_seq_number && sc->pel_seq_number_dma) { 5272 bus_dmamap_unload(sc->pel_seq_num_dmatag, sc->pel_seq_num_dmamap); 5273 bus_dmamem_free(sc->pel_seq_num_dmatag, sc->pel_seq_number, sc->pel_seq_num_dmamap); 5274 sc->pel_seq_number = NULL; 5275 if (sc->pel_seq_num_dmatag != NULL) 5276 bus_dma_tag_destroy(sc->pel_seq_num_dmatag); 5277 } 5278 5279 if (sc->throttle_groups) { 5280 free(sc->throttle_groups, M_MPI3MR); 5281 sc->throttle_groups = NULL; 5282 } 5283 5284 /* Free up operational queues*/ 5285 if (sc->op_req_q) { 5286 for (i = 0; i < sc->num_queues; i++) { 5287 op_req_q = sc->op_req_q + i; 5288 if (op_req_q->q_base && op_req_q->q_base_phys) { 5289 bus_dmamap_unload(op_req_q->q_base_tag, op_req_q->q_base_dmamap); 5290 bus_dmamem_free(op_req_q->q_base_tag, op_req_q->q_base, op_req_q->q_base_dmamap); 5291 op_req_q->q_base = NULL; 5292 if (op_req_q->q_base_tag != NULL) 5293 bus_dma_tag_destroy(op_req_q->q_base_tag); 5294 } 5295 } 5296 free(sc->op_req_q, M_MPI3MR); 5297 sc->op_req_q = NULL; 5298 } 5299 5300 if (sc->op_reply_q) { 5301 for (i = 0; i < sc->num_queues; i++) { 5302 op_reply_q = sc->op_reply_q + i; 5303 if (op_reply_q->q_base && op_reply_q->q_base_phys) { 5304 bus_dmamap_unload(op_reply_q->q_base_tag, op_reply_q->q_base_dmamap); 5305 bus_dmamem_free(op_reply_q->q_base_tag, op_reply_q->q_base, op_reply_q->q_base_dmamap); 5306 op_reply_q->q_base = NULL; 5307 if (op_reply_q->q_base_tag != NULL) 5308 bus_dma_tag_destroy(op_reply_q->q_base_tag); 5309 } 5310 } 5311 free(sc->op_reply_q, M_MPI3MR); 5312 sc->op_reply_q = NULL; 5313 } 5314 5315 /* Free up chain buffers*/ 5316 if (sc->chain_sgl_list) { 5317 for (i = 0; i < sc->chain_buf_count; i++) { 5318 if (sc->chain_sgl_list[i].buf && sc->chain_sgl_list[i].buf_phys) { 5319 bus_dmamap_unload(sc->chain_sgl_list_tag, sc->chain_sgl_list[i].buf_dmamap); 5320 bus_dmamem_free(sc->chain_sgl_list_tag, sc->chain_sgl_list[i].buf, 5321 sc->chain_sgl_list[i].buf_dmamap); 5322 sc->chain_sgl_list[i].buf = NULL; 5323 } 5324 } 5325 if (sc->chain_sgl_list_tag != NULL) 5326 bus_dma_tag_destroy(sc->chain_sgl_list_tag); 5327 free(sc->chain_sgl_list, M_MPI3MR); 5328 sc->chain_sgl_list = NULL; 5329 } 5330 5331 if (sc->chain_bitmap) { 5332 free(sc->chain_bitmap, M_MPI3MR); 5333 sc->chain_bitmap = NULL; 5334 } 5335 5336 for (i = 0; i < sc->msix_count; i++) { 5337 irq_ctx = sc->irq_ctx + i; 5338 if (irq_ctx) 5339 irq_ctx->op_reply_q = NULL; 5340 } 5341 5342 /* Free reply_buf_tag */ 5343 if (sc->reply_buf && sc->reply_buf_phys) { 5344 bus_dmamap_unload(sc->reply_buf_tag, sc->reply_buf_dmamap); 5345 bus_dmamem_free(sc->reply_buf_tag, sc->reply_buf, 5346 sc->reply_buf_dmamap); 5347 sc->reply_buf = NULL; 5348 if (sc->reply_buf_tag != NULL) 5349 bus_dma_tag_destroy(sc->reply_buf_tag); 5350 } 5351 5352 /* Free reply_free_q_tag */ 5353 if (sc->reply_free_q && sc->reply_free_q_phys) { 5354 bus_dmamap_unload(sc->reply_free_q_tag, sc->reply_free_q_dmamap); 5355 bus_dmamem_free(sc->reply_free_q_tag, sc->reply_free_q, 5356 sc->reply_free_q_dmamap); 5357 sc->reply_free_q = NULL; 5358 if (sc->reply_free_q_tag != NULL) 5359 bus_dma_tag_destroy(sc->reply_free_q_tag); 5360 } 5361 5362 /* Free sense_buf_tag */ 5363 if (sc->sense_buf && sc->sense_buf_phys) { 5364 bus_dmamap_unload(sc->sense_buf_tag, sc->sense_buf_dmamap); 5365 bus_dmamem_free(sc->sense_buf_tag, sc->sense_buf, 5366 sc->sense_buf_dmamap); 5367 sc->sense_buf = NULL; 5368 if (sc->sense_buf_tag != NULL) 5369 bus_dma_tag_destroy(sc->sense_buf_tag); 5370 } 5371 5372 /* Free sense_buf_q_tag */ 5373 if (sc->sense_buf_q && sc->sense_buf_q_phys) { 5374 bus_dmamap_unload(sc->sense_buf_q_tag, sc->sense_buf_q_dmamap); 5375 bus_dmamem_free(sc->sense_buf_q_tag, sc->sense_buf_q, 5376 sc->sense_buf_q_dmamap); 5377 sc->sense_buf_q = NULL; 5378 if (sc->sense_buf_q_tag != NULL) 5379 bus_dma_tag_destroy(sc->sense_buf_q_tag); 5380 } 5381 5382 /* Free up internal(non-IO) commands*/ 5383 if (sc->init_cmds.reply) { 5384 free(sc->init_cmds.reply, M_MPI3MR); 5385 sc->init_cmds.reply = NULL; 5386 } 5387 5388 if (sc->ioctl_cmds.reply) { 5389 free(sc->ioctl_cmds.reply, M_MPI3MR); 5390 sc->ioctl_cmds.reply = NULL; 5391 } 5392 5393 if (sc->pel_cmds.reply) { 5394 free(sc->pel_cmds.reply, M_MPI3MR); 5395 sc->pel_cmds.reply = NULL; 5396 } 5397 5398 if (sc->pel_abort_cmd.reply) { 5399 free(sc->pel_abort_cmd.reply, M_MPI3MR); 5400 sc->pel_abort_cmd.reply = NULL; 5401 } 5402 5403 if (sc->host_tm_cmds.reply) { 5404 free(sc->host_tm_cmds.reply, M_MPI3MR); 5405 sc->host_tm_cmds.reply = NULL; 5406 } 5407 5408 if (sc->log_data_buffer) { 5409 free(sc->log_data_buffer, M_MPI3MR); 5410 sc->log_data_buffer = NULL; 5411 } 5412 5413 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 5414 if (sc->dev_rmhs_cmds[i].reply) { 5415 free(sc->dev_rmhs_cmds[i].reply, M_MPI3MR); 5416 sc->dev_rmhs_cmds[i].reply = NULL; 5417 } 5418 } 5419 5420 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 5421 if (sc->evtack_cmds[i].reply) { 5422 free(sc->evtack_cmds[i].reply, M_MPI3MR); 5423 sc->evtack_cmds[i].reply = NULL; 5424 } 5425 } 5426 5427 if (sc->removepend_bitmap) { 5428 free(sc->removepend_bitmap, M_MPI3MR); 5429 sc->removepend_bitmap = NULL; 5430 } 5431 5432 if (sc->devrem_bitmap) { 5433 free(sc->devrem_bitmap, M_MPI3MR); 5434 sc->devrem_bitmap = NULL; 5435 } 5436 5437 if (sc->evtack_cmds_bitmap) { 5438 free(sc->evtack_cmds_bitmap, M_MPI3MR); 5439 sc->evtack_cmds_bitmap = NULL; 5440 } 5441 5442 /* Free Admin reply*/ 5443 if (sc->admin_reply && sc->admin_reply_phys) { 5444 bus_dmamap_unload(sc->admin_reply_tag, sc->admin_reply_dmamap); 5445 bus_dmamem_free(sc->admin_reply_tag, sc->admin_reply, 5446 sc->admin_reply_dmamap); 5447 sc->admin_reply = NULL; 5448 if (sc->admin_reply_tag != NULL) 5449 bus_dma_tag_destroy(sc->admin_reply_tag); 5450 } 5451 5452 /* Free Admin request*/ 5453 if (sc->admin_req && sc->admin_req_phys) { 5454 bus_dmamap_unload(sc->admin_req_tag, sc->admin_req_dmamap); 5455 bus_dmamem_free(sc->admin_req_tag, sc->admin_req, 5456 sc->admin_req_dmamap); 5457 sc->admin_req = NULL; 5458 if (sc->admin_req_tag != NULL) 5459 bus_dma_tag_destroy(sc->admin_req_tag); 5460 } 5461 mpi3mr_free_ioctl_dma_memory(sc); 5462 5463 } 5464 5465 /** 5466 * mpi3mr_drv_cmd_comp_reset - Flush a internal driver command 5467 * @sc: Adapter instance reference 5468 * @cmdptr: Internal command tracker 5469 * 5470 * Complete an internal driver commands with state indicating it 5471 * is completed due to reset. 5472 * 5473 * Return: Nothing. 5474 */ 5475 static inline void mpi3mr_drv_cmd_comp_reset(struct mpi3mr_softc *sc, 5476 struct mpi3mr_drvr_cmd *cmdptr) 5477 { 5478 if (cmdptr->state & MPI3MR_CMD_PENDING) { 5479 cmdptr->state |= MPI3MR_CMD_RESET; 5480 cmdptr->state &= ~MPI3MR_CMD_PENDING; 5481 if (cmdptr->is_waiting) { 5482 complete(&cmdptr->completion); 5483 cmdptr->is_waiting = 0; 5484 } else if (cmdptr->callback) 5485 cmdptr->callback(sc, cmdptr); 5486 } 5487 } 5488 5489 /** 5490 * mpi3mr_flush_drv_cmds - Flush internal driver commands 5491 * @sc: Adapter instance reference 5492 * 5493 * Flush all internal driver commands post reset 5494 * 5495 * Return: Nothing. 5496 */ 5497 static void mpi3mr_flush_drv_cmds(struct mpi3mr_softc *sc) 5498 { 5499 int i = 0; 5500 struct mpi3mr_drvr_cmd *cmdptr; 5501 5502 cmdptr = &sc->init_cmds; 5503 mpi3mr_drv_cmd_comp_reset(sc, cmdptr); 5504 5505 cmdptr = &sc->ioctl_cmds; 5506 mpi3mr_drv_cmd_comp_reset(sc, cmdptr); 5507 5508 cmdptr = &sc->host_tm_cmds; 5509 mpi3mr_drv_cmd_comp_reset(sc, cmdptr); 5510 5511 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) { 5512 cmdptr = &sc->dev_rmhs_cmds[i]; 5513 mpi3mr_drv_cmd_comp_reset(sc, cmdptr); 5514 } 5515 5516 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) { 5517 cmdptr = &sc->evtack_cmds[i]; 5518 mpi3mr_drv_cmd_comp_reset(sc, cmdptr); 5519 } 5520 5521 cmdptr = &sc->pel_cmds; 5522 mpi3mr_drv_cmd_comp_reset(sc, cmdptr); 5523 5524 cmdptr = &sc->pel_abort_cmd; 5525 mpi3mr_drv_cmd_comp_reset(sc, cmdptr); 5526 } 5527 5528 5529 /** 5530 * mpi3mr_memset_buffers - memset memory for a controller 5531 * @sc: Adapter instance reference 5532 * 5533 * clear all the memory allocated for a controller, typically 5534 * called post reset to reuse the memory allocated during the 5535 * controller init. 5536 * 5537 * Return: Nothing. 5538 */ 5539 static void mpi3mr_memset_buffers(struct mpi3mr_softc *sc) 5540 { 5541 U16 i; 5542 struct mpi3mr_throttle_group_info *tg; 5543 5544 memset(sc->admin_req, 0, sc->admin_req_q_sz); 5545 memset(sc->admin_reply, 0, sc->admin_reply_q_sz); 5546 5547 memset(sc->init_cmds.reply, 0, sc->reply_sz); 5548 memset(sc->ioctl_cmds.reply, 0, sc->reply_sz); 5549 memset(sc->host_tm_cmds.reply, 0, sc->reply_sz); 5550 memset(sc->pel_cmds.reply, 0, sc->reply_sz); 5551 memset(sc->pel_abort_cmd.reply, 0, sc->reply_sz); 5552 for (i = 0; i < MPI3MR_NUM_DEVRMCMD; i++) 5553 memset(sc->dev_rmhs_cmds[i].reply, 0, sc->reply_sz); 5554 for (i = 0; i < MPI3MR_NUM_EVTACKCMD; i++) 5555 memset(sc->evtack_cmds[i].reply, 0, sc->reply_sz); 5556 memset(sc->removepend_bitmap, 0, sc->dev_handle_bitmap_sz); 5557 memset(sc->devrem_bitmap, 0, sc->devrem_bitmap_sz); 5558 memset(sc->evtack_cmds_bitmap, 0, sc->evtack_cmds_bitmap_sz); 5559 5560 for (i = 0; i < sc->num_queues; i++) { 5561 sc->op_reply_q[i].qid = 0; 5562 sc->op_reply_q[i].ci = 0; 5563 sc->op_reply_q[i].num_replies = 0; 5564 sc->op_reply_q[i].ephase = 0; 5565 mpi3mr_atomic_set(&sc->op_reply_q[i].pend_ios, 0); 5566 memset(sc->op_reply_q[i].q_base, 0, sc->op_reply_q[i].qsz); 5567 5568 sc->op_req_q[i].ci = 0; 5569 sc->op_req_q[i].pi = 0; 5570 sc->op_req_q[i].num_reqs = 0; 5571 sc->op_req_q[i].qid = 0; 5572 sc->op_req_q[i].reply_qid = 0; 5573 memset(sc->op_req_q[i].q_base, 0, sc->op_req_q[i].qsz); 5574 } 5575 5576 mpi3mr_atomic_set(&sc->pend_large_data_sz, 0); 5577 if (sc->throttle_groups) { 5578 tg = sc->throttle_groups; 5579 for (i = 0; i < sc->num_io_throttle_group; i++, tg++) { 5580 tg->id = 0; 5581 tg->fw_qd = 0; 5582 tg->modified_qd = 0; 5583 tg->io_divert= 0; 5584 tg->high = 0; 5585 tg->low = 0; 5586 mpi3mr_atomic_set(&tg->pend_large_data_sz, 0); 5587 } 5588 } 5589 } 5590 5591 /** 5592 * mpi3mr_invalidate_devhandles -Invalidate device handles 5593 * @sc: Adapter instance reference 5594 * 5595 * Invalidate the device handles in the target device structures 5596 * . Called post reset prior to reinitializing the controller. 5597 * 5598 * Return: Nothing. 5599 */ 5600 static void mpi3mr_invalidate_devhandles(struct mpi3mr_softc *sc) 5601 { 5602 struct mpi3mr_target *target = NULL; 5603 5604 mtx_lock_spin(&sc->target_lock); 5605 TAILQ_FOREACH(target, &sc->cam_sc->tgt_list, tgt_next) { 5606 if (target) { 5607 target->dev_handle = MPI3MR_INVALID_DEV_HANDLE; 5608 target->io_throttle_enabled = 0; 5609 target->io_divert = 0; 5610 target->throttle_group = NULL; 5611 } 5612 } 5613 mtx_unlock_spin(&sc->target_lock); 5614 } 5615 5616 /** 5617 * mpi3mr_rfresh_tgtdevs - Refresh target device exposure 5618 * @sc: Adapter instance reference 5619 * 5620 * This is executed post controller reset to identify any 5621 * missing devices during reset and remove from the upper layers 5622 * or expose any newly detected device to the upper layers. 5623 * 5624 * Return: Nothing. 5625 */ 5626 5627 static void mpi3mr_rfresh_tgtdevs(struct mpi3mr_softc *sc) 5628 { 5629 struct mpi3mr_target *target = NULL; 5630 struct mpi3mr_target *target_temp = NULL; 5631 5632 TAILQ_FOREACH_SAFE(target, &sc->cam_sc->tgt_list, tgt_next, target_temp) { 5633 if (target->dev_handle == MPI3MR_INVALID_DEV_HANDLE) { 5634 if (target->exposed_to_os) 5635 mpi3mr_remove_device_from_os(sc, target->dev_handle); 5636 mpi3mr_remove_device_from_list(sc, target, true); 5637 } 5638 } 5639 5640 TAILQ_FOREACH(target, &sc->cam_sc->tgt_list, tgt_next) { 5641 if ((target->dev_handle != MPI3MR_INVALID_DEV_HANDLE) && 5642 !target->is_hidden && !target->exposed_to_os) { 5643 mpi3mr_add_device(sc, target->per_id); 5644 } 5645 } 5646 5647 } 5648 5649 static void mpi3mr_flush_io(struct mpi3mr_softc *sc) 5650 { 5651 int i; 5652 struct mpi3mr_cmd *cmd = NULL; 5653 union ccb *ccb = NULL; 5654 5655 for (i = 0; i < sc->max_host_ios; i++) { 5656 cmd = sc->cmd_list[i]; 5657 5658 if (cmd && cmd->ccb) { 5659 if (cmd->callout_owner) { 5660 ccb = (union ccb *)(cmd->ccb); 5661 ccb->ccb_h.status = CAM_SCSI_BUS_RESET; 5662 mpi3mr_cmd_done(sc, cmd); 5663 } else { 5664 cmd->ccb = NULL; 5665 mpi3mr_release_command(cmd); 5666 } 5667 } 5668 } 5669 } 5670 /** 5671 * mpi3mr_clear_reset_history - Clear reset history 5672 * @sc: Adapter instance reference 5673 * 5674 * Write the reset history bit in IOC Status to clear the bit, 5675 * if it is already set. 5676 * 5677 * Return: Nothing. 5678 */ 5679 static inline void mpi3mr_clear_reset_history(struct mpi3mr_softc *sc) 5680 { 5681 U32 ioc_status; 5682 5683 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 5684 if (ioc_status & MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) 5685 mpi3mr_regwrite(sc, MPI3_SYSIF_IOC_STATUS_OFFSET, ioc_status); 5686 } 5687 5688 /** 5689 * mpi3mr_set_diagsave - Set diag save bit for snapdump 5690 * @sc: Adapter reference 5691 * 5692 * Set diag save bit in IOC configuration register to enable 5693 * snapdump. 5694 * 5695 * Return: Nothing. 5696 */ 5697 static inline void mpi3mr_set_diagsave(struct mpi3mr_softc *sc) 5698 { 5699 U32 ioc_config; 5700 5701 ioc_config = 5702 mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 5703 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE; 5704 mpi3mr_regwrite(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET, ioc_config); 5705 } 5706 5707 /** 5708 * mpi3mr_issue_reset - Issue reset to the controller 5709 * @sc: Adapter reference 5710 * @reset_type: Reset type 5711 * @reset_reason: Reset reason code 5712 * 5713 * Unlock the host diagnostic registers and write the specific 5714 * reset type to that, wait for reset acknowledgement from the 5715 * controller, if the reset is not successful retry for the 5716 * predefined number of times. 5717 * 5718 * Return: 0 on success, non-zero on failure. 5719 */ 5720 static int mpi3mr_issue_reset(struct mpi3mr_softc *sc, U16 reset_type, 5721 U32 reset_reason) 5722 { 5723 int retval = -1; 5724 U8 unlock_retry_count = 0; 5725 U32 host_diagnostic, ioc_status, ioc_config; 5726 U32 timeout = MPI3MR_RESET_ACK_TIMEOUT * 10; 5727 5728 if ((reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) && 5729 (reset_type != MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT)) 5730 return retval; 5731 if (sc->unrecoverable) 5732 return retval; 5733 5734 if (reset_reason == MPI3MR_RESET_FROM_FIRMWARE) { 5735 retval = 0; 5736 return retval; 5737 } 5738 5739 mpi3mr_dprint(sc, MPI3MR_INFO, "%s reset due to %s(0x%x)\n", 5740 mpi3mr_reset_type_name(reset_type), 5741 mpi3mr_reset_rc_name(reset_reason), reset_reason); 5742 5743 mpi3mr_clear_reset_history(sc); 5744 do { 5745 mpi3mr_dprint(sc, MPI3MR_INFO, 5746 "Write magic sequence to unlock host diag register (retry=%d)\n", 5747 ++unlock_retry_count); 5748 if (unlock_retry_count >= MPI3MR_HOSTDIAG_UNLOCK_RETRY_COUNT) { 5749 mpi3mr_dprint(sc, MPI3MR_ERROR, 5750 "%s reset failed! due to host diag register unlock failure" 5751 "host_diagnostic(0x%08x)\n", mpi3mr_reset_type_name(reset_type), 5752 host_diagnostic); 5753 sc->unrecoverable = 1; 5754 return retval; 5755 } 5756 5757 mpi3mr_regwrite(sc, MPI3_SYSIF_WRITE_SEQUENCE_OFFSET, 5758 MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH); 5759 mpi3mr_regwrite(sc, MPI3_SYSIF_WRITE_SEQUENCE_OFFSET, 5760 MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST); 5761 mpi3mr_regwrite(sc, MPI3_SYSIF_WRITE_SEQUENCE_OFFSET, 5762 MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND); 5763 mpi3mr_regwrite(sc, MPI3_SYSIF_WRITE_SEQUENCE_OFFSET, 5764 MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD); 5765 mpi3mr_regwrite(sc, MPI3_SYSIF_WRITE_SEQUENCE_OFFSET, 5766 MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH); 5767 mpi3mr_regwrite(sc, MPI3_SYSIF_WRITE_SEQUENCE_OFFSET, 5768 MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH); 5769 mpi3mr_regwrite(sc, MPI3_SYSIF_WRITE_SEQUENCE_OFFSET, 5770 MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH); 5771 5772 DELAY(1000); /* delay in usec */ 5773 host_diagnostic = mpi3mr_regread(sc, MPI3_SYSIF_HOST_DIAG_OFFSET); 5774 mpi3mr_dprint(sc, MPI3MR_INFO, 5775 "wrote magic sequence: retry_count(%d), host_diagnostic(0x%08x)\n", 5776 unlock_retry_count, host_diagnostic); 5777 } while (!(host_diagnostic & MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE)); 5778 5779 mpi3mr_regwrite(sc, MPI3_SYSIF_SCRATCHPAD0_OFFSET, reset_reason); 5780 mpi3mr_regwrite(sc, MPI3_SYSIF_HOST_DIAG_OFFSET, host_diagnostic | reset_type); 5781 5782 if (reset_type == MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET) { 5783 do { 5784 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 5785 if (ioc_status & 5786 MPI3_SYSIF_IOC_STATUS_RESET_HISTORY) { 5787 ioc_config = 5788 mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 5789 if (mpi3mr_soft_reset_success(ioc_status, 5790 ioc_config)) { 5791 mpi3mr_clear_reset_history(sc); 5792 retval = 0; 5793 break; 5794 } 5795 } 5796 DELAY(100 * 1000); 5797 } while (--timeout); 5798 } else if (reset_type == MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT) { 5799 do { 5800 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 5801 if (mpi3mr_diagfault_success(sc, ioc_status)) { 5802 retval = 0; 5803 break; 5804 } 5805 DELAY(100 * 1000); 5806 } while (--timeout); 5807 } 5808 5809 mpi3mr_regwrite(sc, MPI3_SYSIF_WRITE_SEQUENCE_OFFSET, 5810 MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND); 5811 5812 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 5813 ioc_config = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 5814 5815 mpi3mr_dprint(sc, MPI3MR_INFO, 5816 "IOC Status/Config after %s reset is (0x%x)/(0x%x)\n", 5817 !retval ? "successful":"failed", ioc_status, 5818 ioc_config); 5819 5820 if (retval) 5821 sc->unrecoverable = 1; 5822 5823 return retval; 5824 } 5825 5826 inline void mpi3mr_cleanup_event_taskq(struct mpi3mr_softc *sc) 5827 { 5828 mtx_lock(&sc->fwevt_lock); 5829 taskqueue_drain(sc->cam_sc->ev_tq, &sc->cam_sc->ev_task); 5830 taskqueue_block(sc->cam_sc->ev_tq); 5831 mtx_unlock(&sc->fwevt_lock); 5832 return; 5833 } 5834 5835 /** 5836 * mpi3mr_soft_reset_handler - Reset the controller 5837 * @sc: Adapter instance reference 5838 * @reset_reason: Reset reason code 5839 * @snapdump: snapdump enable/disbale bit 5840 * 5841 * This is an handler for recovering controller by issuing soft 5842 * reset or diag fault reset. This is a blocking function and 5843 * when one reset is executed if any other resets they will be 5844 * blocked. All IOCTLs/IO will be blocked during the reset. If 5845 * controller reset is successful then the controller will be 5846 * reinitalized, otherwise the controller will be marked as not 5847 * recoverable 5848 * 5849 * Return: 0 on success, non-zero on failure. 5850 */ 5851 int mpi3mr_soft_reset_handler(struct mpi3mr_softc *sc, 5852 U32 reset_reason, bool snapdump) 5853 { 5854 int retval = 0, i = 0; 5855 enum mpi3mr_iocstate ioc_state; 5856 5857 mpi3mr_dprint(sc, MPI3MR_INFO, "soft reset invoked: reason code: %s\n", 5858 mpi3mr_reset_rc_name(reset_reason)); 5859 5860 if ((reset_reason == MPI3MR_RESET_FROM_IOCTL) && 5861 (sc->reset.ioctl_reset_snapdump != true)) 5862 snapdump = false; 5863 5864 mpi3mr_dprint(sc, MPI3MR_INFO, 5865 "soft_reset_handler: wait if diag save is in progress\n"); 5866 while (sc->diagsave_timeout) 5867 DELAY(1000 * 1000); 5868 5869 ioc_state = mpi3mr_get_iocstate(sc); 5870 if (ioc_state == MRIOC_STATE_UNRECOVERABLE) { 5871 mpi3mr_dprint(sc, MPI3MR_ERROR, "controller is in unrecoverable state, exit\n"); 5872 sc->reset.type = MPI3MR_NO_RESET; 5873 sc->reset.reason = MPI3MR_DEFAULT_RESET_REASON; 5874 sc->reset.status = -1; 5875 sc->reset.ioctl_reset_snapdump = false; 5876 return -1; 5877 } 5878 5879 if (sc->reset_in_progress) { 5880 mpi3mr_dprint(sc, MPI3MR_INFO, "reset is already in progress, exit\n"); 5881 return -1; 5882 } 5883 5884 /* Pause IOs, drain and block the event taskqueue */ 5885 xpt_freeze_simq(sc->cam_sc->sim, 1); 5886 5887 mpi3mr_cleanup_event_taskq(sc); 5888 5889 sc->reset_in_progress = 1; 5890 sc->block_ioctls = 1; 5891 5892 while (mpi3mr_atomic_read(&sc->pend_ioctls) && (i < PEND_IOCTLS_COMP_WAIT_TIME)) { 5893 ioc_state = mpi3mr_get_iocstate(sc); 5894 if (ioc_state == MRIOC_STATE_FAULT) 5895 break; 5896 i++; 5897 if (!(i % 5)) { 5898 mpi3mr_dprint(sc, MPI3MR_INFO, 5899 "[%2ds]waiting for IOCTL to be finished from %s\n", i, __func__); 5900 } 5901 DELAY(1000 * 1000); 5902 } 5903 5904 if ((!snapdump) && (reset_reason != MPI3MR_RESET_FROM_FAULT_WATCH) && 5905 (reset_reason != MPI3MR_RESET_FROM_FIRMWARE) && 5906 (reset_reason != MPI3MR_RESET_FROM_CIACTIV_FAULT)) { 5907 5908 mpi3mr_dprint(sc, MPI3MR_INFO, "Turn off events prior to reset\n"); 5909 5910 for (i = 0; i < MPI3_EVENT_NOTIFY_EVENTMASK_WORDS; i++) 5911 sc->event_masks[i] = -1; 5912 mpi3mr_issue_event_notification(sc); 5913 } 5914 5915 mpi3mr_disable_interrupts(sc); 5916 5917 if (snapdump) 5918 mpi3mr_trigger_snapdump(sc, reset_reason); 5919 5920 retval = mpi3mr_issue_reset(sc, 5921 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, reset_reason); 5922 if (retval) { 5923 mpi3mr_dprint(sc, MPI3MR_ERROR, "Failed to issue soft reset to the ioc\n"); 5924 goto out; 5925 } 5926 5927 mpi3mr_flush_drv_cmds(sc); 5928 mpi3mr_flush_io(sc); 5929 mpi3mr_invalidate_devhandles(sc); 5930 mpi3mr_memset_buffers(sc); 5931 5932 if (sc->prepare_for_reset) { 5933 sc->prepare_for_reset = 0; 5934 sc->prepare_for_reset_timeout_counter = 0; 5935 } 5936 5937 retval = mpi3mr_initialize_ioc(sc, MPI3MR_INIT_TYPE_RESET); 5938 if (retval) { 5939 mpi3mr_dprint(sc, MPI3MR_ERROR, "reinit after soft reset failed: reason %d\n", 5940 reset_reason); 5941 goto out; 5942 } 5943 5944 DELAY((1000 * 1000) * 10); 5945 out: 5946 if (!retval) { 5947 sc->diagsave_timeout = 0; 5948 sc->reset_in_progress = 0; 5949 mpi3mr_rfresh_tgtdevs(sc); 5950 sc->ts_update_counter = 0; 5951 sc->block_ioctls = 0; 5952 sc->pel_abort_requested = 0; 5953 if (sc->pel_wait_pend) { 5954 sc->pel_cmds.retry_count = 0; 5955 mpi3mr_issue_pel_wait(sc, &sc->pel_cmds); 5956 mpi3mr_app_send_aen(sc); 5957 } 5958 } else { 5959 mpi3mr_issue_reset(sc, 5960 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT, reset_reason); 5961 sc->unrecoverable = 1; 5962 sc->reset_in_progress = 0; 5963 } 5964 5965 mpi3mr_dprint(sc, MPI3MR_INFO, "Soft Reset: %s\n", ((retval == 0) ? "SUCCESS" : "FAILED")); 5966 5967 taskqueue_unblock(sc->cam_sc->ev_tq); 5968 xpt_release_simq(sc->cam_sc->sim, 1); 5969 5970 sc->reset.type = MPI3MR_NO_RESET; 5971 sc->reset.reason = MPI3MR_DEFAULT_RESET_REASON; 5972 sc->reset.status = retval; 5973 sc->reset.ioctl_reset_snapdump = false; 5974 5975 return retval; 5976 } 5977 5978 /** 5979 * mpi3mr_issue_ioc_shutdown - shutdown controller 5980 * @sc: Adapter instance reference 5981 * 5982 * Send shutodwn notification to the controller and wait for the 5983 * shutdown_timeout for it to be completed. 5984 * 5985 * Return: Nothing. 5986 */ 5987 static void mpi3mr_issue_ioc_shutdown(struct mpi3mr_softc *sc) 5988 { 5989 U32 ioc_config, ioc_status; 5990 U8 retval = 1, retry = 0; 5991 U32 timeout = MPI3MR_DEFAULT_SHUTDOWN_TIME * 10; 5992 5993 mpi3mr_dprint(sc, MPI3MR_INFO, "sending shutdown notification\n"); 5994 if (sc->unrecoverable) { 5995 mpi3mr_dprint(sc, MPI3MR_ERROR, 5996 "controller is unrecoverable, shutdown not issued\n"); 5997 return; 5998 } 5999 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 6000 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 6001 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) { 6002 mpi3mr_dprint(sc, MPI3MR_ERROR, "shutdown already in progress\n"); 6003 return; 6004 } 6005 6006 ioc_config = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 6007 ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL; 6008 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ; 6009 6010 mpi3mr_regwrite(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET, ioc_config); 6011 6012 if (sc->facts.shutdown_timeout) 6013 timeout = sc->facts.shutdown_timeout * 10; 6014 6015 do { 6016 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 6017 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 6018 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE) { 6019 retval = 0; 6020 break; 6021 } 6022 6023 if (sc->unrecoverable) 6024 break; 6025 6026 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_FAULT)) { 6027 mpi3mr_print_fault_info(sc); 6028 6029 if (retry >= MPI3MR_MAX_SHUTDOWN_RETRY_COUNT) 6030 break; 6031 6032 if (mpi3mr_issue_reset(sc, 6033 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, 6034 MPI3MR_RESET_FROM_CTLR_CLEANUP)) 6035 break; 6036 6037 ioc_config = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 6038 ioc_config |= MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL; 6039 ioc_config |= MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ; 6040 6041 mpi3mr_regwrite(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET, ioc_config); 6042 6043 if (sc->facts.shutdown_timeout) 6044 timeout = sc->facts.shutdown_timeout * 10; 6045 6046 retry++; 6047 } 6048 6049 DELAY(100 * 1000); 6050 6051 } while (--timeout); 6052 6053 ioc_status = mpi3mr_regread(sc, MPI3_SYSIF_IOC_STATUS_OFFSET); 6054 ioc_config = mpi3mr_regread(sc, MPI3_SYSIF_IOC_CONFIG_OFFSET); 6055 6056 if (retval) { 6057 if ((ioc_status & MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK) 6058 == MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS) 6059 mpi3mr_dprint(sc, MPI3MR_ERROR, 6060 "shutdown still in progress after timeout\n"); 6061 } 6062 6063 mpi3mr_dprint(sc, MPI3MR_INFO, 6064 "ioc_status/ioc_config after %s shutdown is (0x%x)/(0x%x)\n", 6065 (!retval)?"successful":"failed", ioc_status, 6066 ioc_config); 6067 } 6068 6069 /** 6070 * mpi3mr_cleanup_ioc - Cleanup controller 6071 * @sc: Adapter instance reference 6072 6073 * controller cleanup handler, Message unit reset or soft reset 6074 * and shutdown notification is issued to the controller. 6075 * 6076 * Return: Nothing. 6077 */ 6078 void mpi3mr_cleanup_ioc(struct mpi3mr_softc *sc) 6079 { 6080 enum mpi3mr_iocstate ioc_state; 6081 6082 mpi3mr_dprint(sc, MPI3MR_INFO, "cleaning up the controller\n"); 6083 mpi3mr_disable_interrupts(sc); 6084 6085 ioc_state = mpi3mr_get_iocstate(sc); 6086 6087 if ((!sc->unrecoverable) && (!sc->reset_in_progress) && 6088 (ioc_state == MRIOC_STATE_READY)) { 6089 if (mpi3mr_mur_ioc(sc, 6090 MPI3MR_RESET_FROM_CTLR_CLEANUP)) 6091 mpi3mr_issue_reset(sc, 6092 MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET, 6093 MPI3MR_RESET_FROM_MUR_FAILURE); 6094 mpi3mr_issue_ioc_shutdown(sc); 6095 } 6096 6097 mpi3mr_dprint(sc, MPI3MR_INFO, "controller cleanup completed\n"); 6098 } 6099