1 /* 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016-2023, Broadcom Inc. All rights reserved. 5 * Support: <fbsd-storage-driver.pdl@broadcom.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are 9 * met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation and/or other 15 * materials provided with the distribution. 16 * 3. Neither the name of the Broadcom Inc. nor the names of its contributors 17 * may be used to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 * 32 * The views and conclusions contained in the software and documentation are 33 * those of the authors and should not be interpreted as representing 34 * official policies,either expressed or implied, of the FreeBSD Project. 35 * 36 * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 37 * 38 * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD 39 * 40 */ 41 42 /* 43 * Version History 44 * --------------- 45 * 46 * Date Version Description 47 * -------- ----------- ------------------------------------------------------ 48 * 11-30-18 03.00.00.08 Corresponds to Fusion-MPT MPI 3.0 Specification Rev H. 49 * 02-08-19 03.00.00.09 Corresponds to Fusion-MPT MPI 3.0 Specification Rev I. 50 * 05-03-19 03.00.00.10 Corresponds to Fusion-MPT MPI 3.0 Specification Rev J. 51 * 08-30-19 03.00.00.12 Corresponds to Fusion-MPT MPI 3.0 Specification Rev L. 52 * 11-01-19 03.00.00.13 Corresponds to Fusion-MPT MPI 3.0 Specification Rev M. 53 * 12-16-19 03.00.00.14 Corresponds to Fusion-MPT MPI 3.0 Specification Rev N. 54 * 02-28-20 03.00.00.15 Corresponds to Fusion-MPT MPI 3.0 Specification Rev O. 55 * 05-01-20 03.00.00.16 Corresponds to Fusion-MPT MPI 3.0 Specification Rev P. 56 * 06-26-20 03.00.00.17 Corresponds to Fusion-MPT MPI 3.0 Specification Rev Q. 57 * 08-28-20 03.00.00.18 Corresponds to Fusion-MPT MPI 3.0 Specification Rev R. 58 * 10-30-20 03.00.00.19 Corresponds to Fusion-MPT MPI 3.0 Specification Rev S. 59 * 12-18-20 03.00.00.20 Corresponds to Fusion-MPT MPI 3.0 Specification Rev T. 60 * 02-09-21 03.00.20.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev T - Interim Release 1. 61 * 02-26-21 03.00.21.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev U. 62 * 04-16-21 03.00.21.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev U - Interim Release 1. 63 * 04-28-21 03.00.21.02 Corresponds to Fusion-MPT MPI 3.0 Specification Rev U - Interim Release 2. 64 * 05-28-21 03.00.22.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev V. 65 * 07-23-21 03.00.22.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev V - Interim Release 1. 66 * 09-03-21 03.00.23.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 23. 67 * 10-23-21 03.00.23.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 23 - Interim Release 1. 68 * 12-03-21 03.00.24.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 24. 69 * 02-25-22 03.00.25.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 25. 70 * 06-03-22 03.00.26.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 26. 71 * 08-09-22 03.00.26.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 26 - Interim Release 1. 72 * 09-02-22 03.00.27.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 27. 73 * 10-20-22 03.00.27.01 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 27 - Interim Release 1. 74 * 12-02-22 03.00.28.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 28. 75 * 02-24-22 03.00.29.00 Corresponds to Fusion-MPT MPI 3.0 Specification Rev 29. 76 */ 77 #ifndef MPI30_TRANSPORT_H 78 #define MPI30_TRANSPORT_H 1 79 80 /***************************************************************************** 81 * Common version structure/union used in * 82 * messages and configuration pages * 83 ****************************************************************************/ 84 85 typedef struct _MPI3_VERSION_STRUCT 86 { 87 U8 Dev; /* 0x00 */ 88 U8 Unit; /* 0x01 */ 89 U8 Minor; /* 0x02 */ 90 U8 Major; /* 0x03 */ 91 } MPI3_VERSION_STRUCT, MPI3_POINTER PTR_MPI3_VERSION_STRUCT, 92 Mpi3VersionStruct_t, MPI3_POINTER pMpi3VersionStruct_t; 93 94 typedef union _MPI3_VERSION_UNION 95 { 96 MPI3_VERSION_STRUCT Struct; 97 U32 Word; 98 } MPI3_VERSION_UNION, MPI3_POINTER PTR_MPI3_VERSION_UNION, 99 Mpi3VersionUnion_t, MPI3_POINTER pMpi3VersionUnion_t; 100 101 /****** Version constants for this revision ****/ 102 #define MPI3_VERSION_MAJOR (3) 103 #define MPI3_VERSION_MINOR (0) 104 #define MPI3_VERSION_UNIT (29) 105 #define MPI3_VERSION_DEV (0) 106 107 /****** DevHandle definitions *****/ 108 #define MPI3_DEVHANDLE_INVALID (0xFFFF) 109 110 /***************************************************************************** 111 * System Interface Register Definitions * 112 ****************************************************************************/ 113 typedef struct _MPI3_SYSIF_OPER_QUEUE_INDEXES 114 { 115 U16 ProducerIndex; /* 0x00 */ 116 U16 Reserved02; /* 0x02 */ 117 U16 ConsumerIndex; /* 0x04 */ 118 U16 Reserved06; /* 0x06 */ 119 } MPI3_SYSIF_OPER_QUEUE_INDEXES, MPI3_POINTER PTR_MPI3_SYSIF_OPER_QUEUE_INDEXES; 120 121 typedef volatile struct _MPI3_SYSIF_REGISTERS 122 { 123 U64 IOCInformation; /* 0x00 */ 124 MPI3_VERSION_UNION Version; /* 0x08 */ 125 U32 Reserved0C[2]; /* 0x0C */ 126 U32 IOCConfiguration; /* 0x14 */ 127 U32 Reserved18; /* 0x18 */ 128 U32 IOCStatus; /* 0x1C */ 129 U32 Reserved20; /* 0x20 */ 130 U32 AdminQueueNumEntries; /* 0x24 */ 131 U64 AdminRequestQueueAddress; /* 0x28 */ 132 U64 AdminReplyQueueAddress; /* 0x30 */ 133 U32 Reserved38[2]; /* 0x38 */ 134 U32 CoalesceControl; /* 0x40 */ 135 U32 Reserved44[1007]; /* 0x44 */ 136 U16 AdminRequestQueuePI; /* 0x1000 */ 137 U16 Reserved1002; /* 0x1002 */ 138 U16 AdminReplyQueueCI; /* 0x1004 */ 139 U16 Reserved1006; /* 0x1006 */ 140 MPI3_SYSIF_OPER_QUEUE_INDEXES OperQueueIndexes[383]; /* 0x1008 */ 141 U32 Reserved1C00; /* 0x1C00 */ 142 U32 WriteSequence; /* 0x1C04 */ 143 U32 HostDiagnostic; /* 0x1C08 */ 144 U32 Reserved1C0C; /* 0x1C0C */ 145 U32 Fault; /* 0x1C10 */ 146 U32 FaultInfo[3]; /* 0x1C14 */ 147 U32 Reserved1C20[4]; /* 0x1C20 */ 148 U64 HCBAddress; /* 0x1C30 */ 149 U32 HCBSize; /* 0x1C38 */ 150 U32 Reserved1C3C; /* 0x1C3C */ 151 U32 ReplyFreeHostIndex; /* 0x1C40 */ 152 U32 SenseBufferFreeHostIndex; /* 0x1C44 */ 153 U32 Reserved1C48[2]; /* 0x1C48 */ 154 U64 DiagRWData; /* 0x1C50 */ 155 U64 DiagRWAddress; /* 0x1C58 */ 156 U16 DiagRWControl; /* 0x1C60 */ 157 U16 DiagRWStatus; /* 0x1C62 */ 158 U32 Reserved1C64[35]; /* 0x1C64 */ 159 U32 Scratchpad[4]; /* 0x1CF0 */ 160 U32 Reserved1D00[192]; /* 0x1D00 */ 161 U32 DeviceAssignedRegisters[2048]; /* 0x2000 */ 162 } MPI3_SYSIF_REGS, MPI3_POINTER PTR_MPI3_SYSIF_REGS, 163 Mpi3SysIfRegs_t, MPI3_POINTER pMpi3SysIfRegs_t; 164 165 /**** Defines for the IOCInformation register ****/ 166 #define MPI3_SYSIF_IOC_INFO_LOW_OFFSET (0x00000000) 167 #define MPI3_SYSIF_IOC_INFO_HIGH_OFFSET (0x00000004) 168 #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_MASK (0xFF000000) 169 #define MPI3_SYSIF_IOC_INFO_LOW_TIMEOUT_SHIFT (24) 170 #define MPI3_SYSIF_IOC_INFO_LOW_HCB_DISABLED (0x00000001) 171 172 /**** Defines for the IOCConfiguration register ****/ 173 #define MPI3_SYSIF_IOC_CONFIG_OFFSET (0x00000014) 174 #define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ (0x00F00000) 175 #define MPI3_SYSIF_IOC_CONFIG_OPER_RPY_ENT_SZ_SHIFT (20) 176 #define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ (0x000F0000) 177 #define MPI3_SYSIF_IOC_CONFIG_OPER_REQ_ENT_SZ_SHIFT (16) 178 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_MASK (0x0000C000) 179 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NO (0x00000000) 180 #define MPI3_SYSIF_IOC_CONFIG_SHUTDOWN_NORMAL (0x00004000) 181 #define MPI3_SYSIF_IOC_CONFIG_DEVICE_SHUTDOWN_SEND_REQ (0x00002000) 182 #define MPI3_SYSIF_IOC_CONFIG_DIAG_SAVE (0x00000010) 183 #define MPI3_SYSIF_IOC_CONFIG_ENABLE_IOC (0x00000001) 184 185 /**** Defines for the IOCStatus register ****/ 186 #define MPI3_SYSIF_IOC_STATUS_OFFSET (0x0000001C) 187 #define MPI3_SYSIF_IOC_STATUS_RESET_HISTORY (0x00000010) 188 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_MASK (0x0000000C) 189 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_SHIFT (0x00000002) 190 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_NONE (0x00000000) 191 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_IN_PROGRESS (0x00000004) 192 #define MPI3_SYSIF_IOC_STATUS_SHUTDOWN_COMPLETE (0x00000008) 193 #define MPI3_SYSIF_IOC_STATUS_FAULT (0x00000002) 194 #define MPI3_SYSIF_IOC_STATUS_READY (0x00000001) 195 196 /**** Defines for the AdminQueueNumEntries register ****/ 197 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_OFFSET (0x00000024) 198 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REQ_MASK (0x0FFF) 199 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_OFFSET (0x00000026) 200 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_MASK (0x0FFF0000) 201 #define MPI3_SYSIF_ADMIN_Q_NUM_ENTRIES_REPLY_SHIFT (16) 202 203 /**** Defines for the AdminRequestQueueAddress register ****/ 204 #define MPI3_SYSIF_ADMIN_REQ_Q_ADDR_LOW_OFFSET (0x00000028) 205 #define MPI3_SYSIF_ADMIN_REQ_Q_ADDR_HIGH_OFFSET (0x0000002C) 206 207 /**** Defines for the AdminReplyQueueAddress register ****/ 208 #define MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_LOW_OFFSET (0x00000030) 209 #define MPI3_SYSIF_ADMIN_REPLY_Q_ADDR_HIGH_OFFSET (0x00000034) 210 211 /**** Defines for the CoalesceControl register ****/ 212 #define MPI3_SYSIF_COALESCE_CONTROL_OFFSET (0x00000040) 213 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_MASK (0xC0000000) 214 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_NO_CHANGE (0x00000000) 215 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_DISABLE (0x40000000) 216 #define MPI3_SYSIF_COALESCE_CONTROL_ENABLE_ENABLE (0xC0000000) 217 #define MPI3_SYSIF_COALESCE_CONTROL_VALID (0x20000000) 218 #define MPI3_SYSIF_COALESCE_CONTROL_MSIX_IDX_MASK (0x01FF0000) 219 #define MPI3_SYSIF_COALESCE_CONTROL_MSIX_IDX_SHIFT (16) 220 #define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_MASK (0x0000FF00) 221 #define MPI3_SYSIF_COALESCE_CONTROL_TIMEOUT_SHIFT (8) 222 #define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_MASK (0x000000FF) 223 #define MPI3_SYSIF_COALESCE_CONTROL_DEPTH_SHIFT (0) 224 225 /**** Defines for the AdminRequestQueuePI register ****/ 226 #define MPI3_SYSIF_ADMIN_REQ_Q_PI_OFFSET (0x00001000) 227 228 /**** Defines for the AdminReplyQueueCI register ****/ 229 #define MPI3_SYSIF_ADMIN_REPLY_Q_CI_OFFSET (0x00001004) 230 231 /**** Defines for the OperationalRequestQueuePI register */ 232 #define MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET (0x00001008) 233 #define MPI3_SYSIF_OPER_REQ_Q_N_PI_OFFSET(N) (MPI3_SYSIF_OPER_REQ_Q_PI_OFFSET + (((N)-1)*8)) /* N = 1, 2, 3, ..., 255 */ 234 235 /**** Defines for the OperationalReplyQueueCI register */ 236 #define MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET (0x0000100C) 237 #define MPI3_SYSIF_OPER_REPLY_Q_N_CI_OFFSET(N) (MPI3_SYSIF_OPER_REPLY_Q_CI_OFFSET + (((N)-1)*8)) /* N = 1, 2, 3, ..., 255 */ 238 239 /**** Defines for the WriteSequence register *****/ 240 #define MPI3_SYSIF_WRITE_SEQUENCE_OFFSET (0x00001C04) 241 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_MASK (0x0000000F) 242 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_FLUSH (0x0) 243 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_1ST (0xF) 244 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_2ND (0x4) 245 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_3RD (0xB) 246 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_4TH (0x2) 247 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_5TH (0x7) 248 #define MPI3_SYSIF_WRITE_SEQUENCE_KEY_VALUE_6TH (0xD) 249 250 /**** Defines for the HostDiagnostic register *****/ 251 #define MPI3_SYSIF_HOST_DIAG_OFFSET (0x00001C08) 252 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_MASK (0x00000700) 253 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_NO_RESET (0x00000000) 254 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_SOFT_RESET (0x00000100) 255 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_HOST_CONTROL_BOOT_RESET (0x00000200) 256 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_COMPLETE_RESET (0x00000300) 257 #define MPI3_SYSIF_HOST_DIAG_RESET_ACTION_DIAG_FAULT (0x00000700) 258 #define MPI3_SYSIF_HOST_DIAG_SAVE_IN_PROGRESS (0x00000080) 259 #define MPI3_SYSIF_HOST_DIAG_SECURE_BOOT (0x00000040) 260 #define MPI3_SYSIF_HOST_DIAG_CLEAR_INVALID_FW_IMAGE (0x00000020) 261 #define MPI3_SYSIF_HOST_DIAG_INVALID_FW_IMAGE (0x00000010) 262 #define MPI3_SYSIF_HOST_DIAG_HCBENABLE (0x00000008) 263 #define MPI3_SYSIF_HOST_DIAG_HCBMODE (0x00000004) 264 #define MPI3_SYSIF_HOST_DIAG_DIAG_RW_ENABLE (0x00000002) 265 #define MPI3_SYSIF_HOST_DIAG_DIAG_WRITE_ENABLE (0x00000001) 266 267 /**** Defines for the Fault register ****/ 268 #define MPI3_SYSIF_FAULT_OFFSET (0x00001C10) 269 #define MPI3_SYSIF_FAULT_CODE_MASK (0x0000FFFF) 270 #define MPI3_SYSIF_FAULT_CODE_DIAG_FAULT_RESET (0x0000F000) 271 #define MPI3_SYSIF_FAULT_CODE_CI_ACTIVATION_RESET (0x0000F001) 272 #define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_IN_PROGRESS (0x0000F002) 273 #define MPI3_SYSIF_FAULT_CODE_COMPLETE_RESET_NEEDED (0x0000F003) 274 #define MPI3_SYSIF_FAULT_CODE_SOFT_RESET_NEEDED (0x0000F004) 275 #define MPI3_SYSIF_FAULT_CODE_POWER_CYCLE_REQUIRED (0x0000F005) 276 #define MPI3_SYSIF_FAULT_CODE_TEMP_THRESHOLD_EXCEEDED (0x0000F006) 277 278 /**** Defines for FaultCodeAdditionalInfo registers ****/ 279 #define MPI3_SYSIF_FAULT_INFO0_OFFSET (0x00001C14) 280 #define MPI3_SYSIF_FAULT_INFO1_OFFSET (0x00001C18) 281 #define MPI3_SYSIF_FAULT_INFO2_OFFSET (0x00001C1C) 282 283 /**** Defines for HCBAddress register ****/ 284 #define MPI3_SYSIF_HCB_ADDRESS_LOW_OFFSET (0x00001C30) 285 #define MPI3_SYSIF_HCB_ADDRESS_HIGH_OFFSET (0x00001C34) 286 287 /**** Defines for HCBSize register ****/ 288 #define MPI3_SYSIF_HCB_SIZE_OFFSET (0x00001C38) 289 #define MPI3_SYSIF_HCB_SIZE_SIZE_MASK (0xFFFFF000) 290 #define MPI3_SYSIF_HCB_SIZE_SIZE_SHIFT (12) 291 #define MPI3_SYSIF_HCB_SIZE_HCDW_ENABLE (0x00000001) 292 293 /**** Defines for ReplyFreeHostIndex register ****/ 294 #define MPI3_SYSIF_REPLY_FREE_HOST_INDEX_OFFSET (0x00001C40) 295 296 /**** Defines for SenseBufferFreeHostIndex register ****/ 297 #define MPI3_SYSIF_SENSE_BUF_FREE_HOST_INDEX_OFFSET (0x00001C44) 298 299 /**** Defines for DiagRWData register ****/ 300 #define MPI3_SYSIF_DIAG_RW_DATA_LOW_OFFSET (0x00001C50) 301 #define MPI3_SYSIF_DIAG_RW_DATA_HIGH_OFFSET (0x00001C54) 302 303 /**** Defines for DiagRWAddress ****/ 304 #define MPI3_SYSIF_DIAG_RW_ADDRESS_LOW_OFFSET (0x00001C58) 305 #define MPI3_SYSIF_DIAG_RW_ADDRESS_HIGH_OFFSET (0x00001C5C) 306 307 /**** Defines for DiagRWControl register ****/ 308 #define MPI3_SYSIF_DIAG_RW_CONTROL_OFFSET (0x00001C60) 309 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_MASK (0x00000030) 310 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_1BYTE (0x00000000) 311 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_2BYTES (0x00000010) 312 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_4BYTES (0x00000020) 313 #define MPI3_SYSIF_DIAG_RW_CONTROL_LEN_8BYTES (0x00000030) 314 #define MPI3_SYSIF_DIAG_RW_CONTROL_RESET (0x00000004) 315 #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_MASK (0x00000002) 316 #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_READ (0x00000000) 317 #define MPI3_SYSIF_DIAG_RW_CONTROL_DIR_WRITE (0x00000002) 318 #define MPI3_SYSIF_DIAG_RW_CONTROL_START (0x00000001) 319 320 /**** Defines for DiagRWStatus register ****/ 321 #define MPI3_SYSIF_DIAG_RW_STATUS_OFFSET (0x00001C62) 322 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_MASK (0x0000000E) 323 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_SUCCESS (0x00000000) 324 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_INV_ADDR (0x00000002) 325 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_ACC_ERR (0x00000004) 326 #define MPI3_SYSIF_DIAG_RW_STATUS_STATUS_PAR_ERR (0x00000006) 327 #define MPI3_SYSIF_DIAG_RW_STATUS_BUSY (0x00000001) 328 329 /**** Defines for Scratchpad registers ****/ 330 #define MPI3_SYSIF_SCRATCHPAD0_OFFSET (0x00001CF0) 331 #define MPI3_SYSIF_SCRATCHPAD1_OFFSET (0x00001CF4) 332 #define MPI3_SYSIF_SCRATCHPAD2_OFFSET (0x00001CF8) 333 #define MPI3_SYSIF_SCRATCHPAD3_OFFSET (0x00001CFC) 334 335 /**** Defines for Device Assigned registers ****/ 336 #define MPI3_SYSIF_DEVICE_ASSIGNED_REGS_OFFSET (0x00002000) 337 338 /**** Default Defines for Diag Save Timeout ****/ 339 #define MPI3_SYSIF_DIAG_SAVE_TIMEOUT (60) /* seconds */ 340 341 /***************************************************************************** 342 * Reply Descriptors * 343 ****************************************************************************/ 344 345 /***************************************************************************** 346 * Default Reply Descriptor * 347 ****************************************************************************/ 348 typedef struct _MPI3_DEFAULT_REPLY_DESCRIPTOR 349 { 350 U32 DescriptorTypeDependent1[2]; /* 0x00 */ 351 U16 RequestQueueCI; /* 0x08 */ 352 U16 RequestQueueID; /* 0x0A */ 353 U16 DescriptorTypeDependent2; /* 0x0C */ 354 U16 ReplyFlags; /* 0x0E */ 355 } MPI3_DEFAULT_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_DEFAULT_REPLY_DESCRIPTOR, 356 Mpi3DefaultReplyDescriptor_t, MPI3_POINTER pMpi3DefaultReplyDescriptor_t; 357 358 /**** Defines for the ReplyFlags field ****/ 359 #define MPI3_REPLY_DESCRIPT_FLAGS_PHASE_MASK (0x0001) 360 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_MASK (0xF000) 361 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_ADDRESS_REPLY (0x0000) 362 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_SUCCESS (0x1000) 363 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_TARGET_COMMAND_BUFFER (0x2000) 364 #define MPI3_REPLY_DESCRIPT_FLAGS_TYPE_STATUS (0x3000) 365 366 /**** Defines for the RequestQueueID field ****/ 367 #define MPI3_REPLY_DESCRIPT_REQUEST_QUEUE_ID_INVALID (0xFFFF) 368 369 /***************************************************************************** 370 * Address Reply Descriptor * 371 ****************************************************************************/ 372 typedef struct _MPI3_ADDRESS_REPLY_DESCRIPTOR 373 { 374 U64 ReplyFrameAddress; /* 0x00 */ 375 U16 RequestQueueCI; /* 0x08 */ 376 U16 RequestQueueID; /* 0x0A */ 377 U16 Reserved0C; /* 0x0C */ 378 U16 ReplyFlags; /* 0x0E */ 379 } MPI3_ADDRESS_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_ADDRESS_REPLY_DESCRIPTOR, 380 Mpi3AddressReplyDescriptor_t, MPI3_POINTER pMpi3AddressReplyDescriptor_t; 381 382 /***************************************************************************** 383 * Success Reply Descriptor * 384 ****************************************************************************/ 385 typedef struct _MPI3_SUCCESS_REPLY_DESCRIPTOR 386 { 387 U32 Reserved00[2]; /* 0x00 */ 388 U16 RequestQueueCI; /* 0x08 */ 389 U16 RequestQueueID; /* 0x0A */ 390 U16 HostTag; /* 0x0C */ 391 U16 ReplyFlags; /* 0x0E */ 392 } MPI3_SUCCESS_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_SUCCESS_REPLY_DESCRIPTOR, 393 Mpi3SuccessReplyDescriptor_t, MPI3_POINTER pMpi3SuccessReplyDescriptor_t; 394 395 /***************************************************************************** 396 * Target Command Buffer Reply Descriptor * 397 ****************************************************************************/ 398 typedef struct _MPI3_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR 399 { 400 U32 Reserved00; /* 0x00 */ 401 U16 InitiatorDevHandle; /* 0x04 */ 402 U8 PhyNum; /* 0x06 */ 403 U8 Reserved07; /* 0x07 */ 404 U16 RequestQueueCI; /* 0x08 */ 405 U16 RequestQueueID; /* 0x0A */ 406 U16 IOIndex; /* 0x0C */ 407 U16 ReplyFlags; /* 0x0E */ 408 } MPI3_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR, 409 Mpi3TargetCommandBufferReplyDescriptor_t, MPI3_POINTER pMpi3TargetCommandBufferReplyDescriptor_t; 410 411 /**** See Default Reply Descriptor Defines above for definitions in the ReplyFlags field ****/ 412 413 /***************************************************************************** 414 * Status Reply Descriptor * 415 ****************************************************************************/ 416 typedef struct _MPI3_STATUS_REPLY_DESCRIPTOR 417 { 418 U16 IOCStatus; /* 0x00 */ 419 U16 Reserved02; /* 0x02 */ 420 U32 IOCLogInfo; /* 0x04 */ 421 U16 RequestQueueCI; /* 0x08 */ 422 U16 RequestQueueID; /* 0x0A */ 423 U16 HostTag; /* 0x0C */ 424 U16 ReplyFlags; /* 0x0E */ 425 } MPI3_STATUS_REPLY_DESCRIPTOR, MPI3_POINTER PTR_MPI3_STATUS_REPLY_DESCRIPTOR, 426 Mpi3StatusReplyDescriptor_t, MPI3_POINTER pMpi3StatusReplyDescriptor_t; 427 428 /**** Defines for the IOCStatus field ****/ 429 #define MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_LOGINFOAVAIL (0x8000) 430 #define MPI3_REPLY_DESCRIPT_STATUS_IOCSTATUS_STATUS_MASK (0x7FFF) 431 432 /**** Defines for the IOCLogInfo field ****/ 433 #define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_MASK (0xF0000000) 434 #define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_NO_INFO (0x00000000) 435 #define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_TYPE_SAS (0x30000000) 436 #define MPI3_REPLY_DESCRIPT_STATUS_IOCLOGINFO_DATA_MASK (0x0FFFFFFF) 437 438 /***************************************************************************** 439 * Union of Reply Descriptors * 440 ****************************************************************************/ 441 typedef union _MPI3_REPLY_DESCRIPTORS_UNION 442 { 443 MPI3_DEFAULT_REPLY_DESCRIPTOR Default; 444 MPI3_ADDRESS_REPLY_DESCRIPTOR AddressReply; 445 MPI3_SUCCESS_REPLY_DESCRIPTOR Success; 446 MPI3_TARGET_COMMAND_BUFFER_REPLY_DESCRIPTOR TargetCommandBuffer; 447 MPI3_STATUS_REPLY_DESCRIPTOR Status; 448 U32 Words[4]; 449 } MPI3_REPLY_DESCRIPTORS_UNION, MPI3_POINTER PTR_MPI3_REPLY_DESCRIPTORS_UNION, 450 Mpi3ReplyDescriptorsUnion_t, MPI3_POINTER pMpi3ReplyDescriptorsUnion_t; 451 452 453 /***************************************************************************** 454 * Scatter Gather Elements * 455 ****************************************************************************/ 456 457 /***************************************************************************** 458 * Common structure for Simple, Chain, and Last Chain * 459 * scatter gather elements * 460 ****************************************************************************/ 461 typedef struct _MPI3_SGE_COMMON 462 { 463 U64 Address; /* 0x00 */ 464 U32 Length; /* 0x08 */ 465 U8 Reserved0C[3]; /* 0x0C */ 466 U8 Flags; /* 0x0F */ 467 } MPI3_SGE_SIMPLE, MPI3_POINTER PTR_MPI3_SGE_SIMPLE, 468 Mpi3SGESimple_t, MPI3_POINTER pMpi3SGESimple_t, 469 MPI3_SGE_CHAIN, MPI3_POINTER PTR_MPI3_SGE_CHAIN, 470 Mpi3SGEChain_t, MPI3_POINTER pMpi3SGEChain_t, 471 MPI3_SGE_LAST_CHAIN, MPI3_POINTER PTR_MPI3_SGE_LAST_CHAIN, 472 Mpi3SGELastChain_t, MPI3_POINTER pMpi3SGELastChain_t; 473 474 /***************************************************************************** 475 * Bit Bucket scatter gather element * 476 ****************************************************************************/ 477 typedef struct _MPI3_SGE_BIT_BUCKET 478 { 479 U64 Reserved00; /* 0x00 */ 480 U32 Length; /* 0x08 */ 481 U8 Reserved0C[3]; /* 0x0C */ 482 U8 Flags; /* 0x0F */ 483 } MPI3_SGE_BIT_BUCKET, MPI3_POINTER PTR_MPI3_SGE_BIT_BUCKET, 484 Mpi3SGEBitBucket_t, MPI3_POINTER pMpi3SGEBitBucket_t; 485 486 /***************************************************************************** 487 * Extended EEDP scatter gather element * 488 ****************************************************************************/ 489 typedef struct _MPI3_SGE_EXTENDED_EEDP 490 { 491 U8 UserDataSize; /* 0x00 */ 492 U8 Reserved01; /* 0x01 */ 493 U16 EEDPFlags; /* 0x02 */ 494 U32 SecondaryReferenceTag; /* 0x04 */ 495 U16 SecondaryApplicationTag; /* 0x08 */ 496 U16 ApplicationTagTranslationMask; /* 0x0A */ 497 U16 Reserved0C; /* 0x0C */ 498 U8 ExtendedOperation; /* 0x0E */ 499 U8 Flags; /* 0x0F */ 500 } MPI3_SGE_EXTENDED_EEDP, MPI3_POINTER PTR_MPI3_SGE_EXTENDED_EEDP, 501 Mpi3SGEExtendedEEDP_t, MPI3_POINTER pMpi3SGEExtendedEEDP_t; 502 503 /***************************************************************************** 504 * Union of scatter gather elements * 505 ****************************************************************************/ 506 typedef union _MPI3_SGE_UNION 507 { 508 MPI3_SGE_SIMPLE Simple; 509 MPI3_SGE_CHAIN Chain; 510 MPI3_SGE_LAST_CHAIN LastChain; 511 MPI3_SGE_BIT_BUCKET BitBucket; 512 MPI3_SGE_EXTENDED_EEDP Eedp; 513 U32 Words[4]; 514 } MPI3_SGE_UNION, MPI3_POINTER PTR_MPI3_SGE_UNION, 515 Mpi3SGEUnion_t, MPI3_POINTER pMpi3SGEUnion_t; 516 517 /**** Definitions for the Flags field ****/ 518 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_MASK (0xF0) 519 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_SIMPLE (0x00) 520 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_BIT_BUCKET (0x10) 521 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_CHAIN (0x20) 522 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_LAST_CHAIN (0x30) 523 #define MPI3_SGE_FLAGS_ELEMENT_TYPE_EXTENDED (0xF0) 524 #define MPI3_SGE_FLAGS_END_OF_LIST (0x08) 525 #define MPI3_SGE_FLAGS_END_OF_BUFFER (0x04) 526 #define MPI3_SGE_FLAGS_DLAS_MASK (0x03) 527 #define MPI3_SGE_FLAGS_DLAS_SYSTEM (0x00) 528 #define MPI3_SGE_FLAGS_DLAS_IOC_UDP (0x01) 529 #define MPI3_SGE_FLAGS_DLAS_IOC_CTL (0x02) 530 531 /**** Definitions for the ExtendedOperation field of Extended element ****/ 532 #define MPI3_SGE_EXT_OPER_EEDP (0x00) 533 534 /**** Definitions for the EEDPFlags field of Extended EEDP element ****/ 535 #define MPI3_EEDPFLAGS_INCR_PRI_REF_TAG (0x8000) 536 #define MPI3_EEDPFLAGS_INCR_SEC_REF_TAG (0x4000) 537 #define MPI3_EEDPFLAGS_INCR_PRI_APP_TAG (0x2000) 538 #define MPI3_EEDPFLAGS_INCR_SEC_APP_TAG (0x1000) 539 #define MPI3_EEDPFLAGS_ESC_PASSTHROUGH (0x0800) 540 #define MPI3_EEDPFLAGS_CHK_REF_TAG (0x0400) 541 #define MPI3_EEDPFLAGS_CHK_APP_TAG (0x0200) 542 #define MPI3_EEDPFLAGS_CHK_GUARD (0x0100) 543 #define MPI3_EEDPFLAGS_ESC_MODE_MASK (0x00C0) 544 #define MPI3_EEDPFLAGS_ESC_MODE_DO_NOT_DISABLE (0x0040) 545 #define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_DISABLE (0x0080) 546 #define MPI3_EEDPFLAGS_ESC_MODE_APPTAG_REFTAG_DISABLE (0x00C0) 547 #define MPI3_EEDPFLAGS_HOST_GUARD_MASK (0x0030) 548 #define MPI3_EEDPFLAGS_HOST_GUARD_T10_CRC (0x0000) 549 #define MPI3_EEDPFLAGS_HOST_GUARD_IP_CHKSUM (0x0010) 550 #define MPI3_EEDPFLAGS_HOST_GUARD_OEM_SPECIFIC (0x0020) 551 #define MPI3_EEDPFLAGS_PT_REF_TAG (0x0008) 552 #define MPI3_EEDPFLAGS_EEDP_OP_MASK (0x0007) 553 #define MPI3_EEDPFLAGS_EEDP_OP_CHECK (0x0001) 554 #define MPI3_EEDPFLAGS_EEDP_OP_STRIP (0x0002) 555 #define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REMOVE (0x0003) 556 #define MPI3_EEDPFLAGS_EEDP_OP_INSERT (0x0004) 557 #define MPI3_EEDPFLAGS_EEDP_OP_REPLACE (0x0006) 558 #define MPI3_EEDPFLAGS_EEDP_OP_CHECK_REGEN (0x0007) 559 560 /**** Definitions for the UserDataSize field of Extended EEDP element ****/ 561 #define MPI3_EEDP_UDS_512 (0x01) 562 #define MPI3_EEDP_UDS_520 (0x02) 563 #define MPI3_EEDP_UDS_4080 (0x03) 564 #define MPI3_EEDP_UDS_4088 (0x04) 565 #define MPI3_EEDP_UDS_4096 (0x05) 566 #define MPI3_EEDP_UDS_4104 (0x06) 567 #define MPI3_EEDP_UDS_4160 (0x07) 568 569 /***************************************************************************** 570 * Standard Message Structures * 571 ****************************************************************************/ 572 573 /***************************************************************************** 574 * Request Message Header for all request messages * 575 ****************************************************************************/ 576 typedef struct _MPI3_REQUEST_HEADER 577 { 578 U16 HostTag; /* 0x00 */ 579 U8 IOCUseOnly02; /* 0x02 */ 580 U8 Function; /* 0x03 */ 581 U16 IOCUseOnly04; /* 0x04 */ 582 U8 IOCUseOnly06; /* 0x06 */ 583 U8 MsgFlags; /* 0x07 */ 584 U16 ChangeCount; /* 0x08 */ 585 U16 FunctionDependent; /* 0x0A */ 586 } MPI3_REQUEST_HEADER, MPI3_POINTER PTR_MPI3_REQUEST_HEADER, 587 Mpi3RequestHeader_t, MPI3_POINTER pMpi3RequestHeader_t; 588 589 /***************************************************************************** 590 * Default Reply * 591 ****************************************************************************/ 592 typedef struct _MPI3_DEFAULT_REPLY 593 { 594 U16 HostTag; /* 0x00 */ 595 U8 IOCUseOnly02; /* 0x02 */ 596 U8 Function; /* 0x03 */ 597 U16 IOCUseOnly04; /* 0x04 */ 598 U8 IOCUseOnly06; /* 0x06 */ 599 U8 MsgFlags; /* 0x07 */ 600 U16 IOCUseOnly08; /* 0x08 */ 601 U16 IOCStatus; /* 0x0A */ 602 U32 IOCLogInfo; /* 0x0C */ 603 } MPI3_DEFAULT_REPLY, MPI3_POINTER PTR_MPI3_DEFAULT_REPLY, 604 Mpi3DefaultReply_t, MPI3_POINTER pMpi3DefaultReply_t; 605 606 /**** Defines for the HostTag field ****/ 607 #define MPI3_HOST_TAG_INVALID (0xFFFF) 608 609 /**** Defines for message Function ****/ 610 /* I/O Controller functions */ 611 #define MPI3_FUNCTION_IOC_FACTS (0x01) /* IOC Facts */ 612 #define MPI3_FUNCTION_IOC_INIT (0x02) /* IOC Init */ 613 #define MPI3_FUNCTION_PORT_ENABLE (0x03) /* Port Enable */ 614 #define MPI3_FUNCTION_EVENT_NOTIFICATION (0x04) /* Event Notification */ 615 #define MPI3_FUNCTION_EVENT_ACK (0x05) /* Event Acknowledge */ 616 #define MPI3_FUNCTION_CI_DOWNLOAD (0x06) /* Component Image Download */ 617 #define MPI3_FUNCTION_CI_UPLOAD (0x07) /* Component Image Upload */ 618 #define MPI3_FUNCTION_IO_UNIT_CONTROL (0x08) /* IO Unit Control */ 619 #define MPI3_FUNCTION_PERSISTENT_EVENT_LOG (0x09) /* Persistent Event Log */ 620 #define MPI3_FUNCTION_MGMT_PASSTHROUGH (0x0A) /* Management Passthrough */ 621 #define MPI3_FUNCTION_CONFIG (0x10) /* Configuration */ 622 623 /* SCSI Initiator I/O functions */ 624 #define MPI3_FUNCTION_SCSI_IO (0x20) /* SCSI IO */ 625 #define MPI3_FUNCTION_SCSI_TASK_MGMT (0x21) /* SCSI Task Management */ 626 #define MPI3_FUNCTION_SMP_PASSTHROUGH (0x22) /* SMP Passthrough */ 627 #define MPI3_FUNCTION_NVME_ENCAPSULATED (0x24) /* NVMe Encapsulated */ 628 629 /* SCSI Target I/O functions */ 630 #define MPI3_FUNCTION_TARGET_ASSIST (0x30) /* Target Assist */ 631 #define MPI3_FUNCTION_TARGET_STATUS_SEND (0x31) /* Target Status Send */ 632 #define MPI3_FUNCTION_TARGET_MODE_ABORT (0x32) /* Target Mode Abort */ 633 #define MPI3_FUNCTION_TARGET_CMD_BUF_POST_BASE (0x33) /* Target Command Buffer Post Base */ 634 #define MPI3_FUNCTION_TARGET_CMD_BUF_POST_LIST (0x34) /* Target Command Buffer Post List */ 635 636 /* Queue Management functions */ 637 #define MPI3_FUNCTION_CREATE_REQUEST_QUEUE (0x70) /* Create an operational request queue */ 638 #define MPI3_FUNCTION_DELETE_REQUEST_QUEUE (0x71) /* Delete an operational request queue */ 639 #define MPI3_FUNCTION_CREATE_REPLY_QUEUE (0x72) /* Create an operational reply queue */ 640 #define MPI3_FUNCTION_DELETE_REPLY_QUEUE (0x73) /* Delete an operational reply queue */ 641 642 /* Diagnostic Tools */ 643 #define MPI3_FUNCTION_TOOLBOX (0x80) /* Toolbox */ 644 #define MPI3_FUNCTION_DIAG_BUFFER_POST (0x81) /* Post a Diagnostic Buffer to the I/O Unit */ 645 #define MPI3_FUNCTION_DIAG_BUFFER_MANAGE (0x82) /* Manage a Diagnostic Buffer */ 646 #define MPI3_FUNCTION_DIAG_BUFFER_UPLOAD (0x83) /* Upload a Diagnostic Buffer */ 647 648 /* Miscellaneous functions */ 649 #define MPI3_FUNCTION_MIN_IOC_USE_ONLY (0xC0) /* Beginning of IOC Use Only range of function codes */ 650 #define MPI3_FUNCTION_MAX_IOC_USE_ONLY (0xEF) /* End of IOC Use Only range of function codes */ 651 #define MPI3_FUNCTION_MIN_PRODUCT_SPECIFIC (0xF0) /* Beginning of the product-specific range of function codes */ 652 #define MPI3_FUNCTION_MAX_PRODUCT_SPECIFIC (0xFF) /* End of the product-specific range of function codes */ 653 654 /**** Defines for IOCStatus ****/ 655 #define MPI3_IOCSTATUS_LOG_INFO_AVAIL_MASK (0x8000) 656 #define MPI3_IOCSTATUS_LOG_INFO_AVAILABLE (0x8000) 657 #define MPI3_IOCSTATUS_STATUS_MASK (0x7FFF) 658 659 /* Common IOCStatus values for all replies */ 660 #define MPI3_IOCSTATUS_SUCCESS (0x0000) 661 #define MPI3_IOCSTATUS_INVALID_FUNCTION (0x0001) 662 #define MPI3_IOCSTATUS_BUSY (0x0002) 663 #define MPI3_IOCSTATUS_INVALID_SGL (0x0003) 664 #define MPI3_IOCSTATUS_INTERNAL_ERROR (0x0004) 665 #define MPI3_IOCSTATUS_INSUFFICIENT_RESOURCES (0x0006) 666 #define MPI3_IOCSTATUS_INVALID_FIELD (0x0007) 667 #define MPI3_IOCSTATUS_INVALID_STATE (0x0008) 668 #define MPI3_IOCSTATUS_INSUFFICIENT_POWER (0x000A) 669 #define MPI3_IOCSTATUS_INVALID_CHANGE_COUNT (0x000B) 670 #define MPI3_IOCSTATUS_ALLOWED_CMD_BLOCK (0x000C) 671 #define MPI3_IOCSTATUS_SUPERVISOR_ONLY (0x000D) 672 #define MPI3_IOCSTATUS_FAILURE (0x001F) 673 674 /* Config IOCStatus values */ 675 #define MPI3_IOCSTATUS_CONFIG_INVALID_ACTION (0x0020) 676 #define MPI3_IOCSTATUS_CONFIG_INVALID_TYPE (0x0021) 677 #define MPI3_IOCSTATUS_CONFIG_INVALID_PAGE (0x0022) 678 #define MPI3_IOCSTATUS_CONFIG_INVALID_DATA (0x0023) 679 #define MPI3_IOCSTATUS_CONFIG_NO_DEFAULTS (0x0024) 680 #define MPI3_IOCSTATUS_CONFIG_CANT_COMMIT (0x0025) 681 682 /* SCSI IO IOCStatus values */ 683 #define MPI3_IOCSTATUS_SCSI_RECOVERED_ERROR (0x0040) 684 #define MPI3_IOCSTATUS_SCSI_TM_NOT_SUPPORTED (0x0041) 685 #define MPI3_IOCSTATUS_SCSI_INVALID_DEVHANDLE (0x0042) 686 #define MPI3_IOCSTATUS_SCSI_DEVICE_NOT_THERE (0x0043) 687 #define MPI3_IOCSTATUS_SCSI_DATA_OVERRUN (0x0044) 688 #define MPI3_IOCSTATUS_SCSI_DATA_UNDERRUN (0x0045) 689 #define MPI3_IOCSTATUS_SCSI_IO_DATA_ERROR (0x0046) 690 #define MPI3_IOCSTATUS_SCSI_PROTOCOL_ERROR (0x0047) 691 #define MPI3_IOCSTATUS_SCSI_TASK_TERMINATED (0x0048) 692 #define MPI3_IOCSTATUS_SCSI_RESIDUAL_MISMATCH (0x0049) 693 #define MPI3_IOCSTATUS_SCSI_TASK_MGMT_FAILED (0x004A) 694 #define MPI3_IOCSTATUS_SCSI_IOC_TERMINATED (0x004B) 695 #define MPI3_IOCSTATUS_SCSI_EXT_TERMINATED (0x004C) 696 697 /* SCSI Initiator and SCSI Target end-to-end data protection values */ 698 #define MPI3_IOCSTATUS_EEDP_GUARD_ERROR (0x004D) 699 #define MPI3_IOCSTATUS_EEDP_REF_TAG_ERROR (0x004E) 700 #define MPI3_IOCSTATUS_EEDP_APP_TAG_ERROR (0x004F) 701 702 /* SCSI Target IOCStatus values */ 703 #define MPI3_IOCSTATUS_TARGET_INVALID_IO_INDEX (0x0062) 704 #define MPI3_IOCSTATUS_TARGET_ABORTED (0x0063) 705 #define MPI3_IOCSTATUS_TARGET_NO_CONN_RETRYABLE (0x0064) 706 #define MPI3_IOCSTATUS_TARGET_NO_CONNECTION (0x0065) 707 #define MPI3_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH (0x006A) 708 #define MPI3_IOCSTATUS_TARGET_DATA_OFFSET_ERROR (0x006D) 709 #define MPI3_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA (0x006E) 710 #define MPI3_IOCSTATUS_TARGET_IU_TOO_SHORT (0x006F) 711 #define MPI3_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT (0x0070) 712 #define MPI3_IOCSTATUS_TARGET_NAK_RECEIVED (0x0071) 713 714 /* Serial Attached SCSI IOCStatus values */ 715 #define MPI3_IOCSTATUS_SAS_SMP_REQUEST_FAILED (0x0090) 716 #define MPI3_IOCSTATUS_SAS_SMP_DATA_OVERRUN (0x0091) 717 718 /* Diagnostic Buffer Post/Release IOCStatus values */ 719 #define MPI3_IOCSTATUS_DIAGNOSTIC_RELEASED (0x00A0) 720 721 /* Component Image Upload/Download */ 722 #define MPI3_IOCSTATUS_CI_UNSUPPORTED (0x00B0) 723 #define MPI3_IOCSTATUS_CI_UPDATE_SEQUENCE (0x00B1) 724 #define MPI3_IOCSTATUS_CI_VALIDATION_FAILED (0x00B2) 725 #define MPI3_IOCSTATUS_CI_KEY_UPDATE_PENDING (0x00B3) 726 #define MPI3_IOCSTATUS_CI_KEY_UPDATE_NOT_POSSIBLE (0x00B4) 727 728 /* Security values */ 729 #define MPI3_IOCSTATUS_SECURITY_KEY_REQUIRED (0x00C0) 730 #define MPI3_IOCSTATUS_SECURITY_VIOLATION (0x00C1) 731 732 /* Request and Reply Queues related IOCStatus values */ 733 #define MPI3_IOCSTATUS_INVALID_QUEUE_ID (0x0F00) 734 #define MPI3_IOCSTATUS_INVALID_QUEUE_SIZE (0x0F01) 735 #define MPI3_IOCSTATUS_INVALID_MSIX_VECTOR (0x0F02) 736 #define MPI3_IOCSTATUS_INVALID_REPLY_QUEUE_ID (0x0F03) 737 #define MPI3_IOCSTATUS_INVALID_QUEUE_DELETION (0x0F04) 738 739 /**** Defines for IOCLogInfo ****/ 740 #define MPI3_IOCLOGINFO_TYPE_MASK (0xF0000000) 741 #define MPI3_IOCLOGINFO_TYPE_SHIFT (28) 742 #define MPI3_IOCLOGINFO_TYPE_NONE (0x0) 743 #define MPI3_IOCLOGINFO_TYPE_SAS (0x3) 744 #define MPI3_IOCLOGINFO_LOG_DATA_MASK (0x0FFFFFFF) 745 746 #endif /* MPI30_TRANSPORT_H */ 747 748 749