1 /* 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2016-2024, Broadcom Inc. All rights reserved. 5 * Support: <fbsd-storage-driver.pdl@broadcom.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are 9 * met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation and/or other 15 * materials provided with the distribution. 16 * 3. Neither the name of the Broadcom Inc. nor the names of its contributors 17 * may be used to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 * 32 * The views and conclusions contained in the software and documentation are 33 * those of the authors and should not be interpreted as representing 34 * official policies,either expressed or implied, of the FreeBSD Project. 35 * 36 * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 37 * 38 * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD 39 * 40 */ 41 42 #ifndef MPI30_CNFG_H 43 #define MPI30_CNFG_H 1 44 45 /***************************************************************************** 46 * Configuration Page Types * 47 ****************************************************************************/ 48 #define MPI3_CONFIG_PAGETYPE_IO_UNIT (0x00) 49 #define MPI3_CONFIG_PAGETYPE_MANUFACTURING (0x01) 50 #define MPI3_CONFIG_PAGETYPE_IOC (0x02) 51 #define MPI3_CONFIG_PAGETYPE_DRIVER (0x03) 52 #define MPI3_CONFIG_PAGETYPE_SECURITY (0x04) 53 #define MPI3_CONFIG_PAGETYPE_ENCLOSURE (0x11) 54 #define MPI3_CONFIG_PAGETYPE_DEVICE (0x12) 55 #define MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT (0x20) 56 #define MPI3_CONFIG_PAGETYPE_SAS_EXPANDER (0x21) 57 #define MPI3_CONFIG_PAGETYPE_SAS_PHY (0x23) 58 #define MPI3_CONFIG_PAGETYPE_SAS_PORT (0x24) 59 #define MPI3_CONFIG_PAGETYPE_PCIE_IO_UNIT (0x30) 60 #define MPI3_CONFIG_PAGETYPE_PCIE_SWITCH (0x31) 61 #define MPI3_CONFIG_PAGETYPE_PCIE_LINK (0x33) 62 63 /***************************************************************************** 64 * Configuration Page Attributes * 65 ****************************************************************************/ 66 #define MPI3_CONFIG_PAGEATTR_MASK (0xF0) 67 #define MPI3_CONFIG_PAGEATTR_READ_ONLY (0x00) 68 #define MPI3_CONFIG_PAGEATTR_CHANGEABLE (0x10) 69 #define MPI3_CONFIG_PAGEATTR_PERSISTENT (0x20) 70 71 /***************************************************************************** 72 * Configuration Page Actions * 73 ****************************************************************************/ 74 #define MPI3_CONFIG_ACTION_PAGE_HEADER (0x00) 75 #define MPI3_CONFIG_ACTION_READ_DEFAULT (0x01) 76 #define MPI3_CONFIG_ACTION_READ_CURRENT (0x02) 77 #define MPI3_CONFIG_ACTION_WRITE_CURRENT (0x03) 78 #define MPI3_CONFIG_ACTION_READ_PERSISTENT (0x04) 79 #define MPI3_CONFIG_ACTION_WRITE_PERSISTENT (0x05) 80 81 /***************************************************************************** 82 * Configuration Page Addressing * 83 ****************************************************************************/ 84 85 /**** Device PageAddress Format ****/ 86 #define MPI3_DEVICE_PGAD_FORM_MASK (0xF0000000) 87 #define MPI3_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 88 #define MPI3_DEVICE_PGAD_FORM_HANDLE (0x20000000) 89 #define MPI3_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 90 91 /**** SAS Expander PageAddress Format ****/ 92 #define MPI3_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 93 #define MPI3_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 94 #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x10000000) 95 #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE (0x20000000) 96 #define MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 97 #define MPI3_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 98 #define MPI3_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 99 100 /**** SAS Phy PageAddress Format ****/ 101 #define MPI3_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 102 #define MPI3_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 103 #define MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 104 105 /**** SAS Port PageAddress Format ****/ 106 #define MPI3_SASPORT_PGAD_FORM_MASK (0xF0000000) 107 #define MPI3_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 108 #define MPI3_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 109 #define MPI3_SASPORT_PGAD_PORT_NUMBER_MASK (0x000000FF) 110 111 /**** Enclosure PageAddress Format ****/ 112 #define MPI3_ENCLOS_PGAD_FORM_MASK (0xF0000000) 113 #define MPI3_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 114 #define MPI3_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 115 #define MPI3_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 116 117 /**** PCIe Switch PageAddress Format ****/ 118 #define MPI3_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000) 119 #define MPI3_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 120 #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE_PORT_NUM (0x10000000) 121 #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE (0x20000000) 122 #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000) 123 #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) 124 #define MPI3_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF) 125 126 /**** PCIe Link PageAddress Format ****/ 127 #define MPI3_PCIE_LINK_PGAD_FORM_MASK (0xF0000000) 128 #define MPI3_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) 129 #define MPI3_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) 130 #define MPI3_PCIE_LINK_PGAD_LINKNUM_MASK (0x000000FF) 131 132 /**** Security PageAddress Format ****/ 133 #define MPI3_SECURITY_PGAD_FORM_MASK (0xF0000000) 134 #define MPI3_SECURITY_PGAD_FORM_GET_NEXT_SLOT (0x00000000) 135 #define MPI3_SECURITY_PGAD_FORM_SLOT_NUM (0x10000000) 136 #define MPI3_SECURITY_PGAD_SLOT_GROUP_MASK (0x0000FF00) 137 #define MPI3_SECURITY_PGAD_SLOT_GROUP_SHIFT (8) 138 #define MPI3_SECURITY_PGAD_SLOT_MASK (0x000000FF) 139 140 /***************************************************************************** 141 * Configuration Request Message * 142 ****************************************************************************/ 143 typedef struct _MPI3_CONFIG_REQUEST 144 { 145 U16 HostTag; /* 0x00 */ 146 U8 IOCUseOnly02; /* 0x02 */ 147 U8 Function; /* 0x03 */ 148 U16 IOCUseOnly04; /* 0x04 */ 149 U8 IOCUseOnly06; /* 0x06 */ 150 U8 MsgFlags; /* 0x07 */ 151 U16 ChangeCount; /* 0x08 */ 152 U16 Reserved0A; /* 0x0A */ 153 U8 PageVersion; /* 0x0C */ 154 U8 PageNumber; /* 0x0D */ 155 U8 PageType; /* 0x0E */ 156 U8 Action; /* 0x0F */ 157 U32 PageAddress; /* 0x10 */ 158 U16 PageLength; /* 0x14 */ 159 U16 Reserved16; /* 0x16 */ 160 U32 Reserved18[2]; /* 0x18 */ 161 MPI3_SGE_UNION SGL; /* 0x20 */ 162 } MPI3_CONFIG_REQUEST, MPI3_POINTER PTR_MPI3_CONFIG_REQUEST, 163 Mpi3ConfigRequest_t, MPI3_POINTER pMpi3ConfigRequest_t; 164 165 /***************************************************************************** 166 * Configuration Pages * 167 ****************************************************************************/ 168 169 /***************************************************************************** 170 * Configuration Page Header * 171 ****************************************************************************/ 172 typedef struct _MPI3_CONFIG_PAGE_HEADER 173 { 174 U8 PageVersion; /* 0x00 */ 175 U8 Reserved01; /* 0x01 */ 176 U8 PageNumber; /* 0x02 */ 177 U8 PageAttribute; /* 0x03 */ 178 U16 PageLength; /* 0x04 */ 179 U8 PageType; /* 0x06 */ 180 U8 Reserved07; /* 0x07 */ 181 } MPI3_CONFIG_PAGE_HEADER, MPI3_POINTER PTR_MPI3_CONFIG_PAGE_HEADER, 182 Mpi3ConfigPageHeader_t, MPI3_POINTER pMpi3ConfigPageHeader_t; 183 184 /***************************************************************************** 185 * Common definitions used by Configuration Pages * 186 ****************************************************************************/ 187 188 /**** Defines for NegotiatedLinkRates ****/ 189 #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_MASK (0xF0) 190 #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_SHIFT (4) 191 #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_MASK (0x0F) 192 #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_SHIFT (0) 193 /*** Below defines are used in both the PhysicalLinkRate and ***/ 194 /*** LogicalLinkRate fields above. ***/ 195 /*** (by applying the proper _SHIFT value) ***/ 196 #define MPI3_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 197 #define MPI3_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 198 #define MPI3_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 199 #define MPI3_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 200 #define MPI3_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 201 #define MPI3_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 202 #define MPI3_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 203 #define MPI3_SAS_NEG_LINK_RATE_1_5 (0x08) 204 #define MPI3_SAS_NEG_LINK_RATE_3_0 (0x09) 205 #define MPI3_SAS_NEG_LINK_RATE_6_0 (0x0A) 206 #define MPI3_SAS_NEG_LINK_RATE_12_0 (0x0B) 207 #define MPI3_SAS_NEG_LINK_RATE_22_5 (0x0C) 208 209 /**** Defines for the AttachedPhyInfo field ****/ 210 #define MPI3_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 211 #define MPI3_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 212 #define MPI3_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 213 214 #define MPI3_SAS_APHYINFO_REASON_MASK (0x0000000F) 215 #define MPI3_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 216 #define MPI3_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 217 #define MPI3_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 218 #define MPI3_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 219 #define MPI3_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 220 #define MPI3_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 221 #define MPI3_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 222 #define MPI3_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 223 #define MPI3_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 224 #define MPI3_SAS_APHYINFO_REASON_EXP_REDUCED_FUNC (0x00000009) 225 226 /**** Defines for the PhyInfo field ****/ 227 #define MPI3_SAS_PHYINFO_STATUS_MASK (0xC0000000) 228 #define MPI3_SAS_PHYINFO_STATUS_SHIFT (30) 229 #define MPI3_SAS_PHYINFO_STATUS_ACCESSIBLE (0x00000000) 230 #define MPI3_SAS_PHYINFO_STATUS_NOT_EXIST (0x40000000) 231 #define MPI3_SAS_PHYINFO_STATUS_VACANT (0x80000000) 232 233 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 234 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_ACTIVE (0x00000000) 235 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_PARTIAL (0x08000000) 236 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SLUMBER (0x10000000) 237 238 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_MASK (0x04000000) 239 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_SHIFT (26) 240 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_MASK (0x02000000) 241 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_SHIFT (25) 242 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_MASK (0x01000000) 243 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_SHIFT (24) 244 245 #define MPI3_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 246 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_WITHIN (0x00200000) 247 #define MPI3_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 248 249 #define MPI3_SAS_PHYINFO_REASON_MASK (0x000F0000) 250 #define MPI3_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 251 #define MPI3_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 252 #define MPI3_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 253 #define MPI3_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 254 #define MPI3_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 255 #define MPI3_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 256 #define MPI3_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 257 #define MPI3_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 258 #define MPI3_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 259 #define MPI3_SAS_PHYINFO_REASON_EXP_REDUCED_FUNC (0x00090000) 260 261 #define MPI3_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 262 #define MPI3_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 263 #define MPI3_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 264 265 #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_MASK (0x00000F00) 266 #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_SHIFT (8) 267 268 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_MASK (0x000000F0) 269 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_DIRECT (0x00000000) 270 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_SUBTRACTIVE (0x00000010) 271 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_TABLE (0x00000020) 272 273 /**** Defines for the ProgrammedLinkRate field ****/ 274 #define MPI3_SAS_PRATE_MAX_RATE_MASK (0xF0) 275 #define MPI3_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 276 #define MPI3_SAS_PRATE_MAX_RATE_1_5 (0x80) 277 #define MPI3_SAS_PRATE_MAX_RATE_3_0 (0x90) 278 #define MPI3_SAS_PRATE_MAX_RATE_6_0 (0xA0) 279 #define MPI3_SAS_PRATE_MAX_RATE_12_0 (0xB0) 280 #define MPI3_SAS_PRATE_MAX_RATE_22_5 (0xC0) 281 #define MPI3_SAS_PRATE_MIN_RATE_MASK (0x0F) 282 #define MPI3_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 283 #define MPI3_SAS_PRATE_MIN_RATE_1_5 (0x08) 284 #define MPI3_SAS_PRATE_MIN_RATE_3_0 (0x09) 285 #define MPI3_SAS_PRATE_MIN_RATE_6_0 (0x0A) 286 #define MPI3_SAS_PRATE_MIN_RATE_12_0 (0x0B) 287 #define MPI3_SAS_PRATE_MIN_RATE_22_5 (0x0C) 288 289 /**** Defines for the HwLinkRate field ****/ 290 #define MPI3_SAS_HWRATE_MAX_RATE_MASK (0xF0) 291 #define MPI3_SAS_HWRATE_MAX_RATE_1_5 (0x80) 292 #define MPI3_SAS_HWRATE_MAX_RATE_3_0 (0x90) 293 #define MPI3_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 294 #define MPI3_SAS_HWRATE_MAX_RATE_12_0 (0xB0) 295 #define MPI3_SAS_HWRATE_MAX_RATE_22_5 (0xC0) 296 #define MPI3_SAS_HWRATE_MIN_RATE_MASK (0x0F) 297 #define MPI3_SAS_HWRATE_MIN_RATE_1_5 (0x08) 298 #define MPI3_SAS_HWRATE_MIN_RATE_3_0 (0x09) 299 #define MPI3_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 300 #define MPI3_SAS_HWRATE_MIN_RATE_12_0 (0x0B) 301 #define MPI3_SAS_HWRATE_MIN_RATE_22_5 (0x0C) 302 303 /**** Defines for the Slot field ****/ 304 #define MPI3_SLOT_INVALID (0xFFFF) 305 306 /**** Defines for the SlotIndex field ****/ 307 #define MPI3_SLOT_INDEX_INVALID (0xFFFF) 308 309 /**** Defines for the LinkChangeCount fields ****/ 310 #define MPI3_LINK_CHANGE_COUNT_INVALID (0xFFFF) 311 312 /**** Defines for the RateChangeCount fields ****/ 313 #define MPI3_RATE_CHANGE_COUNT_INVALID (0xFFFF) 314 315 /**** Defines for the Temp Sensor Location field ****/ 316 #define MPI3_TEMP_SENSOR_LOCATION_INTERNAL (0x0) 317 #define MPI3_TEMP_SENSOR_LOCATION_INLET (0x1) 318 #define MPI3_TEMP_SENSOR_LOCATION_OUTLET (0x2) 319 #define MPI3_TEMP_SENSOR_LOCATION_DRAM (0x3) 320 321 /***************************************************************************** 322 * Manufacturing Configuration Pages * 323 ****************************************************************************/ 324 325 #define MPI3_MFGPAGE_VENDORID_BROADCOM (0x1000) 326 327 /* MPI v3.0 SAS Products */ 328 #define MPI3_MFGPAGE_DEVID_SAS4116 (0x00A5) 329 #define MPI3_MFGPAGE_DEVID_SAS5116_MPI (0x00B3) 330 #define MPI3_MFGPAGE_DEVID_SAS5116_NVME (0x00B4) 331 #define MPI3_MFGPAGE_DEVID_SAS5116_MPI_NS (0x00B5) 332 #define MPI3_MFGPAGE_DEVID_SAS5116_NVME_NS (0x00B6) 333 #define MPI3_MFGPAGE_DEVID_SAS5116_PCIE_SWITCH (0x00B8) 334 335 /***************************************************************************** 336 * Manufacturing Page 0 * 337 ****************************************************************************/ 338 typedef struct _MPI3_MAN_PAGE0 339 { 340 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 341 U8 ChipRevision[8]; /* 0x08 */ 342 U8 ChipName[32]; /* 0x10 */ 343 U8 BoardName[32]; /* 0x30 */ 344 U8 BoardAssembly[32]; /* 0x50 */ 345 U8 BoardTracerNumber[32]; /* 0x70 */ 346 U32 BoardPower; /* 0x90 */ 347 U32 Reserved94; /* 0x94 */ 348 U32 Reserved98; /* 0x98 */ 349 U8 OEM; /* 0x9C */ 350 U8 ProfileIdentifier; /* 0x9D */ 351 U16 Flags; /* 0x9E */ 352 U8 BoardMfgDay; /* 0xA0 */ 353 U8 BoardMfgMonth; /* 0xA1 */ 354 U16 BoardMfgYear; /* 0xA2 */ 355 U8 BoardReworkDay; /* 0xA4 */ 356 U8 BoardReworkMonth; /* 0xA5 */ 357 U16 BoardReworkYear; /* 0xA6 */ 358 U8 BoardRevision[8]; /* 0xA8 */ 359 U8 EPackFRU[16]; /* 0xB0 */ 360 U8 ProductName[256]; /* 0xC0 */ 361 } MPI3_MAN_PAGE0, MPI3_POINTER PTR_MPI3_MAN_PAGE0, 362 Mpi3ManPage0_t, MPI3_POINTER pMpi3ManPage0_t; 363 364 /**** Defines for the PageVersion field ****/ 365 #define MPI3_MAN0_PAGEVERSION (0x00) 366 367 /**** Defines for the Flags field ****/ 368 #define MPI3_MAN0_FLAGS_SWITCH_PRESENT (0x0002) 369 #define MPI3_MAN0_FLAGS_EXPANDER_PRESENT (0x0001) 370 371 /***************************************************************************** 372 * Manufacturing Page 1 * 373 ****************************************************************************/ 374 375 #define MPI3_MAN1_VPD_SIZE (512) 376 377 typedef struct _MPI3_MAN_PAGE1 378 { 379 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 380 U32 Reserved08[2]; /* 0x08 */ 381 U8 VPD[MPI3_MAN1_VPD_SIZE]; /* 0x10 */ 382 } MPI3_MAN_PAGE1, MPI3_POINTER PTR_MPI3_MAN_PAGE1, 383 Mpi3ManPage1_t, MPI3_POINTER pMpi3ManPage1_t; 384 385 /**** Defines for the PageVersion field ****/ 386 #define MPI3_MAN1_PAGEVERSION (0x00) 387 388 389 /***************************************************************************** 390 * Manufacturing Page 2 * 391 ****************************************************************************/ 392 393 typedef struct _MPI3_MAN_PAGE2 394 { 395 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 396 U8 Flags; /* 0x08 */ 397 U8 Reserved09[3]; /* 0x09 */ 398 U32 Reserved0C[3]; /* 0x0C */ 399 U8 OEMBoardTracerNumber[32]; /* 0x18 */ 400 } MPI3_MAN_PAGE2, MPI3_POINTER PTR_MPI3_MAN_PAGE2, 401 Mpi3ManPage2_t, MPI3_POINTER pMpi3ManPage2_t; 402 403 /**** Defines for the PageVersion field ****/ 404 #define MPI3_MAN2_PAGEVERSION (0x00) 405 406 /**** Defines for the Flags field ****/ 407 #define MPI3_MAN2_FLAGS_TRACER_PRESENT (0x01) 408 409 /***************************************************************************** 410 * Manufacturing Page 5 * 411 ****************************************************************************/ 412 typedef struct _MPI3_MAN5_PHY_ENTRY 413 { 414 U64 IOC_WWID; /* 0x00 */ 415 U64 DeviceName; /* 0x08 */ 416 U64 SATA_WWID; /* 0x10 */ 417 } MPI3_MAN5_PHY_ENTRY, MPI3_POINTER PTR_MPI3_MAN5_PHY_ENTRY, 418 Mpi3Man5PhyEntry_t, MPI3_POINTER pMpi3Man5PhyEntry_t; 419 420 #ifndef MPI3_MAN5_PHY_MAX 421 #define MPI3_MAN5_PHY_MAX (1) 422 #endif /* MPI3_MAN5_PHY_MAX */ 423 424 typedef struct _MPI3_MAN_PAGE5 425 { 426 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 427 U8 NumPhys; /* 0x08 */ 428 U8 Reserved09[3]; /* 0x09 */ 429 U32 Reserved0C; /* 0x0C */ 430 MPI3_MAN5_PHY_ENTRY Phy[MPI3_MAN5_PHY_MAX]; /* 0x10 */ 431 } MPI3_MAN_PAGE5, MPI3_POINTER PTR_MPI3_MAN_PAGE5, 432 Mpi3ManPage5_t, MPI3_POINTER pMpi3ManPage5_t; 433 434 /**** Defines for the PageVersion field ****/ 435 #define MPI3_MAN5_PAGEVERSION (0x00) 436 437 /***************************************************************************** 438 * Manufacturing Page 6 * 439 ****************************************************************************/ 440 typedef struct _MPI3_MAN6_GPIO_ENTRY 441 { 442 U8 FunctionCode; /* 0x00 */ 443 U8 FunctionFlags; /* 0x01 */ 444 U16 Flags; /* 0x02 */ 445 U8 Param1; /* 0x04 */ 446 U8 Param2; /* 0x05 */ 447 U16 Reserved06; /* 0x06 */ 448 U32 Param3; /* 0x08 */ 449 } MPI3_MAN6_GPIO_ENTRY, MPI3_POINTER PTR_MPI3_MAN6_GPIO_ENTRY, 450 Mpi3Man6GpioEntry_t, MPI3_POINTER pMpi3Man6GpioEntry_t; 451 452 /**** Defines for the FunctionCode field ****/ 453 #define MPI3_MAN6_GPIO_FUNCTION_GENERIC (0x00) 454 #define MPI3_MAN6_GPIO_FUNCTION_ALTERNATE (0x01) 455 #define MPI3_MAN6_GPIO_FUNCTION_EXT_INTERRUPT (0x02) 456 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_ACTIVITY (0x03) 457 #define MPI3_MAN6_GPIO_FUNCTION_OVER_TEMPERATURE (0x04) 458 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_GREEN (0x05) 459 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_YELLOW (0x06) 460 #define MPI3_MAN6_GPIO_FUNCTION_CABLE_MANAGEMENT (0x07) 461 #define MPI3_MAN6_GPIO_FUNCTION_BKPLANE_MGMT_TYPE (0x08) 462 #define MPI3_MAN6_GPIO_FUNCTION_ISTWI_RESET (0x0A) 463 #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET (0x0B) 464 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_FAULT (0x0C) 465 #define MPI3_MAN6_GPIO_FUNCTION_PBLP_STATUS_CHANGE (0x0D) 466 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_ONLINE (0x0E) 467 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_FAULT (0x0F) 468 #define MPI3_MAN6_GPIO_FUNCTION_CTRL_TYPE (0x10) 469 #define MPI3_MAN6_GPIO_FUNCTION_LICENSE (0x11) 470 #define MPI3_MAN6_GPIO_FUNCTION_REFCLK_CONTROL (0x12) 471 #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET_CLAMP (0x13) 472 #define MPI3_MAN6_GPIO_FUNCTION_AUXILIARY_POWER (0x14) 473 #define MPI3_MAN6_GPIO_FUNCTION_RAID_DATA_CACHE_DIRTY (0x15) 474 #define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_CONTROL (0x16) 475 #define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_FAULT (0x17) 476 #define MPI3_MAN6_GPIO_FUNCTION_POWER_BRAKE (0x18) 477 #define MPI3_MAN6_GPIO_FUNCTION_MGMT_CONTROLLER_RESET (0x19) 478 479 /**** Defines for FunctionFlags when FunctionCode is ISTWI_RESET ****/ 480 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_MASK (0x01) 481 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_ISTWI (0x00) 482 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_RECEPTACLEID (0x01) 483 484 /**** Defines for Param1 (Flags) when FunctionCode is EXT_INTERRUPT ****/ 485 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_MASK (0xF0) 486 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_GENERIC (0x00) 487 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_CABLE_MGMT (0x10) 488 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_ACTIVE_CABLE_OVERCURRENT (0x20) 489 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_ACK_REQUIRED (0x02) 490 491 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK (0x01) 492 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE (0x00) 493 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL (0x01) 494 495 /**** Defines for Param1 (PHY STATE) when FunctionCode is PORT_STATUS_GREEN ****/ 496 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ALL_UP (0x00) 497 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ONE_OR_MORE_UP (0x01) 498 499 /**** Defines for Param1 (INTERFACE_SIGNAL) when FunctionCode is CABLE_MANAGEMENT ****/ 500 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_MODULE_PRESENT (0x00) 501 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_ACTIVE_CABLE_ENABLE (0x01) 502 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_CABLE_MGMT_ENABLE (0x02) 503 504 /**** Defines for Param1 (LICENSE_TYPE) when FunctionCode is LICENSE ****/ 505 #define MPI3_MAN6_GPIO_LICENSE_PARAM1_TYPE_IBUTTON (0x00) 506 507 508 /**** Defines for the Flags field ****/ 509 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_MASK (0x0100) 510 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_FAST_EDGE (0x0100) 511 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_SLOW_EDGE (0x0000) 512 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_MASK (0x00C0) 513 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_100OHM (0x0000) 514 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_66OHM (0x0040) 515 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_50OHM (0x0080) 516 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_33OHM (0x00C0) 517 #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_MASK (0x0030) 518 #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_SHIFT (4) 519 #define MPI3_MAN6_GPIO_FLAGS_ACTIVE_HIGH (0x0008) 520 #define MPI3_MAN6_GPIO_FLAGS_BI_DIR_ENABLED (0x0004) 521 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_MASK (0x0003) 522 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_INPUT (0x0000) 523 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_DRAIN_OUTPUT (0x0001) 524 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_SOURCE_OUTPUT (0x0002) 525 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_PUSH_PULL_OUTPUT (0x0003) 526 527 #ifndef MPI3_MAN6_GPIO_MAX 528 #define MPI3_MAN6_GPIO_MAX (1) 529 #endif /* MPI3_MAN6_GPIO_MAX */ 530 531 typedef struct _MPI3_MAN_PAGE6 532 { 533 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 534 U16 Flags; /* 0x08 */ 535 U16 Reserved0A; /* 0x0A */ 536 U8 NumGPIO; /* 0x0C */ 537 U8 Reserved0D[3]; /* 0x0D */ 538 MPI3_MAN6_GPIO_ENTRY GPIO[MPI3_MAN6_GPIO_MAX]; /* 0x10 */ 539 } MPI3_MAN_PAGE6, MPI3_POINTER PTR_MPI3_MAN_PAGE6, 540 Mpi3ManPage6_t, MPI3_POINTER pMpi3ManPage6_t; 541 542 /**** Defines for the PageVersion field ****/ 543 #define MPI3_MAN6_PAGEVERSION (0x00) 544 545 /**** Defines for the Flags field ****/ 546 #define MPI3_MAN6_FLAGS_HEARTBEAT_LED_DISABLED (0x0001) 547 548 /***************************************************************************** 549 * Manufacturing Page 7 * 550 ****************************************************************************/ 551 typedef struct _MPI3_MAN7_RECEPTACLE_INFO 552 { 553 U32 Name[4]; /* 0x00 */ 554 U8 Location; /* 0x10 */ 555 U8 ConnectorType; /* 0x11 */ 556 U8 PEDClk; /* 0x12 */ 557 U8 ConnectorID; /* 0x13 */ 558 U32 Reserved14; /* 0x14 */ 559 } MPI3_MAN7_RECEPTACLE_INFO, MPI3_POINTER PTR_MPI3_MAN7_RECEPTACLE_INFO, 560 Mpi3Man7ReceptacleInfo_t, MPI3_POINTER pMpi3Man7ReceptacleInfo_t; 561 562 /**** Defines for Location field ****/ 563 #define MPI3_MAN7_LOCATION_UNKNOWN (0x00) 564 #define MPI3_MAN7_LOCATION_INTERNAL (0x01) 565 #define MPI3_MAN7_LOCATION_EXTERNAL (0x02) 566 #define MPI3_MAN7_LOCATION_VIRTUAL (0x03) 567 #define MPI3_MAN7_LOCATION_HOST (0x04) 568 569 /**** Defines for ConnectorType - Use definitions from SES-4 ****/ 570 #define MPI3_MAN7_CONNECTOR_TYPE_NO_INFO (0x00) 571 572 /**** Defines for PEDClk field ****/ 573 #define MPI3_MAN7_PEDCLK_ROUTING_MASK (0x10) 574 #define MPI3_MAN7_PEDCLK_ROUTING_DIRECT (0x00) 575 #define MPI3_MAN7_PEDCLK_ROUTING_CLOCK_BUFFER (0x10) 576 #define MPI3_MAN7_PEDCLK_ID_MASK (0x0F) 577 578 #ifndef MPI3_MAN7_RECEPTACLE_INFO_MAX 579 #define MPI3_MAN7_RECEPTACLE_INFO_MAX (1) 580 #endif /* MPI3_MAN7_RECEPTACLE_INFO_MAX */ 581 582 typedef struct _MPI3_MAN_PAGE7 583 { 584 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 585 U32 Flags; /* 0x08 */ 586 U8 NumReceptacles; /* 0x0C */ 587 U8 Reserved0D[3]; /* 0x0D */ 588 U32 EnclosureName[4]; /* 0x10 */ 589 MPI3_MAN7_RECEPTACLE_INFO ReceptacleInfo[MPI3_MAN7_RECEPTACLE_INFO_MAX]; /* 0x20 */ /* variable length array */ 590 } MPI3_MAN_PAGE7, MPI3_POINTER PTR_MPI3_MAN_PAGE7, 591 Mpi3ManPage7_t, MPI3_POINTER pMpi3ManPage7_t; 592 593 /**** Defines for the PageVersion field ****/ 594 #define MPI3_MAN7_PAGEVERSION (0x00) 595 596 /**** Defines for Flags field ****/ 597 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_MASK (0x01) 598 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_0 (0x00) 599 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_1 (0x01) 600 601 602 /***************************************************************************** 603 * Manufacturing Page 8 * 604 ****************************************************************************/ 605 606 typedef struct _MPI3_MAN8_PHY_INFO 607 { 608 U8 ReceptacleID; /* 0x00 */ 609 U8 ConnectorLane; /* 0x01 */ 610 U16 Reserved02; /* 0x02 */ 611 U16 Slotx1; /* 0x04 */ 612 U16 Slotx2; /* 0x06 */ 613 U16 Slotx4; /* 0x08 */ 614 U16 Reserved0A; /* 0x0A */ 615 U32 Reserved0C; /* 0x0C */ 616 } MPI3_MAN8_PHY_INFO, MPI3_POINTER PTR_MPI3_MAN8_PHY_INFO, 617 Mpi3Man8PhyInfo_t, MPI3_POINTER pMpi3Man8PhyInfo_t; 618 619 /**** Defines for ReceptacleID field ****/ 620 #define MPI3_MAN8_PHY_INFO_RECEPTACLE_ID_NOT_ASSOCIATED (0xFF) 621 622 /**** Defines for ConnectorLane field ****/ 623 #define MPI3_MAN8_PHY_INFO_CONNECTOR_LANE_NOT_ASSOCIATED (0xFF) 624 625 #ifndef MPI3_MAN8_PHY_INFO_MAX 626 #define MPI3_MAN8_PHY_INFO_MAX (1) 627 #endif /* MPI3_MAN8_PHY_INFO_MAX */ 628 629 typedef struct _MPI3_MAN_PAGE8 630 { 631 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 632 U32 Reserved08; /* 0x08 */ 633 U8 NumPhys; /* 0x0C */ 634 U8 Reserved0D[3]; /* 0x0D */ 635 MPI3_MAN8_PHY_INFO PhyInfo[MPI3_MAN8_PHY_INFO_MAX]; /* 0x10 */ /* variable length array */ 636 } MPI3_MAN_PAGE8, MPI3_POINTER PTR_MPI3_MAN_PAGE8, 637 Mpi3ManPage8_t, MPI3_POINTER pMpi3ManPage8_t; 638 639 /**** Defines for the PageVersion field ****/ 640 #define MPI3_MAN8_PAGEVERSION (0x00) 641 642 /***************************************************************************** 643 * Manufacturing Page 9 * 644 ****************************************************************************/ 645 typedef struct _MPI3_MAN9_RSRC_ENTRY 646 { 647 U32 Maximum; /* 0x00 */ 648 U32 Decrement; /* 0x04 */ 649 U32 Minimum; /* 0x08 */ 650 U32 Actual; /* 0x0C */ 651 } MPI3_MAN9_RSRC_ENTRY, MPI3_POINTER PTR_MPI3_MAN9_RSRC_ENTRY, 652 Mpi3Man9RsrcEntry_t, MPI3_POINTER pMpi3Man9RsrcEntry_t; 653 654 typedef enum _MPI3_MAN9_RESOURCES 655 { 656 MPI3_MAN9_RSRC_OUTSTANDING_REQS = 0, 657 MPI3_MAN9_RSRC_TARGET_CMDS = 1, 658 MPI3_MAN9_RSRC_RESERVED02 = 2, 659 MPI3_MAN9_RSRC_NVME = 3, 660 MPI3_MAN9_RSRC_INITIATORS = 4, 661 MPI3_MAN9_RSRC_VDS = 5, 662 MPI3_MAN9_RSRC_ENCLOSURES = 6, 663 MPI3_MAN9_RSRC_ENCLOSURE_PHYS = 7, 664 MPI3_MAN9_RSRC_EXPANDERS = 8, 665 MPI3_MAN9_RSRC_PCIE_SWITCHES = 9, 666 MPI3_MAN9_RSRC_RESERVED10 = 10, 667 MPI3_MAN9_RSRC_HOST_PD_DRIVES = 11, 668 MPI3_MAN9_RSRC_ADV_HOST_PD_DRIVES = 12, 669 MPI3_MAN9_RSRC_RAID_PD_DRIVES = 13, 670 MPI3_MAN9_RSRC_DRV_DIAG_BUF = 14, 671 MPI3_MAN9_RSRC_NAMESPACE_COUNT = 15, 672 MPI3_MAN9_RSRC_NUM_RESOURCES 673 } MPI3_MAN9_RESOURCES; 674 675 #define MPI3_MAN9_MIN_OUTSTANDING_REQS (1) 676 #define MPI3_MAN9_MAX_OUTSTANDING_REQS (65000) 677 678 #define MPI3_MAN9_MIN_TARGET_CMDS (0) 679 #define MPI3_MAN9_MAX_TARGET_CMDS (65535) 680 681 #define MPI3_MAN9_MIN_NVME_TARGETS (0) 682 /* Max NVMe Targets is product specific */ 683 684 #define MPI3_MAN9_MIN_INITIATORS (0) 685 /* Max Initiators is product specific */ 686 687 #define MPI3_MAN9_MIN_VDS (0) 688 /* Max VDs is product specific */ 689 690 #define MPI3_MAN9_MIN_ENCLOSURES (1) 691 #define MPI3_MAN9_MAX_ENCLOSURES (65535) 692 693 #define MPI3_MAN9_MIN_ENCLOSURE_PHYS (0) 694 /* Max Enclosure Phys is product specific */ 695 696 #define MPI3_MAN9_MIN_EXPANDERS (0) 697 #define MPI3_MAN9_MAX_EXPANDERS (65535) 698 699 #define MPI3_MAN9_MIN_PCIE_SWITCHES (0) 700 /* Max PCIe Switches is product specific */ 701 702 #define MPI3_MAN9_MIN_HOST_PD_DRIVES (0) 703 /* Max Host PD Drives is product specific */ 704 705 #define MPI3_MAN9_ADV_HOST_PD_DRIVES (0) 706 /* Max Advanced Host PD Drives is product specific */ 707 708 #define MPI3_MAN9_RAID_PD_DRIVES (0) 709 /* Max RAID PD Drives is product specific */ 710 711 #define MPI3_MAN9_DRIVER_DIAG_BUFFER (0) 712 /* Max Driver Diag Buffer is product specific */ 713 714 #define MPI3_MAN9_MIN_NAMESPACE_COUNT (1) 715 716 #define MPI3_MAN9_MIN_EXPANDERS (0) 717 #define MPI3_MAN9_MAX_EXPANDERS (65535) 718 719 720 typedef struct _MPI3_MAN_PAGE9 721 { 722 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 723 U8 NumResources; /* 0x08 */ 724 U8 Reserved09; /* 0x09 */ 725 U16 Reserved0A; /* 0x0A */ 726 U32 Reserved0C; /* 0x0C */ 727 U32 Reserved10; /* 0x10 */ 728 U32 Reserved14; /* 0x14 */ 729 U32 Reserved18; /* 0x18 */ 730 U32 Reserved1C; /* 0x1C */ 731 MPI3_MAN9_RSRC_ENTRY Resource[MPI3_MAN9_RSRC_NUM_RESOURCES]; /* 0x20 */ 732 } MPI3_MAN_PAGE9, MPI3_POINTER PTR_MPI3_MAN_PAGE9, 733 Mpi3ManPage9_t, MPI3_POINTER pMpi3ManPage9_t; 734 735 /**** Defines for the PageVersion field ****/ 736 #define MPI3_MAN9_PAGEVERSION (0x00) 737 738 /***************************************************************************** 739 * Manufacturing Page 10 * 740 ****************************************************************************/ 741 typedef struct _MPI3_MAN10_ISTWI_CTRLR_ENTRY 742 { 743 U16 TargetAddress; /* 0x00 */ 744 U16 Flags; /* 0x02 */ 745 U8 SCLLowOverride; /* 0x04 */ 746 U8 SCLHighOverride; /* 0x05 */ 747 U16 Reserved06; /* 0x06 */ 748 } MPI3_MAN10_ISTWI_CTRLR_ENTRY, MPI3_POINTER PTR_MPI3_MAN10_ISTWI_CTRLR_ENTRY, 749 Mpi3Man10IstwiCtrlrEntry_t, MPI3_POINTER pMpi3Man10IstwiCtrlrEntry_t; 750 751 /**** Defines for the Flags field ****/ 752 753 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_MASK (0xC000) 754 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_SHIFT (14) 755 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_50_NS (0x0000) 756 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_10_NS (0x4000) 757 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_5_NS (0x8000) 758 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_0_NS (0xC000) 759 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_MASK (0x3000) 760 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_SHIFT (12) 761 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_I2C (0x0000) 762 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_I3C (0x1000) 763 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_AUTO (0x2000) 764 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_MASK (0x0E00) 765 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_SHIFT (9) 766 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_12_5_MHZ (0x0000) 767 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_8_MHZ (0x0200) 768 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_6_MHZ (0x0400) 769 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_4_MHZ (0x0600) 770 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_2_MHZ (0x0800) 771 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK (0x000C) 772 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_SHIFT (0) 773 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_100_KHZ (0x0000) 774 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_400_KHZ (0x0004) 775 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_TARGET_ENABLED (0x0002) 776 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_INITIATOR_ENABLED (0x0001) 777 778 #ifndef MPI3_MAN10_ISTWI_CTRLR_MAX 779 #define MPI3_MAN10_ISTWI_CTRLR_MAX (1) 780 #endif /* MPI3_MAN10_ISTWI_CTRLR_MAX */ 781 782 typedef struct _MPI3_MAN_PAGE10 783 { 784 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 785 U32 Reserved08; /* 0x08 */ 786 U8 NumISTWICtrl; /* 0x0C */ 787 U8 Reserved0D[3]; /* 0x0D */ 788 MPI3_MAN10_ISTWI_CTRLR_ENTRY ISTWIController[MPI3_MAN10_ISTWI_CTRLR_MAX]; /* 0x10 */ 789 } MPI3_MAN_PAGE10, MPI3_POINTER PTR_MPI3_MAN_PAGE10, 790 Mpi3ManPage10_t, MPI3_POINTER pMpi3ManPage10_t; 791 792 /**** Defines for the PageVersion field ****/ 793 #define MPI3_MAN10_PAGEVERSION (0x00) 794 795 /***************************************************************************** 796 * Manufacturing Page 11 * 797 ****************************************************************************/ 798 typedef struct _MPI3_MAN11_MUX_DEVICE_FORMAT 799 { 800 U8 MaxChannel; /* 0x00 */ 801 U8 Reserved01[3]; /* 0x01 */ 802 U32 Reserved04; /* 0x04 */ 803 } MPI3_MAN11_MUX_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_MUX_DEVICE_FORMAT, 804 Mpi3Man11MuxDeviceFormat_t, MPI3_POINTER pMpi3Man11MuxDeviceFormat_t; 805 806 typedef struct _MPI3_MAN11_TEMP_SENSOR_DEVICE_FORMAT 807 { 808 U8 Type; /* 0x00 */ 809 U8 Reserved01[3]; /* 0x01 */ 810 U8 TempChannel[4]; /* 0x04 */ 811 } MPI3_MAN11_TEMP_SENSOR_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_TEMP_SENSOR_DEVICE_FORMAT, 812 Mpi3Man11TempSensorDeviceFormat_t, MPI3_POINTER pMpi3Man11TempSensorDeviceFormat_t; 813 814 /**** Defines for the Type field ****/ 815 #define MPI3_MAN11_TEMP_SENSOR_TYPE_MAX6654 (0x00) 816 #define MPI3_MAN11_TEMP_SENSOR_TYPE_EMC1442 (0x01) 817 #define MPI3_MAN11_TEMP_SENSOR_TYPE_ADT7476 (0x02) 818 #define MPI3_MAN11_TEMP_SENSOR_TYPE_SE97B (0x03) 819 820 /**** Define for the TempChannel field ****/ 821 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_MASK (0xE0) 822 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_SHIFT (5) 823 /**** for the Location field values - use MPI3_TEMP_SENSOR_LOCATION_ defines ****/ 824 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_ENABLED (0x01) 825 826 827 typedef struct _MPI3_MAN11_SEEPROM_DEVICE_FORMAT 828 { 829 U8 Size; /* 0x00 */ 830 U8 PageWriteSize; /* 0x01 */ 831 U16 Reserved02; /* 0x02 */ 832 U32 Reserved04; /* 0x04 */ 833 } MPI3_MAN11_SEEPROM_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_SEEPROM_DEVICE_FORMAT, 834 Mpi3Man11SeepromDeviceFormat_t, MPI3_POINTER pMpi3Man11SeepromDeviceFormat_t; 835 836 /**** Defines for the Size field ****/ 837 #define MPI3_MAN11_SEEPROM_SIZE_1KBITS (0x01) 838 #define MPI3_MAN11_SEEPROM_SIZE_2KBITS (0x02) 839 #define MPI3_MAN11_SEEPROM_SIZE_4KBITS (0x03) 840 #define MPI3_MAN11_SEEPROM_SIZE_8KBITS (0x04) 841 #define MPI3_MAN11_SEEPROM_SIZE_16KBITS (0x05) 842 #define MPI3_MAN11_SEEPROM_SIZE_32KBITS (0x06) 843 #define MPI3_MAN11_SEEPROM_SIZE_64KBITS (0x07) 844 #define MPI3_MAN11_SEEPROM_SIZE_128KBITS (0x08) 845 846 typedef struct _MPI3_MAN11_DDR_SPD_DEVICE_FORMAT 847 { 848 U8 Channel; /* 0x00 */ 849 U8 Reserved01[3]; /* 0x01 */ 850 U32 Reserved04; /* 0x04 */ 851 } MPI3_MAN11_DDR_SPD_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_DDR_SPD_DEVICE_FORMAT, 852 Mpi3Man11DdrSpdDeviceFormat_t, MPI3_POINTER pMpi3Man11DdrSpdDeviceFormat_t; 853 854 typedef struct _MPI3_MAN11_CABLE_MGMT_DEVICE_FORMAT 855 { 856 U8 Type; /* 0x00 */ 857 U8 ReceptacleID; /* 0x01 */ 858 U16 Reserved02; /* 0x02 */ 859 U32 Reserved04; /* 0x04 */ 860 } MPI3_MAN11_CABLE_MGMT_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_CABLE_MGMT_DEVICE_FORMAT, 861 Mpi3Man11CableMgmtDeviceFormat_t, MPI3_POINTER pMpi3Man11CableMgmtDeviceFormat_t; 862 863 /**** Defines for the Type field ****/ 864 #define MPI3_MAN11_CABLE_MGMT_TYPE_SFF_8636 (0x00) 865 866 typedef struct _MPI3_MAN11_BKPLANE_SPEC_UBM_FORMAT 867 { 868 U16 Flags; /* 0x00 */ 869 U16 Reserved02; /* 0x02 */ 870 } MPI3_MAN11_BKPLANE_SPEC_UBM_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_BKPLANE_SPEC_UBM_FORMAT, 871 Mpi3Man11BkplaneSpecUBMFormat_t, MPI3_POINTER pMpi3Man11BkplaneSpecUBMFormat_t; 872 873 /**** Defines for the Flags field ****/ 874 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0200) 875 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_FORCE_POLLING (0x0100) 876 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_MASK (0x00F0) 877 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_SHIFT (4) 878 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_MASK (0x000F) 879 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_SHIFT (0) 880 881 typedef struct _MPI3_MAN11_BKPLANE_SPEC_NON_UBM_FORMAT 882 { 883 U16 Flags; /* 0x00 */ 884 U8 Reserved02; /* 0x02 */ 885 U8 Type; /* 0x03 */ 886 } MPI3_MAN11_BKPLANE_SPEC_NON_UBM_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_BKPLANE_SPEC_NON_UBM_FORMAT, 887 Mpi3Man11BkplaneSpecNonUBMFormat_t, MPI3_POINTER pMpi3Man11BkplaneSpecNonUBMFormat_t; 888 889 /**** Defines for the Flags field ****/ 890 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_MASK (0xF000) 891 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_SHIFT (12) 892 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_MASK (0x0600) 893 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_SHIFT (9) 894 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_DEVICE_PRESENT (0x0000) 895 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0200) 896 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_SRIS (0x0400) 897 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_MASK (0x00C0) 898 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_SHIFT (6) 899 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_4 (0x0000) 900 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_2 (0x0040) 901 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_1 (0x0080) 902 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_MASK (0x0030) 903 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_SHIFT (4) 904 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_GPIO (0x0000) 905 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_REG (0x0010) 906 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_MASK (0x000F) 907 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_SHIFT (0) 908 909 /**** Defines for the Type field ****/ 910 #define MPI3_MAN11_BKPLANE_NON_UBM_TYPE_VPP (0x00) 911 912 typedef union _MPI3_MAN11_BKPLANE_SPEC_FORMAT 913 { 914 MPI3_MAN11_BKPLANE_SPEC_UBM_FORMAT Ubm; 915 MPI3_MAN11_BKPLANE_SPEC_NON_UBM_FORMAT NonUbm; 916 } MPI3_MAN11_BKPLANE_SPEC_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_BKPLANE_SPEC_FORMAT, 917 Mpi3Man11BkplaneSpecFormat_t, MPI3_POINTER pMpi3Man11BkplaneSpecFormat_t; 918 919 typedef struct _MPI3_MAN11_BKPLANE_MGMT_DEVICE_FORMAT 920 { 921 U8 Type; /* 0x00 */ 922 U8 ReceptacleID; /* 0x01 */ 923 U8 ResetInfo; /* 0x02 */ 924 U8 Reserved03; /* 0x03 */ 925 MPI3_MAN11_BKPLANE_SPEC_FORMAT BackplaneMgmtSpecific; /* 0x04 */ 926 } MPI3_MAN11_BKPLANE_MGMT_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_BKPLANE_MGMT_DEVICE_FORMAT, 927 Mpi3Man11BkplaneMgmtDeviceFormat_t, MPI3_POINTER pMpi3Man11BkplaneMgmtDeviceFormat_t; 928 929 /**** Defines for the Type field ****/ 930 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_UBM (0x00) 931 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_NON_UBM (0x01) 932 933 /**** Defines for the ResetInfo field ****/ 934 #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_MASK (0xF0) 935 #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_SHIFT (4) 936 #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_MASK (0x0F) 937 #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_SHIFT (0) 938 939 typedef struct _MPI3_MAN11_GAS_GAUGE_DEVICE_FORMAT 940 { 941 U8 Type; /* 0x00 */ 942 U8 Reserved01[3]; /* 0x01 */ 943 U32 Reserved04; /* 0x04 */ 944 } MPI3_MAN11_GAS_GAUGE_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_GAS_GAUGE_DEVICE_FORMAT, 945 Mpi3Man11GasGaugeDeviceFormat_t, MPI3_POINTER pMpi3Man11GasGaugeDeviceFormat_t; 946 947 /**** Defines for the Type field ****/ 948 #define MPI3_MAN11_GAS_GAUGE_TYPE_STANDARD (0x00) 949 950 typedef struct _MPI3_MAN11_MGMT_CTRLR_DEVICE_FORMAT 951 { 952 U32 Reserved00; /* 0x00 */ 953 U32 Reserved04; /* 0x04 */ 954 } MPI3_MAN11_MGMT_CTRLR_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_MGMT_CTRLR_DEVICE_FORMAT, 955 Mpi3Man11MgmtCtrlrDeviceFormat_t, MPI3_POINTER pMpi3Man11MgmtCtrlrDeviceFormat_t; 956 957 typedef struct _MPI3_MAN11_BOARD_FAN_DEVICE_FORMAT 958 { 959 U8 Flags; /* 0x00 */ 960 U8 Reserved01; /* 0x01 */ 961 U8 MinFanSpeed; /* 0x02 */ 962 U8 MaxFanSpeed; /* 0x03 */ 963 U32 Reserved04; /* 0x04 */ 964 } MPI3_MAN11_BOARD_FAN_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_BOARD_FAN_DEVICE_FORMAT, 965 Mpi3Man11BoardFanDeviceFormat_t, MPI3_POINTER pMpi3Man11BoardFanDeviceFormat_t; 966 967 /**** Defines for the Flags field ****/ 968 #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_MASK (0x07) 969 #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_AMC6821 (0x00) 970 971 typedef union _MPI3_MAN11_DEVICE_SPECIFIC_FORMAT 972 { 973 MPI3_MAN11_MUX_DEVICE_FORMAT Mux; 974 MPI3_MAN11_TEMP_SENSOR_DEVICE_FORMAT TempSensor; 975 MPI3_MAN11_SEEPROM_DEVICE_FORMAT Seeprom; 976 MPI3_MAN11_DDR_SPD_DEVICE_FORMAT DdrSpd; 977 MPI3_MAN11_CABLE_MGMT_DEVICE_FORMAT CableMgmt; 978 MPI3_MAN11_BKPLANE_MGMT_DEVICE_FORMAT BkplaneMgmt; 979 MPI3_MAN11_GAS_GAUGE_DEVICE_FORMAT GasGauge; 980 MPI3_MAN11_MGMT_CTRLR_DEVICE_FORMAT MgmtController; 981 MPI3_MAN11_BOARD_FAN_DEVICE_FORMAT BoardFan; 982 U32 Words[2]; 983 } MPI3_MAN11_DEVICE_SPECIFIC_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_DEVICE_SPECIFIC_FORMAT, 984 Mpi3Man11DeviceSpecificFormat_t, MPI3_POINTER pMpi3Man11DeviceSpecificFormat_t; 985 986 typedef struct _MPI3_MAN11_ISTWI_DEVICE_FORMAT 987 { 988 U8 DeviceType; /* 0x00 */ 989 U8 Controller; /* 0x01 */ 990 U8 Reserved02; /* 0x02 */ 991 U8 Flags; /* 0x03 */ 992 U16 DeviceAddress; /* 0x04 */ 993 U8 MuxChannel; /* 0x06 */ 994 U8 MuxIndex; /* 0x07 */ 995 MPI3_MAN11_DEVICE_SPECIFIC_FORMAT DeviceSpecific; /* 0x08 */ 996 } MPI3_MAN11_ISTWI_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_ISTWI_DEVICE_FORMAT, 997 Mpi3Man11IstwiDeviceFormat_t, MPI3_POINTER pMpi3Man11IstwiDeviceFormat_t; 998 999 /**** Defines for the DeviceType field ****/ 1000 #define MPI3_MAN11_ISTWI_DEVTYPE_MUX (0x00) 1001 #define MPI3_MAN11_ISTWI_DEVTYPE_TEMP_SENSOR (0x01) 1002 #define MPI3_MAN11_ISTWI_DEVTYPE_SEEPROM (0x02) 1003 #define MPI3_MAN11_ISTWI_DEVTYPE_DDR_SPD (0x03) 1004 #define MPI3_MAN11_ISTWI_DEVTYPE_CABLE_MGMT (0x04) 1005 #define MPI3_MAN11_ISTWI_DEVTYPE_BACKPLANE_MGMT (0x05) 1006 #define MPI3_MAN11_ISTWI_DEVTYPE_GAS_GAUGE (0x06) 1007 #define MPI3_MAN11_ISTWI_DEVTYPE_MGMT_CONTROLLER (0x07) 1008 #define MPI3_MAN11_ISTWI_DEVTYPE_BOARD_FAN (0x08) 1009 1010 /**** Defines for the Flags field ****/ 1011 #define MPI3_MAN11_ISTWI_FLAGS_MUX_PRESENT (0x01) 1012 1013 #ifndef MPI3_MAN11_ISTWI_DEVICE_MAX 1014 #define MPI3_MAN11_ISTWI_DEVICE_MAX (1) 1015 #endif /* MPI3_MAN11_ISTWI_DEVICE_MAX */ 1016 1017 typedef struct _MPI3_MAN_PAGE11 1018 { 1019 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1020 U32 Reserved08; /* 0x08 */ 1021 U8 NumISTWIDev; /* 0x0C */ 1022 U8 Reserved0D[3]; /* 0x0D */ 1023 MPI3_MAN11_ISTWI_DEVICE_FORMAT ISTWIDevice[MPI3_MAN11_ISTWI_DEVICE_MAX]; /* 0x10 */ 1024 } MPI3_MAN_PAGE11, MPI3_POINTER PTR_MPI3_MAN_PAGE11, 1025 Mpi3ManPage11_t, MPI3_POINTER pMpi3ManPage11_t; 1026 1027 /**** Defines for the PageVersion field ****/ 1028 #define MPI3_MAN11_PAGEVERSION (0x00) 1029 1030 1031 /***************************************************************************** 1032 * Manufacturing Page 12 * 1033 ****************************************************************************/ 1034 #ifndef MPI3_MAN12_NUM_SGPIO_MAX 1035 #define MPI3_MAN12_NUM_SGPIO_MAX (1) 1036 #endif /* MPI3_MAN12_NUM_SGPIO_MAX */ 1037 1038 typedef struct _MPI3_MAN12_SGPIO_INFO 1039 { 1040 U8 SlotCount; /* 0x00 */ 1041 U8 Reserved01[3]; /* 0x01 */ 1042 U32 Reserved04; /* 0x04 */ 1043 U8 PhyOrder[32]; /* 0x08 */ 1044 } MPI3_MAN12_SGPIO_INFO, MPI3_POINTER PTR_MPI3_MAN12_SGPIO_INFO, 1045 Mpi3Man12SGPIOInfo_t, MPI3_POINTER pMpi3Man12SGPIOInfo_t; 1046 1047 typedef struct _MPI3_MAN_PAGE12 1048 { 1049 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1050 U32 Flags; /* 0x08 */ 1051 U32 SClockFreq; /* 0x0C */ 1052 U32 ActivityModulation; /* 0x10 */ 1053 U8 NumSGPIO; /* 0x14 */ 1054 U8 Reserved15[3]; /* 0x15 */ 1055 U32 Reserved18; /* 0x18 */ 1056 U32 Reserved1C; /* 0x1C */ 1057 U32 Pattern[8]; /* 0x20 */ 1058 MPI3_MAN12_SGPIO_INFO SGPIOInfo[MPI3_MAN12_NUM_SGPIO_MAX]; /* 0x40 */ /* variable length */ 1059 } MPI3_MAN_PAGE12, MPI3_POINTER PTR_MPI3_MAN_PAGE12, 1060 Mpi3ManPage12_t, MPI3_POINTER pMpi3ManPage12_t; 1061 1062 /**** Defines for the PageVersion field ****/ 1063 #define MPI3_MAN12_PAGEVERSION (0x00) 1064 1065 /**** Defines for the Flags field ****/ 1066 #define MPI3_MAN12_FLAGS_ERROR_PRESENCE_ENABLED (0x0400) 1067 #define MPI3_MAN12_FLAGS_ACTIVITY_INVERT_ENABLED (0x0200) 1068 #define MPI3_MAN12_FLAGS_GROUP_ID_DISABLED (0x0100) 1069 #define MPI3_MAN12_FLAGS_SIO_CLK_FILTER_ENABLED (0x0004) 1070 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_MASK (0x0002) 1071 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_PUSH_PULL (0x0000) 1072 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_OPEN_DRAIN (0x0002) 1073 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_MASK (0x0001) 1074 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_PUSH_PULL (0x0000) 1075 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_OPEN_DRAIN (0x0001) 1076 1077 /**** Defines for the SClockFreq field ****/ 1078 #define MPI3_MAN12_SIO_CLK_FREQ_MIN (32) /* 32 Hz min SIO Clk Freq */ 1079 #define MPI3_MAN12_SIO_CLK_FREQ_MAX (100000) /* 100 KHz max SIO Clk Freq */ 1080 1081 /**** Defines for the ActivityModulation field ****/ 1082 #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_MASK (0x0000F000) 1083 #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_SHIFT (12) 1084 #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_MASK (0x00000F00) 1085 #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_SHIFT (8) 1086 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_MASK (0x000000F0) 1087 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_SHIFT (4) 1088 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_MASK (0x0000000F) 1089 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_SHIFT (0) 1090 1091 /*** Defines for the Pattern field ****/ 1092 #define MPI3_MAN12_PATTERN_RATE_MASK (0xE0000000) 1093 #define MPI3_MAN12_PATTERN_RATE_2_HZ (0x00000000) 1094 #define MPI3_MAN12_PATTERN_RATE_4_HZ (0x20000000) 1095 #define MPI3_MAN12_PATTERN_RATE_8_HZ (0x40000000) 1096 #define MPI3_MAN12_PATTERN_RATE_16_HZ (0x60000000) 1097 #define MPI3_MAN12_PATTERN_RATE_10_HZ (0x80000000) 1098 #define MPI3_MAN12_PATTERN_RATE_20_HZ (0xA0000000) 1099 #define MPI3_MAN12_PATTERN_RATE_40_HZ (0xC0000000) 1100 #define MPI3_MAN12_PATTERN_LENGTH_MASK (0x1F000000) 1101 #define MPI3_MAN12_PATTERN_LENGTH_SHIFT (24) 1102 #define MPI3_MAN12_PATTERN_BIT_PATTERN_MASK (0x00FFFFFF) 1103 #define MPI3_MAN12_PATTERN_BIT_PATTERN_SHIFT (0) 1104 1105 1106 /***************************************************************************** 1107 * Manufacturing Page 13 * 1108 ****************************************************************************/ 1109 1110 #ifndef MPI3_MAN13_NUM_TRANSLATION_MAX 1111 #define MPI3_MAN13_NUM_TRANSLATION_MAX (1) 1112 #endif /* MPI3_MAN13_NUM_TRANSLATION_MAX */ 1113 1114 typedef struct _MPI3_MAN13_TRANSLATION_INFO 1115 { 1116 U32 SlotStatus; /* 0x00 */ 1117 U32 Mask; /* 0x04 */ 1118 U8 Activity; /* 0x08 */ 1119 U8 Locate; /* 0x09 */ 1120 U8 Error; /* 0x0A */ 1121 U8 Reserved0B; /* 0x0B */ 1122 } MPI3_MAN13_TRANSLATION_INFO, MPI3_POINTER PTR_MPI3_MAN13_TRANSLATION_INFO, 1123 Mpi3Man13TranslationInfo_t, MPI3_POINTER pMpi3Man13TranslationInfo_t; 1124 1125 /**** Defines for the SlotStatus field ****/ 1126 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_FAULT (0x20000000) 1127 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_OFF (0x10000000) 1128 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_ACTIVITY (0x00800000) 1129 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DO_NOT_REMOVE (0x00400000) 1130 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_MISSING (0x00100000) 1131 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_INSERT (0x00080000) 1132 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REMOVAL (0x00040000) 1133 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IDENTIFY (0x00020000) 1134 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_OK (0x00008000) 1135 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_RESERVED_DEVICE (0x00004000) 1136 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_HOT_SPARE (0x00002000) 1137 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_CONSISTENCY_CHECK (0x00001000) 1138 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000800) 1139 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_FAILED_ARRAY (0x00000400) 1140 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP (0x00000200) 1141 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP_ABORT (0x00000100) 1142 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_PREDICTED_FAILURE (0x00000040) 1143 1144 /**** Defines for the Mask field - use MPI3_MAN13_TRANSLATION_SLOTSTATUS_ defines ****/ 1145 1146 /**** Defines for the Activity, Locate, and Error fields ****/ 1147 #define MPI3_MAN13_BLINK_PATTERN_FORCE_OFF (0x00) 1148 #define MPI3_MAN13_BLINK_PATTERN_FORCE_ON (0x01) 1149 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_0 (0x02) 1150 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_1 (0x03) 1151 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_2 (0x04) 1152 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_3 (0x05) 1153 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_4 (0x06) 1154 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_5 (0x07) 1155 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_6 (0x08) 1156 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_7 (0x09) 1157 #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY (0x0A) 1158 #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY_TRAIL (0x0B) 1159 1160 typedef struct _MPI3_MAN_PAGE13 1161 { 1162 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1163 U8 NumTrans; /* 0x08 */ 1164 U8 Reserved09[3]; /* 0x09 */ 1165 U32 Reserved0C; /* 0x0C */ 1166 MPI3_MAN13_TRANSLATION_INFO Translation[MPI3_MAN13_NUM_TRANSLATION_MAX]; /* 0x10 */ /* variable length */ 1167 } MPI3_MAN_PAGE13, MPI3_POINTER PTR_MPI3_MAN_PAGE13, 1168 Mpi3ManPage13_t, MPI3_POINTER pMpi3ManPage13_t; 1169 1170 /**** Defines for the PageVersion field ****/ 1171 #define MPI3_MAN13_PAGEVERSION (0x00) 1172 1173 /***************************************************************************** 1174 * Manufacturing Page 14 * 1175 ****************************************************************************/ 1176 1177 typedef struct _MPI3_MAN_PAGE14 1178 { 1179 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1180 U32 Reserved08; /* 0x08 */ 1181 U8 NumSlotGroups; /* 0x0C */ 1182 U8 NumSlots; /* 0x0D */ 1183 U16 MaxCertChainLength; /* 0x0E */ 1184 U32 SealedSlots; /* 0x10 */ 1185 U32 PopulatedSlots; /* 0x14 */ 1186 U32 MgmtPTUpdatableSlots; /* 0x18 */ 1187 } MPI3_MAN_PAGE14, MPI3_POINTER PTR_MPI3_MAN_PAGE14, 1188 Mpi3ManPage14_t, MPI3_POINTER pMpi3ManPage14_t; 1189 1190 /**** Defines for the PageVersion field ****/ 1191 #define MPI3_MAN14_PAGEVERSION (0x00) 1192 1193 /**** Defines for the NumSlots field ****/ 1194 #define MPI3_MAN14_NUMSLOTS_MAX (32) 1195 1196 /***************************************************************************** 1197 * Manufacturing Page 15 * 1198 ****************************************************************************/ 1199 1200 #ifndef MPI3_MAN15_VERSION_RECORD_MAX 1201 #define MPI3_MAN15_VERSION_RECORD_MAX 1 1202 #endif /* MPI3_MAN15_VERSION_RECORD_MAX */ 1203 1204 typedef struct _MPI3_MAN15_VERSION_RECORD 1205 { 1206 U16 SPDMVersion; /* 0x00 */ 1207 U16 Reserved02; /* 0x02 */ 1208 } MPI3_MAN15_VERSION_RECORD, MPI3_POINTER PTR_MPI3_MAN15_VERSION_RECORD, 1209 Mpi3Man15VersionRecord_t, MPI3_POINTER pMpi3Man15VersionRecord_t; 1210 1211 typedef struct _MPI3_MAN_PAGE15 1212 { 1213 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1214 U8 NumVersionRecords; /* 0x08 */ 1215 U8 Reserved09[3]; /* 0x09 */ 1216 U32 Reserved0C; /* 0x0C */ 1217 MPI3_MAN15_VERSION_RECORD VersionRecord[MPI3_MAN15_VERSION_RECORD_MAX]; /* 0x10 */ 1218 } MPI3_MAN_PAGE15, MPI3_POINTER PTR_MPI3_MAN_PAGE15, 1219 Mpi3ManPage15_t, MPI3_POINTER pMpi3ManPage15_t; 1220 1221 /**** Defines for the PageVersion field ****/ 1222 #define MPI3_MAN15_PAGEVERSION (0x00) 1223 1224 /***************************************************************************** 1225 * Manufacturing Page 16 * 1226 ****************************************************************************/ 1227 1228 #ifndef MPI3_MAN16_CERT_ALGO_MAX 1229 #define MPI3_MAN16_CERT_ALGO_MAX 1 1230 #endif /* MPI3_MAN16_CERT_ALGO_MAX */ 1231 1232 typedef struct _MPI3_MAN16_CERTIFICATE_ALGORITHM 1233 { 1234 U8 SlotGroup; /* 0x00 */ 1235 U8 Reserved01[3]; /* 0x01 */ 1236 U32 BaseAsymAlgo; /* 0x04 */ 1237 U32 BaseHashAlgo; /* 0x08 */ 1238 U32 Reserved0C[3]; /* 0x0C */ 1239 } MPI3_MAN16_CERTIFICATE_ALGORITHM, MPI3_POINTER PTR_MPI3_MAN16_CERTIFICATE_ALGORITHM, 1240 Mpi3Man16CertificateAlgorithm_t, MPI3_POINTER pMpi3Man16CertificateAlgorithm_t; 1241 1242 typedef struct _MPI3_MAN_PAGE16 1243 { 1244 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1245 U32 Reserved08; /* 0x08 */ 1246 U8 NumCertAlgos; /* 0x0C */ 1247 U8 Reserved0D[3]; /* 0x0D */ 1248 MPI3_MAN16_CERTIFICATE_ALGORITHM CertificateAlgorithm[MPI3_MAN16_CERT_ALGO_MAX]; /* 0x10 */ 1249 } MPI3_MAN_PAGE16, MPI3_POINTER PTR_MPI3_MAN_PAGE16, 1250 Mpi3ManPage16_t, MPI3_POINTER pMpi3ManPage16_t; 1251 1252 /**** Defines for the PageVersion field ****/ 1253 #define MPI3_MAN16_PAGEVERSION (0x00) 1254 1255 /***************************************************************************** 1256 * Manufacturing Page 17 * 1257 ****************************************************************************/ 1258 1259 #ifndef MPI3_MAN17_HASH_ALGORITHM_MAX 1260 #define MPI3_MAN17_HASH_ALGORITHM_MAX 1 1261 #endif /* MPI3_MAN17_HASH_ALGORITHM_MAX */ 1262 1263 typedef struct _MPI3_MAN17_HASH_ALGORITHM 1264 { 1265 U8 MeasSpecification; /* 0x00 */ 1266 U8 Reserved01[3]; /* 0x01 */ 1267 U32 MeasurementHashAlgo; /* 0x04 */ 1268 U32 Reserved08[2]; /* 0x08 */ 1269 } MPI3_MAN17_HASH_ALGORITHM, MPI3_POINTER PTR_MPI3_MAN17_HASH_ALGORITHM, 1270 Mpi3Man17HashAlgorithm_t, MPI3_POINTER pMpi3Man17HashAlgorithm_t; 1271 1272 typedef struct _MPI3_MAN_PAGE17 1273 { 1274 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1275 U32 Reserved08; /* 0x08 */ 1276 U8 NumHashAlgos; /* 0x0C */ 1277 U8 Reserved0D[3]; /* 0x0D */ 1278 MPI3_MAN17_HASH_ALGORITHM HashAlgorithm[MPI3_MAN17_HASH_ALGORITHM_MAX]; /* 0x10 */ 1279 } MPI3_MAN_PAGE17, MPI3_POINTER PTR_MPI3_MAN_PAGE17, 1280 Mpi3ManPage17_t, MPI3_POINTER pMpi3ManPage17_t; 1281 1282 /**** Defines for the PageVersion field ****/ 1283 #define MPI3_MAN17_PAGEVERSION (0x00) 1284 1285 /***************************************************************************** 1286 * Manufacturing Page 20 * 1287 ****************************************************************************/ 1288 1289 typedef struct _MPI3_MAN_PAGE20 1290 { 1291 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1292 U32 Reserved08; /* 0x08 */ 1293 U32 NonpremiumFeatures; /* 0x0C */ 1294 U8 AllowedPersonalities; /* 0x10 */ 1295 U8 Reserved11[3]; /* 0x11 */ 1296 } MPI3_MAN_PAGE20, MPI3_POINTER PTR_MPI3_MAN_PAGE20, 1297 Mpi3ManPage20_t, MPI3_POINTER pMpi3ManPage20_t; 1298 1299 /**** Defines for the PageVersion field ****/ 1300 #define MPI3_MAN20_PAGEVERSION (0x00) 1301 1302 /**** Defines for the AllowedPersonalities field ****/ 1303 #define MPI3_MAN20_ALLOWEDPERSON_RAID_MASK (0x02) 1304 #define MPI3_MAN20_ALLOWEDPERSON_RAID_ALLOWED (0x02) 1305 #define MPI3_MAN20_ALLOWEDPERSON_RAID_NOT_ALLOWED (0x00) 1306 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_MASK (0x01) 1307 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_ALLOWED (0x01) 1308 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_NOT_ALLOWED (0x00) 1309 1310 /**** Defines for the NonpremiumFeatures field ****/ 1311 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_MASK (0x01) 1312 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_ENABLED (0x00) 1313 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_DISABLED (0x01) 1314 1315 /***************************************************************************** 1316 * Manufacturing Page 21 * 1317 ****************************************************************************/ 1318 1319 typedef struct _MPI3_MAN_PAGE21 1320 { 1321 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1322 U32 Reserved08; /* 0x08 */ 1323 U32 Flags; /* 0x0C */ 1324 } MPI3_MAN_PAGE21, MPI3_POINTER PTR_MPI3_MAN_PAGE21, 1325 Mpi3ManPage21_t, MPI3_POINTER pMpi3ManPage21_t; 1326 1327 /**** Defines for the PageVersion field ****/ 1328 #define MPI3_MAN21_PAGEVERSION (0x00) 1329 1330 /**** Defines for the Flags field ****/ 1331 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_MASK (0x00000060) 1332 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_BLOCK (0x00000000) 1333 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_ALLOW (0x00000020) 1334 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_WARN (0x00000040) 1335 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_MASK (0x00000008) 1336 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_ALLOW (0x00000000) 1337 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_PREVENT (0x00000008) 1338 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_MASK (0x00000001) 1339 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_DEFAULT (0x00000000) 1340 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_OEM_SPECIFIC (0x00000001) 1341 1342 /***************************************************************************** 1343 * Manufacturing Page 22 * 1344 ****************************************************************************/ 1345 1346 typedef struct _MPI3_MAN_PAGE22 1347 { 1348 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1349 U32 Reserved08; /* 0x08 */ 1350 U16 NumEUI64; /* 0x0C */ 1351 U16 Reserved0E; /* 0x0E */ 1352 U64 BaseEUI64; /* 0x10 */ 1353 } MPI3_MAN_PAGE22, MPI3_POINTER PTR_MPI3_MAN_PAGE22, 1354 Mpi3ManPage22_t, MPI3_POINTER pMpi3ManPage22_t; 1355 1356 /**** Defines for the PageVersion field ****/ 1357 #define MPI3_MAN22_PAGEVERSION (0x00) 1358 1359 /***************************************************************************** 1360 * Manufacturing Pages 32-63 (ProductSpecific) * 1361 ****************************************************************************/ 1362 #ifndef MPI3_MAN_PROD_SPECIFIC_MAX 1363 #define MPI3_MAN_PROD_SPECIFIC_MAX (1) 1364 #endif /* MPI3_MAN_PROD_SPECIFIC_MAX */ 1365 1366 typedef struct _MPI3_MAN_PAGE_PRODUCT_SPECIFIC 1367 { 1368 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1369 U32 ProductSpecificInfo[MPI3_MAN_PROD_SPECIFIC_MAX]; /* 0x08 */ /* variable length array */ 1370 } MPI3_MAN_PAGE_PRODUCT_SPECIFIC, MPI3_POINTER PTR_MPI3_MAN_PAGE_PRODUCT_SPECIFIC, 1371 Mpi3ManPageProductSpecific_t, MPI3_POINTER pMpi3ManPageProductSpecific_t; 1372 1373 /***************************************************************************** 1374 * IO Unit Configuration Pages * 1375 ****************************************************************************/ 1376 1377 /***************************************************************************** 1378 * IO Unit Page 0 * 1379 ****************************************************************************/ 1380 typedef struct _MPI3_IO_UNIT_PAGE0 1381 { 1382 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1383 U64 UniqueValue; /* 0x08 */ 1384 U32 NvdataVersionDefault; /* 0x10 */ 1385 U32 NvdataVersionPersistent; /* 0x14 */ 1386 } MPI3_IO_UNIT_PAGE0, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE0, 1387 Mpi3IOUnitPage0_t, MPI3_POINTER pMpi3IOUnitPage0_t; 1388 1389 /**** Defines for the PageVersion field ****/ 1390 #define MPI3_IOUNIT0_PAGEVERSION (0x00) 1391 1392 /***************************************************************************** 1393 * IO Unit Page 1 * 1394 ****************************************************************************/ 1395 typedef struct _MPI3_IO_UNIT_PAGE1 1396 { 1397 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1398 U32 Flags; /* 0x08 */ 1399 U8 DMDIoDelay; /* 0x0C */ 1400 U8 DMDReportPCIe; /* 0x0D */ 1401 U8 DMDReportSATA; /* 0x0E */ 1402 U8 DMDReportSAS; /* 0x0F */ 1403 } MPI3_IO_UNIT_PAGE1, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE1, 1404 Mpi3IOUnitPage1_t, MPI3_POINTER pMpi3IOUnitPage1_t; 1405 1406 /**** Defines for the PageVersion field ****/ 1407 #define MPI3_IOUNIT1_PAGEVERSION (0x00) 1408 1409 /**** Defines for the Flags field ****/ 1410 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_MASK (0x00000030) 1411 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_ENABLE (0x00000000) 1412 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_DISABLE (0x00000010) 1413 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_NO_MODIFY (0x00000020) 1414 #define MPI3_IOUNIT1_FLAGS_ATA_SECURITY_FREEZE_LOCK (0x00000008) 1415 #define MPI3_IOUNIT1_FLAGS_WRITE_SAME_BUFFER (0x00000004) 1416 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_MASK (0x00000003) 1417 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_ENABLE (0x00000000) 1418 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_DISABLE (0x00000001) 1419 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_UNCHANGED (0x00000002) 1420 1421 /**** Defines for the DMDReport PCIe/SATA/SAS fields ****/ 1422 #define MPI3_IOUNIT1_DMD_REPORT_DELAY_TIME_MASK (0x7F) 1423 #define MPI3_IOUNIT1_DMD_REPORT_UNIT_16_SEC (0x80) 1424 1425 /***************************************************************************** 1426 * IO Unit Page 2 * 1427 ****************************************************************************/ 1428 #ifndef MPI3_IO_UNIT2_GPIO_VAL_MAX 1429 #define MPI3_IO_UNIT2_GPIO_VAL_MAX (1) 1430 #endif /* MPI3_IO_UNIT2_GPIO_VAL_MAX */ 1431 1432 typedef struct _MPI3_IO_UNIT_PAGE2 1433 { 1434 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1435 U8 GPIOCount; /* 0x08 */ 1436 U8 Reserved09[3]; /* 0x09 */ 1437 U16 GPIOVal[MPI3_IO_UNIT2_GPIO_VAL_MAX]; /* 0x0C */ 1438 } MPI3_IO_UNIT_PAGE2, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE2, 1439 Mpi3IOUnitPage2_t, MPI3_POINTER pMpi3IOUnitPage2_t; 1440 1441 /**** Defines for the PageVersion field ****/ 1442 #define MPI3_IOUNIT2_PAGEVERSION (0x00) 1443 1444 /**** Define for the GPIOVal field ****/ 1445 #define MPI3_IOUNIT2_GPIO_FUNCTION_MASK (0xFFFC) 1446 #define MPI3_IOUNIT2_GPIO_FUNCTION_SHIFT (2) 1447 #define MPI3_IOUNIT2_GPIO_SETTING_MASK (0x0001) 1448 #define MPI3_IOUNIT2_GPIO_SETTING_OFF (0x0000) 1449 #define MPI3_IOUNIT2_GPIO_SETTING_ON (0x0001) 1450 1451 /***************************************************************************** 1452 * IO Unit Page 3 * 1453 ****************************************************************************/ 1454 1455 typedef enum _MPI3_IOUNIT3_THRESHOLD 1456 { 1457 MPI3_IOUNIT3_THRESHOLD_WARNING = 0, 1458 MPI3_IOUNIT3_THRESHOLD_CRITICAL = 1, 1459 MPI3_IOUNIT3_THRESHOLD_FATAL = 2, 1460 MPI3_IOUNIT3_THRESHOLD_LOW = 3, 1461 MPI3_IOUNIT3_NUM_THRESHOLDS 1462 } MPI3_IOUNIT3_THRESHOLD; 1463 1464 typedef struct _MPI3_IO_UNIT3_SENSOR 1465 { 1466 U16 Flags; /* 0x00 */ 1467 U8 ThresholdMargin; /* 0x02 */ 1468 U8 Reserved03; /* 0x03 */ 1469 U16 Threshold[MPI3_IOUNIT3_NUM_THRESHOLDS]; /* 0x04 */ 1470 U32 Reserved0C; /* 0x0C */ 1471 U32 Reserved10; /* 0x10 */ 1472 U32 Reserved14; /* 0x14 */ 1473 } MPI3_IO_UNIT3_SENSOR, MPI3_POINTER PTR_MPI3_IO_UNIT3_SENSOR, 1474 Mpi3IOUnit3Sensor_t, MPI3_POINTER pMpi3IOUnit3Sensor_t; 1475 1476 /**** Defines for the Flags field ****/ 1477 #define MPI3_IOUNIT3_SENSOR_FLAGS_LOW_THRESHOLD_VALID (0x0020) 1478 #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_EVENT_ENABLED (0x0010) 1479 #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_ACTION_ENABLED (0x0008) 1480 #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_EVENT_ENABLED (0x0004) 1481 #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_ACTION_ENABLED (0x0002) 1482 #define MPI3_IOUNIT3_SENSOR_FLAGS_WARNING_EVENT_ENABLED (0x0001) 1483 1484 #ifndef MPI3_IO_UNIT3_SENSOR_MAX 1485 #define MPI3_IO_UNIT3_SENSOR_MAX (1) 1486 #endif /* MPI3_IO_UNIT3_SENSOR_MAX */ 1487 1488 typedef struct _MPI3_IO_UNIT_PAGE3 1489 { 1490 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1491 U32 Reserved08; /* 0x08 */ 1492 U8 NumSensors; /* 0x0C */ 1493 U8 NominalPollInterval; /* 0x0D */ 1494 U8 WarningPollInterval; /* 0x0E */ 1495 U8 Reserved0F; /* 0x0F */ 1496 MPI3_IO_UNIT3_SENSOR Sensor[MPI3_IO_UNIT3_SENSOR_MAX]; /* 0x10 */ 1497 } MPI3_IO_UNIT_PAGE3, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE3, 1498 Mpi3IOUnitPage3_t, MPI3_POINTER pMpi3IOUnitPage3_t; 1499 1500 /**** Defines for the PageVersion field ****/ 1501 #define MPI3_IOUNIT3_PAGEVERSION (0x00) 1502 1503 1504 /***************************************************************************** 1505 * IO Unit Page 4 * 1506 ****************************************************************************/ 1507 typedef struct _MPI3_IO_UNIT4_SENSOR 1508 { 1509 U16 CurrentTemperature; /* 0x00 */ 1510 U16 Reserved02; /* 0x02 */ 1511 U8 Flags; /* 0x04 */ 1512 U8 Reserved05[3]; /* 0x05 */ 1513 U16 ISTWIIndex; /* 0x08 */ 1514 U8 Channel; /* 0x0A */ 1515 U8 Reserved0B; /* 0x0B */ 1516 U32 Reserved0C; /* 0x0C */ 1517 } MPI3_IO_UNIT4_SENSOR, MPI3_POINTER PTR_MPI3_IO_UNIT4_SENSOR, 1518 Mpi3IOUnit4Sensor_t, MPI3_POINTER pMpi3IOUnit4Sensor_t; 1519 1520 /**** Defines for the Flags field ****/ 1521 #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_MASK (0xE0) 1522 #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_SHIFT (5) 1523 /**** for the Location field values - use MPI3_TEMP_SENSOR_LOCATION_ defines ****/ 1524 #define MPI3_IOUNIT4_SENSOR_FLAGS_TEMP_VALID (0x01) 1525 1526 1527 /**** Defines for the ISTWIIndex field ****/ 1528 #define MPI3_IOUNIT4_SENSOR_ISTWI_INDEX_INTERNAL (0xFFFF) 1529 1530 /**** Defines for the Channel field ****/ 1531 #define MPI3_IOUNIT4_SENSOR_CHANNEL_RESERVED (0xFF) 1532 1533 #ifndef MPI3_IO_UNIT4_SENSOR_MAX 1534 #define MPI3_IO_UNIT4_SENSOR_MAX (1) 1535 #endif /* MPI3_IO_UNIT4_SENSOR_MAX */ 1536 1537 typedef struct _MPI3_IO_UNIT_PAGE4 1538 { 1539 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1540 U32 Reserved08; /* 0x08 */ 1541 U8 NumSensors; /* 0x0C */ 1542 U8 Reserved0D[3]; /* 0x0D */ 1543 MPI3_IO_UNIT4_SENSOR Sensor[MPI3_IO_UNIT4_SENSOR_MAX]; /* 0x10 */ 1544 } MPI3_IO_UNIT_PAGE4, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE4, 1545 Mpi3IOUnitPage4_t, MPI3_POINTER pMpi3IOUnitPage4_t; 1546 1547 /**** Defines for the PageVersion field ****/ 1548 #define MPI3_IOUNIT4_PAGEVERSION (0x00) 1549 1550 /***************************************************************************** 1551 * IO Unit Page 5 * 1552 ****************************************************************************/ 1553 typedef struct _MPI3_IO_UNIT5_SPINUP_GROUP 1554 { 1555 U8 MaxTargetSpinup; /* 0x00 */ 1556 U8 SpinupDelay; /* 0x01 */ 1557 U8 SpinupFlags; /* 0x02 */ 1558 U8 Reserved03; /* 0x03 */ 1559 } MPI3_IO_UNIT5_SPINUP_GROUP, MPI3_POINTER PTR_MPI3_IO_UNIT5_SPINUP_GROUP, 1560 Mpi3IOUnit5SpinupGroup_t, MPI3_POINTER pMpi3IOUnit5SpinupGroup_t; 1561 1562 /**** Defines for the SpinupFlags field ****/ 1563 #define MPI3_IOUNIT5_SPINUP_FLAGS_DISABLE (0x01) 1564 1565 #ifndef MPI3_IO_UNIT5_PHY_MAX 1566 #define MPI3_IO_UNIT5_PHY_MAX (4) 1567 #endif /* MPI3_IO_UNIT5_PHY_MAX */ 1568 1569 typedef struct _MPI3_IO_UNIT_PAGE5 1570 { 1571 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1572 MPI3_IO_UNIT5_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 1573 U32 Reserved18; /* 0x18 */ 1574 U32 Reserved1C; /* 0x1C */ 1575 U16 DeviceShutdown; /* 0x20 */ 1576 U16 Reserved22; /* 0x22 */ 1577 U8 PCIeDeviceWaitTime; /* 0x24 */ 1578 U8 SATADeviceWaitTime; /* 0x25 */ 1579 U8 SpinupEnclDriveCount; /* 0x26 */ 1580 U8 SpinupEnclDelay; /* 0x27 */ 1581 U8 NumPhys; /* 0x28 */ 1582 U8 PEInitialSpinupDelay; /* 0x29 */ 1583 U8 TopologyStableTime; /* 0x2A */ 1584 U8 Flags; /* 0x2B */ 1585 U8 Phy[MPI3_IO_UNIT5_PHY_MAX]; /* 0x2C */ 1586 } MPI3_IO_UNIT_PAGE5, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE5, 1587 Mpi3IOUnitPage5_t, MPI3_POINTER pMpi3IOUnitPage5_t; 1588 1589 /**** Defines for the PageVersion field ****/ 1590 #define MPI3_IOUNIT5_PAGEVERSION (0x00) 1591 1592 /**** Defines for the DeviceShutdown field ****/ 1593 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NO_ACTION (0x00) 1594 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_ATTACHED (0x01) 1595 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_EXPANDER_ATTACHED (0x02) 1596 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SWITCH_ATTACHED (0x02) 1597 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_EXPANDER (0x03) 1598 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_SWITCH (0x03) 1599 1600 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_MASK (0x0300) 1601 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_SHIFT (8) 1602 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_MASK (0x00C0) 1603 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_SHIFT (6) 1604 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_MASK (0x0030) 1605 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_SHIFT (4) 1606 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_MASK (0x000C) 1607 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_SHIFT (2) 1608 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_MASK (0x0003) 1609 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_SHIFT (0) 1610 1611 /**** Defines for the Flags field ****/ 1612 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_MASK (0x0C) 1613 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_SHIFT (2) 1614 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_NOT_SUPPORTED (0x00) 1615 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_OS_CONTROLLED (0x04) 1616 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_APP_CONTROLLED (0x08) 1617 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_BLOCKED (0x0C) 1618 #define MPI3_IOUNIT5_FLAGS_POWER_CAPABLE_SPINUP (0x02) 1619 #define MPI3_IOUNIT5_FLAGS_AUTO_PORT_ENABLE (0x01) 1620 1621 /**** Defines for the Phy field ****/ 1622 #define MPI3_IOUNIT5_PHY_SPINUP_GROUP_MASK (0x03) 1623 1624 /***************************************************************************** 1625 * IO Unit Page 6 * 1626 ****************************************************************************/ 1627 typedef struct _MPI3_IO_UNIT_PAGE6 1628 { 1629 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1630 U32 BoardPowerRequirement; /* 0x08 */ 1631 U32 PCISlotPowerAllocation; /* 0x0C */ 1632 U8 Flags; /* 0x10 */ 1633 U8 Reserved11[3]; /* 0x11 */ 1634 } MPI3_IO_UNIT_PAGE6, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE6, 1635 Mpi3IOUnitPage6_t, MPI3_POINTER pMpi3IOUnitPage6_t; 1636 1637 /**** Defines for the PageVersion field ****/ 1638 #define MPI3_IOUNIT6_PAGEVERSION (0x00) 1639 1640 /**** Defines for the Flags field ****/ 1641 #define MPI3_IOUNIT6_FLAGS_ACT_CABLE_PWR_EXC (0x01) 1642 1643 /***************************************************************************** 1644 * IO Unit Page 8 * 1645 ****************************************************************************/ 1646 1647 #ifndef MPI3_IOUNIT8_DIGEST_MAX 1648 #define MPI3_IOUNIT8_DIGEST_MAX (1) 1649 #endif /* MPI3_IOUNIT8_DIGEST_MAX */ 1650 1651 typedef union _MPI3_IOUNIT8_RAW_DIGEST 1652 { 1653 U32 Dword[16]; 1654 U16 Word[32]; 1655 U8 Byte[64]; 1656 } MPI3_IOUNIT8_RAW_DIGEST, MPI3_POINTER PTR_MPI3_IOUNIT8_RAW_DIGEST, 1657 Mpi3IOUnit8RawDigest_t, MPI3_POINTER pMpi3IOUnit8RawDigest_t; 1658 1659 typedef struct _MPI3_IOUNIT8_METADATA_DIGEST 1660 { 1661 U8 SlotStatus; /* 0x00 */ 1662 U8 Reserved01[3]; /* 0x01 */ 1663 U32 Reserved04[3]; /* 0x04 */ 1664 MPI3_IOUNIT8_RAW_DIGEST DigestData; /* 0x10 */ 1665 } MPI3_IOUNIT8_METADATA_DIGEST, MPI3_POINTER PTR_MPI3_IOUNIT8_METADATA_DIGEST, 1666 Mpi3IOUnit8MetadataDigest_t, MPI3_POINTER pMpi3IOUnit8MetadataDigest_t; 1667 1668 /**** Defines for the SlotStatus field ****/ 1669 #define MPI3_IOUNIT8_METADATA_DIGEST_SLOTSTATUS_UNUSED (0x00) 1670 #define MPI3_IOUNIT8_METADATA_DIGEST_SLOTSTATUS_UPDATE_PENDING (0x01) 1671 #define MPI3_IOUNIT8_METADATA_DIGEST_SLOTSTATUS_VALID (0x03) 1672 #define MPI3_IOUNIT8_METADATA_DIGEST_SLOTSTATUS_INVALID (0x07) 1673 1674 typedef union _MPI3_IOUNIT8_DIGEST 1675 { 1676 MPI3_IOUNIT8_RAW_DIGEST RawDigest[MPI3_IOUNIT8_DIGEST_MAX]; 1677 MPI3_IOUNIT8_METADATA_DIGEST MetadataDigest[MPI3_IOUNIT8_DIGEST_MAX]; 1678 } MPI3_IOUNIT8_DIGEST, MPI3_POINTER PTR_MPI3_IOUNIT8_DIGEST, 1679 Mpi3IOUnit8Digest_t, MPI3_POINTER pMpi3IOUnit8Digest_t; 1680 1681 typedef struct _MPI3_IO_UNIT_PAGE8 1682 { 1683 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1684 U8 SBMode; /* 0x08 */ 1685 U8 SBState; /* 0x09 */ 1686 U8 Flags; /* 0x0A */ 1687 U8 Reserved0A; /* 0x0B */ 1688 U8 NumSlots; /* 0x0C */ 1689 U8 SlotsAvailable; /* 0x0D */ 1690 U8 CurrentKeyEncryptionAlgo; /* 0x0E */ 1691 U8 KeyDigestHashAlgo; /* 0x0F */ 1692 MPI3_VERSION_UNION CurrentSvn; /* 0x10 */ 1693 U32 Reserved14; /* 0x14 */ 1694 U32 CurrentKey[128]; /* 0x18 */ 1695 MPI3_IOUNIT8_DIGEST Digest; /* 0x218 */ /* variable length */ 1696 } MPI3_IO_UNIT_PAGE8, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE8, 1697 Mpi3IOUnitPage8_t, MPI3_POINTER pMpi3IOUnitPage8_t; 1698 1699 /**** Defines for the PageVersion field ****/ 1700 #define MPI3_IOUNIT8_PAGEVERSION (0x00) 1701 1702 /**** Defines for the SBMode field ****/ 1703 #define MPI3_IOUNIT8_SBMODE_SECURE_DEBUG (0x04) 1704 #define MPI3_IOUNIT8_SBMODE_HARD_SECURE (0x02) 1705 #define MPI3_IOUNIT8_SBMODE_CONFIG_SECURE (0x01) 1706 1707 /**** Defines for the SBState field ****/ 1708 #define MPI3_IOUNIT8_SBSTATE_SVN_UPDATE_PENDING (0x04) 1709 #define MPI3_IOUNIT8_SBSTATE_KEY_UPDATE_PENDING (0x02) 1710 #define MPI3_IOUNIT8_SBSTATE_SECURE_BOOT_ENABLED (0x01) 1711 1712 /**** Defines for the Flags field ****/ 1713 #define MPI3_IOUNIT8_FLAGS_DIGESTFORM_MASK (0x07) 1714 #define MPI3_IOUNIT8_FLAGS_DIGESTFORM_RAW (0x00) 1715 #define MPI3_IOUNIT8_FLAGS_DIGESTFORM_DIGEST_WITH_METADATA (0x01) 1716 1717 /***************************************************************************** 1718 * IO Unit Page 9 * 1719 ****************************************************************************/ 1720 1721 typedef struct _MPI3_IO_UNIT_PAGE9 1722 { 1723 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1724 U32 Flags; /* 0x08 */ 1725 U16 FirstDevice; /* 0x0C */ 1726 U16 Reserved0E; /* 0x0E */ 1727 } MPI3_IO_UNIT_PAGE9, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE9, 1728 Mpi3IOUnitPage9_t, MPI3_POINTER pMpi3IOUnitPage9_t; 1729 1730 /**** Defines for the PageVersion field ****/ 1731 #define MPI3_IOUNIT9_PAGEVERSION (0x00) 1732 1733 /**** Defines for the Flags field ****/ 1734 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_MASK (0x00000006) 1735 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_SHIFT (1) 1736 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_NONE (0x00000000) 1737 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_RECEPTACLE (0x00000002) 1738 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_BACKPLANE_TYPE (0x00000004) 1739 #define MPI3_IOUNIT9_FLAGS_VDFIRST_ENABLED (0x00000001) 1740 1741 /**** Defines for the FirstDevice field ****/ 1742 #define MPI3_IOUNIT9_FIRSTDEVICE_UNKNOWN (0xFFFF) 1743 1744 /***************************************************************************** 1745 * IO Unit Page 10 * 1746 ****************************************************************************/ 1747 1748 typedef struct _MPI3_IO_UNIT_PAGE10 1749 { 1750 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1751 U8 Flags; /* 0x08 */ 1752 U8 Reserved09[3]; /* 0x09 */ 1753 U32 SiliconID; /* 0x0C */ 1754 U8 FWVersionMinor; /* 0x10 */ 1755 U8 FWVersionMajor; /* 0x11 */ 1756 U8 HWVersionMinor; /* 0x12 */ 1757 U8 HWVersionMajor; /* 0x13 */ 1758 U8 PartNumber[16]; /* 0x14 */ 1759 } MPI3_IO_UNIT_PAGE10, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE10, 1760 Mpi3IOUnitPage10_t, MPI3_POINTER pMpi3IOUnitPage10_t; 1761 1762 /**** Defines for the PageVersion field ****/ 1763 #define MPI3_IOUNIT10_PAGEVERSION (0x00) 1764 1765 /**** Defines for the Flags field ****/ 1766 #define MPI3_IOUNIT10_FLAGS_VALID (0x01) 1767 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_MASK (0x02) 1768 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_FIRST_REGION (0x00) 1769 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_SECOND_REGION (0x02) 1770 #define MPI3_IOUNIT10_FLAGS_PBLP_EXPECTED (0x80) 1771 1772 /***************************************************************************** 1773 * IO Unit Page 11 * 1774 ****************************************************************************/ 1775 1776 #ifndef MPI3_IOUNIT11_PROFILE_MAX 1777 #define MPI3_IOUNIT11_PROFILE_MAX (1) 1778 #endif /* MPI3_IOUNIT11_PROFILE_MAX */ 1779 1780 typedef struct _MPI3_IOUNIT11_PROFILE 1781 { 1782 U8 ProfileIdentifier; /* 0x00 */ 1783 U8 Reserved01[3]; /* 0x01 */ 1784 U16 MaxVDs; /* 0x04 */ 1785 U16 MaxHostPDs; /* 0x06 */ 1786 U16 MaxAdvHostPDs; /* 0x08 */ 1787 U16 MaxRAIDPDs; /* 0x0A */ 1788 U16 MaxNVMe; /* 0x0C */ 1789 U16 MaxOutstandingRequests; /* 0x0E */ 1790 U16 SubsystemID; /* 0x10 */ 1791 U16 Reserved12; /* 0x12 */ 1792 U32 Reserved14[2]; /* 0x14 */ 1793 } MPI3_IOUNIT11_PROFILE, MPI3_POINTER PTR_MPI3_IOUNIT11_PROFILE, 1794 Mpi3IOUnit11Profile_t, MPI3_POINTER pMpi3IOUnit11Profile_t; 1795 1796 typedef struct _MPI3_IO_UNIT_PAGE11 1797 { 1798 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1799 U32 Reserved08; /* 0x08 */ 1800 U8 NumProfiles; /* 0x0C */ 1801 U8 CurrentProfileIdentifier; /* 0x0D */ 1802 U16 Reserved0E; /* 0x0E */ 1803 MPI3_IOUNIT11_PROFILE Profile[MPI3_IOUNIT11_PROFILE_MAX]; /* 0x10 */ /* variable length */ 1804 } MPI3_IO_UNIT_PAGE11, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE11, 1805 Mpi3IOUnitPage11_t, MPI3_POINTER pMpi3IOUnitPage11_t; 1806 1807 /**** Defines for the PageVersion field ****/ 1808 #define MPI3_IOUNIT11_PAGEVERSION (0x00) 1809 1810 /***************************************************************************** 1811 * IO Unit Page 12 * 1812 ****************************************************************************/ 1813 1814 #ifndef MPI3_IOUNIT12_BUCKET_MAX 1815 #define MPI3_IOUNIT12_BUCKET_MAX (1) 1816 #endif /* MPI3_IOUNIT12_BUCKET_MAX */ 1817 1818 typedef struct _MPI3_IOUNIT12_BUCKET 1819 { 1820 U8 CoalescingDepth; /* 0x00 */ 1821 U8 CoalescingTimeout; /* 0x01 */ 1822 U16 IOCountLowBoundary; /* 0x02 */ 1823 U32 Reserved04; /* 0x04 */ 1824 } MPI3_IOUNIT12_BUCKET, MPI3_POINTER PTR_MPI3_IOUNIT12_BUCKET, 1825 Mpi3IOUnit12Bucket_t, MPI3_POINTER pMpi3IOUnit12Bucket_t; 1826 1827 typedef struct _MPI3_IO_UNIT_PAGE12 1828 { 1829 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1830 U32 Flags; /* 0x08 */ 1831 U32 Reserved0C[4]; /* 0x0C */ 1832 U8 NumBuckets; /* 0x1C */ 1833 U8 Reserved1D[3]; /* 0x1D */ 1834 MPI3_IOUNIT12_BUCKET Bucket[MPI3_IOUNIT12_BUCKET_MAX]; /* 0x20 */ /* variable length */ 1835 } MPI3_IO_UNIT_PAGE12, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE12, 1836 Mpi3IOUnitPage12_t, MPI3_POINTER pMpi3IOUnitPage12_t; 1837 1838 /**** Defines for the PageVersion field ****/ 1839 #define MPI3_IOUNIT12_PAGEVERSION (0x00) 1840 1841 /**** Defines for the Flags field ****/ 1842 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_MASK (0x00000300) 1843 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_SHIFT (8) 1844 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_8 (0x00000000) 1845 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_16 (0x00000100) 1846 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_32 (0x00000200) 1847 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_64 (0x00000300) 1848 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_MASK (0x00000003) 1849 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_DISABLED (0x00000000) 1850 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_500US (0x00000001) 1851 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_1MS (0x00000002) 1852 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_2MS (0x00000003) 1853 1854 /***************************************************************************** 1855 * IO Unit Page 13 * 1856 ****************************************************************************/ 1857 1858 #ifndef MPI3_IOUNIT13_FUNC_MAX 1859 #define MPI3_IOUNIT13_FUNC_MAX (1) 1860 #endif /* MPI3_IOUNIT13_FUNC_MAX */ 1861 1862 typedef struct _MPI3_IOUNIT13_ALLOWED_FUNCTION 1863 { 1864 U16 SubFunction; /* 0x00 */ 1865 U8 FunctionCode; /* 0x02 */ 1866 U8 FunctionFlags; /* 0x03 */ 1867 } MPI3_IOUNIT13_ALLOWED_FUNCTION, MPI3_POINTER PTR_MPI3_IOUNIT13_ALLOWED_FUNCTION, 1868 Mpi3IOUnit13AllowedFunction_t, MPI3_POINTER pMpi3IOUnit13AllowedFunction_t; 1869 1870 /**** Defines for the FunctionFlags field ****/ 1871 #define MPI3_IOUNIT13_FUNCTION_FLAGS_ADMIN_BLOCKED (0x04) 1872 #define MPI3_IOUNIT13_FUNCTION_FLAGS_OOB_BLOCKED (0x02) 1873 #define MPI3_IOUNIT13_FUNCTION_FLAGS_CHECK_SUBFUNCTION_ENABLED (0x01) 1874 1875 typedef struct _MPI3_IO_UNIT_PAGE13 1876 { 1877 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1878 U16 Flags; /* 0x08 */ 1879 U16 Reserved0A; /* 0x0A */ 1880 U8 NumAllowedFunctions; /* 0x0C */ 1881 U8 Reserved0D[3]; /* 0x0D */ 1882 MPI3_IOUNIT13_ALLOWED_FUNCTION AllowedFunction[MPI3_IOUNIT13_FUNC_MAX]; /* 0x10 */ /* variable length */ 1883 } MPI3_IO_UNIT_PAGE13, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE13, 1884 Mpi3IOUnitPage13_t, MPI3_POINTER pMpi3IOUnitPage13_t; 1885 1886 /**** Defines for the PageVersion field ****/ 1887 #define MPI3_IOUNIT13_PAGEVERSION (0x00) 1888 1889 /**** Defines for the Flags field ****/ 1890 #define MPI3_IOUNIT13_FLAGS_ADMIN_BLOCKED (0x0002) 1891 #define MPI3_IOUNIT13_FLAGS_OOB_BLOCKED (0x0001) 1892 1893 /***************************************************************************** 1894 * IO Unit Page 14 * 1895 ****************************************************************************/ 1896 1897 #ifndef MPI3_IOUNIT14_MD_MAX 1898 #define MPI3_IOUNIT14_MD_MAX (1) 1899 #endif /* MPI3_IOUNIT14_MD_MAX */ 1900 1901 typedef struct _MPI3_IOUNIT14_PAGEMETADATA 1902 { 1903 U8 PageType; /* 0x00 */ 1904 U8 PageNumber; /* 0x01 */ 1905 U8 Reserved02; /* 0x02 */ 1906 U8 PageFlags; /* 0x03 */ 1907 } MPI3_IOUNIT14_PAGEMETADATA, MPI3_POINTER PTR_MPI3_IOUNIT14_PAGEMETADATA, 1908 Mpi3IOUnit14PageMetadata_t, MPI3_POINTER pMpi3IOUnit14PageMetadata_t; 1909 1910 /**** Defines for the PageFlags field ****/ 1911 #define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_OOBWRITE_ALLOWED (0x02) 1912 #define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_HOSTWRITE_ALLOWED (0x01) 1913 1914 typedef struct _MPI3_IO_UNIT_PAGE14 1915 { 1916 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1917 U8 Flags; /* 0x08 */ 1918 U8 Reserved09[3]; /* 0x09 */ 1919 U8 NumPages; /* 0x0C */ 1920 U8 Reserved0D[3]; /* 0x0D */ 1921 MPI3_IOUNIT14_PAGEMETADATA PageMetadata[MPI3_IOUNIT14_MD_MAX]; /* 0x10 */ /* variable length */ 1922 } MPI3_IO_UNIT_PAGE14, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE14, 1923 Mpi3IOUnitPage14_t, MPI3_POINTER pMpi3IOUnitPage14_t; 1924 1925 /**** Defines for the PageVersion field ****/ 1926 #define MPI3_IOUNIT14_PAGEVERSION (0x00) 1927 1928 /**** Defines for the Flags field ****/ 1929 #define MPI3_IOUNIT14_FLAGS_READONLY (0x01) 1930 1931 /***************************************************************************** 1932 * IO Unit Page 15 * 1933 ****************************************************************************/ 1934 1935 #ifndef MPI3_IOUNIT15_PBD_MAX 1936 #define MPI3_IOUNIT15_PBD_MAX (1) 1937 #endif /* MPI3_IOUNIT15_PBD_MAX */ 1938 1939 typedef struct _MPI3_IO_UNIT_PAGE15 1940 { 1941 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1942 U8 Flags; /* 0x08 */ 1943 U8 Reserved09[3]; /* 0x09 */ 1944 U32 Reserved0C; /* 0x0C */ 1945 U8 PowerBudgetingCapability; /* 0x10 */ 1946 U8 Reserved11[3]; /* 0x11 */ 1947 U8 NumPowerBudgetData; /* 0x14 */ 1948 U8 Reserved15[3]; /* 0x15 */ 1949 U32 PowerBudgetData[MPI3_IOUNIT15_PBD_MAX]; /* 0x18 */ /* variable length */ 1950 } MPI3_IO_UNIT_PAGE15, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE15, 1951 Mpi3IOUnitPage15_t, MPI3_POINTER pMpi3IOUnitPage15_t; 1952 1953 /**** Defines for the PageVersion field ****/ 1954 #define MPI3_IOUNIT15_PAGEVERSION (0x00) 1955 1956 /**** Defines for the Flags field ****/ 1957 #define MPI3_IOUNIT15_FLAGS_EPRINIT_INITREQUIRED (0x04) 1958 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_MASK (0x03) 1959 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_NOT_SUPPORTED (0x00) 1960 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITHOUT_POWER_BRAKE_GPIO (0x01) 1961 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITH_POWER_BRAKE_GPIO (0x02) 1962 1963 /**** Defines for the NumPowerBudgetData field ****/ 1964 #define MPI3_IOUNIT15_NUMPOWERBUDGETDATA_POWER_BUDGETING_DISABLED (0x00) 1965 1966 /***************************************************************************** 1967 * IO Unit Page 16 * 1968 ****************************************************************************/ 1969 1970 #ifndef MPI3_IOUNIT16_ERROR_MAX 1971 #define MPI3_IOUNIT16_ERROR_MAX (1) 1972 #endif /* MPI3_IOUNIT16_ERROR_MAX */ 1973 1974 typedef struct _MPI3_IOUNIT16_ERROR 1975 { 1976 U32 Offset; /* 0x00 */ 1977 U32 Reserved04; /* 0x04 */ 1978 U64 Count; /* 0x08 */ 1979 U64 Timestamp; /* 0x10 */ 1980 } MPI3_IOUNIT16_ERROR, MPI3_POINTER PTR_MPI3_IOUNIT16_ERROR, 1981 Mpi3IOUnit16Error_t, MPI3_POINTER pMpi3IOUnit16Error_t; 1982 1983 typedef struct _MPI3_IO_UNIT_PAGE16 1984 { 1985 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1986 U64 TotalErrorCount; /* 0x08 */ 1987 U32 Reserved10[3]; /* 0x10 */ 1988 U8 NumErrors; /* 0x1C */ 1989 U8 MaxErrorsTracked; /* 0x1D */ 1990 U16 Reserved1E; /* 0x1E */ 1991 MPI3_IOUNIT16_ERROR Error[MPI3_IOUNIT16_ERROR_MAX]; /* 0x20 */ /* variable length */ 1992 } MPI3_IO_UNIT_PAGE16, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE16, 1993 Mpi3IOUnitPage16_t, MPI3_POINTER pMpi3IOUnitPage16_t; 1994 1995 /**** Defines for the PageVersion field ****/ 1996 #define MPI3_IOUNIT16_PAGEVERSION (0x00) 1997 1998 /***************************************************************************** 1999 * IOC Configuration Pages * 2000 ****************************************************************************/ 2001 2002 /***************************************************************************** 2003 * IOC Page 0 * 2004 ****************************************************************************/ 2005 typedef struct _MPI3_IOC_PAGE0 2006 { 2007 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2008 U32 Reserved08; /* 0x08 */ 2009 U16 VendorID; /* 0x0C */ 2010 U16 DeviceID; /* 0x0E */ 2011 U8 RevisionID; /* 0x10 */ 2012 U8 Reserved11[3]; /* 0x11 */ 2013 U32 ClassCode; /* 0x14 */ 2014 U16 SubsystemVendorID; /* 0x18 */ 2015 U16 SubsystemID; /* 0x1A */ 2016 } MPI3_IOC_PAGE0, MPI3_POINTER PTR_MPI3_IOC_PAGE0, 2017 Mpi3IOCPage0_t, MPI3_POINTER pMpi3IOCPage0_t; 2018 2019 /**** Defines for the PageVersion field ****/ 2020 #define MPI3_IOC0_PAGEVERSION (0x00) 2021 2022 /***************************************************************************** 2023 * IOC Page 1 * 2024 ****************************************************************************/ 2025 typedef struct _MPI3_IOC_PAGE1 2026 { 2027 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2028 U32 CoalescingTimeout; /* 0x08 */ 2029 U8 CoalescingDepth; /* 0x0C */ 2030 U8 Obsolete; /* 0x0D */ 2031 U16 Reserved0E; /* 0x0E */ 2032 } MPI3_IOC_PAGE1, MPI3_POINTER PTR_MPI3_IOC_PAGE1, 2033 Mpi3IOCPage1_t, MPI3_POINTER pMpi3IOCPage1_t; 2034 2035 /**** Defines for the PageVersion field ****/ 2036 #define MPI3_IOC1_PAGEVERSION (0x00) 2037 2038 /***************************************************************************** 2039 * IOC Page 2 * 2040 ****************************************************************************/ 2041 #ifndef MPI3_IOC2_EVENTMASK_WORDS 2042 #define MPI3_IOC2_EVENTMASK_WORDS (4) 2043 #endif /* MPI3_IOC2_EVENTMASK_WORDS */ 2044 2045 typedef struct _MPI3_IOC_PAGE2 2046 { 2047 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2048 U32 Reserved08; /* 0x08 */ 2049 U16 SASBroadcastPrimitiveMasks; /* 0x0C */ 2050 U16 SASNotifyPrimitiveMasks; /* 0x0E */ 2051 U32 EventMasks[MPI3_IOC2_EVENTMASK_WORDS]; /* 0x10 */ 2052 } MPI3_IOC_PAGE2, MPI3_POINTER PTR_MPI3_IOC_PAGE2, 2053 Mpi3IOCPage2_t, MPI3_POINTER pMpi3IOCPage2_t; 2054 2055 /**** Defines for the PageVersion field ****/ 2056 #define MPI3_IOC2_PAGEVERSION (0x00) 2057 2058 2059 /***************************************************************************** 2060 * Driver Configuration Pages * 2061 ****************************************************************************/ 2062 2063 /**** Defines for the Flags field in Driver Pages 10, 20, and 30 ****/ 2064 /**** NOT used in Driver Page 1 Flags field ****/ 2065 #define MPI3_DRIVER_FLAGS_ADMINRAIDPD_BLOCKED (0x0010) 2066 #define MPI3_DRIVER_FLAGS_OOBRAIDPD_BLOCKED (0x0008) 2067 #define MPI3_DRIVER_FLAGS_OOBRAIDVD_BLOCKED (0x0004) 2068 #define MPI3_DRIVER_FLAGS_OOBADVHOSTPD_BLOCKED (0x0002) 2069 #define MPI3_DRIVER_FLAGS_OOBHOSTPD_BLOCKED (0x0001) 2070 2071 typedef struct _MPI3_ALLOWED_CMD_SCSI 2072 { 2073 U16 ServiceAction; /* 0x00 */ 2074 U8 OperationCode; /* 0x02 */ 2075 U8 CommandFlags; /* 0x03 */ 2076 } MPI3_ALLOWED_CMD_SCSI, MPI3_POINTER PTR_MPI3_ALLOWED_CMD_SCSI, 2077 Mpi3AllowedCmdScsi_t, MPI3_POINTER pMpi3AllowedCmdScsi_t; 2078 2079 typedef struct _MPI3_ALLOWED_CMD_ATA 2080 { 2081 U8 Subcommand; /* 0x00 */ 2082 U8 Reserved01; /* 0x01 */ 2083 U8 Command; /* 0x02 */ 2084 U8 CommandFlags; /* 0x03 */ 2085 } MPI3_ALLOWED_CMD_ATA, MPI3_POINTER PTR_MPI3_ALLOWED_CMD_ATA, 2086 Mpi3AllowedCmdAta_t, MPI3_POINTER pMpi3AllowedCmdAta_t; 2087 2088 typedef struct _MPI3_ALLOWED_CMD_NVME 2089 { 2090 U8 Reserved00; /* 0x00 */ 2091 U8 NVMeCmdFlags; /* 0x01 */ 2092 U8 OpCode; /* 0x02 */ 2093 U8 CommandFlags; /* 0x03 */ 2094 } MPI3_ALLOWED_CMD_NVME, MPI3_POINTER PTR_MPI3_ALLOWED_CMD_NVME, 2095 Mpi3AllowedCmdNvme_t, MPI3_POINTER pMpi3AllowedCmdNvme_t; 2096 2097 /**** Defines for the NVMeCmdFlags field ****/ 2098 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_MASK (0x80) 2099 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_IO (0x00) 2100 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_ADMIN (0x80) 2101 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_MASK (0x3F) 2102 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_NVM (0x00) 2103 2104 typedef union _MPI3_ALLOWED_CMD 2105 { 2106 MPI3_ALLOWED_CMD_SCSI Scsi; 2107 MPI3_ALLOWED_CMD_ATA Ata; 2108 MPI3_ALLOWED_CMD_NVME NVMe; 2109 } MPI3_ALLOWED_CMD, MPI3_POINTER PTR_MPI3_ALLOWED_CMD, 2110 Mpi3AllowedCmd_t, MPI3_POINTER pMpi3AllowedCmd_t; 2111 2112 /**** Defines for the CommandFlags field ****/ 2113 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_ADMINRAIDPD_BLOCKED (0x20) 2114 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDPD_BLOCKED (0x10) 2115 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDVD_BLOCKED (0x08) 2116 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBADVHOSTPD_BLOCKED (0x04) 2117 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBHOSTPD_BLOCKED (0x02) 2118 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_CHECKSUBCMD_ENABLED (0x01) 2119 2120 2121 #ifndef MPI3_ALLOWED_CMDS_MAX 2122 #define MPI3_ALLOWED_CMDS_MAX (1) 2123 #endif /* MPI3_ALLOWED_CMDS_MAX */ 2124 2125 /***************************************************************************** 2126 * Driver Page 0 * 2127 ****************************************************************************/ 2128 typedef struct _MPI3_DRIVER_PAGE0 2129 { 2130 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2131 U32 BSDOptions; /* 0x08 */ 2132 U8 SSUTimeout; /* 0x0C */ 2133 U8 IOTimeout; /* 0x0D */ 2134 U8 TURRetries; /* 0x0E */ 2135 U8 TURInterval; /* 0x0F */ 2136 U8 Reserved10; /* 0x10 */ 2137 U8 SecurityKeyTimeout; /* 0x11 */ 2138 U16 Reserved12; /* 0x12 */ 2139 U32 Reserved14; /* 0x14 */ 2140 U32 Reserved18; /* 0x18 */ 2141 } MPI3_DRIVER_PAGE0, MPI3_POINTER PTR_MPI3_DRIVER_PAGE0, 2142 Mpi3DriverPage0_t, MPI3_POINTER pMpi3DriverPage0_t; 2143 2144 /**** Defines for the PageVersion field ****/ 2145 #define MPI3_DRIVER0_PAGEVERSION (0x00) 2146 2147 /**** Defines for the BSDOptions field ****/ 2148 #define MPI3_DRIVER0_BSDOPTS_DEVICEEXPOSURE_DISABLE (0x00000020) 2149 #define MPI3_DRIVER0_BSDOPTS_WRITECACHE_DISABLE (0x00000010) 2150 #define MPI3_DRIVER0_BSDOPTS_HEADLESS_MODE_ENABLE (0x00000008) 2151 #define MPI3_DRIVER0_BSDOPTS_DIS_HII_CONFIG_UTIL (0x00000004) 2152 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_MASK (0x00000003) 2153 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_DEVS (0x00000000) 2154 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_ONLY (0x00000001) 2155 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_INTERNAL_DEVS (0x00000002) 2156 2157 /***************************************************************************** 2158 * Driver Page 1 * 2159 ****************************************************************************/ 2160 typedef struct _MPI3_DRIVER_PAGE1 2161 { 2162 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2163 U32 Flags; /* 0x08 */ 2164 U32 Reserved0C; /* 0x0C */ 2165 U16 HostDiagTraceMaxSize; /* 0x10 */ 2166 U16 HostDiagTraceMinSize; /* 0x12 */ 2167 U16 HostDiagTraceDecrementSize; /* 0x14 */ 2168 U16 Reserved16; /* 0x16 */ 2169 U16 HostDiagFwMaxSize; /* 0x18 */ 2170 U16 HostDiagFwMinSize; /* 0x1A */ 2171 U16 HostDiagFwDecrementSize; /* 0x1C */ 2172 U16 Reserved1E; /* 0x1E */ 2173 U16 HostDiagDriverMaxSize; /* 0x20 */ 2174 U16 HostDiagDriverMinSize; /* 0x22 */ 2175 U16 HostDiagDriverDecrementSize; /* 0x24 */ 2176 U16 Reserved26; /* 0x26 */ 2177 } MPI3_DRIVER_PAGE1, MPI3_POINTER PTR_MPI3_DRIVER_PAGE1, 2178 Mpi3DriverPage1_t, MPI3_POINTER pMpi3DriverPage1_t; 2179 2180 /**** Defines for the PageVersion field ****/ 2181 #define MPI3_DRIVER1_PAGEVERSION (0x00) 2182 2183 /***************************************************************************** 2184 * Driver Page 2 * 2185 ****************************************************************************/ 2186 #ifndef MPI3_DRIVER2_TRIGGER_MAX 2187 #define MPI3_DRIVER2_TRIGGER_MAX (1) 2188 #endif /* MPI3_DRIVER2_TRIGGER_MAX */ 2189 2190 typedef struct _MPI3_DRIVER2_TRIGGER_EVENT 2191 { 2192 U8 Type; /* 0x00 */ 2193 U8 Flags; /* 0x01 */ 2194 U8 Reserved02; /* 0x02 */ 2195 U8 Event; /* 0x03 */ 2196 U32 Reserved04[3]; /* 0x04 */ 2197 } MPI3_DRIVER2_TRIGGER_EVENT, MPI3_POINTER PTR_MPI3_DRIVER2_TRIGGER_EVENT, 2198 Mpi3Driver2TriggerEvent_t, MPI3_POINTER pMpi3Driver2TriggerEvent_t; 2199 2200 typedef struct _MPI3_DRIVER2_TRIGGER_SCSI_SENSE 2201 { 2202 U8 Type; /* 0x00 */ 2203 U8 Flags; /* 0x01 */ 2204 U16 Reserved02; /* 0x02 */ 2205 U8 ASCQ; /* 0x04 */ 2206 U8 ASC; /* 0x05 */ 2207 U8 SenseKey; /* 0x06 */ 2208 U8 Reserved07; /* 0x07 */ 2209 U32 Reserved08[2]; /* 0x08 */ 2210 } MPI3_DRIVER2_TRIGGER_SCSI_SENSE, MPI3_POINTER PTR_MPI3_DRIVER2_TRIGGER_SCSI_SENSE, 2211 Mpi3Driver2TriggerScsiSense_t, MPI3_POINTER pMpi3Driver2TriggerScsiSense_t; 2212 2213 /**** Defines for the ASCQ field ****/ 2214 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASCQ_MATCH_ALL (0xFF) 2215 2216 /**** Defines for the ASC field ****/ 2217 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASC_MATCH_ALL (0xFF) 2218 2219 /**** Defines for the SenseKey field ****/ 2220 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_SENSE_KEY_MATCH_ALL (0xFF) 2221 2222 typedef struct _MPI3_DRIVER2_TRIGGER_REPLY 2223 { 2224 U8 Type; /* 0x00 */ 2225 U8 Flags; /* 0x01 */ 2226 U16 IOCStatus; /* 0x02 */ 2227 U32 IOCLogInfo; /* 0x04 */ 2228 U32 IOCLogInfoMask; /* 0x08 */ 2229 U32 Reserved0C; /* 0x0C */ 2230 } MPI3_DRIVER2_TRIGGER_REPLY, MPI3_POINTER PTR_MPI3_DRIVER2_TRIGGER_REPLY, 2231 Mpi3Driver2TriggerReply_t, MPI3_POINTER pMpi3Driver2TriggerReply_t; 2232 2233 /**** Defines for the IOCStatus field ****/ 2234 #define MPI3_DRIVER2_TRIGGER_REPLY_IOCSTATUS_MATCH_ALL (0xFFFF) 2235 2236 typedef union _MPI3_DRIVER2_TRIGGER_ELEMENT 2237 { 2238 MPI3_DRIVER2_TRIGGER_EVENT Event; 2239 MPI3_DRIVER2_TRIGGER_SCSI_SENSE ScsiSense; 2240 MPI3_DRIVER2_TRIGGER_REPLY Reply; 2241 } MPI3_DRIVER2_TRIGGER_ELEMENT, MPI3_POINTER PTR_MPI3_DRIVER2_TRIGGER_ELEMENT, 2242 Mpi3Driver2TriggerElement_t, MPI3_POINTER pMpi3Driver2TriggerElement_t; 2243 2244 /**** Defines for the Type field ****/ 2245 #define MPI3_DRIVER2_TRIGGER_TYPE_EVENT (0x00) 2246 #define MPI3_DRIVER2_TRIGGER_TYPE_SCSI_SENSE (0x01) 2247 #define MPI3_DRIVER2_TRIGGER_TYPE_REPLY (0x02) 2248 2249 /**** Defines for the Flags field ****/ 2250 #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_TRACE_RELEASE (0x02) 2251 #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_FW_RELEASE (0x01) 2252 2253 typedef struct _MPI3_DRIVER_PAGE2 2254 { 2255 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2256 U64 GlobalTrigger; /* 0x08 */ 2257 U32 Reserved10[3]; /* 0x10 */ 2258 U8 NumTriggers; /* 0x1C */ 2259 U8 Reserved1D[3]; /* 0x1D */ 2260 MPI3_DRIVER2_TRIGGER_ELEMENT Trigger[MPI3_DRIVER2_TRIGGER_MAX]; /* 0x20 */ /* variable length */ 2261 } MPI3_DRIVER_PAGE2, MPI3_POINTER PTR_MPI3_DRIVER_PAGE2, 2262 Mpi3DriverPage2_t, MPI3_POINTER pMpi3DriverPage2_t; 2263 2264 /**** Defines for the PageVersion field ****/ 2265 #define MPI3_DRIVER2_PAGEVERSION (0x00) 2266 2267 /**** Defines for the GlobalTrigger field ****/ 2268 #define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_TRACE_RELEASE (0x8000000000000000ULL) 2269 #define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_FW_RELEASE (0x4000000000000000ULL) 2270 #define MPI3_DRIVER2_GLOBALTRIGGER_SNAPDUMP_ENABLED (0x2000000000000000ULL) 2271 #define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_TRACE_DISABLED (0x1000000000000000ULL) 2272 #define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_FW_DISABLED (0x0800000000000000ULL) 2273 #define MPI3_DRIVER2_GLOBALTRIGGER_DEVICE_REMOVAL_ENABLED (0x0000000000000004ULL) 2274 #define MPI3_DRIVER2_GLOBALTRIGGER_TASK_MANAGEMENT_ENABLED (0x0000000000000002ULL) 2275 2276 /***************************************************************************** 2277 * Driver Page 10 * 2278 ****************************************************************************/ 2279 2280 typedef struct _MPI3_DRIVER_PAGE10 2281 { 2282 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2283 U16 Flags; /* 0x08 */ 2284 U16 Reserved0A; /* 0x0A */ 2285 U8 NumAllowedCommands; /* 0x0C */ 2286 U8 Reserved0D[3]; /* 0x0D */ 2287 MPI3_ALLOWED_CMD AllowedCommand[MPI3_ALLOWED_CMDS_MAX]; /* 0x10 */ /* variable length */ 2288 } MPI3_DRIVER_PAGE10, MPI3_POINTER PTR_MPI3_DRIVER_PAGE10, 2289 Mpi3DriverPage10_t, MPI3_POINTER pMpi3DriverPage10_t; 2290 2291 /**** Defines for the PageVersion field ****/ 2292 #define MPI3_DRIVER10_PAGEVERSION (0x00) 2293 2294 /**** Defines for the Flags field - use MPI3_DRIVER_FLAGS_ defines ****/ 2295 2296 /***************************************************************************** 2297 * Driver Page 20 * 2298 ****************************************************************************/ 2299 2300 typedef struct _MPI3_DRIVER_PAGE20 2301 { 2302 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2303 U16 Flags; /* 0x08 */ 2304 U16 Reserved0A; /* 0x0A */ 2305 U8 NumAllowedCommands; /* 0x0C */ 2306 U8 Reserved0D[3]; /* 0x0D */ 2307 MPI3_ALLOWED_CMD AllowedCommand[MPI3_ALLOWED_CMDS_MAX]; /* 0x10 */ /* variable length */ 2308 } MPI3_DRIVER_PAGE20, MPI3_POINTER PTR_MPI3_DRIVER_PAGE20, 2309 Mpi3DriverPage20_t, MPI3_POINTER pMpi3DriverPage20_t; 2310 2311 /**** Defines for the PageVersion field ****/ 2312 #define MPI3_DRIVER20_PAGEVERSION (0x00) 2313 2314 /**** Defines for the Flags field - use MPI3_DRIVER_FLAGS_ defines ****/ 2315 2316 /***************************************************************************** 2317 * Driver Page 30 * 2318 ****************************************************************************/ 2319 2320 typedef struct _MPI3_DRIVER_PAGE30 2321 { 2322 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2323 U16 Flags; /* 0x08 */ 2324 U16 Reserved0A; /* 0x0A */ 2325 U8 NumAllowedCommands; /* 0x0C */ 2326 U8 Reserved0D[3]; /* 0x0D */ 2327 MPI3_ALLOWED_CMD AllowedCommand[MPI3_ALLOWED_CMDS_MAX]; /* 0x10 */ /* variable length */ 2328 } MPI3_DRIVER_PAGE30, MPI3_POINTER PTR_MPI3_DRIVER_PAGE30, 2329 Mpi3DriverPage30_t, MPI3_POINTER pMpi3DriverPage30_t; 2330 2331 /**** Defines for the PageVersion field ****/ 2332 #define MPI3_DRIVER30_PAGEVERSION (0x00) 2333 2334 /**** Defines for the Flags field - use MPI3_DRIVER_FLAGS_ defines ****/ 2335 2336 /***************************************************************************** 2337 * Security Configuration Pages * 2338 ****************************************************************************/ 2339 2340 typedef union _MPI3_SECURITY_MAC 2341 { 2342 U32 Dword[16]; 2343 U16 Word[32]; 2344 U8 Byte[64]; 2345 } MPI3_SECURITY_MAC, MPI3_POINTER PTR_MPI3_SECURITY_MAC, 2346 Mpi3SecurityMAC_t, MPI3_POINTER pMpi3SecurityMAC_t; 2347 2348 typedef union _MPI3_SECURITY_NONCE 2349 { 2350 U32 Dword[16]; 2351 U16 Word[32]; 2352 U8 Byte[64]; 2353 } MPI3_SECURITY_NONCE, MPI3_POINTER PTR_MPI3_SECURITY_NONCE, 2354 Mpi3SecurityNonce_t, MPI3_POINTER pMpi3SecurityNonce_t; 2355 2356 /***************************************************************************** 2357 * Security Page 0 * 2358 ****************************************************************************/ 2359 2360 typedef union _MPI3_SECURITY0_CERT_CHAIN 2361 { 2362 U32 Dword[1024]; 2363 U16 Word[2048]; 2364 U8 Byte[4096]; 2365 } MPI3_SECURITY0_CERT_CHAIN, MPI3_POINTER PTR_MPI3_SECURITY0_CERT_CHAIN, 2366 Mpi3Security0CertChain_t, MPI3_POINTER pMpi3Security0CertChain_t; 2367 2368 typedef struct _MPI3_SECURITY_PAGE0 2369 { 2370 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2371 U8 SlotNumGroup; /* 0x08 */ 2372 U8 SlotNum; /* 0x09 */ 2373 U16 CertChainLength; /* 0x0A */ 2374 U8 CertChainFlags; /* 0x0C */ 2375 U8 Reserved0D[3]; /* 0x0D */ 2376 U32 BaseAsymAlgo; /* 0x10 */ 2377 U32 BaseHashAlgo; /* 0x14 */ 2378 U32 Reserved18[4]; /* 0x18 */ 2379 MPI3_SECURITY_MAC Mac; /* 0x28 */ 2380 MPI3_SECURITY_NONCE Nonce; /* 0x68 */ 2381 MPI3_SECURITY0_CERT_CHAIN CertificateChain; /* 0xA8 */ 2382 } MPI3_SECURITY_PAGE0, MPI3_POINTER PTR_MPI3_SECURITY_PAGE0, 2383 Mpi3SecurityPage0_t, MPI3_POINTER pMpi3SecurityPage0_t; 2384 2385 /**** Defines for the PageVersion field ****/ 2386 #define MPI3_SECURITY0_PAGEVERSION (0x00) 2387 2388 /**** Defines for the CertChainFlags field ****/ 2389 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_MASK (0x0E) 2390 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_UNUSED (0x00) 2391 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_CERBERUS (0x02) 2392 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_SPDM (0x04) 2393 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_SEALED (0x01) 2394 2395 /***************************************************************************** 2396 * Security Page 1 * 2397 ****************************************************************************/ 2398 2399 #ifndef MPI3_SECURITY1_KEY_RECORD_MAX 2400 #define MPI3_SECURITY1_KEY_RECORD_MAX 1 2401 #endif /* MPI3_SECURITY1_KEY_RECORD_MAX */ 2402 2403 #ifndef MPI3_SECURITY1_PAD_MAX 2404 #define MPI3_SECURITY1_PAD_MAX 4 2405 #endif /* MPI3_SECURITY1_PAD_MAX */ 2406 2407 typedef union _MPI3_SECURITY1_KEY_DATA 2408 { 2409 U32 Dword[128]; 2410 U16 Word[256]; 2411 U8 Byte[512]; 2412 } MPI3_SECURITY1_KEY_DATA, MPI3_POINTER PTR_MPI3_SECURITY1_KEY_DATA, 2413 Mpi3Security1KeyData_t, MPI3_POINTER pMpi3Security1KeyData_t; 2414 2415 typedef struct _MPI3_SECURITY1_KEY_RECORD 2416 { 2417 U8 Flags; /* 0x00 */ 2418 U8 Consumer; /* 0x01 */ 2419 U16 KeyDataSize; /* 0x02 */ 2420 U32 AdditionalKeyData; /* 0x04 */ 2421 U32 Reserved08[2]; /* 0x08 */ 2422 MPI3_SECURITY1_KEY_DATA KeyData; /* 0x10 */ 2423 } MPI3_SECURITY1_KEY_RECORD, MPI3_POINTER PTR_MPI3_SECURITY1_KEY_RECORD, 2424 Mpi3Security1KeyRecord_t, MPI3_POINTER pMpi3Security1KeyRecord_t; 2425 2426 /**** Defines for the Flags field ****/ 2427 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_MASK (0x1F) 2428 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_NOT_VALID (0x00) 2429 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_HMAC (0x01) 2430 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_AES (0x02) 2431 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PRIVATE (0x03) 2432 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PUBLIC (0x04) 2433 2434 /**** Defines for the Consumer field ****/ 2435 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_NOT_VALID (0x00) 2436 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_SAFESTORE (0x01) 2437 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CERT_CHAIN (0x02) 2438 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_DEVICE_KEY (0x03) 2439 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CACHE_OFFLOAD (0x04) 2440 2441 typedef struct _MPI3_SECURITY_PAGE1 2442 { 2443 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2444 U32 Reserved08[2]; /* 0x08 */ 2445 MPI3_SECURITY_MAC Mac; /* 0x10 */ 2446 MPI3_SECURITY_NONCE Nonce; /* 0x50 */ 2447 U8 NumKeys; /* 0x90 */ 2448 U8 Reserved91[3]; /* 0x91 */ 2449 U32 Reserved94[3]; /* 0x94 */ 2450 MPI3_SECURITY1_KEY_RECORD KeyRecord[MPI3_SECURITY1_KEY_RECORD_MAX]; /* 0xA0 */ 2451 U8 Pad[MPI3_SECURITY1_PAD_MAX]; /* ?? */ 2452 } MPI3_SECURITY_PAGE1, MPI3_POINTER PTR_MPI3_SECURITY_PAGE1, 2453 Mpi3SecurityPage1_t, MPI3_POINTER pMpi3SecurityPage1_t; 2454 2455 /**** Defines for the PageVersion field ****/ 2456 #define MPI3_SECURITY1_PAGEVERSION (0x00) 2457 2458 2459 /***************************************************************************** 2460 * Security Page 2 * 2461 ****************************************************************************/ 2462 2463 #ifndef MPI3_SECURITY2_TRUSTED_ROOT_MAX 2464 #define MPI3_SECURITY2_TRUSTED_ROOT_MAX 1 2465 #endif /* MPI3_SECURITY2_TRUSTED_ROOT_MAX */ 2466 2467 #ifndef MPI3_SECURITY2_ROOT_LEN 2468 #define MPI3_SECURITY2_ROOT_LEN 4 2469 #endif /* MPI3_SECURITY2_ROOT_LEN */ 2470 2471 typedef struct _MPI3_SECURITY2_TRUSTED_ROOT 2472 { 2473 U8 Level; /* 0x00 */ 2474 U8 HashAlgorithm; /* 0x01 */ 2475 U16 TrustedRootFlags; /* 0x02 */ 2476 U32 Reserved04[3]; /* 0x04 */ 2477 U8 Root[MPI3_SECURITY2_ROOT_LEN]; /* 0x10 */ /* variable length */ 2478 } MPI3_SECURITY2_TRUSTED_ROOT, MPI3_POINTER PTR_MPI3_SECURITY2_TRUSTED_ROOT, 2479 Mpi3Security2TrustedRoot_t, MPI3_POINTER pMpi3Security2TrustedRoot_t; 2480 2481 /**** Defines for the TrustedRootFlags field ****/ 2482 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_ROOTFORM_MASK (0xF000) 2483 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_ROOTFORM_SHIFT (12) 2484 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_ROOTFORM_DIGEST (0x0000) 2485 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_ROOTFORM_DERCERT (0x1000) 2486 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_MASK (0x0006) 2487 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_SHIFT (1) 2488 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_HA_FIELD (0x0000) 2489 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_AKI (0x0002) 2490 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_USERPROVISIONED_YES (0x0001) 2491 2492 typedef struct _MPI3_SECURITY_PAGE2 2493 { 2494 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2495 U32 Reserved08[2]; /* 0x08 */ 2496 MPI3_SECURITY_MAC Mac; /* 0x10 */ 2497 MPI3_SECURITY_NONCE Nonce; /* 0x50 */ 2498 U32 Reserved90[3]; /* 0x90 */ 2499 U8 NumRoots; /* 0x9C */ 2500 U8 Reserved9D; /* 0x9D */ 2501 U16 RootElementSize; /* 0x9E */ 2502 MPI3_SECURITY2_TRUSTED_ROOT TrustedRoot[MPI3_SECURITY2_TRUSTED_ROOT_MAX]; /* 0xA0 */ /* variable length */ 2503 } MPI3_SECURITY_PAGE2, MPI3_POINTER PTR_MPI3_SECURITY_PAGE2, 2504 Mpi3SecurityPage2_t, MPI3_POINTER pMpi3SecurityPage2_t; 2505 2506 /**** Defines for the PageVersion field ****/ 2507 #define MPI3_SECURITY2_PAGEVERSION (0x00) 2508 2509 2510 /***************************************************************************** 2511 * SAS IO Unit Configuration Pages * 2512 ****************************************************************************/ 2513 2514 /***************************************************************************** 2515 * SAS IO Unit Page 0 * 2516 ****************************************************************************/ 2517 typedef struct _MPI3_SAS_IO_UNIT0_PHY_DATA 2518 { 2519 U8 IOUnitPort; /* 0x00 */ 2520 U8 PortFlags; /* 0x01 */ 2521 U8 PhyFlags; /* 0x02 */ 2522 U8 NegotiatedLinkRate; /* 0x03 */ 2523 U16 ControllerPhyDeviceInfo; /* 0x04 */ 2524 U16 Reserved06; /* 0x06 */ 2525 U16 AttachedDevHandle; /* 0x08 */ 2526 U16 ControllerDevHandle; /* 0x0A */ 2527 U32 DiscoveryStatus; /* 0x0C */ 2528 U32 Reserved10; /* 0x10 */ 2529 } MPI3_SAS_IO_UNIT0_PHY_DATA, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT0_PHY_DATA, 2530 Mpi3SasIOUnit0PhyData_t, MPI3_POINTER pMpi3SasIOUnit0PhyData_t; 2531 2532 #ifndef MPI3_SAS_IO_UNIT0_PHY_MAX 2533 #define MPI3_SAS_IO_UNIT0_PHY_MAX (1) 2534 #endif /* MPI3_SAS_IO_UNIT0_PHY_MAX */ 2535 2536 typedef struct _MPI3_SAS_IO_UNIT_PAGE0 2537 { 2538 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2539 U32 Reserved08; /* 0x08 */ 2540 U8 NumPhys; /* 0x0C */ 2541 U8 InitStatus; /* 0x0D */ 2542 U16 Reserved0E; /* 0x0E */ 2543 MPI3_SAS_IO_UNIT0_PHY_DATA PhyData[MPI3_SAS_IO_UNIT0_PHY_MAX]; /* 0x10 */ 2544 } MPI3_SAS_IO_UNIT_PAGE0, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT_PAGE0, 2545 Mpi3SasIOUnitPage0_t, MPI3_POINTER pMpi3SasIOUnitPage0_t; 2546 2547 /**** Defines for the PageVersion field ****/ 2548 #define MPI3_SASIOUNIT0_PAGEVERSION (0x00) 2549 2550 /**** Defines for the InitStatus field ****/ 2551 #define MPI3_SASIOUNIT0_INITSTATUS_NO_ERRORS (0x00) 2552 #define MPI3_SASIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION (0x01) 2553 #define MPI3_SASIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED (0x02) 2554 #define MPI3_SASIOUNIT0_INITSTATUS_BAD_NUM_PHYS (0x04) 2555 #define MPI3_SASIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG (0x05) 2556 #define MPI3_SASIOUNIT0_INITSTATUS_HOST_PHYS_ENABLED (0x06) 2557 #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MIN (0xF0) 2558 #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MAX (0xFF) 2559 2560 /**** Defines for the PortFlags field ****/ 2561 #define MPI3_SASIOUNIT0_PORTFLAGS_DISC_IN_PROGRESS (0x08) 2562 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_MASK (0x03) 2563 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_IOUNIT1 (0x00) 2564 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_DYNAMIC (0x01) 2565 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_BACKPLANE (0x02) 2566 2567 /**** Defines for the PhyFlags field ****/ 2568 #define MPI3_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2569 #define MPI3_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2570 #define MPI3_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 2571 #define MPI3_SASIOUNIT0_PHYFLAGS_VIRTUAL_PHY (0x02) 2572 #define MPI3_SASIOUNIT0_PHYFLAGS_HOST_PHY (0x01) 2573 2574 /**** Use MPI3_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field ****/ 2575 2576 /**** Use MPI3_SAS_DEVICE_INFO_ defines (see mpi30_sas.h) for the ControllerPhyDeviceInfo field ****/ 2577 2578 /**** Use MPI3_SAS_DISC_STATUS_ defines (see mpi30_ioc.h) for the DiscoveryStatus field ****/ 2579 2580 /***************************************************************************** 2581 * SAS IO Unit Page 1 * 2582 ****************************************************************************/ 2583 typedef struct _MPI3_SAS_IO_UNIT1_PHY_DATA 2584 { 2585 U8 IOUnitPort; /* 0x00 */ 2586 U8 PortFlags; /* 0x01 */ 2587 U8 PhyFlags; /* 0x02 */ 2588 U8 MaxMinLinkRate; /* 0x03 */ 2589 U16 ControllerPhyDeviceInfo; /* 0x04 */ 2590 U16 MaxTargetPortConnectTime; /* 0x06 */ 2591 U32 Reserved08; /* 0x08 */ 2592 } MPI3_SAS_IO_UNIT1_PHY_DATA, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT1_PHY_DATA, 2593 Mpi3SasIOUnit1PhyData_t, MPI3_POINTER pMpi3SasIOUnit1PhyData_t; 2594 2595 #ifndef MPI3_SAS_IO_UNIT1_PHY_MAX 2596 #define MPI3_SAS_IO_UNIT1_PHY_MAX (1) 2597 #endif /* MPI3_SAS_IO_UNIT1_PHY_MAX */ 2598 2599 typedef struct _MPI3_SAS_IO_UNIT_PAGE1 2600 { 2601 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2602 U16 ControlFlags; /* 0x08 */ 2603 U16 SASNarrowMaxQueueDepth; /* 0x0A */ 2604 U16 AdditionalControlFlags; /* 0x0C */ 2605 U16 SASWideMaxQueueDepth; /* 0x0E */ 2606 U8 NumPhys; /* 0x10 */ 2607 U8 SATAMaxQDepth; /* 0x11 */ 2608 U16 Reserved12; /* 0x12 */ 2609 MPI3_SAS_IO_UNIT1_PHY_DATA PhyData[MPI3_SAS_IO_UNIT1_PHY_MAX]; /* 0x14 */ 2610 } MPI3_SAS_IO_UNIT_PAGE1, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT_PAGE1, 2611 Mpi3SasIOUnitPage1_t, MPI3_POINTER pMpi3SasIOUnitPage1_t; 2612 2613 /**** Defines for the PageVersion field ****/ 2614 #define MPI3_SASIOUNIT1_PAGEVERSION (0x00) 2615 2616 /**** Defines for the ControlFlags field ****/ 2617 #define MPI3_SASIOUNIT1_CONTROL_CONTROLLER_DEVICE_SELF_TEST (0x8000) 2618 #define MPI3_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2619 #define MPI3_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2620 #define MPI3_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2621 #define MPI3_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2622 #define MPI3_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2623 #define MPI3_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 2624 #define MPI3_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2625 #define MPI3_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2626 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_MASK (0x0001) 2627 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_DEVICE_NAME (0x0000) 2628 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_SAS_ADDRESS (0x0001) 2629 2630 /**** Defines for the AdditionalControlFlags field ****/ 2631 #define MPI3_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 2632 #define MPI3_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2633 #define MPI3_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2634 #define MPI3_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 2635 #define MPI3_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2636 #define MPI3_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2637 #define MPI3_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2638 #define MPI3_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2639 #define MPI3_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2640 2641 /**** Defines for the PortFlags field ****/ 2642 #define MPI3_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2643 2644 /**** Defines for the PhyFlags field ****/ 2645 #define MPI3_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2646 #define MPI3_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2647 #define MPI3_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2648 2649 /**** Defines for the MaxMinLinkRate field ****/ 2650 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_MASK (0xF0) 2651 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_SHIFT (4) 2652 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_6_0 (0xA0) 2653 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_12_0 (0xB0) 2654 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_22_5 (0xC0) 2655 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_MASK (0x0F) 2656 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_6_0 (0x0A) 2657 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_12_0 (0x0B) 2658 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_22_5 (0x0C) 2659 2660 /**** Use MPI3_SAS_DEVICE_INFO_ defines (see mpi30_sas.h) for the ControllerPhyDeviceInfo field ****/ 2661 2662 /***************************************************************************** 2663 * SAS IO Unit Page 2 * 2664 ****************************************************************************/ 2665 typedef struct _MPI3_SAS_IO_UNIT2_PHY_PM_SETTINGS 2666 { 2667 U8 ControlFlags; /* 0x00 */ 2668 U8 Reserved01; /* 0x01 */ 2669 U16 InactivityTimerExponent; /* 0x02 */ 2670 U8 SATAPartialTimeout; /* 0x04 */ 2671 U8 Reserved05; /* 0x05 */ 2672 U8 SATASlumberTimeout; /* 0x06 */ 2673 U8 Reserved07; /* 0x07 */ 2674 U8 SASPartialTimeout; /* 0x08 */ 2675 U8 Reserved09; /* 0x09 */ 2676 U8 SASSlumberTimeout; /* 0x0A */ 2677 U8 Reserved0B; /* 0x0B */ 2678 } MPI3_SAS_IO_UNIT2_PHY_PM_SETTINGS, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT2_PHY_PM_SETTINGS, 2679 Mpi3SasIOUnit2PhyPmSettings_t, MPI3_POINTER pMpi3SasIOUnit2PhyPmSettings_t; 2680 2681 #ifndef MPI3_SAS_IO_UNIT2_PHY_MAX 2682 #define MPI3_SAS_IO_UNIT2_PHY_MAX (1) 2683 #endif /* MPI3_SAS_IO_UNIT2_PHY_MAX */ 2684 2685 typedef struct _MPI3_SAS_IO_UNIT_PAGE2 2686 { 2687 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2688 U8 NumPhys; /* 0x08 */ 2689 U8 Reserved09[3]; /* 0x09 */ 2690 U32 Reserved0C; /* 0x0C */ 2691 MPI3_SAS_IO_UNIT2_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI3_SAS_IO_UNIT2_PHY_MAX]; /* 0x10 */ 2692 } MPI3_SAS_IO_UNIT_PAGE2, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT_PAGE2, 2693 Mpi3SasIOUnitPage2_t, MPI3_POINTER pMpi3SasIOUnitPage2_t; 2694 2695 /**** Defines for the PageVersion field ****/ 2696 #define MPI3_SASIOUNIT2_PAGEVERSION (0x00) 2697 2698 /**** Defines for the ControlFlags field ****/ 2699 #define MPI3_SASIOUNIT2_CONTROL_SAS_SLUMBER_ENABLE (0x08) 2700 #define MPI3_SASIOUNIT2_CONTROL_SAS_PARTIAL_ENABLE (0x04) 2701 #define MPI3_SASIOUNIT2_CONTROL_SATA_SLUMBER_ENABLE (0x02) 2702 #define MPI3_SASIOUNIT2_CONTROL_SATA_PARTIAL_ENABLE (0x01) 2703 2704 /**** Defines for the InactivityTimerExponent field ****/ 2705 #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_MASK (0x7000) 2706 #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_SHIFT (12) 2707 #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_MASK (0x0700) 2708 #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_SHIFT (8) 2709 #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_MASK (0x0070) 2710 #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_SHIFT (4) 2711 #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_MASK (0x0007) 2712 #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_SHIFT (0) 2713 2714 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_SECONDS (7) 2715 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_SECOND (6) 2716 #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MILLISECONDS (5) 2717 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MILLISECONDS (4) 2718 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MILLISECOND (3) 2719 #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MICROSECONDS (2) 2720 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MICROSECONDS (1) 2721 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MICROSECOND (0) 2722 2723 /***************************************************************************** 2724 * SAS IO Unit Page 3 * 2725 ****************************************************************************/ 2726 typedef struct _MPI3_SAS_IO_UNIT_PAGE3 2727 { 2728 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2729 U32 Reserved08; /* 0x08 */ 2730 U32 PowerManagementCapabilities; /* 0x0C */ 2731 } MPI3_SAS_IO_UNIT_PAGE3, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT_PAGE3, 2732 Mpi3SasIOUnitPage3_t, MPI3_POINTER pMpi3SasIOUnitPage3_t; 2733 2734 /**** Defines for the PageVersion field ****/ 2735 #define MPI3_SASIOUNIT3_PAGEVERSION (0x00) 2736 2737 /**** Defines for the PowerManagementCapabilities field ****/ 2738 #define MPI3_SASIOUNIT3_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 2739 #define MPI3_SASIOUNIT3_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 2740 #define MPI3_SASIOUNIT3_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 2741 #define MPI3_SASIOUNIT3_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 2742 #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 2743 #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 2744 #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 2745 #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 2746 2747 2748 /***************************************************************************** 2749 * SAS Expander Configuration Pages * 2750 ****************************************************************************/ 2751 2752 /***************************************************************************** 2753 * SAS Expander Page 0 * 2754 ****************************************************************************/ 2755 typedef struct _MPI3_SAS_EXPANDER_PAGE0 2756 { 2757 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2758 U8 IOUnitPort; /* 0x08 */ 2759 U8 ReportGenLength; /* 0x09 */ 2760 U16 EnclosureHandle; /* 0x0A */ 2761 U32 Reserved0C; /* 0x0C */ 2762 U64 SASAddress; /* 0x10 */ 2763 U32 DiscoveryStatus; /* 0x18 */ 2764 U16 DevHandle; /* 0x1C */ 2765 U16 ParentDevHandle; /* 0x1E */ 2766 U16 ExpanderChangeCount; /* 0x20 */ 2767 U16 ExpanderRouteIndexes; /* 0x22 */ 2768 U8 NumPhys; /* 0x24 */ 2769 U8 SASLevel; /* 0x25 */ 2770 U16 Flags; /* 0x26 */ 2771 U16 STPBusInactivityTimeLimit; /* 0x28 */ 2772 U16 STPMaxConnectTimeLimit; /* 0x2A */ 2773 U16 STP_SMP_NexusLossTime; /* 0x2C */ 2774 U16 MaxNumRoutedSASAddresses; /* 0x2E */ 2775 U64 ActiveZoneManagerSASAddress; /* 0x30 */ 2776 U16 ZoneLockInactivityLimit; /* 0x38 */ 2777 U16 Reserved3A; /* 0x3A */ 2778 U8 TimeToReducedFunc; /* 0x3C */ 2779 U8 InitialTimeToReducedFunc; /* 0x3D */ 2780 U8 MaxReducedFuncTime; /* 0x3E */ 2781 U8 ExpStatus; /* 0x3F */ 2782 } MPI3_SAS_EXPANDER_PAGE0, MPI3_POINTER PTR_MPI3_SAS_EXPANDER_PAGE0, 2783 Mpi3SasExpanderPage0_t, MPI3_POINTER pMpi3SasExpanderPage0_t; 2784 2785 /**** Defines for the PageVersion field ****/ 2786 #define MPI3_SASEXPANDER0_PAGEVERSION (0x00) 2787 2788 /**** Use MPI3_SAS_DISC_STATUS_ defines (see mpi30_ioc.h) for the DiscoveryStatus field ****/ 2789 2790 /**** Defines for the Flags field ****/ 2791 #define MPI3_SASEXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2792 #define MPI3_SASEXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2793 #define MPI3_SASEXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2794 #define MPI3_SASEXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2795 #define MPI3_SASEXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2796 #define MPI3_SASEXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2797 #define MPI3_SASEXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2798 #define MPI3_SASEXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2799 #define MPI3_SASEXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2800 #define MPI3_SASEXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2801 #define MPI3_SASEXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2802 2803 /**** Defines for the ExpStatus field ****/ 2804 #define MPI3_SASEXPANDER0_ES_NOT_RESPONDING (0x02) 2805 #define MPI3_SASEXPANDER0_ES_RESPONDING (0x03) 2806 #define MPI3_SASEXPANDER0_ES_DELAY_NOT_RESPONDING (0x04) 2807 2808 /***************************************************************************** 2809 * SAS Expander Page 1 * 2810 ****************************************************************************/ 2811 typedef struct _MPI3_SAS_EXPANDER_PAGE1 2812 { 2813 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2814 U8 IOUnitPort; /* 0x08 */ 2815 U8 Reserved09[3]; /* 0x09 */ 2816 U8 NumPhys; /* 0x0C */ 2817 U8 Phy; /* 0x0D */ 2818 U16 NumTableEntriesProgrammed; /* 0x0E */ 2819 U8 ProgrammedLinkRate; /* 0x10 */ 2820 U8 HwLinkRate; /* 0x11 */ 2821 U16 AttachedDevHandle; /* 0x12 */ 2822 U32 PhyInfo; /* 0x14 */ 2823 U16 AttachedDeviceInfo; /* 0x18 */ 2824 U16 Reserved1A; /* 0x1A */ 2825 U16 ExpanderDevHandle; /* 0x1C */ 2826 U8 ChangeCount; /* 0x1E */ 2827 U8 NegotiatedLinkRate; /* 0x1F */ 2828 U8 PhyIdentifier; /* 0x20 */ 2829 U8 AttachedPhyIdentifier; /* 0x21 */ 2830 U8 Reserved22; /* 0x22 */ 2831 U8 DiscoveryInfo; /* 0x23 */ 2832 U32 AttachedPhyInfo; /* 0x24 */ 2833 U8 ZoneGroup; /* 0x28 */ 2834 U8 SelfConfigStatus; /* 0x29 */ 2835 U16 Reserved2A; /* 0x2A */ 2836 U16 Slot; /* 0x2C */ 2837 U16 SlotIndex; /* 0x2E */ 2838 } MPI3_SAS_EXPANDER_PAGE1, MPI3_POINTER PTR_MPI3_SAS_EXPANDER_PAGE1, 2839 Mpi3SasExpanderPage1_t, MPI3_POINTER pMpi3SasExpanderPage1_t; 2840 2841 /**** Defines for the PageVersion field ****/ 2842 #define MPI3_SASEXPANDER1_PAGEVERSION (0x00) 2843 2844 /**** Defines for the ProgrammedLinkRate field - use MPI3_SAS_PRATE_ defines ****/ 2845 2846 /**** Defines for the HwLinkRate field - use MPI3_SAS_HWRATE_ defines ****/ 2847 2848 /**** Defines for the PhyInfo field - use MPI3_SAS_PHYINFO_ defines ****/ 2849 2850 /**** Defines for the AttachedDeviceInfo field - use MPI3_SAS_DEVICE_INFO_ defines ****/ 2851 2852 /**** Defines for the NegotiatedLinkRate field - use use MPI3_SAS_NEG_LINK_RATE_ defines ****/ 2853 2854 /**** Defines for the DiscoveryInfo field ****/ 2855 #define MPI3_SASEXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2856 #define MPI3_SASEXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2857 #define MPI3_SASEXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2858 2859 /**** Defines for the AttachedPhyInfo field - use MPI3_SAS_APHYINFO_ defines ****/ 2860 2861 /**** Defines for the Slot field - use MPI3_SLOT_ defines ****/ 2862 2863 /**** Defines for the SlotIndex field - use MPI3_SLOT_INDEX_ ****/ 2864 2865 2866 /***************************************************************************** 2867 * SAS Expander Page 2 * 2868 ****************************************************************************/ 2869 #ifndef MPI3_SASEXPANDER2_MAX_NUM_PHYS 2870 #define MPI3_SASEXPANDER2_MAX_NUM_PHYS (1) 2871 #endif /* MPI3_SASEXPANDER2_MAX_NUM_PHYS */ 2872 2873 typedef struct _MPI3_SASEXPANDER2_PHY_ELEMENT 2874 { 2875 U8 LinkChangeCount; /* 0x00 */ 2876 U8 Reserved01; /* 0x01 */ 2877 U16 RateChangeCount; /* 0x02 */ 2878 U32 Reserved04; /* 0x04 */ 2879 } MPI3_SASEXPANDER2_PHY_ELEMENT, MPI3_POINTER PTR_MPI3_SASEXPANDER2_PHY_ELEMENT, 2880 Mpi3SasExpander2PhyElement_t, MPI3_POINTER pMpi3SasExpander2PhyElement_t; 2881 2882 typedef struct _MPI3_SAS_EXPANDER_PAGE2 2883 { 2884 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2885 U8 NumPhys; /* 0x08 */ 2886 U8 Reserved09; /* 0x09 */ 2887 U16 DevHandle; /* 0x0A */ 2888 U32 Reserved0C; /* 0x0C */ 2889 MPI3_SASEXPANDER2_PHY_ELEMENT Phy[MPI3_SASEXPANDER2_MAX_NUM_PHYS]; /* 0x10 */ /* variable length */ 2890 2891 } MPI3_SAS_EXPANDER_PAGE2, MPI3_POINTER PTR_MPI3_SAS_EXPANDER_PAGE2, 2892 Mpi3SasExpanderPage2_t, MPI3_POINTER pMpi3SasExpanderPage2_t; 2893 2894 /**** Defines for the PageVersion field ****/ 2895 #define MPI3_SASEXPANDER2_PAGEVERSION (0x00) 2896 2897 2898 /***************************************************************************** 2899 * SAS Port Configuration Pages * 2900 ****************************************************************************/ 2901 2902 /***************************************************************************** 2903 * SAS Port Page 0 * 2904 ****************************************************************************/ 2905 typedef struct _MPI3_SAS_PORT_PAGE0 2906 { 2907 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2908 U8 PortNumber; /* 0x08 */ 2909 U8 Reserved09; /* 0x09 */ 2910 U8 PortWidth; /* 0x0A */ 2911 U8 Reserved0B; /* 0x0B */ 2912 U8 ZoneGroup; /* 0x0C */ 2913 U8 Reserved0D[3]; /* 0x0D */ 2914 U64 SASAddress; /* 0x10 */ 2915 U16 DeviceInfo; /* 0x18 */ 2916 U16 Reserved1A; /* 0x1A */ 2917 U32 Reserved1C; /* 0x1C */ 2918 } MPI3_SAS_PORT_PAGE0, MPI3_POINTER PTR_MPI3_SAS_PORT_PAGE0, 2919 Mpi3SasPortPage0_t, MPI3_POINTER pMpi3SasPortPage0_t; 2920 2921 /**** Defines for the PageVersion field ****/ 2922 #define MPI3_SASPORT0_PAGEVERSION (0x00) 2923 2924 /**** Defines for the DeviceInfo field - use MPI3_SAS_DEVICE_INFO_ defines ****/ 2925 2926 /***************************************************************************** 2927 * SAS PHY Configuration Pages * 2928 ****************************************************************************/ 2929 2930 /***************************************************************************** 2931 * SAS PHY Page 0 * 2932 ****************************************************************************/ 2933 typedef struct _MPI3_SAS_PHY_PAGE0 2934 { 2935 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2936 U16 OwnerDevHandle; /* 0x08 */ 2937 U16 Reserved0A; /* 0x0A */ 2938 U16 AttachedDevHandle; /* 0x0C */ 2939 U8 AttachedPhyIdentifier; /* 0x0E */ 2940 U8 Reserved0F; /* 0x0F */ 2941 U32 AttachedPhyInfo; /* 0x10 */ 2942 U8 ProgrammedLinkRate; /* 0x14 */ 2943 U8 HwLinkRate; /* 0x15 */ 2944 U8 ChangeCount; /* 0x16 */ 2945 U8 Flags; /* 0x17 */ 2946 U32 PhyInfo; /* 0x18 */ 2947 U8 NegotiatedLinkRate; /* 0x1C */ 2948 U8 Reserved1D[3]; /* 0x1D */ 2949 U16 Slot; /* 0x20 */ 2950 U16 SlotIndex; /* 0x22 */ 2951 } MPI3_SAS_PHY_PAGE0, MPI3_POINTER PTR_MPI3_SAS_PHY_PAGE0, 2952 Mpi3SasPhyPage0_t, MPI3_POINTER pMpi3SasPhyPage0_t; 2953 2954 /**** Defines for the PageVersion field ****/ 2955 #define MPI3_SASPHY0_PAGEVERSION (0x00) 2956 2957 /**** Defines for the AttachedPhyInfo field - use MPI3_SAS_APHYINFO_ defines ****/ 2958 2959 /**** Defines for the ProgrammedLinkRate field - use MPI3_SAS_PRATE_ defines ****/ 2960 2961 /**** Defines for the HwLinkRate field - use MPI3_SAS_HWRATE_ defines ****/ 2962 2963 /**** Defines for the Flags field ****/ 2964 #define MPI3_SASPHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2965 2966 /**** Defines for the PhyInfo field - use MPI3_SAS_PHYINFO_ defines ****/ 2967 2968 /**** Defines for the NegotiatedLinkRate field - use MPI3_SAS_NEG_LINK_RATE_ defines ****/ 2969 2970 /**** Defines for the Slot field - use MPI3_SLOT_ defines ****/ 2971 2972 /**** Defines for the SlotIndex field - use MPI3_SLOT_INDEX_ ****/ 2973 2974 /***************************************************************************** 2975 * SAS PHY Page 1 * 2976 ****************************************************************************/ 2977 typedef struct _MPI3_SAS_PHY_PAGE1 2978 { 2979 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2980 U32 Reserved08; /* 0x08 */ 2981 U32 InvalidDwordCount; /* 0x0C */ 2982 U32 RunningDisparityErrorCount; /* 0x10 */ 2983 U32 LossDwordSynchCount; /* 0x14 */ 2984 U32 PhyResetProblemCount; /* 0x18 */ 2985 } MPI3_SAS_PHY_PAGE1, MPI3_POINTER PTR_MPI3_SAS_PHY_PAGE1, 2986 Mpi3SasPhyPage1_t, MPI3_POINTER pMpi3SasPhyPage1_t; 2987 2988 /**** Defines for the PageVersion field ****/ 2989 #define MPI3_SASPHY1_PAGEVERSION (0x00) 2990 2991 /***************************************************************************** 2992 * SAS PHY Page 2 * 2993 ****************************************************************************/ 2994 typedef struct _MPI3_SAS_PHY2_PHY_EVENT 2995 { 2996 U8 PhyEventCode; /* 0x00 */ 2997 U8 Reserved01[3]; /* 0x01 */ 2998 U32 PhyEventInfo; /* 0x04 */ 2999 } MPI3_SAS_PHY2_PHY_EVENT, MPI3_POINTER PTR_MPI3_SAS_PHY2_PHY_EVENT, 3000 Mpi3SasPhy2PhyEvent_t, MPI3_POINTER pMpi3SasPhy2PhyEvent_t; 3001 3002 /**** Defines for the PhyEventCode field - use MPI3_SASPHY3_EVENT_CODE_ defines */ 3003 3004 #ifndef MPI3_SAS_PHY2_PHY_EVENT_MAX 3005 #define MPI3_SAS_PHY2_PHY_EVENT_MAX (1) 3006 #endif /* MPI3_SAS_PHY2_PHY_EVENT_MAX */ 3007 3008 typedef struct _MPI3_SAS_PHY_PAGE2 3009 { 3010 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3011 U32 Reserved08; /* 0x08 */ 3012 U8 NumPhyEvents; /* 0x0C */ 3013 U8 Reserved0D[3]; /* 0x0D */ 3014 MPI3_SAS_PHY2_PHY_EVENT PhyEvent[MPI3_SAS_PHY2_PHY_EVENT_MAX]; /* 0x10 */ 3015 } MPI3_SAS_PHY_PAGE2, MPI3_POINTER PTR_MPI3_SAS_PHY_PAGE2, 3016 Mpi3SasPhyPage2_t, MPI3_POINTER pMpi3SasPhyPage2_t; 3017 3018 /**** Defines for the PageVersion field ****/ 3019 #define MPI3_SASPHY2_PAGEVERSION (0x00) 3020 3021 /***************************************************************************** 3022 * SAS PHY Page 3 * 3023 ****************************************************************************/ 3024 typedef struct _MPI3_SAS_PHY3_PHY_EVENT_CONFIG 3025 { 3026 U8 PhyEventCode; /* 0x00 */ 3027 U8 Reserved01[3]; /* 0x01 */ 3028 U8 CounterType; /* 0x04 */ 3029 U8 ThresholdWindow; /* 0x05 */ 3030 U8 TimeUnits; /* 0x06 */ 3031 U8 Reserved07; /* 0x07 */ 3032 U32 EventThreshold; /* 0x08 */ 3033 U16 ThresholdFlags; /* 0x0C */ 3034 U16 Reserved0E; /* 0x0E */ 3035 } MPI3_SAS_PHY3_PHY_EVENT_CONFIG, MPI3_POINTER PTR_MPI3_SAS_PHY3_PHY_EVENT_CONFIG, 3036 Mpi3SasPhy3PhyEventConfig_t, MPI3_POINTER pMpi3SasPhy3PhyEventConfig_t; 3037 3038 /**** Defines for the PhyEventCode field ****/ 3039 #define MPI3_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 3040 #define MPI3_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 3041 #define MPI3_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 3042 #define MPI3_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 3043 #define MPI3_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 3044 #define MPI3_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 3045 #define MPI3_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 3046 #define MPI3_SASPHY3_EVENT_CODE_INV_SPL_PACKETS (0x07) 3047 #define MPI3_SASPHY3_EVENT_CODE_LOSS_SPL_PACKET_SYNC (0x08) 3048 #define MPI3_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 3049 #define MPI3_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 3050 #define MPI3_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 3051 #define MPI3_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 3052 #define MPI3_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 3053 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 3054 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 3055 #define MPI3_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 3056 #define MPI3_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 3057 #define MPI3_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 3058 #define MPI3_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 3059 #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 3060 #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 3061 #define MPI3_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 3062 #define MPI3_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 3063 #define MPI3_SASPHY3_EVENT_CODE_PERSIST_CONN (0x2F) 3064 #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 3065 #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 3066 #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 3067 #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 3068 #define MPI3_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 3069 #define MPI3_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 3070 #define MPI3_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 3071 #define MPI3_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 3072 #define MPI3_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 3073 #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 3074 #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 3075 #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 3076 #define MPI3_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 3077 #define MPI3_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 3078 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 3079 #define MPI3_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3) 3080 #define MPI3_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4) 3081 #define MPI3_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5) 3082 #define MPI3_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6) 3083 #define MPI3_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7) 3084 #define MPI3_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8) 3085 #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9) 3086 #define MPI3_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA) 3087 #define MPI3_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB) 3088 #define MPI3_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC) 3089 3090 /**** Defines for the CounterType field ****/ 3091 #define MPI3_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 3092 #define MPI3_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 3093 #define MPI3_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 3094 3095 /**** Defines for the TimeUnits field ****/ 3096 #define MPI3_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 3097 #define MPI3_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 3098 #define MPI3_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 3099 #define MPI3_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 3100 3101 /**** Defines for the ThresholdFlags field ****/ 3102 #define MPI3_SASPHY3_TFLAGS_PHY_RESET (0x0002) 3103 #define MPI3_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 3104 3105 #ifndef MPI3_SAS_PHY3_PHY_EVENT_MAX 3106 #define MPI3_SAS_PHY3_PHY_EVENT_MAX (1) 3107 #endif /* MPI3_SAS_PHY3_PHY_EVENT_MAX */ 3108 3109 typedef struct _MPI3_SAS_PHY_PAGE3 3110 { 3111 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3112 U32 Reserved08; /* 0x08 */ 3113 U8 NumPhyEvents; /* 0x0C */ 3114 U8 Reserved0D[3]; /* 0x0D */ 3115 MPI3_SAS_PHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI3_SAS_PHY3_PHY_EVENT_MAX]; /* 0x10 */ 3116 } MPI3_SAS_PHY_PAGE3, MPI3_POINTER PTR_MPI3_SAS_PHY_PAGE3, 3117 Mpi3SasPhyPage3_t, MPI3_POINTER pMpi3SasPhyPage3_t; 3118 3119 /**** Defines for the PageVersion field ****/ 3120 #define MPI3_SASPHY3_PAGEVERSION (0x00) 3121 3122 /***************************************************************************** 3123 * SAS PHY Page 4 * 3124 ****************************************************************************/ 3125 typedef struct _MPI3_SAS_PHY_PAGE4 3126 { 3127 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3128 U8 Reserved08[3]; /* 0x08 */ 3129 U8 Flags; /* 0x0B */ 3130 U8 InitialFrame[28]; /* 0x0C */ 3131 } MPI3_SAS_PHY_PAGE4, MPI3_POINTER PTR_MPI3_SAS_PHY_PAGE4, 3132 Mpi3SasPhyPage4_t, MPI3_POINTER pMpi3SasPhyPage4_t; 3133 3134 /**** Defines for the PageVersion field ****/ 3135 #define MPI3_SASPHY4_PAGEVERSION (0x00) 3136 3137 /**** Defines for the Flags field ****/ 3138 #define MPI3_SASPHY4_FLAGS_FRAME_VALID (0x02) 3139 #define MPI3_SASPHY4_FLAGS_SATA_FRAME (0x01) 3140 3141 3142 /***************************************************************************** 3143 * Common definitions used by PCIe Configuration Pages * 3144 ****************************************************************************/ 3145 3146 /**** Defines for NegotiatedLinkRates ****/ 3147 #define MPI3_PCIE_LINK_RETIMERS_MASK (0x30) 3148 #define MPI3_PCIE_LINK_RETIMERS_SHIFT (4) 3149 #define MPI3_PCIE_NEG_LINK_RATE_MASK (0x0F) 3150 #define MPI3_PCIE_NEG_LINK_RATE_UNKNOWN (0x00) 3151 #define MPI3_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01) 3152 #define MPI3_PCIE_NEG_LINK_RATE_2_5 (0x02) 3153 #define MPI3_PCIE_NEG_LINK_RATE_5_0 (0x03) 3154 #define MPI3_PCIE_NEG_LINK_RATE_8_0 (0x04) 3155 #define MPI3_PCIE_NEG_LINK_RATE_16_0 (0x05) 3156 #define MPI3_PCIE_NEG_LINK_RATE_32_0 (0x06) 3157 3158 /**** Defines for Enabled ASPM States ****/ 3159 #define MPI3_PCIE_ASPM_ENABLE_NONE (0x0) 3160 #define MPI3_PCIE_ASPM_ENABLE_L0s (0x1) 3161 #define MPI3_PCIE_ASPM_ENABLE_L1 (0x2) 3162 #define MPI3_PCIE_ASPM_ENABLE_L0s_L1 (0x3) 3163 3164 /**** Defines for Enabled ASPM States ****/ 3165 #define MPI3_PCIE_ASPM_SUPPORT_NONE (0x0) 3166 #define MPI3_PCIE_ASPM_SUPPORT_L0s (0x1) 3167 #define MPI3_PCIE_ASPM_SUPPORT_L1 (0x2) 3168 #define MPI3_PCIE_ASPM_SUPPORT_L0s_L1 (0x3) 3169 3170 /***************************************************************************** 3171 * PCIe IO Unit Configuration Pages * 3172 ****************************************************************************/ 3173 3174 /***************************************************************************** 3175 * PCIe IO Unit Page 0 * 3176 ****************************************************************************/ 3177 typedef struct _MPI3_PCIE_IO_UNIT0_PHY_DATA 3178 { 3179 U8 Link; /* 0x00 */ 3180 U8 LinkFlags; /* 0x01 */ 3181 U8 PhyFlags; /* 0x02 */ 3182 U8 NegotiatedLinkRate; /* 0x03 */ 3183 U16 AttachedDevHandle; /* 0x04 */ 3184 U16 ControllerDevHandle; /* 0x06 */ 3185 U32 EnumerationStatus; /* 0x08 */ 3186 U8 IOUnitPort; /* 0x0C */ 3187 U8 Reserved0D[3]; /* 0x0D */ 3188 } MPI3_PCIE_IO_UNIT0_PHY_DATA, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT0_PHY_DATA, 3189 Mpi3PcieIOUnit0PhyData_t, MPI3_POINTER pMpi3PcieIOUnit0PhyData_t; 3190 3191 /**** Defines for the LinkFlags field ****/ 3192 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_MASK (0x10) 3193 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_IOUNIT1 (0x00) 3194 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_BKPLANE (0x10) 3195 #define MPI3_PCIEIOUNIT0_LINKFLAGS_ENUM_IN_PROGRESS (0x08) 3196 3197 /**** Defines for the PhyFlags field ****/ 3198 #define MPI3_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 3199 #define MPI3_PCIEIOUNIT0_PHYFLAGS_HOST_PHY (0x01) 3200 3201 /**** Defines for the NegotiatedLinkRate field - use MPI3_PCIE_NEG_LINK_RATE_ defines ****/ 3202 3203 /**** Defines for the EnumerationStatus field ****/ 3204 #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCH_DEPTH_EXCEEDED (0x80000000) 3205 #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000) 3206 #define MPI3_PCIEIOUNIT0_ES_MAX_ENDPOINTS_EXCEEDED (0x20000000) 3207 #define MPI3_PCIEIOUNIT0_ES_INSUFFICIENT_RESOURCES (0x10000000) 3208 3209 #ifndef MPI3_PCIE_IO_UNIT0_PHY_MAX 3210 #define MPI3_PCIE_IO_UNIT0_PHY_MAX (1) 3211 #endif /* MPI3_PCIE_IO_UNIT0_PHY_MAX */ 3212 3213 typedef struct _MPI3_PCIE_IO_UNIT_PAGE0 3214 { 3215 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3216 U32 Reserved08; /* 0x08 */ 3217 U8 NumPhys; /* 0x0C */ 3218 U8 InitStatus; /* 0x0D */ 3219 U8 ASPM; /* 0x0E */ 3220 U8 Reserved0F; /* 0x0F */ 3221 MPI3_PCIE_IO_UNIT0_PHY_DATA PhyData[MPI3_PCIE_IO_UNIT0_PHY_MAX]; /* 0x10 */ 3222 } MPI3_PCIE_IO_UNIT_PAGE0, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT_PAGE0, 3223 Mpi3PcieIOUnitPage0_t, MPI3_POINTER pMpi3PcieIOUnitPage0_t; 3224 3225 /**** Defines for the PageVersion field ****/ 3226 #define MPI3_PCIEIOUNIT0_PAGEVERSION (0x00) 3227 3228 /**** Defines for the InitStatus field ****/ 3229 #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_ERRORS (0x00) 3230 #define MPI3_PCIEIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION (0x01) 3231 #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED (0x02) 3232 #define MPI3_PCIEIOUNIT0_INITSTATUS_RESOURCE_ALLOC_FAILED (0x03) 3233 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_NUM_PHYS (0x04) 3234 #define MPI3_PCIEIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG (0x05) 3235 #define MPI3_PCIEIOUNIT0_INITSTATUS_HOST_PORT_MISMATCH (0x06) 3236 #define MPI3_PCIEIOUNIT0_INITSTATUS_PHYS_NOT_CONSECUTIVE (0x07) 3237 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_CLOCKING_MODE (0x08) 3238 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_START (0xF0) 3239 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_END (0xFF) 3240 3241 /**** Defines for the ASPM field ****/ 3242 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_MASK (0xC0) 3243 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_SHIFT (6) 3244 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_MASK (0x30) 3245 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_SHIFT (4) 3246 /*** use MPI3_PCIE_ASPM_ENABLE_ defines for field values ***/ 3247 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_MASK (0x0C) 3248 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_SHIFT (2) 3249 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_MASK (0x03) 3250 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_SHIFT (0) 3251 /*** use MPI3_PCIE_ASPM_SUPPORT_ defines for field values ***/ 3252 3253 /***************************************************************************** 3254 * PCIe IO Unit Page 1 * 3255 ****************************************************************************/ 3256 typedef struct _MPI3_PCIE_IO_UNIT1_PHY_DATA 3257 { 3258 U8 Link; /* 0x00 */ 3259 U8 LinkFlags; /* 0x01 */ 3260 U8 PhyFlags; /* 0x02 */ 3261 U8 MaxMinLinkRate; /* 0x03 */ 3262 U32 Reserved04; /* 0x04 */ 3263 U32 Reserved08; /* 0x08 */ 3264 } MPI3_PCIE_IO_UNIT1_PHY_DATA, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT1_PHY_DATA, 3265 Mpi3PcieIOUnit1PhyData_t, MPI3_POINTER pMpi3PcieIOUnit1PhyData_t; 3266 3267 /**** Defines for the LinkFlags field ****/ 3268 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_MASK (0x03) 3269 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_DIS_SEPARATE_REFCLK (0x00) 3270 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRIS (0x01) 3271 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRNS (0x02) 3272 3273 /**** Defines for the PhyFlags field ****/ 3274 #define MPI3_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 3275 3276 /**** Defines for the MaxMinLinkRate ****/ 3277 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_MASK (0xF0) 3278 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_SHIFT (4) 3279 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_2_5 (0x20) 3280 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_5_0 (0x30) 3281 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_8_0 (0x40) 3282 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_16_0 (0x50) 3283 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_32_0 (0x60) 3284 3285 #ifndef MPI3_PCIE_IO_UNIT1_PHY_MAX 3286 #define MPI3_PCIE_IO_UNIT1_PHY_MAX (1) 3287 #endif /* MPI3_PCIE_IO_UNIT1_PHY_MAX */ 3288 3289 typedef struct _MPI3_PCIE_IO_UNIT_PAGE1 3290 { 3291 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3292 U32 ControlFlags; /* 0x08 */ 3293 U32 Reserved0C; /* 0x0C */ 3294 U8 NumPhys; /* 0x10 */ 3295 U8 Reserved11; /* 0x11 */ 3296 U8 ASPM; /* 0x12 */ 3297 U8 Reserved13; /* 0x13 */ 3298 MPI3_PCIE_IO_UNIT1_PHY_DATA PhyData[MPI3_PCIE_IO_UNIT1_PHY_MAX]; /* 0x14 */ 3299 } MPI3_PCIE_IO_UNIT_PAGE1, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT_PAGE1, 3300 Mpi3PcieIOUnitPage1_t, MPI3_POINTER pMpi3PcieIOUnitPage1_t; 3301 3302 /**** Defines for the PageVersion field ****/ 3303 #define MPI3_PCIEIOUNIT1_PAGEVERSION (0x00) 3304 3305 /**** Defines for the ControlFlags field ****/ 3306 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_MASK (0xE0000000) 3307 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_NONE (0x00000000) 3308 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_DEASSERT (0x20000000) 3309 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_ASSERT (0x40000000) 3310 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_BACKPLANE_ERROR (0x60000000) 3311 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_MASK (0x1C000000) 3312 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_NONE (0x00000000) 3313 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_ENABLE (0x04000000) 3314 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_DISABLE (0x08000000) 3315 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_BACKPLANE_ERROR (0x0C000000) 3316 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PARTIAL_CAPACITY_ENABLE (0x00000100) 3317 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_OVERRIDE_DISABLE (0x00000080) 3318 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_DISABLE (0x00000040) 3319 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_MASK (0x00000030) 3320 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SHIFT (4) 3321 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_SRNS_DISABLED (0x00000000) 3322 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_ENABLED (0x00000010) 3323 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRNS_ENABLED (0x00000020) 3324 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MASK (0x0000000F) 3325 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_USE_BACKPLANE (0x00000000) 3326 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_2_5 (0x00000002) 3327 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_5_0 (0x00000003) 3328 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_8_0 (0x00000004) 3329 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_16_0 (0x00000005) 3330 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_32_0 (0x00000006) 3331 3332 /**** Defines for the ASPM field ****/ 3333 #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_MASK (0x0C) 3334 #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_SHIFT (2) 3335 #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_MASK (0x03) 3336 #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_SHIFT (0) 3337 /*** use MPI3_PCIE_ASPM_ENABLE_ defines for ASPM field values ***/ 3338 3339 /***************************************************************************** 3340 * PCIe IO Unit Page 2 * 3341 ****************************************************************************/ 3342 typedef struct _MPI3_PCIE_IO_UNIT_PAGE2 3343 { 3344 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3345 U16 NVMeMaxQDx1; /* 0x08 */ 3346 U16 NVMeMaxQDx2; /* 0x0A */ 3347 U8 NVMeAbortTO; /* 0x0C */ 3348 U8 Reserved0D; /* 0x0D */ 3349 U16 NVMeMaxQDx4; /* 0x0E */ 3350 } MPI3_PCIE_IO_UNIT_PAGE2, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT_PAGE2, 3351 Mpi3PcieIOUnitPage2_t, MPI3_POINTER pMpi3PcieIOUnitPage2_t; 3352 3353 /**** Defines for the PageVersion field ****/ 3354 #define MPI3_PCIEIOUNIT2_PAGEVERSION (0x00) 3355 3356 /***************************************************************************** 3357 * PCIe IO Unit Page 3 * 3358 ****************************************************************************/ 3359 3360 /**** Defines for Error Indexes ****/ 3361 #define MPI3_PCIEIOUNIT3_ERROR_RECEIVER_ERROR (0) 3362 #define MPI3_PCIEIOUNIT3_ERROR_RECOVERY (1) 3363 #define MPI3_PCIEIOUNIT3_ERROR_CORRECTABLE_ERROR_MSG (2) 3364 #define MPI3_PCIEIOUNIT3_ERROR_BAD_DLLP (3) 3365 #define MPI3_PCIEIOUNIT3_ERROR_BAD_TLP (4) 3366 #define MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX (5) 3367 3368 3369 typedef struct _MPI3_PCIE_IO_UNIT3_ERROR 3370 { 3371 U16 ThresholdCount; /* 0x00 */ 3372 U16 Reserved02; /* 0x02 */ 3373 } MPI3_PCIE_IO_UNIT3_ERROR, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT3_ERROR, 3374 Mpi3PcieIOUnit3Error_t, MPI3_POINTER pMpi3PcieIOUnit3Error_t; 3375 3376 typedef struct _MPI3_PCIE_IO_UNIT_PAGE3 3377 { 3378 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3379 U8 ThresholdWindow; /* 0x08 */ 3380 U8 ThresholdAction; /* 0x09 */ 3381 U8 EscalationCount; /* 0x0A */ 3382 U8 EscalationAction; /* 0x0B */ 3383 U8 NumErrors; /* 0x0C */ 3384 U8 Reserved0D[3]; /* 0x0D */ 3385 MPI3_PCIE_IO_UNIT3_ERROR Error[MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX]; /* 0x10 */ 3386 } MPI3_PCIE_IO_UNIT_PAGE3, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT_PAGE3, 3387 Mpi3PcieIOUnitPage3_t, MPI3_POINTER pMpi3PcieIOUnitPage3_t; 3388 3389 /**** Defines for the PageVersion field ****/ 3390 #define MPI3_PCIEIOUNIT3_PAGEVERSION (0x00) 3391 3392 /**** Defines for the ThresholdAction and EscalationAction fields ****/ 3393 #define MPI3_PCIEIOUNIT3_ACTION_NO_ACTION (0x00) 3394 #define MPI3_PCIEIOUNIT3_ACTION_HOT_RESET (0x01) 3395 #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_ONLY (0x02) 3396 #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_NO_ACCESS (0x03) 3397 3398 /**** Defines for Error Indexes - use MPI3_PCIEIOUNIT3_ERROR_ defines ****/ 3399 3400 /***************************************************************************** 3401 * PCIe Switch Configuration Pages * 3402 ****************************************************************************/ 3403 3404 /***************************************************************************** 3405 * PCIe Switch Page 0 * 3406 ****************************************************************************/ 3407 typedef struct _MPI3_PCIE_SWITCH_PAGE0 3408 { 3409 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3410 U8 IOUnitPort; /* 0x08 */ 3411 U8 SwitchStatus; /* 0x09 */ 3412 U8 Reserved0A[2]; /* 0x0A */ 3413 U16 DevHandle; /* 0x0C */ 3414 U16 ParentDevHandle; /* 0x0E */ 3415 U8 NumPorts; /* 0x10 */ 3416 U8 PCIeLevel; /* 0x11 */ 3417 U16 Reserved12; /* 0x12 */ 3418 U32 Reserved14; /* 0x14 */ 3419 U32 Reserved18; /* 0x18 */ 3420 U32 Reserved1C; /* 0x1C */ 3421 } MPI3_PCIE_SWITCH_PAGE0, MPI3_POINTER PTR_MPI3_PCIE_SWITCH_PAGE0, 3422 Mpi3PcieSwitchPage0_t, MPI3_POINTER pMpi3PcieSwitchPage0_t; 3423 3424 /**** Defines for the PageVersion field ****/ 3425 #define MPI3_PCIESWITCH0_PAGEVERSION (0x00) 3426 3427 /**** Defines for the SwitchStatus field ****/ 3428 #define MPI3_PCIESWITCH0_SS_NOT_RESPONDING (0x02) 3429 #define MPI3_PCIESWITCH0_SS_RESPONDING (0x03) 3430 #define MPI3_PCIESWITCH0_SS_DELAY_NOT_RESPONDING (0x04) 3431 3432 /***************************************************************************** 3433 * PCIe Switch Page 1 * 3434 ****************************************************************************/ 3435 typedef struct _MPI3_PCIE_SWITCH_PAGE1 3436 { 3437 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3438 U8 IOUnitPort; /* 0x08 */ 3439 U8 Flags; /* 0x09 */ 3440 U16 Reserved0A; /* 0x0A */ 3441 U8 NumPorts; /* 0x0C */ 3442 U8 PortNum; /* 0x0D */ 3443 U16 AttachedDevHandle; /* 0x0E */ 3444 U16 SwitchDevHandle; /* 0x10 */ 3445 U8 NegotiatedPortWidth; /* 0x12 */ 3446 U8 NegotiatedLinkRate; /* 0x13 */ 3447 U16 Slot; /* 0x14 */ 3448 U16 SlotIndex; /* 0x16 */ 3449 U32 Reserved18; /* 0x18 */ 3450 } MPI3_PCIE_SWITCH_PAGE1, MPI3_POINTER PTR_MPI3_PCIE_SWITCH_PAGE1, 3451 Mpi3PcieSwitchPage1_t, MPI3_POINTER pMpi3PcieSwitchPage1_t; 3452 3453 /**** Defines for the PageVersion field ****/ 3454 #define MPI3_PCIESWITCH1_PAGEVERSION (0x00) 3455 3456 /**** Defines for the Flags field ****/ 3457 #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_MASK (0x0C) 3458 #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_SHIFT (2) 3459 3460 /*** use MPI3_PCIE_ASPM_ENABLE_ defines for ASPMState field values ***/ 3461 #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_MASK (0x03) 3462 #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_SHIFT (0) 3463 3464 /*** use MPI3_PCIE_ASPM_SUPPORT_ defines for ASPMSupport field values ***/ 3465 3466 /**** Defines for the NegotiatedLinkRate field - use MPI3_PCIE_NEG_LINK_RATE_ defines ****/ 3467 3468 /**** Defines for the Slot field - use MPI3_SLOT_ defines ****/ 3469 3470 /**** Defines for the SlotIndex field - use MPI3_SLOT_INDEX_ ****/ 3471 3472 /***************************************************************************** 3473 * PCIe Switch Page 2 * 3474 ****************************************************************************/ 3475 #ifndef MPI3_PCIESWITCH2_MAX_NUM_PORTS 3476 #define MPI3_PCIESWITCH2_MAX_NUM_PORTS (1) 3477 #endif /* MPI3_PCIESWITCH2_MAX_NUM_PORTS */ 3478 3479 typedef struct _MPI3_PCIESWITCH2_PORT_ELEMENT 3480 { 3481 U16 LinkChangeCount; /* 0x00 */ 3482 U16 RateChangeCount; /* 0x02 */ 3483 U32 Reserved04; /* 0x04 */ 3484 } MPI3_PCIESWITCH2_PORT_ELEMENT, MPI3_POINTER PTR_MPI3_PCIESWITCH2_PORT_ELEMENT, 3485 Mpi3PcieSwitch2PortElement_t, MPI3_POINTER pMpi3PcieSwitch2PortElement_t; 3486 3487 typedef struct _MPI3_PCIE_SWITCH_PAGE2 3488 { 3489 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3490 U8 NumPorts; /* 0x08 */ 3491 U8 Reserved09; /* 0x09 */ 3492 U16 DevHandle; /* 0x0A */ 3493 U32 Reserved0C; /* 0x0C */ 3494 MPI3_PCIESWITCH2_PORT_ELEMENT Port[MPI3_PCIESWITCH2_MAX_NUM_PORTS]; /* 0x10 */ /* variable length */ 3495 } MPI3_PCIE_SWITCH_PAGE2, MPI3_POINTER PTR_MPI3_PCIE_SWITCH_PAGE2, 3496 Mpi3PcieSwitchPage2_t, MPI3_POINTER pMpi3PcieSwitchPage2_t; 3497 3498 /**** Defines for the PageVersion field ****/ 3499 #define MPI3_PCIESWITCH2_PAGEVERSION (0x00) 3500 3501 /***************************************************************************** 3502 * PCIe Link Configuration Pages * 3503 ****************************************************************************/ 3504 3505 /***************************************************************************** 3506 * PCIe Link Page 0 * 3507 ****************************************************************************/ 3508 typedef struct _MPI3_PCIE_LINK_PAGE0 3509 { 3510 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3511 U8 Link; /* 0x08 */ 3512 U8 Reserved09[3]; /* 0x09 */ 3513 U32 Reserved0C; /* 0x0C */ 3514 U32 ReceiverErrorCount; /* 0x10 */ 3515 U32 RecoveryCount; /* 0x14 */ 3516 U32 CorrErrorMsgCount; /* 0x18 */ 3517 U32 NonFatalErrorMsgCount; /* 0x1C */ 3518 U32 FatalErrorMsgCount; /* 0x20 */ 3519 U32 NonFatalErrorCount; /* 0x24 */ 3520 U32 FatalErrorCount; /* 0x28 */ 3521 U32 BadDLLPCount; /* 0x2C */ 3522 U32 BadTLPCount; /* 0x30 */ 3523 } MPI3_PCIE_LINK_PAGE0, MPI3_POINTER PTR_MPI3_PCIE_LINK_PAGE0, 3524 Mpi3PcieLinkPage0_t, MPI3_POINTER pMpi3PcieLinkPage0_t; 3525 3526 /**** Defines for the PageVersion field ****/ 3527 #define MPI3_PCIELINK0_PAGEVERSION (0x00) 3528 3529 3530 /***************************************************************************** 3531 * Enclosure Configuration Pages * 3532 ****************************************************************************/ 3533 3534 /***************************************************************************** 3535 * Enclosure Page 0 * 3536 ****************************************************************************/ 3537 typedef struct _MPI3_ENCLOSURE_PAGE0 3538 { 3539 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3540 U64 EnclosureLogicalID; /* 0x08 */ 3541 U16 Flags; /* 0x10 */ 3542 U16 EnclosureHandle; /* 0x12 */ 3543 U16 NumSlots; /* 0x14 */ 3544 U16 Reserved16; /* 0x16 */ 3545 U8 IOUnitPort; /* 0x18 */ 3546 U8 EnclosureLevel; /* 0x19 */ 3547 U16 SEPDevHandle; /* 0x1A */ 3548 U8 ChassisSlot; /* 0x1C */ 3549 U8 Reserved1D[3]; /* 0x1D */ 3550 U32 ReceptacleIDs; /* 0x20 */ 3551 U32 Reserved24; /* 0x24 */ 3552 } MPI3_ENCLOSURE_PAGE0, MPI3_POINTER PTR_MPI3_ENCLOSURE_PAGE0, 3553 Mpi3EnclosurePage0_t, MPI3_POINTER pMpi3EnclosurePage0_t; 3554 3555 /**** Defines for the PageVersion field ****/ 3556 #define MPI3_ENCLOSURE0_PAGEVERSION (0x00) 3557 3558 /**** Defines for the Flags field ****/ 3559 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_MASK (0xC000) 3560 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_VIRTUAL (0x0000) 3561 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_SAS (0x4000) 3562 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_PCIE (0x8000) 3563 #define MPI3_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3564 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT_MASK (0x0010) 3565 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_NOT_FOUND (0x0000) 3566 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT (0x0010) 3567 #define MPI3_ENCLS0_FLAGS_MNG_MASK (0x000F) 3568 #define MPI3_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3569 #define MPI3_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3570 #define MPI3_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0002) 3571 3572 /**** Defines for the ReceptacleIDs field ****/ 3573 #define MPI3_ENCLS0_RECEPTACLEIDS_NOT_REPORTED (0x00000000) 3574 3575 /***************************************************************************** 3576 * Device Configuration Pages * 3577 ****************************************************************************/ 3578 3579 /***************************************************************************** 3580 * Common definitions used by Device Configuration Pages * 3581 ****************************************************************************/ 3582 3583 /**** Defines for the DeviceForm field ****/ 3584 #define MPI3_DEVICE_DEVFORM_SAS_SATA (0x00) 3585 #define MPI3_DEVICE_DEVFORM_PCIE (0x01) 3586 #define MPI3_DEVICE_DEVFORM_VD (0x02) 3587 3588 /***************************************************************************** 3589 * Device Page 0 * 3590 ****************************************************************************/ 3591 typedef struct _MPI3_DEVICE0_SAS_SATA_FORMAT 3592 { 3593 U64 SASAddress; /* 0x00 */ 3594 U16 Flags; /* 0x08 */ 3595 U16 DeviceInfo; /* 0x0A */ 3596 U8 PhyNum; /* 0x0C */ 3597 U8 AttachedPhyIdentifier; /* 0x0D */ 3598 U8 MaxPortConnections; /* 0x0E */ 3599 U8 ZoneGroup; /* 0x0F */ 3600 } MPI3_DEVICE0_SAS_SATA_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE0_SAS_SATA_FORMAT, 3601 Mpi3Device0SasSataFormat_t, MPI3_POINTER pMpi3Device0SasSataFormat_t; 3602 3603 /**** Defines for the Flags field ****/ 3604 #define MPI3_DEVICE0_SASSATA_FLAGS_WRITE_SAME_UNMAP_NCQ (0x0400) 3605 #define MPI3_DEVICE0_SASSATA_FLAGS_SLUMBER_CAP (0x0200) 3606 #define MPI3_DEVICE0_SASSATA_FLAGS_PARTIAL_CAP (0x0100) 3607 #define MPI3_DEVICE0_SASSATA_FLAGS_ASYNC_NOTIFY (0x0080) 3608 #define MPI3_DEVICE0_SASSATA_FLAGS_SW_PRESERVE (0x0040) 3609 #define MPI3_DEVICE0_SASSATA_FLAGS_UNSUPP_DEV (0x0020) 3610 #define MPI3_DEVICE0_SASSATA_FLAGS_48BIT_LBA (0x0010) 3611 #define MPI3_DEVICE0_SASSATA_FLAGS_SMART_SUPP (0x0008) 3612 #define MPI3_DEVICE0_SASSATA_FLAGS_NCQ_SUPP (0x0004) 3613 #define MPI3_DEVICE0_SASSATA_FLAGS_FUA_SUPP (0x0002) 3614 #define MPI3_DEVICE0_SASSATA_FLAGS_PERSIST_CAP (0x0001) 3615 3616 /**** Defines for the DeviceInfo field - use MPI3_SAS_DEVICE_INFO_ defines (see mpi30_sas.h) ****/ 3617 3618 typedef struct _MPI3_DEVICE0_PCIE_FORMAT 3619 { 3620 U8 SupportedLinkRates; /* 0x00 */ 3621 U8 MaxPortWidth; /* 0x01 */ 3622 U8 NegotiatedPortWidth; /* 0x02 */ 3623 U8 NegotiatedLinkRate; /* 0x03 */ 3624 U8 PortNum; /* 0x04 */ 3625 U8 ControllerResetTO; /* 0x05 */ 3626 U16 DeviceInfo; /* 0x06 */ 3627 U32 MaximumDataTransferSize; /* 0x08 */ 3628 U32 Capabilities; /* 0x0C */ 3629 U16 NOIOB; /* 0x10 */ 3630 U8 NVMeAbortTO; /* 0x12 */ 3631 U8 PageSize; /* 0x13 */ 3632 U16 ShutdownLatency; /* 0x14 */ 3633 U8 RecoveryInfo; /* 0x16 */ 3634 U8 Reserved17; /* 0x17 */ 3635 } MPI3_DEVICE0_PCIE_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE0_PCIE_FORMAT, 3636 Mpi3Device0PcieFormat_t, MPI3_POINTER pMpi3Device0PcieFormat_t; 3637 3638 /**** Defines for the SupportedLinkRates field ****/ 3639 #define MPI3_DEVICE0_PCIE_LINK_RATE_32_0_SUPP (0x10) 3640 #define MPI3_DEVICE0_PCIE_LINK_RATE_16_0_SUPP (0x08) 3641 #define MPI3_DEVICE0_PCIE_LINK_RATE_8_0_SUPP (0x04) 3642 #define MPI3_DEVICE0_PCIE_LINK_RATE_5_0_SUPP (0x02) 3643 #define MPI3_DEVICE0_PCIE_LINK_RATE_2_5_SUPP (0x01) 3644 3645 /**** Defines for the NegotiatedLinkRate field - use MPI3_PCIE_NEG_LINK_RATE_ defines ****/ 3646 3647 /**** Defines for DeviceInfo bitfield ****/ 3648 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK (0x0007) 3649 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NO_DEVICE (0x0000) 3650 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE (0x0001) 3651 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SWITCH_DEVICE (0x0002) 3652 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SCSI_DEVICE (0x0003) 3653 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_MASK (0x0030) 3654 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_SHIFT (4) 3655 /*** use MPI3_PCIE_ASPM_ENABLE_ defines for ASPM field values ***/ 3656 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_MASK (0x00C0) 3657 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_SHIFT (6) 3658 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_0 (0x0000) 3659 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_1 (0x0040) 3660 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_2 (0x0080) 3661 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_3 (0x00C0) 3662 3663 3664 /**** Defines for the Capabilities field ****/ 3665 #define MPI3_DEVICE0_PCIE_CAP_SGL_EXTRA_LENGTH_SUPPORTED (0x00000020) 3666 #define MPI3_DEVICE0_PCIE_CAP_METADATA_SEPARATED (0x00000010) 3667 #define MPI3_DEVICE0_PCIE_CAP_SGL_DWORD_ALIGN_REQUIRED (0x00000008) 3668 #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_SGL (0x00000004) 3669 #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_PRP (0x00000000) 3670 #define MPI3_DEVICE0_PCIE_CAP_BIT_BUCKET_SGL_SUPP (0x00000002) 3671 #define MPI3_DEVICE0_PCIE_CAP_SGL_SUPP (0x00000001) 3672 #define MPI3_DEVICE0_PCIE_CAP_ASPM_MASK (0x000000C0) 3673 #define MPI3_DEVICE0_PCIE_CAP_ASPM_SHIFT (6) 3674 /*** use MPI3_PCIE_ASPM_SUPPORT_ defines for ASPM field values ***/ 3675 3676 /**** Defines for the RecoveryInfo field ****/ 3677 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_MASK (0xE0) 3678 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_NS_MGMT (0x00) 3679 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_FORMAT (0x20) 3680 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_MASK (0x1F) 3681 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NS (0x00) 3682 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NSID_1 (0x01) 3683 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_TOO_MANY_NS (0x02) 3684 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_PROTECTION (0x03) 3685 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_METADATA_SZ (0x04) 3686 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_LBA_DATA_SZ (0x05) 3687 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_PARTIAL_CAP (0x06) 3688 3689 typedef struct _MPI3_DEVICE0_VD_FORMAT 3690 { 3691 U8 VdState; /* 0x00 */ 3692 U8 RAIDLevel; /* 0x01 */ 3693 U16 DeviceInfo; /* 0x02 */ 3694 U16 Flags; /* 0x04 */ 3695 U16 IOThrottleGroup; /* 0x06 */ 3696 U16 IOThrottleGroupLow; /* 0x08 */ 3697 U16 IOThrottleGroupHigh; /* 0x0A */ 3698 U32 Reserved0C; /* 0x0C */ 3699 } MPI3_DEVICE0_VD_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE0_VD_FORMAT, 3700 Mpi3Device0VdFormat_t, MPI3_POINTER pMpi3Device0VdFormat_t; 3701 3702 /**** Defines for the VdState field ****/ 3703 #define MPI3_DEVICE0_VD_STATE_OFFLINE (0x00) 3704 #define MPI3_DEVICE0_VD_STATE_PARTIALLY_DEGRADED (0x01) 3705 #define MPI3_DEVICE0_VD_STATE_DEGRADED (0x02) 3706 #define MPI3_DEVICE0_VD_STATE_OPTIMAL (0x03) 3707 3708 /**** Defines for RAIDLevel field ****/ 3709 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_0 (0) 3710 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_1 (1) 3711 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_5 (5) 3712 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_6 (6) 3713 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_10 (10) 3714 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_50 (50) 3715 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_60 (60) 3716 3717 /**** Defines for DeviceInfo field ****/ 3718 #define MPI3_DEVICE0_VD_DEVICE_INFO_HDD (0x0010) 3719 #define MPI3_DEVICE0_VD_DEVICE_INFO_SSD (0x0008) 3720 #define MPI3_DEVICE0_VD_DEVICE_INFO_NVME (0x0004) 3721 #define MPI3_DEVICE0_VD_DEVICE_INFO_SATA (0x0002) 3722 #define MPI3_DEVICE0_VD_DEVICE_INFO_SAS (0x0001) 3723 3724 /**** Defines for the Flags field ****/ 3725 #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_MASK (0xF000) 3726 #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_SHIFT (12) 3727 3728 typedef union _MPI3_DEVICE0_DEV_SPEC_FORMAT 3729 { 3730 MPI3_DEVICE0_SAS_SATA_FORMAT SasSataFormat; 3731 MPI3_DEVICE0_PCIE_FORMAT PcieFormat; 3732 MPI3_DEVICE0_VD_FORMAT VdFormat; 3733 } MPI3_DEVICE0_DEV_SPEC_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE0_DEV_SPEC_FORMAT, 3734 Mpi3Device0DevSpecFormat_t, MPI3_POINTER pMpi3Device0DevSpecFormat_t; 3735 3736 typedef struct _MPI3_DEVICE_PAGE0 3737 { 3738 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3739 U16 DevHandle; /* 0x08 */ 3740 U16 ParentDevHandle; /* 0x0A */ 3741 U16 Slot; /* 0x0C */ 3742 U16 EnclosureHandle; /* 0x0E */ 3743 U64 WWID; /* 0x10 */ 3744 U16 PersistentID; /* 0x18 */ 3745 U8 IOUnitPort; /* 0x1A */ 3746 U8 AccessStatus; /* 0x1B */ 3747 U16 Flags; /* 0x1C */ 3748 U16 Reserved1E; /* 0x1E */ 3749 U16 SlotIndex; /* 0x20 */ 3750 U16 QueueDepth; /* 0x22 */ 3751 U8 Reserved24[3]; /* 0x24 */ 3752 U8 DeviceForm; /* 0x27 */ 3753 MPI3_DEVICE0_DEV_SPEC_FORMAT DeviceSpecific; /* 0x28 */ 3754 } MPI3_DEVICE_PAGE0, MPI3_POINTER PTR_MPI3_DEVICE_PAGE0, 3755 Mpi3DevicePage0_t, MPI3_POINTER pMpi3DevicePage0_t; 3756 3757 /**** Defines for the PageVersion field ****/ 3758 #define MPI3_DEVICE0_PAGEVERSION (0x00) 3759 3760 /**** Defines for the ParentDevHandle field ****/ 3761 #define MPI3_DEVICE0_PARENT_INVALID (0xFFFF) 3762 3763 /**** Defines for the Slot field - use MPI3_SLOT_ defines ****/ 3764 3765 /**** Defines for the EnclosureHandle field ****/ 3766 #define MPI3_DEVICE0_ENCLOSURE_HANDLE_NO_ENCLOSURE (0x0000) 3767 3768 /**** Defines for the WWID field ****/ 3769 #define MPI3_DEVICE0_WWID_INVALID (0xFFFFFFFFFFFFFFFF) 3770 3771 /**** Defines for the PersistentID field ****/ 3772 #define MPI3_DEVICE0_PERSISTENTID_INVALID (0xFFFF) 3773 3774 /**** Defines for the IOUnitPort field ****/ 3775 #define MPI3_DEVICE0_IOUNITPORT_INVALID (0xFF) 3776 3777 /**** Defines for the AccessStatus field ****/ 3778 /* Generic Access Status Codes */ 3779 #define MPI3_DEVICE0_ASTATUS_NO_ERRORS (0x00) 3780 #define MPI3_DEVICE0_ASTATUS_NEEDS_INITIALIZATION (0x01) 3781 #define MPI3_DEVICE0_ASTATUS_CAP_UNSUPPORTED (0x02) 3782 #define MPI3_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x03) 3783 #define MPI3_DEVICE0_ASTATUS_UNAUTHORIZED (0x04) 3784 #define MPI3_DEVICE0_ASTATUS_DEVICE_MISSING_DELAY (0x05) 3785 #define MPI3_DEVICE0_ASTATUS_PREPARE (0x06) 3786 #define MPI3_DEVICE0_ASTATUS_SAFE_MODE (0x07) 3787 #define MPI3_DEVICE0_ASTATUS_GENERIC_MAX (0x0F) 3788 /* SAS Access Status Codes */ 3789 #define MPI3_DEVICE0_ASTATUS_SAS_UNKNOWN (0x10) 3790 #define MPI3_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x11) 3791 #define MPI3_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x12) 3792 #define MPI3_DEVICE0_ASTATUS_SAS_MAX (0x1F) 3793 /* SATA Access Status Codes */ 3794 #define MPI3_DEVICE0_ASTATUS_SIF_UNKNOWN (0x20) 3795 #define MPI3_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x21) 3796 #define MPI3_DEVICE0_ASTATUS_SIF_DIAG (0x22) 3797 #define MPI3_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x23) 3798 #define MPI3_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x24) 3799 #define MPI3_DEVICE0_ASTATUS_SIF_PIO_SN (0x25) 3800 #define MPI3_DEVICE0_ASTATUS_SIF_MDMA_SN (0x26) 3801 #define MPI3_DEVICE0_ASTATUS_SIF_UDMA_SN (0x27) 3802 #define MPI3_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x28) 3803 #define MPI3_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x29) 3804 #define MPI3_DEVICE0_ASTATUS_SIF_MAX (0x2F) 3805 /* PCIe Access Status Codes */ 3806 #define MPI3_DEVICE0_ASTATUS_PCIE_UNKNOWN (0x30) 3807 #define MPI3_DEVICE0_ASTATUS_PCIE_MEM_SPACE_ACCESS (0x31) 3808 #define MPI3_DEVICE0_ASTATUS_PCIE_UNSUPPORTED (0x32) 3809 #define MPI3_DEVICE0_ASTATUS_PCIE_MSIX_REQUIRED (0x33) 3810 #define MPI3_DEVICE0_ASTATUS_PCIE_ECRC_REQUIRED (0x34) 3811 #define MPI3_DEVICE0_ASTATUS_PCIE_MAX (0x3F) 3812 /* NVMe Access Status Codes */ 3813 #define MPI3_DEVICE0_ASTATUS_NVME_UNKNOWN (0x40) 3814 #define MPI3_DEVICE0_ASTATUS_NVME_READY_TIMEOUT (0x41) 3815 #define MPI3_DEVICE0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x42) 3816 #define MPI3_DEVICE0_ASTATUS_NVME_IDENTIFY_FAILED (0x43) 3817 #define MPI3_DEVICE0_ASTATUS_NVME_QCONFIG_FAILED (0x44) 3818 #define MPI3_DEVICE0_ASTATUS_NVME_QCREATION_FAILED (0x45) 3819 #define MPI3_DEVICE0_ASTATUS_NVME_EVENTCFG_FAILED (0x46) 3820 #define MPI3_DEVICE0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x47) 3821 #define MPI3_DEVICE0_ASTATUS_NVME_IDLE_TIMEOUT (0x48) 3822 #define MPI3_DEVICE0_ASTATUS_NVME_CTRL_FAILURE_STATUS (0x49) 3823 #define MPI3_DEVICE0_ASTATUS_NVME_INSUFFICIENT_POWER (0x4A) 3824 #define MPI3_DEVICE0_ASTATUS_NVME_DOORBELL_STRIDE (0x4B) 3825 #define MPI3_DEVICE0_ASTATUS_NVME_MEM_PAGE_MIN_SIZE (0x4C) 3826 #define MPI3_DEVICE0_ASTATUS_NVME_MEMORY_ALLOCATION (0x4D) 3827 #define MPI3_DEVICE0_ASTATUS_NVME_COMPLETION_TIME (0x4E) 3828 #define MPI3_DEVICE0_ASTATUS_NVME_BAR (0x4F) 3829 #define MPI3_DEVICE0_ASTATUS_NVME_NS_DESCRIPTOR (0x50) 3830 #define MPI3_DEVICE0_ASTATUS_NVME_INCOMPATIBLE_SETTINGS (0x51) 3831 #define MPI3_DEVICE0_ASTATUS_NVME_TOO_MANY_ERRORS (0x52) 3832 #define MPI3_DEVICE0_ASTATUS_NVME_MAX (0x5F) 3833 /* Virtual Device Access Status Codes */ 3834 #define MPI3_DEVICE0_ASTATUS_VD_UNKNOWN (0x80) 3835 #define MPI3_DEVICE0_ASTATUS_VD_MAX (0x8F) 3836 3837 /**** Defines for the Flags field ****/ 3838 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_MASK (0xE000) 3839 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_NO_LIMIT (0x0000) 3840 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_256_LB (0x2000) 3841 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_2048_LB (0x4000) 3842 #define MPI3_DEVICE0_FLAGS_CONTROLLER_DEV_HANDLE (0x0080) 3843 #define MPI3_DEVICE0_FLAGS_IO_THROTTLING_REQUIRED (0x0010) 3844 #define MPI3_DEVICE0_FLAGS_HIDDEN (0x0008) 3845 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_VIRTUAL (0x0004) 3846 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_DIR_ATTACHED (0x0002) 3847 #define MPI3_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 3848 3849 /**** Defines for the SlotIndex field - use MPI3_SLOT_INDEX_ defines ****/ 3850 3851 /**** Defines for the DeviceForm field - use MPI3_DEVICE_DEVFORM_ defines ****/ 3852 3853 /**** Defines for the QueueDepth field ****/ 3854 #define MPI3_DEVICE0_QUEUE_DEPTH_NOT_APPLICABLE (0x0000) 3855 3856 3857 /***************************************************************************** 3858 * Device Page 1 * 3859 ****************************************************************************/ 3860 typedef struct _MPI3_DEVICE1_SAS_SATA_FORMAT 3861 { 3862 U32 Reserved00; /* 0x00 */ 3863 } MPI3_DEVICE1_SAS_SATA_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE1_SAS_SATA_FORMAT, 3864 Mpi3Device1SasSataFormat_t, MPI3_POINTER pMpi3Device1SasSataFormat_t; 3865 3866 typedef struct _MPI3_DEVICE1_PCIE_FORMAT 3867 { 3868 U16 VendorID; /* 0x00 */ 3869 U16 DeviceID; /* 0x02 */ 3870 U16 SubsystemVendorID; /* 0x04 */ 3871 U16 SubsystemID; /* 0x06 */ 3872 U32 Reserved08; /* 0x08 */ 3873 U8 RevisionID; /* 0x0C */ 3874 U8 Reserved0D; /* 0x0D */ 3875 U16 PCIParameters; /* 0x0E */ 3876 } MPI3_DEVICE1_PCIE_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE1_PCIE_FORMAT, 3877 Mpi3Device1PcieFormat_t, MPI3_POINTER pMpi3Device1PcieFormat_t; 3878 3879 /**** Defines for the PCIParameters field ****/ 3880 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_128B (0x0) 3881 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_256B (0x1) 3882 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_512B (0x2) 3883 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_1024B (0x3) 3884 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_2048B (0x4) 3885 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_4096B (0x5) 3886 3887 /*** MaxReadRequestSize, CurrentMaxPayloadSize, and MaxPayloadSizeSupported ***/ 3888 /*** all use the size definitions above - shifted to the proper position ***/ 3889 #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_MASK (0x01C0) 3890 #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_SHIFT (6) 3891 #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_MASK (0x0038) 3892 #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_SHIFT (3) 3893 #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_MASK (0x0007) 3894 #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_SHIFT (0) 3895 3896 typedef struct _MPI3_DEVICE1_VD_FORMAT 3897 { 3898 U32 Reserved00; /* 0x00 */ 3899 } MPI3_DEVICE1_VD_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE1_VD_FORMAT, 3900 Mpi3Device1VdFormat_t, MPI3_POINTER pMpi3Device1VdFormat_t; 3901 3902 typedef union _MPI3_DEVICE1_DEV_SPEC_FORMAT 3903 { 3904 MPI3_DEVICE1_SAS_SATA_FORMAT SasSataFormat; 3905 MPI3_DEVICE1_PCIE_FORMAT PcieFormat; 3906 MPI3_DEVICE1_VD_FORMAT VdFormat; 3907 } MPI3_DEVICE1_DEV_SPEC_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE1_DEV_SPEC_FORMAT, 3908 Mpi3Device1DevSpecFormat_t, MPI3_POINTER pMpi3Device1DevSpecFormat_t; 3909 3910 typedef struct _MPI3_DEVICE_PAGE1 3911 { 3912 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3913 U16 DevHandle; /* 0x08 */ 3914 U16 Reserved0A; /* 0x0A */ 3915 U16 LinkChangeCount; /* 0x0C */ 3916 U16 RateChangeCount; /* 0x0E */ 3917 U16 TMCount; /* 0x10 */ 3918 U16 Reserved12; /* 0x12 */ 3919 U32 Reserved14[10]; /* 0x14 */ 3920 U8 Reserved3C[3]; /* 0x3C */ 3921 U8 DeviceForm; /* 0x3F */ 3922 MPI3_DEVICE1_DEV_SPEC_FORMAT DeviceSpecific; /* 0x40 */ 3923 } MPI3_DEVICE_PAGE1, MPI3_POINTER PTR_MPI3_DEVICE_PAGE1, 3924 Mpi3DevicePage1_t, MPI3_POINTER pMpi3DevicePage1_t; 3925 3926 /**** Defines for the PageVersion field ****/ 3927 #define MPI3_DEVICE1_PAGEVERSION (0x00) 3928 3929 /**** Defines for the LinkChangeCount, RateChangeCount, TMCount fields ****/ 3930 #define MPI3_DEVICE1_COUNTER_MAX (0xFFFE) 3931 #define MPI3_DEVICE1_COUNTER_INVALID (0xFFFF) 3932 3933 /**** Defines for the DeviceForm field - use MPI3_DEVICE_DEVFORM_ defines ****/ 3934 3935 #endif /* MPI30_CNFG_H */ 3936