1 /* 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2016-2023, Broadcom Inc. All rights reserved. 5 * Support: <fbsd-storage-driver.pdl@broadcom.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions are 9 * met: 10 * 11 * 1. Redistributions of source code must retain the above copyright notice, 12 * this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright notice, 14 * this list of conditions and the following disclaimer in the documentation and/or other 15 * materials provided with the distribution. 16 * 3. Neither the name of the Broadcom Inc. nor the names of its contributors 17 * may be used to endorse or promote products derived from this software without 18 * specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 24 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 * 32 * The views and conclusions contained in the software and documentation are 33 * those of the authors and should not be interpreted as representing 34 * official policies,either expressed or implied, of the FreeBSD Project. 35 * 36 * Mail to: Broadcom Inc 1320 Ridder Park Dr, San Jose, CA 95131 37 * 38 * Broadcom Inc. (Broadcom) MPI3MR Adapter FreeBSD 39 * 40 */ 41 42 #ifndef MPI30_CNFG_H 43 #define MPI30_CNFG_H 1 44 45 /***************************************************************************** 46 * Configuration Page Types * 47 ****************************************************************************/ 48 #define MPI3_CONFIG_PAGETYPE_IO_UNIT (0x00) 49 #define MPI3_CONFIG_PAGETYPE_MANUFACTURING (0x01) 50 #define MPI3_CONFIG_PAGETYPE_IOC (0x02) 51 #define MPI3_CONFIG_PAGETYPE_DRIVER (0x03) 52 #define MPI3_CONFIG_PAGETYPE_SECURITY (0x04) 53 #define MPI3_CONFIG_PAGETYPE_ENCLOSURE (0x11) 54 #define MPI3_CONFIG_PAGETYPE_DEVICE (0x12) 55 #define MPI3_CONFIG_PAGETYPE_SAS_IO_UNIT (0x20) 56 #define MPI3_CONFIG_PAGETYPE_SAS_EXPANDER (0x21) 57 #define MPI3_CONFIG_PAGETYPE_SAS_PHY (0x23) 58 #define MPI3_CONFIG_PAGETYPE_SAS_PORT (0x24) 59 #define MPI3_CONFIG_PAGETYPE_PCIE_IO_UNIT (0x30) 60 #define MPI3_CONFIG_PAGETYPE_PCIE_SWITCH (0x31) 61 #define MPI3_CONFIG_PAGETYPE_PCIE_LINK (0x33) 62 63 /***************************************************************************** 64 * Configuration Page Attributes * 65 ****************************************************************************/ 66 #define MPI3_CONFIG_PAGEATTR_MASK (0xF0) 67 #define MPI3_CONFIG_PAGEATTR_READ_ONLY (0x00) 68 #define MPI3_CONFIG_PAGEATTR_CHANGEABLE (0x10) 69 #define MPI3_CONFIG_PAGEATTR_PERSISTENT (0x20) 70 71 /***************************************************************************** 72 * Configuration Page Actions * 73 ****************************************************************************/ 74 #define MPI3_CONFIG_ACTION_PAGE_HEADER (0x00) 75 #define MPI3_CONFIG_ACTION_READ_DEFAULT (0x01) 76 #define MPI3_CONFIG_ACTION_READ_CURRENT (0x02) 77 #define MPI3_CONFIG_ACTION_WRITE_CURRENT (0x03) 78 #define MPI3_CONFIG_ACTION_READ_PERSISTENT (0x04) 79 #define MPI3_CONFIG_ACTION_WRITE_PERSISTENT (0x05) 80 81 /***************************************************************************** 82 * Configuration Page Addressing * 83 ****************************************************************************/ 84 85 /**** Device PageAddress Format ****/ 86 #define MPI3_DEVICE_PGAD_FORM_MASK (0xF0000000) 87 #define MPI3_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 88 #define MPI3_DEVICE_PGAD_FORM_HANDLE (0x20000000) 89 #define MPI3_DEVICE_PGAD_HANDLE_MASK (0x0000FFFF) 90 91 /**** SAS Expander PageAddress Format ****/ 92 #define MPI3_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000) 93 #define MPI3_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 94 #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x10000000) 95 #define MPI3_SAS_EXPAND_PGAD_FORM_HANDLE (0x20000000) 96 #define MPI3_SAS_EXPAND_PGAD_PHYNUM_MASK (0x00FF0000) 97 #define MPI3_SAS_EXPAND_PGAD_PHYNUM_SHIFT (16) 98 #define MPI3_SAS_EXPAND_PGAD_HANDLE_MASK (0x0000FFFF) 99 100 /**** SAS Phy PageAddress Format ****/ 101 #define MPI3_SAS_PHY_PGAD_FORM_MASK (0xF0000000) 102 #define MPI3_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x00000000) 103 #define MPI3_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF) 104 105 /**** SAS Port PageAddress Format ****/ 106 #define MPI3_SASPORT_PGAD_FORM_MASK (0xF0000000) 107 #define MPI3_SASPORT_PGAD_FORM_GET_NEXT_PORT (0x00000000) 108 #define MPI3_SASPORT_PGAD_FORM_PORT_NUM (0x10000000) 109 #define MPI3_SASPORT_PGAD_PORT_NUMBER_MASK (0x000000FF) 110 111 /**** Enclosure PageAddress Format ****/ 112 #define MPI3_ENCLOS_PGAD_FORM_MASK (0xF0000000) 113 #define MPI3_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 114 #define MPI3_ENCLOS_PGAD_FORM_HANDLE (0x10000000) 115 #define MPI3_ENCLOS_PGAD_HANDLE_MASK (0x0000FFFF) 116 117 /**** PCIe Switch PageAddress Format ****/ 118 #define MPI3_PCIE_SWITCH_PGAD_FORM_MASK (0xF0000000) 119 #define MPI3_PCIE_SWITCH_PGAD_FORM_GET_NEXT_HANDLE (0x00000000) 120 #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE_PORT_NUM (0x10000000) 121 #define MPI3_PCIE_SWITCH_PGAD_FORM_HANDLE (0x20000000) 122 #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_MASK (0x00FF0000) 123 #define MPI3_PCIE_SWITCH_PGAD_PORTNUM_SHIFT (16) 124 #define MPI3_PCIE_SWITCH_PGAD_HANDLE_MASK (0x0000FFFF) 125 126 /**** PCIe Link PageAddress Format ****/ 127 #define MPI3_PCIE_LINK_PGAD_FORM_MASK (0xF0000000) 128 #define MPI3_PCIE_LINK_PGAD_FORM_GET_NEXT_LINK (0x00000000) 129 #define MPI3_PCIE_LINK_PGAD_FORM_LINK_NUM (0x10000000) 130 #define MPI3_PCIE_LINK_PGAD_LINKNUM_MASK (0x000000FF) 131 132 /**** Security PageAddress Format ****/ 133 #define MPI3_SECURITY_PGAD_FORM_MASK (0xF0000000) 134 #define MPI3_SECURITY_PGAD_FORM_GET_NEXT_SLOT (0x00000000) 135 #define MPI3_SECURITY_PGAD_FORM_SLOT_NUM (0x10000000) 136 #define MPI3_SECURITY_PGAD_SLOT_GROUP_MASK (0x0000FF00) 137 #define MPI3_SECURITY_PGAD_SLOT_GROUP_SHIFT (8) 138 #define MPI3_SECURITY_PGAD_SLOT_MASK (0x000000FF) 139 140 /***************************************************************************** 141 * Configuration Request Message * 142 ****************************************************************************/ 143 typedef struct _MPI3_CONFIG_REQUEST 144 { 145 U16 HostTag; /* 0x00 */ 146 U8 IOCUseOnly02; /* 0x02 */ 147 U8 Function; /* 0x03 */ 148 U16 IOCUseOnly04; /* 0x04 */ 149 U8 IOCUseOnly06; /* 0x06 */ 150 U8 MsgFlags; /* 0x07 */ 151 U16 ChangeCount; /* 0x08 */ 152 U16 Reserved0A; /* 0x0A */ 153 U8 PageVersion; /* 0x0C */ 154 U8 PageNumber; /* 0x0D */ 155 U8 PageType; /* 0x0E */ 156 U8 Action; /* 0x0F */ 157 U32 PageAddress; /* 0x10 */ 158 U16 PageLength; /* 0x14 */ 159 U16 Reserved16; /* 0x16 */ 160 U32 Reserved18[2]; /* 0x18 */ 161 MPI3_SGE_UNION SGL; /* 0x20 */ 162 } MPI3_CONFIG_REQUEST, MPI3_POINTER PTR_MPI3_CONFIG_REQUEST, 163 Mpi3ConfigRequest_t, MPI3_POINTER pMpi3ConfigRequest_t; 164 165 /***************************************************************************** 166 * Configuration Pages * 167 ****************************************************************************/ 168 169 /***************************************************************************** 170 * Configuration Page Header * 171 ****************************************************************************/ 172 typedef struct _MPI3_CONFIG_PAGE_HEADER 173 { 174 U8 PageVersion; /* 0x00 */ 175 U8 Reserved01; /* 0x01 */ 176 U8 PageNumber; /* 0x02 */ 177 U8 PageAttribute; /* 0x03 */ 178 U16 PageLength; /* 0x04 */ 179 U8 PageType; /* 0x06 */ 180 U8 Reserved07; /* 0x07 */ 181 } MPI3_CONFIG_PAGE_HEADER, MPI3_POINTER PTR_MPI3_CONFIG_PAGE_HEADER, 182 Mpi3ConfigPageHeader_t, MPI3_POINTER pMpi3ConfigPageHeader_t; 183 184 /***************************************************************************** 185 * Common definitions used by Configuration Pages * 186 ****************************************************************************/ 187 188 /**** Defines for Negotiated Link Rates ****/ 189 #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_MASK (0xF0) 190 #define MPI3_SAS_NEG_LINK_RATE_LOGICAL_SHIFT (4) 191 #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_MASK (0x0F) 192 #define MPI3_SAS_NEG_LINK_RATE_PHYSICAL_SHIFT (0) 193 /*** Below defines are used in both the PhysicalLinkRate and ***/ 194 /*** LogicalLinkRate fields above. ***/ 195 /*** (by applying the proper _SHIFT value) ***/ 196 #define MPI3_SAS_NEG_LINK_RATE_UNKNOWN_LINK_RATE (0x00) 197 #define MPI3_SAS_NEG_LINK_RATE_PHY_DISABLED (0x01) 198 #define MPI3_SAS_NEG_LINK_RATE_NEGOTIATION_FAILED (0x02) 199 #define MPI3_SAS_NEG_LINK_RATE_SATA_OOB_COMPLETE (0x03) 200 #define MPI3_SAS_NEG_LINK_RATE_PORT_SELECTOR (0x04) 201 #define MPI3_SAS_NEG_LINK_RATE_SMP_RESET_IN_PROGRESS (0x05) 202 #define MPI3_SAS_NEG_LINK_RATE_UNSUPPORTED_PHY (0x06) 203 #define MPI3_SAS_NEG_LINK_RATE_1_5 (0x08) 204 #define MPI3_SAS_NEG_LINK_RATE_3_0 (0x09) 205 #define MPI3_SAS_NEG_LINK_RATE_6_0 (0x0A) 206 #define MPI3_SAS_NEG_LINK_RATE_12_0 (0x0B) 207 #define MPI3_SAS_NEG_LINK_RATE_22_5 (0x0C) 208 209 /**** Defines for the AttachedPhyInfo field ****/ 210 #define MPI3_SAS_APHYINFO_INSIDE_ZPSDS_PERSISTENT (0x00000040) 211 #define MPI3_SAS_APHYINFO_REQUESTED_INSIDE_ZPSDS (0x00000020) 212 #define MPI3_SAS_APHYINFO_BREAK_REPLY_CAPABLE (0x00000010) 213 214 #define MPI3_SAS_APHYINFO_REASON_MASK (0x0000000F) 215 #define MPI3_SAS_APHYINFO_REASON_UNKNOWN (0x00000000) 216 #define MPI3_SAS_APHYINFO_REASON_POWER_ON (0x00000001) 217 #define MPI3_SAS_APHYINFO_REASON_HARD_RESET (0x00000002) 218 #define MPI3_SAS_APHYINFO_REASON_SMP_PHY_CONTROL (0x00000003) 219 #define MPI3_SAS_APHYINFO_REASON_LOSS_OF_SYNC (0x00000004) 220 #define MPI3_SAS_APHYINFO_REASON_MULTIPLEXING_SEQ (0x00000005) 221 #define MPI3_SAS_APHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00000006) 222 #define MPI3_SAS_APHYINFO_REASON_BREAK_TIMEOUT (0x00000007) 223 #define MPI3_SAS_APHYINFO_REASON_PHY_TEST_STOPPED (0x00000008) 224 #define MPI3_SAS_APHYINFO_REASON_EXP_REDUCED_FUNC (0x00000009) 225 226 /**** Defines for the PhyInfo field ****/ 227 #define MPI3_SAS_PHYINFO_STATUS_MASK (0xC0000000) 228 #define MPI3_SAS_PHYINFO_STATUS_SHIFT (30) 229 #define MPI3_SAS_PHYINFO_STATUS_ACCESSIBLE (0x00000000) 230 #define MPI3_SAS_PHYINFO_STATUS_NOT_EXIST (0x40000000) 231 #define MPI3_SAS_PHYINFO_STATUS_VACANT (0x80000000) 232 233 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_MASK (0x18000000) 234 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_ACTIVE (0x00000000) 235 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_PARTIAL (0x08000000) 236 #define MPI3_SAS_PHYINFO_PHY_POWER_CONDITION_SLUMBER (0x10000000) 237 238 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_MASK (0x04000000) 239 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_CHANGED_SHIFT (26) 240 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_MASK (0x02000000) 241 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_PERSISTENT_SHIFT (25) 242 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_MASK (0x01000000) 243 #define MPI3_SAS_PHYINFO_REQUESTED_INSIDE_ZPSDS_SHIFT (24) 244 245 #define MPI3_SAS_PHYINFO_ZONE_GROUP_PERSISTENT (0x00400000) 246 #define MPI3_SAS_PHYINFO_INSIDE_ZPSDS_WITHIN (0x00200000) 247 #define MPI3_SAS_PHYINFO_ZONING_ENABLED (0x00100000) 248 249 #define MPI3_SAS_PHYINFO_REASON_MASK (0x000F0000) 250 #define MPI3_SAS_PHYINFO_REASON_UNKNOWN (0x00000000) 251 #define MPI3_SAS_PHYINFO_REASON_POWER_ON (0x00010000) 252 #define MPI3_SAS_PHYINFO_REASON_HARD_RESET (0x00020000) 253 #define MPI3_SAS_PHYINFO_REASON_SMP_PHY_CONTROL (0x00030000) 254 #define MPI3_SAS_PHYINFO_REASON_LOSS_OF_SYNC (0x00040000) 255 #define MPI3_SAS_PHYINFO_REASON_MULTIPLEXING_SEQ (0x00050000) 256 #define MPI3_SAS_PHYINFO_REASON_IT_NEXUS_LOSS_TIMER (0x00060000) 257 #define MPI3_SAS_PHYINFO_REASON_BREAK_TIMEOUT (0x00070000) 258 #define MPI3_SAS_PHYINFO_REASON_PHY_TEST_STOPPED (0x00080000) 259 #define MPI3_SAS_PHYINFO_REASON_EXP_REDUCED_FUNC (0x00090000) 260 261 #define MPI3_SAS_PHYINFO_SATA_PORT_ACTIVE (0x00004000) 262 #define MPI3_SAS_PHYINFO_SATA_PORT_SELECTOR_PRESENT (0x00002000) 263 #define MPI3_SAS_PHYINFO_VIRTUAL_PHY (0x00001000) 264 265 #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_MASK (0x00000F00) 266 #define MPI3_SAS_PHYINFO_PARTIAL_PATHWAY_TIME_SHIFT (8) 267 268 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_MASK (0x000000F0) 269 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_DIRECT (0x00000000) 270 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_SUBTRACTIVE (0x00000010) 271 #define MPI3_SAS_PHYINFO_ROUTING_ATTRIBUTE_TABLE (0x00000020) 272 273 /**** Defines for the ProgrammedLinkRate field ****/ 274 #define MPI3_SAS_PRATE_MAX_RATE_MASK (0xF0) 275 #define MPI3_SAS_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00) 276 #define MPI3_SAS_PRATE_MAX_RATE_1_5 (0x80) 277 #define MPI3_SAS_PRATE_MAX_RATE_3_0 (0x90) 278 #define MPI3_SAS_PRATE_MAX_RATE_6_0 (0xA0) 279 #define MPI3_SAS_PRATE_MAX_RATE_12_0 (0xB0) 280 #define MPI3_SAS_PRATE_MAX_RATE_22_5 (0xC0) 281 #define MPI3_SAS_PRATE_MIN_RATE_MASK (0x0F) 282 #define MPI3_SAS_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00) 283 #define MPI3_SAS_PRATE_MIN_RATE_1_5 (0x08) 284 #define MPI3_SAS_PRATE_MIN_RATE_3_0 (0x09) 285 #define MPI3_SAS_PRATE_MIN_RATE_6_0 (0x0A) 286 #define MPI3_SAS_PRATE_MIN_RATE_12_0 (0x0B) 287 #define MPI3_SAS_PRATE_MIN_RATE_22_5 (0x0C) 288 289 /**** Defines for the HwLinkRate field ****/ 290 #define MPI3_SAS_HWRATE_MAX_RATE_MASK (0xF0) 291 #define MPI3_SAS_HWRATE_MAX_RATE_1_5 (0x80) 292 #define MPI3_SAS_HWRATE_MAX_RATE_3_0 (0x90) 293 #define MPI3_SAS_HWRATE_MAX_RATE_6_0 (0xA0) 294 #define MPI3_SAS_HWRATE_MAX_RATE_12_0 (0xB0) 295 #define MPI3_SAS_HWRATE_MAX_RATE_22_5 (0xC0) 296 #define MPI3_SAS_HWRATE_MIN_RATE_MASK (0x0F) 297 #define MPI3_SAS_HWRATE_MIN_RATE_1_5 (0x08) 298 #define MPI3_SAS_HWRATE_MIN_RATE_3_0 (0x09) 299 #define MPI3_SAS_HWRATE_MIN_RATE_6_0 (0x0A) 300 #define MPI3_SAS_HWRATE_MIN_RATE_12_0 (0x0B) 301 #define MPI3_SAS_HWRATE_MIN_RATE_22_5 (0x0C) 302 303 /**** Defines for the Slot field ****/ 304 #define MPI3_SLOT_INVALID (0xFFFF) 305 306 /**** Defines for the SlotIndex field ****/ 307 #define MPI3_SLOT_INDEX_INVALID (0xFFFF) 308 309 /**** Defines for the LinkChangeCount fields ****/ 310 #define MPI3_LINK_CHANGE_COUNT_INVALID (0xFFFF) 311 312 /**** Defines for the RateChangeCount fields ****/ 313 #define MPI3_RATE_CHANGE_COUNT_INVALID (0xFFFF) 314 315 /**** Defines for the Temp Sensor Location field ****/ 316 #define MPI3_TEMP_SENSOR_LOCATION_INTERNAL (0x0) 317 #define MPI3_TEMP_SENSOR_LOCATION_INLET (0x1) 318 #define MPI3_TEMP_SENSOR_LOCATION_OUTLET (0x2) 319 #define MPI3_TEMP_SENSOR_LOCATION_DRAM (0x3) 320 321 /***************************************************************************** 322 * Manufacturing Configuration Pages * 323 ****************************************************************************/ 324 325 #define MPI3_MFGPAGE_VENDORID_BROADCOM (0x1000) 326 327 /* MPI v3.0 SAS Products */ 328 #define MPI3_MFGPAGE_DEVID_SAS4116 (0x00A5) 329 #define MPI3_MFGPAGE_DEVID_SAS5116_MPI (0x00B3) 330 #define MPI3_MFGPAGE_DEVID_SAS5116_NVME (0x00B4) 331 #define MPI3_MFGPAGE_DEVID_SAS5116_MPI_NS (0x00B5) 332 #define MPI3_MFGPAGE_DEVID_SAS5116_NVME_NS (0x00B6) 333 #define MPI3_MFGPAGE_DEVID_SAS5116_PCIE_SWITCH (0x00B8) 334 335 /***************************************************************************** 336 * Manufacturing Page 0 * 337 ****************************************************************************/ 338 typedef struct _MPI3_MAN_PAGE0 339 { 340 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 341 U8 ChipRevision[8]; /* 0x08 */ 342 U8 ChipName[32]; /* 0x10 */ 343 U8 BoardName[32]; /* 0x30 */ 344 U8 BoardAssembly[32]; /* 0x50 */ 345 U8 BoardTracerNumber[32]; /* 0x70 */ 346 U32 BoardPower; /* 0x90 */ 347 U32 Reserved94; /* 0x94 */ 348 U32 Reserved98; /* 0x98 */ 349 U8 OEM; /* 0x9C */ 350 U8 ProfileIdentifier; /* 0x9D */ 351 U16 Flags; /* 0x9E */ 352 U8 BoardMfgDay; /* 0xA0 */ 353 U8 BoardMfgMonth; /* 0xA1 */ 354 U16 BoardMfgYear; /* 0xA2 */ 355 U8 BoardReworkDay; /* 0xA4 */ 356 U8 BoardReworkMonth; /* 0xA5 */ 357 U16 BoardReworkYear; /* 0xA6 */ 358 U8 BoardRevision[8]; /* 0xA8 */ 359 U8 EPackFRU[16]; /* 0xB0 */ 360 U8 ProductName[256]; /* 0xC0 */ 361 } MPI3_MAN_PAGE0, MPI3_POINTER PTR_MPI3_MAN_PAGE0, 362 Mpi3ManPage0_t, MPI3_POINTER pMpi3ManPage0_t; 363 364 /**** Defines for the PageVersion field ****/ 365 #define MPI3_MAN0_PAGEVERSION (0x00) 366 367 /**** Defines for the Flags field ****/ 368 #define MPI3_MAN0_FLAGS_SWITCH_PRESENT (0x0002) 369 #define MPI3_MAN0_FLAGS_EXPANDER_PRESENT (0x0001) 370 371 /***************************************************************************** 372 * Manufacturing Page 1 * 373 ****************************************************************************/ 374 375 #define MPI3_MAN1_VPD_SIZE (512) 376 377 typedef struct _MPI3_MAN_PAGE1 378 { 379 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 380 U32 Reserved08[2]; /* 0x08 */ 381 U8 VPD[MPI3_MAN1_VPD_SIZE]; /* 0x10 */ 382 } MPI3_MAN_PAGE1, MPI3_POINTER PTR_MPI3_MAN_PAGE1, 383 Mpi3ManPage1_t, MPI3_POINTER pMpi3ManPage1_t; 384 385 /**** Defines for the PageVersion field ****/ 386 #define MPI3_MAN1_PAGEVERSION (0x00) 387 388 389 /***************************************************************************** 390 * Manufacturing Page 2 * 391 ****************************************************************************/ 392 393 typedef struct _MPI3_MAN_PAGE2 394 { 395 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 396 U8 Flags; /* 0x08 */ 397 U8 Reserved09[3]; /* 0x09 */ 398 U32 Reserved0C[3]; /* 0x0C */ 399 U8 OEMBoardTracerNumber[32]; /* 0x18 */ 400 } MPI3_MAN_PAGE2, MPI3_POINTER PTR_MPI3_MAN_PAGE2, 401 Mpi3ManPage2_t, MPI3_POINTER pMpi3ManPage2_t; 402 403 /**** Defines for the PageVersion field ****/ 404 #define MPI3_MAN2_PAGEVERSION (0x00) 405 406 /**** Defines for the Flags field ****/ 407 #define MPI3_MAN2_FLAGS_TRACER_PRESENT (0x01) 408 409 /***************************************************************************** 410 * Manufacturing Page 5 * 411 ****************************************************************************/ 412 typedef struct _MPI3_MAN5_PHY_ENTRY 413 { 414 U64 IOC_WWID; /* 0x00 */ 415 U64 DeviceName; /* 0x08 */ 416 U64 SATA_WWID; /* 0x10 */ 417 } MPI3_MAN5_PHY_ENTRY, MPI3_POINTER PTR_MPI3_MAN5_PHY_ENTRY, 418 Mpi3Man5PhyEntry_t, MPI3_POINTER pMpi3Man5PhyEntry_t; 419 420 #ifndef MPI3_MAN5_PHY_MAX 421 #define MPI3_MAN5_PHY_MAX (1) 422 #endif /* MPI3_MAN5_PHY_MAX */ 423 424 typedef struct _MPI3_MAN_PAGE5 425 { 426 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 427 U8 NumPhys; /* 0x08 */ 428 U8 Reserved09[3]; /* 0x09 */ 429 U32 Reserved0C; /* 0x0C */ 430 MPI3_MAN5_PHY_ENTRY Phy[MPI3_MAN5_PHY_MAX]; /* 0x10 */ 431 } MPI3_MAN_PAGE5, MPI3_POINTER PTR_MPI3_MAN_PAGE5, 432 Mpi3ManPage5_t, MPI3_POINTER pMpi3ManPage5_t; 433 434 /**** Defines for the PageVersion field ****/ 435 #define MPI3_MAN5_PAGEVERSION (0x00) 436 437 /***************************************************************************** 438 * Manufacturing Page 6 * 439 ****************************************************************************/ 440 typedef struct _MPI3_MAN6_GPIO_ENTRY 441 { 442 U8 FunctionCode; /* 0x00 */ 443 U8 FunctionFlags; /* 0x01 */ 444 U16 Flags; /* 0x02 */ 445 U8 Param1; /* 0x04 */ 446 U8 Param2; /* 0x05 */ 447 U16 Reserved06; /* 0x06 */ 448 U32 Param3; /* 0x08 */ 449 } MPI3_MAN6_GPIO_ENTRY, MPI3_POINTER PTR_MPI3_MAN6_GPIO_ENTRY, 450 Mpi3Man6GpioEntry_t, MPI3_POINTER pMpi3Man6GpioEntry_t; 451 452 /**** Defines for the FunctionCode field ****/ 453 #define MPI3_MAN6_GPIO_FUNCTION_GENERIC (0x00) 454 #define MPI3_MAN6_GPIO_FUNCTION_ALTERNATE (0x01) 455 #define MPI3_MAN6_GPIO_FUNCTION_EXT_INTERRUPT (0x02) 456 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_ACTIVITY (0x03) 457 #define MPI3_MAN6_GPIO_FUNCTION_OVER_TEMPERATURE (0x04) 458 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_GREEN (0x05) 459 #define MPI3_MAN6_GPIO_FUNCTION_PORT_STATUS_YELLOW (0x06) 460 #define MPI3_MAN6_GPIO_FUNCTION_CABLE_MANAGEMENT (0x07) 461 #define MPI3_MAN6_GPIO_FUNCTION_BKPLANE_MGMT_TYPE (0x08) 462 #define MPI3_MAN6_GPIO_FUNCTION_ISTWI_RESET (0x0A) 463 #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET (0x0B) 464 #define MPI3_MAN6_GPIO_FUNCTION_GLOBAL_FAULT (0x0C) 465 #define MPI3_MAN6_GPIO_FUNCTION_PBLP_STATUS_CHANGE (0x0D) 466 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_ONLINE (0x0E) 467 #define MPI3_MAN6_GPIO_FUNCTION_EPACK_FAULT (0x0F) 468 #define MPI3_MAN6_GPIO_FUNCTION_CTRL_TYPE (0x10) 469 #define MPI3_MAN6_GPIO_FUNCTION_LICENSE (0x11) 470 #define MPI3_MAN6_GPIO_FUNCTION_REFCLK_CONTROL (0x12) 471 #define MPI3_MAN6_GPIO_FUNCTION_BACKEND_PCIE_RESET_CLAMP (0x13) 472 #define MPI3_MAN6_GPIO_FUNCTION_AUXILIARY_POWER (0x14) 473 #define MPI3_MAN6_GPIO_FUNCTION_RAID_DATA_CACHE_DIRTY (0x15) 474 #define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_CONTROL (0x16) 475 #define MPI3_MAN6_GPIO_FUNCTION_BOARD_FAN_FAULT (0x17) 476 #define MPI3_MAN6_GPIO_FUNCTION_POWER_BRAKE (0x18) 477 #define MPI3_MAN6_GPIO_FUNCTION_MGMT_CONTROLLER_RESET (0x19) 478 479 /**** Defines for FunctionFlags when FunctionCode is ISTWI_RESET ****/ 480 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_MASK (0x01) 481 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_ISTWI (0x00) 482 #define MPI3_MAN6_GPIO_ISTWI_RESET_FUNCTIONFLAGS_DEVSELECT_RECEPTACLEID (0x01) 483 484 /**** Defines for Param1 (Flags) when FunctionCode is EXT_INTERRUPT ****/ 485 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_MASK (0xF0) 486 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_GENERIC (0x00) 487 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_CABLE_MGMT (0x10) 488 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_SOURCE_ACTIVE_CABLE_OVERCURRENT (0x20) 489 490 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_MASK (0x01) 491 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_EDGE (0x00) 492 #define MPI3_MAN6_GPIO_EXTINT_PARAM1_FLAGS_TRIGGER_LEVEL (0x01) 493 494 /**** Defines for Param1 (PHY STATE) when FunctionCode is PORT_STATUS_GREEN ****/ 495 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ALL_UP (0x00) 496 #define MPI3_MAN6_GPIO_PORT_GREEN_PARAM1_PHY_STATUS_ONE_OR_MORE_UP (0x01) 497 498 /**** Defines for Param1 (INTERFACE_SIGNAL) when FunctionCode is CABLE_MANAGEMENT ****/ 499 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_MODULE_PRESENT (0x00) 500 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_ACTIVE_CABLE_ENABLE (0x01) 501 #define MPI3_MAN6_GPIO_CABLE_MGMT_PARAM1_INTERFACE_CABLE_MGMT_ENABLE (0x02) 502 503 /**** Defines for Param1 (LICENSE_TYPE) when FunctionCode is LICENSE ****/ 504 #define MPI3_MAN6_GPIO_LICENSE_PARAM1_TYPE_IBUTTON (0x00) 505 506 507 /**** Defines for the Flags field ****/ 508 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_MASK (0x0100) 509 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_FAST_EDGE (0x0100) 510 #define MPI3_MAN6_GPIO_FLAGS_SLEW_RATE_SLOW_EDGE (0x0000) 511 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_MASK (0x00C0) 512 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_100OHM (0x0000) 513 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_66OHM (0x0040) 514 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_50OHM (0x0080) 515 #define MPI3_MAN6_GPIO_FLAGS_DRIVE_STRENGTH_33OHM (0x00C0) 516 #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_MASK (0x0030) 517 #define MPI3_MAN6_GPIO_FLAGS_ALT_DATA_SEL_SHIFT (4) 518 #define MPI3_MAN6_GPIO_FLAGS_ACTIVE_HIGH (0x0008) 519 #define MPI3_MAN6_GPIO_FLAGS_BI_DIR_ENABLED (0x0004) 520 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_MASK (0x0003) 521 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_INPUT (0x0000) 522 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_DRAIN_OUTPUT (0x0001) 523 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_OPEN_SOURCE_OUTPUT (0x0002) 524 #define MPI3_MAN6_GPIO_FLAGS_DIRECTION_PUSH_PULL_OUTPUT (0x0003) 525 526 #ifndef MPI3_MAN6_GPIO_MAX 527 #define MPI3_MAN6_GPIO_MAX (1) 528 #endif /* MPI3_MAN6_GPIO_MAX */ 529 530 typedef struct _MPI3_MAN_PAGE6 531 { 532 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 533 U16 Flags; /* 0x08 */ 534 U16 Reserved0A; /* 0x0A */ 535 U8 NumGPIO; /* 0x0C */ 536 U8 Reserved0D[3]; /* 0x0D */ 537 MPI3_MAN6_GPIO_ENTRY GPIO[MPI3_MAN6_GPIO_MAX]; /* 0x10 */ 538 } MPI3_MAN_PAGE6, MPI3_POINTER PTR_MPI3_MAN_PAGE6, 539 Mpi3ManPage6_t, MPI3_POINTER pMpi3ManPage6_t; 540 541 /**** Defines for the PageVersion field ****/ 542 #define MPI3_MAN6_PAGEVERSION (0x00) 543 544 /**** Defines for the Flags field ****/ 545 #define MPI3_MAN6_FLAGS_HEARTBEAT_LED_DISABLED (0x0001) 546 547 /***************************************************************************** 548 * Manufacturing Page 7 * 549 ****************************************************************************/ 550 typedef struct _MPI3_MAN7_RECEPTACLE_INFO 551 { 552 U32 Name[4]; /* 0x00 */ 553 U8 Location; /* 0x10 */ 554 U8 ConnectorType; /* 0x11 */ 555 U8 PEDClk; /* 0x12 */ 556 U8 ConnectorID; /* 0x13 */ 557 U32 Reserved14; /* 0x14 */ 558 } MPI3_MAN7_RECEPTACLE_INFO, MPI3_POINTER PTR_MPI3_MAN7_RECEPTACLE_INFO, 559 Mpi3Man7ReceptacleInfo_t, MPI3_POINTER pMpi3Man7ReceptacleInfo_t; 560 561 /**** Defines for Location field ****/ 562 #define MPI3_MAN7_LOCATION_UNKNOWN (0x00) 563 #define MPI3_MAN7_LOCATION_INTERNAL (0x01) 564 #define MPI3_MAN7_LOCATION_EXTERNAL (0x02) 565 #define MPI3_MAN7_LOCATION_VIRTUAL (0x03) 566 #define MPI3_MAN7_LOCATION_HOST (0x04) 567 568 /**** Defines for ConnectorType - Use definitions from SES-4 ****/ 569 #define MPI3_MAN7_CONNECTOR_TYPE_NO_INFO (0x00) 570 571 /**** Defines for PEDClk field ****/ 572 #define MPI3_MAN7_PEDCLK_ROUTING_MASK (0x10) 573 #define MPI3_MAN7_PEDCLK_ROUTING_DIRECT (0x00) 574 #define MPI3_MAN7_PEDCLK_ROUTING_CLOCK_BUFFER (0x10) 575 #define MPI3_MAN7_PEDCLK_ID_MASK (0x0F) 576 577 #ifndef MPI3_MAN7_RECEPTACLE_INFO_MAX 578 #define MPI3_MAN7_RECEPTACLE_INFO_MAX (1) 579 #endif /* MPI3_MAN7_RECEPTACLE_INFO_MAX */ 580 581 typedef struct _MPI3_MAN_PAGE7 582 { 583 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 584 U32 Flags; /* 0x08 */ 585 U8 NumReceptacles; /* 0x0C */ 586 U8 Reserved0D[3]; /* 0x0D */ 587 U32 EnclosureName[4]; /* 0x10 */ 588 MPI3_MAN7_RECEPTACLE_INFO ReceptacleInfo[MPI3_MAN7_RECEPTACLE_INFO_MAX]; /* 0x20 */ /* variable length array */ 589 } MPI3_MAN_PAGE7, MPI3_POINTER PTR_MPI3_MAN_PAGE7, 590 Mpi3ManPage7_t, MPI3_POINTER pMpi3ManPage7_t; 591 592 /**** Defines for the PageVersion field ****/ 593 #define MPI3_MAN7_PAGEVERSION (0x00) 594 595 /**** Defines for Flags field ****/ 596 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_MASK (0x01) 597 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_0 (0x00) 598 #define MPI3_MAN7_FLAGS_BASE_ENCLOSURE_LEVEL_1 (0x01) 599 600 601 /***************************************************************************** 602 * Manufacturing Page 8 * 603 ****************************************************************************/ 604 605 typedef struct _MPI3_MAN8_PHY_INFO 606 { 607 U8 ReceptacleID; /* 0x00 */ 608 U8 ConnectorLane; /* 0x01 */ 609 U16 Reserved02; /* 0x02 */ 610 U16 Slotx1; /* 0x04 */ 611 U16 Slotx2; /* 0x06 */ 612 U16 Slotx4; /* 0x08 */ 613 U16 Reserved0A; /* 0x0A */ 614 U32 Reserved0C; /* 0x0C */ 615 } MPI3_MAN8_PHY_INFO, MPI3_POINTER PTR_MPI3_MAN8_PHY_INFO, 616 Mpi3Man8PhyInfo_t, MPI3_POINTER pMpi3Man8PhyInfo_t; 617 618 /**** Defines for ReceptacleID field ****/ 619 #define MPI3_MAN8_PHY_INFO_RECEPTACLE_ID_NOT_ASSOCIATED (0xFF) 620 621 /**** Defines for ConnectorLane field ****/ 622 #define MPI3_MAN8_PHY_INFO_CONNECTOR_LANE_NOT_ASSOCIATED (0xFF) 623 624 #ifndef MPI3_MAN8_PHY_INFO_MAX 625 #define MPI3_MAN8_PHY_INFO_MAX (1) 626 #endif /* MPI3_MAN8_PHY_INFO_MAX */ 627 628 typedef struct _MPI3_MAN_PAGE8 629 { 630 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 631 U32 Reserved08; /* 0x08 */ 632 U8 NumPhys; /* 0x0C */ 633 U8 Reserved0D[3]; /* 0x0D */ 634 MPI3_MAN8_PHY_INFO PhyInfo[MPI3_MAN8_PHY_INFO_MAX]; /* 0x10 */ /* variable length array */ 635 } MPI3_MAN_PAGE8, MPI3_POINTER PTR_MPI3_MAN_PAGE8, 636 Mpi3ManPage8_t, MPI3_POINTER pMpi3ManPage8_t; 637 638 /**** Defines for the PageVersion field ****/ 639 #define MPI3_MAN8_PAGEVERSION (0x00) 640 641 /***************************************************************************** 642 * Manufacturing Page 9 * 643 ****************************************************************************/ 644 typedef struct _MPI3_MAN9_RSRC_ENTRY 645 { 646 U32 Maximum; /* 0x00 */ 647 U32 Decrement; /* 0x04 */ 648 U32 Minimum; /* 0x08 */ 649 U32 Actual; /* 0x0C */ 650 } MPI3_MAN9_RSRC_ENTRY, MPI3_POINTER PTR_MPI3_MAN9_RSRC_ENTRY, 651 Mpi3Man9RsrcEntry_t, MPI3_POINTER pMpi3Man9RsrcEntry_t; 652 653 typedef enum _MPI3_MAN9_RESOURCES 654 { 655 MPI3_MAN9_RSRC_OUTSTANDING_REQS = 0, 656 MPI3_MAN9_RSRC_TARGET_CMDS = 1, 657 MPI3_MAN9_RSRC_RESERVED02 = 2, 658 MPI3_MAN9_RSRC_NVME = 3, 659 MPI3_MAN9_RSRC_INITIATORS = 4, 660 MPI3_MAN9_RSRC_VDS = 5, 661 MPI3_MAN9_RSRC_ENCLOSURES = 6, 662 MPI3_MAN9_RSRC_ENCLOSURE_PHYS = 7, 663 MPI3_MAN9_RSRC_EXPANDERS = 8, 664 MPI3_MAN9_RSRC_PCIE_SWITCHES = 9, 665 MPI3_MAN9_RSRC_RESERVED10 = 10, 666 MPI3_MAN9_RSRC_HOST_PD_DRIVES = 11, 667 MPI3_MAN9_RSRC_ADV_HOST_PD_DRIVES = 12, 668 MPI3_MAN9_RSRC_RAID_PD_DRIVES = 13, 669 MPI3_MAN9_RSRC_DRV_DIAG_BUF = 14, 670 MPI3_MAN9_RSRC_NAMESPACE_COUNT = 15, 671 MPI3_MAN9_RSRC_NUM_RESOURCES 672 } MPI3_MAN9_RESOURCES; 673 674 #define MPI3_MAN9_MIN_OUTSTANDING_REQS (1) 675 #define MPI3_MAN9_MAX_OUTSTANDING_REQS (65000) 676 677 #define MPI3_MAN9_MIN_TARGET_CMDS (0) 678 #define MPI3_MAN9_MAX_TARGET_CMDS (65535) 679 680 #define MPI3_MAN9_MIN_NVME_TARGETS (0) 681 /* Max NVMe Targets is product specific */ 682 683 #define MPI3_MAN9_MIN_INITIATORS (0) 684 /* Max Initiators is product specific */ 685 686 #define MPI3_MAN9_MIN_VDS (0) 687 /* Max VDs is product specific */ 688 689 #define MPI3_MAN9_MIN_ENCLOSURES (1) 690 #define MPI3_MAN9_MAX_ENCLOSURES (65535) 691 692 #define MPI3_MAN9_MIN_ENCLOSURE_PHYS (0) 693 /* Max Enclosure Phys is product specific */ 694 695 #define MPI3_MAN9_MIN_EXPANDERS (0) 696 #define MPI3_MAN9_MAX_EXPANDERS (65535) 697 698 #define MPI3_MAN9_MIN_PCIE_SWITCHES (0) 699 /* Max PCIe Switches is product specific */ 700 701 #define MPI3_MAN9_MIN_HOST_PD_DRIVES (0) 702 /* Max Host PD Drives is product specific */ 703 704 #define MPI3_MAN9_ADV_HOST_PD_DRIVES (0) 705 /* Max Advanced Host PD Drives is product specific */ 706 707 #define MPI3_MAN9_RAID_PD_DRIVES (0) 708 /* Max RAID PD Drives is product specific */ 709 710 #define MPI3_MAN9_DRIVER_DIAG_BUFFER (0) 711 /* Max Driver Diag Buffer is product specific */ 712 713 #define MPI3_MAN9_MIN_NAMESPACE_COUNT (1) 714 715 #define MPI3_MAN9_MIN_EXPANDERS (0) 716 #define MPI3_MAN9_MAX_EXPANDERS (65535) 717 718 719 typedef struct _MPI3_MAN_PAGE9 720 { 721 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 722 U8 NumResources; /* 0x08 */ 723 U8 Reserved09; /* 0x09 */ 724 U16 Reserved0A; /* 0x0A */ 725 U32 Reserved0C; /* 0x0C */ 726 U32 Reserved10; /* 0x10 */ 727 U32 Reserved14; /* 0x14 */ 728 U32 Reserved18; /* 0x18 */ 729 U32 Reserved1C; /* 0x1C */ 730 MPI3_MAN9_RSRC_ENTRY Resource[MPI3_MAN9_RSRC_NUM_RESOURCES]; /* 0x20 */ 731 } MPI3_MAN_PAGE9, MPI3_POINTER PTR_MPI3_MAN_PAGE9, 732 Mpi3ManPage9_t, MPI3_POINTER pMpi3ManPage9_t; 733 734 /**** Defines for the PageVersion field ****/ 735 #define MPI3_MAN9_PAGEVERSION (0x00) 736 737 /***************************************************************************** 738 * Manufacturing Page 10 * 739 ****************************************************************************/ 740 typedef struct _MPI3_MAN10_ISTWI_CTRLR_ENTRY 741 { 742 U16 TargetAddress; /* 0x00 */ 743 U16 Flags; /* 0x02 */ 744 U8 SCLLowOverride; /* 0x04 */ 745 U8 SCLHighOverride; /* 0x05 */ 746 U16 Reserved06; /* 0x06 */ 747 } MPI3_MAN10_ISTWI_CTRLR_ENTRY, MPI3_POINTER PTR_MPI3_MAN10_ISTWI_CTRLR_ENTRY, 748 Mpi3Man10IstwiCtrlrEntry_t, MPI3_POINTER pMpi3Man10IstwiCtrlrEntry_t; 749 750 /**** Defines for the Flags field ****/ 751 752 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_MASK (0xC000) 753 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_SHIFT (14) 754 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_50_NS (0x0000) 755 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_10_NS (0x4000) 756 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_5_NS (0x8000) 757 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I2C_GLICH_FLTR_0_NS (0xC000) 758 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_MASK (0x3000) 759 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_SHIFT (12) 760 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_I2C (0x0000) 761 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_I3C (0x1000) 762 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_TYPE_AUTO (0x2000) 763 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_MASK (0x0E00) 764 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_SHIFT (9) 765 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_12_5_MHZ (0x0000) 766 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_8_MHZ (0x0200) 767 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_6_MHZ (0x0400) 768 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_4_MHZ (0x0600) 769 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_I3C_MAX_DATA_RATE_2_MHZ (0x0800) 770 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_MASK (0x000C) 771 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_SHIFT (0) 772 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_100_KHZ (0x0000) 773 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_BUS_SPEED_400_KHZ (0x0004) 774 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_TARGET_ENABLED (0x0002) 775 #define MPI3_MAN10_ISTWI_CTRLR_FLAGS_INITIATOR_ENABLED (0x0001) 776 777 #ifndef MPI3_MAN10_ISTWI_CTRLR_MAX 778 #define MPI3_MAN10_ISTWI_CTRLR_MAX (1) 779 #endif /* MPI3_MAN10_ISTWI_CTRLR_MAX */ 780 781 typedef struct _MPI3_MAN_PAGE10 782 { 783 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 784 U32 Reserved08; /* 0x08 */ 785 U8 NumISTWICtrl; /* 0x0C */ 786 U8 Reserved0D[3]; /* 0x0D */ 787 MPI3_MAN10_ISTWI_CTRLR_ENTRY ISTWIController[MPI3_MAN10_ISTWI_CTRLR_MAX]; /* 0x10 */ 788 } MPI3_MAN_PAGE10, MPI3_POINTER PTR_MPI3_MAN_PAGE10, 789 Mpi3ManPage10_t, MPI3_POINTER pMpi3ManPage10_t; 790 791 /**** Defines for the PageVersion field ****/ 792 #define MPI3_MAN10_PAGEVERSION (0x00) 793 794 /***************************************************************************** 795 * Manufacturing Page 11 * 796 ****************************************************************************/ 797 typedef struct _MPI3_MAN11_MUX_DEVICE_FORMAT 798 { 799 U8 MaxChannel; /* 0x00 */ 800 U8 Reserved01[3]; /* 0x01 */ 801 U32 Reserved04; /* 0x04 */ 802 } MPI3_MAN11_MUX_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_MUX_DEVICE_FORMAT, 803 Mpi3Man11MuxDeviceFormat_t, MPI3_POINTER pMpi3Man11MuxDeviceFormat_t; 804 805 typedef struct _MPI3_MAN11_TEMP_SENSOR_DEVICE_FORMAT 806 { 807 U8 Type; /* 0x00 */ 808 U8 Reserved01[3]; /* 0x01 */ 809 U8 TempChannel[4]; /* 0x04 */ 810 } MPI3_MAN11_TEMP_SENSOR_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_TEMP_SENSOR_DEVICE_FORMAT, 811 Mpi3Man11TempSensorDeviceFormat_t, MPI3_POINTER pMpi3Man11TempSensorDeviceFormat_t; 812 813 /**** Defines for the Type field ****/ 814 #define MPI3_MAN11_TEMP_SENSOR_TYPE_MAX6654 (0x00) 815 #define MPI3_MAN11_TEMP_SENSOR_TYPE_EMC1442 (0x01) 816 #define MPI3_MAN11_TEMP_SENSOR_TYPE_ADT7476 (0x02) 817 #define MPI3_MAN11_TEMP_SENSOR_TYPE_SE97B (0x03) 818 819 /**** Define for the TempChannel field ****/ 820 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_MASK (0xE0) 821 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_LOCATION_SHIFT (5) 822 /**** for the Location field values - use MPI3_TEMP_SENSOR_LOCATION_ defines ****/ 823 #define MPI3_MAN11_TEMP_SENSOR_CHANNEL_ENABLED (0x01) 824 825 826 typedef struct _MPI3_MAN11_SEEPROM_DEVICE_FORMAT 827 { 828 U8 Size; /* 0x00 */ 829 U8 PageWriteSize; /* 0x01 */ 830 U16 Reserved02; /* 0x02 */ 831 U32 Reserved04; /* 0x04 */ 832 } MPI3_MAN11_SEEPROM_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_SEEPROM_DEVICE_FORMAT, 833 Mpi3Man11SeepromDeviceFormat_t, MPI3_POINTER pMpi3Man11SeepromDeviceFormat_t; 834 835 /**** Defines for the Size field ****/ 836 #define MPI3_MAN11_SEEPROM_SIZE_1KBITS (0x01) 837 #define MPI3_MAN11_SEEPROM_SIZE_2KBITS (0x02) 838 #define MPI3_MAN11_SEEPROM_SIZE_4KBITS (0x03) 839 #define MPI3_MAN11_SEEPROM_SIZE_8KBITS (0x04) 840 #define MPI3_MAN11_SEEPROM_SIZE_16KBITS (0x05) 841 #define MPI3_MAN11_SEEPROM_SIZE_32KBITS (0x06) 842 #define MPI3_MAN11_SEEPROM_SIZE_64KBITS (0x07) 843 #define MPI3_MAN11_SEEPROM_SIZE_128KBITS (0x08) 844 845 typedef struct _MPI3_MAN11_DDR_SPD_DEVICE_FORMAT 846 { 847 U8 Channel; /* 0x00 */ 848 U8 Reserved01[3]; /* 0x01 */ 849 U32 Reserved04; /* 0x04 */ 850 } MPI3_MAN11_DDR_SPD_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_DDR_SPD_DEVICE_FORMAT, 851 Mpi3Man11DdrSpdDeviceFormat_t, MPI3_POINTER pMpi3Man11DdrSpdDeviceFormat_t; 852 853 typedef struct _MPI3_MAN11_CABLE_MGMT_DEVICE_FORMAT 854 { 855 U8 Type; /* 0x00 */ 856 U8 ReceptacleID; /* 0x01 */ 857 U16 Reserved02; /* 0x02 */ 858 U32 Reserved04; /* 0x04 */ 859 } MPI3_MAN11_CABLE_MGMT_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_CABLE_MGMT_DEVICE_FORMAT, 860 Mpi3Man11CableMgmtDeviceFormat_t, MPI3_POINTER pMpi3Man11CableMgmtDeviceFormat_t; 861 862 /**** Defines for the Type field ****/ 863 #define MPI3_MAN11_CABLE_MGMT_TYPE_SFF_8636 (0x00) 864 865 typedef struct _MPI3_MAN11_BKPLANE_SPEC_UBM_FORMAT 866 { 867 U16 Flags; /* 0x00 */ 868 U16 Reserved02; /* 0x02 */ 869 } MPI3_MAN11_BKPLANE_SPEC_UBM_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_BKPLANE_SPEC_UBM_FORMAT, 870 Mpi3Man11BkplaneSpecUBMFormat_t, MPI3_POINTER pMpi3Man11BkplaneSpecUBMFormat_t; 871 872 /**** Defines for the Flags field ****/ 873 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0200) 874 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_FORCE_POLLING (0x0100) 875 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_MASK (0x00F0) 876 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_MAX_FRU_SHIFT (4) 877 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_MASK (0x000F) 878 #define MPI3_MAN11_BKPLANE_UBM_FLAGS_POLL_INTERVAL_SHIFT (0) 879 880 typedef struct _MPI3_MAN11_BKPLANE_SPEC_NON_UBM_FORMAT 881 { 882 U16 Flags; /* 0x00 */ 883 U8 Reserved02; /* 0x02 */ 884 U8 Type; /* 0x03 */ 885 } MPI3_MAN11_BKPLANE_SPEC_NON_UBM_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_BKPLANE_SPEC_NON_UBM_FORMAT, 886 Mpi3Man11BkplaneSpecNonUBMFormat_t, MPI3_POINTER pMpi3Man11BkplaneSpecNonUBMFormat_t; 887 888 /**** Defines for the Flags field ****/ 889 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_MASK (0xF000) 890 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_GROUP_SHIFT (12) 891 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_MASK (0x0600) 892 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_SHIFT (9) 893 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_DEVICE_PRESENT (0x0000) 894 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_ALWAYS_ENABLED (0x0200) 895 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_REFCLK_POLICY_SRIS (0x0400) 896 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_MASK (0x00C0) 897 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_SHIFT (6) 898 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_4 (0x0000) 899 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_2 (0x0040) 900 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_LINKWIDTH_1 (0x0080) 901 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_MASK (0x0030) 902 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_SHIFT (4) 903 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_GPIO (0x0000) 904 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_PRESENCE_DETECT_REG (0x0010) 905 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_MASK (0x000F) 906 #define MPI3_MAN11_BKPLANE_NON_UBM_FLAGS_POLL_INTERVAL_SHIFT (0) 907 908 /**** Defines for the Type field ****/ 909 #define MPI3_MAN11_BKPLANE_NON_UBM_TYPE_VPP (0x00) 910 911 typedef union _MPI3_MAN11_BKPLANE_SPEC_FORMAT 912 { 913 MPI3_MAN11_BKPLANE_SPEC_UBM_FORMAT Ubm; 914 MPI3_MAN11_BKPLANE_SPEC_NON_UBM_FORMAT NonUbm; 915 } MPI3_MAN11_BKPLANE_SPEC_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_BKPLANE_SPEC_FORMAT, 916 Mpi3Man11BkplaneSpecFormat_t, MPI3_POINTER pMpi3Man11BkplaneSpecFormat_t; 917 918 typedef struct _MPI3_MAN11_BKPLANE_MGMT_DEVICE_FORMAT 919 { 920 U8 Type; /* 0x00 */ 921 U8 ReceptacleID; /* 0x01 */ 922 U8 ResetInfo; /* 0x02 */ 923 U8 Reserved03; /* 0x03 */ 924 MPI3_MAN11_BKPLANE_SPEC_FORMAT BackplaneMgmtSpecific; /* 0x04 */ 925 } MPI3_MAN11_BKPLANE_MGMT_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_BKPLANE_MGMT_DEVICE_FORMAT, 926 Mpi3Man11BkplaneMgmtDeviceFormat_t, MPI3_POINTER pMpi3Man11BkplaneMgmtDeviceFormat_t; 927 928 /**** Defines for the Type field ****/ 929 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_UBM (0x00) 930 #define MPI3_MAN11_BKPLANE_MGMT_TYPE_NON_UBM (0x01) 931 932 /**** Defines for the ResetInfo field ****/ 933 #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_MASK (0xF0) 934 #define MPI3_MAN11_BACKPLANE_RESETINFO_ASSERT_TIME_SHIFT (4) 935 #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_MASK (0x0F) 936 #define MPI3_MAN11_BACKPLANE_RESETINFO_READY_TIME_SHIFT (0) 937 938 typedef struct _MPI3_MAN11_GAS_GAUGE_DEVICE_FORMAT 939 { 940 U8 Type; /* 0x00 */ 941 U8 Reserved01[3]; /* 0x01 */ 942 U32 Reserved04; /* 0x04 */ 943 } MPI3_MAN11_GAS_GAUGE_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_GAS_GAUGE_DEVICE_FORMAT, 944 Mpi3Man11GasGaugeDeviceFormat_t, MPI3_POINTER pMpi3Man11GasGaugeDeviceFormat_t; 945 946 /**** Defines for the Type field ****/ 947 #define MPI3_MAN11_GAS_GAUGE_TYPE_STANDARD (0x00) 948 949 typedef struct _MPI3_MAN11_MGMT_CTRLR_DEVICE_FORMAT 950 { 951 U32 Reserved00; /* 0x00 */ 952 U32 Reserved04; /* 0x04 */ 953 } MPI3_MAN11_MGMT_CTRLR_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_MGMT_CTRLR_DEVICE_FORMAT, 954 Mpi3Man11MgmtCtrlrDeviceFormat_t, MPI3_POINTER pMpi3Man11MgmtCtrlrDeviceFormat_t; 955 956 typedef struct _MPI3_MAN11_BOARD_FAN_DEVICE_FORMAT 957 { 958 U8 Flags; /* 0x00 */ 959 U8 Reserved01; /* 0x01 */ 960 U8 MinFanSpeed; /* 0x02 */ 961 U8 MaxFanSpeed; /* 0x03 */ 962 U32 Reserved04; /* 0x04 */ 963 } MPI3_MAN11_BOARD_FAN_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_BOARD_FAN_DEVICE_FORMAT, 964 Mpi3Man11BoardFanDeviceFormat_t, MPI3_POINTER pMpi3Man11BoardFanDeviceFormat_t; 965 966 /**** Defines for the Flags field ****/ 967 #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_MASK (0x07) 968 #define MPI3_MAN11_BOARD_FAN_FLAGS_FAN_CTRLR_TYPE_AMC6821 (0x00) 969 970 typedef union _MPI3_MAN11_DEVICE_SPECIFIC_FORMAT 971 { 972 MPI3_MAN11_MUX_DEVICE_FORMAT Mux; 973 MPI3_MAN11_TEMP_SENSOR_DEVICE_FORMAT TempSensor; 974 MPI3_MAN11_SEEPROM_DEVICE_FORMAT Seeprom; 975 MPI3_MAN11_DDR_SPD_DEVICE_FORMAT DdrSpd; 976 MPI3_MAN11_CABLE_MGMT_DEVICE_FORMAT CableMgmt; 977 MPI3_MAN11_BKPLANE_MGMT_DEVICE_FORMAT BkplaneMgmt; 978 MPI3_MAN11_GAS_GAUGE_DEVICE_FORMAT GasGauge; 979 MPI3_MAN11_MGMT_CTRLR_DEVICE_FORMAT MgmtController; 980 MPI3_MAN11_BOARD_FAN_DEVICE_FORMAT BoardFan; 981 U32 Words[2]; 982 } MPI3_MAN11_DEVICE_SPECIFIC_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_DEVICE_SPECIFIC_FORMAT, 983 Mpi3Man11DeviceSpecificFormat_t, MPI3_POINTER pMpi3Man11DeviceSpecificFormat_t; 984 985 typedef struct _MPI3_MAN11_ISTWI_DEVICE_FORMAT 986 { 987 U8 DeviceType; /* 0x00 */ 988 U8 Controller; /* 0x01 */ 989 U8 Reserved02; /* 0x02 */ 990 U8 Flags; /* 0x03 */ 991 U16 DeviceAddress; /* 0x04 */ 992 U8 MuxChannel; /* 0x06 */ 993 U8 MuxIndex; /* 0x07 */ 994 MPI3_MAN11_DEVICE_SPECIFIC_FORMAT DeviceSpecific; /* 0x08 */ 995 } MPI3_MAN11_ISTWI_DEVICE_FORMAT, MPI3_POINTER PTR_MPI3_MAN11_ISTWI_DEVICE_FORMAT, 996 Mpi3Man11IstwiDeviceFormat_t, MPI3_POINTER pMpi3Man11IstwiDeviceFormat_t; 997 998 /**** Defines for the DeviceType field ****/ 999 #define MPI3_MAN11_ISTWI_DEVTYPE_MUX (0x00) 1000 #define MPI3_MAN11_ISTWI_DEVTYPE_TEMP_SENSOR (0x01) 1001 #define MPI3_MAN11_ISTWI_DEVTYPE_SEEPROM (0x02) 1002 #define MPI3_MAN11_ISTWI_DEVTYPE_DDR_SPD (0x03) 1003 #define MPI3_MAN11_ISTWI_DEVTYPE_CABLE_MGMT (0x04) 1004 #define MPI3_MAN11_ISTWI_DEVTYPE_BACKPLANE_MGMT (0x05) 1005 #define MPI3_MAN11_ISTWI_DEVTYPE_GAS_GAUGE (0x06) 1006 #define MPI3_MAN11_ISTWI_DEVTYPE_MGMT_CONTROLLER (0x07) 1007 #define MPI3_MAN11_ISTWI_DEVTYPE_BOARD_FAN (0x08) 1008 1009 /**** Defines for the Flags field ****/ 1010 #define MPI3_MAN11_ISTWI_FLAGS_MUX_PRESENT (0x01) 1011 1012 #ifndef MPI3_MAN11_ISTWI_DEVICE_MAX 1013 #define MPI3_MAN11_ISTWI_DEVICE_MAX (1) 1014 #endif /* MPI3_MAN11_ISTWI_DEVICE_MAX */ 1015 1016 typedef struct _MPI3_MAN_PAGE11 1017 { 1018 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1019 U32 Reserved08; /* 0x08 */ 1020 U8 NumISTWIDev; /* 0x0C */ 1021 U8 Reserved0D[3]; /* 0x0D */ 1022 MPI3_MAN11_ISTWI_DEVICE_FORMAT ISTWIDevice[MPI3_MAN11_ISTWI_DEVICE_MAX]; /* 0x10 */ 1023 } MPI3_MAN_PAGE11, MPI3_POINTER PTR_MPI3_MAN_PAGE11, 1024 Mpi3ManPage11_t, MPI3_POINTER pMpi3ManPage11_t; 1025 1026 /**** Defines for the PageVersion field ****/ 1027 #define MPI3_MAN11_PAGEVERSION (0x00) 1028 1029 1030 /***************************************************************************** 1031 * Manufacturing Page 12 * 1032 ****************************************************************************/ 1033 #ifndef MPI3_MAN12_NUM_SGPIO_MAX 1034 #define MPI3_MAN12_NUM_SGPIO_MAX (1) 1035 #endif /* MPI3_MAN12_NUM_SGPIO_MAX */ 1036 1037 typedef struct _MPI3_MAN12_SGPIO_INFO 1038 { 1039 U8 SlotCount; /* 0x00 */ 1040 U8 Reserved01[3]; /* 0x01 */ 1041 U32 Reserved04; /* 0x04 */ 1042 U8 PhyOrder[32]; /* 0x08 */ 1043 } MPI3_MAN12_SGPIO_INFO, MPI3_POINTER PTR_MPI3_MAN12_SGPIO_INFO, 1044 Mpi3Man12SGPIOInfo_t, MPI3_POINTER pMpi3Man12SGPIOInfo_t; 1045 1046 typedef struct _MPI3_MAN_PAGE12 1047 { 1048 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1049 U32 Flags; /* 0x08 */ 1050 U32 SClockFreq; /* 0x0C */ 1051 U32 ActivityModulation; /* 0x10 */ 1052 U8 NumSGPIO; /* 0x14 */ 1053 U8 Reserved15[3]; /* 0x15 */ 1054 U32 Reserved18; /* 0x18 */ 1055 U32 Reserved1C; /* 0x1C */ 1056 U32 Pattern[8]; /* 0x20 */ 1057 MPI3_MAN12_SGPIO_INFO SGPIOInfo[MPI3_MAN12_NUM_SGPIO_MAX]; /* 0x40 */ /* variable length */ 1058 } MPI3_MAN_PAGE12, MPI3_POINTER PTR_MPI3_MAN_PAGE12, 1059 Mpi3ManPage12_t, MPI3_POINTER pMpi3ManPage12_t; 1060 1061 /**** Defines for the PageVersion field ****/ 1062 #define MPI3_MAN12_PAGEVERSION (0x00) 1063 1064 /**** Defines for the Flags field ****/ 1065 #define MPI3_MAN12_FLAGS_ERROR_PRESENCE_ENABLED (0x0400) 1066 #define MPI3_MAN12_FLAGS_ACTIVITY_INVERT_ENABLED (0x0200) 1067 #define MPI3_MAN12_FLAGS_GROUP_ID_DISABLED (0x0100) 1068 #define MPI3_MAN12_FLAGS_SIO_CLK_FILTER_ENABLED (0x0004) 1069 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_MASK (0x0002) 1070 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_PUSH_PULL (0x0000) 1071 #define MPI3_MAN12_FLAGS_SCLOCK_SLOAD_TYPE_OPEN_DRAIN (0x0002) 1072 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_MASK (0x0001) 1073 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_PUSH_PULL (0x0000) 1074 #define MPI3_MAN12_FLAGS_SDATAOUT_TYPE_OPEN_DRAIN (0x0001) 1075 1076 /**** Defines for the SioClkFreq field ****/ 1077 #define MPI3_MAN12_SIO_CLK_FREQ_MIN (32) /* 32 Hz min SIO Clk Freq */ 1078 #define MPI3_MAN12_SIO_CLK_FREQ_MAX (100000) /* 100 KHz max SIO Clk Freq */ 1079 1080 /**** Defines for the ActivityModulation field ****/ 1081 #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_MASK (0x0000F000) 1082 #define MPI3_MAN12_ACTIVITY_MODULATION_FORCE_OFF_SHIFT (12) 1083 #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_MASK (0x00000F00) 1084 #define MPI3_MAN12_ACTIVITY_MODULATION_MAX_ON_SHIFT (8) 1085 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_MASK (0x000000F0) 1086 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_OFF_SHIFT (4) 1087 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_MASK (0x0000000F) 1088 #define MPI3_MAN12_ACTIVITY_MODULATION_STRETCH_ON_SHIFT (0) 1089 1090 /*** Defines for the Pattern field ****/ 1091 #define MPI3_MAN12_PATTERN_RATE_MASK (0xE0000000) 1092 #define MPI3_MAN12_PATTERN_RATE_2_HZ (0x00000000) 1093 #define MPI3_MAN12_PATTERN_RATE_4_HZ (0x20000000) 1094 #define MPI3_MAN12_PATTERN_RATE_8_HZ (0x40000000) 1095 #define MPI3_MAN12_PATTERN_RATE_16_HZ (0x60000000) 1096 #define MPI3_MAN12_PATTERN_RATE_10_HZ (0x80000000) 1097 #define MPI3_MAN12_PATTERN_RATE_20_HZ (0xA0000000) 1098 #define MPI3_MAN12_PATTERN_RATE_40_HZ (0xC0000000) 1099 #define MPI3_MAN12_PATTERN_LENGTH_MASK (0x1F000000) 1100 #define MPI3_MAN12_PATTERN_LENGTH_SHIFT (24) 1101 #define MPI3_MAN12_PATTERN_BIT_PATTERN_MASK (0x00FFFFFF) 1102 #define MPI3_MAN12_PATTERN_BIT_PATTERN_SHIFT (0) 1103 1104 1105 /***************************************************************************** 1106 * Manufacturing Page 13 * 1107 ****************************************************************************/ 1108 1109 #ifndef MPI3_MAN13_NUM_TRANSLATION_MAX 1110 #define MPI3_MAN13_NUM_TRANSLATION_MAX (1) 1111 #endif /* MPI3_MAN13_NUM_TRANSLATION_MAX */ 1112 1113 typedef struct _MPI3_MAN13_TRANSLATION_INFO 1114 { 1115 U32 SlotStatus; /* 0x00 */ 1116 U32 Mask; /* 0x04 */ 1117 U8 Activity; /* 0x08 */ 1118 U8 Locate; /* 0x09 */ 1119 U8 Error; /* 0x0A */ 1120 U8 Reserved0B; /* 0x0B */ 1121 } MPI3_MAN13_TRANSLATION_INFO, MPI3_POINTER PTR_MPI3_MAN13_TRANSLATION_INFO, 1122 Mpi3Man13TranslationInfo_t, MPI3_POINTER pMpi3Man13TranslationInfo_t; 1123 1124 /**** Defines for the SlotStatus field ****/ 1125 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_FAULT (0x20000000) 1126 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_OFF (0x10000000) 1127 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_ACTIVITY (0x00800000) 1128 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DO_NOT_REMOVE (0x00400000) 1129 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_DEVICE_MISSING (0x00100000) 1130 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_INSERT (0x00080000) 1131 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REMOVAL (0x00040000) 1132 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IDENTIFY (0x00020000) 1133 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_OK (0x00008000) 1134 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_RESERVED_DEVICE (0x00004000) 1135 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_HOT_SPARE (0x00002000) 1136 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_CONSISTENCY_CHECK (0x00001000) 1137 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_CRITICAL_ARRAY (0x00000800) 1138 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_IN_FAILED_ARRAY (0x00000400) 1139 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP (0x00000200) 1140 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_REBUILD_REMAP_ABORT (0x00000100) 1141 #define MPI3_MAN13_TRANSLATION_SLOTSTATUS_PREDICTED_FAILURE (0x00000040) 1142 1143 /**** Defines for the Mask field - use MPI3_MAN13_TRANSLATION_SLOTSTATUS_ defines ****/ 1144 1145 /**** Defines for the Activity, Locate, and Error fields ****/ 1146 #define MPI3_MAN13_BLINK_PATTERN_FORCE_OFF (0x00) 1147 #define MPI3_MAN13_BLINK_PATTERN_FORCE_ON (0x01) 1148 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_0 (0x02) 1149 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_1 (0x03) 1150 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_2 (0x04) 1151 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_3 (0x05) 1152 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_4 (0x06) 1153 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_5 (0x07) 1154 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_6 (0x08) 1155 #define MPI3_MAN13_BLINK_PATTERN_PATTERN_7 (0x09) 1156 #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY (0x0A) 1157 #define MPI3_MAN13_BLINK_PATTERN_ACTIVITY_TRAIL (0x0B) 1158 1159 typedef struct _MPI3_MAN_PAGE13 1160 { 1161 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1162 U8 NumTrans; /* 0x08 */ 1163 U8 Reserved09[3]; /* 0x09 */ 1164 U32 Reserved0C; /* 0x0C */ 1165 MPI3_MAN13_TRANSLATION_INFO Translation[MPI3_MAN13_NUM_TRANSLATION_MAX]; /* 0x10 */ /* variable length */ 1166 } MPI3_MAN_PAGE13, MPI3_POINTER PTR_MPI3_MAN_PAGE13, 1167 Mpi3ManPage13_t, MPI3_POINTER pMpi3ManPage13_t; 1168 1169 /**** Defines for the PageVersion field ****/ 1170 #define MPI3_MAN13_PAGEVERSION (0x00) 1171 1172 /***************************************************************************** 1173 * Manufacturing Page 14 * 1174 ****************************************************************************/ 1175 1176 typedef struct _MPI3_MAN_PAGE14 1177 { 1178 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1179 U32 Reserved08; /* 0x08 */ 1180 U8 NumSlotGroups; /* 0x0C */ 1181 U8 NumSlots; /* 0x0D */ 1182 U16 MaxCertChainLength; /* 0x0E */ 1183 U32 SealedSlots; /* 0x10 */ 1184 U32 PopulatedSlots; /* 0x14 */ 1185 U32 MgmtPTUpdatableSlots; /* 0x18 */ 1186 } MPI3_MAN_PAGE14, MPI3_POINTER PTR_MPI3_MAN_PAGE14, 1187 Mpi3ManPage14_t, MPI3_POINTER pMpi3ManPage14_t; 1188 1189 /**** Defines for the PageVersion field ****/ 1190 #define MPI3_MAN14_PAGEVERSION (0x00) 1191 1192 /**** Defines for the NumSlots field ****/ 1193 #define MPI3_MAN14_NUMSLOTS_MAX (32) 1194 1195 /***************************************************************************** 1196 * Manufacturing Page 15 * 1197 ****************************************************************************/ 1198 1199 #ifndef MPI3_MAN15_VERSION_RECORD_MAX 1200 #define MPI3_MAN15_VERSION_RECORD_MAX 1 1201 #endif /* MPI3_MAN15_VERSION_RECORD_MAX */ 1202 1203 typedef struct _MPI3_MAN15_VERSION_RECORD 1204 { 1205 U16 SPDMVersion; /* 0x00 */ 1206 U16 Reserved02; /* 0x02 */ 1207 } MPI3_MAN15_VERSION_RECORD, MPI3_POINTER PTR_MPI3_MAN15_VERSION_RECORD, 1208 Mpi3Man15VersionRecord_t, MPI3_POINTER pMpi3Man15VersionRecord_t; 1209 1210 typedef struct _MPI3_MAN_PAGE15 1211 { 1212 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1213 U8 NumVersionRecords; /* 0x08 */ 1214 U8 Reserved09[3]; /* 0x09 */ 1215 U32 Reserved0C; /* 0x0C */ 1216 MPI3_MAN15_VERSION_RECORD VersionRecord[MPI3_MAN15_VERSION_RECORD_MAX]; /* 0x10 */ 1217 } MPI3_MAN_PAGE15, MPI3_POINTER PTR_MPI3_MAN_PAGE15, 1218 Mpi3ManPage15_t, MPI3_POINTER pMpi3ManPage15_t; 1219 1220 /**** Defines for the PageVersion field ****/ 1221 #define MPI3_MAN15_PAGEVERSION (0x00) 1222 1223 /***************************************************************************** 1224 * Manufacturing Page 16 * 1225 ****************************************************************************/ 1226 1227 #ifndef MPI3_MAN16_CERT_ALGO_MAX 1228 #define MPI3_MAN16_CERT_ALGO_MAX 1 1229 #endif /* MPI3_MAN16_CERT_ALGO_MAX */ 1230 1231 typedef struct _MPI3_MAN16_CERTIFICATE_ALGORITHM 1232 { 1233 U8 SlotGroup; /* 0x00 */ 1234 U8 Reserved01[3]; /* 0x01 */ 1235 U32 BaseAsymAlgo; /* 0x04 */ 1236 U32 BaseHashAlgo; /* 0x08 */ 1237 U32 Reserved0C[3]; /* 0x0C */ 1238 } MPI3_MAN16_CERTIFICATE_ALGORITHM, MPI3_POINTER PTR_MPI3_MAN16_CERTIFICATE_ALGORITHM, 1239 Mpi3Man16CertificateAlgorithm_t, MPI3_POINTER pMpi3Man16CertificateAlgorithm_t; 1240 1241 typedef struct _MPI3_MAN_PAGE16 1242 { 1243 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1244 U32 Reserved08; /* 0x08 */ 1245 U8 NumCertAlgos; /* 0x0C */ 1246 U8 Reserved0D[3]; /* 0x0D */ 1247 MPI3_MAN16_CERTIFICATE_ALGORITHM CertificateAlgorithm[MPI3_MAN16_CERT_ALGO_MAX]; /* 0x10 */ 1248 } MPI3_MAN_PAGE16, MPI3_POINTER PTR_MPI3_MAN_PAGE16, 1249 Mpi3ManPage16_t, MPI3_POINTER pMpi3ManPage16_t; 1250 1251 /**** Defines for the PageVersion field ****/ 1252 #define MPI3_MAN16_PAGEVERSION (0x00) 1253 1254 /***************************************************************************** 1255 * Manufacturing Page 17 * 1256 ****************************************************************************/ 1257 1258 #ifndef MPI3_MAN17_HASH_ALGORITHM_MAX 1259 #define MPI3_MAN17_HASH_ALGORITHM_MAX 1 1260 #endif /* MPI3_MAN17_HASH_ALGORITHM_MAX */ 1261 1262 typedef struct _MPI3_MAN17_HASH_ALGORITHM 1263 { 1264 U8 MeasSpecification; /* 0x00 */ 1265 U8 Reserved01[3]; /* 0x01 */ 1266 U32 MeasurementHashAlgo; /* 0x04 */ 1267 U32 Reserved08[2]; /* 0x08 */ 1268 } MPI3_MAN17_HASH_ALGORITHM, MPI3_POINTER PTR_MPI3_MAN17_HASH_ALGORITHM, 1269 Mpi3Man17HashAlgorithm_t, MPI3_POINTER pMpi3Man17HashAlgorithm_t; 1270 1271 typedef struct _MPI3_MAN_PAGE17 1272 { 1273 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1274 U32 Reserved08; /* 0x08 */ 1275 U8 NumHashAlgos; /* 0x0C */ 1276 U8 Reserved0D[3]; /* 0x0D */ 1277 MPI3_MAN17_HASH_ALGORITHM HashAlgorithm[MPI3_MAN17_HASH_ALGORITHM_MAX]; /* 0x10 */ 1278 } MPI3_MAN_PAGE17, MPI3_POINTER PTR_MPI3_MAN_PAGE17, 1279 Mpi3ManPage17_t, MPI3_POINTER pMpi3ManPage17_t; 1280 1281 /**** Defines for the PageVersion field ****/ 1282 #define MPI3_MAN17_PAGEVERSION (0x00) 1283 1284 /***************************************************************************** 1285 * Manufacturing Page 20 * 1286 ****************************************************************************/ 1287 1288 typedef struct _MPI3_MAN_PAGE20 1289 { 1290 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1291 U32 Reserved08; /* 0x08 */ 1292 U32 NonpremiumFeatures; /* 0x0C */ 1293 U8 AllowedPersonalities; /* 0x10 */ 1294 U8 Reserved11[3]; /* 0x11 */ 1295 } MPI3_MAN_PAGE20, MPI3_POINTER PTR_MPI3_MAN_PAGE20, 1296 Mpi3ManPage20_t, MPI3_POINTER pMpi3ManPage20_t; 1297 1298 /**** Defines for the PageVersion field ****/ 1299 #define MPI3_MAN20_PAGEVERSION (0x00) 1300 1301 /**** Defines for the AllowedPersonalities field ****/ 1302 #define MPI3_MAN20_ALLOWEDPERSON_RAID_MASK (0x02) 1303 #define MPI3_MAN20_ALLOWEDPERSON_RAID_ALLOWED (0x02) 1304 #define MPI3_MAN20_ALLOWEDPERSON_RAID_NOT_ALLOWED (0x00) 1305 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_MASK (0x01) 1306 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_ALLOWED (0x01) 1307 #define MPI3_MAN20_ALLOWEDPERSON_EHBA_NOT_ALLOWED (0x00) 1308 1309 /**** Defines for the NonpremuimFeatures field ****/ 1310 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_MASK (0x01) 1311 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_ENABLED (0x00) 1312 #define MPI3_MAN20_NONPREMUIM_DISABLE_PD_DEGRADED_DISABLED (0x01) 1313 1314 /***************************************************************************** 1315 * Manufacturing Page 21 * 1316 ****************************************************************************/ 1317 1318 typedef struct _MPI3_MAN_PAGE21 1319 { 1320 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1321 U32 Reserved08; /* 0x08 */ 1322 U32 Flags; /* 0x0C */ 1323 } MPI3_MAN_PAGE21, MPI3_POINTER PTR_MPI3_MAN_PAGE21, 1324 Mpi3ManPage21_t, MPI3_POINTER pMpi3ManPage21_t; 1325 1326 /**** Defines for the PageVersion field ****/ 1327 #define MPI3_MAN21_PAGEVERSION (0x00) 1328 1329 /**** Defines for the Flags field ****/ 1330 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_MASK (0x00000060) 1331 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_BLOCK (0x00000000) 1332 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_ALLOW (0x00000020) 1333 #define MPI3_MAN21_FLAGS_UNCERTIFIED_DRIVES_WARN (0x00000040) 1334 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_MASK (0x00000008) 1335 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_ALLOW (0x00000000) 1336 #define MPI3_MAN21_FLAGS_BLOCK_SSD_WR_CACHE_CHANGE_PREVENT (0x00000008) 1337 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_MASK (0x00000001) 1338 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_DEFAULT (0x00000000) 1339 #define MPI3_MAN21_FLAGS_SES_VPD_ASSOC_OEM_SPECIFIC (0x00000001) 1340 1341 /***************************************************************************** 1342 * Manufacturing Pages 32-63 (ProductSpecific) * 1343 ****************************************************************************/ 1344 #ifndef MPI3_MAN_PROD_SPECIFIC_MAX 1345 #define MPI3_MAN_PROD_SPECIFIC_MAX (1) 1346 #endif /* MPI3_MAN_PROD_SPECIFIC_MAX */ 1347 1348 typedef struct _MPI3_MAN_PAGE_PRODUCT_SPECIFIC 1349 { 1350 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1351 U32 ProductSpecificInfo[MPI3_MAN_PROD_SPECIFIC_MAX]; /* 0x08 */ /* variable length array */ 1352 } MPI3_MAN_PAGE_PRODUCT_SPECIFIC, MPI3_POINTER PTR_MPI3_MAN_PAGE_PRODUCT_SPECIFIC, 1353 Mpi3ManPageProductSpecific_t, MPI3_POINTER pMpi3ManPageProductSpecific_t; 1354 1355 /***************************************************************************** 1356 * IO Unit Configuration Pages * 1357 ****************************************************************************/ 1358 1359 /***************************************************************************** 1360 * IO Unit Page 0 * 1361 ****************************************************************************/ 1362 typedef struct _MPI3_IO_UNIT_PAGE0 1363 { 1364 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1365 U64 UniqueValue; /* 0x08 */ 1366 U32 NvdataVersionDefault; /* 0x10 */ 1367 U32 NvdataVersionPersistent; /* 0x14 */ 1368 } MPI3_IO_UNIT_PAGE0, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE0, 1369 Mpi3IOUnitPage0_t, MPI3_POINTER pMpi3IOUnitPage0_t; 1370 1371 /**** Defines for the PageVersion field ****/ 1372 #define MPI3_IOUNIT0_PAGEVERSION (0x00) 1373 1374 /***************************************************************************** 1375 * IO Unit Page 1 * 1376 ****************************************************************************/ 1377 typedef struct _MPI3_IO_UNIT_PAGE1 1378 { 1379 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1380 U32 Flags; /* 0x08 */ 1381 U8 DMDIoDelay; /* 0x0C */ 1382 U8 DMDReportPCIe; /* 0x0D */ 1383 U8 DMDReportSATA; /* 0x0E */ 1384 U8 DMDReportSAS; /* 0x0F */ 1385 } MPI3_IO_UNIT_PAGE1, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE1, 1386 Mpi3IOUnitPage1_t, MPI3_POINTER pMpi3IOUnitPage1_t; 1387 1388 /**** Defines for the PageVersion field ****/ 1389 #define MPI3_IOUNIT1_PAGEVERSION (0x00) 1390 1391 /**** Defines for the Flags field ****/ 1392 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_MASK (0x00000030) 1393 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_ENABLE (0x00000000) 1394 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_DISABLE (0x00000010) 1395 #define MPI3_IOUNIT1_FLAGS_NVME_WRITE_CACHE_NO_MODIFY (0x00000020) 1396 #define MPI3_IOUNIT1_FLAGS_ATA_SECURITY_FREEZE_LOCK (0x00000008) 1397 #define MPI3_IOUNIT1_FLAGS_WRITE_SAME_BUFFER (0x00000004) 1398 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_MASK (0x00000003) 1399 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_ENABLE (0x00000000) 1400 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_DISABLE (0x00000001) 1401 #define MPI3_IOUNIT1_FLAGS_SATA_WRITE_CACHE_UNCHANGED (0x00000002) 1402 1403 /**** Defines for the DMDReport PCIe/SATA/SAS fields ****/ 1404 #define MPI3_IOUNIT1_DMD_REPORT_DELAY_TIME_MASK (0x7F) 1405 #define MPI3_IOUNIT1_DMD_REPORT_UNIT_16_SEC (0x80) 1406 1407 /***************************************************************************** 1408 * IO Unit Page 2 * 1409 ****************************************************************************/ 1410 #ifndef MPI3_IO_UNIT2_GPIO_VAL_MAX 1411 #define MPI3_IO_UNIT2_GPIO_VAL_MAX (1) 1412 #endif /* MPI3_IO_UNIT2_GPIO_VAL_MAX */ 1413 1414 typedef struct _MPI3_IO_UNIT_PAGE2 1415 { 1416 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1417 U8 GPIOCount; /* 0x08 */ 1418 U8 Reserved09[3]; /* 0x09 */ 1419 U16 GPIOVal[MPI3_IO_UNIT2_GPIO_VAL_MAX]; /* 0x0C */ 1420 } MPI3_IO_UNIT_PAGE2, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE2, 1421 Mpi3IOUnitPage2_t, MPI3_POINTER pMpi3IOUnitPage2_t; 1422 1423 /**** Defines for the PageVersion field ****/ 1424 #define MPI3_IOUNIT2_PAGEVERSION (0x00) 1425 1426 /**** Define for the GPIOVal field ****/ 1427 #define MPI3_IOUNIT2_GPIO_FUNCTION_MASK (0xFFFC) 1428 #define MPI3_IOUNIT2_GPIO_FUNCTION_SHIFT (2) 1429 #define MPI3_IOUNIT2_GPIO_SETTING_MASK (0x0001) 1430 #define MPI3_IOUNIT2_GPIO_SETTING_OFF (0x0000) 1431 #define MPI3_IOUNIT2_GPIO_SETTING_ON (0x0001) 1432 1433 /***************************************************************************** 1434 * IO Unit Page 3 * 1435 ****************************************************************************/ 1436 1437 typedef struct _MPI3_IO_UNIT3_SENSOR 1438 { 1439 U16 Flags; /* 0x00 */ 1440 U8 ThresholdMargin; /* 0x02 */ 1441 U8 Reserved03; /* 0x03 */ 1442 U16 Threshold[3]; /* 0x04 */ 1443 U16 Reserved0A; /* 0x0A */ 1444 U32 Reserved0C; /* 0x0C */ 1445 U32 Reserved10; /* 0x10 */ 1446 U32 Reserved14; /* 0x14 */ 1447 } MPI3_IO_UNIT3_SENSOR, MPI3_POINTER PTR_MPI3_IO_UNIT3_SENSOR, 1448 Mpi3IOUnit3Sensor_t, MPI3_POINTER pMpi3IOUnit3Sensor_t; 1449 1450 /**** Defines for the Flags field ****/ 1451 #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_EVENT_ENABLED (0x0010) 1452 #define MPI3_IOUNIT3_SENSOR_FLAGS_FATAL_ACTION_ENABLED (0x0008) 1453 #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_EVENT_ENABLED (0x0004) 1454 #define MPI3_IOUNIT3_SENSOR_FLAGS_CRITICAL_ACTION_ENABLED (0x0002) 1455 #define MPI3_IOUNIT3_SENSOR_FLAGS_WARNING_EVENT_ENABLED (0x0001) 1456 1457 #ifndef MPI3_IO_UNIT3_SENSOR_MAX 1458 #define MPI3_IO_UNIT3_SENSOR_MAX (1) 1459 #endif /* MPI3_IO_UNIT3_SENSOR_MAX */ 1460 1461 typedef struct _MPI3_IO_UNIT_PAGE3 1462 { 1463 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1464 U32 Reserved08; /* 0x08 */ 1465 U8 NumSensors; /* 0x0C */ 1466 U8 NominalPollInterval; /* 0x0D */ 1467 U8 WarningPollInterval; /* 0x0E */ 1468 U8 Reserved0F; /* 0x0F */ 1469 MPI3_IO_UNIT3_SENSOR Sensor[MPI3_IO_UNIT3_SENSOR_MAX]; /* 0x10 */ 1470 } MPI3_IO_UNIT_PAGE3, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE3, 1471 Mpi3IOUnitPage3_t, MPI3_POINTER pMpi3IOUnitPage3_t; 1472 1473 /**** Defines for the PageVersion field ****/ 1474 #define MPI3_IOUNIT3_PAGEVERSION (0x00) 1475 1476 1477 /***************************************************************************** 1478 * IO Unit Page 4 * 1479 ****************************************************************************/ 1480 typedef struct _MPI3_IO_UNIT4_SENSOR 1481 { 1482 U16 CurrentTemperature; /* 0x00 */ 1483 U16 Reserved02; /* 0x02 */ 1484 U8 Flags; /* 0x04 */ 1485 U8 Reserved05[3]; /* 0x05 */ 1486 U16 ISTWIIndex; /* 0x08 */ 1487 U8 Channel; /* 0x0A */ 1488 U8 Reserved0B; /* 0x0B */ 1489 U32 Reserved0C; /* 0x0C */ 1490 } MPI3_IO_UNIT4_SENSOR, MPI3_POINTER PTR_MPI3_IO_UNIT4_SENSOR, 1491 Mpi3IOUnit4Sensor_t, MPI3_POINTER pMpi3IOUnit4Sensor_t; 1492 1493 /**** Defines for the Flags field ****/ 1494 #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_MASK (0xE0) 1495 #define MPI3_IOUNIT4_SENSOR_FLAGS_LOC_SHIFT (5) 1496 /**** for the Location field values - use MPI3_TEMP_SENSOR_LOCATION_ defines ****/ 1497 #define MPI3_IOUNIT4_SENSOR_FLAGS_TEMP_VALID (0x01) 1498 1499 1500 /**** Defines for the ISTWIIndex field ****/ 1501 #define MPI3_IOUNIT4_SENSOR_ISTWI_INDEX_INTERNAL (0xFFFF) 1502 1503 /**** Defines for the Channel field ****/ 1504 #define MPI3_IOUNIT4_SENSOR_CHANNEL_RESERVED (0xFF) 1505 1506 #ifndef MPI3_IO_UNIT4_SENSOR_MAX 1507 #define MPI3_IO_UNIT4_SENSOR_MAX (1) 1508 #endif /* MPI3_IO_UNIT4_SENSOR_MAX */ 1509 1510 typedef struct _MPI3_IO_UNIT_PAGE4 1511 { 1512 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1513 U32 Reserved08; /* 0x08 */ 1514 U8 NumSensors; /* 0x0C */ 1515 U8 Reserved0D[3]; /* 0x0D */ 1516 MPI3_IO_UNIT4_SENSOR Sensor[MPI3_IO_UNIT4_SENSOR_MAX]; /* 0x10 */ 1517 } MPI3_IO_UNIT_PAGE4, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE4, 1518 Mpi3IOUnitPage4_t, MPI3_POINTER pMpi3IOUnitPage4_t; 1519 1520 /**** Defines for the PageVersion field ****/ 1521 #define MPI3_IOUNIT4_PAGEVERSION (0x00) 1522 1523 /***************************************************************************** 1524 * IO Unit Page 5 * 1525 ****************************************************************************/ 1526 typedef struct _MPI3_IO_UNIT5_SPINUP_GROUP 1527 { 1528 U8 MaxTargetSpinup; /* 0x00 */ 1529 U8 SpinupDelay; /* 0x01 */ 1530 U8 SpinupFlags; /* 0x02 */ 1531 U8 Reserved03; /* 0x03 */ 1532 } MPI3_IO_UNIT5_SPINUP_GROUP, MPI3_POINTER PTR_MPI3_IO_UNIT5_SPINUP_GROUP, 1533 Mpi3IOUnit5SpinupGroup_t, MPI3_POINTER pMpi3IOUnit5SpinupGroup_t; 1534 1535 /**** Defines for the SpinupFlags field ****/ 1536 #define MPI3_IOUNIT5_SPINUP_FLAGS_DISABLE (0x01) 1537 1538 #ifndef MPI3_IO_UNIT5_PHY_MAX 1539 #define MPI3_IO_UNIT5_PHY_MAX (4) 1540 #endif /* MPI3_IO_UNIT5_PHY_MAX */ 1541 1542 typedef struct _MPI3_IO_UNIT_PAGE5 1543 { 1544 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1545 MPI3_IO_UNIT5_SPINUP_GROUP SpinupGroupParameters[4]; /* 0x08 */ 1546 U32 Reserved18; /* 0x18 */ 1547 U32 Reserved1C; /* 0x1C */ 1548 U16 DeviceShutdown; /* 0x20 */ 1549 U16 Reserved22; /* 0x22 */ 1550 U8 PCIeDeviceWaitTime; /* 0x24 */ 1551 U8 SATADeviceWaitTime; /* 0x25 */ 1552 U8 SpinupEnclDriveCount; /* 0x26 */ 1553 U8 SpinupEnclDelay; /* 0x27 */ 1554 U8 NumPhys; /* 0x28 */ 1555 U8 PEInitialSpinupDelay; /* 0x29 */ 1556 U8 TopologyStableTime; /* 0x2A */ 1557 U8 Flags; /* 0x2B */ 1558 U8 Phy[MPI3_IO_UNIT5_PHY_MAX]; /* 0x2C */ 1559 } MPI3_IO_UNIT_PAGE5, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE5, 1560 Mpi3IOUnitPage5_t, MPI3_POINTER pMpi3IOUnitPage5_t; 1561 1562 /**** Defines for the PageVersion field ****/ 1563 #define MPI3_IOUNIT5_PAGEVERSION (0x00) 1564 1565 /**** Defines for the DeviceShutdown field ****/ 1566 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NO_ACTION (0x00) 1567 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_ATTACHED (0x01) 1568 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_EXPANDER_ATTACHED (0x02) 1569 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SWITCH_ATTACHED (0x02) 1570 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_EXPANDER (0x03) 1571 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_DIRECT_AND_SWITCH (0x03) 1572 1573 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_MASK (0x0300) 1574 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_HDD_SHIFT (8) 1575 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_MASK (0x00C0) 1576 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_HDD_SHIFT (6) 1577 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_MASK (0x0030) 1578 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_NVME_SSD_SHIFT (4) 1579 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_MASK (0x000C) 1580 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SATA_SSD_SHIFT (2) 1581 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_MASK (0x0003) 1582 #define MPI3_IOUNIT5_DEVICE_SHUTDOWN_SAS_SSD_SHIFT (0) 1583 1584 /**** Defines for the Flags field ****/ 1585 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_MASK (0x0C) 1586 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_SHIFT (2) 1587 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_NOT_SUPPORTED (0x00) 1588 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_OS_CONTROLLED (0x04) 1589 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_APP_CONTROLLED (0x08) 1590 #define MPI3_IOUNIT5_FLAGS_SATAPUIS_BLOCKED (0x0C) 1591 #define MPI3_IOUNIT5_FLAGS_POWER_CAPABLE_SPINUP (0x02) 1592 #define MPI3_IOUNIT5_FLAGS_AUTO_PORT_ENABLE (0x01) 1593 1594 /**** Defines for the PHY field ****/ 1595 #define MPI3_IOUNIT5_PHY_SPINUP_GROUP_MASK (0x03) 1596 1597 /***************************************************************************** 1598 * IO Unit Page 6 * 1599 ****************************************************************************/ 1600 typedef struct _MPI3_IO_UNIT_PAGE6 1601 { 1602 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1603 U32 BoardPowerRequirement; /* 0x08 */ 1604 U32 PCISlotPowerAllocation; /* 0x0C */ 1605 U8 Flags; /* 0x10 */ 1606 U8 Reserved11[3]; /* 0x11 */ 1607 } MPI3_IO_UNIT_PAGE6, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE6, 1608 Mpi3IOUnitPage6_t, MPI3_POINTER pMpi3IOUnitPage6_t; 1609 1610 /**** Defines for the PageVersion field ****/ 1611 #define MPI3_IOUNIT6_PAGEVERSION (0x00) 1612 1613 /**** Defines for the Flags field ****/ 1614 #define MPI3_IOUNIT6_FLAGS_ACT_CABLE_PWR_EXC (0x01) 1615 1616 /***************************************************************************** 1617 * IO Unit Page 8 * 1618 ****************************************************************************/ 1619 1620 #ifndef MPI3_IOUNIT8_DIGEST_MAX 1621 #define MPI3_IOUNIT8_DIGEST_MAX (1) 1622 #endif /* MPI3_IOUNIT8_DIGEST_MAX */ 1623 1624 typedef union _MPI3_IOUNIT8_DIGEST 1625 { 1626 U32 Dword[16]; 1627 U16 Word[32]; 1628 U8 Byte[64]; 1629 } MPI3_IOUNIT8_DIGEST, MPI3_POINTER PTR_MPI3_IOUNIT8_DIGEST, 1630 Mpi3IOUnit8Digest_t, MPI3_POINTER pMpi3IOUnit8Digest_t; 1631 1632 typedef struct _MPI3_IO_UNIT_PAGE8 1633 { 1634 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1635 U8 SBMode; /* 0x08 */ 1636 U8 SbState; /* 0x09 */ 1637 U16 Reserved0A; /* 0x0A */ 1638 U8 NumSlots; /* 0x0C */ 1639 U8 SlotsAvailable; /* 0x0D */ 1640 U8 CurrentKeyEncryptionAlgo; /* 0x0E */ 1641 U8 KeyDigestHashAlgo; /* 0x0F */ 1642 MPI3_VERSION_UNION CurrentSvn; /* 0x10 */ 1643 U32 Reserved14; /* 0x14 */ 1644 U32 CurrentKey[128]; /* 0x18 */ 1645 MPI3_IOUNIT8_DIGEST Digest[MPI3_IOUNIT8_DIGEST_MAX]; /* 0x218 */ /* variable length */ 1646 } MPI3_IO_UNIT_PAGE8, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE8, 1647 Mpi3IOUnitPage8_t, MPI3_POINTER pMpi3IOUnitPage8_t; 1648 1649 /**** Defines for the PageVersion field ****/ 1650 #define MPI3_IOUNIT8_PAGEVERSION (0x00) 1651 1652 /**** Defines for the SBMode field ****/ 1653 #define MPI3_IOUNIT8_SBMODE_SECURE_DEBUG (0x04) 1654 #define MPI3_IOUNIT8_SBMODE_HARD_SECURE (0x02) 1655 #define MPI3_IOUNIT8_SBMODE_CONFIG_SECURE (0x01) 1656 1657 /**** Defines for the SBState field ****/ 1658 #define MPI3_IOUNIT8_SBSTATE_SVN_UPDATE_PENDING (0x04) 1659 #define MPI3_IOUNIT8_SBSTATE_KEY_UPDATE_PENDING (0x02) 1660 #define MPI3_IOUNIT8_SBSTATE_SECURE_BOOT_ENABLED (0x01) 1661 1662 /***************************************************************************** 1663 * IO Unit Page 9 * 1664 ****************************************************************************/ 1665 1666 typedef struct _MPI3_IO_UNIT_PAGE9 1667 { 1668 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1669 U32 Flags; /* 0x08 */ 1670 U16 FirstDevice; /* 0x0C */ 1671 U16 Reserved0E; /* 0x0E */ 1672 } MPI3_IO_UNIT_PAGE9, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE9, 1673 Mpi3IOUnitPage9_t, MPI3_POINTER pMpi3IOUnitPage9_t; 1674 1675 /**** Defines for the PageVersion field ****/ 1676 #define MPI3_IOUNIT9_PAGEVERSION (0x00) 1677 1678 /**** Defines for the Flags field ****/ 1679 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_MASK (0x00000006) 1680 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_SHIFT (1) 1681 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_NONE (0x00000000) 1682 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_RECEPTACLE (0x00000002) 1683 #define MPI3_IOUNIT9_FLAGS_UBM_ENCLOSURE_ORDER_BACKPLANE_TYPE (0x00000004) 1684 #define MPI3_IOUNIT9_FLAGS_VDFIRST_ENABLED (0x00000001) 1685 1686 /**** Defines for the FirstDevice field ****/ 1687 #define MPI3_IOUNIT9_FIRSTDEVICE_UNKNOWN (0xFFFF) 1688 1689 /***************************************************************************** 1690 * IO Unit Page 10 * 1691 ****************************************************************************/ 1692 1693 typedef struct _MPI3_IO_UNIT_PAGE10 1694 { 1695 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1696 U8 Flags; /* 0x08 */ 1697 U8 Reserved09[3]; /* 0x09 */ 1698 U32 SiliconID; /* 0x0C */ 1699 U8 FWVersionMinor; /* 0x10 */ 1700 U8 FWVersionMajor; /* 0x11 */ 1701 U8 HWVersionMinor; /* 0x12 */ 1702 U8 HWVersionMajor; /* 0x13 */ 1703 U8 PartNumber[16]; /* 0x14 */ 1704 } MPI3_IO_UNIT_PAGE10, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE10, 1705 Mpi3IOUnitPage10_t, MPI3_POINTER pMpi3IOUnitPage10_t; 1706 1707 /**** Defines for the PageVersion field ****/ 1708 #define MPI3_IOUNIT10_PAGEVERSION (0x00) 1709 1710 /**** Defines for the Flags field ****/ 1711 #define MPI3_IOUNIT10_FLAGS_VALID (0x01) 1712 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_MASK (0x02) 1713 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_FIRST_REGION (0x00) 1714 #define MPI3_IOUNIT10_FLAGS_ACTIVEID_SECOND_REGION (0x02) 1715 #define MPI3_IOUNIT10_FLAGS_PBLP_EXPECTED (0x80) 1716 1717 /***************************************************************************** 1718 * IO Unit Page 11 * 1719 ****************************************************************************/ 1720 1721 #ifndef MPI3_IOUNIT11_PROFILE_MAX 1722 #define MPI3_IOUNIT11_PROFILE_MAX (1) 1723 #endif /* MPI3_IOUNIT11_PROFILE_MAX */ 1724 1725 typedef struct _MPI3_IOUNIT11_PROFILE 1726 { 1727 U8 ProfileIdentifier; /* 0x00 */ 1728 U8 Reserved01[3]; /* 0x01 */ 1729 U16 MaxVDs; /* 0x04 */ 1730 U16 MaxHostPDs; /* 0x06 */ 1731 U16 MaxAdvHostPDs; /* 0x08 */ 1732 U16 MaxRAIDPDs; /* 0x0A */ 1733 U16 MaxNVMe; /* 0x0C */ 1734 U16 MaxOutstandingRequests; /* 0x0E */ 1735 U16 SubsystemID; /* 0x10 */ 1736 U16 Reserved12; /* 0x12 */ 1737 U32 Reserved14[2]; /* 0x14 */ 1738 } MPI3_IOUNIT11_PROFILE, MPI3_POINTER PTR_MPI3_IOUNIT11_PROFILE, 1739 Mpi3IOUnit11Profile_t, MPI3_POINTER pMpi3IOUnit11Profile_t; 1740 1741 typedef struct _MPI3_IO_UNIT_PAGE11 1742 { 1743 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1744 U32 Reserved08; /* 0x08 */ 1745 U8 NumProfiles; /* 0x0C */ 1746 U8 CurrentProfileIdentifier; /* 0x0D */ 1747 U16 Reserved0E; /* 0x0E */ 1748 MPI3_IOUNIT11_PROFILE Profile[MPI3_IOUNIT11_PROFILE_MAX]; /* 0x10 */ /* variable length */ 1749 } MPI3_IO_UNIT_PAGE11, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE11, 1750 Mpi3IOUnitPage11_t, MPI3_POINTER pMpi3IOUnitPage11_t; 1751 1752 /**** Defines for the PageVersion field ****/ 1753 #define MPI3_IOUNIT11_PAGEVERSION (0x00) 1754 1755 /***************************************************************************** 1756 * IO Unit Page 12 * 1757 ****************************************************************************/ 1758 1759 #ifndef MPI3_IOUNIT12_BUCKET_MAX 1760 #define MPI3_IOUNIT12_BUCKET_MAX (1) 1761 #endif /* MPI3_IOUNIT12_BUCKET_MAX */ 1762 1763 typedef struct _MPI3_IOUNIT12_BUCKET 1764 { 1765 U8 CoalescingDepth; /* 0x00 */ 1766 U8 CoalescingTimeout; /* 0x01 */ 1767 U16 IOCountLowBoundary; /* 0x02 */ 1768 U32 Reserved04; /* 0x04 */ 1769 } MPI3_IOUNIT12_BUCKET, MPI3_POINTER PTR_MPI3_IOUNIT12_BUCKET, 1770 Mpi3IOUnit12Bucket_t, MPI3_POINTER pMpi3IOUnit12Bucket_t; 1771 1772 typedef struct _MPI3_IO_UNIT_PAGE12 1773 { 1774 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1775 U32 Flags; /* 0x08 */ 1776 U32 Reserved0C[4]; /* 0x0C */ 1777 U8 NumBuckets; /* 0x1C */ 1778 U8 Reserved1D[3]; /* 0x1D */ 1779 MPI3_IOUNIT12_BUCKET Bucket[MPI3_IOUNIT12_BUCKET_MAX]; /* 0x20 */ /* variable length */ 1780 } MPI3_IO_UNIT_PAGE12, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE12, 1781 Mpi3IOUnitPage12_t, MPI3_POINTER pMpi3IOUnitPage12_t; 1782 1783 /**** Defines for the PageVersion field ****/ 1784 #define MPI3_IOUNIT12_PAGEVERSION (0x00) 1785 1786 /**** Defines for the Flags field ****/ 1787 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_MASK (0x00000300) 1788 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_SHIFT (8) 1789 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_8 (0x00000000) 1790 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_16 (0x00000100) 1791 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_32 (0x00000200) 1792 #define MPI3_IOUNIT12_FLAGS_NUMPASSES_64 (0x00000300) 1793 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_MASK (0x00000003) 1794 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_DISABLED (0x00000000) 1795 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_500US (0x00000001) 1796 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_1MS (0x00000002) 1797 #define MPI3_IOUNIT12_FLAGS_PASSPERIOD_2MS (0x00000003) 1798 1799 /***************************************************************************** 1800 * IO Unit Page 13 * 1801 ****************************************************************************/ 1802 1803 #ifndef MPI3_IOUNIT13_FUNC_MAX 1804 #define MPI3_IOUNIT13_FUNC_MAX (1) 1805 #endif /* MPI3_IOUNIT13_FUNC_MAX */ 1806 1807 typedef struct _MPI3_IOUNIT13_ALLOWED_FUNCTION 1808 { 1809 U16 SubFunction; /* 0x00 */ 1810 U8 FunctionCode; /* 0x02 */ 1811 U8 FunctionFlags; /* 0x03 */ 1812 } MPI3_IOUNIT13_ALLOWED_FUNCTION, MPI3_POINTER PTR_MPI3_IOUNIT13_ALLOWED_FUNCTION, 1813 Mpi3IOUnit13AllowedFunction_t, MPI3_POINTER pMpi3IOUnit13AllowedFunction_t; 1814 1815 /**** Defines for the FunctionFlags field ****/ 1816 #define MPI3_IOUNIT13_FUNCTION_FLAGS_ADMIN_BLOCKED (0x04) 1817 #define MPI3_IOUNIT13_FUNCTION_FLAGS_OOB_BLOCKED (0x02) 1818 #define MPI3_IOUNIT13_FUNCTION_FLAGS_CHECK_SUBFUNCTION_ENABLED (0x01) 1819 1820 typedef struct _MPI3_IO_UNIT_PAGE13 1821 { 1822 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1823 U16 Flags; /* 0x08 */ 1824 U16 Reserved0A; /* 0x0A */ 1825 U8 NumAllowedFunctions; /* 0x0C */ 1826 U8 Reserved0D[3]; /* 0x0D */ 1827 MPI3_IOUNIT13_ALLOWED_FUNCTION AllowedFunction[MPI3_IOUNIT13_FUNC_MAX]; /* 0x10 */ /* variable length */ 1828 } MPI3_IO_UNIT_PAGE13, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE13, 1829 Mpi3IOUnitPage13_t, MPI3_POINTER pMpi3IOUnitPage13_t; 1830 1831 /**** Defines for the PageVersion field ****/ 1832 #define MPI3_IOUNIT13_PAGEVERSION (0x00) 1833 1834 /**** Defines for the Flags field ****/ 1835 #define MPI3_IOUNIT13_FLAGS_ADMIN_BLOCKED (0x0002) 1836 #define MPI3_IOUNIT13_FLAGS_OOB_BLOCKED (0x0001) 1837 1838 /***************************************************************************** 1839 * IO Unit Page 14 * 1840 ****************************************************************************/ 1841 1842 #ifndef MPI3_IOUNIT14_MD_MAX 1843 #define MPI3_IOUNIT14_MD_MAX (1) 1844 #endif /* MPI3_IOUNIT14_MD_MAX */ 1845 1846 typedef struct _MPI3_IOUNIT14_PAGEMETADATA 1847 { 1848 U8 PageType; /* 0x00 */ 1849 U8 PageNumber; /* 0x01 */ 1850 U8 Reserved02; /* 0x02 */ 1851 U8 PageFlags; /* 0x03 */ 1852 } MPI3_IOUNIT14_PAGEMETADATA, MPI3_POINTER PTR_MPI3_IOUNIT14_PAGEMETADATA, 1853 Mpi3IOUnit14PageMetadata_t, MPI3_POINTER pMpi3IOUnit14PageMetadata_t; 1854 1855 /**** Defines for the PageFlags field ****/ 1856 #define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_OOBWRITE_ALLOWED (0x02) 1857 #define MPI3_IOUNIT14_PAGEMETADATA_PAGEFLAGS_HOSTWRITE_ALLOWED (0x01) 1858 1859 typedef struct _MPI3_IO_UNIT_PAGE14 1860 { 1861 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1862 U8 Flags; /* 0x08 */ 1863 U8 Reserved09[3]; /* 0x09 */ 1864 U8 NumPages; /* 0x0C */ 1865 U8 Reserved0D[3]; /* 0x0D */ 1866 MPI3_IOUNIT14_PAGEMETADATA PageMetadata[MPI3_IOUNIT14_MD_MAX]; /* 0x10 */ /* variable length */ 1867 } MPI3_IO_UNIT_PAGE14, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE14, 1868 Mpi3IOUnitPage14_t, MPI3_POINTER pMpi3IOUnitPage14_t; 1869 1870 /**** Defines for the PageVersion field ****/ 1871 #define MPI3_IOUNIT14_PAGEVERSION (0x00) 1872 1873 /**** Defines for the Flags field ****/ 1874 #define MPI3_IOUNIT14_FLAGS_READONLY (0x01) 1875 1876 /***************************************************************************** 1877 * IO Unit Page 15 * 1878 ****************************************************************************/ 1879 1880 #ifndef MPI3_IOUNIT15_PBD_MAX 1881 #define MPI3_IOUNIT15_PBD_MAX (1) 1882 #endif /* MPI3_IOUNIT15_PBD_MAX */ 1883 1884 typedef struct _MPI3_IO_UNIT_PAGE15 1885 { 1886 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1887 U8 Flags; /* 0x08 */ 1888 U8 Reserved09[3]; /* 0x09 */ 1889 U32 Reserved0C; /* 0x0C */ 1890 U8 PowerBudgetingCapability; /* 0x10 */ 1891 U8 Reserved11[3]; /* 0x11 */ 1892 U8 NumPowerBudgetData; /* 0x14 */ 1893 U8 Reserved15[3]; /* 0x15 */ 1894 U32 PowerBudgetData[MPI3_IOUNIT15_PBD_MAX]; /* 0x18 */ /* variable length */ 1895 } MPI3_IO_UNIT_PAGE15, MPI3_POINTER PTR_MPI3_IO_UNIT_PAGE15, 1896 Mpi3IOUnitPage15_t, MPI3_POINTER pMpi3IOUnitPage15_t; 1897 1898 /**** Defines for the PageVersion field ****/ 1899 #define MPI3_IOUNIT15_PAGEVERSION (0x00) 1900 1901 /**** Defines for the Flags field ****/ 1902 #define MPI3_IOUNIT15_FLAGS_EPRINIT_INITREQUIRED (0x04) 1903 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_MASK (0x03) 1904 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_NOT_SUPPORTED (0x00) 1905 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITHOUT_POWER_BRAKE_GPIO (0x01) 1906 #define MPI3_IOUNIT15_FLAGS_EPRSUPPORT_WITH_POWER_BRAKE_GPIO (0x02) 1907 1908 /**** Defines for the NumPowerBudgetData field ****/ 1909 #define MPI3_IOUNIT15_NUMPOWERBUDGETDATA_POWER_BUDGETING_DISABLED (0x00) 1910 1911 /***************************************************************************** 1912 * IOC Configuration Pages * 1913 ****************************************************************************/ 1914 1915 /***************************************************************************** 1916 * IOC Page 0 * 1917 ****************************************************************************/ 1918 typedef struct _MPI3_IOC_PAGE0 1919 { 1920 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1921 U32 Reserved08; /* 0x08 */ 1922 U16 VendorID; /* 0x0C */ 1923 U16 DeviceID; /* 0x0E */ 1924 U8 RevisionID; /* 0x10 */ 1925 U8 Reserved11[3]; /* 0x11 */ 1926 U32 ClassCode; /* 0x14 */ 1927 U16 SubsystemVendorID; /* 0x18 */ 1928 U16 SubsystemID; /* 0x1A */ 1929 } MPI3_IOC_PAGE0, MPI3_POINTER PTR_MPI3_IOC_PAGE0, 1930 Mpi3IOCPage0_t, MPI3_POINTER pMpi3IOCPage0_t; 1931 1932 /**** Defines for the PageVersion field ****/ 1933 #define MPI3_IOC0_PAGEVERSION (0x00) 1934 1935 /***************************************************************************** 1936 * IOC Page 1 * 1937 ****************************************************************************/ 1938 typedef struct _MPI3_IOC_PAGE1 1939 { 1940 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1941 U32 CoalescingTimeout; /* 0x08 */ 1942 U8 CoalescingDepth; /* 0x0C */ 1943 U8 Obsolete; /* 0x0D */ 1944 U16 Reserved0E; /* 0x0E */ 1945 } MPI3_IOC_PAGE1, MPI3_POINTER PTR_MPI3_IOC_PAGE1, 1946 Mpi3IOCPage1_t, MPI3_POINTER pMpi3IOCPage1_t; 1947 1948 /**** Defines for the PageVersion field ****/ 1949 #define MPI3_IOC1_PAGEVERSION (0x00) 1950 1951 /***************************************************************************** 1952 * IOC Page 2 * 1953 ****************************************************************************/ 1954 #ifndef MPI3_IOC2_EVENTMASK_WORDS 1955 #define MPI3_IOC2_EVENTMASK_WORDS (4) 1956 #endif /* MPI3_IOC2_EVENTMASK_WORDS */ 1957 1958 typedef struct _MPI3_IOC_PAGE2 1959 { 1960 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 1961 U32 Reserved08; /* 0x08 */ 1962 U16 SASBroadcastPrimitiveMasks; /* 0x0C */ 1963 U16 SASNotifyPrimitiveMasks; /* 0x0E */ 1964 U32 EventMasks[MPI3_IOC2_EVENTMASK_WORDS]; /* 0x10 */ 1965 } MPI3_IOC_PAGE2, MPI3_POINTER PTR_MPI3_IOC_PAGE2, 1966 Mpi3IOCPage2_t, MPI3_POINTER pMpi3IOCPage2_t; 1967 1968 /**** Defines for the PageVersion field ****/ 1969 #define MPI3_IOC2_PAGEVERSION (0x00) 1970 1971 1972 /***************************************************************************** 1973 * Driver Configuration Pages * 1974 ****************************************************************************/ 1975 1976 /**** Defines for the Flags field ****/ 1977 #define MPI3_DRIVER_FLAGS_ADMINRAIDPD_BLOCKED (0x0010) 1978 #define MPI3_DRIVER_FLAGS_OOBRAIDPD_BLOCKED (0x0008) 1979 #define MPI3_DRIVER_FLAGS_OOBRAIDVD_BLOCKED (0x0004) 1980 #define MPI3_DRIVER_FLAGS_OOBADVHOSTPD_BLOCKED (0x0002) 1981 #define MPI3_DRIVER_FLAGS_OOBHOSTPD_BLOCKED (0x0001) 1982 1983 typedef struct _MPI3_ALLOWED_CMD_SCSI 1984 { 1985 U16 ServiceAction; /* 0x00 */ 1986 U8 OperationCode; /* 0x02 */ 1987 U8 CommandFlags; /* 0x03 */ 1988 } MPI3_ALLOWED_CMD_SCSI, MPI3_POINTER PTR_MPI3_ALLOWED_CMD_SCSI, 1989 Mpi3AllowedCmdScsi_t, MPI3_POINTER pMpi3AllowedCmdScsi_t; 1990 1991 typedef struct _MPI3_ALLOWED_CMD_ATA 1992 { 1993 U8 Subcommand; /* 0x00 */ 1994 U8 Reserved01; /* 0x01 */ 1995 U8 Command; /* 0x02 */ 1996 U8 CommandFlags; /* 0x03 */ 1997 } MPI3_ALLOWED_CMD_ATA, MPI3_POINTER PTR_MPI3_ALLOWED_CMD_ATA, 1998 Mpi3AllowedCmdAta_t, MPI3_POINTER pMpi3AllowedCmdAta_t; 1999 2000 typedef struct _MPI3_ALLOWED_CMD_NVME 2001 { 2002 U8 Reserved00; /* 0x00 */ 2003 U8 NVMeCmdFlags; /* 0x01 */ 2004 U8 OpCode; /* 0x02 */ 2005 U8 CommandFlags; /* 0x03 */ 2006 } MPI3_ALLOWED_CMD_NVME, MPI3_POINTER PTR_MPI3_ALLOWED_CMD_NVME, 2007 Mpi3AllowedCmdNvme_t, MPI3_POINTER pMpi3AllowedCmdNvme_t; 2008 2009 /**** Defines for the CommandFlags field ****/ 2010 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_MASK (0x80) 2011 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_IO (0x00) 2012 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_SUBQ_TYPE_ADMIN (0x80) 2013 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_MASK (0x3F) 2014 #define MPI3_DRIVER_ALLOWEDCMD_NVMECMDFLAGS_CMDSET_NVM (0x00) 2015 2016 typedef union _MPI3_ALLOWED_CMD 2017 { 2018 MPI3_ALLOWED_CMD_SCSI Scsi; 2019 MPI3_ALLOWED_CMD_ATA Ata; 2020 MPI3_ALLOWED_CMD_NVME NVMe; 2021 } MPI3_ALLOWED_CMD, MPI3_POINTER PTR_MPI3_ALLOWED_CMD, 2022 Mpi3AllowedCmd_t, MPI3_POINTER pMpi3AllowedCmd_t; 2023 2024 /**** Defines for the CommandFlags field ****/ 2025 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_ADMINRAIDPD_BLOCKED (0x20) 2026 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDPD_BLOCKED (0x10) 2027 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBRAIDVD_BLOCKED (0x08) 2028 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBADVHOSTPD_BLOCKED (0x04) 2029 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_OOBHOSTPD_BLOCKED (0x02) 2030 #define MPI3_DRIVER_ALLOWEDCMD_CMDFLAGS_CHECKSUBCMD_ENABLED (0x01) 2031 2032 2033 #ifndef MPI3_ALLOWED_CMDS_MAX 2034 #define MPI3_ALLOWED_CMDS_MAX (1) 2035 #endif /* MPI3_ALLOWED_CMDS_MAX */ 2036 2037 /***************************************************************************** 2038 * Driver Page 0 * 2039 ****************************************************************************/ 2040 typedef struct _MPI3_DRIVER_PAGE0 2041 { 2042 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2043 U32 BSDOptions; /* 0x08 */ 2044 U8 SSUTimeout; /* 0x0C */ 2045 U8 IOTimeout; /* 0x0D */ 2046 U8 TURRetries; /* 0x0E */ 2047 U8 TURInterval; /* 0x0F */ 2048 U8 Reserved10; /* 0x10 */ 2049 U8 SecurityKeyTimeout; /* 0x11 */ 2050 U16 Reserved12; /* 0x12 */ 2051 U32 Reserved14; /* 0x14 */ 2052 U32 Reserved18; /* 0x18 */ 2053 } MPI3_DRIVER_PAGE0, MPI3_POINTER PTR_MPI3_DRIVER_PAGE0, 2054 Mpi3DriverPage0_t, MPI3_POINTER pMpi3DriverPage0_t; 2055 2056 /**** Defines for the PageVersion field ****/ 2057 #define MPI3_DRIVER0_PAGEVERSION (0x00) 2058 2059 /**** Defines for the BSDOptions field ****/ 2060 #define MPI3_DRIVER0_BSDOPTS_HEADLESS_MODE_ENABLE (0x00000008) 2061 #define MPI3_DRIVER0_BSDOPTS_DIS_HII_CONFIG_UTIL (0x00000004) 2062 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_MASK (0x00000003) 2063 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_DEVS (0x00000000) 2064 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_ONLY (0x00000001) 2065 #define MPI3_DRIVER0_BSDOPTS_REGISTRATION_IOC_AND_INTERNAL_DEVS (0x00000002) 2066 2067 /***************************************************************************** 2068 * Driver Page 1 * 2069 ****************************************************************************/ 2070 typedef struct _MPI3_DRIVER_PAGE1 2071 { 2072 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2073 U32 Flags; /* 0x08 */ 2074 U32 Reserved0C; /* 0x0C */ 2075 U16 HostDiagTraceMaxSize; /* 0x10 */ 2076 U16 HostDiagTraceMinSize; /* 0x12 */ 2077 U16 HostDiagTraceDecrementSize; /* 0x14 */ 2078 U16 Reserved16; /* 0x16 */ 2079 U16 HostDiagFwMaxSize; /* 0x18 */ 2080 U16 HostDiagFwMinSize; /* 0x1A */ 2081 U16 HostDiagFwDecrementSize; /* 0x1C */ 2082 U16 Reserved1E; /* 0x1E */ 2083 U16 HostDiagDriverMaxSize; /* 0x20 */ 2084 U16 HostDiagDriverMinSize; /* 0x22 */ 2085 U16 HostDiagDriverDecrementSize; /* 0x24 */ 2086 U16 Reserved26; /* 0x26 */ 2087 } MPI3_DRIVER_PAGE1, MPI3_POINTER PTR_MPI3_DRIVER_PAGE1, 2088 Mpi3DriverPage1_t, MPI3_POINTER pMpi3DriverPage1_t; 2089 2090 /**** Defines for the PageVersion field ****/ 2091 #define MPI3_DRIVER1_PAGEVERSION (0x00) 2092 2093 /***************************************************************************** 2094 * Driver Page 2 * 2095 ****************************************************************************/ 2096 #ifndef MPI3_DRIVER2_TRIGGER_MAX 2097 #define MPI3_DRIVER2_TRIGGER_MAX (1) 2098 #endif /* MPI3_DRIVER2_TRIGGER_MAX */ 2099 2100 typedef struct _MPI3_DRIVER2_TRIGGER_EVENT 2101 { 2102 U8 Type; /* 0x00 */ 2103 U8 Flags; /* 0x01 */ 2104 U8 Reserved02; /* 0x02 */ 2105 U8 Event; /* 0x03 */ 2106 U32 Reserved04[3]; /* 0x04 */ 2107 } MPI3_DRIVER2_TRIGGER_EVENT, MPI3_POINTER PTR_MPI3_DRIVER2_TRIGGER_EVENT, 2108 Mpi3Driver2TriggerEvent_t, MPI3_POINTER pMpi3Driver2TriggerEvent_t; 2109 2110 typedef struct _MPI3_DRIVER2_TRIGGER_SCSI_SENSE 2111 { 2112 U8 Type; /* 0x00 */ 2113 U8 Flags; /* 0x01 */ 2114 U16 Reserved02; /* 0x02 */ 2115 U8 ASCQ; /* 0x04 */ 2116 U8 ASC; /* 0x05 */ 2117 U8 SenseKey; /* 0x06 */ 2118 U8 Reserved07; /* 0x07 */ 2119 U32 Reserved08[2]; /* 0x08 */ 2120 } MPI3_DRIVER2_TRIGGER_SCSI_SENSE, MPI3_POINTER PTR_MPI3_DRIVER2_TRIGGER_SCSI_SENSE, 2121 Mpi3Driver2TriggerScsiSense_t, MPI3_POINTER pMpi3Driver2TriggerScsiSense_t; 2122 2123 /**** Defines for the ASCQ field ****/ 2124 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASCQ_MATCH_ALL (0xFF) 2125 2126 /**** Defines for the ASC field ****/ 2127 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_ASC_MATCH_ALL (0xFF) 2128 2129 /**** Defines for the SenseKey field ****/ 2130 #define MPI3_DRIVER2_TRIGGER_SCSI_SENSE_SENSE_KEY_MATCH_ALL (0xFF) 2131 2132 typedef struct _MPI3_DRIVER2_TRIGGER_REPLY 2133 { 2134 U8 Type; /* 0x00 */ 2135 U8 Flags; /* 0x01 */ 2136 U16 IOCStatus; /* 0x02 */ 2137 U32 IOCLogInfo; /* 0x04 */ 2138 U32 IOCLogInfoMask; /* 0x08 */ 2139 U32 Reserved0C; /* 0x0C */ 2140 } MPI3_DRIVER2_TRIGGER_REPLY, MPI3_POINTER PTR_MPI3_DRIVER2_TRIGGER_REPLY, 2141 Mpi3Driver2TriggerReply_t, MPI3_POINTER pMpi3Driver2TriggerReply_t; 2142 2143 /**** Defines for the IOCStatus field ****/ 2144 #define MPI3_DRIVER2_TRIGGER_REPLY_IOCSTATUS_MATCH_ALL (0xFFFF) 2145 2146 typedef union _MPI3_DRIVER2_TRIGGER_ELEMENT 2147 { 2148 MPI3_DRIVER2_TRIGGER_EVENT Event; 2149 MPI3_DRIVER2_TRIGGER_SCSI_SENSE ScsiSense; 2150 MPI3_DRIVER2_TRIGGER_REPLY Reply; 2151 } MPI3_DRIVER2_TRIGGER_ELEMENT, MPI3_POINTER PTR_MPI3_DRIVER2_TRIGGER_ELEMENT, 2152 Mpi3Driver2TriggerElement_t, MPI3_POINTER pMpi3Driver2TriggerElement_t; 2153 2154 /**** Defines for the Type field ****/ 2155 #define MPI3_DRIVER2_TRIGGER_TYPE_EVENT (0x00) 2156 #define MPI3_DRIVER2_TRIGGER_TYPE_SCSI_SENSE (0x01) 2157 #define MPI3_DRIVER2_TRIGGER_TYPE_REPLY (0x02) 2158 2159 /**** Defines for the Flags field ****/ 2160 #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_TRACE_RELEASE (0x02) 2161 #define MPI3_DRIVER2_TRIGGER_FLAGS_DIAG_FW_RELEASE (0x01) 2162 2163 typedef struct _MPI3_DRIVER_PAGE2 2164 { 2165 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2166 U64 GlobalTrigger; /* 0x08 */ 2167 U32 Reserved10[3]; /* 0x10 */ 2168 U8 NumTriggers; /* 0x1C */ 2169 U8 Reserved1D[3]; /* 0x1D */ 2170 MPI3_DRIVER2_TRIGGER_ELEMENT Trigger[MPI3_DRIVER2_TRIGGER_MAX]; /* 0x20 */ /* variable length */ 2171 } MPI3_DRIVER_PAGE2, MPI3_POINTER PTR_MPI3_DRIVER_PAGE2, 2172 Mpi3DriverPage2_t, MPI3_POINTER pMpi3DriverPage2_t; 2173 2174 /**** Defines for the PageVersion field ****/ 2175 #define MPI3_DRIVER2_PAGEVERSION (0x00) 2176 2177 /**** Defines for the GlobalTrigger field ****/ 2178 #define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_TRACE_RELEASE (0x8000000000000000ULL) 2179 #define MPI3_DRIVER2_GLOBALTRIGGER_DIAG_FW_RELEASE (0x4000000000000000ULL) 2180 #define MPI3_DRIVER2_GLOBALTRIGGER_SNAPDUMP_ENABLED (0x2000000000000000ULL) 2181 #define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_TRACE_DISABLED (0x1000000000000000ULL) 2182 #define MPI3_DRIVER2_GLOBALTRIGGER_POST_DIAG_FW_DISABLED (0x0800000000000000ULL) 2183 #define MPI3_DRIVER2_GLOBALTRIGGER_DEVICE_REMOVAL_ENABLED (0x0000000000000004ULL) 2184 #define MPI3_DRIVER2_GLOBALTRIGGER_TASK_MANAGEMENT_ENABLED (0x0000000000000002ULL) 2185 2186 /***************************************************************************** 2187 * Driver Page 10 * 2188 ****************************************************************************/ 2189 2190 typedef struct _MPI3_DRIVER_PAGE10 2191 { 2192 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2193 U16 Flags; /* 0x08 */ 2194 U16 Reserved0A; /* 0x0A */ 2195 U8 NumAllowedCommands; /* 0x0C */ 2196 U8 Reserved0D[3]; /* 0x0D */ 2197 MPI3_ALLOWED_CMD AllowedCommand[MPI3_ALLOWED_CMDS_MAX]; /* 0x10 */ /* variable length */ 2198 } MPI3_DRIVER_PAGE10, MPI3_POINTER PTR_MPI3_DRIVER_PAGE10, 2199 Mpi3DriverPage10_t, MPI3_POINTER pMpi3DriverPage10_t; 2200 2201 /**** Defines for the PageVersion field ****/ 2202 #define MPI3_DRIVER10_PAGEVERSION (0x00) 2203 2204 /**** Defines for the Flags field - use MPI3_DRIVER_FLAGS_ defines ****/ 2205 2206 /***************************************************************************** 2207 * Driver Page 20 * 2208 ****************************************************************************/ 2209 2210 typedef struct _MPI3_DRIVER_PAGE20 2211 { 2212 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2213 U16 Flags; /* 0x08 */ 2214 U16 Reserved0A; /* 0x0A */ 2215 U8 NumAllowedCommands; /* 0x0C */ 2216 U8 Reserved0D[3]; /* 0x0D */ 2217 MPI3_ALLOWED_CMD AllowedCommand[MPI3_ALLOWED_CMDS_MAX]; /* 0x10 */ /* variable length */ 2218 } MPI3_DRIVER_PAGE20, MPI3_POINTER PTR_MPI3_DRIVER_PAGE20, 2219 Mpi3DriverPage20_t, MPI3_POINTER pMpi3DriverPage20_t; 2220 2221 /**** Defines for the PageVersion field ****/ 2222 #define MPI3_DRIVER20_PAGEVERSION (0x00) 2223 2224 /**** Defines for the Flags field - use MPI3_DRIVER_FLAGS_ defines ****/ 2225 2226 /***************************************************************************** 2227 * Driver Page 30 * 2228 ****************************************************************************/ 2229 2230 typedef struct _MPI3_DRIVER_PAGE30 2231 { 2232 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2233 U16 Flags; /* 0x08 */ 2234 U16 Reserved0A; /* 0x0A */ 2235 U8 NumAllowedCommands; /* 0x0C */ 2236 U8 Reserved0D[3]; /* 0x0D */ 2237 MPI3_ALLOWED_CMD AllowedCommand[MPI3_ALLOWED_CMDS_MAX]; /* 0x10 */ /* variable length */ 2238 } MPI3_DRIVER_PAGE30, MPI3_POINTER PTR_MPI3_DRIVER_PAGE30, 2239 Mpi3DriverPage30_t, MPI3_POINTER pMpi3DriverPage30_t; 2240 2241 /**** Defines for the PageVersion field ****/ 2242 #define MPI3_DRIVER30_PAGEVERSION (0x00) 2243 2244 /**** Defines for the Flags field - use MPI3_DRIVER_FLAGS_ defines ****/ 2245 2246 /***************************************************************************** 2247 * Security Configuration Pages * 2248 ****************************************************************************/ 2249 2250 typedef union _MPI3_SECURITY_MAC 2251 { 2252 U32 Dword[16]; 2253 U16 Word[32]; 2254 U8 Byte[64]; 2255 } MPI3_SECURITY_MAC, MPI3_POINTER PTR_MPI3_SECURITY_MAC, 2256 Mpi3SecurityMAC_t, MPI3_POINTER pMpi3SecurityMAC_t; 2257 2258 typedef union _MPI3_SECURITY_NONCE 2259 { 2260 U32 Dword[16]; 2261 U16 Word[32]; 2262 U8 Byte[64]; 2263 } MPI3_SECURITY_NONCE, MPI3_POINTER PTR_MPI3_SECURITY_NONCE, 2264 Mpi3SecurityNonce_t, MPI3_POINTER pMpi3SecurityNonce_t; 2265 2266 typedef union _MPI3_SECURITY_ROOT_DIGEST 2267 { 2268 U32 Dword[16]; 2269 U16 Word[32]; 2270 U8 Byte[64]; 2271 } MPI3_SECURITY_ROOT_DIGEST, MPI3_POINTER PTR_MPI3_SECURITY_ROOT_DIGEST, 2272 Mpi3SecurityRootDigest_t, MPI3_POINTER pMpi3SecurityRootDigest_t; 2273 2274 /***************************************************************************** 2275 * Security Page 0 * 2276 ****************************************************************************/ 2277 2278 typedef union _MPI3_SECURITY0_CERT_CHAIN 2279 { 2280 U32 Dword[1024]; 2281 U16 Word[2048]; 2282 U8 Byte[4096]; 2283 } MPI3_SECURITY0_CERT_CHAIN, MPI3_POINTER PTR_MPI3_SECURITY0_CERT_CHAIN, 2284 Mpi3Security0CertChain_t, MPI3_POINTER pMpi3Security0CertChain_t; 2285 2286 typedef struct _MPI3_SECURITY_PAGE0 2287 { 2288 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2289 U8 SlotNumGroup; /* 0x08 */ 2290 U8 SlotNum; /* 0x09 */ 2291 U16 CertChainLength; /* 0x0A */ 2292 U8 CertChainFlags; /* 0x0C */ 2293 U8 Reserved0D[3]; /* 0x0D */ 2294 U32 BaseAsymAlgo; /* 0x10 */ 2295 U32 BaseHashAlgo; /* 0x14 */ 2296 U32 Reserved18[4]; /* 0x18 */ 2297 MPI3_SECURITY_MAC Mac; /* 0x28 */ 2298 MPI3_SECURITY_NONCE Nonce; /* 0x68 */ 2299 MPI3_SECURITY0_CERT_CHAIN CertificateChain; /* 0xA8 */ 2300 } MPI3_SECURITY_PAGE0, MPI3_POINTER PTR_MPI3_SECURITY_PAGE0, 2301 Mpi3SecurityPage0_t, MPI3_POINTER pMpi3SecurityPage0_t; 2302 2303 /**** Defines for the PageVersion field ****/ 2304 #define MPI3_SECURITY0_PAGEVERSION (0x00) 2305 2306 /**** Defines for the CertChainFlags field ****/ 2307 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_MASK (0x0E) 2308 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_UNUSED (0x00) 2309 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_CERBERUS (0x02) 2310 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_AUTH_API_SPDM (0x04) 2311 #define MPI3_SECURITY0_CERTCHAIN_FLAGS_SEALED (0x01) 2312 2313 /***************************************************************************** 2314 * Security Page 1 * 2315 ****************************************************************************/ 2316 2317 #ifndef MPI3_SECURITY1_KEY_RECORD_MAX 2318 #define MPI3_SECURITY1_KEY_RECORD_MAX 1 2319 #endif /* MPI3_SECURITY1_KEY_RECORD_MAX */ 2320 2321 #ifndef MPI3_SECURITY1_PAD_MAX 2322 #define MPI3_SECURITY1_PAD_MAX 4 2323 #endif /* MPI3_SECURITY1_PAD_MAX */ 2324 2325 typedef union _MPI3_SECURITY1_KEY_DATA 2326 { 2327 U32 Dword[128]; 2328 U16 Word[256]; 2329 U8 Byte[512]; 2330 } MPI3_SECURITY1_KEY_DATA, MPI3_POINTER PTR_MPI3_SECURITY1_KEY_DATA, 2331 Mpi3Security1KeyData_t, MPI3_POINTER pMpi3Security1KeyData_t; 2332 2333 typedef struct _MPI3_SECURITY1_KEY_RECORD 2334 { 2335 U8 Flags; /* 0x00 */ 2336 U8 Consumer; /* 0x01 */ 2337 U16 KeyDataSize; /* 0x02 */ 2338 U32 AdditionalKeyData; /* 0x04 */ 2339 U32 Reserved08[2]; /* 0x08 */ 2340 MPI3_SECURITY1_KEY_DATA KeyData; /* 0x10 */ 2341 } MPI3_SECURITY1_KEY_RECORD, MPI3_POINTER PTR_MPI3_SECURITY1_KEY_RECORD, 2342 Mpi3Security1KeyRecord_t, MPI3_POINTER pMpi3Security1KeyRecord_t; 2343 2344 /**** Defines for the Flags field ****/ 2345 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_MASK (0x1F) 2346 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_NOT_VALID (0x00) 2347 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_HMAC (0x01) 2348 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_AES (0x02) 2349 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PRIVATE (0x03) 2350 #define MPI3_SECURITY1_KEY_RECORD_FLAGS_TYPE_ECDSA_PUBLIC (0x04) 2351 2352 /**** Defines for the Consumer field ****/ 2353 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_NOT_VALID (0x00) 2354 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_SAFESTORE (0x01) 2355 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CERT_CHAIN (0x02) 2356 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_DEVICE_KEY (0x03) 2357 #define MPI3_SECURITY1_KEY_RECORD_CONSUMER_CACHE_OFFLOAD (0x04) 2358 2359 typedef struct _MPI3_SECURITY_PAGE1 2360 { 2361 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2362 U32 Reserved08[2]; /* 0x08 */ 2363 MPI3_SECURITY_MAC Mac; /* 0x10 */ 2364 MPI3_SECURITY_NONCE Nonce; /* 0x50 */ 2365 U8 NumKeys; /* 0x90 */ 2366 U8 Reserved91[3]; /* 0x91 */ 2367 U32 Reserved94[3]; /* 0x94 */ 2368 MPI3_SECURITY1_KEY_RECORD KeyRecord[MPI3_SECURITY1_KEY_RECORD_MAX]; /* 0xA0 */ 2369 U8 Pad[MPI3_SECURITY1_PAD_MAX]; /* ?? */ 2370 } MPI3_SECURITY_PAGE1, MPI3_POINTER PTR_MPI3_SECURITY_PAGE1, 2371 Mpi3SecurityPage1_t, MPI3_POINTER pMpi3SecurityPage1_t; 2372 2373 /**** Defines for the PageVersion field ****/ 2374 #define MPI3_SECURITY1_PAGEVERSION (0x00) 2375 2376 2377 /***************************************************************************** 2378 * Security Page 2 * 2379 ****************************************************************************/ 2380 2381 #ifndef MPI3_SECURITY2_TRUSTED_ROOT_MAX 2382 #define MPI3_SECURITY2_TRUSTED_ROOT_MAX 1 2383 #endif /* MPI3_SECURITY2_TRUSTED_ROOT_MAX */ 2384 2385 typedef struct _MPI3_SECURITY2_TRUSTED_ROOT 2386 { 2387 U8 Level; /* 0x00 */ 2388 U8 HashAlgorithm; /* 0x01 */ 2389 U16 TrustedRootFlags; /* 0x02 */ 2390 U32 Reserved04[3]; /* 0x04 */ 2391 MPI3_SECURITY_ROOT_DIGEST RootDigest; /* 0x10 */ 2392 } MPI3_SECURITY2_TRUSTED_ROOT, MPI3_POINTER PTR_MPI3_SECURITY2_TRUSTED_ROOT, 2393 Mpi3Security2TrustedRoot_t, MPI3_POINTER pMpi3Security2TrustedRoot_t; 2394 2395 /**** Defines for the TrustedRootFlags field ****/ 2396 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_MASK (0x0006) 2397 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_SHIFT (1) 2398 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_HA_FIELD (0x0000) 2399 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_HASHALGOSOURCE_AKI (0x0002) 2400 #define MPI3_SECURITY2_TRUSTEDROOT_TRUSTEDROOTFLAGS_USERPROVISIONED_YES (0x0001) 2401 2402 typedef struct _MPI3_SECURITY_PAGE2 2403 { 2404 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2405 U32 Reserved08[2]; /* 0x08 */ 2406 MPI3_SECURITY_MAC Mac; /* 0x10 */ 2407 MPI3_SECURITY_NONCE Nonce; /* 0x50 */ 2408 U32 Reserved90[3]; /* 0x90 */ 2409 U8 NumRoots; /* 0x9C */ 2410 U8 Reserved9D[3]; /* 0x9D */ 2411 MPI3_SECURITY2_TRUSTED_ROOT TrustedRoot[MPI3_SECURITY2_TRUSTED_ROOT_MAX]; /* 0xA0 */ /* variable length */ 2412 } MPI3_SECURITY_PAGE2, MPI3_POINTER PTR_MPI3_SECURITY_PAGE2, 2413 Mpi3SecurityPage2_t, MPI3_POINTER pMpi3SecurityPage2_t; 2414 2415 /**** Defines for the PageVersion field ****/ 2416 #define MPI3_SECURITY2_PAGEVERSION (0x00) 2417 2418 2419 /***************************************************************************** 2420 * SAS IO Unit Configuration Pages * 2421 ****************************************************************************/ 2422 2423 /***************************************************************************** 2424 * SAS IO Unit Page 0 * 2425 ****************************************************************************/ 2426 typedef struct _MPI3_SAS_IO_UNIT0_PHY_DATA 2427 { 2428 U8 IOUnitPort; /* 0x00 */ 2429 U8 PortFlags; /* 0x01 */ 2430 U8 PhyFlags; /* 0x02 */ 2431 U8 NegotiatedLinkRate; /* 0x03 */ 2432 U16 ControllerPhyDeviceInfo; /* 0x04 */ 2433 U16 Reserved06; /* 0x06 */ 2434 U16 AttachedDevHandle; /* 0x08 */ 2435 U16 ControllerDevHandle; /* 0x0A */ 2436 U32 DiscoveryStatus; /* 0x0C */ 2437 U32 Reserved10; /* 0x10 */ 2438 } MPI3_SAS_IO_UNIT0_PHY_DATA, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT0_PHY_DATA, 2439 Mpi3SasIOUnit0PhyData_t, MPI3_POINTER pMpi3SasIOUnit0PhyData_t; 2440 2441 #ifndef MPI3_SAS_IO_UNIT0_PHY_MAX 2442 #define MPI3_SAS_IO_UNIT0_PHY_MAX (1) 2443 #endif /* MPI3_SAS_IO_UNIT0_PHY_MAX */ 2444 2445 typedef struct _MPI3_SAS_IO_UNIT_PAGE0 2446 { 2447 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2448 U32 Reserved08; /* 0x08 */ 2449 U8 NumPhys; /* 0x0C */ 2450 U8 InitStatus; /* 0x0D */ 2451 U16 Reserved0E; /* 0x0E */ 2452 MPI3_SAS_IO_UNIT0_PHY_DATA PhyData[MPI3_SAS_IO_UNIT0_PHY_MAX]; /* 0x10 */ 2453 } MPI3_SAS_IO_UNIT_PAGE0, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT_PAGE0, 2454 Mpi3SasIOUnitPage0_t, MPI3_POINTER pMpi3SasIOUnitPage0_t; 2455 2456 /**** Defines for the PageVersion field ****/ 2457 #define MPI3_SASIOUNIT0_PAGEVERSION (0x00) 2458 2459 /**** Defines for the InitStatus field ****/ 2460 #define MPI3_SASIOUNIT0_INITSTATUS_NO_ERRORS (0x00) 2461 #define MPI3_SASIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION (0x01) 2462 #define MPI3_SASIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED (0x02) 2463 #define MPI3_SASIOUNIT0_INITSTATUS_BAD_NUM_PHYS (0x04) 2464 #define MPI3_SASIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG (0x05) 2465 #define MPI3_SASIOUNIT0_INITSTATUS_HOST_PHYS_ENABLED (0x06) 2466 #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MIN (0xF0) 2467 #define MPI3_SASIOUNIT0_INITSTATUS_PRODUCT_SPECIFIC_MAX (0xFF) 2468 2469 /**** Defines for the PortFlags field ****/ 2470 #define MPI3_SASIOUNIT0_PORTFLAGS_DISC_IN_PROGRESS (0x08) 2471 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_MASK (0x03) 2472 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_IOUNIT1 (0x00) 2473 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_DYNAMIC (0x01) 2474 #define MPI3_SASIOUNIT0_PORTFLAGS_AUTO_PORT_CONFIG_BACKPLANE (0x02) 2475 2476 /**** Defines for the PhyFlags field ****/ 2477 #define MPI3_SASIOUNIT0_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2478 #define MPI3_SASIOUNIT0_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2479 #define MPI3_SASIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 2480 #define MPI3_SASIOUNIT0_PHYFLAGS_VIRTUAL_PHY (0x02) 2481 #define MPI3_SASIOUNIT0_PHYFLAGS_HOST_PHY (0x01) 2482 2483 /**** Use MPI3_SAS_NEG_LINK_RATE_ defines for the NegotiatedLinkRate field ****/ 2484 2485 /**** Use MPI3_SAS_DEVICE_INFO_ defines (see mpi30_sas.h) for the ControllerPhyDeviceInfo field ****/ 2486 2487 /**** Use MPI3_SAS_DISC_STATUS_ defines (see mpi30_ioc.h) for the DiscoveryStatus field ****/ 2488 2489 /***************************************************************************** 2490 * SAS IO Unit Page 1 * 2491 ****************************************************************************/ 2492 typedef struct _MPI3_SAS_IO_UNIT1_PHY_DATA 2493 { 2494 U8 IOUnitPort; /* 0x00 */ 2495 U8 PortFlags; /* 0x01 */ 2496 U8 PhyFlags; /* 0x02 */ 2497 U8 MaxMinLinkRate; /* 0x03 */ 2498 U16 ControllerPhyDeviceInfo; /* 0x04 */ 2499 U16 MaxTargetPortConnectTime; /* 0x06 */ 2500 U32 Reserved08; /* 0x08 */ 2501 } MPI3_SAS_IO_UNIT1_PHY_DATA, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT1_PHY_DATA, 2502 Mpi3SasIOUnit1PhyData_t, MPI3_POINTER pMpi3SasIOUnit1PhyData_t; 2503 2504 #ifndef MPI3_SAS_IO_UNIT1_PHY_MAX 2505 #define MPI3_SAS_IO_UNIT1_PHY_MAX (1) 2506 #endif /* MPI3_SAS_IO_UNIT1_PHY_MAX */ 2507 2508 typedef struct _MPI3_SAS_IO_UNIT_PAGE1 2509 { 2510 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2511 U16 ControlFlags; /* 0x08 */ 2512 U16 SASNarrowMaxQueueDepth; /* 0x0A */ 2513 U16 AdditionalControlFlags; /* 0x0C */ 2514 U16 SASWideMaxQueueDepth; /* 0x0E */ 2515 U8 NumPhys; /* 0x10 */ 2516 U8 SATAMaxQDepth; /* 0x11 */ 2517 U16 Reserved12; /* 0x12 */ 2518 MPI3_SAS_IO_UNIT1_PHY_DATA PhyData[MPI3_SAS_IO_UNIT1_PHY_MAX]; /* 0x14 */ 2519 } MPI3_SAS_IO_UNIT_PAGE1, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT_PAGE1, 2520 Mpi3SasIOUnitPage1_t, MPI3_POINTER pMpi3SasIOUnitPage1_t; 2521 2522 /**** Defines for the PageVersion field ****/ 2523 #define MPI3_SASIOUNIT1_PAGEVERSION (0x00) 2524 2525 /**** Defines for the ControlFlags field ****/ 2526 #define MPI3_SASIOUNIT1_CONTROL_CONTROLLER_DEVICE_SELF_TEST (0x8000) 2527 #define MPI3_SASIOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000) 2528 #define MPI3_SASIOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080) 2529 #define MPI3_SASIOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040) 2530 #define MPI3_SASIOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020) 2531 #define MPI3_SASIOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010) 2532 #define MPI3_SASIOUNIT1_CONTROL_TABLE_SUBTRACTIVE_ILLEGAL (0x0008) 2533 #define MPI3_SASIOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004) 2534 #define MPI3_SASIOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002) 2535 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_MASK (0x0001) 2536 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_DEVICE_NAME (0x0000) 2537 #define MPI3_SASIOUNIT1_CONTROL_HARD_RESET_SAS_ADDRESS (0x0001) 2538 2539 /**** Defines for the AdditionalControlFlags field ****/ 2540 #define MPI3_SASIOUNIT1_ACONTROL_DA_PERSIST_CONNECT (0x0100) 2541 #define MPI3_SASIOUNIT1_ACONTROL_MULTI_PORT_DOMAIN_ILLEGAL (0x0080) 2542 #define MPI3_SASIOUNIT1_ACONTROL_SATA_ASYNCHROUNOUS_NOTIFICATION (0x0040) 2543 #define MPI3_SASIOUNIT1_ACONTROL_INVALID_TOPOLOGY_CORRECTION (0x0020) 2544 #define MPI3_SASIOUNIT1_ACONTROL_PORT_ENABLE_ONLY_SATA_LINK_RESET (0x0010) 2545 #define MPI3_SASIOUNIT1_ACONTROL_OTHER_AFFILIATION_SATA_LINK_RESET (0x0008) 2546 #define MPI3_SASIOUNIT1_ACONTROL_SELF_AFFILIATION_SATA_LINK_RESET (0x0004) 2547 #define MPI3_SASIOUNIT1_ACONTROL_NO_AFFILIATION_SATA_LINK_RESET (0x0002) 2548 #define MPI3_SASIOUNIT1_ACONTROL_ALLOW_TABLE_TO_TABLE (0x0001) 2549 2550 /**** Defines for the PortFlags field ****/ 2551 #define MPI3_SASIOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01) 2552 2553 /**** Defines for the PhyFlags field ****/ 2554 #define MPI3_SASIOUNIT1_PHYFLAGS_INIT_PERSIST_CONNECT (0x40) 2555 #define MPI3_SASIOUNIT1_PHYFLAGS_TARG_PERSIST_CONNECT (0x20) 2556 #define MPI3_SASIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 2557 2558 /**** Defines for the MaxMinLinkRate field ****/ 2559 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_MASK (0xF0) 2560 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_SHIFT (4) 2561 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_6_0 (0xA0) 2562 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_12_0 (0xB0) 2563 #define MPI3_SASIOUNIT1_MMLR_MAX_RATE_22_5 (0xC0) 2564 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_MASK (0x0F) 2565 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_6_0 (0x0A) 2566 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_12_0 (0x0B) 2567 #define MPI3_SASIOUNIT1_MMLR_MIN_RATE_22_5 (0x0C) 2568 2569 /**** Use MPI3_SAS_DEVICE_INFO_ defines (see mpi30_sas.h) for the ControllerPhyDeviceInfo field ****/ 2570 2571 /***************************************************************************** 2572 * SAS IO Unit Page 2 * 2573 ****************************************************************************/ 2574 typedef struct _MPI3_SAS_IO_UNIT2_PHY_PM_SETTINGS 2575 { 2576 U8 ControlFlags; /* 0x00 */ 2577 U8 Reserved01; /* 0x01 */ 2578 U16 InactivityTimerExponent; /* 0x02 */ 2579 U8 SATAPartialTimeout; /* 0x04 */ 2580 U8 Reserved05; /* 0x05 */ 2581 U8 SATASlumberTimeout; /* 0x06 */ 2582 U8 Reserved07; /* 0x07 */ 2583 U8 SASPartialTimeout; /* 0x08 */ 2584 U8 Reserved09; /* 0x09 */ 2585 U8 SASSlumberTimeout; /* 0x0A */ 2586 U8 Reserved0B; /* 0x0B */ 2587 } MPI3_SAS_IO_UNIT2_PHY_PM_SETTINGS, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT2_PHY_PM_SETTINGS, 2588 Mpi3SasIOUnit2PhyPmSettings_t, MPI3_POINTER pMpi3SasIOUnit2PhyPmSettings_t; 2589 2590 #ifndef MPI3_SAS_IO_UNIT2_PHY_MAX 2591 #define MPI3_SAS_IO_UNIT2_PHY_MAX (1) 2592 #endif /* MPI3_SAS_IO_UNIT2_PHY_MAX */ 2593 2594 typedef struct _MPI3_SAS_IO_UNIT_PAGE2 2595 { 2596 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2597 U8 NumPhys; /* 0x08 */ 2598 U8 Reserved09[3]; /* 0x09 */ 2599 U32 Reserved0C; /* 0x0C */ 2600 MPI3_SAS_IO_UNIT2_PHY_PM_SETTINGS SASPhyPowerManagementSettings[MPI3_SAS_IO_UNIT2_PHY_MAX]; /* 0x10 */ 2601 } MPI3_SAS_IO_UNIT_PAGE2, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT_PAGE2, 2602 Mpi3SasIOUnitPage2_t, MPI3_POINTER pMpi3SasIOUnitPage2_t; 2603 2604 /**** Defines for the PageVersion field ****/ 2605 #define MPI3_SASIOUNIT2_PAGEVERSION (0x00) 2606 2607 /**** Defines for the ControlFlags field ****/ 2608 #define MPI3_SASIOUNIT2_CONTROL_SAS_SLUMBER_ENABLE (0x08) 2609 #define MPI3_SASIOUNIT2_CONTROL_SAS_PARTIAL_ENABLE (0x04) 2610 #define MPI3_SASIOUNIT2_CONTROL_SATA_SLUMBER_ENABLE (0x02) 2611 #define MPI3_SASIOUNIT2_CONTROL_SATA_PARTIAL_ENABLE (0x01) 2612 2613 /**** Defines for the InactivityTimerExponent field ****/ 2614 #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_MASK (0x7000) 2615 #define MPI3_SASIOUNIT2_ITE_SAS_SLUMBER_SHIFT (12) 2616 #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_MASK (0x0700) 2617 #define MPI3_SASIOUNIT2_ITE_SAS_PARTIAL_SHIFT (8) 2618 #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_MASK (0x0070) 2619 #define MPI3_SASIOUNIT2_ITE_SATA_SLUMBER_SHIFT (4) 2620 #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_MASK (0x0007) 2621 #define MPI3_SASIOUNIT2_ITE_SATA_PARTIAL_SHIFT (0) 2622 2623 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_SECONDS (7) 2624 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_SECOND (6) 2625 #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MILLISECONDS (5) 2626 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MILLISECONDS (4) 2627 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MILLISECOND (3) 2628 #define MPI3_SASIOUNIT2_ITE_EXP_HUNDRED_MICROSECONDS (2) 2629 #define MPI3_SASIOUNIT2_ITE_EXP_TEN_MICROSECONDS (1) 2630 #define MPI3_SASIOUNIT2_ITE_EXP_ONE_MICROSECOND (0) 2631 2632 /***************************************************************************** 2633 * SAS IO Unit Page 3 * 2634 ****************************************************************************/ 2635 typedef struct _MPI3_SAS_IO_UNIT_PAGE3 2636 { 2637 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2638 U32 Reserved08; /* 0x08 */ 2639 U32 PowerManagementCapabilities; /* 0x0C */ 2640 } MPI3_SAS_IO_UNIT_PAGE3, MPI3_POINTER PTR_MPI3_SAS_IO_UNIT_PAGE3, 2641 Mpi3SasIOUnitPage3_t, MPI3_POINTER pMpi3SasIOUnitPage3_t; 2642 2643 /**** Defines for the PageVersion field ****/ 2644 #define MPI3_SASIOUNIT3_PAGEVERSION (0x00) 2645 2646 /**** Defines for the PowerManagementCapabilities field ****/ 2647 #define MPI3_SASIOUNIT3_PM_HOST_SAS_SLUMBER_MODE (0x00000800) 2648 #define MPI3_SASIOUNIT3_PM_HOST_SAS_PARTIAL_MODE (0x00000400) 2649 #define MPI3_SASIOUNIT3_PM_HOST_SATA_SLUMBER_MODE (0x00000200) 2650 #define MPI3_SASIOUNIT3_PM_HOST_SATA_PARTIAL_MODE (0x00000100) 2651 #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_SLUMBER_MODE (0x00000008) 2652 #define MPI3_SASIOUNIT3_PM_IOUNIT_SAS_PARTIAL_MODE (0x00000004) 2653 #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_SLUMBER_MODE (0x00000002) 2654 #define MPI3_SASIOUNIT3_PM_IOUNIT_SATA_PARTIAL_MODE (0x00000001) 2655 2656 2657 /***************************************************************************** 2658 * SAS Expander Configuration Pages * 2659 ****************************************************************************/ 2660 2661 /***************************************************************************** 2662 * SAS Expander Page 0 * 2663 ****************************************************************************/ 2664 typedef struct _MPI3_SAS_EXPANDER_PAGE0 2665 { 2666 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2667 U8 IOUnitPort; /* 0x08 */ 2668 U8 ReportGenLength; /* 0x09 */ 2669 U16 EnclosureHandle; /* 0x0A */ 2670 U32 Reserved0C; /* 0x0C */ 2671 U64 SASAddress; /* 0x10 */ 2672 U32 DiscoveryStatus; /* 0x18 */ 2673 U16 DevHandle; /* 0x1C */ 2674 U16 ParentDevHandle; /* 0x1E */ 2675 U16 ExpanderChangeCount; /* 0x20 */ 2676 U16 ExpanderRouteIndexes; /* 0x22 */ 2677 U8 NumPhys; /* 0x24 */ 2678 U8 SASLevel; /* 0x25 */ 2679 U16 Flags; /* 0x26 */ 2680 U16 STPBusInactivityTimeLimit; /* 0x28 */ 2681 U16 STPMaxConnectTimeLimit; /* 0x2A */ 2682 U16 STP_SMP_NexusLossTime; /* 0x2C */ 2683 U16 MaxNumRoutedSASAddresses; /* 0x2E */ 2684 U64 ActiveZoneManagerSASAddress; /* 0x30 */ 2685 U16 ZoneLockInactivityLimit; /* 0x38 */ 2686 U16 Reserved3A; /* 0x3A */ 2687 U8 TimeToReducedFunc; /* 0x3C */ 2688 U8 InitialTimeToReducedFunc; /* 0x3D */ 2689 U8 MaxReducedFuncTime; /* 0x3E */ 2690 U8 ExpStatus; /* 0x3F */ 2691 } MPI3_SAS_EXPANDER_PAGE0, MPI3_POINTER PTR_MPI3_SAS_EXPANDER_PAGE0, 2692 Mpi3SasExpanderPage0_t, MPI3_POINTER pMpi3SasExpanderPage0_t; 2693 2694 /**** Defines for the PageVersion field ****/ 2695 #define MPI3_SASEXPANDER0_PAGEVERSION (0x00) 2696 2697 /**** Use MPI3_SAS_DISC_STATUS_ defines (see mpi30_ioc.h) for the DiscoveryStatus field ****/ 2698 2699 /**** Defines for the Flags field ****/ 2700 #define MPI3_SASEXPANDER0_FLAGS_REDUCED_FUNCTIONALITY (0x2000) 2701 #define MPI3_SASEXPANDER0_FLAGS_ZONE_LOCKED (0x1000) 2702 #define MPI3_SASEXPANDER0_FLAGS_SUPPORTED_PHYSICAL_PRES (0x0800) 2703 #define MPI3_SASEXPANDER0_FLAGS_ASSERTED_PHYSICAL_PRES (0x0400) 2704 #define MPI3_SASEXPANDER0_FLAGS_ZONING_SUPPORT (0x0200) 2705 #define MPI3_SASEXPANDER0_FLAGS_ENABLED_ZONING (0x0100) 2706 #define MPI3_SASEXPANDER0_FLAGS_TABLE_TO_TABLE_SUPPORT (0x0080) 2707 #define MPI3_SASEXPANDER0_FLAGS_CONNECTOR_END_DEVICE (0x0010) 2708 #define MPI3_SASEXPANDER0_FLAGS_OTHERS_CONFIG (0x0004) 2709 #define MPI3_SASEXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x0002) 2710 #define MPI3_SASEXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x0001) 2711 2712 /**** Defines for the ExpStatus field ****/ 2713 #define MPI3_SASEXPANDER0_ES_NOT_RESPONDING (0x02) 2714 #define MPI3_SASEXPANDER0_ES_RESPONDING (0x03) 2715 #define MPI3_SASEXPANDER0_ES_DELAY_NOT_RESPONDING (0x04) 2716 2717 /***************************************************************************** 2718 * SAS Expander Page 1 * 2719 ****************************************************************************/ 2720 typedef struct _MPI3_SAS_EXPANDER_PAGE1 2721 { 2722 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2723 U8 IOUnitPort; /* 0x08 */ 2724 U8 Reserved09[3]; /* 0x09 */ 2725 U8 NumPhys; /* 0x0C */ 2726 U8 Phy; /* 0x0D */ 2727 U16 NumTableEntriesProgrammed; /* 0x0E */ 2728 U8 ProgrammedLinkRate; /* 0x10 */ 2729 U8 HwLinkRate; /* 0x11 */ 2730 U16 AttachedDevHandle; /* 0x12 */ 2731 U32 PhyInfo; /* 0x14 */ 2732 U16 AttachedDeviceInfo; /* 0x18 */ 2733 U16 Reserved1A; /* 0x1A */ 2734 U16 ExpanderDevHandle; /* 0x1C */ 2735 U8 ChangeCount; /* 0x1E */ 2736 U8 NegotiatedLinkRate; /* 0x1F */ 2737 U8 PhyIdentifier; /* 0x20 */ 2738 U8 AttachedPhyIdentifier; /* 0x21 */ 2739 U8 Reserved22; /* 0x22 */ 2740 U8 DiscoveryInfo; /* 0x23 */ 2741 U32 AttachedPhyInfo; /* 0x24 */ 2742 U8 ZoneGroup; /* 0x28 */ 2743 U8 SelfConfigStatus; /* 0x29 */ 2744 U16 Reserved2A; /* 0x2A */ 2745 U16 Slot; /* 0x2C */ 2746 U16 SlotIndex; /* 0x2E */ 2747 } MPI3_SAS_EXPANDER_PAGE1, MPI3_POINTER PTR_MPI3_SAS_EXPANDER_PAGE1, 2748 Mpi3SasExpanderPage1_t, MPI3_POINTER pMpi3SasExpanderPage1_t; 2749 2750 /**** Defines for the PageVersion field ****/ 2751 #define MPI3_SASEXPANDER1_PAGEVERSION (0x00) 2752 2753 /**** Defines for the ProgrammedLinkRate field - use MPI3_SAS_PRATE_ defines ****/ 2754 2755 /**** Defines for the HwLinkRate field - use MPI3_SAS_HWRATE_ defines ****/ 2756 2757 /**** Defines for the PhyInfo field - use MPI3_SAS_PHYINFO_ defines ****/ 2758 2759 /**** Defines for the AttachedDeviceInfo field - use MPI3_SAS_DEVICE_INFO_ defines ****/ 2760 2761 /**** Defines for the NegotiatedLinkRate field - use use MPI3_SAS_NEG_LINK_RATE_ defines ****/ 2762 2763 /**** Defines for the DiscoveryInfo field ****/ 2764 #define MPI3_SASEXPANDER1_DISCINFO_BAD_PHY_DISABLED (0x04) 2765 #define MPI3_SASEXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02) 2766 #define MPI3_SASEXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01) 2767 2768 /**** Defines for the AttachedPhyInfo field - use MPI3_SAS_APHYINFO_ defines ****/ 2769 2770 /**** Defines for the Slot field - use MPI3_SLOT_ defines ****/ 2771 2772 /**** Defines for the SlotIndex field - use MPI3_SLOT_INDEX_ ****/ 2773 2774 2775 /***************************************************************************** 2776 * SAS Expander Page 2 * 2777 ****************************************************************************/ 2778 #ifndef MPI3_SASEXPANDER2_MAX_NUM_PHYS 2779 #define MPI3_SASEXPANDER2_MAX_NUM_PHYS (1) 2780 #endif /* MPI3_SASEXPANDER2_MAX_NUM_PHYS */ 2781 2782 typedef struct _MPI3_SASEXPANDER2_PHY_ELEMENT 2783 { 2784 U8 LinkChangeCount; /* 0x00 */ 2785 U8 Reserved01; /* 0x01 */ 2786 U16 RateChangeCount; /* 0x02 */ 2787 U32 Reserved04; /* 0x04 */ 2788 } MPI3_SASEXPANDER2_PHY_ELEMENT, MPI3_POINTER PTR_MPI3_SASEXPANDER2_PHY_ELEMENT, 2789 Mpi3SasExpander2PhyElement_t, MPI3_POINTER pMpi3SasExpander2PhyElement_t; 2790 2791 typedef struct _MPI3_SAS_EXPANDER_PAGE2 2792 { 2793 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2794 U8 NumPhys; /* 0x08 */ 2795 U8 Reserved09; /* 0x09 */ 2796 U16 DevHandle; /* 0x0A */ 2797 U32 Reserved0C; /* 0x0C */ 2798 MPI3_SASEXPANDER2_PHY_ELEMENT Phy[MPI3_SASEXPANDER2_MAX_NUM_PHYS]; /* 0x10 */ /* variable length */ 2799 2800 } MPI3_SAS_EXPANDER_PAGE2, MPI3_POINTER PTR_MPI3_SAS_EXPANDER_PAGE2, 2801 Mpi3SasExpanderPage2_t, MPI3_POINTER pMpi3SasExpanderPage2_t; 2802 2803 /**** Defines for the PageVersion field ****/ 2804 #define MPI3_SASEXPANDER2_PAGEVERSION (0x00) 2805 2806 2807 /***************************************************************************** 2808 * SAS Port Configuration Pages * 2809 ****************************************************************************/ 2810 2811 /***************************************************************************** 2812 * SAS Port Page 0 * 2813 ****************************************************************************/ 2814 typedef struct _MPI3_SAS_PORT_PAGE0 2815 { 2816 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2817 U8 PortNumber; /* 0x08 */ 2818 U8 Reserved09; /* 0x09 */ 2819 U8 PortWidth; /* 0x0A */ 2820 U8 Reserved0B; /* 0x0B */ 2821 U8 ZoneGroup; /* 0x0C */ 2822 U8 Reserved0D[3]; /* 0x0D */ 2823 U64 SASAddress; /* 0x10 */ 2824 U16 DeviceInfo; /* 0x18 */ 2825 U16 Reserved1A; /* 0x1A */ 2826 U32 Reserved1C; /* 0x1C */ 2827 } MPI3_SAS_PORT_PAGE0, MPI3_POINTER PTR_MPI3_SAS_PORT_PAGE0, 2828 Mpi3SasPortPage0_t, MPI3_POINTER pMpi3SasPortPage0_t; 2829 2830 /**** Defines for the PageVersion field ****/ 2831 #define MPI3_SASPORT0_PAGEVERSION (0x00) 2832 2833 /**** Defines for the DeviceInfo field - use MPI3_SAS_DEVICE_INFO_ defines ****/ 2834 2835 /***************************************************************************** 2836 * SAS PHY Configuration Pages * 2837 ****************************************************************************/ 2838 2839 /***************************************************************************** 2840 * SAS PHY Page 0 * 2841 ****************************************************************************/ 2842 typedef struct _MPI3_SAS_PHY_PAGE0 2843 { 2844 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2845 U16 OwnerDevHandle; /* 0x08 */ 2846 U16 Reserved0A; /* 0x0A */ 2847 U16 AttachedDevHandle; /* 0x0C */ 2848 U8 AttachedPhyIdentifier; /* 0x0E */ 2849 U8 Reserved0F; /* 0x0F */ 2850 U32 AttachedPhyInfo; /* 0x10 */ 2851 U8 ProgrammedLinkRate; /* 0x14 */ 2852 U8 HwLinkRate; /* 0x15 */ 2853 U8 ChangeCount; /* 0x16 */ 2854 U8 Flags; /* 0x17 */ 2855 U32 PhyInfo; /* 0x18 */ 2856 U8 NegotiatedLinkRate; /* 0x1C */ 2857 U8 Reserved1D[3]; /* 0x1D */ 2858 U16 Slot; /* 0x20 */ 2859 U16 SlotIndex; /* 0x22 */ 2860 } MPI3_SAS_PHY_PAGE0, MPI3_POINTER PTR_MPI3_SAS_PHY_PAGE0, 2861 Mpi3SasPhyPage0_t, MPI3_POINTER pMpi3SasPhyPage0_t; 2862 2863 /**** Defines for the PageVersion field ****/ 2864 #define MPI3_SASPHY0_PAGEVERSION (0x00) 2865 2866 /**** Defines for the AttachedPhyInfo field - use MPI3_SAS_APHYINFO_ defines ****/ 2867 2868 /**** Defines for the ProgrammedLinkRate field - use MPI3_SAS_PRATE_ defines ****/ 2869 2870 /**** Defines for the HwLinkRate field - use MPI3_SAS_HWRATE_ defines ****/ 2871 2872 /**** Defines for the Flags field ****/ 2873 #define MPI3_SASPHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01) 2874 2875 /**** Defines for the PhyInfo field - use MPI3_SAS_PHYINFO_ defines ****/ 2876 2877 /**** Defines for the NegotiatedLinkRate field - use MPI3_SAS_NEG_LINK_RATE_ defines ****/ 2878 2879 /**** Defines for the Slot field - use MPI3_SLOT_ defines ****/ 2880 2881 /**** Defines for the SlotIndex field - use MPI3_SLOT_INDEX_ ****/ 2882 2883 /***************************************************************************** 2884 * SAS PHY Page 1 * 2885 ****************************************************************************/ 2886 typedef struct _MPI3_SAS_PHY_PAGE1 2887 { 2888 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2889 U32 Reserved08; /* 0x08 */ 2890 U32 InvalidDwordCount; /* 0x0C */ 2891 U32 RunningDisparityErrorCount; /* 0x10 */ 2892 U32 LossDwordSynchCount; /* 0x14 */ 2893 U32 PhyResetProblemCount; /* 0x18 */ 2894 } MPI3_SAS_PHY_PAGE1, MPI3_POINTER PTR_MPI3_SAS_PHY_PAGE1, 2895 Mpi3SasPhyPage1_t, MPI3_POINTER pMpi3SasPhyPage1_t; 2896 2897 /**** Defines for the PageVersion field ****/ 2898 #define MPI3_SASPHY1_PAGEVERSION (0x00) 2899 2900 /***************************************************************************** 2901 * SAS PHY Page 2 * 2902 ****************************************************************************/ 2903 typedef struct _MPI3_SAS_PHY2_PHY_EVENT 2904 { 2905 U8 PhyEventCode; /* 0x00 */ 2906 U8 Reserved01[3]; /* 0x01 */ 2907 U32 PhyEventInfo; /* 0x04 */ 2908 } MPI3_SAS_PHY2_PHY_EVENT, MPI3_POINTER PTR_MPI3_SAS_PHY2_PHY_EVENT, 2909 Mpi3SasPhy2PhyEvent_t, MPI3_POINTER pMpi3SasPhy2PhyEvent_t; 2910 2911 /**** Defines for the PhyEventCode field - use MPI3_SASPHY3_EVENT_CODE_ defines */ 2912 2913 #ifndef MPI3_SAS_PHY2_PHY_EVENT_MAX 2914 #define MPI3_SAS_PHY2_PHY_EVENT_MAX (1) 2915 #endif /* MPI3_SAS_PHY2_PHY_EVENT_MAX */ 2916 2917 typedef struct _MPI3_SAS_PHY_PAGE2 2918 { 2919 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 2920 U32 Reserved08; /* 0x08 */ 2921 U8 NumPhyEvents; /* 0x0C */ 2922 U8 Reserved0D[3]; /* 0x0D */ 2923 MPI3_SAS_PHY2_PHY_EVENT PhyEvent[MPI3_SAS_PHY2_PHY_EVENT_MAX]; /* 0x10 */ 2924 } MPI3_SAS_PHY_PAGE2, MPI3_POINTER PTR_MPI3_SAS_PHY_PAGE2, 2925 Mpi3SasPhyPage2_t, MPI3_POINTER pMpi3SasPhyPage2_t; 2926 2927 /**** Defines for the PageVersion field ****/ 2928 #define MPI3_SASPHY2_PAGEVERSION (0x00) 2929 2930 /***************************************************************************** 2931 * SAS PHY Page 3 * 2932 ****************************************************************************/ 2933 typedef struct _MPI3_SAS_PHY3_PHY_EVENT_CONFIG 2934 { 2935 U8 PhyEventCode; /* 0x00 */ 2936 U8 Reserved01[3]; /* 0x01 */ 2937 U8 CounterType; /* 0x04 */ 2938 U8 ThresholdWindow; /* 0x05 */ 2939 U8 TimeUnits; /* 0x06 */ 2940 U8 Reserved07; /* 0x07 */ 2941 U32 EventThreshold; /* 0x08 */ 2942 U16 ThresholdFlags; /* 0x0C */ 2943 U16 Reserved0E; /* 0x0E */ 2944 } MPI3_SAS_PHY3_PHY_EVENT_CONFIG, MPI3_POINTER PTR_MPI3_SAS_PHY3_PHY_EVENT_CONFIG, 2945 Mpi3SasPhy3PhyEventConfig_t, MPI3_POINTER pMpi3SasPhy3PhyEventConfig_t; 2946 2947 /**** Defines for the PhyEventCode field ****/ 2948 #define MPI3_SASPHY3_EVENT_CODE_NO_EVENT (0x00) 2949 #define MPI3_SASPHY3_EVENT_CODE_INVALID_DWORD (0x01) 2950 #define MPI3_SASPHY3_EVENT_CODE_RUNNING_DISPARITY_ERROR (0x02) 2951 #define MPI3_SASPHY3_EVENT_CODE_LOSS_DWORD_SYNC (0x03) 2952 #define MPI3_SASPHY3_EVENT_CODE_PHY_RESET_PROBLEM (0x04) 2953 #define MPI3_SASPHY3_EVENT_CODE_ELASTICITY_BUF_OVERFLOW (0x05) 2954 #define MPI3_SASPHY3_EVENT_CODE_RX_ERROR (0x06) 2955 #define MPI3_SASPHY3_EVENT_CODE_INV_SPL_PACKETS (0x07) 2956 #define MPI3_SASPHY3_EVENT_CODE_LOSS_SPL_PACKET_SYNC (0x08) 2957 #define MPI3_SASPHY3_EVENT_CODE_RX_ADDR_FRAME_ERROR (0x20) 2958 #define MPI3_SASPHY3_EVENT_CODE_TX_AC_OPEN_REJECT (0x21) 2959 #define MPI3_SASPHY3_EVENT_CODE_RX_AC_OPEN_REJECT (0x22) 2960 #define MPI3_SASPHY3_EVENT_CODE_TX_RC_OPEN_REJECT (0x23) 2961 #define MPI3_SASPHY3_EVENT_CODE_RX_RC_OPEN_REJECT (0x24) 2962 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_PARTIAL_WAITING_ON (0x25) 2963 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP_CONNECT_WAITING_ON (0x26) 2964 #define MPI3_SASPHY3_EVENT_CODE_TX_BREAK (0x27) 2965 #define MPI3_SASPHY3_EVENT_CODE_RX_BREAK (0x28) 2966 #define MPI3_SASPHY3_EVENT_CODE_BREAK_TIMEOUT (0x29) 2967 #define MPI3_SASPHY3_EVENT_CODE_CONNECTION (0x2A) 2968 #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_PATHWAY_BLOCKED (0x2B) 2969 #define MPI3_SASPHY3_EVENT_CODE_PEAKTX_ARB_WAIT_TIME (0x2C) 2970 #define MPI3_SASPHY3_EVENT_CODE_PEAK_ARB_WAIT_TIME (0x2D) 2971 #define MPI3_SASPHY3_EVENT_CODE_PEAK_CONNECT_TIME (0x2E) 2972 #define MPI3_SASPHY3_EVENT_CODE_PERSIST_CONN (0x2F) 2973 #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_FRAMES (0x40) 2974 #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_FRAMES (0x41) 2975 #define MPI3_SASPHY3_EVENT_CODE_TX_SSP_ERROR_FRAMES (0x42) 2976 #define MPI3_SASPHY3_EVENT_CODE_RX_SSP_ERROR_FRAMES (0x43) 2977 #define MPI3_SASPHY3_EVENT_CODE_TX_CREDIT_BLOCKED (0x44) 2978 #define MPI3_SASPHY3_EVENT_CODE_RX_CREDIT_BLOCKED (0x45) 2979 #define MPI3_SASPHY3_EVENT_CODE_TX_SATA_FRAMES (0x50) 2980 #define MPI3_SASPHY3_EVENT_CODE_RX_SATA_FRAMES (0x51) 2981 #define MPI3_SASPHY3_EVENT_CODE_SATA_OVERFLOW (0x52) 2982 #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_FRAMES (0x60) 2983 #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_FRAMES (0x61) 2984 #define MPI3_SASPHY3_EVENT_CODE_RX_SMP_ERROR_FRAMES (0x63) 2985 #define MPI3_SASPHY3_EVENT_CODE_HOTPLUG_TIMEOUT (0xD0) 2986 #define MPI3_SASPHY3_EVENT_CODE_MISALIGNED_MUX_PRIMITIVE (0xD1) 2987 #define MPI3_SASPHY3_EVENT_CODE_RX_AIP (0xD2) 2988 #define MPI3_SASPHY3_EVENT_CODE_LCARB_WAIT_TIME (0xD3) 2989 #define MPI3_SASPHY3_EVENT_CODE_RCVD_CONN_RESP_WAIT_TIME (0xD4) 2990 #define MPI3_SASPHY3_EVENT_CODE_LCCONN_TIME (0xD5) 2991 #define MPI3_SASPHY3_EVENT_CODE_SSP_TX_START_TRANSMIT (0xD6) 2992 #define MPI3_SASPHY3_EVENT_CODE_SATA_TX_START (0xD7) 2993 #define MPI3_SASPHY3_EVENT_CODE_SMP_TX_START_TRANSMT (0xD8) 2994 #define MPI3_SASPHY3_EVENT_CODE_TX_SMP_BREAK_CONN (0xD9) 2995 #define MPI3_SASPHY3_EVENT_CODE_SSP_RX_START_RECEIVE (0xDA) 2996 #define MPI3_SASPHY3_EVENT_CODE_SATA_RX_START_RECEIVE (0xDB) 2997 #define MPI3_SASPHY3_EVENT_CODE_SMP_RX_START_RECEIVE (0xDC) 2998 2999 /**** Defines for the CounterType field ****/ 3000 #define MPI3_SASPHY3_COUNTER_TYPE_WRAPPING (0x00) 3001 #define MPI3_SASPHY3_COUNTER_TYPE_SATURATING (0x01) 3002 #define MPI3_SASPHY3_COUNTER_TYPE_PEAK_VALUE (0x02) 3003 3004 /**** Defines for the TimeUnits field ****/ 3005 #define MPI3_SASPHY3_TIME_UNITS_10_MICROSECONDS (0x00) 3006 #define MPI3_SASPHY3_TIME_UNITS_100_MICROSECONDS (0x01) 3007 #define MPI3_SASPHY3_TIME_UNITS_1_MILLISECOND (0x02) 3008 #define MPI3_SASPHY3_TIME_UNITS_10_MILLISECONDS (0x03) 3009 3010 /**** Defines for the ThresholdFlags field ****/ 3011 #define MPI3_SASPHY3_TFLAGS_PHY_RESET (0x0002) 3012 #define MPI3_SASPHY3_TFLAGS_EVENT_NOTIFY (0x0001) 3013 3014 #ifndef MPI3_SAS_PHY3_PHY_EVENT_MAX 3015 #define MPI3_SAS_PHY3_PHY_EVENT_MAX (1) 3016 #endif /* MPI3_SAS_PHY3_PHY_EVENT_MAX */ 3017 3018 typedef struct _MPI3_SAS_PHY_PAGE3 3019 { 3020 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3021 U32 Reserved08; /* 0x08 */ 3022 U8 NumPhyEvents; /* 0x0C */ 3023 U8 Reserved0D[3]; /* 0x0D */ 3024 MPI3_SAS_PHY3_PHY_EVENT_CONFIG PhyEventConfig[MPI3_SAS_PHY3_PHY_EVENT_MAX]; /* 0x10 */ 3025 } MPI3_SAS_PHY_PAGE3, MPI3_POINTER PTR_MPI3_SAS_PHY_PAGE3, 3026 Mpi3SasPhyPage3_t, MPI3_POINTER pMpi3SasPhyPage3_t; 3027 3028 /**** Defines for the PageVersion field ****/ 3029 #define MPI3_SASPHY3_PAGEVERSION (0x00) 3030 3031 /***************************************************************************** 3032 * SAS PHY Page 4 * 3033 ****************************************************************************/ 3034 typedef struct _MPI3_SAS_PHY_PAGE4 3035 { 3036 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3037 U8 Reserved08[3]; /* 0x08 */ 3038 U8 Flags; /* 0x0B */ 3039 U8 InitialFrame[28]; /* 0x0C */ 3040 } MPI3_SAS_PHY_PAGE4, MPI3_POINTER PTR_MPI3_SAS_PHY_PAGE4, 3041 Mpi3SasPhyPage4_t, MPI3_POINTER pMpi3SasPhyPage4_t; 3042 3043 /**** Defines for the PageVersion field ****/ 3044 #define MPI3_SASPHY4_PAGEVERSION (0x00) 3045 3046 /**** Defines for the Flags field ****/ 3047 #define MPI3_SASPHY4_FLAGS_FRAME_VALID (0x02) 3048 #define MPI3_SASPHY4_FLAGS_SATA_FRAME (0x01) 3049 3050 3051 /***************************************************************************** 3052 * Common definitions used by PCIe Configuration Pages * 3053 ****************************************************************************/ 3054 3055 /**** Defines for Negotiated Link Rates ****/ 3056 #define MPI3_PCIE_LINK_RETIMERS_MASK (0x30) 3057 #define MPI3_PCIE_LINK_RETIMERS_SHIFT (4) 3058 #define MPI3_PCIE_NEG_LINK_RATE_MASK (0x0F) 3059 #define MPI3_PCIE_NEG_LINK_RATE_UNKNOWN (0x00) 3060 #define MPI3_PCIE_NEG_LINK_RATE_PHY_DISABLED (0x01) 3061 #define MPI3_PCIE_NEG_LINK_RATE_2_5 (0x02) 3062 #define MPI3_PCIE_NEG_LINK_RATE_5_0 (0x03) 3063 #define MPI3_PCIE_NEG_LINK_RATE_8_0 (0x04) 3064 #define MPI3_PCIE_NEG_LINK_RATE_16_0 (0x05) 3065 #define MPI3_PCIE_NEG_LINK_RATE_32_0 (0x06) 3066 3067 /**** Defines for Enabled ASPM States ****/ 3068 #define MPI3_PCIE_ASPM_ENABLE_NONE (0x0) 3069 #define MPI3_PCIE_ASPM_ENABLE_L0s (0x1) 3070 #define MPI3_PCIE_ASPM_ENABLE_L1 (0x2) 3071 #define MPI3_PCIE_ASPM_ENABLE_L0s_L1 (0x3) 3072 3073 /**** Defines for Enabled ASPM States ****/ 3074 #define MPI3_PCIE_ASPM_SUPPORT_NONE (0x0) 3075 #define MPI3_PCIE_ASPM_SUPPORT_L0s (0x1) 3076 #define MPI3_PCIE_ASPM_SUPPORT_L1 (0x2) 3077 #define MPI3_PCIE_ASPM_SUPPORT_L0s_L1 (0x3) 3078 3079 /***************************************************************************** 3080 * PCIe IO Unit Configuration Pages * 3081 ****************************************************************************/ 3082 3083 /***************************************************************************** 3084 * PCIe IO Unit Page 0 * 3085 ****************************************************************************/ 3086 typedef struct _MPI3_PCIE_IO_UNIT0_PHY_DATA 3087 { 3088 U8 Link; /* 0x00 */ 3089 U8 LinkFlags; /* 0x01 */ 3090 U8 PhyFlags; /* 0x02 */ 3091 U8 NegotiatedLinkRate; /* 0x03 */ 3092 U16 AttachedDevHandle; /* 0x04 */ 3093 U16 ControllerDevHandle; /* 0x06 */ 3094 U32 EnumerationStatus; /* 0x08 */ 3095 U8 IOUnitPort; /* 0x0C */ 3096 U8 Reserved0D[3]; /* 0x0D */ 3097 } MPI3_PCIE_IO_UNIT0_PHY_DATA, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT0_PHY_DATA, 3098 Mpi3PcieIOUnit0PhyData_t, MPI3_POINTER pMpi3PcieIOUnit0PhyData_t; 3099 3100 /**** Defines for the LinkFlags field ****/ 3101 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_MASK (0x10) 3102 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_IOUNIT1 (0x00) 3103 #define MPI3_PCIEIOUNIT0_LINKFLAGS_CONFIG_SOURCE_BKPLANE (0x10) 3104 #define MPI3_PCIEIOUNIT0_LINKFLAGS_ENUM_IN_PROGRESS (0x08) 3105 3106 /**** Defines for the PhyFlags field ****/ 3107 #define MPI3_PCIEIOUNIT0_PHYFLAGS_PHY_DISABLED (0x08) 3108 #define MPI3_PCIEIOUNIT0_PHYFLAGS_HOST_PHY (0x01) 3109 3110 /**** Defines for the NegotiatedLinkRate field - use MPI3_PCIE_NEG_LINK_RATE_ defines ****/ 3111 3112 /**** Defines for the EnumerationStatus field ****/ 3113 #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCH_DEPTH_EXCEEDED (0x80000000) 3114 #define MPI3_PCIEIOUNIT0_ES_MAX_SWITCHES_EXCEEDED (0x40000000) 3115 #define MPI3_PCIEIOUNIT0_ES_MAX_ENDPOINTS_EXCEEDED (0x20000000) 3116 #define MPI3_PCIEIOUNIT0_ES_INSUFFICIENT_RESOURCES (0x10000000) 3117 3118 #ifndef MPI3_PCIE_IO_UNIT0_PHY_MAX 3119 #define MPI3_PCIE_IO_UNIT0_PHY_MAX (1) 3120 #endif /* MPI3_PCIE_IO_UNIT0_PHY_MAX */ 3121 3122 typedef struct _MPI3_PCIE_IO_UNIT_PAGE0 3123 { 3124 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3125 U32 Reserved08; /* 0x08 */ 3126 U8 NumPhys; /* 0x0C */ 3127 U8 InitStatus; /* 0x0D */ 3128 U8 ASPM; /* 0x0E */ 3129 U8 Reserved0F; /* 0x0F */ 3130 MPI3_PCIE_IO_UNIT0_PHY_DATA PhyData[MPI3_PCIE_IO_UNIT0_PHY_MAX]; /* 0x10 */ 3131 } MPI3_PCIE_IO_UNIT_PAGE0, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT_PAGE0, 3132 Mpi3PcieIOUnitPage0_t, MPI3_POINTER pMpi3PcieIOUnitPage0_t; 3133 3134 /**** Defines for the PageVersion field ****/ 3135 #define MPI3_PCIEIOUNIT0_PAGEVERSION (0x00) 3136 3137 /**** Defines for the InitStatus field ****/ 3138 #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_ERRORS (0x00) 3139 #define MPI3_PCIEIOUNIT0_INITSTATUS_NEEDS_INITIALIZATION (0x01) 3140 #define MPI3_PCIEIOUNIT0_INITSTATUS_NO_TARGETS_ALLOCATED (0x02) 3141 #define MPI3_PCIEIOUNIT0_INITSTATUS_RESOURCE_ALLOC_FAILED (0x03) 3142 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_NUM_PHYS (0x04) 3143 #define MPI3_PCIEIOUNIT0_INITSTATUS_UNSUPPORTED_CONFIG (0x05) 3144 #define MPI3_PCIEIOUNIT0_INITSTATUS_HOST_PORT_MISMATCH (0x06) 3145 #define MPI3_PCIEIOUNIT0_INITSTATUS_PHYS_NOT_CONSECUTIVE (0x07) 3146 #define MPI3_PCIEIOUNIT0_INITSTATUS_BAD_CLOCKING_MODE (0x08) 3147 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_START (0xF0) 3148 #define MPI3_PCIEIOUNIT0_INITSTATUS_PROD_SPEC_END (0xFF) 3149 3150 /**** Defines for the ASPM field ****/ 3151 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_MASK (0xC0) 3152 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_STATES_SHIFT (6) 3153 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_MASK (0x30) 3154 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_STATES_SHIFT (4) 3155 /*** use MPI3_PCIE_ASPM_ENABLE_ defines for field values ***/ 3156 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_MASK (0x0C) 3157 #define MPI3_PCIEIOUNIT0_ASPM_SWITCH_SUPPORT_SHIFT (2) 3158 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_MASK (0x03) 3159 #define MPI3_PCIEIOUNIT0_ASPM_DIRECT_SUPPORT_SHIFT (0) 3160 /*** use MPI3_PCIE_ASPM_SUPPORT_ defines for field values ***/ 3161 3162 /***************************************************************************** 3163 * PCIe IO Unit Page 1 * 3164 ****************************************************************************/ 3165 typedef struct _MPI3_PCIE_IO_UNIT1_PHY_DATA 3166 { 3167 U8 Link; /* 0x00 */ 3168 U8 LinkFlags; /* 0x01 */ 3169 U8 PhyFlags; /* 0x02 */ 3170 U8 MaxMinLinkRate; /* 0x03 */ 3171 U32 Reserved04; /* 0x04 */ 3172 U32 Reserved08; /* 0x08 */ 3173 } MPI3_PCIE_IO_UNIT1_PHY_DATA, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT1_PHY_DATA, 3174 Mpi3PcieIOUnit1PhyData_t, MPI3_POINTER pMpi3PcieIOUnit1PhyData_t; 3175 3176 /**** Defines for the LinkFlags field ****/ 3177 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_MASK (0x03) 3178 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_DIS_SEPARATE_REFCLK (0x00) 3179 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRIS (0x01) 3180 #define MPI3_PCIEIOUNIT1_LINKFLAGS_PCIE_CLK_MODE_EN_SRNS (0x02) 3181 3182 /**** Defines for the PhyFlags field ****/ 3183 #define MPI3_PCIEIOUNIT1_PHYFLAGS_PHY_DISABLE (0x08) 3184 3185 /**** Defines for the MaxMinLinkRate ****/ 3186 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_MASK (0xF0) 3187 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_SHIFT (4) 3188 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_2_5 (0x20) 3189 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_5_0 (0x30) 3190 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_8_0 (0x40) 3191 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_16_0 (0x50) 3192 #define MPI3_PCIEIOUNIT1_MMLR_MAX_RATE_32_0 (0x60) 3193 3194 #ifndef MPI3_PCIE_IO_UNIT1_PHY_MAX 3195 #define MPI3_PCIE_IO_UNIT1_PHY_MAX (1) 3196 #endif /* MPI3_PCIE_IO_UNIT1_PHY_MAX */ 3197 3198 typedef struct _MPI3_PCIE_IO_UNIT_PAGE1 3199 { 3200 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3201 U32 ControlFlags; /* 0x08 */ 3202 U32 Reserved0C; /* 0x0C */ 3203 U8 NumPhys; /* 0x10 */ 3204 U8 Reserved11; /* 0x11 */ 3205 U8 ASPM; /* 0x12 */ 3206 U8 Reserved13; /* 0x13 */ 3207 MPI3_PCIE_IO_UNIT1_PHY_DATA PhyData[MPI3_PCIE_IO_UNIT1_PHY_MAX]; /* 0x14 */ 3208 } MPI3_PCIE_IO_UNIT_PAGE1, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT_PAGE1, 3209 Mpi3PcieIOUnitPage1_t, MPI3_POINTER pMpi3PcieIOUnitPage1_t; 3210 3211 /**** Defines for the PageVersion field ****/ 3212 #define MPI3_PCIEIOUNIT1_PAGEVERSION (0x00) 3213 3214 /**** Defines for the ControlFlags field ****/ 3215 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_MASK (0xE0000000) 3216 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_NONE (0x00000000) 3217 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_DEASSERT (0x20000000) 3218 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_ASSERT (0x40000000) 3219 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PERST_OVERRIDE_BACKPLANE_ERROR (0x60000000) 3220 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_MASK (0x1C000000) 3221 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_NONE (0x00000000) 3222 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_DEASSERT (0x04000000) 3223 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_ASSERT (0x08000000) 3224 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_REFCLK_OVERRIDE_BACKPLANE_ERROR (0x0C000000) 3225 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_PARTIAL_CAPACITY_ENABLE (0x00000100) 3226 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_OVERRIDE_DISABLE (0x00000080) 3227 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_DISABLE (0x00000040) 3228 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_MASK (0x00000030) 3229 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SHIFT (4) 3230 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_SRNS_DISABLED (0x00000000) 3231 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRIS_ENABLED (0x00000010) 3232 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_CLOCK_OVERRIDE_MODE_SRNS_ENABLED (0x00000020) 3233 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MASK (0x0000000F) 3234 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_USE_BACKPLANE (0x00000000) 3235 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_2_5 (0x00000002) 3236 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_5_0 (0x00000003) 3237 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_8_0 (0x00000004) 3238 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_16_0 (0x00000005) 3239 #define MPI3_PCIEIOUNIT1_CONTROL_FLAGS_LINK_RATE_OVERRIDE_MAX_32_0 (0x00000006) 3240 3241 /**** Defines for the ASPM field ****/ 3242 #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_MASK (0x0C) 3243 #define MPI3_PCIEIOUNIT1_ASPM_SWITCH_SHIFT (2) 3244 #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_MASK (0x03) 3245 #define MPI3_PCIEIOUNIT1_ASPM_DIRECT_SHIFT (0) 3246 /*** use MPI3_PCIE_ASPM_ENABLE_ defines for ASPM field values ***/ 3247 3248 /***************************************************************************** 3249 * PCIe IO Unit Page 2 * 3250 ****************************************************************************/ 3251 typedef struct _MPI3_PCIE_IO_UNIT_PAGE2 3252 { 3253 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3254 U16 NVMeMaxQDx1; /* 0x08 */ 3255 U16 NVMeMaxQDx2; /* 0x0A */ 3256 U8 NVMeAbortTO; /* 0x0C */ 3257 U8 Reserved0D; /* 0x0D */ 3258 U16 NVMeMaxQDx4; /* 0x0E */ 3259 } MPI3_PCIE_IO_UNIT_PAGE2, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT_PAGE2, 3260 Mpi3PcieIOUnitPage2_t, MPI3_POINTER pMpi3PcieIOUnitPage2_t; 3261 3262 /**** Defines for the PageVersion field ****/ 3263 #define MPI3_PCIEIOUNIT2_PAGEVERSION (0x00) 3264 3265 /***************************************************************************** 3266 * PCIe IO Unit Page 3 * 3267 ****************************************************************************/ 3268 3269 /**** Defines for Error Indexes ****/ 3270 #define MPI3_PCIEIOUNIT3_ERROR_RECEIVER_ERROR (0) 3271 #define MPI3_PCIEIOUNIT3_ERROR_RECOVERY (1) 3272 #define MPI3_PCIEIOUNIT3_ERROR_CORRECTABLE_ERROR_MSG (2) 3273 #define MPI3_PCIEIOUNIT3_ERROR_BAD_DLLP (3) 3274 #define MPI3_PCIEIOUNIT3_ERROR_BAD_TLP (4) 3275 #define MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX (5) 3276 3277 3278 typedef struct _MPI3_PCIE_IO_UNIT3_ERROR 3279 { 3280 U16 ThresholdCount; /* 0x00 */ 3281 U16 Reserved02; /* 0x02 */ 3282 } MPI3_PCIE_IO_UNIT3_ERROR, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT3_ERROR, 3283 Mpi3PcieIOUnit3Error_t, MPI3_POINTER pMpi3PcieIOUnit3Error_t; 3284 3285 typedef struct _MPI3_PCIE_IO_UNIT_PAGE3 3286 { 3287 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3288 U8 ThresholdWindow; /* 0x08 */ 3289 U8 ThresholdAction; /* 0x09 */ 3290 U8 EscalationCount; /* 0x0A */ 3291 U8 EscalationAction; /* 0x0B */ 3292 U8 NumErrors; /* 0x0C */ 3293 U8 Reserved0D[3]; /* 0x0D */ 3294 MPI3_PCIE_IO_UNIT3_ERROR Error[MPI3_PCIEIOUNIT3_NUM_ERROR_INDEX]; /* 0x10 */ 3295 } MPI3_PCIE_IO_UNIT_PAGE3, MPI3_POINTER PTR_MPI3_PCIE_IO_UNIT_PAGE3, 3296 Mpi3PcieIOUnitPage3_t, MPI3_POINTER pMpi3PcieIOUnitPage3_t; 3297 3298 /**** Defines for the PageVersion field ****/ 3299 #define MPI3_PCIEIOUNIT3_PAGEVERSION (0x00) 3300 3301 /**** Defines for the ThresholdAction and EscalationAction fields ****/ 3302 #define MPI3_PCIEIOUNIT3_ACTION_NO_ACTION (0x00) 3303 #define MPI3_PCIEIOUNIT3_ACTION_HOT_RESET (0x01) 3304 #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_ONLY (0x02) 3305 #define MPI3_PCIEIOUNIT3_ACTION_REDUCE_LINK_RATE_NO_ACCESS (0x03) 3306 3307 /**** Defines for Error Indexes - use MPI3_PCIEIOUNIT3_ERROR_ defines ****/ 3308 3309 /***************************************************************************** 3310 * PCIe Switch Configuration Pages * 3311 ****************************************************************************/ 3312 3313 /***************************************************************************** 3314 * PCIe Switch Page 0 * 3315 ****************************************************************************/ 3316 typedef struct _MPI3_PCIE_SWITCH_PAGE0 3317 { 3318 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3319 U8 IOUnitPort; /* 0x08 */ 3320 U8 SwitchStatus; /* 0x09 */ 3321 U8 Reserved0A[2]; /* 0x0A */ 3322 U16 DevHandle; /* 0x0C */ 3323 U16 ParentDevHandle; /* 0x0E */ 3324 U8 NumPorts; /* 0x10 */ 3325 U8 PCIeLevel; /* 0x11 */ 3326 U16 Reserved12; /* 0x12 */ 3327 U32 Reserved14; /* 0x14 */ 3328 U32 Reserved18; /* 0x18 */ 3329 U32 Reserved1C; /* 0x1C */ 3330 } MPI3_PCIE_SWITCH_PAGE0, MPI3_POINTER PTR_MPI3_PCIE_SWITCH_PAGE0, 3331 Mpi3PcieSwitchPage0_t, MPI3_POINTER pMpi3PcieSwitchPage0_t; 3332 3333 /**** Defines for the PageVersion field ****/ 3334 #define MPI3_PCIESWITCH0_PAGEVERSION (0x00) 3335 3336 /**** Defines for the SwitchStatus field ****/ 3337 #define MPI3_PCIESWITCH0_SS_NOT_RESPONDING (0x02) 3338 #define MPI3_PCIESWITCH0_SS_RESPONDING (0x03) 3339 #define MPI3_PCIESWITCH0_SS_DELAY_NOT_RESPONDING (0x04) 3340 3341 /***************************************************************************** 3342 * PCIe Switch Page 1 * 3343 ****************************************************************************/ 3344 typedef struct _MPI3_PCIE_SWITCH_PAGE1 3345 { 3346 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3347 U8 IOUnitPort; /* 0x08 */ 3348 U8 Flags; /* 0x09 */ 3349 U16 Reserved0A; /* 0x0A */ 3350 U8 NumPorts; /* 0x0C */ 3351 U8 PortNum; /* 0x0D */ 3352 U16 AttachedDevHandle; /* 0x0E */ 3353 U16 SwitchDevHandle; /* 0x10 */ 3354 U8 NegotiatedPortWidth; /* 0x12 */ 3355 U8 NegotiatedLinkRate; /* 0x13 */ 3356 U16 Slot; /* 0x14 */ 3357 U16 SlotIndex; /* 0x16 */ 3358 U32 Reserved18; /* 0x18 */ 3359 } MPI3_PCIE_SWITCH_PAGE1, MPI3_POINTER PTR_MPI3_PCIE_SWITCH_PAGE1, 3360 Mpi3PcieSwitchPage1_t, MPI3_POINTER pMpi3PcieSwitchPage1_t; 3361 3362 /**** Defines for the PageVersion field ****/ 3363 #define MPI3_PCIESWITCH1_PAGEVERSION (0x00) 3364 3365 /**** Defines for the FLAGS field ****/ 3366 #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_MASK (0x0C) 3367 #define MPI3_PCIESWITCH1_FLAGS_ASPMSTATE_SHIFT (2) 3368 /*** use MPI3_PCIE_ASPM_ENABLE_ defines for ASPMState field values ***/ 3369 #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_MASK (0x03) 3370 #define MPI3_PCIESWITCH1_FLAGS_ASPMSUPPORT_SHIFT (0) 3371 /*** use MPI3_PCIE_ASPM_SUPPORT_ defines for ASPMSupport field values ***/ 3372 3373 /**** Defines for the NegotiatedLinkRate field - use MPI3_PCIE_NEG_LINK_RATE_ defines ****/ 3374 3375 /**** Defines for the Slot field - use MPI3_SLOT_ defines ****/ 3376 3377 /**** Defines for the SlotIndex field - use MPI3_SLOT_INDEX_ ****/ 3378 3379 /***************************************************************************** 3380 * PCIe Switch Page 2 * 3381 ****************************************************************************/ 3382 #ifndef MPI3_PCIESWITCH2_MAX_NUM_PORTS 3383 #define MPI3_PCIESWITCH2_MAX_NUM_PORTS (1) 3384 #endif /* MPI3_PCIESWITCH2_MAX_NUM_PORTS */ 3385 3386 typedef struct _MPI3_PCIESWITCH2_PORT_ELEMENT 3387 { 3388 U16 LinkChangeCount; /* 0x00 */ 3389 U16 RateChangeCount; /* 0x02 */ 3390 U32 Reserved04; /* 0x04 */ 3391 } MPI3_PCIESWITCH2_PORT_ELEMENT, MPI3_POINTER PTR_MPI3_PCIESWITCH2_PORT_ELEMENT, 3392 Mpi3PcieSwitch2PortElement_t, MPI3_POINTER pMpi3PcieSwitch2PortElement_t; 3393 3394 typedef struct _MPI3_PCIE_SWITCH_PAGE2 3395 { 3396 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3397 U8 NumPorts; /* 0x08 */ 3398 U8 Reserved09; /* 0x09 */ 3399 U16 DevHandle; /* 0x0A */ 3400 U32 Reserved0C; /* 0x0C */ 3401 MPI3_PCIESWITCH2_PORT_ELEMENT Port[MPI3_PCIESWITCH2_MAX_NUM_PORTS]; /* 0x10 */ /* variable length */ 3402 } MPI3_PCIE_SWITCH_PAGE2, MPI3_POINTER PTR_MPI3_PCIE_SWITCH_PAGE2, 3403 Mpi3PcieSwitchPage2_t, MPI3_POINTER pMpi3PcieSwitchPage2_t; 3404 3405 /**** Defines for the PageVersion field ****/ 3406 #define MPI3_PCIESWITCH2_PAGEVERSION (0x00) 3407 3408 /***************************************************************************** 3409 * PCIe Link Configuration Pages * 3410 ****************************************************************************/ 3411 3412 /***************************************************************************** 3413 * PCIe Link Page 0 * 3414 ****************************************************************************/ 3415 typedef struct _MPI3_PCIE_LINK_PAGE0 3416 { 3417 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3418 U8 Link; /* 0x08 */ 3419 U8 Reserved09[3]; /* 0x09 */ 3420 U32 Reserved0C; /* 0x0C */ 3421 U32 ReceiverErrorCount; /* 0x10 */ 3422 U32 RecoveryCount; /* 0x14 */ 3423 U32 CorrErrorMsgCount; /* 0x18 */ 3424 U32 NonFatalErrorMsgCount; /* 0x1C */ 3425 U32 FatalErrorMsgCount; /* 0x20 */ 3426 U32 NonFatalErrorCount; /* 0x24 */ 3427 U32 FatalErrorCount; /* 0x28 */ 3428 U32 BadDLLPCount; /* 0x2C */ 3429 U32 BadTLPCount; /* 0x30 */ 3430 } MPI3_PCIE_LINK_PAGE0, MPI3_POINTER PTR_MPI3_PCIE_LINK_PAGE0, 3431 Mpi3PcieLinkPage0_t, MPI3_POINTER pMpi3PcieLinkPage0_t; 3432 3433 /**** Defines for the PageVersion field ****/ 3434 #define MPI3_PCIELINK0_PAGEVERSION (0x00) 3435 3436 3437 /***************************************************************************** 3438 * Enclosure Configuration Pages * 3439 ****************************************************************************/ 3440 3441 /***************************************************************************** 3442 * Enclosure Page 0 * 3443 ****************************************************************************/ 3444 typedef struct _MPI3_ENCLOSURE_PAGE0 3445 { 3446 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3447 U64 EnclosureLogicalID; /* 0x08 */ 3448 U16 Flags; /* 0x10 */ 3449 U16 EnclosureHandle; /* 0x12 */ 3450 U16 NumSlots; /* 0x14 */ 3451 U16 Reserved16; /* 0x16 */ 3452 U8 IOUnitPort; /* 0x18 */ 3453 U8 EnclosureLevel; /* 0x19 */ 3454 U16 SEPDevHandle; /* 0x1A */ 3455 U8 ChassisSlot; /* 0x1C */ 3456 U8 Reserved1D[3]; /* 0x1D */ 3457 } MPI3_ENCLOSURE_PAGE0, MPI3_POINTER PTR_MPI3_ENCLOSURE_PAGE0, 3458 Mpi3EnclosurePage0_t, MPI3_POINTER pMpi3EnclosurePage0_t; 3459 3460 /**** Defines for the PageVersion field ****/ 3461 #define MPI3_ENCLOSURE0_PAGEVERSION (0x00) 3462 3463 /**** Defines for the Flags field ****/ 3464 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_MASK (0xC000) 3465 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_VIRTUAL (0x0000) 3466 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_SAS (0x4000) 3467 #define MPI3_ENCLS0_FLAGS_ENCL_TYPE_PCIE (0x8000) 3468 #define MPI3_ENCLS0_FLAGS_CHASSIS_SLOT_VALID (0x0020) 3469 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT_MASK (0x0010) 3470 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_NOT_FOUND (0x0000) 3471 #define MPI3_ENCLS0_FLAGS_ENCL_DEV_PRESENT (0x0010) 3472 #define MPI3_ENCLS0_FLAGS_MNG_MASK (0x000F) 3473 #define MPI3_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000) 3474 #define MPI3_ENCLS0_FLAGS_MNG_IOC_SES (0x0001) 3475 #define MPI3_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0002) 3476 3477 /**** Defines for the PhysicalPort field - use MPI3_DEVICE0_PHYPORT_ defines ****/ 3478 3479 /***************************************************************************** 3480 * Device Configuration Pages * 3481 ****************************************************************************/ 3482 3483 /***************************************************************************** 3484 * Common definitions used by Device Configuration Pages * 3485 ****************************************************************************/ 3486 3487 /**** Defines for the DeviceForm field ****/ 3488 #define MPI3_DEVICE_DEVFORM_SAS_SATA (0x00) 3489 #define MPI3_DEVICE_DEVFORM_PCIE (0x01) 3490 #define MPI3_DEVICE_DEVFORM_VD (0x02) 3491 3492 /***************************************************************************** 3493 * Device Page 0 * 3494 ****************************************************************************/ 3495 typedef struct _MPI3_DEVICE0_SAS_SATA_FORMAT 3496 { 3497 U64 SASAddress; /* 0x00 */ 3498 U16 Flags; /* 0x08 */ 3499 U16 DeviceInfo; /* 0x0A */ 3500 U8 PhyNum; /* 0x0C */ 3501 U8 AttachedPhyIdentifier; /* 0x0D */ 3502 U8 MaxPortConnections; /* 0x0E */ 3503 U8 ZoneGroup; /* 0x0F */ 3504 } MPI3_DEVICE0_SAS_SATA_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE0_SAS_SATA_FORMAT, 3505 Mpi3Device0SasSataFormat_t, MPI3_POINTER pMpi3Device0SasSataFormat_t; 3506 3507 /**** Defines for the Flags field ****/ 3508 #define MPI3_DEVICE0_SASSATA_FLAGS_WRITE_SAME_UNMAP_NCQ (0x0400) 3509 #define MPI3_DEVICE0_SASSATA_FLAGS_SLUMBER_CAP (0x0200) 3510 #define MPI3_DEVICE0_SASSATA_FLAGS_PARTIAL_CAP (0x0100) 3511 #define MPI3_DEVICE0_SASSATA_FLAGS_ASYNC_NOTIFY (0x0080) 3512 #define MPI3_DEVICE0_SASSATA_FLAGS_SW_PRESERVE (0x0040) 3513 #define MPI3_DEVICE0_SASSATA_FLAGS_UNSUPP_DEV (0x0020) 3514 #define MPI3_DEVICE0_SASSATA_FLAGS_48BIT_LBA (0x0010) 3515 #define MPI3_DEVICE0_SASSATA_FLAGS_SMART_SUPP (0x0008) 3516 #define MPI3_DEVICE0_SASSATA_FLAGS_NCQ_SUPP (0x0004) 3517 #define MPI3_DEVICE0_SASSATA_FLAGS_FUA_SUPP (0x0002) 3518 #define MPI3_DEVICE0_SASSATA_FLAGS_PERSIST_CAP (0x0001) 3519 3520 /**** Defines for the DeviceInfo field - use MPI3_SAS_DEVICE_INFO_ defines (see mpi30_sas.h) ****/ 3521 3522 typedef struct _MPI3_DEVICE0_PCIE_FORMAT 3523 { 3524 U8 SupportedLinkRates; /* 0x00 */ 3525 U8 MaxPortWidth; /* 0x01 */ 3526 U8 NegotiatedPortWidth; /* 0x02 */ 3527 U8 NegotiatedLinkRate; /* 0x03 */ 3528 U8 PortNum; /* 0x04 */ 3529 U8 ControllerResetTO; /* 0x05 */ 3530 U16 DeviceInfo; /* 0x06 */ 3531 U32 MaximumDataTransferSize; /* 0x08 */ 3532 U32 Capabilities; /* 0x0C */ 3533 U16 NOIOB; /* 0x10 */ 3534 U8 NVMeAbortTO; /* 0x12 */ 3535 U8 PageSize; /* 0x13 */ 3536 U16 ShutdownLatency; /* 0x14 */ 3537 U8 RecoveryInfo; /* 0x16 */ 3538 U8 Reserved17; /* 0x17 */ 3539 } MPI3_DEVICE0_PCIE_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE0_PCIE_FORMAT, 3540 Mpi3Device0PcieFormat_t, MPI3_POINTER pMpi3Device0PcieFormat_t; 3541 3542 /**** Defines for the SupportedLinkRates field ****/ 3543 #define MPI3_DEVICE0_PCIE_LINK_RATE_32_0_SUPP (0x10) 3544 #define MPI3_DEVICE0_PCIE_LINK_RATE_16_0_SUPP (0x08) 3545 #define MPI3_DEVICE0_PCIE_LINK_RATE_8_0_SUPP (0x04) 3546 #define MPI3_DEVICE0_PCIE_LINK_RATE_5_0_SUPP (0x02) 3547 #define MPI3_DEVICE0_PCIE_LINK_RATE_2_5_SUPP (0x01) 3548 3549 /**** Defines for the NegotiatedLinkRate field - use MPI3_PCIE_NEG_LINK_RATE_ defines ****/ 3550 3551 /**** Defines for DeviceInfo bitfield ****/ 3552 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_MASK (0x0007) 3553 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NO_DEVICE (0x0000) 3554 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_NVME_DEVICE (0x0001) 3555 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SWITCH_DEVICE (0x0002) 3556 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_TYPE_SCSI_DEVICE (0x0003) 3557 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_MASK (0x0030) 3558 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_ASPM_SHIFT (4) 3559 /*** use MPI3_PCIE_ASPM_ENABLE_ defines for ASPM field values ***/ 3560 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_MASK (0x00C0) 3561 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_SHIFT (6) 3562 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_0 (0x0000) 3563 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_1 (0x0040) 3564 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_2 (0x0080) 3565 #define MPI3_DEVICE0_PCIE_DEVICE_INFO_PITYPE_3 (0x00C0) 3566 3567 3568 /**** Defines for the Capabilities field ****/ 3569 #define MPI3_DEVICE0_PCIE_CAP_SGL_EXTRA_LENGTH_SUPPORTED (0x00000020) 3570 #define MPI3_DEVICE0_PCIE_CAP_METADATA_SEPARATED (0x00000010) 3571 #define MPI3_DEVICE0_PCIE_CAP_SGL_DWORD_ALIGN_REQUIRED (0x00000008) 3572 #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_SGL (0x00000004) 3573 #define MPI3_DEVICE0_PCIE_CAP_SGL_FORMAT_PRP (0x00000000) 3574 #define MPI3_DEVICE0_PCIE_CAP_BIT_BUCKET_SGL_SUPP (0x00000002) 3575 #define MPI3_DEVICE0_PCIE_CAP_SGL_SUPP (0x00000001) 3576 #define MPI3_DEVICE0_PCIE_CAP_ASPM_MASK (0x000000C0) 3577 #define MPI3_DEVICE0_PCIE_CAP_ASPM_SHIFT (6) 3578 /*** use MPI3_PCIE_ASPM_SUPPORT_ defines for ASPM field values ***/ 3579 3580 /**** Defines for the RecoverMethod field ****/ 3581 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_MASK (0xE0) 3582 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_NS_MGMT (0x00) 3583 #define MPI3_DEVICE0_PCIE_RECOVER_METHOD_FORMAT (0x20) 3584 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_MASK (0x1F) 3585 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NS (0x00) 3586 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_NO_NSID_1 (0x01) 3587 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_TOO_MANY_NS (0x02) 3588 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_PROTECTION (0x03) 3589 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_METADATA_SZ (0x04) 3590 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_LBA_DATA_SZ (0x05) 3591 #define MPI3_DEVICE0_PCIE_RECOVER_REASON_PARTIAL_CAP (0x06) 3592 3593 typedef struct _MPI3_DEVICE0_VD_FORMAT 3594 { 3595 U8 VdState; /* 0x00 */ 3596 U8 RAIDLevel; /* 0x01 */ 3597 U16 DeviceInfo; /* 0x02 */ 3598 U16 Flags; /* 0x04 */ 3599 U16 IOThrottleGroup; /* 0x06 */ 3600 U16 IOThrottleGroupLow; /* 0x08 */ 3601 U16 IOThrottleGroupHigh; /* 0x0A */ 3602 U32 Reserved0C; /* 0x0C */ 3603 } MPI3_DEVICE0_VD_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE0_VD_FORMAT, 3604 Mpi3Device0VdFormat_t, MPI3_POINTER pMpi3Device0VdFormat_t; 3605 3606 /**** Defines for the VdState field ****/ 3607 #define MPI3_DEVICE0_VD_STATE_OFFLINE (0x00) 3608 #define MPI3_DEVICE0_VD_STATE_PARTIALLY_DEGRADED (0x01) 3609 #define MPI3_DEVICE0_VD_STATE_DEGRADED (0x02) 3610 #define MPI3_DEVICE0_VD_STATE_OPTIMAL (0x03) 3611 3612 /**** Defines for RAIDLevel field ****/ 3613 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_0 (0) 3614 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_1 (1) 3615 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_5 (5) 3616 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_6 (6) 3617 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_10 (10) 3618 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_50 (50) 3619 #define MPI3_DEVICE0_VD_RAIDLEVEL_RAID_60 (60) 3620 3621 /**** Defines for DeviceInfo field ****/ 3622 #define MPI3_DEVICE0_VD_DEVICE_INFO_HDD (0x0010) 3623 #define MPI3_DEVICE0_VD_DEVICE_INFO_SSD (0x0008) 3624 #define MPI3_DEVICE0_VD_DEVICE_INFO_NVME (0x0004) 3625 #define MPI3_DEVICE0_VD_DEVICE_INFO_SATA (0x0002) 3626 #define MPI3_DEVICE0_VD_DEVICE_INFO_SAS (0x0001) 3627 3628 /**** Defines for the Flags field ****/ 3629 #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_MASK (0xF000) 3630 #define MPI3_DEVICE0_VD_FLAGS_IO_THROTTLE_GROUP_QD_SHIFT (12) 3631 3632 typedef union _MPI3_DEVICE0_DEV_SPEC_FORMAT 3633 { 3634 MPI3_DEVICE0_SAS_SATA_FORMAT SasSataFormat; 3635 MPI3_DEVICE0_PCIE_FORMAT PcieFormat; 3636 MPI3_DEVICE0_VD_FORMAT VdFormat; 3637 } MPI3_DEVICE0_DEV_SPEC_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE0_DEV_SPEC_FORMAT, 3638 Mpi3Device0DevSpecFormat_t, MPI3_POINTER pMpi3Device0DevSpecFormat_t; 3639 3640 typedef struct _MPI3_DEVICE_PAGE0 3641 { 3642 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3643 U16 DevHandle; /* 0x08 */ 3644 U16 ParentDevHandle; /* 0x0A */ 3645 U16 Slot; /* 0x0C */ 3646 U16 EnclosureHandle; /* 0x0E */ 3647 U64 WWID; /* 0x10 */ 3648 U16 PersistentID; /* 0x18 */ 3649 U8 IOUnitPort; /* 0x1A */ 3650 U8 AccessStatus; /* 0x1B */ 3651 U16 Flags; /* 0x1C */ 3652 U16 Reserved1E; /* 0x1E */ 3653 U16 SlotIndex; /* 0x20 */ 3654 U16 QueueDepth; /* 0x22 */ 3655 U8 Reserved24[3]; /* 0x24 */ 3656 U8 DeviceForm; /* 0x27 */ 3657 MPI3_DEVICE0_DEV_SPEC_FORMAT DeviceSpecific; /* 0x28 */ 3658 } MPI3_DEVICE_PAGE0, MPI3_POINTER PTR_MPI3_DEVICE_PAGE0, 3659 Mpi3DevicePage0_t, MPI3_POINTER pMpi3DevicePage0_t; 3660 3661 /**** Defines for the PageVersion field ****/ 3662 #define MPI3_DEVICE0_PAGEVERSION (0x00) 3663 3664 /**** Defines for the ParentDevHandle field ****/ 3665 #define MPI3_DEVICE0_PARENT_INVALID (0xFFFF) 3666 3667 /**** Defines for the Slot field - use MPI3_SLOT_ defines ****/ 3668 3669 /**** Defines for the EnclosureHandle field ****/ 3670 #define MPI3_DEVICE0_ENCLOSURE_HANDLE_NO_ENCLOSURE (0x0000) 3671 3672 /**** Defines for the WWID field ****/ 3673 #define MPI3_DEVICE0_WWID_INVALID (0xFFFFFFFFFFFFFFFF) 3674 3675 /**** Defines for the PersistentID field ****/ 3676 #define MPI3_DEVICE0_PERSISTENTID_INVALID (0xFFFF) 3677 3678 /**** Defines for the IOUnitPort field ****/ 3679 #define MPI3_DEVICE0_IOUNITPORT_INVALID (0xFF) 3680 3681 /**** Defines for the AccessStatus field ****/ 3682 /* Generic Access Status Codes */ 3683 #define MPI3_DEVICE0_ASTATUS_NO_ERRORS (0x00) 3684 #define MPI3_DEVICE0_ASTATUS_NEEDS_INITIALIZATION (0x01) 3685 #define MPI3_DEVICE0_ASTATUS_CAP_UNSUPPORTED (0x02) 3686 #define MPI3_DEVICE0_ASTATUS_DEVICE_BLOCKED (0x03) 3687 #define MPI3_DEVICE0_ASTATUS_UNAUTHORIZED (0x04) 3688 #define MPI3_DEVICE0_ASTATUS_DEVICE_MISSING_DELAY (0x05) 3689 #define MPI3_DEVICE0_ASTATUS_PREPARE (0x06) 3690 #define MPI3_DEVICE0_ASTATUS_SAFE_MODE (0x07) 3691 #define MPI3_DEVICE0_ASTATUS_GENERIC_MAX (0x0F) 3692 /* SAS Access Status Codes */ 3693 #define MPI3_DEVICE0_ASTATUS_SAS_UNKNOWN (0x10) 3694 #define MPI3_DEVICE0_ASTATUS_ROUTE_NOT_ADDRESSABLE (0x11) 3695 #define MPI3_DEVICE0_ASTATUS_SMP_ERROR_NOT_ADDRESSABLE (0x12) 3696 #define MPI3_DEVICE0_ASTATUS_SAS_MAX (0x1F) 3697 /* SATA Access Status Codes */ 3698 #define MPI3_DEVICE0_ASTATUS_SIF_UNKNOWN (0x20) 3699 #define MPI3_DEVICE0_ASTATUS_SIF_AFFILIATION_CONFLICT (0x21) 3700 #define MPI3_DEVICE0_ASTATUS_SIF_DIAG (0x22) 3701 #define MPI3_DEVICE0_ASTATUS_SIF_IDENTIFICATION (0x23) 3702 #define MPI3_DEVICE0_ASTATUS_SIF_CHECK_POWER (0x24) 3703 #define MPI3_DEVICE0_ASTATUS_SIF_PIO_SN (0x25) 3704 #define MPI3_DEVICE0_ASTATUS_SIF_MDMA_SN (0x26) 3705 #define MPI3_DEVICE0_ASTATUS_SIF_UDMA_SN (0x27) 3706 #define MPI3_DEVICE0_ASTATUS_SIF_ZONING_VIOLATION (0x28) 3707 #define MPI3_DEVICE0_ASTATUS_SIF_NOT_ADDRESSABLE (0x29) 3708 #define MPI3_DEVICE0_ASTATUS_SIF_MAX (0x2F) 3709 /* PCIe Access Status Codes */ 3710 #define MPI3_DEVICE0_ASTATUS_PCIE_UNKNOWN (0x30) 3711 #define MPI3_DEVICE0_ASTATUS_PCIE_MEM_SPACE_ACCESS (0x31) 3712 #define MPI3_DEVICE0_ASTATUS_PCIE_UNSUPPORTED (0x32) 3713 #define MPI3_DEVICE0_ASTATUS_PCIE_MSIX_REQUIRED (0x33) 3714 #define MPI3_DEVICE0_ASTATUS_PCIE_ECRC_REQUIRED (0x34) 3715 #define MPI3_DEVICE0_ASTATUS_PCIE_MAX (0x3F) 3716 /* NVMe Access Status Codes */ 3717 #define MPI3_DEVICE0_ASTATUS_NVME_UNKNOWN (0x40) 3718 #define MPI3_DEVICE0_ASTATUS_NVME_READY_TIMEOUT (0x41) 3719 #define MPI3_DEVICE0_ASTATUS_NVME_DEVCFG_UNSUPPORTED (0x42) 3720 #define MPI3_DEVICE0_ASTATUS_NVME_IDENTIFY_FAILED (0x43) 3721 #define MPI3_DEVICE0_ASTATUS_NVME_QCONFIG_FAILED (0x44) 3722 #define MPI3_DEVICE0_ASTATUS_NVME_QCREATION_FAILED (0x45) 3723 #define MPI3_DEVICE0_ASTATUS_NVME_EVENTCFG_FAILED (0x46) 3724 #define MPI3_DEVICE0_ASTATUS_NVME_GET_FEATURE_STAT_FAILED (0x47) 3725 #define MPI3_DEVICE0_ASTATUS_NVME_IDLE_TIMEOUT (0x48) 3726 #define MPI3_DEVICE0_ASTATUS_NVME_CTRL_FAILURE_STATUS (0x49) 3727 #define MPI3_DEVICE0_ASTATUS_NVME_INSUFFICIENT_POWER (0x4A) 3728 #define MPI3_DEVICE0_ASTATUS_NVME_DOORBELL_STRIDE (0x4B) 3729 #define MPI3_DEVICE0_ASTATUS_NVME_MEM_PAGE_MIN_SIZE (0x4C) 3730 #define MPI3_DEVICE0_ASTATUS_NVME_MEMORY_ALLOCATION (0x4D) 3731 #define MPI3_DEVICE0_ASTATUS_NVME_COMPLETION_TIME (0x4E) 3732 #define MPI3_DEVICE0_ASTATUS_NVME_BAR (0x4F) 3733 #define MPI3_DEVICE0_ASTATUS_NVME_NS_DESCRIPTOR (0x50) 3734 #define MPI3_DEVICE0_ASTATUS_NVME_INCOMPATIBLE_SETTINGS (0x51) 3735 #define MPI3_DEVICE0_ASTATUS_NVME_TOO_MANY_ERRORS (0x52) 3736 #define MPI3_DEVICE0_ASTATUS_NVME_MAX (0x5F) 3737 /* Virtual Device Access Status Codes */ 3738 #define MPI3_DEVICE0_ASTATUS_VD_UNKNOWN (0x80) 3739 #define MPI3_DEVICE0_ASTATUS_VD_MAX (0x8F) 3740 3741 /**** Defines for the Flags field ****/ 3742 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_MASK (0xE000) 3743 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_NO_LIMIT (0x0000) 3744 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_256_LB (0x2000) 3745 #define MPI3_DEVICE0_FLAGS_MAX_WRITE_SAME_2048_LB (0x4000) 3746 #define MPI3_DEVICE0_FLAGS_CONTROLLER_DEV_HANDLE (0x0080) 3747 #define MPI3_DEVICE0_FLAGS_IO_THROTTLING_REQUIRED (0x0010) 3748 #define MPI3_DEVICE0_FLAGS_HIDDEN (0x0008) 3749 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_VIRTUAL (0x0004) 3750 #define MPI3_DEVICE0_FLAGS_ATT_METHOD_DIR_ATTACHED (0x0002) 3751 #define MPI3_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001) 3752 3753 /**** Defines for the SlotIndex field - use MPI3_SLOT_INDEX_ defines ****/ 3754 3755 /**** Defines for the DeviceForm field - use MPI3_DEVICE_DEVFORM_ defines ****/ 3756 3757 /**** Defines for the QueueDepth field ****/ 3758 #define MPI3_DEVICE0_QUEUE_DEPTH_NOT_APPLICABLE (0x0000) 3759 3760 3761 /***************************************************************************** 3762 * Device Page 1 * 3763 ****************************************************************************/ 3764 typedef struct _MPI3_DEVICE1_SAS_SATA_FORMAT 3765 { 3766 U32 Reserved00; /* 0x00 */ 3767 } MPI3_DEVICE1_SAS_SATA_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE1_SAS_SATA_FORMAT, 3768 Mpi3Device1SasSataFormat_t, MPI3_POINTER pMpi3Device1SasSataFormat_t; 3769 3770 typedef struct _MPI3_DEVICE1_PCIE_FORMAT 3771 { 3772 U16 VendorID; /* 0x00 */ 3773 U16 DeviceID; /* 0x02 */ 3774 U16 SubsystemVendorID; /* 0x04 */ 3775 U16 SubsystemID; /* 0x06 */ 3776 U32 Reserved08; /* 0x08 */ 3777 U8 RevisionID; /* 0x0C */ 3778 U8 Reserved0D; /* 0x0D */ 3779 U16 PCIParameters; /* 0x0E */ 3780 } MPI3_DEVICE1_PCIE_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE1_PCIE_FORMAT, 3781 Mpi3Device1PcieFormat_t, MPI3_POINTER pMpi3Device1PcieFormat_t; 3782 3783 /**** Defines for the PCIParameters field ****/ 3784 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_128B (0x0) 3785 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_256B (0x1) 3786 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_512B (0x2) 3787 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_1024B (0x3) 3788 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_2048B (0x4) 3789 #define MPI3_DEVICE1_PCIE_PARAMS_DATA_SIZE_4096B (0x5) 3790 3791 /*** MaxReadRequestSize, CurrentMaxPayloadSize, and MaxPayloadSizeSupported ***/ 3792 /*** all use the size definitions above - shifted to the proper position ***/ 3793 #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_MASK (0x01C0) 3794 #define MPI3_DEVICE1_PCIE_PARAMS_MAX_READ_REQ_SHIFT (6) 3795 #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_MASK (0x0038) 3796 #define MPI3_DEVICE1_PCIE_PARAMS_CURR_MAX_PAYLOAD_SHIFT (3) 3797 #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_MASK (0x0007) 3798 #define MPI3_DEVICE1_PCIE_PARAMS_SUPP_MAX_PAYLOAD_SHIFT (0) 3799 3800 typedef struct _MPI3_DEVICE1_VD_FORMAT 3801 { 3802 U32 Reserved00; /* 0x00 */ 3803 } MPI3_DEVICE1_VD_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE1_VD_FORMAT, 3804 Mpi3Device1VdFormat_t, MPI3_POINTER pMpi3Device1VdFormat_t; 3805 3806 typedef union _MPI3_DEVICE1_DEV_SPEC_FORMAT 3807 { 3808 MPI3_DEVICE1_SAS_SATA_FORMAT SasSataFormat; 3809 MPI3_DEVICE1_PCIE_FORMAT PcieFormat; 3810 MPI3_DEVICE1_VD_FORMAT VdFormat; 3811 } MPI3_DEVICE1_DEV_SPEC_FORMAT, MPI3_POINTER PTR_MPI3_DEVICE1_DEV_SPEC_FORMAT, 3812 Mpi3Device1DevSpecFormat_t, MPI3_POINTER pMpi3Device1DevSpecFormat_t; 3813 3814 typedef struct _MPI3_DEVICE_PAGE1 3815 { 3816 MPI3_CONFIG_PAGE_HEADER Header; /* 0x00 */ 3817 U16 DevHandle; /* 0x08 */ 3818 U16 Reserved0A; /* 0x0A */ 3819 U16 LinkChangeCount; /* 0x0C */ 3820 U16 RateChangeCount; /* 0x0E */ 3821 U16 TMCount; /* 0x10 */ 3822 U16 Reserved12; /* 0x12 */ 3823 U32 Reserved14[10]; /* 0x14 */ 3824 U8 Reserved3C[3]; /* 0x3C */ 3825 U8 DeviceForm; /* 0x3F */ 3826 MPI3_DEVICE1_DEV_SPEC_FORMAT DeviceSpecific; /* 0x40 */ 3827 } MPI3_DEVICE_PAGE1, MPI3_POINTER PTR_MPI3_DEVICE_PAGE1, 3828 Mpi3DevicePage1_t, MPI3_POINTER pMpi3DevicePage1_t; 3829 3830 /**** Defines for the PageVersion field ****/ 3831 #define MPI3_DEVICE1_PAGEVERSION (0x00) 3832 3833 /**** Defines for the LinkChangeCount, RateChangeCount, TMCount fields ****/ 3834 #define MPI3_DEVICE1_COUNTER_MAX (0xFFFE) 3835 #define MPI3_DEVICE1_COUNTER_INVALID (0xFFFF) 3836 3837 /**** Defines for the DeviceForm field - use MPI3_DEVICE_DEVFORM_ defines ****/ 3838 3839 #endif /* MPI30_CNFG_H */ 3840